diff --git a/.github/workflows/docs.yml b/.github/workflows/docs.yml index d58c7d51e0e44..17b2fbbae7bd5 100644 --- a/.github/workflows/docs.yml +++ b/.github/workflows/docs.yml @@ -15,17 +15,68 @@ on: paths: - 'llvm/docs/**' - 'clang/docs/**' + - 'clang-tools-extra/docs/**' + - 'lldb/docs/**' + - 'libunwind/docs/**' + - 'libcxx/docs/**' + - 'libc/docs/**' + - 'lld/docs/**' + - 'openmp/docs/**' + - 'polly/docs/**' pull_request: paths: - 'llvm/docs/**' - 'clang/docs/**' + - 'clang-tools-extra/docs/**' + - 'lldb/docs/**' + - 'libunwind/docs/**' + - 'libcxx/docs/**' + - 'libc/docs/**' + - 'lld/docs/**' + - 'openmp/docs/**' + - 'polly/docs/**' jobs: check-docs-build: name: "Test documentation build" runs-on: ubuntu-latest steps: - - name: Fetch LLVM sources + # Don't fetch before checking for file changes to force the file changes + # action to use the Github API in pull requests. If it's a push to a + # branch we can't use the Github API to get the diff, so we need to have + # a local checkout beforehand. + - name: Fetch LLVM sources (Push) + if: ${{ github.event_name == 'push' }} + uses: actions/checkout@v4 + with: + fetch-depth: 1 + - name: Get subprojects that have doc changes + id: docs-changed-subprojects + uses: tj-actions/changed-files@v39 + with: + files_yaml: | + llvm: + - 'llvm/docs/**' + clang: + - 'clang/docs/**' + clang-tools-extra: + - 'clang-tools-extra/docs/**' + lldb: + - 'lldb/docs/**' + libunwind: + - 'libunwind/docs/**' + libcxx: + - 'libcxx/docs/**' + libc: + - 'libc/docs/**' + lld: + - 'lld/docs/**' + openmp: + - 'openmp/docs/**' + polly: + - 'polly/docs/**' + - name: Fetch LLVM sources (PR) + if: ${{ github.event_name == 'pull_request' }} uses: actions/checkout@v4 with: fetch-depth: 1 @@ -40,24 +91,56 @@ jobs: - name: Install system dependencies run: | sudo apt-get update - sudo apt-get install -y cmake ninja-build - - name: Get subprojects that have doc changes - id: docs-changed-subprojects - uses: tj-actions/changed-files@v39 - with: - files_yaml: | - llvm: - - 'llvm/docs/**' - clang: - - 'clang/docs/**' + # swig and graphviz are lldb specific dependencies + sudo apt-get install -y cmake ninja-build swig graphviz - name: Build LLVM docs if: steps.docs-changed-subprojects.outputs.llvm_any_changed == 'true' run: | - cmake -B llvm-build -GNinja -DCMAKE_BUILD_TYPE=Release -DLLVM_ENABLE_SPHINX=ON -DSPHINX_OUTPUT_HTML=ON -DSPHINX_OUTPUT_MAN=ON ./llvm + cmake -B llvm-build -GNinja -DCMAKE_BUILD_TYPE=Release -DLLVM_ENABLE_SPHINX=ON ./llvm TZ=UTC ninja -C llvm-build docs-llvm-html docs-llvm-man - name: Build Clang docs if: steps.docs-changed-subprojects.outputs.clang_any_changed == 'true' run: | - cmake -B clang-build -GNinja -DCMAKE_BUILD_TYPE=Release -DLLVM_ENABLE_PROJECTS="clang" -DLLVM_ENABLE_SPHINX=ON -DSPHINX_OUTPUT_HTML=ON -DSPHINX_OUTPUT_MAN=ON ./llvm + cmake -B clang-build -GNinja -DCMAKE_BUILD_TYPE=Release -DLLVM_ENABLE_PROJECTS="clang" -DLLVM_ENABLE_SPHINX=ON ./llvm TZ=UTC ninja -C clang-build docs-clang-html docs-clang-man + - name: Build clang-tools-extra docs + if: steps.docs-changed-subprojects.outputs.clang-tools-extra_any_changed == 'true' + run: | + cmake -B clang-tools-extra-build -GNinja -DCMAKE_BUILD_TYPE=Release -DLLVM_ENABLE_PROJECTS="clang;clang-tools-extra" -DLLVM_ENABLE_SPHINX=ON ./llvm + TZ=UTC ninja -C clang-tools-extra-build docs-clang-tools-html docs-clang-tools-man + - name: Build LLDB docs + if: steps.docs-changed-subprojects.outputs.lldb_any_changed == 'true' + run: | + cmake -B lldb-build -GNinja -DCMAKE_BUILD_TYPE=Release -DLLVM_ENABLE_PROJECTS="clang;lldb" -DLLVM_ENABLE_SPHINX=ON ./llvm + TZ=UTC ninja -C lldb-build docs-lldb-html docs-lldb-man + - name: Build libunwind docs + if: steps.docs-changed-subprojects.outputs.libunwind_any_changed == 'true' + run: | + cmake -B libunwind-build -GNinja -DCMAKE_BUILD_TYPE=Release -DLLVM_ENABLE_RUNTIMES="libunwind" -DLLVM_ENABLE_SPHINX=ON ./runtimes + TZ=UTC ninja -C libunwind-build docs-libunwind-html + - name: Build libcxx docs + if: steps.docs-changed-subprojects.outputs.libcxx_any_changed == 'true' + run: | + cmake -B libcxx-build -GNinja -DCMAKE_BUILD_TYPE=Release -DLLVM_ENABLE_RUNTIMES="libcxxabi;libcxx" -DLLVM_ENABLE_SPHINX=ON ./runtimes + TZ=UTC ninja -C libcxx-build docs-libcxx-html + - name: Build libc docs + if: steps.docs-changed-subprojects.outputs.libc_any_changed == 'true' + run: | + cmake -B libc-build -GNinja -DCMAKE_BUILD_TYPE=Release -DLLVM_ENABLE_RUNTIMES="libc" -DLLVM_ENABLE_SPHINX=ON ./runtimes + TZ=UTC ninja -C libc-build docs-libc-html + - name: Build LLD docs + if: steps.docs-changed-subprojects.outputs.lld_any_changed == 'true' + run: | + cmake -B lld-build -GNinja -DCMAKE_BUILD_TYPE=Release -DLLVM_ENABLE_PROJECTS="lld" -DLLVM_ENABLE_SPHINX=ON ./llvm + TZ=UTC ninja -C lld-build docs-lld-html + - name: Build OpenMP docs + if: steps.docs-changed-subprojects.outputs.openmp_any_changed == 'true' + run: | + cmake -B openmp-build -GNinja -DCMAKE_BUILD_TYPE=Release -DLLVM_ENABLE_PROJECTS="clang;openmp" -DLLVM_ENABLE_SPHINX=ON ./llvm + TZ=UTC ninja -C openmp-build docs-openmp-html + - name: Build Polly docs + if: steps.docs-changed-subprojects.outputs.polly_any_changed == 'true' + run: | + cmake -B polly-build -GNinja -DCMAKE_BUILD_TYPE=Release -DLLVM_ENABLE_PROJECTS="polly" -DLLVM_ENABLE_SPHINX=ON ./llvm + TZ=UTC ninja -C polly-build docs-polly-html docs-polly-man diff --git a/.github/workflows/libcxx-check-generated-files.yml b/.github/workflows/libcxx-check-generated-files.yml index 6f2d01ee0a56f..570055624b2a8 100644 --- a/.github/workflows/libcxx-check-generated-files.yml +++ b/.github/workflows/libcxx-check-generated-files.yml @@ -4,6 +4,9 @@ on: paths: - 'libcxx/**' +permissions: + contents: read + jobs: check_generated_files: runs-on: ubuntu-latest diff --git a/README.md b/README.md index eb8d624d75cec..692f2bb3916f5 100644 --- a/README.md +++ b/README.md @@ -32,8 +32,9 @@ the [Contributing to LLVM](https://llvm.org/docs/Contributing.html) guide. ## Getting in touch Join the [LLVM Discourse forums](https://discourse.llvm.org/), [Discord -chat](https://discord.gg/xS7Z362), or #llvm IRC channel on -[OFTC](https://oftc.net/). +chat](https://discord.gg/xS7Z362), +[LLVM Office Hours](https://llvm.org/docs/GettingInvolved.html#office-hours) or +[Regular sync-ups](https://llvm.org/docs/GettingInvolved.html#online-sync-ups). The LLVM project has adopted a [code of conduct](https://llvm.org/docs/CodeOfConduct.html) for participants to all modes of communication within the project. diff --git a/bolt/include/bolt/Core/AddressMap.h b/bolt/include/bolt/Core/AddressMap.h index 16c2727b6943f..85a9ab4473aaf 100644 --- a/bolt/include/bolt/Core/AddressMap.h +++ b/bolt/include/bolt/Core/AddressMap.h @@ -6,18 +6,16 @@ // //===----------------------------------------------------------------------===// // -// Helper class to create a mapping from input to output addresses needed for -// updating debugging symbols and BAT. We emit an MCSection containing -// pairs to the object file and JITLink will -// transform this in pairs. The linker output -// can then be parsed and used to establish the mapping. +// This file contains the declaration of the AddressMap class used for looking +// up addresses in the output object. // //===----------------------------------------------------------------------===// -// + #ifndef BOLT_CORE_ADDRESS_MAP_H #define BOLT_CORE_ADDRESS_MAP_H #include "llvm/ADT/StringRef.h" +#include "llvm/MC/MCSymbol.h" #include #include @@ -30,26 +28,48 @@ namespace bolt { class BinaryContext; +/// Helper class to create a mapping from input entities to output addresses +/// needed for updating debugging symbols and BAT. We emit a section containing +/// pairs to the object file and JITLink will +/// transform this in pairs. The linker output +/// can then be parsed and used to establish the mapping. +/// +/// The entities that can be mapped to output address are input addresses and +/// labels (MCSymbol). Input addresses support one-to-many mapping. class AddressMap { - using MapTy = std::unordered_multimap; - MapTy Map; + static const char *const AddressSectionName; + static const char *const LabelSectionName; -public: - static const char *const SectionName; + /// Map multiple to . + using Addr2AddrMapTy = std::unordered_multimap; + Addr2AddrMapTy Address2AddressMap; + /// Map MCSymbol to its output address. Normally used for temp symbols that + /// are not updated by the linker. + using Label2AddrMapTy = DenseMap; + Label2AddrMapTy Label2AddrMap; + +public: static void emit(MCStreamer &Streamer, BinaryContext &BC); - static AddressMap parse(StringRef Buffer, const BinaryContext &BC); + static std::optional parse(BinaryContext &BC); std::optional lookup(uint64_t InputAddress) const { - auto It = Map.find(InputAddress); - if (It != Map.end()) + auto It = Address2AddressMap.find(InputAddress); + if (It != Address2AddressMap.end()) + return It->second; + return std::nullopt; + } + + std::optional lookup(const MCSymbol *Symbol) const { + auto It = Label2AddrMap.find(Symbol); + if (It != Label2AddrMap.end()) return It->second; return std::nullopt; } - std::pair + std::pair lookupAll(uint64_t InputAddress) const { - return Map.equal_range(InputAddress); + return Address2AddressMap.equal_range(InputAddress); } }; diff --git a/bolt/include/bolt/Core/BinaryFunction.h b/bolt/include/bolt/Core/BinaryFunction.h index a4c9eb4265ec9..c67ddccbf4892 100644 --- a/bolt/include/bolt/Core/BinaryFunction.h +++ b/bolt/include/bolt/Core/BinaryFunction.h @@ -1721,14 +1721,7 @@ class BinaryFunction { // Align data in code BFs minimum to CI alignment if (!size() && hasIslandsInfo()) return getConstantIslandAlignment(); - - // Minimal code alignment on AArch64 and RISCV is 4 - if (BC.isAArch64() || BC.isRISCV()) - return 4; - - // We have to use at least 2-byte alignment for functions because - // of C++ ABI. - return 2; + return BC.MIB->getMinFunctionAlignment(); } Align getMinAlign() const { return Align(getMinAlignment()); } diff --git a/bolt/include/bolt/Core/MCPlusBuilder.h b/bolt/include/bolt/Core/MCPlusBuilder.h index b6817c1d7f45e..d136c627bc5cc 100644 --- a/bolt/include/bolt/Core/MCPlusBuilder.h +++ b/bolt/include/bolt/Core/MCPlusBuilder.h @@ -2077,6 +2077,12 @@ class MCPlusBuilder { return BlocksVectorTy(); } + virtual uint16_t getMinFunctionAlignment() const { + // We have to use at least 2-byte alignment for functions because of C++ + // ABI. + return 2; + } + // AliasMap caches a mapping of registers to the set of registers that // alias (are sub or superregs of itself, including itself). std::vector AliasMap; diff --git a/bolt/lib/Core/AddressMap.cpp b/bolt/lib/Core/AddressMap.cpp index c5f628d878640..efa376d408db8 100644 --- a/bolt/lib/Core/AddressMap.cpp +++ b/bolt/lib/Core/AddressMap.cpp @@ -1,22 +1,44 @@ +//===- bolt/Core/AddressMap.cpp - Input-output Address Map ----------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + #include "bolt/Core/AddressMap.h" #include "bolt/Core/BinaryContext.h" #include "bolt/Core/BinaryFunction.h" +#include "bolt/Core/BinarySection.h" #include "llvm/MC/MCStreamer.h" #include "llvm/Support/DataExtractor.h" namespace llvm { namespace bolt { -const char *const AddressMap::SectionName = ".bolt.address_map"; +const char *const AddressMap::AddressSectionName = ".bolt.addr2addr_map"; +const char *const AddressMap::LabelSectionName = ".bolt.label2addr_map"; -static void emitLabel(MCStreamer &Streamer, uint64_t InputAddress, - const MCSymbol *OutputLabel) { +static void emitAddress(MCStreamer &Streamer, uint64_t InputAddress, + const MCSymbol *OutputLabel) { Streamer.emitIntValue(InputAddress, 8); Streamer.emitSymbolValue(OutputLabel, 8); } +static void emitLabel(MCStreamer &Streamer, const MCSymbol *OutputLabel) { + Streamer.emitIntValue(reinterpret_cast(OutputLabel), 8); + Streamer.emitSymbolValue(OutputLabel, 8); +} + void AddressMap::emit(MCStreamer &Streamer, BinaryContext &BC) { - Streamer.switchSection(BC.getDataSection(SectionName)); + // Mark map sections as link-only to avoid allocation in the output file. + const unsigned Flags = BinarySection::getFlags(/*IsReadOnly*/ true, + /*IsText*/ false, + /*IsAllocatable*/ true); + BC.registerOrUpdateSection(AddressSectionName, ELF::SHT_PROGBITS, Flags) + .setLinkOnly(); + BC.registerOrUpdateSection(LabelSectionName, ELF::SHT_PROGBITS, Flags) + .setLinkOnly(); for (const auto &[BFAddress, BF] : BC.getBinaryFunctions()) { if (!BF.requiresAddressMap()) @@ -26,37 +48,69 @@ void AddressMap::emit(MCStreamer &Streamer, BinaryContext &BC) { if (!BB.getLabel()->isDefined()) continue; - emitLabel(Streamer, BFAddress + BB.getInputAddressRange().first, - BB.getLabel()); + Streamer.switchSection(BC.getDataSection(LabelSectionName)); + emitLabel(Streamer, BB.getLabel()); if (!BB.hasLocSyms()) continue; + Streamer.switchSection(BC.getDataSection(AddressSectionName)); for (auto [Offset, Symbol] : BB.getLocSyms()) - emitLabel(Streamer, BFAddress + Offset, Symbol); + emitAddress(Streamer, BFAddress + Offset, Symbol); } } } -AddressMap AddressMap::parse(StringRef Buffer, const BinaryContext &BC) { - const auto EntrySize = 2 * BC.AsmInfo->getCodePointerSize(); - assert(Buffer.size() % EntrySize == 0 && "Unexpected address map size"); +std::optional AddressMap::parse(BinaryContext &BC) { + auto AddressMapSection = BC.getUniqueSectionByName(AddressSectionName); + auto LabelMapSection = BC.getUniqueSectionByName(LabelSectionName); - DataExtractor DE(Buffer, BC.AsmInfo->isLittleEndian(), - BC.AsmInfo->getCodePointerSize()); - DataExtractor::Cursor Cursor(0); + if (!AddressMapSection && !LabelMapSection) + return std::nullopt; AddressMap Parsed; - Parsed.Map.reserve(Buffer.size() / EntrySize); - while (Cursor && !DE.eof(Cursor)) { - const auto Input = DE.getAddress(Cursor); - const auto Output = DE.getAddress(Cursor); - if (!Parsed.Map.count(Input)) - Parsed.Map.insert({Input, Output}); + const size_t EntrySize = 2 * BC.AsmInfo->getCodePointerSize(); + auto parseSection = + [&](BinarySection &Section, + function_ref InsertCallback) { + StringRef Buffer = Section.getOutputContents(); + assert(Buffer.size() % EntrySize == 0 && "Unexpected address map size"); + + DataExtractor DE(Buffer, BC.AsmInfo->isLittleEndian(), + BC.AsmInfo->getCodePointerSize()); + DataExtractor::Cursor Cursor(0); + + while (Cursor && !DE.eof(Cursor)) { + const uint64_t Input = DE.getAddress(Cursor); + const uint64_t Output = DE.getAddress(Cursor); + InsertCallback(Input, Output); + } + + assert(Cursor && "Error reading address map section"); + BC.deregisterSection(Section); + }; + + if (AddressMapSection) { + Parsed.Address2AddressMap.reserve(AddressMapSection->getOutputSize() / + EntrySize); + parseSection(*AddressMapSection, [&](uint64_t Input, uint64_t Output) { + if (!Parsed.Address2AddressMap.count(Input)) + Parsed.Address2AddressMap.insert({Input, Output}); + }); + } + + if (LabelMapSection) { + Parsed.Label2AddrMap.reserve(LabelMapSection->getOutputSize() / EntrySize); + parseSection(*LabelMapSection, [&](uint64_t Input, uint64_t Output) { + assert(!Parsed.Label2AddrMap.count( + reinterpret_cast(Input)) && + "Duplicate label entry detected."); + Parsed.Label2AddrMap.insert( + {reinterpret_cast(Input), Output}); + }); } - assert(Cursor && "Error reading address map section"); return Parsed; } diff --git a/bolt/lib/Core/BinaryContext.cpp b/bolt/lib/Core/BinaryContext.cpp index f19460f8c1f52..8e2331db3e330 100644 --- a/bolt/lib/Core/BinaryContext.cpp +++ b/bolt/lib/Core/BinaryContext.cpp @@ -118,7 +118,7 @@ Expected> BinaryContext::createBinaryContext(const ObjectFile *File, bool IsPIC, std::unique_ptr DwCtx) { StringRef ArchName = ""; - StringRef FeaturesStr = ""; + std::string FeaturesStr = ""; switch (File->getArch()) { case llvm::Triple::x86_64: ArchName = "x86-64"; @@ -128,11 +128,20 @@ BinaryContext::createBinaryContext(const ObjectFile *File, bool IsPIC, ArchName = "aarch64"; FeaturesStr = "+all"; break; - case llvm::Triple::riscv64: + case llvm::Triple::riscv64: { ArchName = "riscv64"; - // RV64GC - FeaturesStr = "+m,+a,+f,+d,+zicsr,+zifencei,+c,+relax"; + Expected Features = File->getFeatures(); + + if (auto E = Features.takeError()) + return std::move(E); + + // We rely on relaxation for some transformations (e.g., promoting all calls + // to PseudoCALL and then making JITLink relax them). Since the relax + // feature is not stored in the object file, we manually enable it. + Features->AddFeature("relax"); + FeaturesStr = Features->getString(); break; + } default: return createStringError(std::errc::not_supported, "BOLT-ERROR: Unrecognized machine in ELF file"); diff --git a/bolt/lib/Core/BinaryFunction.cpp b/bolt/lib/Core/BinaryFunction.cpp index c196ab41e2a44..2e1fa739e53f2 100644 --- a/bolt/lib/Core/BinaryFunction.cpp +++ b/bolt/lib/Core/BinaryFunction.cpp @@ -2462,6 +2462,13 @@ struct CFISnapshot { case MCCFIInstruction::OpDefCfaRegister: CFAReg = Instr.getRegister(); CFARule = UNKNOWN; + + // This shouldn't happen according to the spec but GNU binutils on RISC-V + // emits a DW_CFA_def_cfa_register in CIE's which leaves the offset + // unspecified. Both readelf and llvm-dwarfdump interpret the offset as 0 + // in this case so let's do the same. + if (CFAOffset == UNKNOWN) + CFAOffset = 0; break; case MCCFIInstruction::OpDefCfaOffset: CFAOffset = Instr.getOffset(); @@ -4158,15 +4165,20 @@ void BinaryFunction::updateOutputValues(const BOLTLinker &Linker) { // Injected functions likely will fail lookup, as they have no // input range. Just assign the BB the output address of the // function. - auto MaybeBBAddress = - BC.getIOAddressMap().lookup(BB->getInputOffset() + getAddress()); + auto MaybeBBAddress = BC.getIOAddressMap().lookup(BB->getLabel()); const uint64_t BBAddress = MaybeBBAddress ? *MaybeBBAddress : BB->isSplit() ? FF.getAddress() : getOutputAddress(); BB->setOutputStartAddress(BBAddress); - if (PrevBB) + if (PrevBB) { + assert(PrevBB->getOutputAddressRange().first <= BBAddress && + "Bad output address for basic block."); + assert((PrevBB->getOutputAddressRange().first != BBAddress || + !hasInstructions() || PrevBB->empty()) && + "Bad output address for basic block."); PrevBB->setOutputEndAddress(BBAddress); + } PrevBB = BB; } diff --git a/bolt/lib/Passes/HFSortPlus.cpp b/bolt/lib/Passes/HFSortPlus.cpp index 70b9a4d51e6ee..0a481b5418dd2 100644 --- a/bolt/lib/Passes/HFSortPlus.cpp +++ b/bolt/lib/Passes/HFSortPlus.cpp @@ -567,7 +567,7 @@ class HFSortPlus { Into->Score = score(Into); // Remove chain From From the list of active chains - llvm::erase_value(HotChains, From); + llvm::erase(HotChains, From); } private: diff --git a/bolt/lib/Passes/IndirectCallPromotion.cpp b/bolt/lib/Passes/IndirectCallPromotion.cpp index ea8019431cf52..457997d35323d 100644 --- a/bolt/lib/Passes/IndirectCallPromotion.cpp +++ b/bolt/lib/Passes/IndirectCallPromotion.cpp @@ -591,7 +591,7 @@ IndirectCallPromotion::findCallTargetSymbols(std::vector &Targets, NewTargets.push_back(Target); std::vector({JTIndex}).swap(NewTargets.back().JTIndices); - llvm::erase_value(Target.JTIndices, JTIndex); + llvm::erase(Target.JTIndices, JTIndex); // Keep fixCFG counts sane if more indices use this same target later assert(IndicesPerTarget[Target.To.Sym] > 0 && "wrong map"); diff --git a/bolt/lib/Passes/ValidateMemRefs.cpp b/bolt/lib/Passes/ValidateMemRefs.cpp index 69cd82af16829..3324776830d17 100644 --- a/bolt/lib/Passes/ValidateMemRefs.cpp +++ b/bolt/lib/Passes/ValidateMemRefs.cpp @@ -34,8 +34,7 @@ bool ValidateMemRefs::checkAndFixJTReference(BinaryFunction &BF, MCInst &Inst, if (!JT) return false; - const bool IsLegitAccess = llvm::any_of( - JT->Parents, [&](const BinaryFunction *Parent) { return Parent == &BF; }); + const bool IsLegitAccess = llvm::is_contained(JT->Parents, &BF); if (IsLegitAccess) return true; diff --git a/bolt/lib/Profile/DataAggregator.cpp b/bolt/lib/Profile/DataAggregator.cpp index f8ade24bdc024..b72bd0edf1a2d 100644 --- a/bolt/lib/Profile/DataAggregator.cpp +++ b/bolt/lib/Profile/DataAggregator.cpp @@ -181,15 +181,13 @@ void DataAggregator::start() { "script -F pid,event,addr,ip", /*Wait = */false); - launchPerfProcess("process events", - MMapEventsPPI, - "script --show-mmap-events", - /*Wait = */false); + launchPerfProcess("process events", MMapEventsPPI, + "script --show-mmap-events --no-itrace", + /*Wait = */ false); - launchPerfProcess("task events", - TaskEventsPPI, - "script --show-task-events", - /*Wait = */false); + launchPerfProcess("task events", TaskEventsPPI, + "script --show-task-events --no-itrace", + /*Wait = */ false); } void DataAggregator::abort() { diff --git a/bolt/lib/Rewrite/RewriteInstance.cpp b/bolt/lib/Rewrite/RewriteInstance.cpp index b3de3b96b3ab8..0d78c9b75e03d 100644 --- a/bolt/lib/Rewrite/RewriteInstance.cpp +++ b/bolt/lib/Rewrite/RewriteInstance.cpp @@ -3196,9 +3196,6 @@ void RewriteInstance::preregisterSections() { ROFlags); BC->registerOrUpdateSection(getNewSecPrefix() + ".rodata.cold", ELF::SHT_PROGBITS, ROFlags); - BC->registerOrUpdateSection(AddressMap::SectionName, ELF::SHT_PROGBITS, - ROFlags) - .setLinkOnly(); } void RewriteInstance::emitAndLink() { @@ -3669,11 +3666,8 @@ void RewriteInstance::mapAllocatableSections( } void RewriteInstance::updateOutputValues(const BOLTLinker &Linker) { - if (auto MapSection = BC->getUniqueSectionByName(AddressMap::SectionName)) { - auto Map = AddressMap::parse(MapSection->getOutputContents(), *BC); - BC->setIOAddressMap(std::move(Map)); - BC->deregisterSection(*MapSection); - } + if (std::optional Map = AddressMap::parse(*BC)) + BC->setIOAddressMap(std::move(*Map)); for (BinaryFunction *Function : BC->getAllBinaryFunctions()) Function->updateOutputValues(Linker); diff --git a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp index c2a4607411a49..b31813680f121 100644 --- a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp +++ b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp @@ -1643,6 +1643,8 @@ class AArch64MCPlusBuilder : public MCPlusBuilder { return Relocation({RelOffset, RelSymbol, RelType, RelAddend, 0}); } + + uint16_t getMinFunctionAlignment() const override { return 4; } }; } // end anonymous namespace diff --git a/bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp b/bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp index 85855fbf3ab97..c2bc597950b85 100644 --- a/bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp +++ b/bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp @@ -15,6 +15,7 @@ #include "bolt/Core/MCPlusBuilder.h" #include "llvm/BinaryFormat/ELF.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/Format.h" @@ -490,6 +491,13 @@ class RISCVMCPlusBuilder : public MCPlusBuilder { assert(Second.getOpcode() == RISCV::JALR); return true; } + + uint16_t getMinFunctionAlignment() const override { + if (STI->hasFeature(RISCV::FeatureStdExtC) || + STI->hasFeature(RISCV::FeatureStdExtZca)) + return 2; + return 4; + } }; } // end anonymous namespace diff --git a/bolt/test/RISCV/Inputs/cie-gnu.yaml b/bolt/test/RISCV/Inputs/cie-gnu.yaml new file mode 100644 index 0000000000000..7e05636ef86ab --- /dev/null +++ b/bolt/test/RISCV/Inputs/cie-gnu.yaml @@ -0,0 +1,109 @@ +## Compiled and stripped-down version of: +## (riscv64-linux-gnu-gcc -nostdlib -static -Wl,-q cie-gnu.s) +# .text +# .globl _start +# .type _start, @function +# _start: +# .cfi_startproc +# beq a0, a1, 1f +# ret +# 1: +# .cfi_undefined t0 # Arbitrary cfi command to force a new state +# ret +# .cfi_endproc +# .size _start, .-_start + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_EXEC + Machine: EM_RISCV + Flags: [ EF_RISCV_RVC, EF_RISCV_FLOAT_ABI_DOUBLE ] + Entry: 0x10144 +ProgramHeaders: + - Type: PT_LOAD + Flags: [ PF_X, PF_R ] + FirstSec: .text + LastSec: .eh_frame + VAddr: 0x10000 + Align: 0x1000 + Offset: 0x0 +Sections: + - Name: .text + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC, SHF_EXECINSTR ] + Address: 0x10144 + AddressAlign: 0x2 + Offset: 0x144 + Content: 6303B50082808280 + - Name: .eh_frame + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC ] + Address: 0x10150 + AddressAlign: 0x8 + Content: 1000000000000000037A5200017C01011B0D02001000000018000000D8FFFFFF0800000000460705 + - Name: .rela.text + Type: SHT_RELA + Flags: [ SHF_INFO_LINK ] + Link: .symtab + AddressAlign: 0x8 + Info: .text + Relocations: + - Offset: 0x10144 + Symbol: ".L1\x021" + Type: R_RISCV_BRANCH + - Name: .rela.eh_frame + Type: SHT_RELA + Flags: [ SHF_INFO_LINK ] + Link: .symtab + AddressAlign: 0x8 + Info: .eh_frame + Relocations: + - Offset: 0x1016C + Symbol: '.L0 ' + Type: R_RISCV_32_PCREL + - Offset: 0x10170 + Symbol: '.L0 (1)' + Type: R_RISCV_ADD32 + - Offset: 0x10170 + Symbol: '.L0 ' + Type: R_RISCV_SUB32 + - Offset: 0x10175 + Symbol: '.L0 (2)' + Type: R_RISCV_SET6 + - Offset: 0x10175 + Symbol: '.L0 ' + Type: R_RISCV_SUB6 + - Type: SectionHeaderTable + Sections: + - Name: .text + - Name: .rela.text + - Name: .eh_frame + - Name: .rela.eh_frame + - Name: .symtab + - Name: .strtab + - Name: .shstrtab +Symbols: + - Name: '$x' + Section: .text + Value: 0x10144 + - Name: ".L1\x021" + Section: .text + Value: 0x1014A + - Name: '.L0 ' + Section: .text + Value: 0x10144 + - Name: '.L0 (1)' + Section: .text + Value: 0x1014C + - Name: '.L0 (2)' + Section: .text + Value: 0x1014A + - Name: _start + Type: STT_FUNC + Section: .text + Binding: STB_GLOBAL + Value: 0x10144 + Size: 0x8 +... diff --git a/bolt/test/RISCV/call-annotations.s b/bolt/test/RISCV/call-annotations.s index bc539bb0ec779..477c4693cd6dd 100644 --- a/bolt/test/RISCV/call-annotations.s +++ b/bolt/test/RISCV/call-annotations.s @@ -1,12 +1,13 @@ /// Test that annotations are properly carried over to fixed calls. /// Note that --enable-bat is used to force offsets to be kept. -// RUN: llvm-mc -triple riscv64 -filetype obj -o %t.o %s +// RUN: llvm-mc -triple riscv64 -mattr=+c -filetype obj -o %t.o %s // RUN: ld.lld --emit-relocs -o %t %t.o // RUN: llvm-bolt --enable-bat --print-cfg --print-fix-riscv-calls \ // RUN: -o /dev/null %t | FileCheck %s .text + .option norvc .global f .p2align 1 f: diff --git a/bolt/test/RISCV/cie-gnu.test b/bolt/test/RISCV/cie-gnu.test new file mode 100644 index 0000000000000..deea8027ef3d6 --- /dev/null +++ b/bolt/test/RISCV/cie-gnu.test @@ -0,0 +1,17 @@ +# Test that BOLT can handle CIE's produced by GNU as. On RISC-V, GNU as produces +# the following initial instruction: +# DW_CFA_def_cfa_register: r2 +# While I believe it is technically incorrect to use this instruction without +# first using a DW_CFA_def_cfa (since the offset is unspecified), both readelf +# and llvm-dwarfdump accept this and implicitly set the offset to 0. +# In BOLT, this used to trigger an assert, however, since it (correctly) +# believed the offset was not set. This test checks we can handle this +# situation. + +RUN: yaml2obj -o %t %p/Inputs/cie-gnu.yaml +RUN: llvm-bolt -o %t.bolt %t --reorder-blocks=reverse +RUN: llvm-dwarfdump --debug-frame %t.bolt | FileCheck %s + +CHECK: 0x400000: CFA=X2 +CHECK: 0x400004: CFA=X2: X5=undefined +CHECK: 0x400006: CFA=X2 diff --git a/bolt/test/RISCV/function-alignment.s b/bolt/test/RISCV/function-alignment.s new file mode 100644 index 0000000000000..c52cff9e2347a --- /dev/null +++ b/bolt/test/RISCV/function-alignment.s @@ -0,0 +1,38 @@ +## Test that BOLT uses a minimum function alignment of 4 (or 2 for RVC) bytes. + +# RUN: llvm-mc -triple=riscv64 -filetype=obj -o %t.o %s +# RUN: ld.lld -q -o %t %t.o +# RUN: llvm-bolt --align-functions=1 --use-old-text=0 -o %t.bolt %t +# RUN: llvm-nm -n %t.bolt | FileCheck %s + +# RUN: llvm-mc -triple=riscv64 -mattr=+c -filetype=obj -o %t-c.o %s +# RUN: ld.lld -q -o %t-c %t-c.o +# RUN: llvm-bolt --align-functions=1 --use-old-text=0 -o %t-c.bolt %t-c +# RUN: llvm-nm -n %t-c.bolt | FileCheck --check-prefix=CHECK-C %s + +# CHECK: {{[048c]}} T _start +# CHECK-NEXT: {{[048c]}} T dummy + +# CHECK-C: {{[02468ace]}} T _start +# CHECK-C-NEXT: {{[02468ace]}} T dummy + + .text + + # Make sure input binary is only 1 byte aligned. BOLT should increase the + # alignment to 2 or 4 bytes. + .byte 0 + .balign 1 + + .globl _start + .type _start, @function +_start: + # Dummy reloc to force relocation mode. + .reloc 0, R_RISCV_NONE + ret + .size _start, .-_start + + .globl dummy + .type dummy, @function +dummy: + ret + .size dummy, .-dummy diff --git a/bolt/test/RISCV/internal-func-reloc.s b/bolt/test/RISCV/internal-func-reloc.s index ea99b564fe42c..c6c74bed92efe 100644 --- a/bolt/test/RISCV/internal-func-reloc.s +++ b/bolt/test/RISCV/internal-func-reloc.s @@ -2,18 +2,14 @@ /// get transformed by BOLT. The tests rely on the "remove-nops" optimization: /// if nops got removed from the function, it got transformed by BOLT. -// RUN: %clang %cflags -o %t %s +// RUN: llvm-mc -triple riscv64 -filetype=obj -o %t.o %s +// RUN: ld.lld --emit-relocs -o %t %t.o // RUN: llvm-bolt -o %t.bolt %t // RUN: llvm-objdump -d %t.bolt | FileCheck %s .text - - /// These options are only used to make the assembler output easier to predict - .option norelax - .option norvc - .globl _start - .p2align 1 + .p2align 2 // CHECK: <_start>: // CHECK-NEXT: j 0x{{.*}} <_start> _start: @@ -23,10 +19,10 @@ _start: .size _start, .-_start .globl f - .p2align 1 + .p2align 2 // CHECK: : -// CHECK-NEXT: auipc a0, 0 -// CHECK-NEXT: addi a0, a0, 64 +// CHECK-NEXT: auipc a0, [[#]] +// CHECK-NEXT: addi a0, a0, [[#]] f: nop 1: @@ -37,7 +33,7 @@ f: .size f, .-f .globl g - .p2align 1 + .p2align 2 g: ret .size g, .-g diff --git a/bolt/test/X86/jump-table-icp.test b/bolt/test/X86/jump-table-icp.test index 708f1273af3f1..34339dc327fae 100644 --- a/bolt/test/X86/jump-table-icp.test +++ b/bolt/test/X86/jump-table-icp.test @@ -12,6 +12,7 @@ RUN: (llvm-bolt %t.exe --data %t.fdata -o %t --relocs \ RUN: --reorder-blocks=cache --split-functions --split-all-cold \ RUN: --use-gnu-stack --dyno-stats --indirect-call-promotion=jump-tables \ RUN: --print-icp -v=0 \ +RUN: --enable-bat --print-cache-metrics \ RUN: --icp-jt-remaining-percent-threshold=10 \ RUN: --icp-jt-total-percent-threshold=2 \ RUN: --indirect-call-promotion-topn=1 \ diff --git a/clang-tools-extra/clang-tidy/bugprone/BugproneTidyModule.cpp b/clang-tools-extra/clang-tidy/bugprone/BugproneTidyModule.cpp index 543c522899d7a..7a910037368c8 100644 --- a/clang-tools-extra/clang-tidy/bugprone/BugproneTidyModule.cpp +++ b/clang-tools-extra/clang-tidy/bugprone/BugproneTidyModule.cpp @@ -16,6 +16,7 @@ #include "BadSignalToKillThreadCheck.h" #include "BoolPointerImplicitConversionCheck.h" #include "BranchCloneCheck.h" +#include "CastingThroughVoidCheck.h" #include "ComparePointerToMemberVirtualFunctionCheck.h" #include "CopyConstructorInitCheck.h" #include "DanglingHandleCheck.h" @@ -104,6 +105,8 @@ class BugproneModule : public ClangTidyModule { CheckFactories.registerCheck( "bugprone-bool-pointer-implicit-conversion"); CheckFactories.registerCheck("bugprone-branch-clone"); + CheckFactories.registerCheck( + "bugprone-casting-through-void"); CheckFactories.registerCheck( "bugprone-compare-pointer-to-member-virtual-function"); CheckFactories.registerCheck( diff --git a/clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt b/clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt index 0df9e439b715e..d443fd8d1452f 100644 --- a/clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt +++ b/clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt @@ -11,6 +11,7 @@ add_clang_library(clangTidyBugproneModule BoolPointerImplicitConversionCheck.cpp BranchCloneCheck.cpp BugproneTidyModule.cpp + CastingThroughVoidCheck.cpp ComparePointerToMemberVirtualFunctionCheck.cpp CopyConstructorInitCheck.cpp DanglingHandleCheck.cpp diff --git a/clang-tools-extra/clang-tidy/bugprone/CastingThroughVoidCheck.cpp b/clang-tools-extra/clang-tidy/bugprone/CastingThroughVoidCheck.cpp new file mode 100644 index 0000000000000..4c2416a89aef9 --- /dev/null +++ b/clang-tools-extra/clang-tidy/bugprone/CastingThroughVoidCheck.cpp @@ -0,0 +1,45 @@ +//===--- CastingThroughVoidCheck.cpp - clang-tidy -------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "CastingThroughVoidCheck.h" +#include "clang/AST/ASTContext.h" +#include "clang/AST/Expr.h" +#include "clang/AST/Type.h" +#include "clang/ASTMatchers/ASTMatchFinder.h" +#include "clang/ASTMatchers/ASTMatchers.h" +#include "llvm/ADT/StringSet.h" + +using namespace clang::ast_matchers; + +namespace clang::tidy::bugprone { + +void CastingThroughVoidCheck::registerMatchers(MatchFinder *Finder) { + Finder->addMatcher( + explicitCastExpr( + hasDestinationType( + qualType(unless(hasCanonicalType(pointsTo(voidType())))) + .bind("target_type")), + hasSourceExpression( + explicitCastExpr( + hasSourceExpression( + expr(hasType(qualType().bind("source_type")))), + hasDestinationType( + qualType(pointsTo(voidType())).bind("void_type"))) + .bind("cast"))), + this); +} + +void CastingThroughVoidCheck::check(const MatchFinder::MatchResult &Result) { + const auto TT = *Result.Nodes.getNodeAs("target_type"); + const auto ST = *Result.Nodes.getNodeAs("source_type"); + const auto VT = *Result.Nodes.getNodeAs("void_type"); + const auto *CE = Result.Nodes.getNodeAs("cast"); + diag(CE->getExprLoc(), "do not cast %0 to %1 through %2") << ST << TT << VT; +} + +} // namespace clang::tidy::bugprone diff --git a/clang-tools-extra/clang-tidy/bugprone/CastingThroughVoidCheck.h b/clang-tools-extra/clang-tidy/bugprone/CastingThroughVoidCheck.h new file mode 100644 index 0000000000000..834676aaf0543 --- /dev/null +++ b/clang-tools-extra/clang-tidy/bugprone/CastingThroughVoidCheck.h @@ -0,0 +1,32 @@ +//===--- CastingThroughVoidCheck.h - clang-tidy -----------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_BUGPRONE_CASTINGTHROUGHVOIDCHECK_H +#define LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_BUGPRONE_CASTINGTHROUGHVOIDCHECK_H + +#include "../ClangTidyCheck.h" + +namespace clang::tidy::bugprone { + +/// Detects unsafe or redundant two-step casting operations involving ``void*``. +/// For the user-facing documentation see: +/// http://clang.llvm.org/extra/clang-tidy/checks/bugprone/casting-through-void.html +class CastingThroughVoidCheck : public ClangTidyCheck { +public: + CastingThroughVoidCheck(StringRef Name, ClangTidyContext *Context) + : ClangTidyCheck(Name, Context) {} + void registerMatchers(ast_matchers::MatchFinder *Finder) override; + void check(const ast_matchers::MatchFinder::MatchResult &Result) override; + std::optional getCheckTraversalKind() const override { + return TK_IgnoreUnlessSpelledInSource; + } +}; + +} // namespace clang::tidy::bugprone + +#endif // LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_BUGPRONE_CASTINGTHROUGHVOIDCHECK_H diff --git a/clang-tools-extra/clang-tidy/bugprone/DanglingHandleCheck.cpp b/clang-tools-extra/clang-tidy/bugprone/DanglingHandleCheck.cpp index 9ded699ba78e6..d55df3a6d7b74 100644 --- a/clang-tools-extra/clang-tidy/bugprone/DanglingHandleCheck.cpp +++ b/clang-tools-extra/clang-tidy/bugprone/DanglingHandleCheck.cpp @@ -33,14 +33,20 @@ handleFrom(const ast_matchers::internal::Matcher &IsAHandle, ast_matchers::internal::Matcher handleFromTemporaryValue( const ast_matchers::internal::Matcher &IsAHandle) { + + const auto TemporaryExpr = anyOf( + cxxBindTemporaryExpr(), + cxxFunctionalCastExpr( + hasCastKind(CK_ConstructorConversion), + hasSourceExpression(ignoringParenImpCasts(cxxBindTemporaryExpr())))); // If a ternary operator returns a temporary value, then both branches hold a // temporary value. If one of them is not a temporary then it must be copied // into one to satisfy the type of the operator. const auto TemporaryTernary = conditionalOperator( - hasTrueExpression(ignoringParenImpCasts(cxxBindTemporaryExpr())), - hasFalseExpression(ignoringParenImpCasts(cxxBindTemporaryExpr()))); + hasTrueExpression(ignoringParenImpCasts(TemporaryExpr)), + hasFalseExpression(ignoringParenImpCasts(TemporaryExpr))); - return handleFrom(IsAHandle, anyOf(cxxBindTemporaryExpr(), TemporaryTernary)); + return handleFrom(IsAHandle, anyOf(TemporaryExpr, TemporaryTernary)); } ast_matchers::internal::Matcher isASequence() { diff --git a/clang-tools-extra/clang-tidy/bugprone/UnusedReturnValueCheck.cpp b/clang-tools-extra/clang-tidy/bugprone/UnusedReturnValueCheck.cpp index bdc601c2445f5..6bc9f2dd367dc 100644 --- a/clang-tools-extra/clang-tidy/bugprone/UnusedReturnValueCheck.cpp +++ b/clang-tools-extra/clang-tidy/bugprone/UnusedReturnValueCheck.cpp @@ -130,26 +130,35 @@ UnusedReturnValueCheck::UnusedReturnValueCheck(llvm::StringRef Name, "::std::error_condition;" "::std::errc;" "::std::expected;" - "::boost::system::error_code"))) {} + "::boost::system::error_code"))), + AllowCastToVoid(Options.get("AllowCastToVoid", false)) {} void UnusedReturnValueCheck::storeOptions(ClangTidyOptions::OptionMap &Opts) { Options.store(Opts, "CheckedFunctions", CheckedFunctions); Options.store(Opts, "CheckedReturnTypes", utils::options::serializeStringList(CheckedReturnTypes)); + Options.store(Opts, "AllowCastToVoid", AllowCastToVoid); } void UnusedReturnValueCheck::registerMatchers(MatchFinder *Finder) { auto FunVec = utils::options::parseStringList(CheckedFunctions); - auto MatchedCallExpr = expr(ignoringImplicit(ignoringParenImpCasts( - callExpr(callee(functionDecl( - // Don't match void overloads of checked functions. - unless(returns(voidType())), - anyOf(isInstantiatedFrom(hasAnyName(FunVec)), - returns(hasCanonicalType(hasDeclaration( - namedDecl(matchers::matchesAnyListedName( - CheckedReturnTypes))))))))) - .bind("match")))); + auto MatchedDirectCallExpr = + expr(callExpr(callee(functionDecl( + // Don't match void overloads of checked functions. + unless(returns(voidType())), + anyOf(isInstantiatedFrom(hasAnyName(FunVec)), + returns(hasCanonicalType(hasDeclaration( + namedDecl(matchers::matchesAnyListedName( + CheckedReturnTypes))))))))) + .bind("match")); + + auto CheckCastToVoid = + AllowCastToVoid ? castExpr(unless(hasCastKind(CK_ToVoid))) : castExpr(); + auto MatchedCallExpr = expr( + anyOf(MatchedDirectCallExpr, + explicitCastExpr(unless(cxxFunctionalCastExpr()), CheckCastToVoid, + hasSourceExpression(MatchedDirectCallExpr)))); auto UnusedInCompoundStmt = compoundStmt(forEach(MatchedCallExpr), @@ -178,8 +187,13 @@ void UnusedReturnValueCheck::registerMatchers(MatchFinder *Finder) { void UnusedReturnValueCheck::check(const MatchFinder::MatchResult &Result) { if (const auto *Matched = Result.Nodes.getNodeAs("match")) { diag(Matched->getBeginLoc(), - "the value returned by this function should be used") + "the value returned by this function should not be disregarded; " + "neglecting it may lead to errors") << Matched->getSourceRange(); + + if (!AllowCastToVoid) + return; + diag(Matched->getBeginLoc(), "cast the expression to void to silence this warning", DiagnosticIDs::Note); diff --git a/clang-tools-extra/clang-tidy/bugprone/UnusedReturnValueCheck.h b/clang-tools-extra/clang-tidy/bugprone/UnusedReturnValueCheck.h index 15881e12ca0c3..b4356f8379fdc 100644 --- a/clang-tools-extra/clang-tidy/bugprone/UnusedReturnValueCheck.h +++ b/clang-tools-extra/clang-tidy/bugprone/UnusedReturnValueCheck.h @@ -24,10 +24,14 @@ class UnusedReturnValueCheck : public ClangTidyCheck { void storeOptions(ClangTidyOptions::OptionMap &Opts) override; void registerMatchers(ast_matchers::MatchFinder *Finder) override; void check(const ast_matchers::MatchFinder::MatchResult &Result) override; + std::optional getCheckTraversalKind() const override { + return TK_IgnoreUnlessSpelledInSource; + } private: std::string CheckedFunctions; const std::vector CheckedReturnTypes; + const bool AllowCastToVoid; }; } // namespace clang::tidy::bugprone diff --git a/clang-tools-extra/clang-tidy/cert/CERTTidyModule.cpp b/clang-tools-extra/clang-tidy/cert/CERTTidyModule.cpp index d448d9ba61454..d334ab8c437d3 100644 --- a/clang-tools-extra/clang-tidy/cert/CERTTidyModule.cpp +++ b/clang-tools-extra/clang-tidy/cert/CERTTidyModule.cpp @@ -328,6 +328,7 @@ class CERTModule : public ClangTidyModule { ClangTidyOptions::OptionMap &Opts = Options.CheckOptions; Opts["cert-dcl16-c.NewSuffixes"] = "L;LL;LU;LLU"; Opts["cert-err33-c.CheckedFunctions"] = CertErr33CCheckedFunctions; + Opts["cert-err33-c.AllowCastToVoid"] = "true"; Opts["cert-oop54-cpp.WarnOnlyIfThisHasSuspiciousField"] = "false"; Opts["cert-str34-c.DiagnoseSignedUnsignedCharComparisons"] = "false"; return Options; diff --git a/clang-tools-extra/clang-tidy/cppcoreguidelines/NarrowingConversionsCheck.cpp b/clang-tools-extra/clang-tidy/cppcoreguidelines/NarrowingConversionsCheck.cpp index 1b858db511f50..45fef9471d521 100644 --- a/clang-tools-extra/clang-tidy/cppcoreguidelines/NarrowingConversionsCheck.cpp +++ b/clang-tools-extra/clang-tidy/cppcoreguidelines/NarrowingConversionsCheck.cpp @@ -14,6 +14,7 @@ #include "clang/ASTMatchers/ASTMatchFinder.h" #include "clang/ASTMatchers/ASTMatchers.h" #include "llvm/ADT/APSInt.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/SmallVector.h" @@ -23,6 +24,26 @@ using namespace clang::ast_matchers; namespace clang::tidy::cppcoreguidelines { +namespace { + +AST_MATCHER_P(QualType, hasAnyType, std::vector, Names) { + if (Names.empty()) + return false; + + std::string Name = Node.getLocalUnqualifiedType().getAsString(); + return llvm::any_of(Names, [&Name](StringRef Ref) { return Ref == Name; }); +} + +AST_MATCHER(FieldDecl, hasIntBitwidth) { + assert(Node.isBitField()); + const ASTContext &Ctx = Node.getASTContext(); + unsigned IntBitWidth = Ctx.getIntWidth(Ctx.IntTy); + unsigned CurrentBitWidth = Node.getBitWidthValue(Ctx); + return IntBitWidth == CurrentBitWidth; +} + +} // namespace + NarrowingConversionsCheck::NarrowingConversionsCheck(StringRef Name, ClangTidyContext *Context) : ClangTidyCheck(Name, Context), @@ -53,25 +74,22 @@ void NarrowingConversionsCheck::storeOptions( Options.store(Opts, "PedanticMode", PedanticMode); } -AST_MATCHER(FieldDecl, hasIntBitwidth) { - assert(Node.isBitField()); - const ASTContext &Ctx = Node.getASTContext(); - unsigned IntBitWidth = Ctx.getIntWidth(Ctx.IntTy); - unsigned CurrentBitWidth = Node.getBitWidthValue(Ctx); - return IntBitWidth == CurrentBitWidth; -} - void NarrowingConversionsCheck::registerMatchers(MatchFinder *Finder) { // ceil() and floor() are guaranteed to return integers, even though the type // is not integral. const auto IsCeilFloorCallExpr = expr(callExpr(callee(functionDecl( hasAnyName("::ceil", "::std::ceil", "::floor", "::std::floor"))))); + std::vector IgnoreConversionFromTypesVec = + utils::options::parseStringList(IgnoreConversionFromTypes); + // We may want to exclude other types from the checks, such as `size_type` // and `difference_type`. These are often used to count elements, represented // in 64 bits and assigned to `int`. Rarely are people counting >2B elements. - const auto IsConversionFromIgnoredType = hasType(namedDecl( - hasAnyName(utils::options::parseStringList(IgnoreConversionFromTypes)))); + const auto IsConversionFromIgnoredType = + anyOf(hasType(namedDecl(hasAnyName(IgnoreConversionFromTypesVec))), + allOf(unless(hasType(namedDecl())), + hasType(qualType(hasAnyType(IgnoreConversionFromTypesVec))))); // `IsConversionFromIgnoredType` will ignore narrowing calls from those types, // but not expressions that are promoted to an ignored type as a result of a diff --git a/clang-tools-extra/clang-tidy/cppcoreguidelines/PreferMemberInitializerCheck.cpp b/clang-tools-extra/clang-tidy/cppcoreguidelines/PreferMemberInitializerCheck.cpp index aac824f15fa57..b6daf8b936bde 100644 --- a/clang-tools-extra/clang-tidy/cppcoreguidelines/PreferMemberInitializerCheck.cpp +++ b/clang-tools-extra/clang-tidy/cppcoreguidelines/PreferMemberInitializerCheck.cpp @@ -8,8 +8,10 @@ #include "PreferMemberInitializerCheck.h" #include "clang/AST/ASTContext.h" +#include "clang/AST/Decl.h" #include "clang/ASTMatchers/ASTMatchFinder.h" #include "clang/Lex/Lexer.h" +#include "llvm/ADT/DenseMap.h" using namespace clang::ast_matchers; @@ -54,31 +56,66 @@ static bool shouldBeDefaultMemberInitializer(const Expr *Value) { } namespace { + AST_MATCHER_P(FieldDecl, indexNotLessThan, unsigned, Index) { return Node.getFieldIndex() >= Index; } + +enum class AssignedLevel { + // Field is not assigned. + None, + // Field is assigned. + Default, + // Assignment of field has side effect: + // - assign to reference. + // FIXME: support other side effect. + HasSideEffect, + // Assignment of field has data dependence. + HasDependence, +}; + } // namespace +static bool canAdvanceAssignment(AssignedLevel Level) { + return Level == AssignedLevel::None || Level == AssignedLevel::Default; +} + // Checks if Field is initialised using a field that will be initialised after // it. // TODO: Probably should guard against function calls that could have side -// effects or if they do reference another field that's initialized before this -// field, but is modified before the assignment. -static bool isSafeAssignment(const FieldDecl *Field, const Expr *Init, - const CXXConstructorDecl *Context) { +// effects or if they do reference another field that's initialized before +// this field, but is modified before the assignment. +static void updateAssignmentLevel( + const FieldDecl *Field, const Expr *Init, const CXXConstructorDecl *Ctor, + llvm::DenseMap &AssignedFields) { + auto It = AssignedFields.find(Field); + if (It == AssignedFields.end()) + It = AssignedFields.insert({Field, AssignedLevel::None}).first; + + if (!canAdvanceAssignment(It->second)) + // fast path for already decided field. + return; + + if (Field->getType().getCanonicalType()->isReferenceType()) { + // assign to reference type twice cannot be simplified to once. + It->second = AssignedLevel::HasSideEffect; + return; + } auto MemberMatcher = memberExpr(hasObjectExpression(cxxThisExpr()), member(fieldDecl(indexNotLessThan(Field->getFieldIndex())))); - auto DeclMatcher = declRefExpr( - to(varDecl(unless(parmVarDecl()), hasDeclContext(equalsNode(Context))))); - - return match(expr(anyOf(MemberMatcher, DeclMatcher, - hasDescendant(MemberMatcher), - hasDescendant(DeclMatcher))), - *Init, Field->getASTContext()) - .empty(); + to(varDecl(unless(parmVarDecl()), hasDeclContext(equalsNode(Ctor))))); + const bool HasDependence = !match(expr(anyOf(MemberMatcher, DeclMatcher, + hasDescendant(MemberMatcher), + hasDescendant(DeclMatcher))), + *Init, Field->getASTContext()) + .empty(); + if (HasDependence) { + It->second = AssignedLevel::HasDependence; + return; + } } static std::pair @@ -99,9 +136,9 @@ isAssignmentToMemberOf(const CXXRecordDecl *Rec, const Stmt *S, if (!isa(ME->getBase())) return std::make_pair(nullptr, nullptr); const Expr *Init = BO->getRHS()->IgnoreParenImpCasts(); - if (isSafeAssignment(Field, Init, Ctor)) - return std::make_pair(Field, Init); - } else if (const auto *COCE = dyn_cast(S)) { + return std::make_pair(Field, Init); + } + if (const auto *COCE = dyn_cast(S)) { if (COCE->getOperator() != OO_Equal) return std::make_pair(nullptr, nullptr); @@ -117,10 +154,8 @@ isAssignmentToMemberOf(const CXXRecordDecl *Rec, const Stmt *S, if (!isa(ME->getBase())) return std::make_pair(nullptr, nullptr); const Expr *Init = COCE->getArg(1)->IgnoreParenImpCasts(); - if (isSafeAssignment(Field, Init, Ctor)) - return std::make_pair(Field, Init); + return std::make_pair(Field, Init); } - return std::make_pair(nullptr, nullptr); } @@ -156,6 +191,12 @@ void PreferMemberInitializerCheck::check( const CXXRecordDecl *Class = Ctor->getParent(); bool FirstToCtorInits = true; + llvm::DenseMap AssignedFields{}; + + for (const CXXCtorInitializer *Init : Ctor->inits()) + if (FieldDecl *Field = Init->getMember()) + updateAssignmentLevel(Field, Init->getInit(), Ctor, AssignedFields); + for (const Stmt *S : Body->body()) { if (S->getBeginLoc().isMacroID()) { StringRef MacroName = Lexer::getImmediateMacroName( @@ -178,140 +219,143 @@ void PreferMemberInitializerCheck::check( const FieldDecl *Field = nullptr; const Expr *InitValue = nullptr; std::tie(Field, InitValue) = isAssignmentToMemberOf(Class, S, Ctor); - if (Field) { - if (IsUseDefaultMemberInitEnabled && getLangOpts().CPlusPlus11 && - Ctor->isDefaultConstructor() && - (getLangOpts().CPlusPlus20 || !Field->isBitField()) && - !Field->hasInClassInitializer() && - (!isa(Class->getDeclContext()) || - !cast(Class->getDeclContext())->isUnion()) && - shouldBeDefaultMemberInitializer(InitValue)) { - - bool InvalidFix = false; - SourceLocation FieldEnd = - Lexer::getLocForEndOfToken(Field->getSourceRange().getEnd(), 0, - *Result.SourceManager, getLangOpts()); - InvalidFix |= FieldEnd.isInvalid() || FieldEnd.isMacroID(); - SourceLocation SemiColonEnd; - if (auto NextToken = Lexer::findNextToken( - S->getEndLoc(), *Result.SourceManager, getLangOpts())) - SemiColonEnd = NextToken->getEndLoc(); - else - InvalidFix = true; - auto Diag = - diag(S->getBeginLoc(), "%0 should be initialized in an in-class" - " default member initializer") - << Field; - if (InvalidFix) + if (!Field) + continue; + updateAssignmentLevel(Field, InitValue, Ctor, AssignedFields); + if (!canAdvanceAssignment(AssignedFields[Field])) + continue; + const bool IsInDefaultMemberInitializer = + IsUseDefaultMemberInitEnabled && getLangOpts().CPlusPlus11 && + Ctor->isDefaultConstructor() && + (getLangOpts().CPlusPlus20 || !Field->isBitField()) && + !Field->hasInClassInitializer() && + (!isa(Class->getDeclContext()) || + !cast(Class->getDeclContext())->isUnion()) && + shouldBeDefaultMemberInitializer(InitValue); + if (IsInDefaultMemberInitializer) { + bool InvalidFix = false; + SourceLocation FieldEnd = + Lexer::getLocForEndOfToken(Field->getSourceRange().getEnd(), 0, + *Result.SourceManager, getLangOpts()); + InvalidFix |= FieldEnd.isInvalid() || FieldEnd.isMacroID(); + SourceLocation SemiColonEnd; + if (auto NextToken = Lexer::findNextToken( + S->getEndLoc(), *Result.SourceManager, getLangOpts())) + SemiColonEnd = NextToken->getEndLoc(); + else + InvalidFix = true; + auto Diag = + diag(S->getBeginLoc(), "%0 should be initialized in an in-class" + " default member initializer") + << Field; + if (InvalidFix) + continue; + CharSourceRange StmtRange = + CharSourceRange::getCharRange(S->getBeginLoc(), SemiColonEnd); + + SmallString<128> Insertion( + {UseAssignment ? " = " : "{", + Lexer::getSourceText( + CharSourceRange(InitValue->getSourceRange(), true), + *Result.SourceManager, getLangOpts()), + UseAssignment ? "" : "}"}); + + Diag << FixItHint::CreateInsertion(FieldEnd, Insertion) + << FixItHint::CreateRemoval(StmtRange); + + } else { + StringRef InsertPrefix = ""; + bool HasInitAlready = false; + SourceLocation InsertPos; + SourceRange ReplaceRange; + bool AddComma = false; + bool InvalidFix = false; + unsigned Index = Field->getFieldIndex(); + const CXXCtorInitializer *LastInListInit = nullptr; + for (const CXXCtorInitializer *Init : Ctor->inits()) { + if (!Init->isWritten() || Init->isInClassMemberInitializer()) continue; - CharSourceRange StmtRange = - CharSourceRange::getCharRange(S->getBeginLoc(), SemiColonEnd); - - SmallString<128> Insertion( - {UseAssignment ? " = " : "{", - Lexer::getSourceText( - CharSourceRange(InitValue->getSourceRange(), true), - *Result.SourceManager, getLangOpts()), - UseAssignment ? "" : "}"}); - - Diag << FixItHint::CreateInsertion(FieldEnd, Insertion) - << FixItHint::CreateRemoval(StmtRange); - - } else { - StringRef InsertPrefix = ""; - bool HasInitAlready = false; - SourceLocation InsertPos; - SourceRange ReplaceRange; - bool AddComma = false; - bool InvalidFix = false; - unsigned Index = Field->getFieldIndex(); - const CXXCtorInitializer *LastInListInit = nullptr; - for (const CXXCtorInitializer *Init : Ctor->inits()) { - if (!Init->isWritten() || Init->isInClassMemberInitializer()) - continue; - if (Init->getMember() == Field) { - HasInitAlready = true; - if (isa(Init->getInit())) - InsertPos = Init->getRParenLoc(); - else { - ReplaceRange = Init->getInit()->getSourceRange(); - } - break; - } - if (Init->isMemberInitializer() && - Index < Init->getMember()->getFieldIndex()) { - InsertPos = Init->getSourceLocation(); - // There are initializers after the one we are inserting, so add a - // comma after this insertion in order to not break anything. - AddComma = true; - break; + if (Init->getMember() == Field) { + HasInitAlready = true; + if (isa(Init->getInit())) + InsertPos = Init->getRParenLoc(); + else { + ReplaceRange = Init->getInit()->getSourceRange(); } - LastInListInit = Init; + break; } - if (HasInitAlready) { - if (InsertPos.isValid()) - InvalidFix |= InsertPos.isMacroID(); - else - InvalidFix |= ReplaceRange.getBegin().isMacroID() || - ReplaceRange.getEnd().isMacroID(); - } else { - if (InsertPos.isInvalid()) { - if (LastInListInit) { - InsertPos = Lexer::getLocForEndOfToken( - LastInListInit->getRParenLoc(), 0, *Result.SourceManager, - getLangOpts()); - // Inserting after the last constructor initializer, so we need a - // comma. - InsertPrefix = ", "; - } else { - InsertPos = Lexer::getLocForEndOfToken( - Ctor->getTypeSourceInfo() - ->getTypeLoc() - .getAs() - .getLocalRangeEnd(), - 0, *Result.SourceManager, getLangOpts()); - - // If this is first time in the loop, there are no initializers so - // `:` declares member initialization list. If this is a - // subsequent pass then we have already inserted a `:` so continue - // with a comma. - InsertPrefix = FirstToCtorInits ? " : " : ", "; - } - } + if (Init->isMemberInitializer() && + Index < Init->getMember()->getFieldIndex()) { + InsertPos = Init->getSourceLocation(); + // There are initializers after the one we are inserting, so add a + // comma after this insertion in order to not break anything. + AddComma = true; + break; + } + LastInListInit = Init; + } + if (HasInitAlready) { + if (InsertPos.isValid()) InvalidFix |= InsertPos.isMacroID(); + else + InvalidFix |= ReplaceRange.getBegin().isMacroID() || + ReplaceRange.getEnd().isMacroID(); + } else { + if (InsertPos.isInvalid()) { + if (LastInListInit) { + InsertPos = Lexer::getLocForEndOfToken( + LastInListInit->getRParenLoc(), 0, *Result.SourceManager, + getLangOpts()); + // Inserting after the last constructor initializer, so we need a + // comma. + InsertPrefix = ", "; + } else { + InsertPos = Lexer::getLocForEndOfToken( + Ctor->getTypeSourceInfo() + ->getTypeLoc() + .getAs() + .getLocalRangeEnd(), + 0, *Result.SourceManager, getLangOpts()); + + // If this is first time in the loop, there are no initializers so + // `:` declares member initialization list. If this is a + // subsequent pass then we have already inserted a `:` so continue + // with a comma. + InsertPrefix = FirstToCtorInits ? " : " : ", "; + } } + InvalidFix |= InsertPos.isMacroID(); + } - SourceLocation SemiColonEnd; - if (auto NextToken = Lexer::findNextToken( - S->getEndLoc(), *Result.SourceManager, getLangOpts())) - SemiColonEnd = NextToken->getEndLoc(); + SourceLocation SemiColonEnd; + if (auto NextToken = Lexer::findNextToken( + S->getEndLoc(), *Result.SourceManager, getLangOpts())) + SemiColonEnd = NextToken->getEndLoc(); + else + InvalidFix = true; + + auto Diag = diag(S->getBeginLoc(), "%0 should be initialized in a member" + " initializer of the constructor") + << Field; + if (InvalidFix) + continue; + StringRef NewInit = Lexer::getSourceText( + CharSourceRange(InitValue->getSourceRange(), true), + *Result.SourceManager, getLangOpts()); + if (HasInitAlready) { + if (InsertPos.isValid()) + Diag << FixItHint::CreateInsertion(InsertPos, NewInit); else - InvalidFix = true; - - auto Diag = - diag(S->getBeginLoc(), "%0 should be initialized in a member" - " initializer of the constructor") - << Field; - if (InvalidFix) - continue; - StringRef NewInit = Lexer::getSourceText( - CharSourceRange(InitValue->getSourceRange(), true), - *Result.SourceManager, getLangOpts()); - if (HasInitAlready) { - if (InsertPos.isValid()) - Diag << FixItHint::CreateInsertion(InsertPos, NewInit); - else - Diag << FixItHint::CreateReplacement(ReplaceRange, NewInit); - } else { - SmallString<128> Insertion({InsertPrefix, Field->getName(), "(", - NewInit, AddComma ? "), " : ")"}); - Diag << FixItHint::CreateInsertion(InsertPos, Insertion, - FirstToCtorInits); - FirstToCtorInits = areDiagsSelfContained(); - } - Diag << FixItHint::CreateRemoval( - CharSourceRange::getCharRange(S->getBeginLoc(), SemiColonEnd)); + Diag << FixItHint::CreateReplacement(ReplaceRange, NewInit); + } else { + SmallString<128> Insertion({InsertPrefix, Field->getName(), "(", + NewInit, AddComma ? "), " : ")"}); + Diag << FixItHint::CreateInsertion(InsertPos, Insertion, + FirstToCtorInits); + FirstToCtorInits = areDiagsSelfContained(); } + Diag << FixItHint::CreateRemoval( + CharSourceRange::getCharRange(S->getBeginLoc(), SemiColonEnd)); } } } diff --git a/clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeConstCastCheck.cpp b/clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeConstCastCheck.cpp index ef803ab85fa08..8c44c1bfb62b6 100644 --- a/clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeConstCastCheck.cpp +++ b/clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeConstCastCheck.cpp @@ -14,13 +14,60 @@ using namespace clang::ast_matchers; namespace clang::tidy::cppcoreguidelines { +static bool hasConstQualifier(QualType Type) { + const QualType PtrType = Type->getPointeeType(); + if (!PtrType.isNull()) + return hasConstQualifier(PtrType); + + return Type.isConstQualified(); +} + +static bool hasVolatileQualifier(QualType Type) { + const QualType PtrType = Type->getPointeeType(); + if (!PtrType.isNull()) + return hasVolatileQualifier(PtrType); + return Type.isVolatileQualified(); +} + +ProTypeConstCastCheck::ProTypeConstCastCheck(StringRef Name, + ClangTidyContext *Context) + : ClangTidyCheck(Name, Context), + StrictMode(Options.getLocalOrGlobal("StrictMode", false)) {} + +void ProTypeConstCastCheck::storeOptions(ClangTidyOptions::OptionMap &Opts) { + Options.store(Opts, "StrictMode", StrictMode); +} + void ProTypeConstCastCheck::registerMatchers(MatchFinder *Finder) { Finder->addMatcher(cxxConstCastExpr().bind("cast"), this); } void ProTypeConstCastCheck::check(const MatchFinder::MatchResult &Result) { const auto *MatchedCast = Result.Nodes.getNodeAs("cast"); - diag(MatchedCast->getOperatorLoc(), "do not use const_cast"); + if (StrictMode) { + diag(MatchedCast->getOperatorLoc(), "do not use const_cast"); + return; + } + + const QualType TargetType = MatchedCast->getType().getCanonicalType(); + const QualType SourceType = + MatchedCast->getSubExpr()->getType().getCanonicalType(); + + const bool RemovingConst = + hasConstQualifier(SourceType) && !hasConstQualifier(TargetType); + const bool RemovingVolatile = + hasVolatileQualifier(SourceType) && !hasVolatileQualifier(TargetType); + + if (!RemovingConst && !RemovingVolatile) { + // Cast is doing nothing. + return; + } + + diag(MatchedCast->getOperatorLoc(), + "do not use const_cast to remove%select{| const}0%select{| " + "and}2%select{| volatile}1 qualifier") + << RemovingConst << RemovingVolatile + << (RemovingConst && RemovingVolatile); } } // namespace clang::tidy::cppcoreguidelines diff --git a/clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeConstCastCheck.h b/clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeConstCastCheck.h index f7ae9bbb60dcd..8d93633a321b5 100644 --- a/clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeConstCastCheck.h +++ b/clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeConstCastCheck.h @@ -13,19 +13,25 @@ namespace clang::tidy::cppcoreguidelines { -/// This check flags all instances of const_cast +/// Imposes limitations on the use of const_cast within C++ code. /// /// For the user-facing documentation see: /// http://clang.llvm.org/extra/clang-tidy/checks/cppcoreguidelines/pro-type-const-cast.html class ProTypeConstCastCheck : public ClangTidyCheck { public: - ProTypeConstCastCheck(StringRef Name, ClangTidyContext *Context) - : ClangTidyCheck(Name, Context) {} + ProTypeConstCastCheck(StringRef Name, ClangTidyContext *Context); bool isLanguageVersionSupported(const LangOptions &LangOpts) const override { return LangOpts.CPlusPlus; } void registerMatchers(ast_matchers::MatchFinder *Finder) override; void check(const ast_matchers::MatchFinder::MatchResult &Result) override; + void storeOptions(ClangTidyOptions::OptionMap &Opts) override; + std::optional getCheckTraversalKind() const override { + return TK_IgnoreUnlessSpelledInSource; + } + +private: + const bool StrictMode; }; } // namespace clang::tidy::cppcoreguidelines diff --git a/clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeStaticCastDowncastCheck.cpp b/clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeStaticCastDowncastCheck.cpp index 5344d465ad1fa..2a89de27760fe 100644 --- a/clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeStaticCastDowncastCheck.cpp +++ b/clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeStaticCastDowncastCheck.cpp @@ -14,17 +14,24 @@ using namespace clang::ast_matchers; namespace clang::tidy::cppcoreguidelines { +ProTypeStaticCastDowncastCheck::ProTypeStaticCastDowncastCheck( + StringRef Name, ClangTidyContext *Context) + : ClangTidyCheck(Name, Context), + StrictMode(Options.getLocalOrGlobal("StrictMode", true)) {} + +void ProTypeStaticCastDowncastCheck::storeOptions( + ClangTidyOptions::OptionMap &Opts) { + Options.store(Opts, "StrictMode", StrictMode); +} + void ProTypeStaticCastDowncastCheck::registerMatchers(MatchFinder *Finder) { Finder->addMatcher( - cxxStaticCastExpr(unless(isInTemplateInstantiation())).bind("cast"), - this); + cxxStaticCastExpr(hasCastKind(CK_BaseToDerived)).bind("cast"), this); } void ProTypeStaticCastDowncastCheck::check( const MatchFinder::MatchResult &Result) { const auto *MatchedCast = Result.Nodes.getNodeAs("cast"); - if (MatchedCast->getCastKind() != CK_BaseToDerived) - return; QualType SourceType = MatchedCast->getSubExpr()->getType(); const auto *SourceDecl = SourceType->getPointeeCXXRecordDecl(); @@ -33,15 +40,20 @@ void ProTypeStaticCastDowncastCheck::check( if (!SourceDecl) return; - if (SourceDecl->isPolymorphic()) + if (SourceDecl->isPolymorphic()) { diag(MatchedCast->getOperatorLoc(), "do not use static_cast to downcast from a base to a derived class; " "use dynamic_cast instead") << FixItHint::CreateReplacement(MatchedCast->getOperatorLoc(), "dynamic_cast"); - else - diag(MatchedCast->getOperatorLoc(), - "do not use static_cast to downcast from a base to a derived class"); + return; + } + + if (!StrictMode) + return; + + diag(MatchedCast->getOperatorLoc(), + "do not use static_cast to downcast from a base to a derived class"); } } // namespace clang::tidy::cppcoreguidelines diff --git a/clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeStaticCastDowncastCheck.h b/clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeStaticCastDowncastCheck.h index 33ec8a071c108..b9e78a82a39f2 100644 --- a/clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeStaticCastDowncastCheck.h +++ b/clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeStaticCastDowncastCheck.h @@ -20,13 +20,19 @@ namespace clang::tidy::cppcoreguidelines { /// http://clang.llvm.org/extra/clang-tidy/checks/cppcoreguidelines/pro-type-static-cast-downcast.html class ProTypeStaticCastDowncastCheck : public ClangTidyCheck { public: - ProTypeStaticCastDowncastCheck(StringRef Name, ClangTidyContext *Context) - : ClangTidyCheck(Name, Context) {} + ProTypeStaticCastDowncastCheck(StringRef Name, ClangTidyContext *Context); bool isLanguageVersionSupported(const LangOptions &LangOpts) const override { return LangOpts.CPlusPlus; } void registerMatchers(ast_matchers::MatchFinder *Finder) override; void check(const ast_matchers::MatchFinder::MatchResult &Result) override; + void storeOptions(ClangTidyOptions::OptionMap &Opts) override; + std::optional getCheckTraversalKind() const override { + return TK_IgnoreUnlessSpelledInSource; + } + +private: + const bool StrictMode; }; } // namespace clang::tidy::cppcoreguidelines diff --git a/clang-tools-extra/clang-tidy/cppcoreguidelines/RvalueReferenceParamNotMovedCheck.cpp b/clang-tools-extra/clang-tidy/cppcoreguidelines/RvalueReferenceParamNotMovedCheck.cpp index 88b00dc17470f..7db9e29e8fd0e 100644 --- a/clang-tools-extra/clang-tidy/cppcoreguidelines/RvalueReferenceParamNotMovedCheck.cpp +++ b/clang-tools-extra/clang-tidy/cppcoreguidelines/RvalueReferenceParamNotMovedCheck.cpp @@ -62,23 +62,28 @@ void RvalueReferenceParamNotMovedCheck::registerMatchers(MatchFinder *Finder) { anyOf(isConstQualified(), substTemplateTypeParmType()))))), optionally(hasType(qualType(references(templateTypeParmType( hasDeclaration(templateTypeParmDecl().bind("template-type"))))))), - anyOf(hasAncestor(cxxConstructorDecl( - ToParam, isDefinition(), unless(isMoveConstructor()), - optionally(hasDescendant(MoveCallMatcher)))), - hasAncestor(functionDecl( - unless(cxxConstructorDecl()), ToParam, - unless(cxxMethodDecl(isMoveAssignmentOperator())), - hasBody(optionally(hasDescendant(MoveCallMatcher))))))), + hasDeclContext( + functionDecl( + isDefinition(), unless(isDeleted()), unless(isDefaulted()), + unless(cxxConstructorDecl(isMoveConstructor())), + unless(cxxMethodDecl(isMoveAssignmentOperator())), ToParam, + anyOf(cxxConstructorDecl( + optionally(hasDescendant(MoveCallMatcher))), + functionDecl(unless(cxxConstructorDecl()), + optionally(hasBody( + hasDescendant(MoveCallMatcher)))))) + .bind("func"))), this); } void RvalueReferenceParamNotMovedCheck::check( const MatchFinder::MatchResult &Result) { const auto *Param = Result.Nodes.getNodeAs("param"); + const auto *Function = Result.Nodes.getNodeAs("func"); const auto *TemplateType = Result.Nodes.getNodeAs("template-type"); - if (!Param) + if (!Param || !Function) return; if (IgnoreUnnamedParams && Param->getName().empty()) @@ -87,10 +92,6 @@ void RvalueReferenceParamNotMovedCheck::check( if (!Param->isUsed() && Param->hasAttr()) return; - const auto *Function = dyn_cast(Param->getDeclContext()); - if (!Function) - return; - if (IgnoreNonDeducedTemplateTypes && TemplateType) return; diff --git a/clang-tools-extra/clang-tidy/misc/UnusedUsingDeclsCheck.cpp b/clang-tools-extra/clang-tidy/misc/UnusedUsingDeclsCheck.cpp index 14b6aca6f3b8f..051375263e53c 100644 --- a/clang-tools-extra/clang-tidy/misc/UnusedUsingDeclsCheck.cpp +++ b/clang-tools-extra/clang-tidy/misc/UnusedUsingDeclsCheck.cpp @@ -8,6 +8,7 @@ #include "UnusedUsingDeclsCheck.h" #include "clang/AST/ASTContext.h" +#include "clang/AST/Decl.h" #include "clang/ASTMatchers/ASTMatchFinder.h" #include "clang/Lex/Lexer.h" @@ -71,6 +72,10 @@ void UnusedUsingDeclsCheck::registerMatchers(MatchFinder *Finder) { templateArgument().bind("used")))), this); Finder->addMatcher(userDefinedLiteral().bind("used"), this); + Finder->addMatcher( + loc(elaboratedType(unless(hasQualifier(nestedNameSpecifier())), + hasUnqualifiedDesugaredType(type().bind("usedType")))), + this); // Cases where we can identify the UsingShadowDecl directly, rather than // just its target. // FIXME: cover more cases in this way, as the AST supports it. @@ -145,6 +150,12 @@ void UnusedUsingDeclsCheck::check(const MatchFinder::MatchResult &Result) { return; } + if (const auto *T = Result.Nodes.getNodeAs("usedType")) { + if (const auto *ND = T->getAsTagDecl()) + RemoveNamedDecl(ND); + return; + } + if (const auto *UsedShadow = Result.Nodes.getNodeAs("usedShadow")) { removeFromFoundDecls(UsedShadow->getTargetDecl()); diff --git a/clang-tools-extra/clang-tidy/modernize/AvoidBindCheck.cpp b/clang-tools-extra/clang-tidy/modernize/AvoidBindCheck.cpp index 4628c09f19699..2a54eaddccb15 100644 --- a/clang-tools-extra/clang-tidy/modernize/AvoidBindCheck.cpp +++ b/clang-tools-extra/clang-tidy/modernize/AvoidBindCheck.cpp @@ -96,6 +96,7 @@ struct CallableInfo { std::string UsageIdentifier; StringRef CaptureInitializer; const FunctionDecl *Decl = nullptr; + bool DoesReturn = false; }; struct LambdaProperties { @@ -554,6 +555,10 @@ getLambdaProperties(const MatchFinder::MatchResult &Result) { LP.Callable.Materialization = getCallableMaterialization(Result); LP.Callable.Decl = getCallMethodDecl(Result, LP.Callable.Type, LP.Callable.Materialization); + if (LP.Callable.Decl) + if (const Type *ReturnType = + LP.Callable.Decl->getReturnType().getCanonicalType().getTypePtr()) + LP.Callable.DoesReturn = !ReturnType->isVoidType(); LP.Callable.SourceTokens = getSourceTextForExpr(Result, CalleeExpr); if (LP.Callable.Materialization == CMK_VariableRef) { LP.Callable.CE = CE_Var; @@ -672,15 +677,20 @@ void AvoidBindCheck::check(const MatchFinder::MatchResult &Result) { addPlaceholderArgs(LP, Stream, PermissiveParameterList); + Stream << " { "; + + if (LP.Callable.DoesReturn) { + Stream << "return "; + } + if (LP.Callable.Type == CT_Function) { StringRef SourceTokens = LP.Callable.SourceTokens; SourceTokens.consume_front("&"); - Stream << " { return " << SourceTokens; + Stream << SourceTokens; } else if (LP.Callable.Type == CT_MemberFunction) { const auto *MethodDecl = dyn_cast(LP.Callable.Decl); const BindArgument &ObjPtr = FunctionCallArgs.front(); - Stream << " { "; if (!isa(ignoreTemporariesAndPointers(ObjPtr.E))) { Stream << ObjPtr.UsageIdentifier; Stream << "->"; @@ -688,7 +698,6 @@ void AvoidBindCheck::check(const MatchFinder::MatchResult &Result) { Stream << MethodDecl->getName(); } else { - Stream << " { return "; switch (LP.Callable.CE) { case CE_Var: if (LP.Callable.UsageIdentifier != LP.Callable.CaptureIdentifier) { diff --git a/clang-tools-extra/clang-tidy/readability/AvoidConstParamsInDecls.cpp b/clang-tools-extra/clang-tidy/readability/AvoidConstParamsInDecls.cpp index 6476f1d7fdf2b..24cbbd8bc60a2 100644 --- a/clang-tools-extra/clang-tidy/readability/AvoidConstParamsInDecls.cpp +++ b/clang-tools-extra/clang-tidy/readability/AvoidConstParamsInDecls.cpp @@ -21,6 +21,24 @@ SourceRange getTypeRange(const ParmVarDecl &Param) { return {Param.getBeginLoc(), Param.getLocation().getLocWithOffset(-1)}; } +// Finds the location of the qualifying `const` token in the `ParmValDecl`'s +// return type. Returns `std::nullopt` when the parm type is not +// `const`-qualified like when the type is an alias or a macro. +static std::optional +findConstToRemove(const ParmVarDecl &Param, + const MatchFinder::MatchResult &Result) { + + CharSourceRange FileRange = Lexer::makeFileCharRange( + CharSourceRange::getTokenRange(getTypeRange(Param)), + *Result.SourceManager, Result.Context->getLangOpts()); + + if (FileRange.isInvalid()) + return std::nullopt; + + return tidy::utils::lexer::getQualifyingToken( + tok::kw_const, FileRange, *Result.Context, *Result.SourceManager); +} + } // namespace void AvoidConstParamsInDecls::storeOptions(ClangTidyOptions::OptionMap &Opts) { @@ -30,11 +48,10 @@ void AvoidConstParamsInDecls::storeOptions(ClangTidyOptions::OptionMap &Opts) { void AvoidConstParamsInDecls::registerMatchers(MatchFinder *Finder) { const auto ConstParamDecl = parmVarDecl(hasType(qualType(isConstQualified()))).bind("param"); - Finder->addMatcher( - functionDecl(unless(isDefinition()), - has(typeLoc(forEach(ConstParamDecl)))) - .bind("func"), - this); + Finder->addMatcher(functionDecl(unless(isDefinition()), + has(typeLoc(forEach(ConstParamDecl)))) + .bind("func"), + this); } void AvoidConstParamsInDecls::check(const MatchFinder::MatchResult &Result) { @@ -50,7 +67,10 @@ void AvoidConstParamsInDecls::check(const MatchFinder::MatchResult &Result) { return; } - auto Diag = diag(Param->getBeginLoc(), + const auto Tok = findConstToRemove(*Param, Result); + const auto ConstLocation = Tok ? Tok->getLocation() : Param->getBeginLoc(); + + auto Diag = diag(ConstLocation, "parameter %0 is const-qualified in the function " "declaration; const-qualification of parameters only has an " "effect in function definitions"); @@ -70,18 +90,9 @@ void AvoidConstParamsInDecls::check(const MatchFinder::MatchResult &Result) { // from a macro. return; } - - CharSourceRange FileRange = Lexer::makeFileCharRange( - CharSourceRange::getTokenRange(getTypeRange(*Param)), - *Result.SourceManager, getLangOpts()); - - if (!FileRange.isValid()) - return; - - auto Tok = tidy::utils::lexer::getQualifyingToken( - tok::kw_const, FileRange, *Result.Context, *Result.SourceManager); if (!Tok) return; + Diag << FixItHint::CreateRemoval( CharSourceRange::getTokenRange(Tok->getLocation(), Tok->getLocation())); } diff --git a/clang-tools-extra/clang-tidy/tool/clang-tidy-diff.py b/clang-tools-extra/clang-tidy/tool/clang-tidy-diff.py index 06f2cebe7c09e..8817e2914f6e2 100755 --- a/clang-tools-extra/clang-tidy/tool/clang-tidy-diff.py +++ b/clang-tools-extra/clang-tidy/tool/clang-tidy-diff.py @@ -180,10 +180,21 @@ def main(): if yaml: parser.add_argument( "-export-fixes", - metavar="FILE", + metavar="FILE_OR_DIRECTORY", dest="export_fixes", - help="Create a yaml file to store suggested fixes in, " - "which can be applied with clang-apply-replacements.", + help="A directory or a yaml file to store suggested fixes in, " + "which can be applied with clang-apply-replacements. If the " + "parameter is a directory, the fixes of each compilation unit are " + "stored in individual yaml files in the directory.", + ) + else: + parser.add_argument( + "-export-fixes", + metavar="DIRECTORY", + dest="export_fixes", + help="A directory to store suggested fixes in, which can be applied " + "with clang-apply-replacements. The fixes of each compilation unit are " + "stored in individual yaml files in the directory.", ) parser.add_argument( "-extra-arg", @@ -258,9 +269,30 @@ def main(): max_task_count = multiprocessing.cpu_count() max_task_count = min(len(lines_by_file), max_task_count) - tmpdir = None - if yaml and args.export_fixes: - tmpdir = tempfile.mkdtemp() + combine_fixes = False + export_fixes_dir = None + delete_fixes_dir = False + if args.export_fixes is not None: + # if a directory is given, create it if it does not exist + if args.export_fixes.endswith(os.path.sep) and not os.path.isdir( + args.export_fixes + ): + os.makedirs(args.export_fixes) + + if not os.path.isdir(args.export_fixes): + if not yaml: + raise RuntimeError( + "Cannot combine fixes in one yaml file. Either install PyYAML or specify an output directory." + ) + + combine_fixes = True + + if os.path.isdir(args.export_fixes): + export_fixes_dir = args.export_fixes + + if combine_fixes: + export_fixes_dir = tempfile.mkdtemp() + delete_fixes_dir = True # Tasks for clang-tidy. task_queue = queue.Queue(max_task_count) @@ -302,10 +334,10 @@ def main(): # Run clang-tidy on files containing changes. command = [args.clang_tidy_binary] command.append("-line-filter=" + line_filter_json) - if yaml and args.export_fixes: + if args.export_fixes is not None: # Get a temporary file. We immediately close the handle so clang-tidy can # overwrite it. - (handle, tmp_name) = tempfile.mkstemp(suffix=".yaml", dir=tmpdir) + (handle, tmp_name) = tempfile.mkstemp(suffix=".yaml", dir=export_fixes_dir) os.close(handle) command.append("-export-fixes=" + tmp_name) command.extend(common_clang_tidy_args) @@ -324,17 +356,17 @@ def main(): if failed_files: return_code = 1 - if yaml and args.export_fixes: + if combine_fixes: print("Writing fixes to " + args.export_fixes + " ...") try: - merge_replacement_files(tmpdir, args.export_fixes) + merge_replacement_files(export_fixes_dir, args.export_fixes) except: sys.stderr.write("Error exporting fixes.\n") traceback.print_exc() return_code = 1 - if tmpdir: - shutil.rmtree(tmpdir) + if delete_fixes_dir: + shutil.rmtree(export_fixes_dir) sys.exit(return_code) diff --git a/clang-tools-extra/clang-tidy/tool/run-clang-tidy.py b/clang-tools-extra/clang-tidy/tool/run-clang-tidy.py index 312d9241cfa57..179759216196f 100755 --- a/clang-tools-extra/clang-tidy/tool/run-clang-tidy.py +++ b/clang-tools-extra/clang-tidy/tool/run-clang-tidy.py @@ -308,10 +308,21 @@ def main(): if yaml: parser.add_argument( "-export-fixes", - metavar="filename", + metavar="file_or_directory", dest="export_fixes", - help="Create a yaml file to store suggested fixes in, " - "which can be applied with clang-apply-replacements.", + help="A directory or a yaml file to store suggested fixes in, " + "which can be applied with clang-apply-replacements. If the " + "parameter is a directory, the fixes of each compilation unit are " + "stored in individual yaml files in the directory.", + ) + else: + parser.add_argument( + "-export-fixes", + metavar="directory", + dest="export_fixes", + help="A directory to store suggested fixes in, which can be applied " + "with clang-apply-replacements. The fixes of each compilation unit are " + "stored in individual yaml files in the directory.", ) parser.add_argument( "-j", @@ -384,14 +395,35 @@ def main(): clang_tidy_binary = find_binary(args.clang_tidy_binary, "clang-tidy", build_path) - tmpdir = None if args.fix: clang_apply_replacements_binary = find_binary( args.clang_apply_replacements_binary, "clang-apply-replacements", build_path ) - if args.fix or (yaml and args.export_fixes): - tmpdir = tempfile.mkdtemp() + combine_fixes = False + export_fixes_dir = None + delete_fixes_dir = False + if args.export_fixes is not None: + # if a directory is given, create it if it does not exist + if args.export_fixes.endswith(os.path.sep) and not os.path.isdir( + args.export_fixes + ): + os.makedirs(args.export_fixes) + + if not os.path.isdir(args.export_fixes): + if not yaml: + raise RuntimeError( + "Cannot combine fixes in one yaml file. Either install PyYAML or specify an output directory." + ) + + combine_fixes = True + + if os.path.isdir(args.export_fixes): + export_fixes_dir = args.export_fixes + + if export_fixes_dir is None and (args.fix or combine_fixes): + export_fixes_dir = tempfile.mkdtemp() + delete_fixes_dir = True try: invocation = get_tidy_invocation( @@ -450,7 +482,7 @@ def main(): args=( args, clang_tidy_binary, - tmpdir, + export_fixes_dir, build_path, task_queue, lock, @@ -474,14 +506,14 @@ def main(): # This is a sad hack. Unfortunately subprocess goes # bonkers with ctrl-c and we start forking merrily. print("\nCtrl-C detected, goodbye.") - if tmpdir: - shutil.rmtree(tmpdir) + if delete_fixes_dir: + shutil.rmtree(export_fixes_dir) os.kill(0, 9) - if yaml and args.export_fixes: + if combine_fixes: print("Writing fixes to " + args.export_fixes + " ...") try: - merge_replacement_files(tmpdir, args.export_fixes) + merge_replacement_files(export_fixes_dir, args.export_fixes) except: print("Error exporting fixes.\n", file=sys.stderr) traceback.print_exc() @@ -490,14 +522,14 @@ def main(): if args.fix: print("Applying fixes ...") try: - apply_fixes(args, clang_apply_replacements_binary, tmpdir) + apply_fixes(args, clang_apply_replacements_binary, export_fixes_dir) except: print("Error applying fixes.\n", file=sys.stderr) traceback.print_exc() return_code = 1 - if tmpdir: - shutil.rmtree(tmpdir) + if delete_fixes_dir: + shutil.rmtree(export_fixes_dir) sys.exit(return_code) diff --git a/clang-tools-extra/clangd/Config.h b/clang-tools-extra/clangd/Config.h index daae8d1c0c833..4371c80a6c587 100644 --- a/clang-tools-extra/clangd/Config.h +++ b/clang-tools-extra/clangd/Config.h @@ -93,6 +93,7 @@ struct Config { Strict, None, }; + enum class FastCheckPolicy { Strict, Loose, None }; /// Controls warnings and errors when parsing code. struct { bool SuppressAll = false; @@ -103,6 +104,7 @@ struct Config { // A comma-separated list of globs specify which clang-tidy checks to run. std::string Checks; llvm::StringMap CheckOptions; + FastCheckPolicy FastCheckFilter = FastCheckPolicy::Strict; } ClangTidy; IncludesPolicy UnusedIncludes = IncludesPolicy::Strict; diff --git a/clang-tools-extra/clangd/ConfigCompile.cpp b/clang-tools-extra/clangd/ConfigCompile.cpp index d4ff7ae3181bc..0c9fc27643be8 100644 --- a/clang-tools-extra/clangd/ConfigCompile.cpp +++ b/clang-tools-extra/clangd/ConfigCompile.cpp @@ -324,11 +324,11 @@ struct FragmentCompiler { void compile(Fragment::IndexBlock &&F) { if (F.Background) { - if (auto Val = compileEnum("Background", - **F.Background) - .map("Build", Config::BackgroundPolicy::Build) - .map("Skip", Config::BackgroundPolicy::Skip) - .value()) + if (auto Val = + compileEnum("Background", *F.Background) + .map("Build", Config::BackgroundPolicy::Build) + .map("Skip", Config::BackgroundPolicy::Skip) + .value()) Out.Apply.push_back( [Val](const Params &, Config &C) { C.Index.Background = *Val; }); } @@ -494,11 +494,31 @@ struct FragmentCompiler { diag(Error, "Invalid clang-tidy check name", Arg.Range); return; } - if (!Str.contains('*') && !isRegisteredTidyCheck(Str)) { - diag(Warning, - llvm::formatv("clang-tidy check '{0}' was not found", Str).str(), - Arg.Range); - return; + if (!Str.contains('*')) { + if (!isRegisteredTidyCheck(Str)) { + diag(Warning, + llvm::formatv("clang-tidy check '{0}' was not found", Str).str(), + Arg.Range); + return; + } + auto Fast = isFastTidyCheck(Str); + if (!Fast.has_value()) { + diag(Warning, + llvm::formatv( + "Latency of clang-tidy check '{0}' is not known. " + "It will only run if ClangTidy.FastCheckFilter is Loose or None", + Str) + .str(), + Arg.Range); + } else if (!*Fast) { + diag(Warning, + llvm::formatv( + "clang-tidy check '{0}' is slow. " + "It will only run if ClangTidy.FastCheckFilter is None", + Str) + .str(), + Arg.Range); + } } CurSpec += ','; if (!IsPositive) @@ -534,6 +554,16 @@ struct FragmentCompiler { StringPair.first, StringPair.second); }); } + if (F.FastCheckFilter.has_value()) + if (auto Val = compileEnum("FastCheckFilter", + *F.FastCheckFilter) + .map("Strict", Config::FastCheckPolicy::Strict) + .map("Loose", Config::FastCheckPolicy::Loose) + .map("None", Config::FastCheckPolicy::None) + .value()) + Out.Apply.push_back([Val](const Params &, Config &C) { + C.Diagnostics.ClangTidy.FastCheckFilter = *Val; + }); } void compile(Fragment::DiagnosticsBlock::IncludesBlock &&F) { diff --git a/clang-tools-extra/clangd/ConfigFragment.h b/clang-tools-extra/clangd/ConfigFragment.h index a59d4124b0828..7fa61108c78a0 100644 --- a/clang-tools-extra/clangd/ConfigFragment.h +++ b/clang-tools-extra/clangd/ConfigFragment.h @@ -277,6 +277,13 @@ struct Fragment { /// readability-braces-around-statements.ShortStatementLines: 2 std::vector, Located>> CheckOptions; + + /// Whether to run checks that may slow down clangd. + /// Strict: Run only checks measured to be fast. (Default) + /// This excludes recently-added checks we have not timed yet. + /// Loose: Run checks unless they are known to be slow. + /// None: Run checks regardless of their speed. + std::optional> FastCheckFilter; }; ClangTidyBlock ClangTidy; }; diff --git a/clang-tools-extra/clangd/ConfigYAML.cpp b/clang-tools-extra/clangd/ConfigYAML.cpp index cf3cec472bf8a..ce09af819247a 100644 --- a/clang-tools-extra/clangd/ConfigYAML.cpp +++ b/clang-tools-extra/clangd/ConfigYAML.cpp @@ -156,6 +156,10 @@ class Parser { }); CheckOptDict.parse(N); }); + Dict.handle("FastCheckFilter", [&](Node &N) { + if (auto FastCheckFilter = scalarValue(N, "FastCheckFilter")) + F.FastCheckFilter = *FastCheckFilter; + }); Dict.parse(N); } diff --git a/clang-tools-extra/clangd/FindTarget.cpp b/clang-tools-extra/clangd/FindTarget.cpp index a766122ad3dee..839cf6332fe8b 100644 --- a/clang-tools-extra/clangd/FindTarget.cpp +++ b/clang-tools-extra/clangd/FindTarget.cpp @@ -1131,7 +1131,7 @@ class ExplicitReferenceCollector void reportReference(ReferenceLoc &&Ref, DynTypedNode N) { // Strip null targets that can arise from invalid code. // (This avoids having to check for null everywhere we insert) - llvm::erase_value(Ref.Targets, nullptr); + llvm::erase(Ref.Targets, nullptr); // Our promise is to return only references from the source code. If we lack // location information, skip these nodes. // Normally this should not happen in practice, unless there are bugs in the diff --git a/clang-tools-extra/clangd/Hover.cpp b/clang-tools-extra/clangd/Hover.cpp index 0ec85fc24df15..933c69294b409 100644 --- a/clang-tools-extra/clangd/Hover.cpp +++ b/clang-tools-extra/clangd/Hover.cpp @@ -1001,6 +1001,8 @@ void addLayoutInfo(const NamedDecl &ND, HoverInfo &HI) { if (auto *RD = llvm::dyn_cast(&ND)) { if (auto Size = Ctx.getTypeSizeInCharsIfKnown(RD->getTypeForDecl())) HI.Size = Size->getQuantity() * 8; + if (!RD->isDependentType() && RD->isCompleteDefinition()) + HI.Align = Ctx.getTypeAlign(RD->getTypeForDecl()); return; } @@ -1009,6 +1011,7 @@ void addLayoutInfo(const NamedDecl &ND, HoverInfo &HI) { if (Record) Record = Record->getDefinition(); if (Record && !Record->isInvalidDecl() && !Record->isDependentType()) { + HI.Align = Ctx.getTypeAlign(FD->getType()); const ASTRecordLayout &Layout = Ctx.getASTRecordLayout(Record); HI.Offset = Layout.getFieldOffset(FD->getFieldIndex()); if (FD->isBitField()) @@ -1487,6 +1490,8 @@ markup::Document HoverInfo::present() const { P.appendText( llvm::formatv(" (+{0} padding)", formatSize(*Padding)).str()); } + if (Align) + P.appendText(", alignment " + formatSize(*Align)); } if (CalleeArgInfo) { diff --git a/clang-tools-extra/clangd/Hover.h b/clang-tools-extra/clangd/Hover.h index 6a61100912918..fe689de44732e 100644 --- a/clang-tools-extra/clangd/Hover.h +++ b/clang-tools-extra/clangd/Hover.h @@ -97,6 +97,8 @@ struct HoverInfo { std::optional Offset; /// Contains the padding following a field within the enclosing class. std::optional Padding; + /// Contains the alignment of fields and types where it's interesting. + std::optional Align; // Set when symbol is inside function call. Contains information extracted // from the callee definition about the argument this is passed as. std::optional CalleeArgInfo; diff --git a/clang-tools-extra/clangd/InlayHints.cpp b/clang-tools-extra/clangd/InlayHints.cpp index e6e5e11b889bf..3da047f954213 100644 --- a/clang-tools-extra/clangd/InlayHints.cpp +++ b/clang-tools-extra/clangd/InlayHints.cpp @@ -528,6 +528,13 @@ static FunctionProtoTypeLoc getPrototypeLoc(Expr *Fn) { return {}; } +ArrayRef +maybeDropCxxExplicitObjectParameters(ArrayRef Params) { + if (!Params.empty() && Params.front()->isExplicitObjectParameter()) + Params = Params.drop_front(1); + return Params; +} + struct Callee { // Only one of Decl or Loc is set. // Loc is for calls through function pointers. @@ -614,15 +621,21 @@ class InlayHintVisitor : public RecursiveASTVisitor { // argument expressions present in the function call syntax preceded by the // implied object argument (E). // - // However, we don't have the implied object argument for static - // operator() per clang::Sema::BuildCallToObjectOfClassType. + // As well as the provision from P0847R7 Deducing This [expr.call]p7: + // ...If the function is an explicit object member function and there is an + // implied object argument ([over.call.func]), the list of provided + // arguments is preceded by the implied object argument for the purposes of + // this correspondence... + // + // However, we don't have the implied object argument + // for static operator() per clang::Sema::BuildCallToObjectOfClassType. llvm::ArrayRef Args = {E->getArgs(), E->getNumArgs()}; - if (IsFunctor) - // We don't have the implied object argument through - // a function pointer either. - if (const CXXMethodDecl *Method = - dyn_cast_or_null(Callee.Decl); - Method && Method->isInstance()) + // We don't have the implied object argument through a function pointer + // either. + if (const CXXMethodDecl *Method = + dyn_cast_or_null(Callee.Decl)) + if (Method->isInstance() && + (IsFunctor || Method->hasCXXExplicitFunctionObjectParameter())) Args = Args.drop_front(1); processCall(Callee, Args); return true; @@ -849,15 +862,18 @@ class InlayHintVisitor : public RecursiveASTVisitor { if (Ctor->isCopyOrMoveConstructor()) return; - auto Params = - Callee.Decl ? Callee.Decl->parameters() : Callee.Loc.getParams(); - + ArrayRef Params, ForwardedParams; // Resolve parameter packs to their forwarded parameter - SmallVector ForwardedParams; - if (Callee.Decl) - ForwardedParams = resolveForwardingParameters(Callee.Decl); - else + SmallVector ForwardedParamsStorage; + if (Callee.Decl) { + Params = maybeDropCxxExplicitObjectParameters(Callee.Decl->parameters()); + ForwardedParamsStorage = resolveForwardingParameters(Callee.Decl); + ForwardedParams = + maybeDropCxxExplicitObjectParameters(ForwardedParamsStorage); + } else { + Params = maybeDropCxxExplicitObjectParameters(Callee.Loc.getParams()); ForwardedParams = {Params.begin(), Params.end()}; + } NameVec ParameterNames = chooseParameterNames(ForwardedParams); @@ -1018,7 +1034,7 @@ class InlayHintVisitor : public RecursiveASTVisitor { return {}; } - NameVec chooseParameterNames(SmallVector Parameters) { + NameVec chooseParameterNames(ArrayRef Parameters) { NameVec ParameterNames; for (const auto *P : Parameters) { if (isExpandedFromParameterPack(P)) { diff --git a/clang-tools-extra/clangd/ParsedAST.cpp b/clang-tools-extra/clangd/ParsedAST.cpp index d033d29e901fa..edd0f77b1031e 100644 --- a/clang-tools-extra/clangd/ParsedAST.cpp +++ b/clang-tools-extra/clangd/ParsedAST.cpp @@ -381,6 +381,20 @@ std::vector getIncludeCleanerDiags(ParsedAST &AST, llvm::StringRef Code) { Cfg.Diagnostics.Includes.IgnoreHeader); } +tidy::ClangTidyCheckFactories +filterFastTidyChecks(const tidy::ClangTidyCheckFactories &All, + Config::FastCheckPolicy Policy) { + if (Policy == Config::FastCheckPolicy::None) + return All; + bool AllowUnknown = Policy == Config::FastCheckPolicy::Loose; + tidy::ClangTidyCheckFactories Fast; + for (const auto &Factory : All) { + if (isFastTidyCheck(Factory.getKey()).value_or(AllowUnknown)) + Fast.registerCheckFactory(Factory.first(), Factory.second); + } + return Fast; +} + } // namespace std::optional @@ -390,6 +404,7 @@ ParsedAST::build(llvm::StringRef Filename, const ParseInputs &Inputs, std::shared_ptr Preamble) { trace::Span Tracer("BuildAST"); SPAN_ATTACH(Tracer, "File", Filename); + const Config &Cfg = Config::current(); auto VFS = Inputs.TFS->view(Inputs.CompileCommand.Directory); if (Preamble && Preamble->StatCache) @@ -520,19 +535,21 @@ ParsedAST::build(llvm::StringRef Filename, const ParseInputs &Inputs, // diagnostics. { trace::Span Tracer("ClangTidyInit"); - static const auto *CTFactories = [] { + static const auto *AllCTFactories = [] { auto *CTFactories = new tidy::ClangTidyCheckFactories; for (const auto &E : tidy::ClangTidyModuleRegistry::entries()) E.instantiate()->addCheckFactories(*CTFactories); return CTFactories; }(); + tidy::ClangTidyCheckFactories FastFactories = filterFastTidyChecks( + *AllCTFactories, Cfg.Diagnostics.ClangTidy.FastCheckFilter); CTContext.emplace(std::make_unique( tidy::ClangTidyGlobalOptions(), ClangTidyOpts)); CTContext->setDiagnosticsEngine(&Clang->getDiagnostics()); CTContext->setASTContext(&Clang->getASTContext()); CTContext->setCurrentFile(Filename); CTContext->setSelfContainedDiags(true); - CTChecks = CTFactories->createChecksForLanguage(&*CTContext); + CTChecks = FastFactories.createChecksForLanguage(&*CTContext); Preprocessor *PP = &Clang->getPreprocessor(); for (const auto &Check : CTChecks) { Check->registerPPCallbacks(Clang->getSourceManager(), PP, PP); @@ -554,7 +571,6 @@ ParsedAST::build(llvm::StringRef Filename, const ParseInputs &Inputs, SourceLocation()); } - const Config &Cfg = Config::current(); ASTDiags.setLevelAdjuster([&](DiagnosticsEngine::Level DiagLevel, const clang::Diagnostic &Info) { if (Cfg.Diagnostics.SuppressAll || diff --git a/clang-tools-extra/clangd/SystemIncludeExtractor.cpp b/clang-tools-extra/clangd/SystemIncludeExtractor.cpp index 74bae786425c8..a86f152c3bf36 100644 --- a/clang-tools-extra/clangd/SystemIncludeExtractor.cpp +++ b/clang-tools-extra/clangd/SystemIncludeExtractor.cpp @@ -88,12 +88,14 @@ struct DriverArgs { std::string Sysroot; std::string ISysroot; std::string Target; + std::string Stdlib; bool operator==(const DriverArgs &RHS) const { return std::tie(Driver, StandardIncludes, StandardCXXIncludes, Lang, - Sysroot, ISysroot, Target) == + Sysroot, ISysroot, Target, Stdlib) == std::tie(RHS.Driver, RHS.StandardIncludes, RHS.StandardCXXIncludes, - RHS.Lang, RHS.Sysroot, RHS.ISysroot, RHS.Target); + RHS.Lang, RHS.Sysroot, RHS.ISysroot, RHS.Target, + RHS.Stdlib); } DriverArgs(const tooling::CompileCommand &Cmd, llvm::StringRef File) { @@ -136,6 +138,13 @@ struct DriverArgs { } else if (Arg.consume_front("-target")) { if (Arg.empty() && I + 1 < E) Target = Cmd.CommandLine[I + 1]; + } else if (Arg.consume_front("--stdlib")) { + if (Arg.consume_front("=")) + Stdlib = Arg.str(); + else if (Arg.empty() && I + 1 < E) + Stdlib = Cmd.CommandLine[I + 1]; + } else if (Arg.consume_front("-stdlib=")) { + Stdlib = Arg.str(); } } @@ -175,6 +184,8 @@ struct DriverArgs { Args.append({"-isysroot", ISysroot}); if (!Target.empty()) Args.append({"-target", Target}); + if (!Stdlib.empty()) + Args.append({"--stdlib", Stdlib}); return Args; } @@ -206,6 +217,8 @@ template <> struct DenseMapInfo { Val.Lang, Val.Sysroot, Val.ISysroot, + Val.Target, + Val.Stdlib, }); } static bool isEqual(const DriverArgs &LHS, const DriverArgs &RHS) { @@ -376,8 +389,7 @@ extractSystemIncludesAndTarget(const DriverArgs &InputArgs, auto Path = llvm::StringRef(*BuiltinHeaders).trim(); if (!Path.empty() && llvm::sys::path::is_absolute(Path)) { auto Size = Info->SystemIncludes.size(); - llvm::erase_if(Info->SystemIncludes, - [&](llvm::StringRef Entry) { return Path == Entry; }); + llvm::erase(Info->SystemIncludes, Path); vlog("System includes extractor: builtin headers {0} {1}", Path, (Info->SystemIncludes.size() != Size) ? "excluded" diff --git a/clang-tools-extra/clangd/TidyProvider.cpp b/clang-tools-extra/clangd/TidyProvider.cpp index 2a6fba52e29bf..b658a80559937 100644 --- a/clang-tools-extra/clangd/TidyProvider.cpp +++ b/clang-tools-extra/clangd/TidyProvider.cpp @@ -323,5 +323,17 @@ bool isRegisteredTidyCheck(llvm::StringRef Check) { return AllChecks.contains(Check); } + +std::optional isFastTidyCheck(llvm::StringRef Check) { + static auto &Fast = *new llvm::StringMap{ +#define FAST(CHECK, TIME) {#CHECK,true}, +#define SLOW(CHECK, TIME) {#CHECK,false}, +#include "TidyFastChecks.inc" + }; + if (auto It = Fast.find(Check); It != Fast.end()) + return It->second; + return std::nullopt; +} + } // namespace clangd } // namespace clang diff --git a/clang-tools-extra/clangd/TidyProvider.h b/clang-tools-extra/clangd/TidyProvider.h index 2f31366e1c9bc..7d849d340f3aa 100644 --- a/clang-tools-extra/clangd/TidyProvider.h +++ b/clang-tools-extra/clangd/TidyProvider.h @@ -60,6 +60,10 @@ tidy::ClangTidyOptions getTidyOptionsForFile(TidyProviderRef Provider, /// \pre \p must not be empty, must not contain '*' or ',' or start with '-'. bool isRegisteredTidyCheck(llvm::StringRef Check); +/// Returns if \p Check is known-fast, known-slow, or its speed is unknown. +/// By default, only fast checks will run in clangd. +std::optional isFastTidyCheck(llvm::StringRef Check); + } // namespace clangd } // namespace clang diff --git a/clang-tools-extra/clangd/refactor/tweaks/RawStringLiteral.cpp b/clang-tools-extra/clangd/refactor/tweaks/RawStringLiteral.cpp index f5021b820f38d..5613ceacdfe1b 100644 --- a/clang-tools-extra/clangd/refactor/tweaks/RawStringLiteral.cpp +++ b/clang-tools-extra/clangd/refactor/tweaks/RawStringLiteral.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "ParsedAST.h" #include "refactor/Tweak.h" +#include "clang/AST/ASTContext.h" #include "clang/AST/Stmt.h" #include "clang/Basic/LangOptions.h" #include "clang/Basic/SourceLocation.h" @@ -43,6 +44,12 @@ class RawStringLiteral : public Tweak { REGISTER_TWEAK(RawStringLiteral) +static bool isFeatureAvailable(const ASTContext &Context) { + // Raw strings are available only for C++11 or later versions, and they are + // not available for C. + return Context.getLangOpts().CPlusPlus11; +} + static bool isNormalString(const StringLiteral &Str, SourceLocation Cursor, SourceManager &SM) { // All chunks must be normal ASCII strings, not u8"..." etc. @@ -72,6 +79,9 @@ static bool canBeRaw(llvm::StringRef Content) { } bool RawStringLiteral::prepare(const Selection &Inputs) { + if (!isFeatureAvailable(Inputs.AST->getASTContext())) { + return false; + } const SelectionTree::Node *N = Inputs.ASTSelection.commonAncestor(); if (!N) return false; diff --git a/clang-tools-extra/clangd/test/system-include-extractor.test b/clang-tools-extra/clangd/test/system-include-extractor.test index 66882e424bb92..cbb3018b2fa73 100644 --- a/clang-tools-extra/clangd/test/system-include-extractor.test +++ b/clang-tools-extra/clangd/test/system-include-extractor.test @@ -18,6 +18,7 @@ # RUN: echo '[ -z "${args##*"--sysroot /my/sysroot/path"*}" ] || exit' >> %t.dir/bin/my_driver.sh # RUN: echo '[ -z "${args##*"-isysroot /isysroot"*}" ] || exit' >> %t.dir/bin/my_driver.sh # RUN: echo '[ -z "${args##*"-target arm-linux-gnueabihf"*}" ] || exit' >> %t.dir/bin/my_driver.sh +# RUN: echo '[ -z "${args##*"--stdlib libc++"*}" ] || exit' >> %t.dir/bin/my_driver.sh # RUN: echo 'echo line to ignore >&2' >> %t.dir/bin/my_driver.sh # RUN: echo 'printf "Target: arm-linux-gnueabihf\r\n" >&2' >> %t.dir/bin/my_driver.sh # RUN: echo 'printf "#include <...> search starts here:\r\n" >&2' >> %t.dir/bin/my_driver.sh @@ -37,7 +38,7 @@ # Generate a compile_commands.json that will query the mock driver we've # created. Which should add a.h and b.h into include search path. -# RUN: echo '[{"directory": "%/t.dir", "command": "my_driver.sh the-file.cpp --target=arm-linux-gnueabihf -nostdinc --sysroot /my/sysroot/path -isysroot/isysroot", "file": "the-file.cpp"}]' > %t.dir/compile_commands.json +# RUN: echo '[{"directory": "%/t.dir", "command": "my_driver.sh the-file.cpp --target=arm-linux-gnueabihf -nostdinc --sysroot /my/sysroot/path -isysroot/isysroot -stdlib=libc++", "file": "the-file.cpp"}]' > %t.dir/compile_commands.json # RUN: sed -e "s|INPUT_DIR|%/t.dir|g" %s > %t.test.1 # On Windows, we need the URI in didOpen to look like "uri":"file:///C:/..." @@ -75,7 +76,7 @@ {"jsonrpc":"2.0","method":"exit"} # Generate a different compile_commands.json which does not point to the mock driver -# RUN: echo '[{"directory": "%/t.dir", "command": "gcc the-file.cpp --target=arm-linux-gnueabihf -nostdinc --sysroot /my/sysroot/path -isysroot/isysroot", "file": "the-file.cpp"}]' > %t.dir/compile_commands.json +# RUN: echo '[{"directory": "%/t.dir", "command": "gcc the-file.cpp --target=arm-linux-gnueabihf -nostdinc --sysroot /my/sysroot/path -isysroot/isysroot -stdlib=libc++", "file": "the-file.cpp"}]' > %t.dir/compile_commands.json # Generate a clangd config file which points to the mock driver instead # RUN: echo 'CompileFlags:' > %t.dir/.clangd diff --git a/clang-tools-extra/clangd/tool/Check.cpp b/clang-tools-extra/clangd/tool/Check.cpp index 46fcab0b69ce0..b5c4d145619df 100644 --- a/clang-tools-extra/clangd/tool/Check.cpp +++ b/clang-tools-extra/clangd/tool/Check.cpp @@ -34,6 +34,8 @@ #include "CompileCommands.h" #include "Compiler.h" #include "Config.h" +#include "ConfigFragment.h" +#include "ConfigProvider.h" #include "Diagnostics.h" #include "Feature.h" #include "GlobalCompilationDatabase.h" @@ -103,15 +105,19 @@ llvm::cl::opt CheckCompletion{ "check-completion", llvm::cl::desc("Run code-completion at each point (slow)"), llvm::cl::init(false)}; +llvm::cl::opt CheckWarnings{ + "check-warnings", + llvm::cl::desc("Print warnings as well as errors"), + llvm::cl::init(false)}; -// Print (and count) the error-level diagnostics (warnings are ignored). +// Print the diagnostics meeting severity threshold, and return count of errors. unsigned showErrors(llvm::ArrayRef Diags) { unsigned ErrCount = 0; for (const auto &D : Diags) { - if (D.Severity >= DiagnosticsEngine::Error) { + if (D.Severity >= DiagnosticsEngine::Error || CheckWarnings) elog("[{0}] Line {1}: {2}", D.Name, D.Range.start.line + 1, D.Message); + if (D.Severity >= DiagnosticsEngine::Error) ++ErrCount; - } } return ErrCount; } @@ -476,8 +482,23 @@ bool check(llvm::StringRef File, const ThreadsafeFS &TFS, } log("Testing on source file {0}", File); + class OverrideConfigProvider : public config::Provider { + std::vector + getFragments(const config::Params &, + config::DiagnosticCallback Diag) const override { + config::Fragment F; + // If we're timing clang-tidy checks, implicitly disabling the slow ones + // is counterproductive! + if (CheckTidyTime.getNumOccurrences()) + F.Diagnostics.ClangTidy.FastCheckFilter.emplace("None"); + return {std::move(F).compile(Diag)}; + } + } OverrideConfig; + auto ConfigProvider = + config::Provider::combine({Opts.ConfigProvider, &OverrideConfig}); + auto ContextProvider = ClangdServer::createConfiguredContextProvider( - Opts.ConfigProvider, nullptr); + ConfigProvider.get(), nullptr); WithContext Ctx(ContextProvider( FakeFile.empty() ? File diff --git a/clang-tools-extra/clangd/unittests/DiagnosticsTests.cpp b/clang-tools-extra/clangd/unittests/DiagnosticsTests.cpp index f9b71a32304f2..14dd1f4b3f6d5 100644 --- a/clang-tools-extra/clangd/unittests/DiagnosticsTests.cpp +++ b/clang-tools-extra/clangd/unittests/DiagnosticsTests.cpp @@ -1808,29 +1808,13 @@ TEST(ToLSPDiag, RangeIsInMain) { } TEST(ParsedASTTest, ModuleSawDiag) { - static constexpr const llvm::StringLiteral KDiagMsg = "StampedDiag"; - struct DiagModifierModule final : public FeatureModule { - struct Listener : public FeatureModule::ASTListener { - void sawDiagnostic(const clang::Diagnostic &Info, - clangd::Diag &Diag) override { - Diag.Message = KDiagMsg.str(); - } - }; - std::unique_ptr astListeners() override { - return std::make_unique(); - }; - }; - FeatureModuleSet FMS; - FMS.add(std::make_unique()); - - Annotations Code("[[test]]; /* error-ok */"); TestTU TU; - TU.Code = Code.code().str(); - TU.FeatureModules = &FMS; auto AST = TU.build(); + #if 0 EXPECT_THAT(AST.getDiagnostics(), testing::Contains(Diag(Code.range(), KDiagMsg.str()))); + #endif } TEST(Preamble, EndsOnNonEmptyLine) { diff --git a/clang-tools-extra/clangd/unittests/HoverTests.cpp b/clang-tools-extra/clangd/unittests/HoverTests.cpp index 8c88cd5257453..063a60db04406 100644 --- a/clang-tools-extra/clangd/unittests/HoverTests.cpp +++ b/clang-tools-extra/clangd/unittests/HoverTests.cpp @@ -92,6 +92,7 @@ TEST(Hover, Structured) { HI.Offset = 0; HI.Size = 8; HI.Padding = 56; + HI.Align = 8; HI.AccessSpecifier = "private"; }}, // Union field @@ -110,6 +111,7 @@ TEST(Hover, Structured) { HI.Type = "char"; HI.Size = 8; HI.Padding = 120; + HI.Align = 8; HI.AccessSpecifier = "public"; }}, // Bitfield @@ -128,6 +130,7 @@ TEST(Hover, Structured) { HI.Type = "int"; HI.Offset = 0; HI.Size = 1; + HI.Align = 32; HI.AccessSpecifier = "public"; }}, // Local to class method. @@ -192,6 +195,7 @@ TEST(Hover, Structured) { HI.Type = "char"; HI.Offset = 0; HI.Size = 8; + HI.Align = 8; HI.AccessSpecifier = "public"; }}, // Struct definition shows size. @@ -204,6 +208,7 @@ TEST(Hover, Structured) { HI.Kind = index::SymbolKind::Struct; HI.Definition = "struct X {}"; HI.Size = 8; + HI.Align = 8; }}, // Variable with template type {R"cpp( @@ -1375,6 +1380,7 @@ class Foo final {})cpp"; HI.Offset = 8; HI.Size = 1; HI.Padding = 23; + HI.Align = 8; HI.AccessSpecifier = "public"; }}}; for (const auto &Case : Cases) { @@ -1411,6 +1417,7 @@ class Foo final {})cpp"; EXPECT_EQ(H->Value, Expected.Value); EXPECT_EQ(H->Size, Expected.Size); EXPECT_EQ(H->Offset, Expected.Offset); + EXPECT_EQ(H->Align, Expected.Align); EXPECT_EQ(H->AccessSpecifier, Expected.AccessSpecifier); EXPECT_EQ(H->CalleeArgInfo, Expected.CalleeArgInfo); EXPECT_EQ(H->CallPassType, Expected.CallPassType); @@ -3448,13 +3455,14 @@ template class Foo {})", HI.Size = 32; HI.Offset = 96; HI.Padding = 32; + HI.Align = 32; }, R"(field foo Type: type (aka can_type) Value = value Offset: 12 bytes -Size: 4 bytes (+4 bytes padding) +Size: 4 bytes (+4 bytes padding), alignment 4 bytes // In test::Bar def)", @@ -3470,13 +3478,14 @@ def)", HI.Size = 25; HI.Offset = 35; HI.Padding = 4; + HI.Align = 64; }, R"(field foo Type: type (aka can_type) Value = value Offset: 4 bytes and 3 bits -Size: 25 bits (+4 bits padding) +Size: 25 bits (+4 bits padding), alignment 8 bytes // In test::Bar def)", diff --git a/clang-tools-extra/clangd/unittests/InlayHintTests.cpp b/clang-tools-extra/clangd/unittests/InlayHintTests.cpp index a8c3546eb80cc..20c1cdd985dbc 100644 --- a/clang-tools-extra/clangd/unittests/InlayHintTests.cpp +++ b/clang-tools-extra/clangd/unittests/InlayHintTests.cpp @@ -843,6 +843,34 @@ TEST(ParameterHints, FunctionCallOperator) { ExpectedHint{"a: ", "11"}, ExpectedHint{"b: ", "12"}); } +TEST(ParameterHints, DeducingThis) { + assertParameterHints(R"cpp( + struct S { + template + auto operator()(this This &&Self, int Param) { + return 42; + } + + auto function(this auto &Self, int Param) { + return Param; + } + }; + void work() { + S s; + s($1[[42]]); + s.function($2[[42]]); + S()($3[[42]]); + auto lambda = [](this auto &Self, char C) -> void { + return Self(C); + }; + lambda($4[['A']]); + } + )cpp", + ExpectedHint{"Param: ", "1"}, + ExpectedHint{"Param: ", "2"}, + ExpectedHint{"Param: ", "3"}, ExpectedHint{"C: ", "4"}); +} + TEST(ParameterHints, Macros) { // Handling of macros depends on where the call's argument list comes from. diff --git a/clang-tools-extra/clangd/unittests/ParsedASTTests.cpp b/clang-tools-extra/clangd/unittests/ParsedASTTests.cpp index 0348348450453..500b72b9b327a 100644 --- a/clang-tools-extra/clangd/unittests/ParsedASTTests.cpp +++ b/clang-tools-extra/clangd/unittests/ParsedASTTests.cpp @@ -12,6 +12,8 @@ //===----------------------------------------------------------------------===// #include "../../clang-tidy/ClangTidyCheck.h" +#include "../../clang-tidy/ClangTidyModule.h" +#include "../../clang-tidy/ClangTidyModuleRegistry.h" #include "AST.h" #include "CompileCommands.h" #include "Compiler.h" @@ -26,9 +28,11 @@ #include "TidyProvider.h" #include "support/Context.h" #include "clang/AST/DeclTemplate.h" +#include "clang/Basic/FileEntry.h" #include "clang/Basic/SourceLocation.h" #include "clang/Basic/SourceManager.h" #include "clang/Basic/TokenKinds.h" +#include "clang/Lex/PPCallbacks.h" #include "clang/Tooling/Syntax/Tokens.h" #include "llvm/ADT/StringRef.h" #include "llvm/Testing/Annotations/Annotations.h" @@ -36,7 +40,9 @@ #include "gmock/gmock-matchers.h" #include "gmock/gmock.h" #include "gtest/gtest.h" +#include #include +#include namespace clang { namespace clangd { diff --git a/clang-tools-extra/clangd/unittests/ReplayPeambleTests.cpp b/clang-tools-extra/clangd/unittests/ReplayPeambleTests.cpp index 459a8f4c36a4c..472fe30ee46ed 100644 --- a/clang-tools-extra/clangd/unittests/ReplayPeambleTests.cpp +++ b/clang-tools-extra/clangd/unittests/ReplayPeambleTests.cpp @@ -15,11 +15,13 @@ #include "../../clang-tidy/ClangTidyModule.h" #include "../../clang-tidy/ClangTidyModuleRegistry.h" #include "AST.h" +#include "Config.h" #include "Diagnostics.h" #include "ParsedAST.h" #include "SourceCode.h" #include "TestTU.h" #include "TidyProvider.h" +#include "support/Context.h" #include "clang/AST/DeclTemplate.h" #include "clang/Basic/FileEntry.h" #include "clang/Basic/LLVM.h" @@ -121,6 +123,11 @@ TEST(ReplayPreambleTest, IncludesAndSkippedFiles) { // obj-c. TU.ExtraArgs = {"-isystem.", "-xobjective-c"}; + // Allow the check to run even though not marked as fast. + Config Cfg; + Cfg.Diagnostics.ClangTidy.FastCheckFilter = Config::FastCheckPolicy::Loose; + WithContextValue WithCfg(Config::Key, std::move(Cfg)); + const auto &AST = TU.build(); const auto &SM = AST.getSourceManager(); diff --git a/clang-tools-extra/clangd/unittests/TidyProviderTests.cpp b/clang-tools-extra/clangd/unittests/TidyProviderTests.cpp index ece7f52d04d45..56b984c8e5333 100644 --- a/clang-tools-extra/clangd/unittests/TidyProviderTests.cpp +++ b/clang-tools-extra/clangd/unittests/TidyProviderTests.cpp @@ -6,8 +6,10 @@ // //===----------------------------------------------------------------------===// +#include "Feature.h" #include "TestFS.h" #include "TidyProvider.h" +#include "llvm/Testing/Support/SupportHelpers.h" #include "gtest/gtest.h" namespace clang { @@ -52,6 +54,22 @@ TEST(TidyProvider, NestedDirectories) { EXPECT_EQ(*Sub2Options.Checks, "misc-*,bugprone-*"); EXPECT_EQ(Sub2Options.CheckOptions.lookup("TestKey").Value, "3"); } + +TEST(TidyProvider, IsFastTidyCheck) { + EXPECT_THAT(isFastTidyCheck("misc-const-correctness"), llvm::ValueIs(false)); + EXPECT_THAT(isFastTidyCheck("bugprone-suspicious-include"), + llvm::ValueIs(true)); + // Linked in (ParsedASTTests.cpp) but not measured. + EXPECT_EQ(isFastTidyCheck("replay-preamble-check"), std::nullopt); +} + +#if CLANGD_TIDY_CHECKS +TEST(TidyProvider, IsValidCheck) { + EXPECT_TRUE(isRegisteredTidyCheck("bugprone-argument-comment")); + EXPECT_FALSE(isRegisteredTidyCheck("bugprone-argument-clinic")); +} +#endif + } // namespace } // namespace clangd } // namespace clang diff --git a/clang-tools-extra/clangd/unittests/tweaks/RawStringLiteralTests.cpp b/clang-tools-extra/clangd/unittests/tweaks/RawStringLiteralTests.cpp index 4bc3045597050..2681b8c815dba 100644 --- a/clang-tools-extra/clangd/unittests/tweaks/RawStringLiteralTests.cpp +++ b/clang-tools-extra/clangd/unittests/tweaks/RawStringLiteralTests.cpp @@ -36,6 +36,20 @@ literal)")cpp"; EXPECT_EQ(apply(Input), Output); } +TEST_F(RawStringLiteralTest, TestC) { + Context = File; + FileName = "TestTU.c"; + ExtraArgs = {"-xc"}; // raw strings are unavailable in C + EXPECT_UNAVAILABLE(R"c(const char *a = ^"^f^o^o^\^n^";)c"); +} + +TEST_F(RawStringLiteralTest, TestCpp98) { + Context = File; + ExtraArgs = {"-std=c++98"}; // raw strings are unavailable + // in versions prior to C++11 + EXPECT_UNAVAILABLE(R"cpp(const char *a = ^"^f^o^o^\^n^";)cpp"); +} + } // namespace } // namespace clangd } // namespace clang diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index 3e1fbe091c9ff..ecfb3aa9267f1 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -120,11 +120,21 @@ Improvements to clang-tidy - Improved :program:`clang-tidy-diff.py` script. It now returns exit code `1` if any :program:`clang-tidy` subprocess exits with a non-zero code or if - exporting fixes fails. + exporting fixes fails. It now accepts a directory as a value for + `-export-fixes` to export individual yaml files for each compilation unit. + +- Improved :program:`run-clang-tidy.py` script. It now accepts a directory + as a value for `-export-fixes` to export individual yaml files for each + compilation unit. New checks ^^^^^^^^^^ +- New :doc:`bugprone-casting-through-void + ` check. + + Detects unsafe or redundant two-step casting operations involving ``void*``. + - New :doc:`bugprone-compare-pointer-to-member-virtual-function ` check. @@ -197,6 +207,11 @@ New check aliases Changes in existing checks ^^^^^^^^^^^^^^^^^^^^^^^^^^ +- Improved :doc:`bugprone-dangling-handle + ` check to support functional + casting during type conversions at variable initialization, now with improved + compatibility for C++17 and later versions. + - Improved :doc:`bugprone-lambda-function-name ` check by adding option `IgnoreMacros` to ignore warnings in macros. @@ -209,10 +224,20 @@ Changes in existing checks ` check, so that it does not warn on macros starting with underscore and lowercase letter. +- Improved :doc:`bugprone-unchecked-optional-access + ` check, so that it does + not crash during handling of optional values. + - Improved :doc:`bugprone-undefined-memory-manipulation ` check to support fixed-size arrays of non-trivial types. +- Improved :doc:`bugprone-unused-return-value + ` check diagnostic message, + added support for detection of unused results when cast to non-``void`` type. + Casting to ``void`` no longer suppresses issues by default, control this + behavior with the new `AllowCastToVoid` option. + - Improved :doc:`cppcoreguidelines-avoid-non-const-global-variables ` check to ignore ``static`` variables declared within the scope of @@ -224,9 +249,15 @@ Changes in existing checks coroutine functions and increase issue detection for cases involving type aliases with references. +- Improved :doc:`cppcoreguidelines-narrowing-conversions + ` check by + extending the `IgnoreConversionFromTypes` option to include types without a + declaration, such as built-in types. + - Improved :doc:`cppcoreguidelines-prefer-member-initializer ` check to - ignore delegate constructors. + ignore delegate constructors and ignore re-assignment for reference or when + initialization depend on field that is initialized before. - Improved :doc:`cppcoreguidelines-pro-bounds-array-to-pointer-decay ` check @@ -236,17 +267,28 @@ Changes in existing checks ` check to perform checks on derived classes of ``std::array``. +- Improved :doc:`cppcoreguidelines-pro-type-const-cast + ` check to ignore + casts to ``const`` or ``volatile`` type (controlled by `StrictMode` option) + and casts in implicitly invoked code. + - Improved :doc:`cppcoreguidelines-pro-type-member-init ` check to ignore dependent delegate constructors. +- Improved :doc:`cppcoreguidelines-pro-type-static-cast-downcast + ` check to + disregard casts on non-polymorphic types when the `StrictMode` option is set + to `false`. + - Improved :doc:`cppcoreguidelines-pro-type-vararg ` check to ignore false-positives in unevaluated context (e.g., ``decltype``, ``sizeof``, ...). - Improved :doc:`cppcoreguidelines-rvalue-reference-param-not-moved ` check - to ignore unused parameters when they are marked as unused. + to ignore unused parameters when they are marked as unused and parameters of + deleted functions and constructors. - Improved :doc:`llvm-namespace-comment ` check to provide fixes for @@ -276,6 +318,14 @@ Changes in existing checks ` check to ignore false-positives in unevaluated context (e.g., ``decltype``). +- Improved :doc:`misc-unused-using-decls + ` check to avoid false positive when + using in elaborated type. + +- Improved :doc:`modernize-avoid-bind + ` check to + not emit a ``return`` for fixes when the function returns ``void``. + - Improved :doc:`modernize-loop-convert ` to support for-loops with iterators initialized by free functions like ``begin``, ``end``, or ``size`` @@ -319,6 +369,10 @@ Changes in existing checks ` check to ignore false-positive for ``if constexpr`` in lambda expression. +- Improved :doc:`readability-avoid-const-params-in-decls + ` diagnositics to + highlight the const location + - Improved :doc:`readability-container-size-empty ` check to detect comparison between string and empty string literals and support diff --git a/clang-tools-extra/docs/clang-tidy/Integrations.rst b/clang-tools-extra/docs/clang-tidy/Integrations.rst index 8f3f5a31274e8..7104944120a93 100644 --- a/clang-tools-extra/docs/clang-tidy/Integrations.rst +++ b/clang-tools-extra/docs/clang-tidy/Integrations.rst @@ -15,7 +15,7 @@ The following table shows the most well-known :program:`clang-tidy` integrations in detail. +--------------------------------------+------------------------+---------------------------------+--------------------------+-----------------------------------------+--------------------------+ -| | Feature | +| | Feature | | | | | +======================================+========================+=================================+==========================+=========================================+==========================+ | **Tool** | On-the-fly inspection | Check list configuration (GUI) | Options to checks (GUI) | Configuration via ``.clang-tidy`` files | Custom clang-tidy binary | +--------------------------------------+------------------------+---------------------------------+--------------------------+-----------------------------------------+--------------------------+ diff --git a/clang-tools-extra/docs/clang-tidy/checks/bugprone/casting-through-void.rst b/clang-tools-extra/docs/clang-tidy/checks/bugprone/casting-through-void.rst new file mode 100644 index 0000000000000..a9ab478b9a82e --- /dev/null +++ b/clang-tools-extra/docs/clang-tidy/checks/bugprone/casting-through-void.rst @@ -0,0 +1,31 @@ +.. title:: clang-tidy - bugprone-casting-through-void + +bugprone-casting-through-void +============================= + +Detects unsafe or redundant two-step casting operations involving ``void*``. + +Two-step type conversions via ``void*`` are discouraged for several reasons. + +- They obscure code and impede its understandability, complicating maintenance. +- These conversions bypass valuable compiler support, erasing warnings related + to pointer alignment. It may violate strict aliasing rule and leading to + undefined behavior. +- In scenarios involving multiple inheritance, ambiguity and unexpected outcomes + can arise due to the loss of type information, posing runtime issues. + +In summary, avoiding two-step type conversions through ``void*`` ensures clearer code, +maintains essential compiler warnings, and prevents ambiguity and potential runtime +errors, particularly in complex inheritance scenarios. + +Examples: + +.. code-block:: c++ + + using IntegerPointer = int *; + double *ptr; + + static_cast(static_cast(ptr)); // WRONG + reinterpret_cast(reinterpret_cast(ptr)); // WRONG + (IntegerPointer)(void *)ptr; // WRONG + IntegerPointer(static_cast(ptr)); // WRONG diff --git a/clang-tools-extra/docs/clang-tidy/checks/bugprone/unused-return-value.rst b/clang-tools-extra/docs/clang-tidy/checks/bugprone/unused-return-value.rst index 5ca96216a1004..1e3c8a3268222 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/bugprone/unused-return-value.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/bugprone/unused-return-value.rst @@ -52,5 +52,9 @@ Options By default the following function return types are checked: `::std::error_code`, `::std::error_condition`, `::std::errc`, `::std::expected`, `::boost::system::error_code` +.. option:: AllowCastToVoid + + Controls whether casting return values to ``void`` is permitted. Default: `false`. + :doc:`cert-err33-c <../cert/err33-c>` is an alias of this check that checks a fixed and large set of standard library functions. diff --git a/clang-tools-extra/docs/clang-tidy/checks/cert/err33-c.rst b/clang-tools-extra/docs/clang-tidy/checks/cert/err33-c.rst index f3211e50b7e6c..c1414ec5e086d 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/cert/err33-c.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/cert/err33-c.rst @@ -189,6 +189,9 @@ functions are checked: This check is an alias of check :doc:`bugprone-unused-return-value <../bugprone/unused-return-value>` with a fixed set of functions. +Suppressing issues by casting to ``void`` is enabled by default and can be +disabled by setting `AllowCastToVoid` option to ``false``. + The check corresponds to a part of CERT C Coding Standard rule `ERR33-C. Detect and handle standard library errors `_. diff --git a/clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/pro-type-const-cast.rst b/clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/pro-type-const-cast.rst index eb572e625f129..961a591cb81f8 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/pro-type-const-cast.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/pro-type-const-cast.rst @@ -3,11 +3,35 @@ cppcoreguidelines-pro-type-const-cast ===================================== -This check flags all uses of ``const_cast`` in C++ code. +Imposes limitations on the use of ``const_cast`` within C++ code. It depends on +the :option:`StrictMode` option setting to determine whether it should flag all +instances of ``const_cast`` or only those that remove either ``const`` or +``volatile`` qualifier. -Modifying a variable that was declared const is undefined behavior, even with -``const_cast``. +Modifying a variable that has been declared as ``const`` in C++ is generally +considered undefined behavior, and this remains true even when using +``const_cast``. In C++, the ``const`` qualifier indicates that a variable is +intended to be read-only, and the compiler enforces this by disallowing any +attempts to change the value of that variable. + +Removing the ``volatile`` qualifier in C++ can have serious consequences. This +qualifier indicates that a variable's value can change unpredictably, and +removing it may lead to undefined behavior, optimization problems, and debugging +challenges. It's essential to retain the ``volatile`` qualifier in situations +where the variable's volatility is a crucial aspect of program correctness and +reliability. This rule is part of the `Type safety (Type 3) `_ -profile from the C++ Core Guidelines. +profile and `ES.50: Don’t cast away const +`_ +rule from the C++ Core Guidelines. + +Options +------- + +.. option:: StrictMode + + When this setting is set to `true`, it means that any usage of ``const_cast`` + is not allowed. On the other hand, when it's set to `false`, it permits + casting to ``const`` or ``volatile`` types. Default value is `false`. diff --git a/clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/pro-type-static-cast-downcast.rst b/clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/pro-type-static-cast-downcast.rst index bcb353301f028..333e6db2aacec 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/pro-type-static-cast-downcast.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/pro-type-static-cast-downcast.rst @@ -14,3 +14,11 @@ unrelated type ``Z``. This rule is part of the `Type safety (Type.2) `_ profile from the C++ Core Guidelines. + +Options +------- + +.. option:: StrictMode + + When set to `false`, no warnings are emitted for casts on non-polymorphic + types. Default is `true`. diff --git a/clang-tools-extra/docs/clang-tidy/checks/list.rst b/clang-tools-extra/docs/clang-tidy/checks/list.rst index 3ec7e49236101..6f987ba1672e3 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/list.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/list.rst @@ -82,6 +82,7 @@ Clang-Tidy Checks :doc:`bugprone-bad-signal-to-kill-thread `, :doc:`bugprone-bool-pointer-implicit-conversion `, "Yes" :doc:`bugprone-branch-clone `, + :doc:`bugprone-casting-through-void `, :doc:`bugprone-compare-pointer-to-member-virtual-function `, :doc:`bugprone-copy-constructor-init `, "Yes" :doc:`bugprone-dangling-handle `, diff --git a/clang-tools-extra/docs/clang-tidy/checks/readability/identifier-naming.rst b/clang-tools-extra/docs/clang-tidy/checks/readability/identifier-naming.rst index 467968ce43fae..608bc2acdc0d5 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/readability/identifier-naming.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/readability/identifier-naming.rst @@ -2526,41 +2526,41 @@ Otherwise the case of this character denotes scope. The following table is the default mapping table of Hungarian Notation which maps Decl to its prefix string. You can also have your own style in config file. -================= ============== ====================== ============== =========== ============== -Primitive Types Microsoft data types ----------------------------------------------------------------------- -------------------------- - Type Prefix Type Prefix Type Prefix -================= ============== ====================== ============== =========== ============== -int8_t i8 signed int si BOOL b -int16_t i16 signed short ss BOOLEAN b -int32_t i32 signed short int ssi BYTE by -int64_t i64 signed long long int slli CHAR c -uint8_t u8 signed long long sll UCHAR uc -uint16_t u16 signed long int sli SHORT s -uint32_t u32 signed long sl USHORT us -uint64_t u64 signed s WORD w -char8_t c8 unsigned long long int ulli DWORD dw -char16_t c16 unsigned long long ull DWORD32 dw32 -char32_t c32 unsigned long int uli DWORD64 dw64 -float f unsigned long ul LONG l -double d unsigned short int usi ULONG ul -char c unsigned short us ULONG32 ul32 -bool b unsigned int ui ULONG64 ul64 -_Bool b unsigned char uc ULONGLONG ull -int i unsigned u HANDLE h -size_t n long long int lli INT i -short s long double ld INT8 i8 -signed i long long ll INT16 i16 -unsigned u long int li INT32 i32 -long l long l INT64 i64 -long long ll ptrdiff_t p UINT ui -unsigned long ul void *none* UINT8 u8 -long double ld UINT16 u16 -ptrdiff_t p UINT32 u32 -wchar_t wc UINT64 u64 -short int si PVOID p +================= ============== ====================== ============== ============== ============== +Primitive Type Microsoft Type +----------------- -------------- ---------------------- -------------- -------------- -------------- + Type Prefix Type Prefix Type Prefix +================= ============== ====================== ============== ============== ============== +int8_t i8 signed int si BOOL b +int16_t i16 signed short ss BOOLEAN b +int32_t i32 signed short int ssi BYTE by +int64_t i64 signed long long int slli CHAR c +uint8_t u8 signed long long sll UCHAR uc +uint16_t u16 signed long int sli SHORT s +uint32_t u32 signed long sl USHORT us +uint64_t u64 signed s WORD w +char8_t c8 unsigned long long int ulli DWORD dw +char16_t c16 unsigned long long ull DWORD32 dw32 +char32_t c32 unsigned long int uli DWORD64 dw64 +float f unsigned long ul LONG l +double d unsigned short int usi ULONG ul +char c unsigned short us ULONG32 ul32 +bool b unsigned int ui ULONG64 ul64 +_Bool b unsigned char uc ULONGLONG ull +int i unsigned u HANDLE h +size_t n long long int lli INT i +short s long double ld INT8 i8 +signed i long long ll INT16 i16 +unsigned u long int li INT32 i32 +long l long l INT64 i64 +long long ll ptrdiff_t p UINT ui +unsigned long ul void *none* UINT8 u8 +long double ld UINT16 u16 +ptrdiff_t p UINT32 u32 +wchar_t wc UINT64 u64 +short int si PVOID p short s -================= ============== ====================== ============== =========== ============== +================= ============== ====================== ============== ============== ============== **There are more trivial options for Hungarian Notation:** diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone/Inputs/unchecked-optional-access/absl/types/optional.h b/clang-tools-extra/test/clang-tidy/checkers/bugprone/Inputs/unchecked-optional-access/absl/types/optional.h index 154cc262ab7cd..3e692f347aa1e 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/bugprone/Inputs/unchecked-optional-access/absl/types/optional.h +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone/Inputs/unchecked-optional-access/absl/types/optional.h @@ -66,6 +66,8 @@ class optional { void reset() noexcept; void swap(optional &rhs) noexcept; + + template optional &operator=(const U &u); }; } // namespace absl diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone/casting-through-void.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone/casting-through-void.cpp new file mode 100644 index 0000000000000..3913d2d8a295c --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone/casting-through-void.cpp @@ -0,0 +1,91 @@ +// RUN: %check_clang_tidy %s bugprone-casting-through-void %t + +using V = void*; +using CV = const void*; + +int i = 100; +double d = 100; +const int ci = 100; +const double cd = 100; + +void normal_test() { + static_cast(static_cast(&d)); + // CHECK-MESSAGES: :[[@LINE-1]]:22: warning: do not cast 'double *' to 'int *' through 'void *' [bugprone-casting-through-void] + static_cast(static_cast(&d)); + // CHECK-MESSAGES: :[[@LINE-1]]:22: warning: do not cast 'double *' to 'int *' through 'V' (aka 'void *') [bugprone-casting-through-void] + static_cast(static_cast(&i)); + // CHECK-MESSAGES: :[[@LINE-1]]:22: warning: do not cast 'int *' to 'int *' through 'void *' [bugprone-casting-through-void] + + static_cast(static_cast(&i)); +} + +void const_pointer_test() { + static_cast(static_cast(&d)); + // CHECK-MESSAGES: :[[@LINE-1]]:27: warning: do not cast 'double *' to 'int *const' through 'void *' [bugprone-casting-through-void] + static_cast(static_cast(&d)); + // CHECK-MESSAGES: :[[@LINE-1]]:27: warning: do not cast 'double *' to 'int *const' through 'V' (aka 'void *') [bugprone-casting-through-void] + static_cast(static_cast(&i)); + // CHECK-MESSAGES: :[[@LINE-1]]:27: warning: do not cast 'int *' to 'int *const' through 'void *' [bugprone-casting-through-void] + + static_cast(static_cast(&i)); +} + +void const_test() { + static_cast(static_cast(&d)); + // CHECK-MESSAGES: :[[@LINE-1]]:28: warning: do not cast 'double *' to 'const int *' through 'const void *' [bugprone-casting-through-void] + static_cast(static_cast(&d)); + // CHECK-MESSAGES: :[[@LINE-1]]:28: warning: do not cast 'double *' to 'const int *' through 'const V' (aka 'void *const') [bugprone-casting-through-void] + static_cast(static_cast(&i)); + // CHECK-MESSAGES: :[[@LINE-1]]:28: warning: do not cast 'int *' to 'const int *' through 'const void *' [bugprone-casting-through-void] + + static_cast(static_cast(&i)); + + static_cast(static_cast(&cd)); + // CHECK-MESSAGES: :[[@LINE-1]]:28: warning: do not cast 'const double *' to 'const int *' through 'const void *' [bugprone-casting-through-void] + static_cast(static_cast(&cd)); + // CHECK-MESSAGES: :[[@LINE-1]]:28: warning: do not cast 'const double *' to 'const int *' through 'const CV' (aka 'const void *const') [bugprone-casting-through-void] + static_cast(static_cast(&ci)); + // CHECK-MESSAGES: :[[@LINE-1]]:28: warning: do not cast 'const int *' to 'const int *' through 'const void *' [bugprone-casting-through-void] + + static_cast(static_cast(&ci)); +} + + +void reinterpret_cast_test() { + static_cast(reinterpret_cast(&d)); + // CHECK-MESSAGES: :[[@LINE-1]]:22: warning: do not cast 'double *' to 'int *' through 'void *' [bugprone-casting-through-void] + reinterpret_cast(static_cast(&d)); + // CHECK-MESSAGES: :[[@LINE-1]]:27: warning: do not cast 'double *' to 'int *' through 'void *' [bugprone-casting-through-void] + reinterpret_cast(reinterpret_cast(&d)); + // CHECK-MESSAGES: :[[@LINE-1]]:27: warning: do not cast 'double *' to 'int *' through 'void *' [bugprone-casting-through-void] + + static_cast(reinterpret_cast(&i)); + reinterpret_cast(reinterpret_cast(&i)); + reinterpret_cast(static_cast(&i)); +} + +void c_style_cast_test() { + static_cast((void *)&d); + // CHECK-MESSAGES: :[[@LINE-1]]:22: warning: do not cast 'double *' to 'int *' through 'void *' [bugprone-casting-through-void] + (int *)(void *)&d; + // CHECK-MESSAGES: :[[@LINE-1]]:10: warning: do not cast 'double *' to 'int *' through 'void *' [bugprone-casting-through-void] + static_cast((void *)&d); + // CHECK-MESSAGES: :[[@LINE-1]]:22: warning: do not cast 'double *' to 'int *' through 'void *' [bugprone-casting-through-void] + + static_cast((void *)&i); +} + +struct A { + A(void*); +}; +using I = int *; +void cxx_functional_cast() { + A(static_cast(&d)); + I(static_cast(&d)); + // CHECK-MESSAGES: :[[@LINE-1]]:5: warning: do not cast 'double *' to 'I' (aka 'int *') through 'void *' [bugprone-casting-through-void] +} + +void bit_cast() { + __builtin_bit_cast(int *, static_cast(&d)); + // CHECK-MESSAGES: :[[@LINE-1]]:29: warning: do not cast 'double *' to 'int *' through 'void *' [bugprone-casting-through-void] +} diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone/dangling-handle.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone/dangling-handle.cpp index 23cda53217643..96c812617038a 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/bugprone/dangling-handle.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone/dangling-handle.cpp @@ -108,6 +108,14 @@ void Positives() { std::string_view view4(ReturnsAString()); // CHECK-MESSAGES-CXX14: [[@LINE-1]]:20: warning: std::basic_string_view outlives // CHECK-MESSAGES-CXX17: [[@LINE-2]]:26: warning: std::basic_string_view outlives + + std::string_view view5 = std::string("test"); + // CHECK-MESSAGES-CXX14: [[@LINE-1]]:20: warning: std::basic_string_view outlives its value [bugprone-dangling-handle] + // CHECK-MESSAGES-CXX17: [[@LINE-2]]:28: warning: std::basic_string_view outlives its value [bugprone-dangling-handle] + + std::string_view view6 = std::string{"test"}; + // CHECK-MESSAGES-CXX14: [[@LINE-1]]:20: warning: std::basic_string_view outlives its value [bugprone-dangling-handle] + // CHECK-MESSAGES-CXX17: [[@LINE-2]]:28: warning: std::basic_string_view outlives its value [bugprone-dangling-handle] } void OtherTypes() { diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone/string-constructor.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone/string-constructor.cpp index 1ca4d14f85e29..a5b6b240ddc66 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/bugprone/string-constructor.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone/string-constructor.cpp @@ -49,6 +49,8 @@ void Test() { // CHECK-MESSAGES: [[@LINE-1]]:15: warning: negative value used as length parameter std::string q2("test", 200); // CHECK-MESSAGES: [[@LINE-1]]:15: warning: length is bigger than string literal size + std::string t1("test", 5); + // CHECK-MESSAGES: [[@LINE-1]]:15: warning: length is bigger than string literal size std::string q3(kText, 200); // CHECK-MESSAGES: [[@LINE-1]]:15: warning: length is bigger than string literal size std::string q4(kText2, 200); @@ -97,6 +99,8 @@ void Valid() { std::string s1("test", 4); std::string s2("test", 3); std::string s3("test"); + std::string s4("test\000", 5); + std::string s6("te" "st", 4); std::string_view emptyv(); std::string_view sv1("test", 4); diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone/unchecked-optional-access.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone/unchecked-optional-access.cpp index 1921291f2187d..13a3ff52f3ebc 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/bugprone/unchecked-optional-access.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone/unchecked-optional-access.cpp @@ -180,3 +180,23 @@ void std_forward_rvalue_ref_safe(absl::optional&& opt) { std::forward>(opt).value(); } + +namespace std { + +template class vector { +public: + T &operator[](unsigned long index); + bool empty(); +}; + +} // namespace std + +struct S { + absl::optional x; +}; +std::vector vec; + +void foo() { + if (!vec.empty()) + vec[0].x = 0; +} diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone/unused-return-value-custom.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone/unused-return-value-custom.cpp index fb5f77031a327..d3650b210ab02 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/bugprone/unused-return-value-custom.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone/unused-return-value-custom.cpp @@ -47,40 +47,35 @@ void fun(int); void warning() { fun(); - // CHECK-NOTES: [[@LINE-1]]:3: warning: the value returned by this function should be used - // CHECK-NOTES: [[@LINE-2]]:3: note: cast the expression to void to silence this warning + // CHECK-MESSAGES: [[@LINE-1]]:3: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors (fun()); - // CHECK-NOTES: [[@LINE-1]]:4: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:4: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:4: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + + (void)fun(); + // CHECK-MESSAGES: [[@LINE-1]]:9: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors ns::Outer::Inner ObjA1; ObjA1.memFun(); - // CHECK-NOTES: [[@LINE-1]]:3: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:3: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:3: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors ns::AliasName::Inner ObjA2; ObjA2.memFun(); - // CHECK-NOTES: [[@LINE-1]]:3: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:3: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:3: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors ns::Derived ObjA3; ObjA3.memFun(); - // CHECK-NOTES: [[@LINE-1]]:3: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:3: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:3: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors ns::Type::staticFun(); - // CHECK-NOTES: [[@LINE-1]]:3: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:3: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:3: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors ns::ClassTemplate ObjA4; ObjA4.memFun(); - // CHECK-NOTES: [[@LINE-1]]:3: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:3: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:3: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors ns::ClassTemplate::staticFun(); - // CHECK-NOTES: [[@LINE-1]]:3: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:3: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:3: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors } void noWarning() { diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone/unused-return-value.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone/unused-return-value.cpp index 6da66ca42d90f..5c6ce1e4bf1fd 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/bugprone/unused-return-value.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone/unused-return-value.cpp @@ -1,4 +1,5 @@ -// RUN: %check_clang_tidy %s bugprone-unused-return-value %t -- -- -fexceptions +// RUN: %check_clang_tidy %s bugprone-unused-return-value %t -- \ +// RUN: --config="{CheckOptions: {bugprone-unused-return-value.AllowCastToVoid: true}}" -- -fexceptions namespace std { @@ -81,121 +82,125 @@ std::error_code errorFunc() { void warning() { std::async(increment, 42); - // CHECK-NOTES: [[@LINE-1]]:3: warning: the value returned by this function should be used - // CHECK-NOTES: [[@LINE-2]]:3: note: cast the expression to void to silence this warning + // CHECK-MESSAGES: [[@LINE-1]]:3: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:3: note: cast the expression to void to silence this warning std::async(std::launch::async, increment, 42); - // CHECK-NOTES: [[@LINE-1]]:3: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:3: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:3: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:3: note: cast the expression to void to silence this warning Foo F; std::launder(&F); - // CHECK-NOTES: [[@LINE-1]]:3: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:3: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:3: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:3: note: cast the expression to void to silence this warning std::remove(nullptr, nullptr, 1); - // CHECK-NOTES: [[@LINE-1]]:3: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:3: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:3: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:3: note: cast the expression to void to silence this warning std::remove_if(nullptr, nullptr, nullptr); - // CHECK-NOTES: [[@LINE-1]]:3: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:3: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:3: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:3: note: cast the expression to void to silence this warning std::unique(nullptr, nullptr); - // CHECK-NOTES: [[@LINE-1]]:3: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:3: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:3: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:3: note: cast the expression to void to silence this warning std::unique_ptr UPtr; UPtr.release(); - // CHECK-NOTES: [[@LINE-1]]:3: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:3: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:3: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:3: note: cast the expression to void to silence this warning std::string Str; Str.empty(); - // CHECK-NOTES: [[@LINE-1]]:3: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:3: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:3: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:3: note: cast the expression to void to silence this warning + + (int)Str.empty(); + // CHECK-MESSAGES: [[@LINE-1]]:8: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:8: note: cast the expression to void to silence this warning std::vector Vec; Vec.empty(); - // CHECK-NOTES: [[@LINE-1]]:3: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:3: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:3: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:3: note: cast the expression to void to silence this warning // test discarding return values inside different kinds of statements auto Lambda = [] { std::remove(nullptr, nullptr, 1); }; - // CHECK-NOTES: [[@LINE-1]]:22: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:22: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:22: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:22: note: cast the expression to void to silence this warning if (true) std::remove(nullptr, nullptr, 1); - // CHECK-NOTES: [[@LINE-1]]:5: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:5: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:5: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:5: note: cast the expression to void to silence this warning else if (true) std::remove(nullptr, nullptr, 1); - // CHECK-NOTES: [[@LINE-1]]:5: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:5: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:5: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:5: note: cast the expression to void to silence this warning else std::remove(nullptr, nullptr, 1); - // CHECK-NOTES: [[@LINE-1]]:5: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:5: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:5: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:5: note: cast the expression to void to silence this warning while (true) std::remove(nullptr, nullptr, 1); - // CHECK-NOTES: [[@LINE-1]]:5: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:5: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:5: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:5: note: cast the expression to void to silence this warning do std::remove(nullptr, nullptr, 1); - // CHECK-NOTES: [[@LINE-1]]:5: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:5: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:5: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:5: note: cast the expression to void to silence this warning while (true); for (;;) std::remove(nullptr, nullptr, 1); - // CHECK-NOTES: [[@LINE-1]]:5: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:5: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:5: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:5: note: cast the expression to void to silence this warning for (std::remove(nullptr, nullptr, 1);;) - // CHECK-NOTES: [[@LINE-1]]:8: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:8: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:8: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:8: note: cast the expression to void to silence this warning ; for (;; std::remove(nullptr, nullptr, 1)) - // CHECK-NOTES: [[@LINE-1]]:11: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:11: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:11: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:11: note: cast the expression to void to silence this warning ; for (auto C : "foo") std::remove(nullptr, nullptr, 1); - // CHECK-NOTES: [[@LINE-1]]:5: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:5: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:5: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:5: note: cast the expression to void to silence this warning switch (1) { case 1: std::remove(nullptr, nullptr, 1); - // CHECK-NOTES: [[@LINE-1]]:5: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:5: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:5: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:5: note: cast the expression to void to silence this warning break; default: std::remove(nullptr, nullptr, 1); - // CHECK-NOTES: [[@LINE-1]]:5: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:5: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:5: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:5: note: cast the expression to void to silence this warning break; } try { std::remove(nullptr, nullptr, 1); - // CHECK-NOTES: [[@LINE-1]]:5: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:5: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:5: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:5: note: cast the expression to void to silence this warning } catch (...) { std::remove(nullptr, nullptr, 1); - // CHECK-NOTES: [[@LINE-1]]:5: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:5: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:5: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:5: note: cast the expression to void to silence this warning } errorFunc(); - // CHECK-NOTES: [[@LINE-1]]:3: warning: the value {{.*}} should be used - // CHECK-NOTES: [[@LINE-2]]:3: note: cast {{.*}} this warning + // CHECK-MESSAGES: [[@LINE-1]]:3: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:3: note: cast the expression to void to silence this warning } void noWarning() { diff --git a/clang-tools-extra/test/clang-tidy/checkers/cert/err33-c.c b/clang-tools-extra/test/clang-tidy/checkers/cert/err33-c.c index 520ff17bd890e..87ce0acf664e6 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/cert/err33-c.c +++ b/clang-tools-extra/test/clang-tidy/checkers/cert/err33-c.c @@ -4,15 +4,15 @@ typedef __SIZE_TYPE__ size_t; void *aligned_alloc(size_t alignment, size_t size); void test_aligned_alloc(void) { aligned_alloc(2, 10); - // CHECK-NOTES: [[@LINE-1]]:3: warning: the value returned by this function should be used - // CHECK-NOTES: [[@LINE-2]]:3: note: cast the expression to void to silence this warning + // CHECK-MESSAGES: [[@LINE-1]]:3: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:3: note: cast the expression to void to silence this warning } long strtol(const char *restrict nptr, char **restrict endptr, int base); void test_strtol(void) { strtol("123", 0, 10); - // CHECK-NOTES: [[@LINE-1]]:3: warning: the value returned by this function should be used - // CHECK-NOTES: [[@LINE-2]]:3: note: cast the expression to void to silence this warning + // CHECK-MESSAGES: [[@LINE-1]]:3: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:3: note: cast the expression to void to silence this warning } typedef char wchar_t; @@ -20,6 +20,6 @@ int wscanf_s(const wchar_t *restrict format, ...); void test_wscanf_s(void) { int Val; wscanf_s("%i", &Val); - // CHECK-NOTES: [[@LINE-1]]:3: warning: the value returned by this function should be used - // CHECK-NOTES: [[@LINE-2]]:3: note: cast the expression to void to silence this warning + // CHECK-MESSAGES: [[@LINE-1]]:3: warning: the value returned by this function should not be disregarded; neglecting it may lead to errors + // CHECK-MESSAGES: [[@LINE-2]]:3: note: cast the expression to void to silence this warning } diff --git a/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/narrowing-conversions-ignoreconversionfromtypes-option.cpp b/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/narrowing-conversions-ignoreconversionfromtypes-option.cpp index ab9aabf44ff68..91e908f535a0d 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/narrowing-conversions-ignoreconversionfromtypes-option.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/narrowing-conversions-ignoreconversionfromtypes-option.cpp @@ -4,7 +4,7 @@ // RUN: %check_clang_tidy -check-suffix=IGNORED %s \ // RUN: cppcoreguidelines-narrowing-conversions %t -- \ // RUN: -config='{CheckOptions: { \ -// RUN: cppcoreguidelines-narrowing-conversions.IgnoreConversionFromTypes: "global_size_t;nested_size_type" \ +// RUN: cppcoreguidelines-narrowing-conversions.IgnoreConversionFromTypes: "global_size_t;nested_size_type;long" \ // RUN: }}' // We use global_size_t instead of 'size_t' because windows predefines size_t. @@ -72,3 +72,10 @@ void most_narrowing_is_not_ok() { // CHECK-MESSAGES-DEFAULT: :[[@LINE-1]]:7: warning: narrowing conversion from 'long long' to signed type 'int' is implementation-defined [cppcoreguidelines-narrowing-conversions] // CHECK-MESSAGES-IGNORED: :[[@LINE-2]]:7: warning: narrowing conversion from 'long long' to signed type 'int' is implementation-defined [cppcoreguidelines-narrowing-conversions] } + +void test_ignore_builtin_type_pr58809() { + long x = 123; + short y = x; + // CHECK-MESSAGES-DEFAULT: :[[@LINE-1]]:13: warning: narrowing conversion from 'long' to signed type 'short' is implementation-defined [cppcoreguidelines-narrowing-conversions] + // CHECK-MESSAGES-NOT-IGNORED: :[[@LINE-2]]:13: warning: narrowing conversion from 'long' to signed type 'short' is implementation-defined [cppcoreguidelines-narrowing-conversions] +} diff --git a/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/prefer-member-initializer.cpp b/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/prefer-member-initializer.cpp index 9d7aad52c8fa8..b5603dea316d5 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/prefer-member-initializer.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/prefer-member-initializer.cpp @@ -570,3 +570,19 @@ struct PR52818 { int bar; }; + +struct RefReassignment { + RefReassignment(int &i) : m_i{i} { + m_i = 1; + } + int & m_i; +}; + +struct ReassignmentAfterUnsafetyAssignment { + ReassignmentAfterUnsafetyAssignment() { + int a = 10; + m_i = a; + m_i = 1; + } + int m_i; +}; diff --git a/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/pro-type-const-cast.cpp b/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/pro-type-const-cast.cpp index 2d32e13723abf..be70e3ba35699 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/pro-type-const-cast.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/pro-type-const-cast.cpp @@ -1,6 +1,86 @@ -// RUN: %check_clang_tidy %s cppcoreguidelines-pro-type-const-cast %t +// RUN: %check_clang_tidy -check-suffix=STRICT %s cppcoreguidelines-pro-type-const-cast %t -- -config="{CheckOptions: {StrictMode: true}}" +// RUN: %check_clang_tidy -check-suffix=NSTRICT %s cppcoreguidelines-pro-type-const-cast %t +namespace Const { const int *i; int *j; -void f() { j = const_cast(i); } -// CHECK-MESSAGES: :[[@LINE-1]]:16: warning: do not use const_cast [cppcoreguidelines-pro-type-const-cast] + +void f() { + j = const_cast(i); + // CHECK-MESSAGES-NSTRICT: :[[@LINE-1]]:7: warning: do not use const_cast to remove const qualifier [cppcoreguidelines-pro-type-const-cast] + // CHECK-MESSAGES-STRICT: :[[@LINE-2]]:7: warning: do not use const_cast [cppcoreguidelines-pro-type-const-cast] + + i = const_cast(j); + // CHECK-MESSAGES-STRICT: :[[@LINE-1]]:7: warning: do not use const_cast [cppcoreguidelines-pro-type-const-cast] + + j = *const_cast(&i); + // CHECK-MESSAGES-NSTRICT: :[[@LINE-1]]:8: warning: do not use const_cast to remove const qualifier [cppcoreguidelines-pro-type-const-cast] + // CHECK-MESSAGES-STRICT: :[[@LINE-2]]:8: warning: do not use const_cast [cppcoreguidelines-pro-type-const-cast] + + i = *const_cast(&j); + // CHECK-MESSAGES-STRICT: :[[@LINE-1]]:8: warning: do not use const_cast [cppcoreguidelines-pro-type-const-cast] + + j = &const_cast(*i); + // CHECK-MESSAGES-NSTRICT: :[[@LINE-1]]:8: warning: do not use const_cast to remove const qualifier [cppcoreguidelines-pro-type-const-cast] + // CHECK-MESSAGES-STRICT: :[[@LINE-2]]:8: warning: do not use const_cast [cppcoreguidelines-pro-type-const-cast] + + i = &const_cast(*j); + // CHECK-MESSAGES-STRICT: :[[@LINE-1]]:8: warning: do not use const_cast [cppcoreguidelines-pro-type-const-cast] +} +} + +namespace Volatile { +volatile int *i; +int *j; + +void f() { + j = const_cast(i); + // CHECK-MESSAGES-NSTRICT: :[[@LINE-1]]:7: warning: do not use const_cast to remove volatile qualifier [cppcoreguidelines-pro-type-const-cast] + // CHECK-MESSAGES-STRICT: :[[@LINE-2]]:7: warning: do not use const_cast [cppcoreguidelines-pro-type-const-cast] + + i = const_cast(j); + // CHECK-MESSAGES-STRICT: :[[@LINE-1]]:7: warning: do not use const_cast [cppcoreguidelines-pro-type-const-cast] + + j = *const_cast(&i); + // CHECK-MESSAGES-NSTRICT: :[[@LINE-1]]:8: warning: do not use const_cast to remove volatile qualifier [cppcoreguidelines-pro-type-const-cast] + // CHECK-MESSAGES-STRICT: :[[@LINE-2]]:8: warning: do not use const_cast [cppcoreguidelines-pro-type-const-cast] + + i = *const_cast(&j); + // CHECK-MESSAGES-STRICT: :[[@LINE-1]]:8: warning: do not use const_cast [cppcoreguidelines-pro-type-const-cast] + + j = &const_cast(*i); + // CHECK-MESSAGES-NSTRICT: :[[@LINE-1]]:8: warning: do not use const_cast to remove volatile qualifier [cppcoreguidelines-pro-type-const-cast] + // CHECK-MESSAGES-STRICT: :[[@LINE-2]]:8: warning: do not use const_cast [cppcoreguidelines-pro-type-const-cast] + + i = &const_cast(*j); + // CHECK-MESSAGES-STRICT: :[[@LINE-1]]:8: warning: do not use const_cast [cppcoreguidelines-pro-type-const-cast] +} +} + +namespace ConstAndVolatile { +const volatile int *i; +int *j; + +void f() { + j = const_cast(i); + // CHECK-MESSAGES-NSTRICT: :[[@LINE-1]]:7: warning: do not use const_cast to remove const and volatile qualifier [cppcoreguidelines-pro-type-const-cast] + // CHECK-MESSAGES-STRICT: :[[@LINE-2]]:7: warning: do not use const_cast [cppcoreguidelines-pro-type-const-cast] + + i = const_cast(j); + // CHECK-MESSAGES-STRICT: :[[@LINE-1]]:7: warning: do not use const_cast [cppcoreguidelines-pro-type-const-cast] + + j = *const_cast(&i); + // CHECK-MESSAGES-NSTRICT: :[[@LINE-1]]:8: warning: do not use const_cast to remove const and volatile qualifier [cppcoreguidelines-pro-type-const-cast] + // CHECK-MESSAGES-STRICT: :[[@LINE-2]]:8: warning: do not use const_cast [cppcoreguidelines-pro-type-const-cast] + + i = *const_cast(&j); + // CHECK-MESSAGES-STRICT: :[[@LINE-1]]:8: warning: do not use const_cast [cppcoreguidelines-pro-type-const-cast] + + j = &const_cast(*i); + // CHECK-MESSAGES-NSTRICT: :[[@LINE-1]]:8: warning: do not use const_cast to remove const and volatile qualifier [cppcoreguidelines-pro-type-const-cast] + // CHECK-MESSAGES-STRICT: :[[@LINE-2]]:8: warning: do not use const_cast [cppcoreguidelines-pro-type-const-cast] + + i = &const_cast(*j); + // CHECK-MESSAGES-STRICT: :[[@LINE-1]]:8: warning: do not use const_cast [cppcoreguidelines-pro-type-const-cast] +} +} diff --git a/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/pro-type-static-cast-downcast.cpp b/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/pro-type-static-cast-downcast.cpp index 7a6c027ec479b..11179b7d2d19b 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/pro-type-static-cast-downcast.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/pro-type-static-cast-downcast.cpp @@ -1,4 +1,5 @@ -// RUN: %check_clang_tidy %s cppcoreguidelines-pro-type-static-cast-downcast %t +// RUN: %check_clang_tidy -check-suffixes=NSTRICT,STRICT %s cppcoreguidelines-pro-type-static-cast-downcast %t +// RUN: %check_clang_tidy -check-suffix=NSTRICT %s cppcoreguidelines-pro-type-static-cast-downcast %t -- -config="{CheckOptions: {StrictMode: false}}" class Base { }; @@ -26,11 +27,11 @@ class PolymorphicMultiDerived : public Base, public PolymorphicBase { void pointers() { auto P0 = static_cast(new Base()); - // CHECK-MESSAGES: :[[@LINE-1]]:13: warning: do not use static_cast to downcast from a base to a derived class [cppcoreguidelines-pro-type-static-cast-downcast] + // CHECK-MESSAGES-STRICT: :[[@LINE-1]]:13: warning: do not use static_cast to downcast from a base to a derived class [cppcoreguidelines-pro-type-static-cast-downcast] const Base* B0; auto PC0 = static_cast(B0); - // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: do not use static_cast to downcast from a base to a derived class [cppcoreguidelines-pro-type-static-cast-downcast] + // CHECK-MESSAGES-STRICT: :[[@LINE-1]]:14: warning: do not use static_cast to downcast from a base to a derived class [cppcoreguidelines-pro-type-static-cast-downcast] auto P1 = static_cast(new Derived()); // OK, upcast to a public base auto P2 = static_cast(new MultiDerived()); // OK, upcast to a public base @@ -40,13 +41,13 @@ void pointers() { void pointers_polymorphic() { auto PP0 = static_cast(new PolymorphicBase()); - // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: do not use static_cast to downcast from a base to a derived class; use dynamic_cast instead [cppcoreguidelines-pro-type-static-cast-downcast] - // CHECK-FIXES: auto PP0 = dynamic_cast(new PolymorphicBase()); + // CHECK-MESSAGES-NSTRICT: :[[@LINE-1]]:14: warning: do not use static_cast to downcast from a base to a derived class; use dynamic_cast instead [cppcoreguidelines-pro-type-static-cast-downcast] + // CHECK-FIXES-NSTRICT: auto PP0 = dynamic_cast(new PolymorphicBase()); const PolymorphicBase* B0; auto PPC0 = static_cast(B0); - // CHECK-MESSAGES: :[[@LINE-1]]:15: warning: do not use static_cast to downcast from a base to a derived class; use dynamic_cast instead [cppcoreguidelines-pro-type-static-cast-downcast] - // CHECK-FIXES: auto PPC0 = dynamic_cast(B0); + // CHECK-MESSAGES-NSTRICT: :[[@LINE-1]]:15: warning: do not use static_cast to downcast from a base to a derived class; use dynamic_cast instead [cppcoreguidelines-pro-type-static-cast-downcast] + // CHECK-FIXES-NSTRICT: auto PPC0 = dynamic_cast(B0); auto B1 = static_cast(new PolymorphicDerived()); // OK, upcast to a public base @@ -57,27 +58,27 @@ void pointers_polymorphic() { void arrays() { Base ArrayOfBase[10]; auto A0 = static_cast(ArrayOfBase); - // CHECK-MESSAGES: :[[@LINE-1]]:13: warning: do not use static_cast to downcast from a base to a derived class [cppcoreguidelines-pro-type-static-cast-downcast] + // CHECK-MESSAGES-STRICT: :[[@LINE-1]]:13: warning: do not use static_cast to downcast from a base to a derived class [cppcoreguidelines-pro-type-static-cast-downcast] } void arrays_polymorphic() { PolymorphicBase ArrayOfPolymorphicBase[10]; auto AP0 = static_cast(ArrayOfPolymorphicBase); - // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: do not use static_cast to downcast from a base to a derived class; use dynamic_cast instead - // CHECK-FIXES: auto AP0 = dynamic_cast(ArrayOfPolymorphicBase); + // CHECK-MESSAGES-NSTRICT: :[[@LINE-1]]:14: warning: do not use static_cast to downcast from a base to a derived class; use dynamic_cast instead + // CHECK-FIXES-NSTRICT: auto AP0 = dynamic_cast(ArrayOfPolymorphicBase); } void references() { Base B0; auto R0 = static_cast(B0); - // CHECK-MESSAGES: :[[@LINE-1]]:13: warning: do not use static_cast to downcast from a base to a derived class [cppcoreguidelines-pro-type-static-cast-downcast] + // CHECK-MESSAGES-STRICT: :[[@LINE-1]]:13: warning: do not use static_cast to downcast from a base to a derived class [cppcoreguidelines-pro-type-static-cast-downcast] Base& RefToBase = B0; auto R1 = static_cast(RefToBase); - // CHECK-MESSAGES: :[[@LINE-1]]:13: warning: do not use static_cast to downcast from a base to a derived class [cppcoreguidelines-pro-type-static-cast-downcast] + // CHECK-MESSAGES-STRICT: :[[@LINE-1]]:13: warning: do not use static_cast to downcast from a base to a derived class [cppcoreguidelines-pro-type-static-cast-downcast] const Base& ConstRefToBase = B0; auto RC1 = static_cast(ConstRefToBase); - // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: do not use static_cast to downcast from a base to a derived class [cppcoreguidelines-pro-type-static-cast-downcast] + // CHECK-MESSAGES-STRICT: :[[@LINE-1]]:14: warning: do not use static_cast to downcast from a base to a derived class [cppcoreguidelines-pro-type-static-cast-downcast] Derived RD1; @@ -87,18 +88,18 @@ void references() { void references_polymorphic() { PolymorphicBase B0; auto RP0 = static_cast(B0); - // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: do not use static_cast to downcast from a base to a derived class; use dynamic_cast instead - // CHECK-FIXES: auto RP0 = dynamic_cast(B0); + // CHECK-MESSAGES-NSTRICT: :[[@LINE-1]]:14: warning: do not use static_cast to downcast from a base to a derived class; use dynamic_cast instead + // CHECK-FIXES-NSTRICT: auto RP0 = dynamic_cast(B0); PolymorphicBase& RefToPolymorphicBase = B0; auto RP1 = static_cast(RefToPolymorphicBase); - // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: do not use static_cast to downcast from a base to a derived class; use dynamic_cast instead [cppcoreguidelines-pro-type-static-cast-downcast] - // CHECK-FIXES: auto RP1 = dynamic_cast(RefToPolymorphicBase); + // CHECK-MESSAGES-NSTRICT: :[[@LINE-1]]:14: warning: do not use static_cast to downcast from a base to a derived class; use dynamic_cast instead [cppcoreguidelines-pro-type-static-cast-downcast] + // CHECK-FIXES-NSTRICT: auto RP1 = dynamic_cast(RefToPolymorphicBase); const PolymorphicBase& ConstRefToPolymorphicBase = B0; auto RPC2 = static_cast(ConstRefToPolymorphicBase); - // CHECK-MESSAGES: :[[@LINE-1]]:15: warning: do not use static_cast to downcast from a base to a derived class; use dynamic_cast instead [cppcoreguidelines-pro-type-static-cast-downcast] - // CHECK-FIXES: auto RPC2 = dynamic_cast(ConstRefToPolymorphicBase); + // CHECK-MESSAGES-NSTRICT: :[[@LINE-1]]:15: warning: do not use static_cast to downcast from a base to a derived class; use dynamic_cast instead [cppcoreguidelines-pro-type-static-cast-downcast] + // CHECK-FIXES-NSTRICT: auto RPC2 = dynamic_cast(ConstRefToPolymorphicBase); PolymorphicDerived d1; auto RP2 = static_cast(d1); // OK, upcast to a public base diff --git a/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/rvalue-reference-param-not-moved.cpp b/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/rvalue-reference-param-not-moved.cpp index a9b87567a08cc..e996690102dff 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/rvalue-reference-param-not-moved.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/rvalue-reference-param-not-moved.cpp @@ -334,8 +334,7 @@ void instantiate_a_class_template() { withObjRef.never_moves(o); } -namespace gh68209 -{ +namespace gh68209 { void f1([[maybe_unused]] int&& x) {} void f2(__attribute__((unused)) int&& x) {} @@ -358,3 +357,13 @@ namespace gh68209 void f8(__attribute__((unused)) int&& x) { x += 1; } // CHECK-MESSAGES: :[[@LINE-1]]:41: warning: rvalue reference parameter 'x' is never moved from inside the function body [cppcoreguidelines-rvalue-reference-param-not-moved] } // namespace gh68209 + +namespace gh69412 { + struct S + { + S(const int&); + S(int&&) = delete; + + void foo(int&&) = delete; + }; +} // namespace gh69412 diff --git a/clang-tools-extra/test/clang-tidy/checkers/misc/unused-using-decls.cpp b/clang-tools-extra/test/clang-tidy/checkers/misc/unused-using-decls.cpp index 7d02aa4d2e2bf..12fc18f340f21 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/misc/unused-using-decls.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/misc/unused-using-decls.cpp @@ -213,3 +213,12 @@ template class U> class Bar {}; // We used to report Q unsued, because we only checked the first template // argument. Bar *bar; + +namespace gh69714 { +struct StructGH69714_1 {}; +struct StructGH69714_2 {}; +} // namespace gh69714 +using gh69714::StructGH69714_1; +using gh69714::StructGH69714_2; +struct StructGH69714_1 a; +struct StructGH69714_2 *b; diff --git a/clang-tools-extra/test/clang-tidy/checkers/modernize/avoid-bind.cpp b/clang-tools-extra/test/clang-tidy/checkers/modernize/avoid-bind.cpp index 3334eab2d407e..336b3cb4ee08f 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/modernize/avoid-bind.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/modernize/avoid-bind.cpp @@ -45,6 +45,7 @@ struct D { void operator()(int x, int y) const {} void MemberFunction(int x) {} + int MemberFunctionWithReturn(int x) {} static D *create(); }; @@ -162,11 +163,11 @@ struct TestCaptureByValueStruct { // those here. auto FFF = boost::bind(UseF, f); // CHECK-MESSAGES: :[[@LINE-1]]:16: warning: prefer a lambda to boost::bind [modernize-avoid-bind] - // CHECK-FIXES: auto FFF = [f] { return UseF(f); }; + // CHECK-FIXES: auto FFF = [f] { UseF(f); }; auto GGG = boost::bind(UseF, MemberStruct); // CHECK-MESSAGES: :[[@LINE-1]]:16: warning: prefer a lambda to boost::bind [modernize-avoid-bind] - // CHECK-FIXES: auto GGG = [this] { return UseF(MemberStruct); }; + // CHECK-FIXES: auto GGG = [this] { UseF(MemberStruct); }; auto HHH = std::bind(add, MemberStructWithData._member, 1); // CHECK-MESSAGES: :[[@LINE-1]]:16: warning: prefer a lambda to std::bind @@ -227,34 +228,34 @@ void testFunctionObjects() { D *e = nullptr; auto AAA = std::bind(d, 1, 2); // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: prefer a lambda to std::bind - // CHECK-FIXES: auto AAA = [d] { return d(1, 2); } + // CHECK-FIXES: auto AAA = [d] { d(1, 2); } auto BBB = std::bind(*e, 1, 2); // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: prefer a lambda to std::bind - // CHECK-FIXES: auto BBB = [e] { return (*e)(1, 2); } + // CHECK-FIXES: auto BBB = [e] { (*e)(1, 2); } auto CCC = std::bind(D{}, 1, 2); // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: prefer a lambda to std::bind - // CHECK-FIXES: auto CCC = [] { return D{}(1, 2); } + // CHECK-FIXES: auto CCC = [] { D{}(1, 2); } auto DDD = std::bind(D(), 1, 2); // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: prefer a lambda to std::bind - // CHECK-FIXES: auto DDD = [] { return D()(1, 2); } + // CHECK-FIXES: auto DDD = [] { D()(1, 2); } auto EEE = std::bind(*D::create(), 1, 2); // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: prefer a lambda to std::bind - // CHECK-FIXES: auto EEE = [Func = *D::create()] { return Func(1, 2); }; + // CHECK-FIXES: auto EEE = [Func = *D::create()] { Func(1, 2); }; auto FFF = std::bind(G(), 1); // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: prefer a lambda to std::bind // Templated function call operators may be used - // CHECK-FIXES: auto FFF = [] { return G()(1); }; + // CHECK-FIXES: auto FFF = [] { G()(1); }; int CTorArg = 42; auto GGG = std::bind(G(CTorArg), 1); // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: prefer a lambda to std::bind // Function objects with constructor arguments should be captured - // CHECK-FIXES: auto GGG = [Func = G(CTorArg)] { return Func(1); }; + // CHECK-FIXES: auto GGG = [Func = G(CTorArg)] { Func(1); }; } template @@ -262,7 +263,7 @@ void testMemberFnOfClassTemplate(T) { auto HHH = std::bind(H(), 42); // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: prefer a lambda to std::bind // Ensure function class template arguments are preserved - // CHECK-FIXES: auto HHH = [] { return H()(42); }; + // CHECK-FIXES: auto HHH = [] { H()(42); }; } template void testMemberFnOfClassTemplate(int); @@ -335,11 +336,12 @@ void testCapturedSubexpressions() { auto CCC = std::bind(sub, std::ref(*p), _1); // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: prefer a lambda to std::bind // Expressions returning references are captured - // CHECK-FIXES: auto CCC = [&capture0 = *p](auto && PH1) { return sub(capture0, std::forward(PH1)); }; + // CHECK-FIXES: auto CCC = [&capture0 = *p](auto && PH1) { sub(capture0, std::forward(PH1)); }; } struct E { void MemberFunction(int x) {} + int MemberFunctionWithReturn(int x) {} void testMemberFunctions() { D *d; @@ -360,6 +362,23 @@ struct E { auto DDD = std::bind(&D::MemberFunction, _1, 1); // CHECK-MESSAGES: :[[@LINE-1]]:16: warning: prefer a lambda to std::bind // CHECK-FIXES: auto DDD = [](auto && PH1) { PH1->MemberFunction(1); }; + + auto EEE = std::bind(&D::MemberFunctionWithReturn, d, 1); + // CHECK-MESSAGES: :[[@LINE-1]]:16: warning: prefer a lambda to std::bind + // CHECK-FIXES: auto EEE = [d] { return d->MemberFunctionWithReturn(1); }; + + auto FFF = std::bind(&D::MemberFunctionWithReturn, &dd, 1); + // CHECK-MESSAGES: :[[@LINE-1]]:16: warning: prefer a lambda to std::bind + // CHECK-FIXES: auto FFF = [ObjectPtr = &dd] { return ObjectPtr->MemberFunctionWithReturn(1); }; + + auto GGG = std::bind(&E::MemberFunctionWithReturn, this, 1); + // CHECK-MESSAGES: :[[@LINE-1]]:16: warning: prefer a lambda to std::bind + // CHECK-FIXES: auto GGG = [this] { return MemberFunctionWithReturn(1); }; + + // Test what happens when the object pointer is itself a placeholder. + auto HHH = std::bind(&D::MemberFunctionWithReturn, _1, 1); + // CHECK-MESSAGES: :[[@LINE-1]]:16: warning: prefer a lambda to std::bind + // CHECK-FIXES: auto HHH = [](auto && PH1) { return PH1->MemberFunctionWithReturn(1); }; } }; @@ -368,5 +387,5 @@ void testStdFunction(Thing *t) { if (t) cb.Reset(std::bind(UseThing, t)); // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: prefer a lambda to std::bind - // CHECK-FIXES: cb.Reset([t] { return UseThing(t); }); + // CHECK-FIXES: cb.Reset([t] { UseThing(t); }); } diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability/avoid-const-params-in-decls.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability/avoid-const-params-in-decls.cpp index d521fd238b7d5..bc098efe3044a 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/readability/avoid-const-params-in-decls.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/readability/avoid-const-params-in-decls.cpp @@ -9,15 +9,15 @@ void F1(const int i); // CHECK-FIXES: void F1(int i); void F2(const int *const i); -// CHECK-MESSAGES: :[[@LINE-1]]:9: warning: parameter 'i' is const-qualified +// CHECK-MESSAGES: :[[@LINE-1]]:20: warning: parameter 'i' is const-qualified // CHECK-FIXES: void F2(const int *i); void F3(int const i); -// CHECK-MESSAGES: :[[@LINE-1]]:9: warning: parameter 'i' is const-qualified +// CHECK-MESSAGES: :[[@LINE-1]]:13: warning: parameter 'i' is const-qualified // CHECK-FIXES: void F3(int i); void F4(alias_type const i); -// CHECK-MESSAGES: :[[@LINE-1]]:9: warning: parameter 'i' is const-qualified +// CHECK-MESSAGES: :[[@LINE-1]]:20: warning: parameter 'i' is const-qualified // CHECK-FIXES: void F4(alias_type i); void F5(const int); @@ -25,7 +25,7 @@ void F5(const int); // CHECK-FIXES: void F5(int); void F6(const int *const); -// CHECK-MESSAGES: :[[@LINE-1]]:9: warning: parameter 1 is const-qualified +// CHECK-MESSAGES: :[[@LINE-1]]:20: warning: parameter 1 is const-qualified // CHECK-FIXES: void F6(const int *); void F7(int, const int); @@ -42,7 +42,7 @@ void F9(const int long_name); // CHECK-FIXES: void F9(int long_name); void F10(const int *const *const long_name); -// CHECK-MESSAGES: :[[@LINE-1]]:10: warning: parameter 'long_name' +// CHECK-MESSAGES: :[[@LINE-1]]:28: warning: parameter 'long_name' // CHECK-FIXES: void F10(const int *const *long_name); void F11(const unsigned int /*v*/); @@ -71,11 +71,11 @@ void F15(const A Named); // CHECK-FIXES: void F15(A Named); void F16(const A *const); -// CHECK-MESSAGES: :[[@LINE-1]]:10: warning: parameter 1 is const-qualified +// CHECK-MESSAGES: :[[@LINE-1]]:30: warning: parameter 1 is const-qualified // CHECK-FIXES: void F16(const A *); void F17(const A *const Named); -// CHECK-MESSAGES: :[[@LINE-1]]:10: warning: parameter 'Named' is const-qualified +// CHECK-MESSAGES: :[[@LINE-1]]:30: warning: parameter 'Named' is const-qualified // CHECK-FIXES: void F17(const A *Named); struct Foo { diff --git a/clang-tools-extra/test/clang-tidy/infrastructure/nonstandard-file-extension.test b/clang-tools-extra/test/clang-tidy/infrastructure/nonstandard-file-extension.test index 4cb4d1171195a..9f98d86d0bcc0 100644 --- a/clang-tools-extra/test/clang-tidy/infrastructure/nonstandard-file-extension.test +++ b/clang-tools-extra/test/clang-tidy/infrastructure/nonstandard-file-extension.test @@ -3,4 +3,4 @@ const int *i; int *j; void f() { j = const_cast(i); } -// CHECK-MESSAGES: :[[@LINE-1]]:16: warning: do not use const_cast [cppcoreguidelines-pro-type-const-cast] +// CHECK-MESSAGES: :[[@LINE-1]]:16: warning: do not use const_cast to remove const qualifier [cppcoreguidelines-pro-type-const-cast] diff --git a/clang/CodeOwners.rst b/clang/CodeOwners.rst index 820cb3cccd2ea..995a2f50226a1 100644 --- a/clang/CodeOwners.rst +++ b/clang/CodeOwners.rst @@ -75,7 +75,7 @@ Modules & serialization Templates ~~~~~~~~~ | Erich Keane -| erich.keane\@intel.com (email), ErichKeane (Phabricator), erichkeane (GitHub) +| ekeane\@nvidia.com (email), ErichKeane (Phabricator), erichkeane (GitHub) Debug information @@ -174,7 +174,7 @@ compiler. Attributes ~~~~~~~~~~ | Erich Keane -| erich.keane\@intel.com (email), ErichKeane (Phabricator), erichkeane (GitHub) +| ekeane\@nvidia.com (email), ErichKeane (Phabricator), erichkeane (GitHub) Inline assembly diff --git a/clang/bindings/python/clang/cindex.py b/clang/bindings/python/clang/cindex.py index ff386d2094a0b..6a16f3a9ef6e9 100644 --- a/clang/bindings/python/clang/cindex.py +++ b/clang/bindings/python/clang/cindex.py @@ -1403,6 +1403,8 @@ def __repr__(self): CursorKind.STATIC_ASSERT = CursorKind(602) # A friend declaration CursorKind.FRIEND_DECL = CursorKind(603) +# A concept declaration +CursorKind.CONCEPT_DECL = CursorKind(604) # A code completion overload candidate. CursorKind.OVERLOAD_CANDIDATE = CursorKind(700) diff --git a/clang/docs/ClangFormatStyleOptions.rst b/clang/docs/ClangFormatStyleOptions.rst index c5c72c68ee9b8..21342e1b89ea8 100644 --- a/clang/docs/ClangFormatStyleOptions.rst +++ b/clang/docs/ClangFormatStyleOptions.rst @@ -980,6 +980,10 @@ the configuration (without a prefix: ``Auto``). **AlignTrailingComments** (``TrailingCommentsAlignmentStyle``) :versionbadge:`clang-format 3.7` :ref:`¶ ` Control of trailing comments. + The alignment stops at closing braces after a line break, and only + followed by other closing braces, a (``do-``) ``while``, a lambda call, or + a semicolon. + .. note:: @@ -1211,6 +1215,27 @@ the configuration (without a prefix: ``Auto``). return; } +.. _AllowShortCompoundRequirementOnASingleLine: + +**AllowShortCompoundRequirementOnASingleLine** (``Boolean``) :versionbadge:`clang-format 18` :ref:`¶ ` + Allow short compound requirement on a single line. + + .. code-block:: c++ + + true: + template + concept c = requires(T x) { + { x + 1 } -> std::same_as; + }; + + false: + template + concept c = requires(T x) { + { + x + 1 + } -> std::same_as; + }; + .. _AllowShortEnumsOnASingleLine: **AllowShortEnumsOnASingleLine** (``Boolean``) :versionbadge:`clang-format 11` :ref:`¶ ` @@ -5224,6 +5249,33 @@ the configuration (without a prefix: ``Auto``). void operator++ (int a); vs. void operator++(int a); object.operator++ (10); object.operator++(10); + * ``AfterPlacementOperatorStyle AfterPlacementOperator`` :versionbadge:`clang-format 18` + + Defines in which cases to put a space between ``new/delete`` operators + and opening parentheses. + + Possible values: + + * ``APO_Never`` (in configuration: ``Never``) + Remove space after ``new/delete`` operators and before ``(``. + + .. code-block:: c++ + + new(buf) T; + delete(buf) T; + + * ``APO_Always`` (in configuration: ``Always``) + Always add space after ``new/delete`` operators and before ``(``. + + .. code-block:: c++ + + new (buf) T; + delete (buf) T; + + * ``APO_Leave`` (in configuration: ``Leave``) + Leave placement ``new/delete`` expressions as they are. + + * ``bool AfterRequiresInClause`` If ``true``, put space between requires keyword in a requires clause and opening parentheses, if there is one. diff --git a/clang/docs/ClangRepl.rst b/clang/docs/ClangRepl.rst index aaaabd99bc82f..5399036c123fb 100644 --- a/clang/docs/ClangRepl.rst +++ b/clang/docs/ClangRepl.rst @@ -213,6 +213,411 @@ concept helps support advanced use cases such as template instantiations on dema automatic language interoperability. It also helps static languages such as C/C++ become apt for data science. +Execution Results Handling in Clang-Repl +======================================== + +Execution Results Handling features discussed below help extend the Clang-Repl +functionality by creating an interface between the execution results of a +program and the compiled program. + +1. **Capture Execution Results**: This feature helps capture the execution results +of a program and bring them back to the compiled program. + +2. **Dump Captured Execution Results**: This feature helps create a temporary dump +for Value Printing/Automatic Printf, that is, to display the value and type of +the captured data. + + +1. Capture Execution Results +============================ + +In many cases, it is useful to bring back the program execution result to the +compiled program. This result can be stored in an object of type **Value**. + +How Execution Results are captured (Value Synthesis): +----------------------------------------------------- + +The synthesizer chooses which expression to synthesize, and then it replaces +the original expression with the synthesized expression. Depending on the +expression type, it may choose to save an object (``LastValue``) of type 'value' +while allocating memory to it (``SetValueWithAlloc()``), or not ( +``SetValueNoAlloc()``). + +.. graphviz:: + :name: valuesynthesis + :caption: Value Synthesis + :alt: Shows how an object of type 'Value' is synthesized + :align: center + + digraph "valuesynthesis" { + rankdir="LR"; + graph [fontname="Verdana", fontsize="12"]; + node [fontname="Verdana", fontsize="12"]; + edge [fontname="Sans", fontsize="9"]; + + start [label=" Create an Object \n 'Last Value' \n of type 'Value' ", shape="note", fontcolor=white, fillcolor="#3333ff", style=filled]; + assign [label=" Assign the result \n to the 'LastValue' \n (based on respective \n Memory Allocation \n scenario) ", shape="box"] + print [label=" Pretty Print \n the Value Object ", shape="Msquare", fillcolor="yellow", style=filled]; + start -> assign; + assign -> print; + + subgraph SynthesizeExpression { + synth [label=" SynthesizeExpr() ", shape="note", fontcolor=white, fillcolor="#3333ff", style=filled]; + mem [label=" New Memory \n Allocation? ", shape="diamond"]; + withaloc [label=" SetValueWithAlloc() ", shape="box"]; + noaloc [label=" SetValueNoAlloc() ", shape="box"]; + right [label=" 1. RValue Structure \n (a temporary value)", shape="box"]; + left2 [label=" 2. LValue Structure \n (a variable with \n an address)", shape="box"]; + left3 [label=" 3. Built-In Type \n (int, float, etc.)", shape="box"]; + output [label=" move to 'Assign' step ", shape="box"]; + + synth -> mem; + mem -> withaloc [label="Yes"]; + mem -> noaloc [label="No"]; + withaloc -> right; + noaloc -> left2; + noaloc -> left3; + right -> output; + left2 -> output; + left3 -> output; + } + output -> assign + } + +Where is the captured result stored? +------------------------------------ + +``LastValue`` holds the last result of the value printing. It is a class member +because it can be accessed even after subsequent inputs. + +**Note:** If no value printing happens, then it is in an invalid state. + +Improving Efficiency and User Experience +---------------------------------------- + +The Value object is essentially used to create a mapping between an expression +'type' and the allocated 'memory'. Built-in types (bool, char, int, +float, double, etc.) are copyable. Their memory allocation size is known +and the Value object can introduce a small-buffer optimization. +In case of objects, the ``Value`` class provides reference-counted memory +management. + +The implementation maps the type as written and the Clang Type to be able to use +the preprocessor to synthesize the relevant cast operations. For example, +``X(char, Char_S)``, where ``char`` is the type from the language's type system +and ``Char_S`` is the Clang builtin type which represents it. This mapping helps +to import execution results from the interpreter in a compiled program and vice +versa. The ``Value.h`` header file can be included at runtime and this is why it +has a very low token count and was developed with strict constraints in mind. + +This also enables the user to receive the computed 'type' back in their code +and then transform the type into something else (e.g., re-cast a double into +a float). Normally, the compiler can handle these conversions transparently, +but in interpreter mode, the compiler cannot see all the 'from' and 'to' types, +so it cannot implicitly do the conversions. So this logic enables providing +these conversions on request. + +On-request conversions can help improve the user experience, by allowing +conversion to a desired 'to' type, when the 'from' type is unknown or unclear. + +Significance of this Feature +---------------------------- + +The 'Value' object enables wrapping a memory region that comes from the +JIT, and bringing it back to the compiled code (and vice versa). +This is a very useful functionality when: + +- connecting an interpreter to the compiled code, or +- connecting an interpreter in another language. + +For example, this feature helps transport values across boundaries. A notable +example is the cppyy project code makes use of this feature to enable running C++ +within Python. It enables transporting values/information between C++ +and Python. + +Note: `cppyy `_ is an automatic, run-time, +Python-to-C++ bindings generator, for calling C++ from Python and Python from C++. +It uses LLVM along with a C++ interpreter (e.g., Cling) to enable features like +run-time instantiation of C++ templates, cross-inheritance, callbacks, +auto-casting, transparent use of smart pointers, etc. + +In a nutshell, this feature enables a new way of developing code, paving the +way for language interoperability and easier interactive programming. + +Implementation Details +====================== + +Interpreter as a REPL vs. as a Library +-------------------------------------- + +1 - If we're using the interpreter in interactive (REPL) mode, it will dump +the value (i.e., value printing). + +.. code-block:: console + + if (LastValue.isValid()) { + if (!V) { + LastValue.dump(); + LastValue.clear(); + } else + *V = std::move(LastValue); + } + + +2 - If we're using the interpreter as a library, then it will pass the value +to the user. + +Incremental AST Consumer +------------------------ + +The ``IncrementalASTConsumer`` class wraps the original code generator +``ASTConsumer`` and it performs a hook, to traverse all the top-level decls, to +look for expressions to synthesize, based on the ``isSemiMissing()`` condition. + +If this condition is found to be true, then ``Interp.SynthesizeExpr()`` will be +invoked. + +**Note:** Following is a sample code snippet. Actual code may vary over time. + +.. code-block:: console + + for (Decl *D : DGR) + if (auto *TSD = llvm::dyn_cast(D); + TSD && TSD->isSemiMissing()) + TSD->setStmt(Interp.SynthesizeExpr(cast(TSD->getStmt()))); + + return Consumer->HandleTopLevelDecl(DGR); + +The synthesizer will then choose the relevant expression, based on its type. + +Communication between Compiled Code and Interpreted Code +-------------------------------------------------------- + +In Clang-Repl there is **interpreted code**, and this feature adds a 'value' +runtime that can talk to the **compiled code**. + +Following is an example where the compiled code interacts with the interpreter +code. The execution results of an expression are stored in the object 'V' of +type Value. This value is then printed, effectively helping the interpreter +use a value from the compiled code. + +.. code-block:: console + + int Global = 42; + void setGlobal(int val) { Global = val; } + int getGlobal() { return Global; } + Interp.ParseAndExecute(“void setGlobal(int val);”); + Interp.ParseAndExecute(“int getGlobal();”); + Value V; + Interp.ParseAndExecute(“getGlobal()”, &V); + std::cout << V.getAs() << “\n”; // Prints 42 + + +**Note:** Above is an example of interoperability between the compiled code and +the interpreted code. Interoperability between languages (e.g., C++ and Python) +works similarly. + + +2. Dump Captured Execution Results +================================== + +This feature helps create a temporary dump to display the value and type +(pretty print) of the desired data. This is a good way to interact with the +interpreter during interactive programming. + +How value printing is simplified (Automatic Printf) +--------------------------------------------------- + +The ``Automatic Printf`` feature makes it easy to display variable values during +program execution. Using the ``printf`` function repeatedly is not required. +This is achieved using an extension in the ``libclangInterpreter`` library. + +To automatically print the value of an expression, simply write the expression +in the global scope **without a semicolon**. + +.. graphviz:: + :name: automaticprintf + :caption: Automatic PrintF + :alt: Shows how Automatic PrintF can be used + :align: center + + digraph "AutomaticPrintF" { + size="6,4"; + rankdir="LR"; + graph [fontname="Verdana", fontsize="12"]; + node [fontname="Verdana", fontsize="12"]; + edge [fontname="Sans", fontsize="9"]; + + manual [label=" Manual PrintF ", shape="box"]; + int1 [label=" int ( &) 42 ", shape="box"] + auto [label=" Automatic PrintF ", shape="box"]; + int2 [label=" int ( &) 42 ", shape="box"] + + auto -> int2 [label="int x = 42; \n x"]; + manual -> int1 [label="int x = 42; \n printf("(int &) %d \\n", x);"]; + } + + +Significance of this feature +---------------------------- + +Inspired by a similar implementation in `Cling `_, +this feature added to upstream Clang repo has essentially extended the syntax of +C++, so that it can be more helpful for people that are writing code for data +science applications. + +This is useful, for example, when you want to experiment with a set of values +against a set of functions, and you'd like to know the results right away. +This is similar to how Python works (hence its popularity in data science +research), but the superior performance of C++, along with this flexibility +makes it a more attractive option. + +Implementation Details +====================== + +Parsing mechanism: +------------------ + +The Interpreter in Clang-Repl (``Interpreter.cpp``) includes the function +``ParseAndExecute()`` that can accept a 'Value' parameter to capture the result. +But if the value parameter is made optional and it is omitted (i.e., that the +user does not want to utilize it elsewhere), then the last value can be +validated and pushed into the ``dump()`` function. + +.. graphviz:: + :name: parsing + :caption: Parsing Mechanism + :alt: Shows the Parsing Mechanism for Pretty Printing + :align: center + + + digraph "prettyprint" { + rankdir="LR"; + graph [fontname="Verdana", fontsize="12"]; + node [fontname="Verdana", fontsize="12"]; + edge [fontname="Verdana", fontsize="9"]; + + parse [label=" ParseAndExecute() \n in Clang ", shape="box"]; + capture [label=" Capture 'Value' parameter \n for processing? ", shape="diamond"]; + use [label=" Use for processing ", shape="box"]; + dump [label=" Validate and push \n to dump()", shape="box"]; + callp [label=" call print() function ", shape="box"]; + type [label=" Print the Type \n ReplPrintTypeImpl()", shape="box"]; + data [label=" Print the Data \n ReplPrintDataImpl() ", shape="box"]; + output [label=" Output Pretty Print \n to the user ", shape="box", fontcolor=white, fillcolor="#3333ff", style=filled]; + + parse -> capture [label="Optional 'Value' Parameter"]; + capture -> use [label="Yes"]; + use -> End; + capture -> dump [label="No"]; + dump -> callp; + callp -> type; + callp -> data; + type -> output; + data -> output; + } + +**Note:** Following is a sample code snippet. Actual code may vary over time. + +.. code-block:: console + + llvm::Error Interpreter::ParseAndExecute(llvm::StringRef Code, Value *V) { + + auto PTU = Parse(Code); + if (!PTU) + return PTU.takeError(); + if (PTU->TheModule) + if (llvm::Error Err = Execute(*PTU)) + return Err; + + if (LastValue.isValid()) { + if (!V) { + LastValue.dump(); + LastValue.clear(); + } else + *V = std::move(LastValue); + } + return llvm::Error::success(); + } + +The ``dump()`` function (in ``value.cpp``) calls the ``print()`` function. + +Printing the Data and Type are handled in their respective functions: +``ReplPrintDataImpl()`` and ``ReplPrintTypeImpl()``. + +Annotation Token (annot_repl_input_end) +--------------------------------------- + +This feature uses a new token (``annot_repl_input_end``) to consider printing the +value of an expression if it doesn't end with a semicolon. When parsing an +Expression Statement, if the last semicolon is missing, then the code will +pretend that there one and set a marker there for later utilization, and +continue parsing. + +A semicolon is normally required in C++, but this feature expands the C++ +syntax to handle cases where a missing semicolon is expected (i.e., when +handling an expression statement). It also makes sure that an error is not +generated for the missing semicolon in this specific case. + +This is accomplished by identifying the end position of the user input +(expression statement). This helps store and return the expression statement +effectively, so that it can be printed (displayed to the user automatically). + +**Note:** This logic is only available for C++ for now, since part of the +implementation itself requires C++ features. Future versions may support more +languages. + +.. code-block:: console + + Token *CurTok = nullptr; + // If the semicolon is missing at the end of REPL input, consider if + // we want to do value printing. Note this is only enabled in C++ mode + // since part of the implementation requires C++ language features. + // Note we shouldn't eat the token since the callback needs it. + if (Tok.is(tok::annot_repl_input_end) && Actions.getLangOpts().CPlusPlus) + CurTok = &Tok; + else + // Otherwise, eat the semicolon. + ExpectAndConsumeSemi(diag::err_expected_semi_after_expr); + + StmtResult R = handleExprStmt(Expr, StmtCtx); + if (CurTok && !R.isInvalid()) + CurTok->setAnnotationValue(R.get()); + + return R; + } + +AST Transformation +------------------- + +When Sema encounters the ``annot_repl_input_end`` token, it knows to transform +the AST before the real CodeGen process. It will consume the token and set a +'semi missing' bit in the respective decl. + +.. code-block:: console + + if (Tok.is(tok::annot_repl_input_end) && + Tok.getAnnotationValue() != nullptr) { + ConsumeAnnotationToken(); + cast(DeclsInGroup.back())->setSemiMissing(); + } + +In the AST Consumer, traverse all the Top Level Decls, to look for expressions +to synthesize. If the current Decl is the Top Level Statement +Decl(``TopLevelStmtDecl``) and has a semicolon missing, then ask the interpreter +to synthesize another expression (an internal function call) to replace this +original expression. + + +Detailed RFC and Discussion: +---------------------------- + +For more technical details, community discussion and links to patches related +to these features, +Please visit: `RFC on LLVM Discourse `_. + +Some logic presented in the RFC (e.g. ValueGetter()) may be outdated, +compared to the final developed solution. Related Reading =============== diff --git a/clang/docs/HowToSetupToolingForLLVM.rst b/clang/docs/HowToSetupToolingForLLVM.rst index 62189511aeb2a..dc1c17b0ae68d 100644 --- a/clang/docs/HowToSetupToolingForLLVM.rst +++ b/clang/docs/HowToSetupToolingForLLVM.rst @@ -172,7 +172,7 @@ Examples: clang::ASTConsumer *newASTConsumer() (CompoundStmt 0x44da290 (IfStmt 0x44d97c8 <<>> - (ImplicitCastExpr 0x44d96d0 '_Bool':'_Bool' + (ImplicitCastExpr 0x44d96d0 '_Bool' ... $ clang-check tools/clang/tools/clang-check/ClangCheck.cpp -ast-print -ast-dump-filter ActionFactory::newASTConsumer Processing: tools/clang/tools/clang-check/ClangCheck.cpp. diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index fc8caf9221b9d..bc28bb567f693 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -43,8 +43,8 @@ C/C++ Language Potentially Breaking Changes - The default extension name for PCH generation (``-c -xc-header`` and ``-c -xc++-header``) is now ``.pch`` instead of ``.gch``. -- ``-include a.h`` probing ``a.h.gch`` is deprecated. Change the extension name - to ``.pch`` or use ``-include-pch a.h.gch``. +- ``-include a.h`` probing ``a.h.gch`` will now ignore ``a.h.gch`` if it is not + a clang pch file or a directory containing any clang pch file. - Fixed a bug that caused ``__has_cpp_attribute`` and ``__has_c_attribute`` return incorrect values for some C++-11-style attributes. Below is a complete list of behavior changes. @@ -64,6 +64,10 @@ C/C++ Language Potentially Breaking Changes ``__has_c_attribute(warn_unused_result)``, 202003, 0 ``__has_c_attribute(gnu::warn_unused_result)``, 202003, 1 +- Fixed a bug in finding matching `operator!=` while adding reversed `operator==` as + outlined in "The Equality Operator You Are Looking For" (`P2468 `_). + Fixes (`#68901: `_). + C++ Specific Potentially Breaking Changes ----------------------------------------- - The name mangling rules for function templates has been changed to take into @@ -100,11 +104,37 @@ C++ Specific Potentially Breaking Changes system headers and macros. It will be turned into a hard (non-downgradable) error in the next Clang release. +- The flag `-fdelayed-template-parsing` won't be enabled by default with C++20 + when targetting MSVC to match the behavior of MSVC. + (`MSVC Docs `_) + ABI Changes in This Version --------------------------- - Following the SystemV ABI for x86-64, ``__int128`` arguments will no longer be split between a register and a stack slot. +AST Dumping Potentially Breaking Changes +---------------------------------------- +- When dumping a sugared type, Clang will no longer print the desugared type if + its textual representation is the same as the sugared one. This applies to + both text dumps of the form ``'foo':'foo'`` which will now be dumped as just + ``'foo'``, and JSON dumps of the form: + + .. code-block:: json + + "type": { + "qualType": "foo", + "desugaredQualType": "foo" + } + + which will now be dumped as just: + + .. code-block:: json + + "type": { + "qualType": "foo" + } + What's New in Clang |release|? ============================== Some of the major new features and improvements to Clang are listed @@ -177,7 +207,7 @@ C23 Feature Support - Clang now supports ``N3007 Type inference for object definitions``. - Clang now supports ```` which defines several macros for performing - checked integer arithmetic. + checked integer arithmetic. It is also exposed in pre-C23 modes. Non-comprehensive list of changes in this release ------------------------------------------------- @@ -203,9 +233,6 @@ New Compiler Flags the preprocessed text to the output. This can greatly reduce the size of the preprocessed output, which can be helpful when trying to reduce a test case. -* ``-Wbitfield-conversion`` was added to detect assignments of integral - types to a bitfield that may change the value. - Deprecated Compiler Flags ------------------------- @@ -243,6 +270,24 @@ Attribute Changes in Clang supports but that are never the result of default argument promotion, such as ``float``. (`#59824: `_) +- Clang now supports ``[[clang::preferred_type(type-name)]]`` as an attribute + which can be applied to a bit-field. This attribute helps to map a bit-field + back to a particular type that may be better-suited to representing the bit- + field but cannot be used for other reasons and will impact the debug + information generated for the bit-field. This is most useful when mapping a + bit-field of basic integer type back to a ``bool`` or an enumeration type, + e.g., + + .. code-block:: c++ + + enum E { Apple, Orange, Pear }; + struct S { + [[clang::preferred_type(E)]] unsigned FruitKind : 2; + }; + + When viewing ``S::FruitKind`` in a debugger, it will behave as if the member + was declared as type ``E`` rather than ``unsigned``. + Improvements to Clang's diagnostics ----------------------------------- - Clang constexpr evaluator now prints template arguments when displaying @@ -325,6 +370,62 @@ Improvements to Clang's diagnostics | ~~~~~~~~~^~~~~~~~ - Clang now always diagnoses when using non-standard layout types in ``offsetof`` . (`#64619: `_) +- Clang now diagnoses redefined defaulted constructor when redefined + defaulted constructor with different exception specs. + (`#69094: `_) +- Clang now diagnoses use of variable-length arrays in C++ by default (and + under ``-Wall`` in GNU++ mode). This is an extension supported by Clang and + GCC, but is very easy to accidentally use without realizing it's a + nonportable construct that has different semantics from a constant-sized + array. (`#62836 `_) + +- Clang changed the order in which it displays candidate functions on overloading failures. + Previously, Clang used definition of ordering from the C++ Standard. The order defined in + the Standard is partial and is not suited for sorting. Instead, Clang now uses a strict + order that still attempts to push more relevant functions to the top by comparing their + corresponding conversions. In some cases, this results in better order. E.g., for the + following code + + .. code-block:: cpp + + struct Foo { + operator int(); + operator const char*(); + }; + + void test() { Foo() - Foo(); } + + Clang now produces a list with two most relevant builtin operators at the top, + i.e. ``operator-(int, int)`` and ``operator-(const char*, const char*)``. + Previously ``operator-(const char*, const char*)`` was the first element, + but ``operator-(int, int)`` was only the 13th element in the output. + However, new implementation does not take into account some aspects of + C++ semantics, e.g. which function template is more specialized. This + can sometimes lead to worse ordering. + + +- When describing a warning/error in a function-style type conversion Clang underlines only until + the end of the expression we convert from. Now Clang underlines until the closing parenthesis. + + Before: + + .. code-block:: text + + warning: cast from 'long (*)(const int &)' to 'decltype(fun_ptr)' (aka 'long (*)(int &)') converts to incompatible function type [-Wcast-function-type-strict] + 24 | return decltype(fun_ptr)( f_ptr /*comment*/); + | ^~~~~~~~~~~~~~~~~~~~~~~~ + + After: + + .. code-block:: text + + warning: cast from 'long (*)(const int &)' to 'decltype(fun_ptr)' (aka 'long (*)(int &)') converts to incompatible function type [-Wcast-function-type-strict] + 24 | return decltype(fun_ptr)( f_ptr /*comment*/); + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- ``-Wzero-as-null-pointer-constant`` diagnostic is no longer emitted when using ``__null`` + (or, more commonly, ``NULL`` when the platform defines it as ``__null``) to be more consistent + with GCC. Bug Fixes in This Version ------------------------- @@ -402,6 +503,10 @@ Bug Fixes in This Version cannot be used with ``Release`` mode builds. (`#68237 `_). - Fix crash in evaluating ``constexpr`` value for invalid template function. Fixes (`#68542 `_) +- Clang will correctly evaluate ``noexcept`` expression for template functions + of template classes. Fixes + (`#68543 `_, + `#42496 `_) - Fixed an issue when a shift count larger than ``__INT64_MAX__``, in a right shift operation, could result in missing warnings about ``shift count >= width of type`` or internal compiler error. @@ -412,6 +517,22 @@ Bug Fixes in This Version - Clang no longer permits using the `_BitInt` types as an underlying type for an enumeration as specified in the C23 Standard. Fixes (`#69619 `_) +- Fixed an issue when a shift count specified by a small constant ``_BitInt()``, + in a left shift operation, could result in a faulty warnings about + ``shift count >= width of type``. +- Clang now accepts anonymous members initialized with designated initializers + inside templates. + Fixes (`#65143 `_) +- Fix crash in formatting the real/imaginary part of a complex lvalue. + Fixes (`#69218 `_) +- No longer use C++ ``thread_local`` semantics in C23 when using + ``thread_local`` instead of ``_Thread_local``. + Fixes (`#70068 `_) and + (`#69167 `_) +- Fix crash in evaluating invalid lambda expression which forget capture this. + Fixes (`#67687 `_) +- Fix crash from constexpr evaluator evaluating uninitialized arrays as rvalue. + Fixes (`#67317 `_) Bug Fixes to Compiler Builtins ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -536,6 +657,19 @@ Bug Fixes to C++ Support declaration definition. Fixes: (`#61763 `_) +- Fix a bug where implicit deduction guides are not correctly generated for nested template + classes. Fixes: + (`#46200 `_) + (`#57812 `_) + +- Diagnose use of a variable-length array in a coroutine. The design of + coroutines is such that it is not possible to support VLA use. Fixes: + (`#65858 `_) + +- Fix bug where we were overriding zero-initialization of class members when + default initializing a base class in a constant expression context. Fixes: + (`#69890 `_) + Bug Fixes to AST Handling ^^^^^^^^^^^^^^^^^^^^^^^^^ - Fixed an import failure of recursive friend class template. @@ -546,6 +680,9 @@ Bug Fixes to AST Handling `Issue 64170 `_ - Fixed ``hasAnyBase`` not binding nodes in its submatcher. (`#65421 `_) +- Fixed a bug where RecursiveASTVisitor fails to visit the + initializer of a bitfield. + `Issue 64916 `_ Miscellaneous Bug Fixes ^^^^^^^^^^^^^^^^^^^^^^^ @@ -585,6 +722,11 @@ X86 Support Arm and AArch64 Support ^^^^^^^^^^^^^^^^^^^^^^^ +- C++ function name mangling has been changed to align with the specification + (https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst). + This affects C++ functions with SVE ACLE parameters. Clang will use the old + manglings if ``-fclang-abi-compat=17`` or lower is specified. + Android Support ^^^^^^^^^^^^^^^ @@ -677,6 +819,8 @@ AST Matchers clang-format ------------ - Add ``AllowBreakBeforeNoexceptSpecifier`` option. +- Add ``AllowShortCompoundRequirementOnASingleLine`` option. +- Change ``BreakAfterAttributes`` from ``Never`` to ``Leave`` in LLVM style. libclang -------- diff --git a/clang/docs/StandardCPlusPlusModules.rst b/clang/docs/StandardCPlusPlusModules.rst index 8dd86edc64a80..4970457574030 100644 --- a/clang/docs/StandardCPlusPlusModules.rst +++ b/clang/docs/StandardCPlusPlusModules.rst @@ -365,6 +365,10 @@ the above example could be rewritten into: $ clang++ -std=c++20 M.cppm --precompile -fmodule-file=M:interface_part=M-interface_part.pcm -fmodule-file=M:impl_part=M-impl_part.pcm -o M.pcm +When there are multiple ``-fmodule-file==`` options for the same +````, the last ``-fmodule-file==`` will override the previous +``-fmodule-file==`` options. + ``-fprebuilt-module-path`` is more convenient and ``-fmodule-file`` is faster since it saves time for file lookup. diff --git a/clang/docs/analyzer/checkers.rst b/clang/docs/analyzer/checkers.rst index 597ffcc4a10a2..43137f4b020f9 100644 --- a/clang/docs/analyzer/checkers.rst +++ b/clang/docs/analyzer/checkers.rst @@ -2520,13 +2520,34 @@ pointer. These functions include: getenv, localeconv, asctime, setlocale, strerr char *p, *pp; p = getenv("VAR"); - pp = getenv("VAR2"); - // subsequent call to 'getenv' invalidated previous one + setenv("SOMEVAR", "VALUE", /*overwrite = */1); + // call to 'setenv' may invalidate p *p; // dereferencing invalid pointer } + +The ``InvalidatingGetEnv`` option is available for treating getenv calls as +invalidating. When enabled, the checker issues a warning if getenv is called +multiple times and their results are used without first creating a copy. +This level of strictness might be considered overly pedantic for the commonly +used getenv implementations. + +To enable this option, use: +``-analyzer-config alpha.security.cert.env.InvalidPtr:InvalidatingGetEnv=true``. + +By default, this option is set to *false*. + +When this option is enabled, warnings will be generated for scenarios like the +following: + +.. code-block:: c + + char* p = getenv("VAR"); + char* pp = getenv("VAR2"); // assumes this call can invalidate `env` + strlen(p); // warns about accessing invalid ptr + alpha.security.taint ^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/docs/conf.py b/clang/docs/conf.py index ca310026f53e2..31a4daa39d5b8 100644 --- a/clang/docs/conf.py +++ b/clang/docs/conf.py @@ -27,7 +27,7 @@ # Add any Sphinx extension module names here, as strings. They can be extensions # coming with Sphinx (named 'sphinx.ext.*') or your custom ones. -extensions = ["sphinx.ext.todo", "sphinx.ext.mathjax"] +extensions = ["sphinx.ext.todo", "sphinx.ext.mathjax", "sphinx.ext.graphviz"] # Add any paths that contain templates here, relative to this directory. templates_path = ["_templates"] diff --git a/clang/docs/tools/clang-formatted-files.txt b/clang/docs/tools/clang-formatted-files.txt index 16f84727117e2..48cd800bffd00 100644 --- a/clang/docs/tools/clang-formatted-files.txt +++ b/clang/docs/tools/clang-formatted-files.txt @@ -6813,7 +6813,6 @@ llvm/lib/Target/X86/X86LoadValueInjectionRetHardening.cpp llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp llvm/lib/Target/X86/X86LowerAMXType.cpp llvm/lib/Target/X86/X86LowerTileCopy.cpp -llvm/lib/Target/X86/X86PreAMXConfig.cpp llvm/lib/Target/X86/X86PreTileConfig.cpp llvm/lib/Target/X86/X86RegisterBankInfo.h llvm/lib/Target/X86/X86ShuffleDecodeConstantPool.cpp diff --git a/clang/docs/tools/dump_format_style.py b/clang/docs/tools/dump_format_style.py index 270ac34c03b39..75d4a044ef19f 100755 --- a/clang/docs/tools/dump_format_style.py +++ b/clang/docs/tools/dump_format_style.py @@ -143,11 +143,18 @@ def __str__(self): class NestedField(object): - def __init__(self, name, comment): + def __init__(self, name, comment, version): self.name = name self.comment = comment.strip() + self.version = version def __str__(self): + if self.version: + return "\n* ``%s`` :versionbadge:`clang-format %s`\n%s" % ( + self.name, + self.version, + doxygen2rst(indent(self.comment, 2, indent_first_line=False)), + ) return "\n* ``%s`` %s" % ( self.name, doxygen2rst(indent(self.comment, 2, indent_first_line=False)), @@ -165,18 +172,28 @@ def __str__(self): class NestedEnum(object): - def __init__(self, name, enumtype, comment, values): + def __init__(self, name, enumtype, comment, version, values): self.name = name self.comment = comment self.values = values self.type = enumtype + self.version = version def __str__(self): - s = "\n* ``%s %s``\n%s" % ( - to_yaml_type(self.type), - self.name, - doxygen2rst(indent(self.comment, 2)), - ) + s = "" + if self.version: + s = "\n* ``%s %s`` :versionbadge:`clang-format %s`\n\n%s" % ( + to_yaml_type(self.type), + self.name, + self.version, + doxygen2rst(indent(self.comment, 2)), + ) + else: + s = "\n* ``%s %s``\n%s" % ( + to_yaml_type(self.type), + self.name, + doxygen2rst(indent(self.comment, 2)), + ) s += indent("\nPossible values:\n\n", 2) s += indent("\n".join(map(str, self.values)), 2) return s @@ -278,7 +295,9 @@ class State: InFieldComment, InEnum, InEnumMemberComment, - ) = range(8) + InNestedEnum, + InNestedEnumMemberComment, + ) = range(10) state = State.BeforeStruct @@ -344,27 +363,38 @@ class State: state = State.InStruct nested_structs[nested_struct.name] = nested_struct elif state == State.InNestedFieldComment: - if line.startswith("///"): + if line.startswith(r"/// \version"): + match = re.match(r"/// \\version\s*(?P[0-9.]+)*", line) + if match: + version = match.group("version") + elif line.startswith("///"): comment += self.__clean_comment_line(line) + elif line.startswith("enum"): + state = State.InNestedEnum + name = re.sub(r"enum\s+(\w+)\s*(:((\s*\w+)+)\s*)?\{", "\\1", line) + enum = Enum(name, comment) else: state = State.InNestedStruct field_type, field_name = re.match( r"([<>:\w(,\s)]+)\s+(\w+);", line ).groups() + # if not version: + # self.__warning(f"missing version for {field_name}", line) if field_type in enums: nested_struct.values.append( NestedEnum( field_name, field_type, comment, + version, enums[field_type].values, ) ) else: nested_struct.values.append( - NestedField(field_type + " " + field_name, comment) + NestedField(field_type + " " + field_name, comment, version) ) - + version = None elif state == State.InEnum: if line.startswith("///"): state = State.InEnumMemberComment @@ -376,6 +406,17 @@ class State: # Enum member without documentation. Must be documented where the enum # is used. pass + elif state == State.InNestedEnum: + if line.startswith("///"): + state = State.InNestedEnumMemberComment + comment = self.__clean_comment_line(line) + elif line == "};": + state = State.InNestedStruct + enums[enum.name] = enum + else: + # Enum member without documentation. Must be + # documented where the enum is used. + pass elif state == State.InEnumMemberComment: if line.startswith("///"): comment += self.__clean_comment_line(line) @@ -389,6 +430,19 @@ class State: else: config = val enum.values.append(EnumValue(val, comment, config)) + elif state == State.InNestedEnumMemberComment: + if line.startswith("///"): + comment += self.__clean_comment_line(line) + else: + state = State.InNestedEnum + val = line.replace(",", "") + pos = val.find(" // ") + if pos != -1: + config = val[pos + 4 :] + val = val[:pos] + else: + config = val + enum.values.append(EnumValue(val, comment, config)) if state != State.Finished: raise Exception("Not finished by the end of file") diff --git a/clang/include/clang/APINotes/APINotesReader.h b/clang/include/clang/APINotes/APINotesReader.h new file mode 100644 index 0000000000000..1c5aab0959550 --- /dev/null +++ b/clang/include/clang/APINotes/APINotesReader.h @@ -0,0 +1,200 @@ +//===--- APINotesReader.h - API Notes Reader --------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines the \c APINotesReader class that reads source API notes +// data providing additional information about source code as a separate input, +// such as the non-nil/nilable annotations for method parameters. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_APINOTES_READER_H +#define LLVM_CLANG_APINOTES_READER_H + +#include "clang/APINotes/Types.h" +#include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/VersionTuple.h" +#include + +namespace clang { +namespace api_notes { + +/// A class that reads API notes data from a binary file that was written by +/// the \c APINotesWriter. +class APINotesReader { + class Implementation; + std::unique_ptr Implementation; + + APINotesReader(llvm::MemoryBuffer *InputBuffer, + llvm::VersionTuple SwiftVersion, bool &Failed); + +public: + /// Create a new API notes reader from the given member buffer, which + /// contains the contents of a binary API notes file. + /// + /// \returns the new API notes reader, or null if an error occurred. + static std::unique_ptr + Create(std::unique_ptr InputBuffer, + llvm::VersionTuple SwiftVersion); + + ~APINotesReader(); + + APINotesReader(const APINotesReader &) = delete; + APINotesReader &operator=(const APINotesReader &) = delete; + + /// Captures the completed versioned information for a particular part of + /// API notes, including both unversioned API notes and each versioned API + /// note for that particular entity. + template class VersionedInfo { + /// The complete set of results. + llvm::SmallVector, 1> Results; + + /// The index of the result that is the "selected" set based on the desired + /// Swift version, or null if nothing matched. + std::optional Selected; + + public: + /// Form an empty set of versioned information. + VersionedInfo(std::nullopt_t) : Selected(std::nullopt) {} + + /// Form a versioned info set given the desired version and a set of + /// results. + VersionedInfo( + llvm::VersionTuple Version, + llvm::SmallVector, 1> Results); + + /// Retrieve the selected index in the result set. + std::optional getSelected() const { return Selected; } + + /// Return the number of versioned results we know about. + unsigned size() const { return Results.size(); } + + /// Access all versioned results. + const std::pair *begin() const { + assert(!Results.empty()); + return Results.begin(); + } + const std::pair *end() const { + return Results.end(); + } + + /// Access a specific versioned result. + const std::pair &operator[](unsigned index) const { + assert(index < Results.size()); + return Results[index]; + } + }; + + /// Look for the context ID of the given Objective-C class. + /// + /// \param Name The name of the class we're looking for. + /// + /// \returns The ID, if known. + std::optional lookupObjCClassID(llvm::StringRef Name); + + /// Look for information regarding the given Objective-C class. + /// + /// \param Name The name of the class we're looking for. + /// + /// \returns The information about the class, if known. + VersionedInfo lookupObjCClassInfo(llvm::StringRef Name); + + /// Look for the context ID of the given Objective-C protocol. + /// + /// \param Name The name of the protocol we're looking for. + /// + /// \returns The ID of the protocol, if known. + std::optional lookupObjCProtocolID(llvm::StringRef Name); + + /// Look for information regarding the given Objective-C protocol. + /// + /// \param Name The name of the protocol we're looking for. + /// + /// \returns The information about the protocol, if known. + VersionedInfo lookupObjCProtocolInfo(llvm::StringRef Name); + + /// Look for information regarding the given Objective-C property in + /// the given context. + /// + /// \param CtxID The ID that references the context we are looking for. + /// \param Name The name of the property we're looking for. + /// \param IsInstance Whether we are looking for an instance property (vs. + /// a class property). + /// + /// \returns Information about the property, if known. + VersionedInfo + lookupObjCProperty(ContextID CtxID, llvm::StringRef Name, bool IsInstance); + + /// Look for information regarding the given Objective-C method in + /// the given context. + /// + /// \param CtxID The ID that references the context we are looking for. + /// \param Selector The selector naming the method we're looking for. + /// \param IsInstanceMethod Whether we are looking for an instance method. + /// + /// \returns Information about the method, if known. + VersionedInfo lookupObjCMethod(ContextID CtxID, + ObjCSelectorRef Selector, + bool IsInstanceMethod); + + /// Look for information regarding the given global variable. + /// + /// \param Name The name of the global variable. + /// + /// \returns information about the global variable, if known. + VersionedInfo + lookupGlobalVariable(llvm::StringRef Name, + std::optional Ctx = std::nullopt); + + /// Look for information regarding the given global function. + /// + /// \param Name The name of the global function. + /// + /// \returns information about the global function, if known. + VersionedInfo + lookupGlobalFunction(llvm::StringRef Name, + std::optional Ctx = std::nullopt); + + /// Look for information regarding the given enumerator. + /// + /// \param Name The name of the enumerator. + /// + /// \returns information about the enumerator, if known. + VersionedInfo lookupEnumConstant(llvm::StringRef Name); + + /// Look for information regarding the given tag + /// (struct/union/enum/C++ class). + /// + /// \param Name The name of the tag. + /// + /// \returns information about the tag, if known. + VersionedInfo lookupTag(llvm::StringRef Name, + std::optional Ctx = std::nullopt); + + /// Look for information regarding the given typedef. + /// + /// \param Name The name of the typedef. + /// + /// \returns information about the typedef, if known. + VersionedInfo + lookupTypedef(llvm::StringRef Name, + std::optional Ctx = std::nullopt); + + /// Look for the context ID of the given C++ namespace. + /// + /// \param Name The name of the class we're looking for. + /// + /// \returns The ID, if known. + std::optional + lookupNamespaceID(llvm::StringRef Name, + std::optional ParentNamespaceID = std::nullopt); +}; + +} // end namespace api_notes +} // end namespace clang + +#endif // LLVM_CLANG_APINOTES_READER_H diff --git a/clang/include/clang/APINotes/Types.h b/clang/include/clang/APINotes/Types.h index 354458588e309..b74244bc8f1cb 100644 --- a/clang/include/clang/APINotes/Types.h +++ b/clang/include/clang/APINotes/Types.h @@ -144,16 +144,10 @@ class CommonTypeInfo : public CommonEntityInfo { return SwiftBridge; } - void setSwiftBridge(const std::optional &SwiftType) { + void setSwiftBridge(std::optional SwiftType) { SwiftBridge = SwiftType; } - void setSwiftBridge(const std::optional &SwiftType) { - SwiftBridge = SwiftType - ? std::optional(std::string(*SwiftType)) - : std::nullopt; - } - const std::optional &getNSErrorDomain() const { return NSErrorDomain; } diff --git a/clang/include/clang/ARCMigrate/FileRemapper.h b/clang/include/clang/ARCMigrate/FileRemapper.h index ceb3e67b50352..afcee363516a2 100644 --- a/clang/include/clang/ARCMigrate/FileRemapper.h +++ b/clang/include/clang/ARCMigrate/FileRemapper.h @@ -12,10 +12,10 @@ #include "clang/Basic/FileEntry.h" #include "clang/Basic/LLVM.h" #include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/PointerUnion.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringRef.h" #include +#include namespace llvm { class MemoryBuffer; @@ -33,7 +33,7 @@ class FileRemapper { // FIXME: Reuse the same FileManager for multiple ASTContexts. std::unique_ptr FileMgr; - typedef llvm::PointerUnion Target; + using Target = std::variant; using MappingsTy = llvm::DenseMap; MappingsTy FromToMappings; diff --git a/clang/include/clang/AST/DeclBase.h b/clang/include/clang/AST/DeclBase.h index d383e46e22e16..978e4255e877e 100644 --- a/clang/include/clang/AST/DeclBase.h +++ b/clang/include/clang/AST/DeclBase.h @@ -1515,16 +1515,14 @@ class DeclContext { uint64_t IsThisDeclarationADemotedDefinition : 1; }; - /// Number of non-inherited bits in TagDeclBitfields. - enum { NumTagDeclBits = 10 }; + /// Number of inherited and non-inherited bits in TagDeclBitfields. + enum { NumTagDeclBits = NumDeclContextBits + 10 }; /// Stores the bits used by EnumDecl. /// If modified NumEnumDeclBit and the accessor /// methods in EnumDecl should be updated appropriately. class EnumDeclBitfields { friend class EnumDecl; - /// For the bits in DeclContextBitfields. - uint64_t : NumDeclContextBits; /// For the bits in TagDeclBitfields. uint64_t : NumTagDeclBits; @@ -1554,16 +1552,14 @@ class DeclContext { uint64_t HasODRHash : 1; }; - /// Number of non-inherited bits in EnumDeclBitfields. - enum { NumEnumDeclBits = 20 }; + /// Number of inherited and non-inherited bits in EnumDeclBitfields. + enum { NumEnumDeclBits = NumTagDeclBits + 20 }; /// Stores the bits used by RecordDecl. /// If modified NumRecordDeclBits and the accessor /// methods in RecordDecl should be updated appropriately. class RecordDeclBitfields { friend class RecordDecl; - /// For the bits in DeclContextBitfields. - uint64_t : NumDeclContextBits; /// For the bits in TagDeclBitfields. uint64_t : NumTagDeclBits; @@ -1615,8 +1611,8 @@ class DeclContext { uint64_t ODRHash : 26; }; - /// Number of non-inherited bits in RecordDeclBitfields. - enum { NumRecordDeclBits = 41 }; + /// Number of inherited and non-inherited bits in RecordDeclBitfields. + enum { NumRecordDeclBits = NumTagDeclBits + 41 }; /// Stores the bits used by OMPDeclareReductionDecl. /// If modified NumOMPDeclareReductionDeclBits and the accessor @@ -1631,8 +1627,9 @@ class DeclContext { uint64_t InitializerKind : 2; }; - /// Number of non-inherited bits in OMPDeclareReductionDeclBitfields. - enum { NumOMPDeclareReductionDeclBits = 2 }; + /// Number of inherited and non-inherited bits in + /// OMPDeclareReductionDeclBitfields. + enum { NumOMPDeclareReductionDeclBits = NumDeclContextBits + 2 }; /// Stores the bits used by FunctionDecl. /// If modified NumFunctionDeclBits and the accessor @@ -1711,16 +1708,14 @@ class DeclContext { uint64_t FriendConstraintRefersToEnclosingTemplate : 1; }; - /// Number of non-inherited bits in FunctionDeclBitfields. - enum { NumFunctionDeclBits = 31 }; + /// Number of inherited and non-inherited bits in FunctionDeclBitfields. + enum { NumFunctionDeclBits = NumDeclContextBits + 31 }; /// Stores the bits used by CXXConstructorDecl. If modified /// NumCXXConstructorDeclBits and the accessor /// methods in CXXConstructorDecl should be updated appropriately. class CXXConstructorDeclBitfields { friend class CXXConstructorDecl; - /// For the bits in DeclContextBitfields. - uint64_t : NumDeclContextBits; /// For the bits in FunctionDeclBitfields. uint64_t : NumFunctionDeclBits; @@ -1739,10 +1734,8 @@ class DeclContext { uint64_t IsSimpleExplicit : 1; }; - /// Number of non-inherited bits in CXXConstructorDeclBitfields. - enum { - NumCXXConstructorDeclBits = 64 - NumDeclContextBits - NumFunctionDeclBits - }; + /// Number of inherited and non-inherited bits in CXXConstructorDeclBitfields. + enum { NumCXXConstructorDeclBits = NumFunctionDeclBits + 20 }; /// Stores the bits used by ObjCMethodDecl. /// If modified NumObjCMethodDeclBits and the accessor @@ -1803,8 +1796,8 @@ class DeclContext { uint64_t HasSkippedBody : 1; }; - /// Number of non-inherited bits in ObjCMethodDeclBitfields. - enum { NumObjCMethodDeclBits = 24 }; + /// Number of inherited and non-inherited bits in ObjCMethodDeclBitfields. + enum { NumObjCMethodDeclBits = NumDeclContextBits + 24 }; /// Stores the bits used by ObjCContainerDecl. /// If modified NumObjCContainerDeclBits and the accessor @@ -1819,10 +1812,10 @@ class DeclContext { SourceLocation AtStart; }; - /// Number of non-inherited bits in ObjCContainerDeclBitfields. + /// Number of inherited and non-inherited bits in ObjCContainerDeclBitfields. /// Note that here we rely on the fact that SourceLocation is 32 bits /// wide. We check this with the static_assert in the ctor of DeclContext. - enum { NumObjCContainerDeclBits = 64 - NumDeclContextBits }; + enum { NumObjCContainerDeclBits = 64 }; /// Stores the bits used by LinkageSpecDecl. /// If modified NumLinkageSpecDeclBits and the accessor @@ -1843,8 +1836,8 @@ class DeclContext { uint64_t HasBraces : 1; }; - /// Number of non-inherited bits in LinkageSpecDeclBitfields. - enum { NumLinkageSpecDeclBits = 4 }; + /// Number of inherited and non-inherited bits in LinkageSpecDeclBitfields. + enum { NumLinkageSpecDeclBits = NumDeclContextBits + 4 }; /// Stores the bits used by BlockDecl. /// If modified NumBlockDeclBits and the accessor @@ -1869,8 +1862,8 @@ class DeclContext { uint64_t CanAvoidCopyToHeap : 1; }; - /// Number of non-inherited bits in BlockDeclBitfields. - enum { NumBlockDeclBits = 5 }; + /// Number of inherited and non-inherited bits in BlockDeclBitfields. + enum { NumBlockDeclBits = NumDeclContextBits + 5 }; /// Pointer to the data structure used to lookup declarations /// within this context (or a DependentStoredDeclsMap if this is a diff --git a/clang/include/clang/AST/DeclarationName.h b/clang/include/clang/AST/DeclarationName.h index b06931ea3e418..c9b01dc53964b 100644 --- a/clang/include/clang/AST/DeclarationName.h +++ b/clang/include/clang/AST/DeclarationName.h @@ -362,7 +362,8 @@ class DeclarationName { } /// Construct a declaration name from an Objective-C selector. - DeclarationName(Selector Sel) : Ptr(Sel.InfoPtr) {} + DeclarationName(Selector Sel) + : Ptr(reinterpret_cast(Sel.InfoPtr.getOpaqueValue())) {} /// Returns the name for all C++ using-directives. static DeclarationName getUsingDirectiveName() { diff --git a/clang/include/clang/AST/OpenMPClause.h b/clang/include/clang/AST/OpenMPClause.h index eeeca1998f9fa..549f12e87df59 100644 --- a/clang/include/clang/AST/OpenMPClause.h +++ b/clang/include/clang/AST/OpenMPClause.h @@ -3918,6 +3918,9 @@ class OMPLinearClause final /// Location of ':'. SourceLocation ColonLoc; + /// Location of 'step' modifier. + SourceLocation StepModifierLoc; + /// Sets the linear step for clause. void setStep(Expr *Step) { *(getFinals().end()) = Step; } @@ -3929,16 +3932,18 @@ class OMPLinearClause final /// \param StartLoc Starting location of the clause. /// \param LParenLoc Location of '('. /// \param ColonLoc Location of ':'. + /// \param StepModifierLoc Location of 'step' modifier. /// \param EndLoc Ending location of the clause. /// \param NumVars Number of variables. OMPLinearClause(SourceLocation StartLoc, SourceLocation LParenLoc, OpenMPLinearClauseKind Modifier, SourceLocation ModifierLoc, - SourceLocation ColonLoc, SourceLocation EndLoc, - unsigned NumVars) + SourceLocation ColonLoc, SourceLocation StepModifierLoc, + SourceLocation EndLoc, unsigned NumVars) : OMPVarListClause(llvm::omp::OMPC_linear, StartLoc, LParenLoc, EndLoc, NumVars), OMPClauseWithPostUpdate(this), Modifier(Modifier), - ModifierLoc(ModifierLoc), ColonLoc(ColonLoc) {} + ModifierLoc(ModifierLoc), ColonLoc(ColonLoc), + StepModifierLoc(StepModifierLoc) {} /// Build an empty clause. /// @@ -4017,6 +4022,7 @@ class OMPLinearClause final /// \param Modifier Modifier of 'linear' clause. /// \param ModifierLoc Modifier location. /// \param ColonLoc Location of ':'. + /// \param StepModifierLoc Location of 'step' modifier. /// \param EndLoc Ending location of the clause. /// \param VL List of references to the variables. /// \param PL List of private copies of original variables. @@ -4030,9 +4036,10 @@ class OMPLinearClause final static OMPLinearClause * Create(const ASTContext &C, SourceLocation StartLoc, SourceLocation LParenLoc, OpenMPLinearClauseKind Modifier, SourceLocation ModifierLoc, - SourceLocation ColonLoc, SourceLocation EndLoc, ArrayRef VL, - ArrayRef PL, ArrayRef IL, Expr *Step, Expr *CalcStep, - Stmt *PreInit, Expr *PostUpdate); + SourceLocation ColonLoc, SourceLocation StepModifierLoc, + SourceLocation EndLoc, ArrayRef VL, ArrayRef PL, + ArrayRef IL, Expr *Step, Expr *CalcStep, Stmt *PreInit, + Expr *PostUpdate); /// Creates an empty clause with the place for \a NumVars variables. /// @@ -4055,9 +4062,15 @@ class OMPLinearClause final /// Sets the location of ':'. void setColonLoc(SourceLocation Loc) { ColonLoc = Loc; } + /// Sets the location of 'step' modifier. + void setStepModifierLoc(SourceLocation Loc) { StepModifierLoc = Loc; } + /// Returns the location of ':'. SourceLocation getColonLoc() const { return ColonLoc; } + /// Returns the location of 'step' modifier. + SourceLocation getStepModifierLoc() const { return StepModifierLoc; } + /// Returns linear step. Expr *getStep() { return *(getFinals().end()); } diff --git a/clang/include/clang/AST/RecursiveASTVisitor.h b/clang/include/clang/AST/RecursiveASTVisitor.h index 3dd23eb38eeab..53bc15e1b19f6 100644 --- a/clang/include/clang/AST/RecursiveASTVisitor.h +++ b/clang/include/clang/AST/RecursiveASTVisitor.h @@ -2103,7 +2103,7 @@ DEF_TRAVERSE_DECL(FieldDecl, { TRY_TO(TraverseDeclaratorHelper(D)); if (D->isBitField()) TRY_TO(TraverseStmt(D->getBitWidth())); - else if (D->hasInClassInitializer()) + if (D->hasInClassInitializer()) TRY_TO(TraverseStmt(D->getInClassInitializer())); }) diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h index e3dbe3b8a45cc..1e8e1303e65f6 100644 --- a/clang/include/clang/AST/Type.h +++ b/clang/include/clang/AST/Type.h @@ -1663,11 +1663,12 @@ class alignas(TypeAlignment) Type : public ExtQualsTypeCommonBase { /// Actually an ArrayType::ArraySizeModifier. unsigned SizeModifier : 3; }; + enum { NumArrayTypeBits = NumTypeBits + 6 }; class ConstantArrayTypeBitfields { friend class ConstantArrayType; - unsigned : NumTypeBits + 3 + 3; + unsigned : NumArrayTypeBits; /// Whether we have a stored size expression. unsigned HasStoredSizeExpr : 1; @@ -1780,7 +1781,7 @@ class alignas(TypeAlignment) Type : public ExtQualsTypeCommonBase { unsigned Keyword : 8; }; - enum { NumTypeWithKeywordBits = 8 }; + enum { NumTypeWithKeywordBits = NumTypeBits + 8 }; class ElaboratedTypeBitfields { friend class ElaboratedType; @@ -1913,7 +1914,6 @@ class alignas(TypeAlignment) Type : public ExtQualsTypeCommonBase { class DependentTemplateSpecializationTypeBitfields { friend class DependentTemplateSpecializationType; - unsigned : NumTypeBits; unsigned : NumTypeWithKeywordBits; /// The number of template arguments named in this class template diff --git a/clang/include/clang/AST/TypeLoc.h b/clang/include/clang/AST/TypeLoc.h index 98427a8dcbfe6..5bb487f1a7f44 100644 --- a/clang/include/clang/AST/TypeLoc.h +++ b/clang/include/clang/AST/TypeLoc.h @@ -243,7 +243,7 @@ class TypeLoc { inline TypeSourceInfo::TypeSourceInfo(QualType ty, size_t DataSize) : Ty(ty) { // Init data attached to the object. See getTypeLoc. - memset(this + 1, 0, DataSize); + memset(static_cast(this + 1), 0, DataSize); } /// Return the TypeLoc for a type source info. diff --git a/clang/include/clang/Analysis/Analyses/Dominators.h b/clang/include/clang/Analysis/Analyses/Dominators.h index 9ac9cbe7d3ec7..7dd54c5ce262c 100644 --- a/clang/include/clang/Analysis/Analyses/Dominators.h +++ b/clang/include/clang/Analysis/Analyses/Dominators.h @@ -202,7 +202,7 @@ struct ChildrenGetterTy { auto Children = children(N); ChildrenTy Ret{Children.begin(), Children.end()}; - llvm::erase_value(Ret, nullptr); + llvm::erase(Ret, nullptr); return Ret; } }; diff --git a/clang/include/clang/Analysis/FlowSensitive/DataflowAnalysisContext.h b/clang/include/clang/Analysis/FlowSensitive/DataflowAnalysisContext.h index c46109a02921e..c1aa8484817a9 100644 --- a/clang/include/clang/Analysis/FlowSensitive/DataflowAnalysisContext.h +++ b/clang/include/clang/Analysis/FlowSensitive/DataflowAnalysisContext.h @@ -129,13 +129,17 @@ class DataflowAnalysisContext { /// token. Atom joinFlowConditions(Atom FirstToken, Atom SecondToken); - /// Returns true if and only if the constraints of the flow condition - /// identified by `Token` imply that `Val` is true. - bool flowConditionImplies(Atom Token, const Formula &); - - /// Returns true if and only if the constraints of the flow condition - /// identified by `Token` are always true. - bool flowConditionIsTautology(Atom Token); + /// Returns true if the constraints of the flow condition identified by + /// `Token` imply that `F` is true. + /// Returns false if the flow condition does not imply `F` or if the solver + /// times out. + bool flowConditionImplies(Atom Token, const Formula &F); + + /// Returns true if the constraints of the flow condition identified by + /// `Token` still allow `F` to be true. + /// Returns false if the flow condition implies that `F` is false or if the + /// solver times out. + bool flowConditionAllows(Atom Token, const Formula &F); /// Returns true if `Val1` is equivalent to `Val2`. /// Note: This function doesn't take into account constraints on `Val1` and @@ -188,6 +192,12 @@ class DataflowAnalysisContext { addTransitiveFlowConditionConstraints(Atom Token, llvm::SetVector &Out); + /// Returns true if the solver is able to prove that there is a satisfying + /// assignment for `Constraints`. + bool isSatisfiable(llvm::SetVector Constraints) { + return querySolver(std::move(Constraints)).getStatus() == + Solver::Result::Status::Satisfiable; + } /// Returns true if the solver is able to prove that there is no satisfying /// assignment for `Constraints` diff --git a/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h b/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h index 9ac2cb90ccc4d..963197b728f42 100644 --- a/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h +++ b/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h @@ -260,11 +260,7 @@ class Environment { /// if `D` isn't assigned a storage location in the environment. StorageLocation *getStorageLocation(const ValueDecl &D) const; - /// Removes the location assigned to `D` in the environment. - /// - /// Requirements: - /// - /// `D` must have a storage location assigned in the environment. + /// Removes the location assigned to `D` in the environment (if any). void removeDecl(const ValueDecl &D); /// Assigns `Loc` as the storage location of the glvalue `E` in the @@ -546,12 +542,29 @@ class Environment { Atom getFlowConditionToken() const { return FlowConditionToken; } /// Record a fact that must be true if this point in the program is reached. - void addToFlowCondition(const Formula &); + void assume(const Formula &); + + /// Deprecated synonym for `assume()`. + void addToFlowCondition(const Formula &F) { assume(F); } /// Returns true if the formula is always true when this point is reached. - /// Returns false if the formula may be false, or if the flow condition isn't - /// sufficiently precise to prove that it is true. - bool flowConditionImplies(const Formula &) const; + /// Returns false if the formula may be false (or the flow condition isn't + /// sufficiently precise to prove that it is true) or if the solver times out. + /// + /// Note that there is an asymmetry between this function and `allows()` in + /// that they both return false if the solver times out. The assumption is + /// that if `proves()` or `allows()` returns true, this will result in a + /// diagnostic, and we want to bias towards false negatives in the case where + /// the solver times out. + bool proves(const Formula &) const; + + /// Returns true if the formula may be true when this point is reached. + /// Returns false if the formula is always false when this point is reached + /// (or the flow condition is overly constraining) or if the solver times out. + bool allows(const Formula &) const; + + /// Deprecated synonym for `proves()`. + bool flowConditionImplies(const Formula &F) const { return proves(F); } /// Returns the `DeclContext` of the block being analysed, if any. Otherwise, /// returns null. diff --git a/clang/include/clang/Basic/AArch64SVEACLETypes.def b/clang/include/clang/Basic/AArch64SVEACLETypes.def index 56af270e1d10a..fa9c1ac0491c4 100644 --- a/clang/include/clang/Basic/AArch64SVEACLETypes.def +++ b/clang/include/clang/Basic/AArch64SVEACLETypes.def @@ -71,7 +71,7 @@ SVE_VECTOR_TYPE("__SVFloat16_t", "__SVFloat16_t", SveFloat16, SveFloat16Ty, 8, 1 SVE_VECTOR_TYPE("__SVFloat32_t", "__SVFloat32_t", SveFloat32, SveFloat32Ty, 4, 32, true, true, false) SVE_VECTOR_TYPE("__SVFloat64_t", "__SVFloat64_t", SveFloat64, SveFloat64Ty, 2, 64, true, true, false) -SVE_VECTOR_TYPE("__SVBFloat16_t", "__SVBFloat16_t", SveBFloat16, SveBFloat16Ty, 8, 16, true, false, true) +SVE_VECTOR_TYPE("__SVBfloat16_t", "__SVBfloat16_t", SveBFloat16, SveBFloat16Ty, 8, 16, true, false, true) // // x2 diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index 5486b36133755..25231c5b82b90 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -107,6 +107,10 @@ def NonBitField : SubsetSubjectisBitField()}], "non-bit-field non-static data members">; +def BitField : SubsetSubjectisBitField()}], + "bit-field data members">; + def NonStaticCXXMethod : SubsetSubjectisStatic()}], "non-static member functions">; @@ -4269,3 +4273,10 @@ def CountedBy : InheritableAttr { void setCountedByFieldLoc(SourceRange Loc) { CountedByFieldLoc = Loc; } }]; } + +def PreferredType: InheritableAttr { + let Spellings = [Clang<"preferred_type">]; + let Subjects = SubjectList<[BitField], ErrorDiag>; + let Args = [TypeArgument<"Type", 1>]; + let Documentation = [PreferredTypeDocumentation]; +} diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index cbbf69faeb308..05703df2129f6 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -7231,6 +7231,69 @@ its underlying representation to be a WebAssembly ``funcref``. }]; } +def PreferredTypeDocumentation : Documentation { + let Category = DocCatField; + let Content = [{ +This attribute allows adjusting the type of a bit-field in debug information. +This can be helpful when a bit-field is intended to store an enumeration value, +but has to be specified as having the enumeration's underlying type in order to +facilitate compiler optimizations or bit-field packing behavior. Normally, the +underlying type is what is emitted in debug information, which can make it hard +for debuggers to know to map a bit-field's value back to a particular enumeration. + +.. code-block:: c++ + + enum Colors { Red, Green, Blue }; + + struct S { + [[clang::preferred_type(Colors)]] unsigned ColorVal : 2; + [[clang::preferred_type(bool)]] unsigned UseAlternateColorSpace : 1; + } s = { Green, false }; + +Without the attribute, a debugger is likely to display the value ``1`` for ``ColorVal`` +and ``0`` for ``UseAlternateColorSpace``. With the attribute, the debugger may now +display ``Green`` and ``false`` instead. + +This can be used to map a bit-field to an arbitrary type that isn't integral +or an enumeration type. For example: + +.. code-block:: c++ + + struct A { + short a1; + short a2; + }; + + struct B { + [[clang::preferred_type(A)]] unsigned b1 : 32 = 0x000F'000C; + }; + +will associate the type ``A`` with the ``b1`` bit-field and is intended to display +something like this in the debugger: + +.. code-block:: text + + Process 2755547 stopped + * thread #1, name = 'test-preferred-', stop reason = step in + frame #0: 0x0000555555555148 test-preferred-type`main at test.cxx:13:14 + 10 int main() + 11 { + 12 B b; + -> 13 return b.b1; + 14 } + (lldb) v -T + (B) b = { + (A:32) b1 = { + (short) a1 = 12 + (short) a2 = 15 + } + } + +Note that debuggers may not be able to handle more complex mappings, and so +this usage is debugger-dependent. + }]; +} + def CleanupDocs : Documentation { let Category = DocCatType; let Content = [{ diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def index 18a1186053481..a35488ed3dfa5 100644 --- a/clang/include/clang/Basic/BuiltinsPPC.def +++ b/clang/include/clang/Basic/BuiltinsPPC.def @@ -151,9 +151,11 @@ TARGET_BUILTIN(__builtin_ppc_extract_exp, "Uid", "", "power9-vector") TARGET_BUILTIN(__builtin_ppc_extract_sig, "ULLid", "", "power9-vector") BUILTIN(__builtin_ppc_mtfsb0, "vUIi", "") BUILTIN(__builtin_ppc_mtfsb1, "vUIi", "") +BUILTIN(__builtin_ppc_mffs, "d", "") TARGET_BUILTIN(__builtin_ppc_mffsl, "d", "", "isa-v30-instructions") BUILTIN(__builtin_ppc_mtfsf, "vUIiUi", "") BUILTIN(__builtin_ppc_mtfsfi, "vUIiUIi", "") +BUILTIN(__builtin_ppc_set_fpscr_rn, "di", "") TARGET_BUILTIN(__builtin_ppc_insert_exp, "ddULLi", "", "power9-vector") BUILTIN(__builtin_ppc_fmsub, "dddd", "") BUILTIN(__builtin_ppc_fmsubs, "ffff", "") diff --git a/clang/include/clang/Basic/DiagnosticASTKinds.td b/clang/include/clang/Basic/DiagnosticASTKinds.td index b70cf1071d865..031117f2c4137 100644 --- a/clang/include/clang/Basic/DiagnosticASTKinds.td +++ b/clang/include/clang/Basic/DiagnosticASTKinds.td @@ -69,7 +69,7 @@ def note_consteval_address_accessible : Note< "%select{pointer|reference}0 to a consteval declaration " "is not a constant expression">; def note_constexpr_uninitialized : Note< - "subobject %0 is not initialized">; + "subobject %select{of type |}0%1 is not initialized">; def note_constexpr_uninitialized_base : Note< "constructor of base class %0 is not called">; def note_constexpr_static_local : Note< @@ -317,7 +317,7 @@ def note_constexpr_memcpy_unsupported : Note< "source is not a contiguous array of at least %4 elements of type %3|" "destination is not a contiguous array of at least %4 elements of type %3}2">; def note_constexpr_bit_cast_unsupported_type : Note< - "constexpr bit_cast involving type %0 is not yet supported">; + "constexpr bit cast involving type %0 is not yet supported">; def note_constexpr_bit_cast_unsupported_bitfield : Note< "constexpr bit_cast involving bit-field is not yet supported">; def note_constexpr_bit_cast_invalid_type : Note< @@ -326,6 +326,9 @@ def note_constexpr_bit_cast_invalid_type : Note< "%select{type|member}1 is not allowed in a constant expression">; def note_constexpr_bit_cast_invalid_subtype : Note< "invalid type %0 is a %select{member|base}1 of %2">; +def note_constexpr_bit_cast_invalid_vector : Note< + "bit_cast involving type %0 is not allowed in a constant expression; " + "element size %1 * element count %2 is not a multiple of the byte size %3">; def note_constexpr_bit_cast_indet_dest : Note< "indeterminate value can only initialize an object of type 'unsigned char'" "%select{, 'char',|}1 or 'std::byte'; %0 is invalid">; diff --git a/clang/include/clang/Basic/DiagnosticCommonKinds.td b/clang/include/clang/Basic/DiagnosticCommonKinds.td index f2df283c74829..9f0ccd255a321 100644 --- a/clang/include/clang/Basic/DiagnosticCommonKinds.td +++ b/clang/include/clang/Basic/DiagnosticCommonKinds.td @@ -356,9 +356,8 @@ def err_file_modified : Error< "file '%0' modified since it was first processed">, DefaultFatal; def err_file_too_large : Error< "sorry, unsupported: file '%0' is too large for Clang to process">; -def err_include_too_large : Error< - "sorry, this include generates a translation unit too large for" - " Clang to process.">, DefaultFatal; +def err_sloc_space_too_large : Error< + "sorry, the translation unit is too large for Clang to process: ran out of source locations">, DefaultFatal; def err_unsupported_bom : Error<"%0 byte order mark detected in '%1', but " "encoding is not supported">, DefaultFatal; def err_unable_to_rename_temp : Error< diff --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td b/clang/include/clang/Basic/DiagnosticDriverKinds.td index 9c00fa50bb955..c0ccd64a2a7b8 100644 --- a/clang/include/clang/Basic/DiagnosticDriverKinds.td +++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td @@ -20,6 +20,8 @@ def err_drv_unsupported_opt_for_language_mode : Error< "unsupported option '%0' for language mode '%1'">; def err_drv_unsupported_option_argument : Error< "unsupported argument '%1' to option '%0'">; +def err_drv_unsupported_option_argument_for_target : Error< + "unsupported argument '%1' to option '%0' for target '%2'">; def err_drv_unknown_stdin_type : Error< "-E or -x required when input is from standard input">; def err_drv_unknown_stdin_type_clang_cl : Error< @@ -441,11 +443,14 @@ def warn_drv_overriding_option : Warning< def warn_drv_treating_input_as_cxx : Warning< "treating '%0' input as '%1' when in C++ mode, this behavior is deprecated">, InGroup; -def warn_drv_include_probe_gch : Warning< - "'%0' probing .gch is deprecated. Use '-include-pch %1' or switch to .pch instead">, - InGroup; def warn_drv_pch_not_first_include : Warning< "precompiled header '%0' was ignored because '%1' is not first '-include'">; +def warn_drv_pch_ignoring_gch_file : Warning< + "precompiled header '%0' was ignored because it is not a clang PCH file">, + InGroup; +def warn_drv_pch_ignoring_gch_dir : Warning< + "precompiled header directory '%0' was ignored because it contains no clang PCH files">, + InGroup; def warn_missing_sysroot : Warning<"no such sysroot directory: '%0'">, InGroup>; def warn_incompatible_sysroot : Warning<"using sysroot for '%0' but targeting '%1'">, @@ -527,6 +532,10 @@ def err_test_module_file_extension_format : Error< def err_drv_module_output_with_multiple_arch : Error< "option '-fmodule-output' can't be used with multiple arch options">; +def warn_drv_delayed_template_parsing_after_cxx20 : Warning< + "-fdelayed-template-parsing is deprecated after C++20">, + InGroup>; + def err_drv_extract_api_wrong_kind : Error< "header file '%0' input '%1' does not match the type of prior input " "in api extraction; use '-x %2' to override">; diff --git a/clang/include/clang/Basic/DiagnosticGroups.td b/clang/include/clang/Basic/DiagnosticGroups.td index 2e4e22e4f90be..9a8f3f03b39d1 100644 --- a/clang/include/clang/Basic/DiagnosticGroups.td +++ b/clang/include/clang/Basic/DiagnosticGroups.td @@ -53,8 +53,8 @@ def SingleBitBitFieldConstantConversion : def BitFieldConstantConversion : DiagGroup<"bitfield-constant-conversion", [SingleBitBitFieldConstantConversion]>; def BitFieldEnumConversion : DiagGroup<"bitfield-enum-conversion">; -def BitFieldConversion : DiagGroup<"bitfield-conversion">; def BitFieldWidth : DiagGroup<"bitfield-width">; +def BitFieldType : DiagGroup<"bitfield-type">; def CompoundTokenSplitByMacro : DiagGroup<"compound-token-split-by-macro">; def CompoundTokenSplitBySpace : DiagGroup<"compound-token-split-by-space">; def CompoundTokenSplit : DiagGroup<"compound-token-split", @@ -210,7 +210,6 @@ def DeprecatedWritableStr : DiagGroup<"deprecated-writable-strings", [CXX11CompatDeprecatedWritableStr]>; def DeprecatedPragma : DiagGroup<"deprecated-pragma">; def DeprecatedType : DiagGroup<"deprecated-type">; -def DeprecatedIncludeGch : DiagGroup<"deprecated-include-gch">; // FIXME: Why is DeprecatedImplementations not in this group? def Deprecated : DiagGroup<"deprecated", [DeprecatedAnonEnumEnumConversion, DeprecatedArrayCompare, @@ -233,8 +232,7 @@ def Deprecated : DiagGroup<"deprecated", [DeprecatedAnonEnumEnumConversion, DeprecatedType, DeprecatedVolatile, DeprecatedWritableStr, - DeprecatedRedundantConstexprStaticDef, - DeprecatedIncludeGch + DeprecatedRedundantConstexprStaticDef ]>, DiagCategory<"Deprecations">; @@ -417,7 +415,11 @@ def : DiagGroup<"c++2a-compat-pedantic", [CXX20CompatPedantic]>; def ExitTimeDestructors : DiagGroup<"exit-time-destructors">; def FlexibleArrayExtensions : DiagGroup<"flexible-array-extensions">; def FourByteMultiChar : DiagGroup<"four-char-constants">; -def GlobalConstructors : DiagGroup<"global-constructors">; +def GlobalConstructors : DiagGroup<"global-constructors"> { + code Documentation = [{ +Emit a warning for each variable declaration that generates code run at startup. + }]; +} def BitwiseConditionalParentheses: DiagGroup<"bitwise-conditional-parentheses">; def BitwiseOpParentheses: DiagGroup<"bitwise-op-parentheses">; def LogicalOpParentheses: DiagGroup<"logical-op-parentheses">; @@ -444,6 +446,7 @@ def IncrementBool : DiagGroup<"increment-bool", [DeprecatedIncrementBool]>; def InfiniteRecursion : DiagGroup<"infinite-recursion">; def PureVirtualCallFromCtorDtor: DiagGroup<"call-to-pure-virtual-from-ctor-dtor">; def GNUImaginaryConstant : DiagGroup<"gnu-imaginary-constant">; +def IgnoredGCH : DiagGroup<"ignored-gch">; def IgnoredReferenceQualifiers : DiagGroup<"ignored-reference-qualifiers">; def IgnoredQualifiers : DiagGroup<"ignored-qualifiers", [IgnoredReferenceQualifiers]>; def : DiagGroup<"import">; @@ -848,7 +851,9 @@ def OverridingMethodMismatch : DiagGroup<"overriding-method-mismatch">; def VariadicMacros : DiagGroup<"variadic-macros">; def VectorConversion : DiagGroup<"vector-conversion">; // clang specific def VexingParse : DiagGroup<"vexing-parse">; -def VLAExtension : DiagGroup<"vla-extension">; +def VLAUseStaticAssert : DiagGroup<"vla-extension-static-assert">; +def VLACxxExtension : DiagGroup<"vla-cxx-extension", [VLAUseStaticAssert]>; +def VLAExtension : DiagGroup<"vla-extension", [VLACxxExtension]>; def VLA : DiagGroup<"vla", [VLAExtension]>; def VolatileRegisterVar : DiagGroup<"volatile-register-var">; def Visibility : DiagGroup<"visibility">; @@ -934,7 +939,6 @@ def Conversion : DiagGroup<"conversion", ConstantConversion, EnumConversion, BitFieldEnumConversion, - BitFieldConversion, FloatConversion, Shorten64To32, IntConversion, @@ -1085,7 +1089,8 @@ def Consumed : DiagGroup<"consumed">; // warning should be active _only_ when -Wall is passed in, mark it as // DefaultIgnore in addition to putting it here. def All : DiagGroup<"all", [Most, Parentheses, Switch, SwitchBool, - MisleadingIndentation, PackedNonPod]>; + MisleadingIndentation, PackedNonPod, + VLACxxExtension]>; // Warnings that should be in clang-cl /w4. def : DiagGroup<"CL4", [All, Extra]>; diff --git a/clang/include/clang/Basic/DiagnosticParseKinds.td b/clang/include/clang/Basic/DiagnosticParseKinds.td index 43a5f000eda6c..de180344fcc5c 100644 --- a/clang/include/clang/Basic/DiagnosticParseKinds.td +++ b/clang/include/clang/Basic/DiagnosticParseKinds.td @@ -1348,6 +1348,10 @@ def warn_pragma_omp_ignored : Warning< def warn_omp_extra_tokens_at_eol : Warning< "extra tokens at the end of '#pragma omp %0' are ignored">, InGroup; +def err_omp_multiple_step_or_linear_modifier : Error< + "multiple %select{'step size'|'linear modifier'}0 found in linear clause">; +def err_omp_deprecate_old_syntax: Error< + "old syntax '%0' on '%1' clause was deprecated, use new syntax '%2'">; def warn_pragma_expected_colon_r_paren : Warning< "missing ':' or ')' after %0 - ignoring">, InGroup; def err_omp_unknown_directive : Error< @@ -1534,6 +1538,7 @@ def warn_omp51_compat_attributes : Warning< "standards before OpenMP 5.1">, InGroup, DefaultIgnore; def err_omp_expected_colon : Error<"missing ':' in %0">; +def err_omp_missing_comma : Error< "missing ',' after %0">; def err_omp_expected_context_selector : Error<"expected valid context selector in %0">; def err_omp_requires_out_inout_depend_type : Error< diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index 6b499d112b79f..224c0df7f1fb7 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -137,6 +137,18 @@ def err_half_const_requires_fp16 : Error< // C99 variable-length arrays def ext_vla : Extension<"variable length arrays are a C99 feature">, InGroup; +// In C++ language modes, we warn by default as an extension, while in GNU++ +// language modes, we warn as an extension but add the warning group to -Wall. +def ext_vla_cxx : ExtWarn< + "variable length arrays in C++ are a Clang extension">, + InGroup; +def ext_vla_cxx_in_gnu_mode : Extension, + InGroup; +def ext_vla_cxx_static_assert : ExtWarn< + "variable length arrays in C++ are a Clang extension; did you mean to use " + "'static_assert'?">, InGroup; +def ext_vla_cxx_in_gnu_mode_static_assert : Extension< + ext_vla_cxx_static_assert.Summary>, InGroup; def warn_vla_used : Warning<"variable length array used">, InGroup, DefaultIgnore; def err_vla_in_sfinae : Error< @@ -154,6 +166,8 @@ def ext_vla_folded_to_constant : ExtWarn< InGroup; def err_vla_unsupported : Error< "variable length arrays are not supported for %select{the current target|'%1'}0">; +def err_vla_in_coroutine_unsupported : Error< + "variable length arrays in a coroutine are not supported">; def note_vla_unsupported : Note< "variable length arrays are not supported for the current target">; @@ -3153,6 +3167,9 @@ def err_invalid_branch_protection_spec : Error< "invalid or misplaced branch protection specification '%0'">; def warn_unsupported_branch_protection_spec : Warning< "unsupported branch protection specification '%0'">, InGroup; +def warn_attribute_underlying_type_mismatch : Warning< + "underlying type %0 of enumeration %1 doesn't match bit-field type %2">, + InGroup; def warn_unsupported_target_attribute : Warning<"%select{unsupported|duplicate|unknown}0%select{| CPU|" @@ -6179,9 +6196,6 @@ def warn_signed_bitfield_enum_conversion : Warning< "signed bit-field %0 needs an extra bit to represent the largest positive " "enumerators of %1">, InGroup, DefaultIgnore; -def warn_bitfield_too_small_for_integral_type : Warning< - "conversion from %2 (%3 bits) to bit-field %0 (%1 bits) may change value">, - InGroup, DefaultIgnore; def note_change_bitfield_sign : Note< "consider making the bitfield type %select{unsigned|signed}0">; @@ -9469,6 +9483,9 @@ def err_defaulted_special_member_return_type : Error< def err_defaulted_special_member_quals : Error< "an explicitly-defaulted %select{copy|move}0 assignment operator may not " "have 'const'%select{, 'constexpr'|}1 or 'volatile' qualifiers">; +def err_defaulted_special_member_explicit_object_mismatch : Error< + "the type of the explicit object parameter of an explicitly-defaulted " + "%select{copy|move}0 assignment operator should match the type of the class %1">; def err_defaulted_special_member_volatile_param : Error< "the parameter for an explicitly-defaulted %sub{select_special_member_kind}0 " "may not be volatile">; @@ -11016,6 +11033,8 @@ def err_omp_wrong_linear_modifier : Error< "expected %select{'val' modifier|one of 'ref', val' or 'uval' modifiers}0">; def err_omp_wrong_linear_modifier_non_reference : Error< "variable of non-reference type %0 can be used only with 'val' modifier, but used with '%1'">; +def err_omp_step_simple_modifier_exclusive : Error< + "step simple modifier is exclusive and can't be use with 'val', 'uval' or 'ref' modifier">; def err_omp_wrong_simdlen_safelen_values : Error< "the value of 'simdlen' parameter must be less than or equal to the value of the 'safelen' parameter">; def err_omp_wrong_if_directive_name_modifier : Error< diff --git a/clang/include/clang/Basic/FileEntry.h b/clang/include/clang/Basic/FileEntry.h index 23237a9326f84..bc65463735488 100644 --- a/clang/include/clang/Basic/FileEntry.h +++ b/clang/include/clang/Basic/FileEntry.h @@ -235,37 +235,6 @@ static_assert(std::is_trivially_copyable::value, namespace llvm { -template <> struct PointerLikeTypeTraits { - static inline void *getAsVoidPointer(clang::FileEntryRef File) { - return const_cast(&File.getMapEntry()); - } - - static inline clang::FileEntryRef getFromVoidPointer(void *Ptr) { - return clang::FileEntryRef( - *reinterpret_cast(Ptr)); - } - - static constexpr int NumLowBitsAvailable = PointerLikeTypeTraits< - const clang::FileEntryRef::MapEntry *>::NumLowBitsAvailable; -}; - -template <> struct PointerLikeTypeTraits { - static inline void *getAsVoidPointer(clang::OptionalFileEntryRef File) { - if (!File) - return nullptr; - return PointerLikeTypeTraits::getAsVoidPointer(*File); - } - - static inline clang::OptionalFileEntryRef getFromVoidPointer(void *Ptr) { - if (!Ptr) - return std::nullopt; - return PointerLikeTypeTraits::getFromVoidPointer(Ptr); - } - - static constexpr int NumLowBitsAvailable = - PointerLikeTypeTraits::NumLowBitsAvailable; -}; - /// Specialisation of DenseMapInfo for FileEntryRef. template <> struct DenseMapInfo { static inline clang::FileEntryRef getEmptyKey() { diff --git a/clang/include/clang/Basic/IdentifierTable.h b/clang/include/clang/Basic/IdentifierTable.h index 1a1ffddf2b1c6..2eafe59384067 100644 --- a/clang/include/clang/Basic/IdentifierTable.h +++ b/clang/include/clang/Basic/IdentifierTable.h @@ -19,6 +19,9 @@ #include "clang/Basic/LLVM.h" #include "clang/Basic/TokenKinds.h" #include "llvm/ADT/DenseMapInfo.h" +#include "llvm/ADT/FoldingSet.h" +#include "llvm/ADT/PointerIntPair.h" +#include "llvm/ADT/PointerUnion.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringMap.h" #include "llvm/ADT/StringRef.h" @@ -794,6 +797,121 @@ enum ObjCStringFormatFamily { SFF_CFString }; +namespace detail { + +/// DeclarationNameExtra is used as a base of various uncommon special names. +/// This class is needed since DeclarationName has not enough space to store +/// the kind of every possible names. Therefore the kind of common names is +/// stored directly in DeclarationName, and the kind of uncommon names is +/// stored in DeclarationNameExtra. It is aligned to 8 bytes because +/// DeclarationName needs the lower 3 bits to store the kind of common names. +/// DeclarationNameExtra is tightly coupled to DeclarationName and any change +/// here is very likely to require changes in DeclarationName(Table). +class alignas(IdentifierInfoAlignment) DeclarationNameExtra { + friend class clang::DeclarationName; + friend class clang::DeclarationNameTable; + +protected: + /// The kind of "extra" information stored in the DeclarationName. See + /// @c ExtraKindOrNumArgs for an explanation of how these enumerator values + /// are used. Note that DeclarationName depends on the numerical values + /// of the enumerators in this enum. See DeclarationName::StoredNameKind + /// for more info. + enum ExtraKind { + CXXDeductionGuideName, + CXXLiteralOperatorName, + CXXUsingDirective, + ObjCMultiArgSelector + }; + + /// ExtraKindOrNumArgs has one of the following meaning: + /// * The kind of an uncommon C++ special name. This DeclarationNameExtra + /// is in this case in fact either a CXXDeductionGuideNameExtra or + /// a CXXLiteralOperatorIdName. + /// + /// * It may be also name common to C++ using-directives (CXXUsingDirective), + /// + /// * Otherwise it is ObjCMultiArgSelector+NumArgs, where NumArgs is + /// the number of arguments in the Objective-C selector, in which + /// case the DeclarationNameExtra is also a MultiKeywordSelector. + unsigned ExtraKindOrNumArgs; + + DeclarationNameExtra(ExtraKind Kind) : ExtraKindOrNumArgs(Kind) {} + DeclarationNameExtra(unsigned NumArgs) + : ExtraKindOrNumArgs(ObjCMultiArgSelector + NumArgs) {} + + /// Return the corresponding ExtraKind. + ExtraKind getKind() const { + return static_cast(ExtraKindOrNumArgs > + (unsigned)ObjCMultiArgSelector + ? (unsigned)ObjCMultiArgSelector + : ExtraKindOrNumArgs); + } + + /// Return the number of arguments in an ObjC selector. Only valid when this + /// is indeed an ObjCMultiArgSelector. + unsigned getNumArgs() const { + assert(ExtraKindOrNumArgs >= (unsigned)ObjCMultiArgSelector && + "getNumArgs called but this is not an ObjC selector!"); + return ExtraKindOrNumArgs - (unsigned)ObjCMultiArgSelector; + } +}; + +} // namespace detail + +/// One of these variable length records is kept for each +/// selector containing more than one keyword. We use a folding set +/// to unique aggregate names (keyword selectors in ObjC parlance). Access to +/// this class is provided strictly through Selector. +class alignas(IdentifierInfoAlignment) MultiKeywordSelector + : public detail::DeclarationNameExtra, + public llvm::FoldingSetNode { + MultiKeywordSelector(unsigned nKeys) : DeclarationNameExtra(nKeys) {} + +public: + // Constructor for keyword selectors. + MultiKeywordSelector(unsigned nKeys, IdentifierInfo **IIV) + : DeclarationNameExtra(nKeys) { + assert((nKeys > 1) && "not a multi-keyword selector"); + + // Fill in the trailing keyword array. + IdentifierInfo **KeyInfo = reinterpret_cast(this + 1); + for (unsigned i = 0; i != nKeys; ++i) + KeyInfo[i] = IIV[i]; + } + + // getName - Derive the full selector name and return it. + std::string getName() const; + + using DeclarationNameExtra::getNumArgs; + + using keyword_iterator = IdentifierInfo *const *; + + keyword_iterator keyword_begin() const { + return reinterpret_cast(this + 1); + } + + keyword_iterator keyword_end() const { + return keyword_begin() + getNumArgs(); + } + + IdentifierInfo *getIdentifierInfoForSlot(unsigned i) const { + assert(i < getNumArgs() && "getIdentifierInfoForSlot(): illegal index"); + return keyword_begin()[i]; + } + + static void Profile(llvm::FoldingSetNodeID &ID, keyword_iterator ArgTys, + unsigned NumArgs) { + ID.AddInteger(NumArgs); + for (unsigned i = 0; i != NumArgs; ++i) + ID.AddPointer(ArgTys[i]); + } + + void Profile(llvm::FoldingSetNodeID &ID) { + Profile(ID, keyword_begin(), getNumArgs()); + } +}; + /// Smart pointer class that efficiently represents Objective-C method /// names. /// @@ -809,43 +927,58 @@ class Selector { enum IdentifierInfoFlag { // Empty selector = 0. Note that these enumeration values must // correspond to the enumeration values of DeclarationName::StoredNameKind - ZeroArg = 0x01, - OneArg = 0x02, + ZeroArg = 0x01, + OneArg = 0x02, + // IMPORTANT NOTE: see comments in InfoPtr (below) about this enumerator + // value. MultiArg = 0x07, - ArgFlags = 0x07 }; - /// A pointer to the MultiKeywordSelector or IdentifierInfo. We use the low - /// three bits of InfoPtr to store an IdentifierInfoFlag. Note that in any - /// case IdentifierInfo and MultiKeywordSelector are already aligned to - /// 8 bytes even on 32 bits archs because of DeclarationName. - uintptr_t InfoPtr = 0; + /// IMPORTANT NOTE: the order of the types in this PointerUnion are + /// important! The DeclarationName class has bidirectional conversion + /// to/from Selector through an opaque pointer (void *) which corresponds + /// to this PointerIntPair. The discriminator bit from the PointerUnion + /// corresponds to the high bit in the MultiArg enumerator. So while this + /// PointerIntPair only has two bits for the integer (and we mask off the + /// high bit in `MultiArg` when it is used), that discrimator bit is + /// still necessary for the opaque conversion. The discriminator bit + /// from the PointerUnion and the two integer bits from the + /// PointerIntPair are also exposed via the DeclarationName::StoredNameKind + /// enumeration; see the comments in DeclarationName.h for more details. + /// Do not reorder or add any arguments to this template + /// without thoroughly understanding how tightly coupled these classes are. + llvm::PointerIntPair< + llvm::PointerUnion, 2> + InfoPtr; Selector(IdentifierInfo *II, unsigned nArgs) { - InfoPtr = reinterpret_cast(II); - assert((InfoPtr & ArgFlags) == 0 &&"Insufficiently aligned IdentifierInfo"); assert(nArgs < 2 && "nArgs not equal to 0/1"); - InfoPtr |= nArgs+1; + InfoPtr.setPointerAndInt(II, nArgs + 1); } Selector(MultiKeywordSelector *SI) { - InfoPtr = reinterpret_cast(SI); - assert((InfoPtr & ArgFlags) == 0 &&"Insufficiently aligned IdentifierInfo"); - InfoPtr |= MultiArg; + // IMPORTANT NOTE: we mask off the upper bit of this value because we only + // reserve two bits for the integer in the PointerIntPair. See the comments + // in `InfoPtr` for more details. + InfoPtr.setPointerAndInt(SI, MultiArg & 0b11); } IdentifierInfo *getAsIdentifierInfo() const { - if (getIdentifierInfoFlag() < MultiArg) - return reinterpret_cast(InfoPtr & ~ArgFlags); - return nullptr; + return InfoPtr.getPointer().dyn_cast(); } MultiKeywordSelector *getMultiKeywordSelector() const { - return reinterpret_cast(InfoPtr & ~ArgFlags); + return InfoPtr.getPointer().get(); } unsigned getIdentifierInfoFlag() const { - return InfoPtr & ArgFlags; + unsigned new_flags = InfoPtr.getInt(); + // IMPORTANT NOTE: We have to reconstitute this data rather than use the + // value directly from the PointerIntPair. See the comments in `InfoPtr` + // for more details. + if (InfoPtr.getPointer().is()) + new_flags |= MultiArg; + return new_flags; } static ObjCMethodFamily getMethodFamilyImpl(Selector sel); @@ -856,31 +989,27 @@ class Selector { /// The default ctor should only be used when creating data structures that /// will contain selectors. Selector() = default; - explicit Selector(uintptr_t V) : InfoPtr(V) {} + explicit Selector(uintptr_t V) { + InfoPtr.setFromOpaqueValue(reinterpret_cast(V)); + } /// operator==/!= - Indicate whether the specified selectors are identical. bool operator==(Selector RHS) const { - return InfoPtr == RHS.InfoPtr; + return InfoPtr.getOpaqueValue() == RHS.InfoPtr.getOpaqueValue(); } bool operator!=(Selector RHS) const { - return InfoPtr != RHS.InfoPtr; + return InfoPtr.getOpaqueValue() != RHS.InfoPtr.getOpaqueValue(); } - void *getAsOpaquePtr() const { - return reinterpret_cast(InfoPtr); - } + void *getAsOpaquePtr() const { return InfoPtr.getOpaqueValue(); } /// Determine whether this is the empty selector. - bool isNull() const { return InfoPtr == 0; } + bool isNull() const { return InfoPtr.getOpaqueValue() == nullptr; } // Predicates to identify the selector type. - bool isKeywordSelector() const { - return getIdentifierInfoFlag() != ZeroArg; - } + bool isKeywordSelector() const { return InfoPtr.getInt() != ZeroArg; } - bool isUnarySelector() const { - return getIdentifierInfoFlag() == ZeroArg; - } + bool isUnarySelector() const { return InfoPtr.getInt() == ZeroArg; } /// If this selector is the specific keyword selector described by Names. bool isKeywordSelector(ArrayRef Names) const; @@ -991,68 +1120,6 @@ class SelectorTable { static std::string getPropertyNameFromSetterSelector(Selector Sel); }; -namespace detail { - -/// DeclarationNameExtra is used as a base of various uncommon special names. -/// This class is needed since DeclarationName has not enough space to store -/// the kind of every possible names. Therefore the kind of common names is -/// stored directly in DeclarationName, and the kind of uncommon names is -/// stored in DeclarationNameExtra. It is aligned to 8 bytes because -/// DeclarationName needs the lower 3 bits to store the kind of common names. -/// DeclarationNameExtra is tightly coupled to DeclarationName and any change -/// here is very likely to require changes in DeclarationName(Table). -class alignas(IdentifierInfoAlignment) DeclarationNameExtra { - friend class clang::DeclarationName; - friend class clang::DeclarationNameTable; - -protected: - /// The kind of "extra" information stored in the DeclarationName. See - /// @c ExtraKindOrNumArgs for an explanation of how these enumerator values - /// are used. Note that DeclarationName depends on the numerical values - /// of the enumerators in this enum. See DeclarationName::StoredNameKind - /// for more info. - enum ExtraKind { - CXXDeductionGuideName, - CXXLiteralOperatorName, - CXXUsingDirective, - ObjCMultiArgSelector - }; - - /// ExtraKindOrNumArgs has one of the following meaning: - /// * The kind of an uncommon C++ special name. This DeclarationNameExtra - /// is in this case in fact either a CXXDeductionGuideNameExtra or - /// a CXXLiteralOperatorIdName. - /// - /// * It may be also name common to C++ using-directives (CXXUsingDirective), - /// - /// * Otherwise it is ObjCMultiArgSelector+NumArgs, where NumArgs is - /// the number of arguments in the Objective-C selector, in which - /// case the DeclarationNameExtra is also a MultiKeywordSelector. - unsigned ExtraKindOrNumArgs; - - DeclarationNameExtra(ExtraKind Kind) : ExtraKindOrNumArgs(Kind) {} - DeclarationNameExtra(unsigned NumArgs) - : ExtraKindOrNumArgs(ObjCMultiArgSelector + NumArgs) {} - - /// Return the corresponding ExtraKind. - ExtraKind getKind() const { - return static_cast(ExtraKindOrNumArgs > - (unsigned)ObjCMultiArgSelector - ? (unsigned)ObjCMultiArgSelector - : ExtraKindOrNumArgs); - } - - /// Return the number of arguments in an ObjC selector. Only valid when this - /// is indeed an ObjCMultiArgSelector. - unsigned getNumArgs() const { - assert(ExtraKindOrNumArgs >= (unsigned)ObjCMultiArgSelector && - "getNumArgs called but this is not an ObjC selector!"); - return ExtraKindOrNumArgs - (unsigned)ObjCMultiArgSelector; - } -}; - -} // namespace detail - } // namespace clang namespace llvm { @@ -1089,34 +1156,6 @@ struct PointerLikeTypeTraits { static constexpr int NumLowBitsAvailable = 0; }; -// Provide PointerLikeTypeTraits for IdentifierInfo pointers, which -// are not guaranteed to be 8-byte aligned. -template<> -struct PointerLikeTypeTraits { - static void *getAsVoidPointer(clang::IdentifierInfo* P) { - return P; - } - - static clang::IdentifierInfo *getFromVoidPointer(void *P) { - return static_cast(P); - } - - static constexpr int NumLowBitsAvailable = 1; -}; - -template<> -struct PointerLikeTypeTraits { - static const void *getAsVoidPointer(const clang::IdentifierInfo* P) { - return P; - } - - static const clang::IdentifierInfo *getFromVoidPointer(const void *P) { - return static_cast(P); - } - - static constexpr int NumLowBitsAvailable = 1; -}; - } // namespace llvm #endif // LLVM_CLANG_BASIC_IDENTIFIERTABLE_H diff --git a/clang/include/clang/Basic/JsonSupport.h b/clang/include/clang/Basic/JsonSupport.h index 37f66ab63eb1b..bcaa3d364444e 100644 --- a/clang/include/clang/Basic/JsonSupport.h +++ b/clang/include/clang/Basic/JsonSupport.h @@ -71,7 +71,7 @@ inline std::string JsonFormat(StringRef RawSR, bool AddQuotes) { } // Remove new-lines. - llvm::erase_value(Str, '\n'); + llvm::erase(Str, '\n'); if (!AddQuotes) return Str; diff --git a/clang/include/clang/Basic/LangStandard.h b/clang/include/clang/Basic/LangStandard.h index 6356f16acc811..bc49669a82ad2 100644 --- a/clang/include/clang/Basic/LangStandard.h +++ b/clang/include/clang/Basic/LangStandard.h @@ -43,6 +43,7 @@ enum class Language : uint8_t { HLSL, ///@} }; +StringRef languageToString(Language L); enum LangFeatures { LineComment = (1 << 0), diff --git a/clang/include/clang/Basic/Module.h b/clang/include/clang/Basic/Module.h index 676fd372493a3..6a7423938bdb8 100644 --- a/clang/include/clang/Basic/Module.h +++ b/clang/include/clang/Basic/Module.h @@ -35,6 +35,7 @@ #include #include #include +#include #include namespace llvm { @@ -162,7 +163,7 @@ class alignas(8) Module { std::string PresumedModuleMapFile; /// The umbrella header or directory. - llvm::PointerUnion Umbrella; + std::variant Umbrella; /// The module signature. ASTFileSignature Signature; @@ -665,18 +666,17 @@ class alignas(8) Module { /// Retrieve the umbrella directory as written. std::optional getUmbrellaDirAsWritten() const { - if (Umbrella && Umbrella.is()) + if (const auto *Dir = std::get_if(&Umbrella)) return DirectoryName{UmbrellaAsWritten, - UmbrellaRelativeToRootModuleDirectory, - Umbrella.get()}; + UmbrellaRelativeToRootModuleDirectory, *Dir}; return std::nullopt; } /// Retrieve the umbrella header as written. std::optional
getUmbrellaHeaderAsWritten() const { - if (Umbrella && Umbrella.is()) + if (const auto *Hdr = std::get_if(&Umbrella)) return Header{UmbrellaAsWritten, UmbrellaRelativeToRootModuleDirectory, - Umbrella.get()}; + *Hdr}; return std::nullopt; } diff --git a/clang/include/clang/Basic/OpenMPKinds.def b/clang/include/clang/Basic/OpenMPKinds.def index c999b8b9c4ff5..272537b769742 100644 --- a/clang/include/clang/Basic/OpenMPKinds.def +++ b/clang/include/clang/Basic/OpenMPKinds.def @@ -131,6 +131,7 @@ OPENMP_DEPEND_KIND(inoutallmemory) OPENMP_LINEAR_KIND(val) OPENMP_LINEAR_KIND(ref) OPENMP_LINEAR_KIND(uval) +OPENMP_LINEAR_KIND(step) // Modifiers for 'atomic_default_mem_order' clause. OPENMP_ATOMIC_DEFAULT_MEM_ORDER_KIND(seq_cst) diff --git a/clang/include/clang/Basic/TokenKinds.def b/clang/include/clang/Basic/TokenKinds.def index bbae1200d376c..3ce317d318f9b 100644 --- a/clang/include/clang/Basic/TokenKinds.def +++ b/clang/include/clang/Basic/TokenKinds.def @@ -423,9 +423,9 @@ C23_KEYWORD(typeof , KEYGNU) C23_KEYWORD(typeof_unqual , 0) // ISO/IEC JTC1 SC22 WG14 N1169 Extension -KEYWORD(_Accum , KEYALL) -KEYWORD(_Fract , KEYALL) -KEYWORD(_Sat , KEYALL) +KEYWORD(_Accum , KEYNOCXX) +KEYWORD(_Fract , KEYNOCXX) +KEYWORD(_Sat , KEYNOCXX) // GNU Extensions (in impl-reserved namespace) KEYWORD(_Decimal32 , KEYALL) diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td index a1585443e5fd2..b5baafedd1396 100644 --- a/clang/include/clang/Basic/arm_sve.td +++ b/clang/include/clang/Basic/arm_sve.td @@ -1977,4 +1977,6 @@ def SVPSEL_S : SInst<"svpsel_lane_b32", "PPPm", "Pi", MergeNone, "", [], []>; def SVPSEL_D : SInst<"svpsel_lane_b64", "PPPm", "Pl", MergeNone, "", [], []>; def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone, "aarch64_sve_cntp_{d}", [IsOverloadNone], [ImmCheck<1, ImmCheck2_4_Mul2>]>; + +defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUl", "aarch64_sve_revd">; } diff --git a/clang/include/clang/Basic/riscv_sifive_vector.td b/clang/include/clang/Basic/riscv_sifive_vector.td index 6583a7eb7b2e5..fb8561a05a0d4 100644 --- a/clang/include/clang/Basic/riscv_sifive_vector.td +++ b/clang/include/clang/Basic/riscv_sifive_vector.td @@ -103,3 +103,27 @@ let SupportOverloading = false in { defm sf_vc_v_fvw : RVVVCIXBuiltinSet<["si"], "UwKzUwUvFe", [-1, 0, 2, 3], UseGPR=0>; } } + +multiclass RVVVQMACCBuiltinSet> suffixes_prototypes> { + let OverloadedName = NAME, + Name = NAME, + HasMasked = false, + Log2LMUL = [0, 1, 2, 3] in + defm NAME : RVVOutOp1Op2BuiltinSet; +} + +let UnMaskedPolicyScheme = HasPolicyOperand in + let RequiredFeatures = ["Xsfvqmaccdod"] in { + defm sf_vqmaccu_2x8x2 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)Uv"]]>; + defm sf_vqmacc_2x8x2 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)v"]]>; + defm sf_vqmaccus_2x8x2 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)v"]]>; + defm sf_vqmaccsu_2x8x2 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)Uv"]]>; + } + +let UnMaskedPolicyScheme = HasPolicyOperand in + let RequiredFeatures = ["Xsfvqmaccqoq"] in { + defm sf_vqmaccu_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)Uv"]]>; + defm sf_vqmacc_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)v"]]>; + defm sf_vqmaccus_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)v"]]>; + defm sf_vqmaccsu_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)Uv"]]>; + } diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td index c685f3ef6087d..63316da940594 100644 --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -2320,6 +2320,15 @@ let HasMasked = false, HasVL = false, IRName = "" in { }] in { def vundefined : RVVBuiltin<"v", "v", "csilxfd">; def vundefined_u : RVVBuiltin<"Uv", "Uv", "csil">; + + foreach nf = NFList in { + let NF = nf in { + defvar T = "(Tuple:" # nf # ")"; + def : RVVBuiltin; + def : RVVBuiltin; + } + } + } // LMUL truncation diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index e63158fb0e533..7f3f5125d42e7 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -1382,9 +1382,13 @@ def dsym_dir : JoinedOrSeparate<["-"], "dsym-dir">, def dumpdir : Separate<["-"], "dumpdir">, Visibility<[ClangOption, CC1Option]>, MetaVarName<"">, HelpText<"Use as a prefix to form auxiliary and dump file names">; -def dumpmachine : Flag<["-"], "dumpmachine">; +def dumpmachine : Flag<["-"], "dumpmachine">, + Visibility<[ClangOption, FlangOption]>, + HelpText<"Display the compiler's target processor">; +def dumpversion : Flag<["-"], "dumpversion">, + Visibility<[ClangOption, FlangOption]>, + HelpText<"Display the version of the compiler">; def dumpspecs : Flag<["-"], "dumpspecs">, Flags<[Unsupported]>; -def dumpversion : Flag<["-"], "dumpversion">; def dylib__file : Separate<["-"], "dylib_file">; def dylinker__install__name : JoinedOrSeparate<["-"], "dylinker_install_name">; def dylinker : Flag<["-"], "dylinker">; @@ -1569,12 +1573,12 @@ def fprofile_sample_use : Flag<["-"], "fprofile-sample-use">, Group, def fno_profile_sample_use : Flag<["-"], "fno-profile-sample-use">, Group, Visibility<[ClangOption, CLOption]>; def fprofile_sample_use_EQ : Joined<["-"], "fprofile-sample-use=">, - Group, Flags<[NoXarchOption]>, + Group, Visibility<[ClangOption, CC1Option]>, HelpText<"Enable sample-based profile guided optimizations">, MarshallingInfoString>; def fprofile_sample_accurate : Flag<["-"], "fprofile-sample-accurate">, - Group, Flags<[NoXarchOption]>, + Group, Visibility<[ClangOption, CC1Option]>, HelpText<"Specifies that the sample profile is accurate">, DocBrief<[{Specifies that the sample profile is accurate. If the sample @@ -1583,15 +1587,14 @@ def fprofile_sample_accurate : Flag<["-"], "fprofile-sample-accurate">, we have no profile}]>, MarshallingInfoFlag>; def fsample_profile_use_profi : Flag<["-"], "fsample-profile-use-profi">, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CC1Option]>, + Visibility<[ClangOption, CC1Option]>, Group, HelpText<"Use profi to infer block and edge counts">, DocBrief<[{Infer block and edge counts. If the profiles have errors or missing blocks caused by sampling, profile inference (profi) can convert basic block counts to branch probabilites to fix them by extended and re-engineered classic MCMF (min-cost max-flow) approach.}]>; -def fno_profile_sample_accurate : Flag<["-"], "fno-profile-sample-accurate">, - Group, Flags<[NoXarchOption]>; +def fno_profile_sample_accurate : Flag<["-"], "fno-profile-sample-accurate">, Group; def fauto_profile : Flag<["-"], "fauto-profile">, Group, Alias; def fno_auto_profile : Flag<["-"], "fno-auto-profile">, Group, @@ -1662,7 +1665,7 @@ def fcs_profile_generate_EQ : Joined<["-"], "fcs-profile-generate=">, def fprofile_use : Flag<["-"], "fprofile-use">, Group, Visibility<[ClangOption, CLOption]>, Alias; def fprofile_use_EQ : Joined<["-"], "fprofile-use=">, - Group, Flags<[NoXarchOption]>, + Group, Visibility<[ClangOption, CLOption]>, MetaVarName<"">, HelpText<"Use instrumentation data for profile-guided optimization. If pathname is a directory, it reads from /default.profdata. Otherwise, it reads from file .">; @@ -1700,7 +1703,7 @@ defm pseudo_probe_for_profiling : BoolFOption<"pseudo-probe-for-profiling", CodeGenOpts<"PseudoProbeForProfiling">, DefaultFalse, PosFlag, NegFlag, - BothFlags<[NoXarchOption], [ClangOption, CC1Option], + BothFlags<[], [ClangOption, CC1Option], " pseudo probes for sample profiling">>; def forder_file_instrumentation : Flag<["-"], "forder-file-instrumentation">, Group, Visibility<[ClangOption, CC1Option, CLOption]>, @@ -1746,7 +1749,7 @@ defm borland_extensions : BoolFOption<"borland-extensions", def fbuiltin : Flag<["-"], "fbuiltin">, Group, Visibility<[ClangOption, CLOption, DXCOption]>; def fbuiltin_module_map : Flag <["-"], "fbuiltin-module-map">, Group, - Flags<[NoXarchOption]>, HelpText<"Load the clang builtins module map file.">; + Flags<[]>, HelpText<"Load the clang builtins module map file.">; defm caret_diagnostics : BoolFOption<"caret-diagnostics", DiagnosticOpts<"ShowCarets">, DefaultTrue, NegFlag, @@ -1864,7 +1867,7 @@ defm cxx_modules : BoolFOption<"cxx-modules", LangOpts<"CPlusPlusModules">, Default, NegFlag, PosFlag, - BothFlags<[NoXarchOption], [], " modules for C++">>, + BothFlags<[], [], " modules for C++">>, ShouldParseIf; def fdebug_pass_arguments : Flag<["-"], "fdebug-pass-arguments">, Group; def fdebug_pass_structure : Flag<["-"], "fdebug-pass-structure">, Group; @@ -1918,16 +1921,16 @@ defm safe_buffer_usage_suggestions : BoolFOption<"safe-buffer-usage-suggestions" NegFlag>; def fverify_intermediate_code : Flag<["-"], "fverify-intermediate-code">, Group, Visibility<[ClangOption, CLOption, DXCOption]>, - HelpText<"Enable verification of LLVM IR">, Flags<[NoXarchOption]>; + HelpText<"Enable verification of LLVM IR">; def fno_verify_intermediate_code : Flag<["-"], "fno-verify-intermediate-code">, Group, Visibility<[ClangOption, CLOption, DXCOption]>, - HelpText<"Disable verification of LLVM IR">, Flags<[NoXarchOption]>; + HelpText<"Disable verification of LLVM IR">; def fdiscard_value_names : Flag<["-"], "fdiscard-value-names">, Group, Visibility<[ClangOption, DXCOption]>, - HelpText<"Discard value names in LLVM IR">, Flags<[NoXarchOption]>; + HelpText<"Discard value names in LLVM IR">; def fno_discard_value_names : Flag<["-"], "fno-discard-value-names">, Group, Visibility<[ClangOption, DXCOption]>, - HelpText<"Do not discard value names in LLVM IR">, Flags<[NoXarchOption]>; + HelpText<"Do not discard value names in LLVM IR">; defm dollars_in_identifiers : BoolFOption<"dollars-in-identifiers", LangOpts<"DollarIdents">, Default, PosFlag, @@ -2040,7 +2043,6 @@ def ffp_eval_method_EQ : Joined<["-"], "ffp-eval-method=">, Group, NormalizedValues<["FEM_Source", "FEM_Double", "FEM_Extended"]>, MarshallingInfoEnum, "FEM_UnsetOnCommandLine">; def ffp_model_EQ : Joined<["-"], "ffp-model=">, Group, - Flags<[NoXarchOption]>, HelpText<"Controls the semantics of floating-point calculations.">; def ffp_exception_behavior_EQ : Joined<["-"], "ffp-exception-behavior=">, Group, Visibility<[ClangOption, CC1Option]>, @@ -2086,18 +2088,18 @@ defm keep_static_consts : BoolFOption<"keep-static-consts", CodeGenOpts<"KeepStaticConsts">, DefaultFalse, PosFlag, NegFlag, - BothFlags<[NoXarchOption], [], " static const variables even if unused">>; + BothFlags<[], [], " static const variables even if unused">>; defm keep_persistent_storage_variables : BoolFOption<"keep-persistent-storage-variables", CodeGenOpts<"KeepPersistentStorageVariables">, DefaultFalse, PosFlag, NegFlag, - BothFlags<[NoXarchOption], [], + BothFlags<[], [], " keeping all variables that have a persistent storage duration, including global, static and thread-local variables, to guarantee that they can be directly addressed">>; defm fixed_point : BoolFOption<"fixed-point", LangOpts<"FixedPoint">, DefaultFalse, PosFlag, NegFlag, - BothFlags<[], [ClangOption], " fixed point types">>; + BothFlags<[], [ClangOption], " fixed point types">>, ShouldParseIf; defm cxx_static_destructors : BoolFOption<"c++-static-destructors", LangOpts<"RegisterStaticDestructors">, DefaultTrue, NegFlag; def fno_sanitize_EQ : CommaJoined<["-"], "fno-sanitize=">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CLOption]>; def fsanitize_ignorelist_EQ : Joined<["-"], "fsanitize-ignorelist=">, @@ -2149,20 +2150,17 @@ def fsanitize_coverage : CommaJoined<["-"], "fsanitize-coverage=">, Group, HelpText<"Specify the type of coverage instrumentation for Sanitizers">; def fno_sanitize_coverage : CommaJoined<["-"], "fno-sanitize-coverage=">, - Group, Flags<[NoXarchOption]>, - Visibility<[ClangOption, CLOption]>, + Group, Visibility<[ClangOption, CLOption]>, HelpText<"Disable features of coverage instrumentation for Sanitizers">, Values<"func,bb,edge,indirect-calls,trace-bb,trace-cmp,trace-div,trace-gep," "8bit-counters,trace-pc,trace-pc-guard,no-prune,inline-8bit-counters," "inline-bool-flag">; def fsanitize_coverage_allowlist : Joined<["-"], "fsanitize-coverage-allowlist=">, - Group, Flags<[NoXarchOption]>, - Visibility<[ClangOption, CLOption]>, + Group, Visibility<[ClangOption, CLOption]>, HelpText<"Restrict sanitizer coverage instrumentation exclusively to modules and functions that match the provided special case list, except the blocked ones">, MarshallingInfoStringVector>; def fsanitize_coverage_ignorelist : Joined<["-"], "fsanitize-coverage-ignorelist=">, - Group, Flags<[NoXarchOption]>, - Visibility<[ClangOption, CLOption]>, + Group, Visibility<[ClangOption, CLOption]>, HelpText<"Disable sanitizer coverage instrumentation for modules and functions " "that match the provided special case list, even the allowed ones">, MarshallingInfoStringVector>; @@ -2186,7 +2184,6 @@ def fsanitize_memory_track_origins : Flag<["-"], "fsanitize-memory-track-origins HelpText<"Enable origins tracking in MemorySanitizer">; def fno_sanitize_memory_track_origins : Flag<["-"], "fno-sanitize-memory-track-origins">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CLOption]>, HelpText<"Disable origins tracking in MemorySanitizer">; def fsanitize_address_outline_instrumentation : Flag<["-"], "fsanitize-address-outline-instrumentation">, @@ -2208,7 +2205,7 @@ def fsanitize_hwaddress_experimental_aliasing HelpText<"Enable aliasing mode in HWAddressSanitizer">; def fno_sanitize_hwaddress_experimental_aliasing : Flag<["-"], "fno-sanitize-hwaddress-experimental-aliasing">, - Group, Flags<[NoXarchOption]>, + Group, Visibility<[ClangOption, CLOption]>, HelpText<"Disable aliasing mode in HWAddressSanitizer">; defm sanitize_memory_use_after_dtor : BoolOption<"f", "sanitize-memory-use-after-dtor", @@ -2224,7 +2221,7 @@ def fsanitize_address_field_padding : Joined<["-"], "fsanitize-address-field-pad defm sanitize_address_use_after_scope : BoolOption<"f", "sanitize-address-use-after-scope", CodeGenOpts<"SanitizeAddressUseAfterScope">, DefaultFalse, PosFlag, - NegFlag, BothFlags<[], [ClangOption], " use-after-scope detection in AddressSanitizer">>, Group; @@ -2299,20 +2296,18 @@ def fsanitize_recover_EQ : CommaJoined<["-"], "fsanitize-recover=">, Group, HelpText<"Enable recovery for specified sanitizers">; def fno_sanitize_recover_EQ : CommaJoined<["-"], "fno-sanitize-recover=">, - Group, Flags<[NoXarchOption]>, + Group, Visibility<[ClangOption, CLOption]>, HelpText<"Disable recovery for specified sanitizers">; def fsanitize_recover : Flag<["-"], "fsanitize-recover">, Group, Alias, AliasArgs<["all"]>; def fno_sanitize_recover : Flag<["-"], "fno-sanitize-recover">, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CLOption]>, Group, Alias, AliasArgs<["all"]>; def fsanitize_trap_EQ : CommaJoined<["-"], "fsanitize-trap=">, Group, HelpText<"Enable trapping for specified sanitizers">; def fno_sanitize_trap_EQ : CommaJoined<["-"], "fno-sanitize-trap=">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CLOption]>, HelpText<"Disable trapping for specified sanitizers">; def fsanitize_trap : Flag<["-"], "fsanitize-trap">, Group, @@ -2320,7 +2315,6 @@ def fsanitize_trap : Flag<["-"], "fsanitize-trap">, Group, HelpText<"Enable trapping for all sanitizers">; def fno_sanitize_trap : Flag<["-"], "fno-sanitize-trap">, Group, Alias, AliasArgs<["all"]>, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CLOption]>, HelpText<"Disable trapping for all sanitizers">; def fsanitize_undefined_trap_on_error @@ -2345,7 +2339,7 @@ def fno_sanitize_link_cxx_runtime : Flag<["-"], "fno-sanitize-link-c++-runtime"> defm sanitize_cfi_cross_dso : BoolOption<"f", "sanitize-cfi-cross-dso", CodeGenOpts<"SanitizeCfiCrossDso">, DefaultFalse, PosFlag, - NegFlag, BothFlags<[], [ClangOption], " control flow integrity (CFI) checks for cross-DSO calls.">>, Group; @@ -2360,14 +2354,14 @@ def fsanitize_cfi_icall_normalize_integers : Flag<["-"], "fsanitize-cfi-icall-ex defm sanitize_cfi_canonical_jump_tables : BoolOption<"f", "sanitize-cfi-canonical-jump-tables", CodeGenOpts<"SanitizeCfiCanonicalJumpTables">, DefaultFalse, PosFlag, - NegFlag, BothFlags<[], [ClangOption], " the jump table addresses canonical in the symbol table">>, Group; defm sanitize_stats : BoolOption<"f", "sanitize-stats", CodeGenOpts<"SanitizeStats">, DefaultFalse, PosFlag, - NegFlag, BothFlags<[], [ClangOption], " sanitizer statistics gathering.">>, Group; @@ -2376,7 +2370,6 @@ def fsanitize_thread_memory_access : Flag<["-"], "fsanitize-thread-memory-access HelpText<"Enable memory access instrumentation in ThreadSanitizer (default)">; def fno_sanitize_thread_memory_access : Flag<["-"], "fno-sanitize-thread-memory-access">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CLOption]>, HelpText<"Disable memory access instrumentation in ThreadSanitizer">; def fsanitize_thread_func_entry_exit : Flag<["-"], "fsanitize-thread-func-entry-exit">, @@ -2384,7 +2377,6 @@ def fsanitize_thread_func_entry_exit : Flag<["-"], "fsanitize-thread-func-entry- HelpText<"Enable function entry/exit instrumentation in ThreadSanitizer (default)">; def fno_sanitize_thread_func_entry_exit : Flag<["-"], "fno-sanitize-thread-func-entry-exit">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CLOption]>, HelpText<"Disable function entry/exit instrumentation in ThreadSanitizer">; def fsanitize_thread_atomics : Flag<["-"], "fsanitize-thread-atomics">, @@ -2392,7 +2384,6 @@ def fsanitize_thread_atomics : Flag<["-"], "fsanitize-thread-atomics">, HelpText<"Enable atomic operations instrumentation in ThreadSanitizer (default)">; def fno_sanitize_thread_atomics : Flag<["-"], "fno-sanitize-thread-atomics">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CLOption]>, HelpText<"Disable atomic operations instrumentation in ThreadSanitizer">; def fsanitize_undefined_strip_path_components_EQ : Joined<["-"], "fsanitize-undefined-strip-path-components=">, @@ -2798,8 +2789,7 @@ defm fat_lto_objects : BoolFOption<"fat-lto-objects", NegFlag, BothFlags<[], [ClangOption, CC1Option], " fat LTO object support">>; def fmacro_backtrace_limit_EQ : Joined<["-"], "fmacro-backtrace-limit=">, - Group, Flags<[NoXarchOption]>, - Visibility<[ClangOption, CC1Option, CLOption]>, + Group, Visibility<[ClangOption, CC1Option, CLOption]>, HelpText<"Set the maximum number of entries to print in a macro expansion backtrace (0 = no limit)">, MarshallingInfoInt, "DiagnosticOptions::DefaultMacroBacktraceLimit">; def fcaret_diagnostics_max_lines_EQ : @@ -2840,7 +2830,7 @@ def fms_volatile : Flag<["-"], "fms-volatile">, Group, Visibility<[ClangOption, CC1Option]>, MarshallingInfoFlag>; def fmsc_version : Joined<["-"], "fmsc-version=">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CLOption]>, + Visibility<[ClangOption, CLOption]>, HelpText<"Microsoft compiler version number to report in _MSC_VER (0 = don't define it (default))">; def fms_compatibility_version : Joined<["-"], "fms-compatibility-version=">, @@ -2850,7 +2840,7 @@ def fms_compatibility_version "version number to report in _MSC_VER (0 = don't define it " "(default))">; def fms_runtime_lib_EQ : Joined<["-"], "fms-runtime-lib=">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CLOption]>, + Flags<[]>, Visibility<[ClangOption, CLOption]>, Values<"static,static_dbg,dll,dll_dbg">, HelpText<"Select Windows run-time library">, DocBrief<[{ @@ -2859,13 +2849,13 @@ to the cl flags /MT and /MTd which use the multithread, static version. "dll" and "dll_dbg" correspond to the cl flags /MD and /MDd which use the multithread, dll version.}]>; def fms_omit_default_lib : Joined<["-"], "fms-omit-default-lib">, - Group, Flags<[NoXarchOption]>, + Group, Flags<[]>, Visibility<[ClangOption, CLOption]>; defm delayed_template_parsing : BoolFOption<"delayed-template-parsing", LangOpts<"DelayedTemplateParsing">, DefaultFalse, PosFlag, - NegFlag, + NegFlag, BothFlags<[], [ClangOption, CLOption]>>; def fms_memptr_rep_EQ : Joined<["-"], "fms-memptr-rep=">, Group, Visibility<[ClangOption, CC1Option]>, @@ -2891,22 +2881,22 @@ defm declspec : BoolOption<"f", "declspec", BothFlags<[], [ClangOption, CC1Option], " __declspec as a keyword">>, Group; def fmodules_cache_path : Joined<["-"], "fmodules-cache-path=">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CC1Option]>, + Flags<[]>, Visibility<[ClangOption, CC1Option]>, MetaVarName<"">, HelpText<"Specify the module cache path">; def fmodules_user_build_path : Separate<["-"], "fmodules-user-build-path">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CC1Option]>, + Flags<[]>, Visibility<[ClangOption, CC1Option]>, MetaVarName<"">, HelpText<"Specify the module user build path">, MarshallingInfoString>; def fprebuilt_module_path : Joined<["-"], "fprebuilt-module-path=">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CC1Option]>, + Flags<[]>, Visibility<[ClangOption, CC1Option]>, MetaVarName<"">, HelpText<"Specify the prebuilt module path">; defm prebuilt_implicit_modules : BoolFOption<"prebuilt-implicit-modules", HeaderSearchOpts<"EnablePrebuiltImplicitModules">, DefaultFalse, PosFlag, - NegFlag, BothFlags<[NoXarchOption], [ClangOption, CC1Option]>>; + NegFlag, BothFlags<[], [ClangOption, CC1Option]>>; def fmodule_output_EQ : Joined<["-"], "fmodule-output=">, Flags<[NoXarchOption]>, Visibility<[ClangOption, CC1Option]>, @@ -2944,10 +2934,10 @@ defm modules_validate_system_headers : BoolOption<"f", "modules-validate-system- HeaderSearchOpts<"ModulesValidateSystemHeaders">, DefaultFalse, PosFlag, - NegFlag>, Group; + NegFlag>, Group; def fno_modules_validate_textual_header_includes : Flag<["-"], "fno-modules-validate-textual-header-includes">, - Group, Flags<[NoXarchOption]>, Visibility<[ClangOption, CC1Option]>, + Group, Flags<[]>, Visibility<[ClangOption, CC1Option]>, MarshallingInfoNegativeFlag>, HelpText<"Do not enforce -fmodules-decluse and private header restrictions for textual headers. " "This flag will be removed in a future Clang release.">; @@ -2973,18 +2963,18 @@ def fforce_check_cxx20_modules_input_files: MarshallingInfoFlag>; def fmodules_validate_input_files_content: Flag <["-"], "fmodules-validate-input-files-content">, - Group, Flags<[NoXarchOption]>, + Group, HelpText<"Validate PCM input files based on content if mtime differs">; def fno_modules_validate_input_files_content: Flag <["-"], "fno_modules-validate-input-files-content">, - Group, Flags<[NoXarchOption]>; + Group; def fpch_validate_input_files_content: Flag <["-"], "fpch-validate-input-files-content">, - Group, Flags<[NoXarchOption]>, + Group, HelpText<"Validate PCH input files based on content if mtime differs">; def fno_pch_validate_input_files_content: Flag <["-"], "fno_pch-validate-input-files-content">, - Group, Flags<[NoXarchOption]>; + Group; defm pch_instantiate_templates : BoolFOption<"pch-instantiate-templates", LangOpts<"PCHInstantiateTemplates">, DefaultFalse, PosFlag, @@ -2996,7 +2986,6 @@ defm pch_debuginfo: OptInCC1FFlag<"pch-debuginfo", "Generate ", "Do not generate "debug info for types in an object file built from this PCH and do not generate them elsewhere">; def fimplicit_module_maps : Flag <["-"], "fimplicit-module-maps">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CC1Option, CLOption]>, HelpText<"Implicitly search the file system for module map files.">, MarshallingInfoFlag>; @@ -3008,7 +2997,6 @@ defm modules : BoolFOption<"modules", [NoXarchOption], [ClangOption, CLOption]>>; def fbuiltin_headers_in_system_modules : Flag <["-"], "fbuiltin-headers-in-system-modules">, Group, - Flags<[NoXarchOption]>, Visibility<[CC1Option]>, ShouldParseIf, HelpText<"builtin headers belong to system modules, and _Builtin_ modules are ignored for cstdlib headers">, @@ -3016,7 +3004,6 @@ def fbuiltin_headers_in_system_modules : Flag <["-"], "fbuiltin-headers-in-syste def fmodule_maps : Flag <["-"], "fmodule-maps">, Visibility<[ClangOption, CLOption]>, Alias; def fmodule_name_EQ : Joined<["-"], "fmodule-name=">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CC1Option, CLOption]>, MetaVarName<"">, HelpText<"Specify the name of the module to build">, @@ -3029,13 +3016,13 @@ def fsystem_module : Flag<["-"], "fsystem-module">, HelpText<"Build this module as a system module. Only used with -emit-module">, MarshallingInfoFlag>; def fmodule_map_file : Joined<["-"], "fmodule-map-file=">, - Group, Flags<[NoXarchOption]>, + Group, Visibility<[ClangOption, CC1Option, CLOption]>, MetaVarName<"">, HelpText<"Load this module map file">, MarshallingInfoStringVector>; def fmodule_file : Joined<["-"], "fmodule-file=">, - Group, Flags<[NoXarchOption]>, + Group, Visibility<[ClangOption, CC1Option, CLOption]>, MetaVarName<"[=]">, HelpText<"Specify the mapping of module name to precompiled module file, or load a module file if name is omitted.">; @@ -3043,7 +3030,6 @@ def fmodules_ignore_macro : Joined<["-"], "fmodules-ignore-macro=">, Group, HelpText<"Ignore the definition of the given macro when building and loading modules">; def fmodules_strict_decluse : Flag <["-"], "fmodules-strict-decluse">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CC1Option, CLOption]>, HelpText<"Like -fmodules-decluse but requires all headers to be in modules">, MarshallingInfoFlag>; @@ -3051,13 +3037,11 @@ defm modules_decluse : BoolFOption<"modules-decluse", LangOpts<"ModulesDeclUse">, Default, PosFlag, - NegFlag, BothFlags< - [NoXarchOption], [ClangOption, CLOption]>>; + NegFlag, BothFlags<[], [ClangOption, CLOption]>>; defm modules_search_all : BoolFOption<"modules-search-all", LangOpts<"ModulesSearchAll">, DefaultFalse, PosFlag, - NegFlag, BothFlags< - [NoXarchOption], [ClangOption, CC1Option, CLOption]>>, + NegFlag, BothFlags<[], [ClangOption, CC1Option, CLOption]>>, ShouldParseIf; defm implicit_modules : BoolFOption<"implicit-modules", LangOpts<"ImplicitModules">, DefaultTrue, @@ -3072,9 +3056,9 @@ def fretain_comments_from_system_headers : Flag<["-"], "fretain-comments-from-sy Visibility<[ClangOption, CC1Option]>, MarshallingInfoFlag>; def fmodule_header : Flag <["-"], "fmodule-header">, Group, - Flags<[NoXarchOption]>, HelpText<"Build a C++20 Header Unit from a header.">; + HelpText<"Build a C++20 Header Unit from a header">; def fmodule_header_EQ : Joined<["-"], "fmodule-header=">, Group, - Flags<[NoXarchOption]>, MetaVarName<"">, + MetaVarName<"">, HelpText<"Build a C++20 Header Unit from a header that should be found in the user (fmodule-header=user) or system (fmodule-header=system) search path.">; def fno_knr_functions : Flag<["-"], "fno-knr-functions">, Group, @@ -3125,15 +3109,11 @@ def fveclib : Joined<["-"], "fveclib=">, Group, MarshallingInfoEnum, "NoLibrary">; def fno_lax_vector_conversions : Flag<["-"], "fno-lax-vector-conversions">, Group, Alias, AliasArgs<["none"]>; -def fno_implicit_module_maps : Flag <["-"], "fno-implicit-module-maps">, Group, - Flags<[NoXarchOption]>; +def fno_implicit_module_maps : Flag <["-"], "fno-implicit-module-maps">, Group; def fno_module_maps : Flag <["-"], "fno-module-maps">, Alias; -def fno_modules_strict_decluse : Flag <["-"], "fno-strict-modules-decluse">, Group, - Flags<[NoXarchOption]>; -def fmodule_file_deps : Flag <["-"], "fmodule-file-deps">, Group, - Flags<[NoXarchOption]>; -def fno_module_file_deps : Flag <["-"], "fno-module-file-deps">, Group, - Flags<[NoXarchOption]>; +def fno_modules_strict_decluse : Flag <["-"], "fno-strict-modules-decluse">, Group; +def fmodule_file_deps : Flag <["-"], "fmodule-file-deps">, Group; +def fno_module_file_deps : Flag <["-"], "fno-module-file-deps">, Group; def fno_ms_extensions : Flag<["-"], "fno-ms-extensions">, Group, Visibility<[ClangOption, CLOption]>; def fno_ms_compatibility : Flag<["-"], "fno-ms-compatibility">, Group, @@ -3159,7 +3139,7 @@ defm diagnostics_show_line_numbers : BoolFOption<"diagnostics-show-line-numbers" def fno_stack_protector : Flag<["-"], "fno-stack-protector">, Group, HelpText<"Disable the use of stack protectors">; def fno_strict_aliasing : Flag<["-"], "fno-strict-aliasing">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CLOption, DXCOption]>, + Visibility<[ClangOption, CLOption, DXCOption]>, HelpText<"Disable optimizations based on strict aliasing rules">; def fstruct_path_tbaa : Flag<["-"], "fstruct-path-tbaa">, Group; def fno_struct_path_tbaa : Flag<["-"], "fno-struct-path-tbaa">, Group; @@ -3603,7 +3583,7 @@ def fno_debug_macro : Flag<["-"], "fno-debug-macro">, Group, Visibility<[ClangOption, CLOption, DXCOption]>, HelpText<"Do not emit macro debug information">; def fstrict_aliasing : Flag<["-"], "fstrict-aliasing">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CLOption, DXCOption]>, + Visibility<[ClangOption, CLOption, DXCOption]>, HelpText<"Enable optimizations based on strict aliasing rules">; def fstrict_enums : Flag<["-"], "fstrict-enums">, Group, Visibility<[ClangOption, CC1Option]>, @@ -3686,7 +3666,6 @@ def Wlarger_than_ : Joined<["-"], "Wlarger-than-">, Alias; // This is converted to -fwarn-stack-size=N and also passed through by the driver. // FIXME: The driver should strip out the = when passing W_value_Group through. def Wframe_larger_than_EQ : Joined<["-"], "Wframe-larger-than=">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CC1Option]>; def Wframe_larger_than : Flag<["-"], "Wframe-larger-than">, Alias; @@ -4302,7 +4281,7 @@ def mwatchsimulator_version_min_EQ : Joined<["-"], "mwatchsimulator-version-min= def march_EQ : Joined<["-"], "march=">, Group, Flags<[TargetSpecific]>, Visibility<[ClangOption, CLOption, DXCOption, FlangOption]>, HelpText<"For a list of available architectures for the target use '-mcpu=help'">; -def masm_EQ : Joined<["-"], "masm=">, Group, Flags<[NoXarchOption]>; +def masm_EQ : Joined<["-"], "masm=">, Group; def inline_asm_EQ : Joined<["-"], "inline-asm=">, Group, Visibility<[ClangOption, CC1Option]>, Values<"att,intel">, @@ -4315,7 +4294,7 @@ def mlarge_data_threshold_EQ : Joined<["-"], "mlarge-data-threshold=">, Group, MarshallingInfoInt, "65535">; def mtls_size_EQ : Joined<["-"], "mtls-size=">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CC1Option]>, + Visibility<[ClangOption, CC1Option]>, HelpText<"Specify bit size of immediate TLS offsets (AArch64 ELF only): " "12 (for 4KB) | 24 (for 16MB, default) | 32 (for 4GB) | 48 (for 256TB, needs -mcmodel=large)">, MarshallingInfoInt>; @@ -4460,32 +4439,32 @@ def mno_stackrealign : Flag<["-"], "mno-stackrealign">, Group; } // let Flags = [TargetSpecific] def mretpoline : Flag<["-"], "mretpoline">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CLOption]>; + Visibility<[ClangOption, CLOption]>; def mno_retpoline : Flag<["-"], "mno-retpoline">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CLOption]>; + Visibility<[ClangOption, CLOption]>; defm speculative_load_hardening : BoolOption<"m", "speculative-load-hardening", CodeGenOpts<"SpeculativeLoadHardening">, DefaultFalse, PosFlag, NegFlag, BothFlags<[], [ClangOption, CLOption]>>, Group; def mlvi_hardening : Flag<["-"], "mlvi-hardening">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CLOption]>, + Visibility<[ClangOption, CLOption]>, HelpText<"Enable all mitigations for Load Value Injection (LVI)">; def mno_lvi_hardening : Flag<["-"], "mno-lvi-hardening">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CLOption]>, + Visibility<[ClangOption, CLOption]>, HelpText<"Disable mitigations for Load Value Injection (LVI)">; def mlvi_cfi : Flag<["-"], "mlvi-cfi">, Group, Flags<[NoXarchOption]>, Visibility<[ClangOption, CLOption]>, HelpText<"Enable only control-flow mitigations for Load Value Injection (LVI)">; def mno_lvi_cfi : Flag<["-"], "mno-lvi-cfi">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CLOption]>, + Visibility<[ClangOption, CLOption]>, HelpText<"Disable control-flow mitigations for Load Value Injection (LVI)">; def m_seses : Flag<["-"], "mseses">, Group, Flags<[NoXarchOption]>, Visibility<[ClangOption, CLOption]>, HelpText<"Enable speculative execution side effect suppression (SESES). " "Includes LVI control flow integrity mitigations">; def mno_seses : Flag<["-"], "mno-seses">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CLOption]>, + Visibility<[ClangOption, CLOption]>, HelpText<"Disable speculative execution side effect suppression (SESES)">; def mrelax : Flag<["-"], "mrelax">, Group, @@ -4501,14 +4480,6 @@ def msave_restore : Flag<["-"], "msave-restore">, Group, def mno_save_restore : Flag<["-"], "mno-save-restore">, Group, HelpText<"Disable using library calls for save and restore">; } // let Flags = [TargetSpecific] -def mcmodel_EQ_medlow : Flag<["-"], "mcmodel=medlow">, Group, - Visibility<[ClangOption, CC1Option]>, - Alias, AliasArgs<["small"]>, - HelpText<"Equivalent to -mcmodel=small, compatible with RISC-V gcc.">; -def mcmodel_EQ_medany : Flag<["-"], "mcmodel=medany">, Group, - Visibility<[ClangOption, CC1Option]>, - Alias, AliasArgs<["medium"]>, - HelpText<"Equivalent to -mcmodel=medium, compatible with RISC-V gcc.">; let Flags = [TargetSpecific] in { def menable_experimental_extensions : Flag<["-"], "menable-experimental-extensions">, Group, HelpText<"Enable use of experimental RISC-V extensions.">; @@ -4549,18 +4520,18 @@ def mno_neg_immediates: Flag<["-"], "mno-neg-immediates">, Group; } // let Flags = [TargetSpecific] def mcmse : Flag<["-"], "mcmse">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CC1Option]>, + Visibility<[ClangOption, CC1Option]>, HelpText<"Allow use of CMSE (Armv8-M Security Extensions)">, MarshallingInfoFlag>; def ForceAAPCSBitfieldLoad : Flag<["-"], "faapcs-bitfield-load">, Group, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CC1Option]>, + Visibility<[ClangOption, CC1Option]>, HelpText<"Follows the AAPCS standard that all volatile bit-field write generates at least one load. (ARM only).">, MarshallingInfoFlag>; defm aapcs_bitfield_width : BoolOption<"f", "aapcs-bitfield-width", CodeGenOpts<"AAPCSBitfieldWidth">, DefaultTrue, NegFlag, PosFlag, - BothFlags<[NoXarchOption], [ClangOption, CC1Option], + BothFlags<[], [ClangOption, CC1Option], " the AAPCS standard requirement stating that" " volatile bit-field width is dictated by the field container type. (ARM only).">>, Group; @@ -4712,9 +4683,8 @@ defm unsafe_fp_atomics : BoolOption<"m", "unsafe-fp-atomics", "for certain memory destinations. (AMDGPU only)">, NegFlag>, Group; -def faltivec : Flag<["-"], "faltivec">, Group, Flags<[NoXarchOption]>; -def fno_altivec : Flag<["-"], "fno-altivec">, Group, - Flags<[NoXarchOption]>; +def faltivec : Flag<["-"], "faltivec">, Group; +def fno_altivec : Flag<["-"], "fno-altivec">, Group; let Flags = [TargetSpecific] in { def maltivec : Flag<["-"], "maltivec">, Group, HelpText<"Enable AltiVec vector initializer syntax">; @@ -4842,8 +4812,7 @@ HelpText<"Not emit the visibility attribute for asm in AIX OS or give all symbol defm backchain : BoolOption<"m", "backchain", CodeGenOpts<"Backchain">, DefaultFalse, PosFlag, - NegFlag, BothFlags<[NoXarchOption], [ClangOption, CC1Option] - >>, Group; + NegFlag, BothFlags<[], [ClangOption, CC1Option]>>, Group; def mno_warn_nonportable_cfstrings : Flag<["-"], "mno-warn-nonportable-cfstrings">, Group; def mno_omit_leaf_frame_pointer : Flag<["-"], "mno-omit-leaf-frame-pointer">, Group; @@ -5081,7 +5050,7 @@ def mno_relax_pic_calls : Flag<["-"], "mno-relax-pic-calls">, "call sequences into direct calls (MIPS only)">, Flags<[HelpHidden]>; def mglibc : Flag<["-"], "mglibc">, Group, Flags<[HelpHidden]>; def muclibc : Flag<["-"], "muclibc">, Group, Flags<[HelpHidden]>; -def module_file_info : Flag<["-"], "module-file-info">, Flags<[NoXarchOption]>, +def module_file_info : Flag<["-"], "module-file-info">, Flags<[]>, Visibility<[ClangOption, CC1Option]>, Group, HelpText<"Provide information about a particular module file">; def mthumb : Flag<["-"], "mthumb">, Group; @@ -5098,8 +5067,7 @@ def no_canonical_prefixes : Flag<["-"], "no-canonical-prefixes">, Flags<[HelpHidden]>, Visibility<[ClangOption, CLOption, DXCOption]>, HelpText<"Use relative paths for invoking subcommands">; def no_cpp_precomp : Flag<["-"], "no-cpp-precomp">, Group; -def no_integrated_cpp : Flag<["-", "--"], "no-integrated-cpp">, - Flags<[NoXarchOption]>; +def no_integrated_cpp : Flag<["-", "--"], "no-integrated-cpp">; def no_pedantic : Flag<["-", "--"], "no-pedantic">, Group; def no__dead__strip__inits__and__terms : Flag<["-"], "no_dead_strip_inits_and_terms">; def nobuiltininc : Flag<["-"], "nobuiltininc">, @@ -5421,29 +5389,25 @@ defm integrated_as : BoolFOption<"integrated-as", BothFlags<[], [ClangOption], " the integrated assembler">>; def fintegrated_cc1 : Flag<["-"], "fintegrated-cc1">, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CLOption, DXCOption]>, Group, HelpText<"Run cc1 in-process">; def fno_integrated_cc1 : Flag<["-"], "fno-integrated-cc1">, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CLOption, DXCOption]>, Group, HelpText<"Spawn a separate process for each cc1">; def fintegrated_objemitter : Flag<["-"], "fintegrated-objemitter">, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CLOption]>, + Visibility<[ClangOption, CLOption]>, Group, HelpText<"Use internal machine object code emitter.">; def fno_integrated_objemitter : Flag<["-"], "fno-integrated-objemitter">, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CLOption]>, + Visibility<[ClangOption, CLOption]>, Group, HelpText<"Use external machine object code emitter.">; -def : Flag<["-"], "integrated-as">, Alias, - Flags<[NoXarchOption]>; +def : Flag<["-"], "integrated-as">, Alias; def : Flag<["-"], "no-integrated-as">, Alias, - Flags<[NoXarchOption]>, Visibility<[ClangOption, CC1Option, FlangOption]>; def working_directory : Separate<["-"], "working-directory">, @@ -6196,10 +6160,10 @@ defm : FlangIgnoredDiagOpt<"frontend-loop-interchange">; defm : FlangIgnoredDiagOpt<"target-lifetime">; // C++ SYCL options -def fsycl : Flag<["-"], "fsycl">, Flags<[NoXarchOption]>, +def fsycl : Flag<["-"], "fsycl">, Visibility<[ClangOption, CLOption]>, Group, HelpText<"Enables SYCL kernels compilation for device">; -def fno_sycl : Flag<["-"], "fno-sycl">, Flags<[NoXarchOption]>, +def fno_sycl : Flag<["-"], "fno-sycl">, Visibility<[ClangOption, CLOption]>, Group, HelpText<"Disables SYCL kernels compilation for device">; @@ -6208,11 +6172,11 @@ def fno_sycl : Flag<["-"], "fno-sycl">, Flags<[NoXarchOption]>, //===----------------------------------------------------------------------===// def flang_experimental_hlfir : Flag<["-"], "flang-experimental-hlfir">, - Flags<[NoXarchOption, HelpHidden]>, Visibility<[FlangOption, FC1Option]>, + Flags<[HelpHidden]>, Visibility<[FlangOption, FC1Option]>, HelpText<"Use HLFIR lowering (experimental)">; def flang_experimental_polymorphism : Flag<["-"], "flang-experimental-polymorphism">, - Flags<[NoXarchOption, HelpHidden]>, Visibility<[FlangOption, FC1Option]>, + Flags<[HelpHidden]>, Visibility<[FlangOption, FC1Option]>, HelpText<"Enable Fortran 2003 polymorphism (experimental)">; @@ -8301,9 +8265,9 @@ def _SLASH_ZW : CLJoined<"ZW">; def dxc_Group : OptionGroup<"">, Visibility<[DXCOption]>, HelpText<"dxc compatibility options">; class DXCFlag : Option<["/", "-"], name, KIND_FLAG>, - Group, Flags<[NoXarchOption]>, Visibility<[DXCOption]>; + Group, Visibility<[DXCOption]>; class DXCJoinedOrSeparate : Option<["/", "-"], name, - KIND_JOINED_OR_SEPARATE>, Group, Flags<[NoXarchOption]>, + KIND_JOINED_OR_SEPARATE>, Group, Visibility<[DXCOption]>; def dxc_no_stdinc : DXCFlag<"hlsl-no-stdinc">, @@ -8313,7 +8277,7 @@ def dxc_Fo : DXCJoinedOrSeparate<"Fo">, def dxc_Fc : DXCJoinedOrSeparate<"Fc">, HelpText<"Output assembly listing file">; def dxil_validator_version : Option<["/", "-"], "validator-version", KIND_SEPARATE>, - Group, Flags<[NoXarchOption, HelpHidden]>, + Group, Flags<[HelpHidden]>, Visibility<[DXCOption, ClangOption, CC1Option]>, HelpText<"Override validator version for module. Format: ;" "Default: DXIL.dll version or current internal version">, @@ -8343,12 +8307,12 @@ def hlsl_entrypoint : Option<["-"], "hlsl-entry", KIND_SEPARATE>, HelpText<"Entry point name for hlsl">; def dxc_entrypoint : Option<["--", "/", "-"], "E", KIND_JOINED_OR_SEPARATE>, Group, - Flags<[NoXarchOption]>, Visibility<[DXCOption]>, + Visibility<[DXCOption]>, HelpText<"Entry point name">; def dxc_validator_path_EQ : Joined<["--"], "dxv-path=">, Group, HelpText<"DXIL validator installation path">; def dxc_disable_validation : DXCFlag<"Vd">, HelpText<"Disable validation">; def : Option<["/", "-"], "Qembed_debug", KIND_FLAG>, Group, - Flags<[Ignored, NoXarchOption]>, Visibility<[DXCOption]>, + Flags<[Ignored]>, Visibility<[DXCOption]>, HelpText<"Embed PDB in shader container (ignored)">; diff --git a/clang/include/clang/Format/Format.h b/clang/include/clang/Format/Format.h index 2707ea608c74e..3e9d1915badd8 100644 --- a/clang/include/clang/Format/Format.h +++ b/clang/include/clang/Format/Format.h @@ -539,6 +539,10 @@ struct FormatStyle { /// Control of trailing comments. /// + /// The alignment stops at closing braces after a line break, and only + /// followed by other closing braces, a (``do-``) ``while``, a lambda call, or + /// a semicolon. + /// /// \note /// As of clang-format 16 this option is not a bool but can be set /// to the options. Conventional bool options still can be parsed as before. @@ -681,6 +685,25 @@ struct FormatStyle { /// \version 3.6 bool AllowShortCaseLabelsOnASingleLine; + /// Allow short compound requirement on a single line. + /// \code + /// true: + /// template + /// concept c = requires(T x) { + /// { x + 1 } -> std::same_as; + /// }; + /// + /// false: + /// template + /// concept c = requires(T x) { + /// { + /// x + 1 + /// } -> std::same_as; + /// }; + /// \endcode + /// \version 18 + bool AllowShortCompoundRequirementOnASingleLine; + /// Allow short enums on a single line. /// \code /// true: @@ -4128,6 +4151,28 @@ struct FormatStyle { /// object.operator++ (10); object.operator++(10); /// \endcode bool AfterOverloadedOperator; + /// Styles for adding spacing between ``new/delete`` operators and opening + /// parentheses. + enum AfterPlacementOperatorStyle : int8_t { + /// Remove space after ``new/delete`` operators and before ``(``. + /// \code + /// new(buf) T; + /// delete(buf) T; + /// \endcode + APO_Never, + /// Always add space after ``new/delete`` operators and before ``(``. + /// \code + /// new (buf) T; + /// delete (buf) T; + /// \endcode + APO_Always, + /// Leave placement ``new/delete`` expressions as they are. + APO_Leave, + }; + /// Defines in which cases to put a space between ``new/delete`` operators + /// and opening parentheses. + /// \version 18 + AfterPlacementOperatorStyle AfterPlacementOperator; /// If ``true``, put space between requires keyword in a requires clause and /// opening parentheses, if there is one. /// \code @@ -4160,8 +4205,9 @@ struct FormatStyle { : AfterControlStatements(false), AfterForeachMacros(false), AfterFunctionDeclarationName(false), AfterFunctionDefinitionName(false), AfterIfMacros(false), - AfterOverloadedOperator(false), AfterRequiresInClause(false), - AfterRequiresInExpression(false), BeforeNonEmptyParentheses(false) {} + AfterOverloadedOperator(false), AfterPlacementOperator(APO_Leave), + AfterRequiresInClause(false), AfterRequiresInExpression(false), + BeforeNonEmptyParentheses(false) {} bool operator==(const SpaceBeforeParensCustom &Other) const { return AfterControlStatements == Other.AfterControlStatements && @@ -4171,6 +4217,7 @@ struct FormatStyle { AfterFunctionDefinitionName == Other.AfterFunctionDefinitionName && AfterIfMacros == Other.AfterIfMacros && AfterOverloadedOperator == Other.AfterOverloadedOperator && + AfterPlacementOperator == Other.AfterPlacementOperator && AfterRequiresInClause == Other.AfterRequiresInClause && AfterRequiresInExpression == Other.AfterRequiresInExpression && BeforeNonEmptyParentheses == Other.BeforeNonEmptyParentheses; @@ -4622,6 +4669,8 @@ struct FormatStyle { AllowShortBlocksOnASingleLine == R.AllowShortBlocksOnASingleLine && AllowShortCaseLabelsOnASingleLine == R.AllowShortCaseLabelsOnASingleLine && + AllowShortCompoundRequirementOnASingleLine == + R.AllowShortCompoundRequirementOnASingleLine && AllowShortEnumsOnASingleLine == R.AllowShortEnumsOnASingleLine && AllowShortFunctionsOnASingleLine == R.AllowShortFunctionsOnASingleLine && @@ -4837,6 +4886,8 @@ FormatStyle getGNUStyle(); /// https://docs.microsoft.com/en-us/visualstudio/ide/editorconfig-code-style-settings-reference?view=vs-2017 FormatStyle getMicrosoftStyle(FormatStyle::LanguageKind Language); +FormatStyle getClangFormatStyle(); + /// Returns style indicating formatting should be not applied at all. FormatStyle getNoStyle(); diff --git a/clang/include/clang/Frontend/VerifyDiagnosticConsumer.h b/clang/include/clang/Frontend/VerifyDiagnosticConsumer.h index e0f3570e5b2bc..500a7e11ab9ac 100644 --- a/clang/include/clang/Frontend/VerifyDiagnosticConsumer.h +++ b/clang/include/clang/Frontend/VerifyDiagnosticConsumer.h @@ -278,14 +278,15 @@ class VerifyDiagnosticConsumer: public DiagnosticConsumer, // These facilities are used for validation in debug builds. class UnparsedFileStatus { - llvm::PointerIntPair Data; + OptionalFileEntryRef File; + bool FoundDirectives; public: UnparsedFileStatus(OptionalFileEntryRef File, bool FoundDirectives) - : Data(File, FoundDirectives) {} + : File(File), FoundDirectives(FoundDirectives) {} - OptionalFileEntryRef getFile() const { return Data.getPointer(); } - bool foundDirectives() const { return Data.getInt(); } + OptionalFileEntryRef getFile() const { return File; } + bool foundDirectives() const { return FoundDirectives; } }; using ParsedFilesMap = llvm::DenseMap; diff --git a/clang/include/clang/Lex/ModuleMap.h b/clang/include/clang/Lex/ModuleMap.h index fc49742ad4af2..69ec8f34a3242 100644 --- a/clang/include/clang/Lex/ModuleMap.h +++ b/clang/include/clang/Lex/ModuleMap.h @@ -20,8 +20,8 @@ #include "clang/Basic/SourceLocation.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/DenseSet.h" #include "llvm/ADT/PointerIntPair.h" -#include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringMap.h" #include "llvm/ADT/StringRef.h" @@ -194,7 +194,7 @@ class ModuleMap { } }; - using AdditionalModMapsSet = llvm::SmallPtrSet; + using AdditionalModMapsSet = llvm::DenseSet; private: friend class ModuleMapParser; @@ -410,13 +410,16 @@ class ModuleMap { } /// Get the directory that contains Clang-supplied include files. - const DirectoryEntry *getBuiltinDir() const { + OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr getBuiltinDir() const { return BuiltinIncludeDir; } /// Is this a compiler builtin header? bool isBuiltinHeader(FileEntryRef File); + bool shouldImportRelativeToBuiltinIncludeDir(StringRef FileName, + Module *Module) const; + /// Add a module map callback. void addModuleMapCallbacks(std::unique_ptr Callback) { Callbacks.push_back(std::move(Callback)); diff --git a/clang/include/clang/Lex/Preprocessor.h b/clang/include/clang/Lex/Preprocessor.h index 18d88407ae12c..4a99447e757c6 100644 --- a/clang/include/clang/Lex/Preprocessor.h +++ b/clang/include/clang/Lex/Preprocessor.h @@ -2879,9 +2879,9 @@ class Preprocessor { /// Alter the state of whether this PP currently is in a /// "-Wunsafe-buffer-usage" opt-out region. /// - /// \param isEnter: true if this PP is entering a region; otherwise, this PP + /// \param isEnter true if this PP is entering a region; otherwise, this PP /// is exiting a region - /// \param Loc: the location of the entry or exit of a + /// \param Loc the location of the entry or exit of a /// region /// \return true iff it is INVALID to enter or exit a region, i.e., /// attempt to enter a region before exiting a previous region, or exiting a @@ -2893,7 +2893,7 @@ class Preprocessor { /// opt-out region bool isPPInSafeBufferOptOutRegion(); - /// \param StartLoc: output argument. It will be set to the start location of + /// \param StartLoc output argument. It will be set to the start location of /// the current "-Wunsafe-buffer-usage" opt-out region iff this function /// returns true. /// \return true iff this PP is currently in a "-Wunsafe-buffer-usage" diff --git a/clang/include/clang/Sema/ScopeInfo.h b/clang/include/clang/Sema/ScopeInfo.h index 361108fb51ba0..b2f6e3289f41f 100644 --- a/clang/include/clang/Sema/ScopeInfo.h +++ b/clang/include/clang/Sema/ScopeInfo.h @@ -189,6 +189,9 @@ class FunctionScopeInfo { /// First SEH '__try' statement in the current function. SourceLocation FirstSEHTryLoc; + /// First use of a VLA within the current function. + SourceLocation FirstVLALoc; + private: /// Used to determine if errors occurred in this function or block. DiagnosticErrorTrap ErrorTrap; @@ -473,6 +476,11 @@ class FunctionScopeInfo { FirstSEHTryLoc = TryLoc; } + void setHasVLA(SourceLocation VLALoc) { + if (FirstVLALoc.isInvalid()) + FirstVLALoc = VLALoc; + } + bool NeedsScopeChecking() const { return !HasDroppedStmt && (HasIndirectGoto || HasMustTail || (HasBranchProtectedScope && HasBranchIntoScope)); @@ -1027,7 +1035,7 @@ class LambdaScopeInfo final : return NonODRUsedCapturingExprs.count(CapturingVarExpr); } void removePotentialCapture(Expr *E) { - llvm::erase_value(PotentiallyCapturingExprs, E); + llvm::erase(PotentiallyCapturingExprs, E); } void clearPotentialCaptures() { PotentiallyCapturingExprs.clear(); diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index 73fee208cbef1..1e9752345ffd1 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -12307,6 +12307,8 @@ class Sema final { bool IsMapTypeImplicit = false; SourceLocation ExtraModifierLoc; SourceLocation OmpAllMemoryLoc; + SourceLocation + StepModifierLoc; /// 'step' modifier location for linear clause }; OMPClause *ActOnOpenMPVarListClause(OpenMPClauseKind Kind, @@ -12371,11 +12373,11 @@ class Sema final { const DeclarationNameInfo &ReductionId, ArrayRef UnresolvedReductions = std::nullopt); /// Called on well-formed 'linear' clause. - OMPClause * - ActOnOpenMPLinearClause(ArrayRef VarList, Expr *Step, - SourceLocation StartLoc, SourceLocation LParenLoc, - OpenMPLinearClauseKind LinKind, SourceLocation LinLoc, - SourceLocation ColonLoc, SourceLocation EndLoc); + OMPClause *ActOnOpenMPLinearClause( + ArrayRef VarList, Expr *Step, SourceLocation StartLoc, + SourceLocation LParenLoc, OpenMPLinearClauseKind LinKind, + SourceLocation LinLoc, SourceLocation ColonLoc, + SourceLocation StepModifierLoc, SourceLocation EndLoc); /// Called on well-formed 'aligned' clause. OMPClause *ActOnOpenMPAlignedClause(ArrayRef VarList, Expr *Alignment, diff --git a/clang/include/clang/StaticAnalyzer/Checkers/Checkers.td b/clang/include/clang/StaticAnalyzer/Checkers/Checkers.td index be813bde8be41..b6e9f0fae1c7f 100644 --- a/clang/include/clang/StaticAnalyzer/Checkers/Checkers.td +++ b/clang/include/clang/StaticAnalyzer/Checkers/Checkers.td @@ -1002,6 +1002,15 @@ let ParentPackage = ENV in { def InvalidPtrChecker : Checker<"InvalidPtr">, HelpText<"Finds usages of possibly invalidated pointers">, + CheckerOptions<[ + CmdLineOption, + ]>, Documentation; } // end "alpha.cert.env" diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h b/clang/include/clang/Support/RISCVVIntrinsicUtils.h index 8ba57d77221dc..90d99b7efa8af 100644 --- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h +++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h @@ -485,14 +485,16 @@ enum RVVRequire : uint16_t { RVV_REQ_RV64 = 1 << 0, RVV_REQ_ZvfhminOrZvfh = 1 << 1, RVV_REQ_Xsfvcp = 1 << 2, - RVV_REQ_Zvbb = 1 << 3, - RVV_REQ_Zvbc = 1 << 4, - RVV_REQ_Zvkb = 1 << 5, - RVV_REQ_Zvkg = 1 << 6, - RVV_REQ_Zvkned = 1 << 7, - RVV_REQ_Zvknha = 1 << 8, - RVV_REQ_Zvksed = 1 << 9, - RVV_REQ_Zvksh = 1 << 10, + RVV_REQ_Xsfvqmaccdod = 1 << 3, + RVV_REQ_Xsfvqmaccqoq = 1 << 4, + RVV_REQ_Zvbb = 1 << 5, + RVV_REQ_Zvbc = 1 << 6, + RVV_REQ_Zvkb = 1 << 7, + RVV_REQ_Zvkg = 1 << 8, + RVV_REQ_Zvkned = 1 << 9, + RVV_REQ_Zvknha = 1 << 10, + RVV_REQ_Zvksed = 1 << 11, + RVV_REQ_Zvksh = 1 << 12, LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Zvksh) }; diff --git a/clang/lib/APINotes/APINotesReader.cpp b/clang/lib/APINotes/APINotesReader.cpp new file mode 100644 index 0000000000000..2cbf5fd3bf503 --- /dev/null +++ b/clang/lib/APINotes/APINotesReader.cpp @@ -0,0 +1,2048 @@ +//===--- APINotesReader.cpp - API Notes Reader ------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "clang/APINotes/APINotesReader.h" +#include "APINotesFormat.h" +#include "llvm/ADT/Hashing.h" +#include "llvm/ADT/StringExtras.h" +#include "llvm/Bitstream/BitstreamReader.h" +#include "llvm/Support/DJB.h" +#include "llvm/Support/EndianStream.h" +#include "llvm/Support/OnDiskHashTable.h" + +namespace clang { +namespace api_notes { +using namespace llvm::support; + +namespace { +/// Deserialize a version tuple. +llvm::VersionTuple ReadVersionTuple(const uint8_t *&Data) { + uint8_t NumVersions = (*Data++) & 0x03; + + unsigned Major = + endian::readNext(Data); + if (NumVersions == 0) + return llvm::VersionTuple(Major); + + unsigned Minor = + endian::readNext(Data); + if (NumVersions == 1) + return llvm::VersionTuple(Major, Minor); + + unsigned Subminor = + endian::readNext(Data); + if (NumVersions == 2) + return llvm::VersionTuple(Major, Minor, Subminor); + + unsigned Build = + endian::readNext(Data); + return llvm::VersionTuple(Major, Minor, Subminor, Build); +} + +/// An on-disk hash table whose data is versioned based on the Swift version. +template +class VersionedTableInfo { +public: + using internal_key_type = KeyType; + using external_key_type = KeyType; + using data_type = + llvm::SmallVector, 1>; + using hash_value_type = size_t; + using offset_type = unsigned; + + internal_key_type GetInternalKey(external_key_type Key) { return Key; } + + external_key_type GetExternalKey(internal_key_type Key) { return Key; } + + static bool EqualKey(internal_key_type LHS, internal_key_type RHS) { + return LHS == RHS; + } + + static std::pair ReadKeyDataLength(const uint8_t *&Data) { + unsigned KeyLength = + endian::readNext(Data); + unsigned DataLength = + endian::readNext(Data); + return {KeyLength, DataLength}; + } + + static data_type ReadData(internal_key_type Key, const uint8_t *Data, + unsigned Length) { + unsigned NumElements = + endian::readNext(Data); + data_type Result; + Result.reserve(NumElements); + for (unsigned i = 0; i != NumElements; ++i) { + auto version = ReadVersionTuple(Data); + const auto *DataBefore = Data; + (void)DataBefore; + assert(Data != DataBefore && + "Unversioned data reader didn't move pointer"); + auto UnversionedData = Derived::readUnversioned(Key, Data); + Result.push_back({version, UnversionedData}); + } + return Result; + } +}; + +/// Read serialized CommonEntityInfo. +void ReadCommonEntityInfo(const uint8_t *&Data, CommonEntityInfo &Info) { + uint8_t UnavailableBits = *Data++; + Info.Unavailable = (UnavailableBits >> 1) & 0x01; + Info.UnavailableInSwift = UnavailableBits & 0x01; + if ((UnavailableBits >> 2) & 0x01) + Info.setSwiftPrivate(static_cast((UnavailableBits >> 3) & 0x01)); + + unsigned MsgLength = + endian::readNext(Data); + Info.UnavailableMsg = + std::string(reinterpret_cast(Data), + reinterpret_cast(Data) + MsgLength); + Data += MsgLength; + + unsigned SwiftNameLength = + endian::readNext(Data); + Info.SwiftName = + std::string(reinterpret_cast(Data), + reinterpret_cast(Data) + SwiftNameLength); + Data += SwiftNameLength; +} + +/// Read serialized CommonTypeInfo. +void ReadCommonTypeInfo(const uint8_t *&Data, CommonTypeInfo &Info) { + ReadCommonEntityInfo(Data, Info); + + unsigned SwiftBridgeLength = + endian::readNext(Data); + if (SwiftBridgeLength > 0) { + Info.setSwiftBridge(std::string(reinterpret_cast(Data), + SwiftBridgeLength - 1)); + Data += SwiftBridgeLength - 1; + } + + unsigned ErrorDomainLength = + endian::readNext(Data); + if (ErrorDomainLength > 0) { + Info.setNSErrorDomain(std::optional(std::string( + reinterpret_cast(Data), ErrorDomainLength - 1))); + Data += ErrorDomainLength - 1; + } +} + +/// Used to deserialize the on-disk identifier table. +class IdentifierTableInfo { +public: + using internal_key_type = llvm::StringRef; + using external_key_type = llvm::StringRef; + using data_type = IdentifierID; + using hash_value_type = uint32_t; + using offset_type = unsigned; + + internal_key_type GetInternalKey(external_key_type Key) { return Key; } + + external_key_type GetExternalKey(internal_key_type Key) { return Key; } + + hash_value_type ComputeHash(internal_key_type Key) { + return llvm::hash_value(Key); + } + + static bool EqualKey(internal_key_type LHS, internal_key_type RHS) { + return LHS == RHS; + } + + static std::pair ReadKeyDataLength(const uint8_t *&Data) { + unsigned KeyLength = + endian::readNext(Data); + unsigned DataLength = + endian::readNext(Data); + return {KeyLength, DataLength}; + } + + static internal_key_type ReadKey(const uint8_t *Data, unsigned Length) { + return llvm::StringRef(reinterpret_cast(Data), Length); + } + + static data_type ReadData(internal_key_type key, const uint8_t *Data, + unsigned Length) { + return endian::readNext( + Data); + } +}; + +/// Used to deserialize the on-disk Objective-C class table. +class ObjCContextIDTableInfo { +public: + using internal_key_type = ContextTableKey; + using external_key_type = internal_key_type; + using data_type = unsigned; + using hash_value_type = size_t; + using offset_type = unsigned; + + internal_key_type GetInternalKey(external_key_type Key) { return Key; } + + external_key_type GetExternalKey(internal_key_type Key) { return Key; } + + hash_value_type ComputeHash(internal_key_type Key) { + return static_cast(Key.hashValue()); + } + + static bool EqualKey(internal_key_type LHS, internal_key_type RHS) { + return LHS == RHS; + } + + static std::pair ReadKeyDataLength(const uint8_t *&Data) { + unsigned KeyLength = + endian::readNext(Data); + unsigned DataLength = + endian::readNext(Data); + return {KeyLength, DataLength}; + } + + static internal_key_type ReadKey(const uint8_t *Data, unsigned Length) { + auto ParentCtxID = + endian::readNext(Data); + auto ContextKind = + endian::readNext(Data); + auto NameID = + endian::readNext(Data); + return {ParentCtxID, ContextKind, NameID}; + } + + static data_type ReadData(internal_key_type Key, const uint8_t *Data, + unsigned Length) { + return endian::readNext( + Data); + } +}; + +/// Used to deserialize the on-disk Objective-C property table. +class ObjCContextInfoTableInfo + : public VersionedTableInfo { +public: + static internal_key_type ReadKey(const uint8_t *Data, unsigned Length) { + return endian::readNext( + Data); + } + + hash_value_type ComputeHash(internal_key_type Key) { + return static_cast(llvm::hash_value(Key)); + } + + static ObjCContextInfo readUnversioned(internal_key_type Key, + const uint8_t *&Data) { + ObjCContextInfo Info; + ReadCommonTypeInfo(Data, Info); + uint8_t Payload = *Data++; + + if (Payload & 0x01) + Info.setHasDesignatedInits(true); + Payload = Payload >> 1; + + if (Payload & 0x4) + Info.setDefaultNullability(static_cast(Payload & 0x03)); + Payload >>= 3; + + if (Payload & (1 << 1)) + Info.setSwiftObjCMembers(Payload & 1); + Payload >>= 2; + + if (Payload & (1 << 1)) + Info.setSwiftImportAsNonGeneric(Payload & 1); + + return Info; + } +}; + +/// Read serialized VariableInfo. +void ReadVariableInfo(const uint8_t *&Data, VariableInfo &Info) { + ReadCommonEntityInfo(Data, Info); + if (*Data++) { + Info.setNullabilityAudited(static_cast(*Data)); + } + ++Data; + + auto TypeLen = + endian::readNext(Data); + Info.setType(std::string(Data, Data + TypeLen)); + Data += TypeLen; +} + +/// Used to deserialize the on-disk Objective-C property table. +class ObjCPropertyTableInfo + : public VersionedTableInfo, + ObjCPropertyInfo> { +public: + static internal_key_type ReadKey(const uint8_t *Data, unsigned Length) { + auto ClassID = + endian::readNext(Data); + auto NameID = + endian::readNext(Data); + char IsInstance = + endian::readNext(Data); + return {ClassID, NameID, IsInstance}; + } + + hash_value_type ComputeHash(internal_key_type Key) { + return static_cast(llvm::hash_value(Key)); + } + + static ObjCPropertyInfo readUnversioned(internal_key_type Key, + const uint8_t *&Data) { + ObjCPropertyInfo Info; + ReadVariableInfo(Data, Info); + uint8_t Flags = *Data++; + if (Flags & (1 << 0)) + Info.setSwiftImportAsAccessors(Flags & (1 << 1)); + return Info; + } +}; + +/// Read serialized ParamInfo. +void ReadParamInfo(const uint8_t *&Data, ParamInfo &Info) { + ReadVariableInfo(Data, Info); + + uint8_t Payload = + endian::readNext(Data); + if (auto RawConvention = Payload & 0x7) { + auto Convention = static_cast(RawConvention - 1); + Info.setRetainCountConvention(Convention); + } + Payload >>= 3; + if (Payload & 0x01) + Info.setNoEscape(Payload & 0x02); + Payload >>= 2; + assert(Payload == 0 && "Bad API notes"); +} + +/// Read serialized FunctionInfo. +void ReadFunctionInfo(const uint8_t *&Data, FunctionInfo &Info) { + ReadCommonEntityInfo(Data, Info); + + uint8_t Payload = + endian::readNext(Data); + if (auto RawConvention = Payload & 0x7) { + auto Convention = static_cast(RawConvention - 1); + Info.setRetainCountConvention(Convention); + } + Payload >>= 3; + Info.NullabilityAudited = Payload & 0x1; + Payload >>= 1; + assert(Payload == 0 && "Bad API notes"); + + Info.NumAdjustedNullable = + endian::readNext(Data); + Info.NullabilityPayload = + endian::readNext(Data); + + unsigned NumParams = + endian::readNext(Data); + while (NumParams > 0) { + ParamInfo pi; + ReadParamInfo(Data, pi); + Info.Params.push_back(pi); + --NumParams; + } + + unsigned ResultTypeLen = + endian::readNext(Data); + Info.ResultType = std::string(Data, Data + ResultTypeLen); + Data += ResultTypeLen; +} + +/// Used to deserialize the on-disk Objective-C method table. +class ObjCMethodTableInfo + : public VersionedTableInfo, + ObjCMethodInfo> { +public: + static internal_key_type ReadKey(const uint8_t *Data, unsigned Length) { + auto ClassID = + endian::readNext(Data); + auto SelectorID = + endian::readNext(Data); + auto IsInstance = + endian::readNext(Data); + return {ClassID, SelectorID, IsInstance}; + } + + hash_value_type ComputeHash(internal_key_type Key) { + return static_cast(llvm::hash_value(Key)); + } + + static ObjCMethodInfo readUnversioned(internal_key_type Key, + const uint8_t *&Data) { + ObjCMethodInfo Info; + uint8_t Payload = *Data++; + Info.RequiredInit = Payload & 0x01; + Payload >>= 1; + Info.DesignatedInit = Payload & 0x01; + Payload >>= 1; + + ReadFunctionInfo(Data, Info); + return Info; + } +}; + +/// Used to deserialize the on-disk Objective-C selector table. +class ObjCSelectorTableInfo { +public: + using internal_key_type = StoredObjCSelector; + using external_key_type = internal_key_type; + using data_type = SelectorID; + using hash_value_type = unsigned; + using offset_type = unsigned; + + internal_key_type GetInternalKey(external_key_type Key) { return Key; } + + external_key_type GetExternalKey(internal_key_type Key) { return Key; } + + hash_value_type ComputeHash(internal_key_type Key) { + return llvm::DenseMapInfo::getHashValue(Key); + } + + static bool EqualKey(internal_key_type LHS, internal_key_type RHS) { + return llvm::DenseMapInfo::isEqual(LHS, RHS); + } + + static std::pair ReadKeyDataLength(const uint8_t *&Data) { + unsigned KeyLength = + endian::readNext(Data); + unsigned DataLength = + endian::readNext(Data); + return {KeyLength, DataLength}; + } + + static internal_key_type ReadKey(const uint8_t *Data, unsigned Length) { + internal_key_type Key; + Key.NumPieces = + endian::readNext(Data); + unsigned NumIdents = (Length - sizeof(uint16_t)) / sizeof(uint32_t); + for (unsigned i = 0; i != NumIdents; ++i) { + Key.Identifiers.push_back( + endian::readNext( + Data)); + } + return Key; + } + + static data_type ReadData(internal_key_type Key, const uint8_t *Data, + unsigned Length) { + return endian::readNext( + Data); + } +}; + +/// Used to deserialize the on-disk global variable table. +class GlobalVariableTableInfo + : public VersionedTableInfo { +public: + static internal_key_type ReadKey(const uint8_t *Data, unsigned Length) { + auto CtxID = + endian::readNext(Data); + auto ContextKind = + endian::readNext(Data); + auto NameID = + endian::readNext(Data); + return {CtxID, ContextKind, NameID}; + } + + hash_value_type ComputeHash(internal_key_type Key) { + return static_cast(Key.hashValue()); + } + + static GlobalVariableInfo readUnversioned(internal_key_type Key, + const uint8_t *&Data) { + GlobalVariableInfo Info; + ReadVariableInfo(Data, Info); + return Info; + } +}; + +/// Used to deserialize the on-disk global function table. +class GlobalFunctionTableInfo + : public VersionedTableInfo { +public: + static internal_key_type ReadKey(const uint8_t *Data, unsigned Length) { + auto CtxID = + endian::readNext(Data); + auto ContextKind = + endian::readNext(Data); + auto NameID = + endian::readNext(Data); + return {CtxID, ContextKind, NameID}; + } + + hash_value_type ComputeHash(internal_key_type Key) { + return static_cast(Key.hashValue()); + } + + static GlobalFunctionInfo readUnversioned(internal_key_type Key, + const uint8_t *&Data) { + GlobalFunctionInfo Info; + ReadFunctionInfo(Data, Info); + return Info; + } +}; + +/// Used to deserialize the on-disk enumerator table. +class EnumConstantTableInfo + : public VersionedTableInfo { +public: + static internal_key_type ReadKey(const uint8_t *Data, unsigned Length) { + auto NameID = + endian::readNext(Data); + return NameID; + } + + hash_value_type ComputeHash(internal_key_type Key) { + return static_cast(llvm::hash_value(Key)); + } + + static EnumConstantInfo readUnversioned(internal_key_type Key, + const uint8_t *&Data) { + EnumConstantInfo Info; + ReadCommonEntityInfo(Data, Info); + return Info; + } +}; + +/// Used to deserialize the on-disk tag table. +class TagTableInfo + : public VersionedTableInfo { +public: + static internal_key_type ReadKey(const uint8_t *Data, unsigned Length) { + auto CtxID = + endian::readNext(Data); + auto ContextKind = + endian::readNext(Data); + auto NameID = + endian::readNext( + Data); + return {CtxID, ContextKind, NameID}; + } + + hash_value_type ComputeHash(internal_key_type Key) { + return static_cast(Key.hashValue()); + } + + static TagInfo readUnversioned(internal_key_type Key, const uint8_t *&Data) { + TagInfo Info; + + uint8_t Payload = *Data++; + if (Payload & 1) + Info.setFlagEnum(Payload & 2); + Payload >>= 2; + if (Payload > 0) + Info.EnumExtensibility = + static_cast((Payload & 0x3) - 1); + + unsigned ImportAsLength = + endian::readNext(Data); + if (ImportAsLength > 0) { + Info.SwiftImportAs = + std::string(reinterpret_cast(Data), ImportAsLength - 1); + Data += ImportAsLength - 1; + } + unsigned RetainOpLength = + endian::readNext(Data); + if (RetainOpLength > 0) { + Info.SwiftRetainOp = + std::string(reinterpret_cast(Data), RetainOpLength - 1); + Data += RetainOpLength - 1; + } + unsigned ReleaseOpLength = + endian::readNext(Data); + if (ReleaseOpLength > 0) { + Info.SwiftReleaseOp = std::string(reinterpret_cast(Data), + ReleaseOpLength - 1); + Data += ReleaseOpLength - 1; + } + + ReadCommonTypeInfo(Data, Info); + return Info; + } +}; + +/// Used to deserialize the on-disk typedef table. +class TypedefTableInfo + : public VersionedTableInfo { +public: + static internal_key_type ReadKey(const uint8_t *Data, unsigned Length) { + auto CtxID = + endian::readNext(Data); + auto ContextKind = + endian::readNext(Data); + auto nameID = + endian::readNext( + Data); + return {CtxID, ContextKind, nameID}; + } + + hash_value_type ComputeHash(internal_key_type Key) { + return static_cast(Key.hashValue()); + } + + static TypedefInfo readUnversioned(internal_key_type Key, + const uint8_t *&Data) { + TypedefInfo Info; + + uint8_t Payload = *Data++; + if (Payload > 0) + Info.SwiftWrapper = static_cast((Payload & 0x3) - 1); + + ReadCommonTypeInfo(Data, Info); + return Info; + } +}; +} // end anonymous namespace + +class APINotesReader::Implementation { +public: + /// The input buffer for the API notes data. + llvm::MemoryBuffer *InputBuffer; + + /// The Swift version to use for filtering. + llvm::VersionTuple SwiftVersion; + + /// The name of the module that we read from the control block. + std::string ModuleName; + + // The size and modification time of the source file from + // which this API notes file was created, if known. + std::optional> SourceFileSizeAndModTime; + + using SerializedIdentifierTable = + llvm::OnDiskIterableChainedHashTable; + + /// The identifier table. + std::unique_ptr IdentifierTable; + + using SerializedObjCContextIDTable = + llvm::OnDiskIterableChainedHashTable; + + /// The Objective-C context ID table. + std::unique_ptr ObjCContextIDTable; + + using SerializedObjCContextInfoTable = + llvm::OnDiskIterableChainedHashTable; + + /// The Objective-C context info table. + std::unique_ptr ObjCContextInfoTable; + + using SerializedObjCPropertyTable = + llvm::OnDiskIterableChainedHashTable; + + /// The Objective-C property table. + std::unique_ptr ObjCPropertyTable; + + using SerializedObjCMethodTable = + llvm::OnDiskIterableChainedHashTable; + + /// The Objective-C method table. + std::unique_ptr ObjCMethodTable; + + using SerializedObjCSelectorTable = + llvm::OnDiskIterableChainedHashTable; + + /// The Objective-C selector table. + std::unique_ptr ObjCSelectorTable; + + using SerializedGlobalVariableTable = + llvm::OnDiskIterableChainedHashTable; + + /// The global variable table. + std::unique_ptr GlobalVariableTable; + + using SerializedGlobalFunctionTable = + llvm::OnDiskIterableChainedHashTable; + + /// The global function table. + std::unique_ptr GlobalFunctionTable; + + using SerializedEnumConstantTable = + llvm::OnDiskIterableChainedHashTable; + + /// The enumerator table. + std::unique_ptr EnumConstantTable; + + using SerializedTagTable = llvm::OnDiskIterableChainedHashTable; + + /// The tag table. + std::unique_ptr TagTable; + + using SerializedTypedefTable = + llvm::OnDiskIterableChainedHashTable; + + /// The typedef table. + std::unique_ptr TypedefTable; + + /// Retrieve the identifier ID for the given string, or an empty + /// optional if the string is unknown. + std::optional getIdentifier(llvm::StringRef Str); + + /// Retrieve the selector ID for the given selector, or an empty + /// optional if the string is unknown. + std::optional getSelector(ObjCSelectorRef Selector); + + bool readControlBlock(llvm::BitstreamCursor &Cursor, + llvm::SmallVectorImpl &Scratch); + bool readIdentifierBlock(llvm::BitstreamCursor &Cursor, + llvm::SmallVectorImpl &Scratch); + bool readObjCContextBlock(llvm::BitstreamCursor &Cursor, + llvm::SmallVectorImpl &Scratch); + bool readObjCPropertyBlock(llvm::BitstreamCursor &Cursor, + llvm::SmallVectorImpl &Scratch); + bool readObjCMethodBlock(llvm::BitstreamCursor &Cursor, + llvm::SmallVectorImpl &Scratch); + bool readObjCSelectorBlock(llvm::BitstreamCursor &Cursor, + llvm::SmallVectorImpl &Scratch); + bool readGlobalVariableBlock(llvm::BitstreamCursor &Cursor, + llvm::SmallVectorImpl &Scratch); + bool readGlobalFunctionBlock(llvm::BitstreamCursor &Cursor, + llvm::SmallVectorImpl &Scratch); + bool readEnumConstantBlock(llvm::BitstreamCursor &Cursor, + llvm::SmallVectorImpl &Scratch); + bool readTagBlock(llvm::BitstreamCursor &Cursor, + llvm::SmallVectorImpl &Scratch); + bool readTypedefBlock(llvm::BitstreamCursor &Cursor, + llvm::SmallVectorImpl &Scratch); +}; + +std::optional +APINotesReader::Implementation::getIdentifier(llvm::StringRef Str) { + if (!IdentifierTable) + return std::nullopt; + + if (Str.empty()) + return IdentifierID(0); + + auto Known = IdentifierTable->find(Str); + if (Known == IdentifierTable->end()) + return std::nullopt; + + return *Known; +} + +std::optional +APINotesReader::Implementation::getSelector(ObjCSelectorRef Selector) { + if (!ObjCSelectorTable || !IdentifierTable) + return std::nullopt; + + // Translate the identifiers. + StoredObjCSelector Key; + for (auto Ident : Selector.Identifiers) { + if (auto IdentID = getIdentifier(Ident)) { + Key.Identifiers.push_back(*IdentID); + } else { + return std::nullopt; + } + } + + auto Known = ObjCSelectorTable->find(Key); + if (Known == ObjCSelectorTable->end()) + return std::nullopt; + + return *Known; +} + +bool APINotesReader::Implementation::readControlBlock( + llvm::BitstreamCursor &Cursor, llvm::SmallVectorImpl &Scratch) { + if (Cursor.EnterSubBlock(CONTROL_BLOCK_ID)) + return true; + + bool SawMetadata = false; + + llvm::Expected MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + llvm::BitstreamEntry Next = MaybeNext.get(); + + while (Next.Kind != llvm::BitstreamEntry::EndBlock) { + if (Next.Kind == llvm::BitstreamEntry::Error) + return true; + + if (Next.Kind == llvm::BitstreamEntry::SubBlock) { + // Unknown metadata sub-block, possibly for use by a future version of the + // API notes format. + if (Cursor.SkipBlock()) + return true; + + MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + Next = MaybeNext.get(); + continue; + } + + Scratch.clear(); + llvm::StringRef BlobData; + llvm::Expected MaybeKind = + Cursor.readRecord(Next.ID, Scratch, &BlobData); + if (!MaybeKind) { + // FIXME this drops the error on the floor. + consumeError(MaybeKind.takeError()); + return false; + } + unsigned Kind = MaybeKind.get(); + + switch (Kind) { + case control_block::METADATA: + // Already saw metadata. + if (SawMetadata) + return true; + + if (Scratch[0] != VERSION_MAJOR || Scratch[1] != VERSION_MINOR) + return true; + + SawMetadata = true; + break; + + case control_block::MODULE_NAME: + ModuleName = BlobData.str(); + break; + + case control_block::MODULE_OPTIONS: + break; + + case control_block::SOURCE_FILE: + SourceFileSizeAndModTime = {Scratch[0], Scratch[1]}; + break; + + default: + // Unknown metadata record, possibly for use by a future version of the + // module format. + break; + } + + MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + Next = MaybeNext.get(); + } + + return !SawMetadata; +} + +bool APINotesReader::Implementation::readIdentifierBlock( + llvm::BitstreamCursor &Cursor, llvm::SmallVectorImpl &Scratch) { + if (Cursor.EnterSubBlock(IDENTIFIER_BLOCK_ID)) + return true; + + llvm::Expected MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + llvm::BitstreamEntry Next = MaybeNext.get(); + + while (Next.Kind != llvm::BitstreamEntry::EndBlock) { + if (Next.Kind == llvm::BitstreamEntry::Error) + return true; + + if (Next.Kind == llvm::BitstreamEntry::SubBlock) { + // Unknown sub-block, possibly for use by a future version of the + // API notes format. + if (Cursor.SkipBlock()) + return true; + + MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + Next = MaybeNext.get(); + continue; + } + + Scratch.clear(); + llvm::StringRef BlobData; + llvm::Expected MaybeKind = + Cursor.readRecord(Next.ID, Scratch, &BlobData); + if (!MaybeKind) { + // FIXME this drops the error on the floor. + consumeError(MaybeKind.takeError()); + return false; + } + unsigned Kind = MaybeKind.get(); + switch (Kind) { + case identifier_block::IDENTIFIER_DATA: { + // Already saw identifier table. + if (IdentifierTable) + return true; + + uint32_t tableOffset; + identifier_block::IdentifierDataLayout::readRecord(Scratch, tableOffset); + auto base = reinterpret_cast(BlobData.data()); + + IdentifierTable.reset(SerializedIdentifierTable::Create( + base + tableOffset, base + sizeof(uint32_t), base)); + break; + } + + default: + // Unknown record, possibly for use by a future version of the + // module format. + break; + } + + MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + Next = MaybeNext.get(); + } + + return false; +} + +bool APINotesReader::Implementation::readObjCContextBlock( + llvm::BitstreamCursor &Cursor, llvm::SmallVectorImpl &Scratch) { + if (Cursor.EnterSubBlock(OBJC_CONTEXT_BLOCK_ID)) + return true; + + llvm::Expected MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + llvm::BitstreamEntry Next = MaybeNext.get(); + + while (Next.Kind != llvm::BitstreamEntry::EndBlock) { + if (Next.Kind == llvm::BitstreamEntry::Error) + return true; + + if (Next.Kind == llvm::BitstreamEntry::SubBlock) { + // Unknown sub-block, possibly for use by a future version of the + // API notes format. + if (Cursor.SkipBlock()) + return true; + + MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + Next = MaybeNext.get(); + continue; + } + + Scratch.clear(); + llvm::StringRef BlobData; + llvm::Expected MaybeKind = + Cursor.readRecord(Next.ID, Scratch, &BlobData); + if (!MaybeKind) { + // FIXME this drops the error on the floor. + consumeError(MaybeKind.takeError()); + return false; + } + unsigned Kind = MaybeKind.get(); + switch (Kind) { + case objc_context_block::OBJC_CONTEXT_ID_DATA: { + // Already saw Objective-C context ID table. + if (ObjCContextIDTable) + return true; + + uint32_t tableOffset; + objc_context_block::ObjCContextIDLayout::readRecord(Scratch, tableOffset); + auto base = reinterpret_cast(BlobData.data()); + + ObjCContextIDTable.reset(SerializedObjCContextIDTable::Create( + base + tableOffset, base + sizeof(uint32_t), base)); + break; + } + + case objc_context_block::OBJC_CONTEXT_INFO_DATA: { + // Already saw Objective-C context info table. + if (ObjCContextInfoTable) + return true; + + uint32_t tableOffset; + objc_context_block::ObjCContextInfoLayout::readRecord(Scratch, + tableOffset); + auto base = reinterpret_cast(BlobData.data()); + + ObjCContextInfoTable.reset(SerializedObjCContextInfoTable::Create( + base + tableOffset, base + sizeof(uint32_t), base)); + break; + } + + default: + // Unknown record, possibly for use by a future version of the + // module format. + break; + } + + MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + Next = MaybeNext.get(); + } + + return false; +} + +bool APINotesReader::Implementation::readObjCPropertyBlock( + llvm::BitstreamCursor &Cursor, llvm::SmallVectorImpl &Scratch) { + if (Cursor.EnterSubBlock(OBJC_PROPERTY_BLOCK_ID)) + return true; + + llvm::Expected MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + llvm::BitstreamEntry Next = MaybeNext.get(); + + while (Next.Kind != llvm::BitstreamEntry::EndBlock) { + if (Next.Kind == llvm::BitstreamEntry::Error) + return true; + + if (Next.Kind == llvm::BitstreamEntry::SubBlock) { + // Unknown sub-block, possibly for use by a future version of the + // API notes format. + if (Cursor.SkipBlock()) + return true; + + MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + Next = MaybeNext.get(); + continue; + } + + Scratch.clear(); + llvm::StringRef BlobData; + llvm::Expected MaybeKind = + Cursor.readRecord(Next.ID, Scratch, &BlobData); + if (!MaybeKind) { + // FIXME this drops the error on the floor. + consumeError(MaybeKind.takeError()); + return false; + } + unsigned Kind = MaybeKind.get(); + switch (Kind) { + case objc_property_block::OBJC_PROPERTY_DATA: { + // Already saw Objective-C property table. + if (ObjCPropertyTable) + return true; + + uint32_t tableOffset; + objc_property_block::ObjCPropertyDataLayout::readRecord(Scratch, + tableOffset); + auto base = reinterpret_cast(BlobData.data()); + + ObjCPropertyTable.reset(SerializedObjCPropertyTable::Create( + base + tableOffset, base + sizeof(uint32_t), base)); + break; + } + + default: + // Unknown record, possibly for use by a future version of the + // module format. + break; + } + + MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + Next = MaybeNext.get(); + } + + return false; +} + +bool APINotesReader::Implementation::readObjCMethodBlock( + llvm::BitstreamCursor &Cursor, llvm::SmallVectorImpl &Scratch) { + if (Cursor.EnterSubBlock(OBJC_METHOD_BLOCK_ID)) + return true; + + llvm::Expected MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + llvm::BitstreamEntry Next = MaybeNext.get(); + while (Next.Kind != llvm::BitstreamEntry::EndBlock) { + if (Next.Kind == llvm::BitstreamEntry::Error) + return true; + + if (Next.Kind == llvm::BitstreamEntry::SubBlock) { + // Unknown sub-block, possibly for use by a future version of the + // API notes format. + if (Cursor.SkipBlock()) + return true; + + MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + Next = MaybeNext.get(); + continue; + } + + Scratch.clear(); + llvm::StringRef BlobData; + llvm::Expected MaybeKind = + Cursor.readRecord(Next.ID, Scratch, &BlobData); + if (!MaybeKind) { + // FIXME this drops the error on the floor. + consumeError(MaybeKind.takeError()); + return false; + } + unsigned Kind = MaybeKind.get(); + switch (Kind) { + case objc_method_block::OBJC_METHOD_DATA: { + // Already saw Objective-C method table. + if (ObjCMethodTable) + return true; + + uint32_t tableOffset; + objc_method_block::ObjCMethodDataLayout::readRecord(Scratch, tableOffset); + auto base = reinterpret_cast(BlobData.data()); + + ObjCMethodTable.reset(SerializedObjCMethodTable::Create( + base + tableOffset, base + sizeof(uint32_t), base)); + break; + } + + default: + // Unknown record, possibly for use by a future version of the + // module format. + break; + } + + MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + Next = MaybeNext.get(); + } + + return false; +} + +bool APINotesReader::Implementation::readObjCSelectorBlock( + llvm::BitstreamCursor &Cursor, llvm::SmallVectorImpl &Scratch) { + if (Cursor.EnterSubBlock(OBJC_SELECTOR_BLOCK_ID)) + return true; + + llvm::Expected MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + llvm::BitstreamEntry Next = MaybeNext.get(); + while (Next.Kind != llvm::BitstreamEntry::EndBlock) { + if (Next.Kind == llvm::BitstreamEntry::Error) + return true; + + if (Next.Kind == llvm::BitstreamEntry::SubBlock) { + // Unknown sub-block, possibly for use by a future version of the + // API notes format. + if (Cursor.SkipBlock()) + return true; + + MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + Next = MaybeNext.get(); + continue; + } + + Scratch.clear(); + llvm::StringRef BlobData; + llvm::Expected MaybeKind = + Cursor.readRecord(Next.ID, Scratch, &BlobData); + if (!MaybeKind) { + // FIXME this drops the error on the floor. + consumeError(MaybeKind.takeError()); + return false; + } + unsigned Kind = MaybeKind.get(); + switch (Kind) { + case objc_selector_block::OBJC_SELECTOR_DATA: { + // Already saw Objective-C selector table. + if (ObjCSelectorTable) + return true; + + uint32_t tableOffset; + objc_selector_block::ObjCSelectorDataLayout::readRecord(Scratch, + tableOffset); + auto base = reinterpret_cast(BlobData.data()); + + ObjCSelectorTable.reset(SerializedObjCSelectorTable::Create( + base + tableOffset, base + sizeof(uint32_t), base)); + break; + } + + default: + // Unknown record, possibly for use by a future version of the + // module format. + break; + } + + MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + Next = MaybeNext.get(); + } + + return false; +} + +bool APINotesReader::Implementation::readGlobalVariableBlock( + llvm::BitstreamCursor &Cursor, llvm::SmallVectorImpl &Scratch) { + if (Cursor.EnterSubBlock(GLOBAL_VARIABLE_BLOCK_ID)) + return true; + + llvm::Expected MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + llvm::BitstreamEntry Next = MaybeNext.get(); + while (Next.Kind != llvm::BitstreamEntry::EndBlock) { + if (Next.Kind == llvm::BitstreamEntry::Error) + return true; + + if (Next.Kind == llvm::BitstreamEntry::SubBlock) { + // Unknown sub-block, possibly for use by a future version of the + // API notes format. + if (Cursor.SkipBlock()) + return true; + + MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + Next = MaybeNext.get(); + continue; + } + + Scratch.clear(); + llvm::StringRef BlobData; + llvm::Expected MaybeKind = + Cursor.readRecord(Next.ID, Scratch, &BlobData); + if (!MaybeKind) { + // FIXME this drops the error on the floor. + consumeError(MaybeKind.takeError()); + return false; + } + unsigned Kind = MaybeKind.get(); + switch (Kind) { + case global_variable_block::GLOBAL_VARIABLE_DATA: { + // Already saw global variable table. + if (GlobalVariableTable) + return true; + + uint32_t tableOffset; + global_variable_block::GlobalVariableDataLayout::readRecord(Scratch, + tableOffset); + auto base = reinterpret_cast(BlobData.data()); + + GlobalVariableTable.reset(SerializedGlobalVariableTable::Create( + base + tableOffset, base + sizeof(uint32_t), base)); + break; + } + + default: + // Unknown record, possibly for use by a future version of the + // module format. + break; + } + + MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + Next = MaybeNext.get(); + } + + return false; +} + +bool APINotesReader::Implementation::readGlobalFunctionBlock( + llvm::BitstreamCursor &Cursor, llvm::SmallVectorImpl &Scratch) { + if (Cursor.EnterSubBlock(GLOBAL_FUNCTION_BLOCK_ID)) + return true; + + llvm::Expected MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + llvm::BitstreamEntry Next = MaybeNext.get(); + while (Next.Kind != llvm::BitstreamEntry::EndBlock) { + if (Next.Kind == llvm::BitstreamEntry::Error) + return true; + + if (Next.Kind == llvm::BitstreamEntry::SubBlock) { + // Unknown sub-block, possibly for use by a future version of the + // API notes format. + if (Cursor.SkipBlock()) + return true; + + MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + Next = MaybeNext.get(); + continue; + } + + Scratch.clear(); + llvm::StringRef BlobData; + llvm::Expected MaybeKind = + Cursor.readRecord(Next.ID, Scratch, &BlobData); + if (!MaybeKind) { + // FIXME this drops the error on the floor. + consumeError(MaybeKind.takeError()); + return false; + } + unsigned Kind = MaybeKind.get(); + switch (Kind) { + case global_function_block::GLOBAL_FUNCTION_DATA: { + // Already saw global function table. + if (GlobalFunctionTable) + return true; + + uint32_t tableOffset; + global_function_block::GlobalFunctionDataLayout::readRecord(Scratch, + tableOffset); + auto base = reinterpret_cast(BlobData.data()); + + GlobalFunctionTable.reset(SerializedGlobalFunctionTable::Create( + base + tableOffset, base + sizeof(uint32_t), base)); + break; + } + + default: + // Unknown record, possibly for use by a future version of the + // module format. + break; + } + + MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + Next = MaybeNext.get(); + } + + return false; +} + +bool APINotesReader::Implementation::readEnumConstantBlock( + llvm::BitstreamCursor &Cursor, llvm::SmallVectorImpl &Scratch) { + if (Cursor.EnterSubBlock(ENUM_CONSTANT_BLOCK_ID)) + return true; + + llvm::Expected MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + llvm::BitstreamEntry Next = MaybeNext.get(); + while (Next.Kind != llvm::BitstreamEntry::EndBlock) { + if (Next.Kind == llvm::BitstreamEntry::Error) + return true; + + if (Next.Kind == llvm::BitstreamEntry::SubBlock) { + // Unknown sub-block, possibly for use by a future version of the + // API notes format. + if (Cursor.SkipBlock()) + return true; + + MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + Next = MaybeNext.get(); + continue; + } + + Scratch.clear(); + llvm::StringRef BlobData; + llvm::Expected MaybeKind = + Cursor.readRecord(Next.ID, Scratch, &BlobData); + if (!MaybeKind) { + // FIXME this drops the error on the floor. + consumeError(MaybeKind.takeError()); + return false; + } + unsigned Kind = MaybeKind.get(); + switch (Kind) { + case enum_constant_block::ENUM_CONSTANT_DATA: { + // Already saw enumerator table. + if (EnumConstantTable) + return true; + + uint32_t tableOffset; + enum_constant_block::EnumConstantDataLayout::readRecord(Scratch, + tableOffset); + auto base = reinterpret_cast(BlobData.data()); + + EnumConstantTable.reset(SerializedEnumConstantTable::Create( + base + tableOffset, base + sizeof(uint32_t), base)); + break; + } + + default: + // Unknown record, possibly for use by a future version of the + // module format. + break; + } + + MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + Next = MaybeNext.get(); + } + + return false; +} + +bool APINotesReader::Implementation::readTagBlock( + llvm::BitstreamCursor &Cursor, llvm::SmallVectorImpl &Scratch) { + if (Cursor.EnterSubBlock(TAG_BLOCK_ID)) + return true; + + llvm::Expected MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + llvm::BitstreamEntry Next = MaybeNext.get(); + while (Next.Kind != llvm::BitstreamEntry::EndBlock) { + if (Next.Kind == llvm::BitstreamEntry::Error) + return true; + + if (Next.Kind == llvm::BitstreamEntry::SubBlock) { + // Unknown sub-block, possibly for use by a future version of the + // API notes format. + if (Cursor.SkipBlock()) + return true; + + MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + Next = MaybeNext.get(); + continue; + } + + Scratch.clear(); + llvm::StringRef BlobData; + llvm::Expected MaybeKind = + Cursor.readRecord(Next.ID, Scratch, &BlobData); + if (!MaybeKind) { + // FIXME this drops the error on the floor. + consumeError(MaybeKind.takeError()); + return false; + } + unsigned Kind = MaybeKind.get(); + switch (Kind) { + case tag_block::TAG_DATA: { + // Already saw tag table. + if (TagTable) + return true; + + uint32_t tableOffset; + tag_block::TagDataLayout::readRecord(Scratch, tableOffset); + auto base = reinterpret_cast(BlobData.data()); + + TagTable.reset(SerializedTagTable::Create(base + tableOffset, + base + sizeof(uint32_t), base)); + break; + } + + default: + // Unknown record, possibly for use by a future version of the + // module format. + break; + } + + MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + Next = MaybeNext.get(); + } + + return false; +} + +bool APINotesReader::Implementation::readTypedefBlock( + llvm::BitstreamCursor &Cursor, llvm::SmallVectorImpl &Scratch) { + if (Cursor.EnterSubBlock(TYPEDEF_BLOCK_ID)) + return true; + + llvm::Expected MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + llvm::BitstreamEntry Next = MaybeNext.get(); + while (Next.Kind != llvm::BitstreamEntry::EndBlock) { + if (Next.Kind == llvm::BitstreamEntry::Error) + return true; + + if (Next.Kind == llvm::BitstreamEntry::SubBlock) { + // Unknown sub-block, possibly for use by a future version of the + // API notes format. + if (Cursor.SkipBlock()) + return true; + + MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + Next = MaybeNext.get(); + continue; + } + + Scratch.clear(); + llvm::StringRef BlobData; + llvm::Expected MaybeKind = + Cursor.readRecord(Next.ID, Scratch, &BlobData); + if (!MaybeKind) { + // FIXME this drops the error on the floor. + consumeError(MaybeKind.takeError()); + return false; + } + unsigned Kind = MaybeKind.get(); + switch (Kind) { + case typedef_block::TYPEDEF_DATA: { + // Already saw typedef table. + if (TypedefTable) + return true; + + uint32_t tableOffset; + typedef_block::TypedefDataLayout::readRecord(Scratch, tableOffset); + auto base = reinterpret_cast(BlobData.data()); + + TypedefTable.reset(SerializedTypedefTable::Create( + base + tableOffset, base + sizeof(uint32_t), base)); + break; + } + + default: + // Unknown record, possibly for use by a future version of the + // module format. + break; + } + + MaybeNext = Cursor.advance(); + if (!MaybeNext) { + // FIXME this drops the error on the floor. + consumeError(MaybeNext.takeError()); + return false; + } + Next = MaybeNext.get(); + } + + return false; +} + +APINotesReader::APINotesReader(llvm::MemoryBuffer *InputBuffer, + llvm::VersionTuple SwiftVersion, bool &Failed) + : Implementation(new class Implementation) { + Failed = false; + + // Initialize the input buffer. + Implementation->InputBuffer = InputBuffer; + Implementation->SwiftVersion = SwiftVersion; + llvm::BitstreamCursor Cursor(*Implementation->InputBuffer); + + // Validate signature. + for (auto byte : API_NOTES_SIGNATURE) { + if (Cursor.AtEndOfStream()) { + Failed = true; + return; + } + if (llvm::Expected maybeRead = + Cursor.Read(8)) { + if (maybeRead.get() != byte) { + Failed = true; + return; + } + } else { + // FIXME this drops the error on the floor. + consumeError(maybeRead.takeError()); + Failed = true; + return; + } + } + + // Look at all of the blocks. + bool HasValidControlBlock = false; + llvm::SmallVector Scratch; + while (!Cursor.AtEndOfStream()) { + llvm::Expected MaybeTopLevelEntry = Cursor.advance(); + if (!MaybeTopLevelEntry) { + // FIXME this drops the error on the floor. + consumeError(MaybeTopLevelEntry.takeError()); + Failed = true; + return; + } + llvm::BitstreamEntry TopLevelEntry = MaybeTopLevelEntry.get(); + + if (TopLevelEntry.Kind != llvm::BitstreamEntry::SubBlock) + break; + + switch (TopLevelEntry.ID) { + case llvm::bitc::BLOCKINFO_BLOCK_ID: + if (!Cursor.ReadBlockInfoBlock()) { + Failed = true; + break; + } + break; + + case CONTROL_BLOCK_ID: + // Only allow a single control block. + if (HasValidControlBlock || + Implementation->readControlBlock(Cursor, Scratch)) { + Failed = true; + return; + } + + HasValidControlBlock = true; + break; + + case IDENTIFIER_BLOCK_ID: + if (!HasValidControlBlock || + Implementation->readIdentifierBlock(Cursor, Scratch)) { + Failed = true; + return; + } + break; + + case OBJC_CONTEXT_BLOCK_ID: + if (!HasValidControlBlock || + Implementation->readObjCContextBlock(Cursor, Scratch)) { + Failed = true; + return; + } + + break; + + case OBJC_PROPERTY_BLOCK_ID: + if (!HasValidControlBlock || + Implementation->readObjCPropertyBlock(Cursor, Scratch)) { + Failed = true; + return; + } + break; + + case OBJC_METHOD_BLOCK_ID: + if (!HasValidControlBlock || + Implementation->readObjCMethodBlock(Cursor, Scratch)) { + Failed = true; + return; + } + break; + + case OBJC_SELECTOR_BLOCK_ID: + if (!HasValidControlBlock || + Implementation->readObjCSelectorBlock(Cursor, Scratch)) { + Failed = true; + return; + } + break; + + case GLOBAL_VARIABLE_BLOCK_ID: + if (!HasValidControlBlock || + Implementation->readGlobalVariableBlock(Cursor, Scratch)) { + Failed = true; + return; + } + break; + + case GLOBAL_FUNCTION_BLOCK_ID: + if (!HasValidControlBlock || + Implementation->readGlobalFunctionBlock(Cursor, Scratch)) { + Failed = true; + return; + } + break; + + case ENUM_CONSTANT_BLOCK_ID: + if (!HasValidControlBlock || + Implementation->readEnumConstantBlock(Cursor, Scratch)) { + Failed = true; + return; + } + break; + + case TAG_BLOCK_ID: + if (!HasValidControlBlock || + Implementation->readTagBlock(Cursor, Scratch)) { + Failed = true; + return; + } + break; + + case TYPEDEF_BLOCK_ID: + if (!HasValidControlBlock || + Implementation->readTypedefBlock(Cursor, Scratch)) { + Failed = true; + return; + } + break; + + default: + // Unknown top-level block, possibly for use by a future version of the + // module format. + if (Cursor.SkipBlock()) { + Failed = true; + return; + } + break; + } + } + + if (!Cursor.AtEndOfStream()) { + Failed = true; + return; + } +} + +APINotesReader::~APINotesReader() { delete Implementation->InputBuffer; } + +std::unique_ptr +APINotesReader::Create(std::unique_ptr InputBuffer, + llvm::VersionTuple SwiftVersion) { + bool Failed = false; + std::unique_ptr Reader( + new APINotesReader(InputBuffer.release(), SwiftVersion, Failed)); + if (Failed) + return nullptr; + + return Reader; +} + +template +APINotesReader::VersionedInfo::VersionedInfo( + llvm::VersionTuple Version, + llvm::SmallVector, 1> Results) + : Results(std::move(Results)) { + + assert(!Results.empty()); + assert(std::is_sorted( + Results.begin(), Results.end(), + [](const std::pair &left, + const std::pair &right) -> bool { + assert(left.first != right.first && "two entries for the same version"); + return left.first < right.first; + })); + + Selected = std::nullopt; + for (unsigned i = 0, n = Results.size(); i != n; ++i) { + if (!Version.empty() && Results[i].first >= Version) { + // If the current version is "4", then entries for 4 are better than + // entries for 5, but both are valid. Because entries are sorted, we get + // that behavior by picking the first match. + Selected = i; + break; + } + } + + // If we didn't find a match but we have an unversioned result, use the + // unversioned result. This will always be the first entry because we encode + // it as version 0. + if (!Selected && Results[0].first.empty()) + Selected = 0; +} + +auto APINotesReader::lookupObjCClassID(llvm::StringRef Name) + -> std::optional { + if (!Implementation->ObjCContextIDTable) + return std::nullopt; + + std::optional ClassID = Implementation->getIdentifier(Name); + if (!ClassID) + return std::nullopt; + + // ObjC classes can't be declared in C++ namespaces, so use -1 as the global + // context. + auto KnownID = Implementation->ObjCContextIDTable->find( + ContextTableKey(-1, (uint8_t)ContextKind::ObjCClass, *ClassID)); + if (KnownID == Implementation->ObjCContextIDTable->end()) + return std::nullopt; + + return ContextID(*KnownID); +} + +auto APINotesReader::lookupObjCClassInfo(llvm::StringRef Name) + -> VersionedInfo { + if (!Implementation->ObjCContextInfoTable) + return std::nullopt; + + std::optional CtxID = lookupObjCClassID(Name); + if (!CtxID) + return std::nullopt; + + auto KnownInfo = Implementation->ObjCContextInfoTable->find(CtxID->Value); + if (KnownInfo == Implementation->ObjCContextInfoTable->end()) + return std::nullopt; + + return {Implementation->SwiftVersion, *KnownInfo}; +} + +auto APINotesReader::lookupObjCProtocolID(llvm::StringRef Name) + -> std::optional { + if (!Implementation->ObjCContextIDTable) + return std::nullopt; + + std::optional classID = Implementation->getIdentifier(Name); + if (!classID) + return std::nullopt; + + // ObjC classes can't be declared in C++ namespaces, so use -1 as the global + // context. + auto KnownID = Implementation->ObjCContextIDTable->find( + ContextTableKey(-1, (uint8_t)ContextKind::ObjCProtocol, *classID)); + if (KnownID == Implementation->ObjCContextIDTable->end()) + return std::nullopt; + + return ContextID(*KnownID); +} + +auto APINotesReader::lookupObjCProtocolInfo(llvm::StringRef Name) + -> VersionedInfo { + if (!Implementation->ObjCContextInfoTable) + return std::nullopt; + + std::optional CtxID = lookupObjCProtocolID(Name); + if (!CtxID) + return std::nullopt; + + auto KnownInfo = Implementation->ObjCContextInfoTable->find(CtxID->Value); + if (KnownInfo == Implementation->ObjCContextInfoTable->end()) + return std::nullopt; + + return {Implementation->SwiftVersion, *KnownInfo}; +} + +auto APINotesReader::lookupObjCProperty(ContextID CtxID, llvm::StringRef Name, + bool IsInstance) + -> VersionedInfo { + if (!Implementation->ObjCPropertyTable) + return std::nullopt; + + std::optional PropertyID = Implementation->getIdentifier(Name); + if (!PropertyID) + return std::nullopt; + + auto Known = Implementation->ObjCPropertyTable->find( + std::make_tuple(CtxID.Value, *PropertyID, (char)IsInstance)); + if (Known == Implementation->ObjCPropertyTable->end()) + return std::nullopt; + + return {Implementation->SwiftVersion, *Known}; +} + +auto APINotesReader::lookupObjCMethod(ContextID CtxID, ObjCSelectorRef Selector, + bool IsInstanceMethod) + -> VersionedInfo { + if (!Implementation->ObjCMethodTable) + return std::nullopt; + + std::optional SelID = Implementation->getSelector(Selector); + if (!SelID) + return std::nullopt; + + auto Known = Implementation->ObjCMethodTable->find( + ObjCMethodTableInfo::internal_key_type{CtxID.Value, *SelID, + IsInstanceMethod}); + if (Known == Implementation->ObjCMethodTable->end()) + return std::nullopt; + + return {Implementation->SwiftVersion, *Known}; +} + +auto APINotesReader::lookupGlobalVariable(llvm::StringRef Name, + std::optional Ctx) + -> VersionedInfo { + if (!Implementation->GlobalVariableTable) + return std::nullopt; + + std::optional NameID = Implementation->getIdentifier(Name); + if (!NameID) + return std::nullopt; + + ContextTableKey Key(Ctx, *NameID); + + auto Known = Implementation->GlobalVariableTable->find(Key); + if (Known == Implementation->GlobalVariableTable->end()) + return std::nullopt; + + return {Implementation->SwiftVersion, *Known}; +} + +auto APINotesReader::lookupGlobalFunction(llvm::StringRef Name, + std::optional Ctx) + -> VersionedInfo { + if (!Implementation->GlobalFunctionTable) + return std::nullopt; + + std::optional NameID = Implementation->getIdentifier(Name); + if (!NameID) + return std::nullopt; + + ContextTableKey Key(Ctx, *NameID); + + auto Known = Implementation->GlobalFunctionTable->find(Key); + if (Known == Implementation->GlobalFunctionTable->end()) + return std::nullopt; + + return {Implementation->SwiftVersion, *Known}; +} + +auto APINotesReader::lookupEnumConstant(llvm::StringRef Name) + -> VersionedInfo { + if (!Implementation->EnumConstantTable) + return std::nullopt; + + std::optional NameID = Implementation->getIdentifier(Name); + if (!NameID) + return std::nullopt; + + auto Known = Implementation->EnumConstantTable->find(*NameID); + if (Known == Implementation->EnumConstantTable->end()) + return std::nullopt; + + return {Implementation->SwiftVersion, *Known}; +} + +auto APINotesReader::lookupTag(llvm::StringRef Name, std::optional Ctx) + -> VersionedInfo { + if (!Implementation->TagTable) + return std::nullopt; + + std::optional NameID = Implementation->getIdentifier(Name); + if (!NameID) + return std::nullopt; + + ContextTableKey Key(Ctx, *NameID); + + auto Known = Implementation->TagTable->find(Key); + if (Known == Implementation->TagTable->end()) + return std::nullopt; + + return {Implementation->SwiftVersion, *Known}; +} + +auto APINotesReader::lookupTypedef(llvm::StringRef Name, + std::optional Ctx) + -> VersionedInfo { + if (!Implementation->TypedefTable) + return std::nullopt; + + std::optional NameID = Implementation->getIdentifier(Name); + if (!NameID) + return std::nullopt; + + ContextTableKey Key(Ctx, *NameID); + + auto Known = Implementation->TypedefTable->find(Key); + if (Known == Implementation->TypedefTable->end()) + return std::nullopt; + + return {Implementation->SwiftVersion, *Known}; +} + +auto APINotesReader::lookupNamespaceID( + llvm::StringRef Name, std::optional ParentNamespaceID) + -> std::optional { + if (!Implementation->ObjCContextIDTable) + return std::nullopt; + + std::optional NamespaceID = Implementation->getIdentifier(Name); + if (!NamespaceID) + return std::nullopt; + + uint32_t RawParentNamespaceID = + ParentNamespaceID ? ParentNamespaceID->Value : -1; + auto KnownID = Implementation->ObjCContextIDTable->find( + {RawParentNamespaceID, (uint8_t)ContextKind::Namespace, *NamespaceID}); + if (KnownID == Implementation->ObjCContextIDTable->end()) + return std::nullopt; + + return ContextID(*KnownID); +} + +} // namespace api_notes +} // namespace clang diff --git a/clang/lib/APINotes/CMakeLists.txt b/clang/lib/APINotes/CMakeLists.txt index c34168876a42e..dec596ea160c6 100644 --- a/clang/lib/APINotes/CMakeLists.txt +++ b/clang/lib/APINotes/CMakeLists.txt @@ -1,6 +1,9 @@ set(LLVM_LINK_COMPONENTS + BitReader + BitstreamReader Support) add_clang_library(clangAPINotes + APINotesReader.cpp APINotesTypes.cpp APINotesWriter.cpp APINotesYAMLCompiler.cpp diff --git a/clang/lib/ARCMigrate/FileRemapper.cpp b/clang/lib/ARCMigrate/FileRemapper.cpp index bd8317e0a2451..7abc862ceecc2 100644 --- a/clang/lib/ARCMigrate/FileRemapper.cpp +++ b/clang/lib/ARCMigrate/FileRemapper.cpp @@ -134,9 +134,8 @@ bool FileRemapper::flushToFile(StringRef outputPath, DiagnosticsEngine &Diag) { infoOut << origPath << '\n'; infoOut << (uint64_t)origFE.getModificationTime() << '\n'; - if (I->second.is()) { - auto FE = I->second.get(); - SmallString<200> newPath = StringRef(FE.getName()); + if (const auto *FE = std::get_if(&I->second)) { + SmallString<200> newPath = StringRef(FE->getName()); fs::make_absolute(newPath); infoOut << newPath << '\n'; } else { @@ -150,7 +149,7 @@ bool FileRemapper::flushToFile(StringRef outputPath, DiagnosticsEngine &Diag) { return report("Could not create file: " + tempPath.str(), Diag); llvm::raw_fd_ostream newOut(fd, /*shouldClose=*/true); - llvm::MemoryBuffer *mem = I->second.get(); + llvm::MemoryBuffer *mem = std::get(I->second); newOut.write(mem->getBufferStart(), mem->getBufferSize()); newOut.close(); @@ -173,7 +172,7 @@ bool FileRemapper::overwriteOriginal(DiagnosticsEngine &Diag, for (MappingsTy::iterator I = FromToMappings.begin(), E = FromToMappings.end(); I != E; ++I) { FileEntryRef origFE = I->first; - assert(I->second.is()); + assert(std::holds_alternative(I->second)); if (!fs::exists(origFE.getName())) return report(StringRef("File does not exist: ") + origFE.getName(), Diag); @@ -183,7 +182,7 @@ bool FileRemapper::overwriteOriginal(DiagnosticsEngine &Diag, if (EC) return report(EC.message(), Diag); - llvm::MemoryBuffer *mem = I->second.get(); + llvm::MemoryBuffer *mem = std::get(I->second); Out.write(mem->getBufferStart(), mem->getBufferSize()); Out.close(); } @@ -197,25 +196,23 @@ void FileRemapper::forEachMapping( llvm::function_ref CaptureBuffer) const { for (auto &Mapping : FromToMappings) { - if (Mapping.second.is()) { - auto FE = Mapping.second.get(); - CaptureFile(Mapping.first.getName(), FE.getName()); + if (const auto *FE = std::get_if(&Mapping.second)) { + CaptureFile(Mapping.first.getName(), FE->getName()); continue; } CaptureBuffer( Mapping.first.getName(), - Mapping.second.get()->getMemBufferRef()); + std::get(Mapping.second)->getMemBufferRef()); } } void FileRemapper::applyMappings(PreprocessorOptions &PPOpts) const { for (MappingsTy::const_iterator I = FromToMappings.begin(), E = FromToMappings.end(); I != E; ++I) { - if (I->second.is()) { - auto FE = I->second.get(); - PPOpts.addRemappedFile(I->first.getName(), FE.getName()); + if (const auto *FE = std::get_if(&I->second)) { + PPOpts.addRemappedFile(I->first.getName(), FE->getName()); } else { - llvm::MemoryBuffer *mem = I->second.get(); + llvm::MemoryBuffer *mem = std::get(I->second); PPOpts.addRemappedFile(I->first.getName(), mem); } } @@ -230,18 +227,20 @@ void FileRemapper::remap(StringRef filePath, remap(*File, std::move(memBuf)); } -void FileRemapper::remap(FileEntryRef file, - std::unique_ptr memBuf) { - Target &targ = FromToMappings[file]; - resetTarget(targ); - targ = memBuf.release(); +void FileRemapper::remap(FileEntryRef File, + std::unique_ptr MemBuf) { + auto [It, New] = FromToMappings.insert({File, nullptr}); + if (!New) + resetTarget(It->second); + It->second = MemBuf.release(); } -void FileRemapper::remap(FileEntryRef file, FileEntryRef newfile) { - Target &targ = FromToMappings[file]; - resetTarget(targ); - targ = newfile; - ToFromMappings.insert({newfile, file}); +void FileRemapper::remap(FileEntryRef File, FileEntryRef NewFile) { + auto [It, New] = FromToMappings.insert({File, nullptr}); + if (!New) + resetTarget(It->second); + It->second = NewFile; + ToFromMappings.insert({NewFile, File}); } OptionalFileEntryRef FileRemapper::getOriginalFile(StringRef filePath) { @@ -259,13 +258,11 @@ OptionalFileEntryRef FileRemapper::getOriginalFile(StringRef filePath) { } void FileRemapper::resetTarget(Target &targ) { - if (!targ) - return; - - if (llvm::MemoryBuffer *oldmem = targ.dyn_cast()) { + if (std::holds_alternative(targ)) { + llvm::MemoryBuffer *oldmem = std::get(targ); delete oldmem; } else { - FileEntryRef toFE = targ.get(); + FileEntryRef toFE = std::get(targ); ToFromMappings.erase(toFE); } } diff --git a/clang/lib/ARCMigrate/ObjCMT.cpp b/clang/lib/ARCMigrate/ObjCMT.cpp index 8458a72d6a248..4fa4ab8d42b7d 100644 --- a/clang/lib/ARCMigrate/ObjCMT.cpp +++ b/clang/lib/ARCMigrate/ObjCMT.cpp @@ -123,9 +123,7 @@ class ObjCMigrateASTConsumer : public ASTConsumer { NSIntegerTypedefed(nullptr), NSUIntegerTypedefed(nullptr), Remapper(remapper), FileMgr(fileMgr), PPRec(PPRec), PP(PP), IsOutputFile(isOutputFile), FoundationIncluded(false) { - // FIXME: StringSet should have insert(iter, iter) to use here. - for (const std::string &Val : AllowList) - AllowListFilenames.insert(Val); + AllowListFilenames.insert(AllowList.begin(), AllowList.end()); } protected: diff --git a/clang/lib/AST/APValue.cpp b/clang/lib/AST/APValue.cpp index ef42421518228..d08c2936b56dd 100644 --- a/clang/lib/AST/APValue.cpp +++ b/clang/lib/AST/APValue.cpp @@ -841,6 +841,10 @@ void APValue::printPretty(raw_ostream &Out, const PrintingPolicy &Policy, Out << *VD; ElemTy = VD->getType(); } + } else if (ElemTy->isAnyComplexType()) { + // The lvalue refers to a complex type + Out << (Path[I].getAsArrayIndex() == 0 ? ".real" : ".imag"); + ElemTy = ElemTy->castAs()->getElementType(); } else { // The lvalue must refer to an array. Out << '[' << Path[I].getAsArrayIndex() << ']'; diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp index 27a675b832117..349c559b48b41 100644 --- a/clang/lib/AST/ASTContext.cpp +++ b/clang/lib/AST/ASTContext.cpp @@ -112,10 +112,10 @@ enum FloatingRank { Ibm128Rank }; -/// \returns location that is relevant when searching for Doc comments related -/// to \p D. -static SourceLocation getDeclLocForCommentSearch(const Decl *D, - SourceManager &SourceMgr) { +/// \returns The locations that are relevant when searching for Doc comments +/// related to \p D. +static SmallVector +getDeclLocsForCommentSearch(const Decl *D, SourceManager &SourceMgr) { assert(D); // User can not attach documentation to implicit declarations. @@ -167,115 +167,48 @@ static SourceLocation getDeclLocForCommentSearch(const Decl *D, isa(D)) return {}; + SmallVector Locations; // Find declaration location. // For Objective-C declarations we generally don't expect to have multiple // declarators, thus use declaration starting location as the "declaration // location". // For all other declarations multiple declarators are used quite frequently, // so we use the location of the identifier as the "declaration location". + SourceLocation BaseLocation; if (isa(D) || isa(D) || - isa(D) || - isa(D) || + isa(D) || isa(D) || isa(D) || // Allow association with Y across {} in `typedef struct X {} Y`. isa(D)) - return D->getBeginLoc(); + BaseLocation = D->getBeginLoc(); + else + BaseLocation = D->getLocation(); - const SourceLocation DeclLoc = D->getLocation(); - if (DeclLoc.isMacroID()) { - // There are (at least) three types of macros we care about here. - // - // 1. Macros that are used in the definition of a type outside the macro, - // with a comment attached at the macro call site. - // ``` - // #define MAKE_NAME(Foo) Name##Foo - // - // /// Comment is here, where we use the macro. - // struct MAKE_NAME(Foo) { - // int a; - // int b; - // }; - // ``` - // 2. Macros that define whole things along with the comment. - // ``` - // #define MAKE_METHOD(name) \ - // /** Comment is here, inside the macro. */ \ - // void name() {} - // - // struct S { - // MAKE_METHOD(f) - // } - // ``` - // 3. Macros that both declare a type and name a decl outside the macro. - // ``` - // /// Comment is here, where we use the macro. - // typedef NS_ENUM(NSInteger, Size) { - // SizeWidth, - // SizeHeight - // }; - // ``` - // In this case NS_ENUM declares am enum type, and uses the same name for - // the typedef declaration that appears outside the macro. The comment - // here should be applied to both declarations inside and outside the - // macro. - // - // We have found a Decl name that comes from inside a macro, but - // Decl::getLocation() returns the place where the macro is being called. - // If the declaration (and not just the name) resides inside the macro, - // then we want to map Decl::getLocation() into the macro to where the - // declaration and its attached comment (if any) were written. - // - // This mapping into the macro is done by mapping the location to its - // spelling location, however even if the declaration is inside a macro, - // the name's spelling can come from a macro argument (case 2 above). In - // this case mapping the location to the spelling location finds the - // argument's position (at `f` in MAKE_METHOD(`f`) above), which is not - // where the declaration and its comment are located. - // - // To avoid this issue, we make use of Decl::getBeginLocation() instead. - // While the declaration's position is where the name is written, the - // comment is always attached to the begining of the declaration, not to - // the name. - // - // In the first case, the begin location of the decl is outside the macro, - // at the location of `typedef`. This is where the comment is found as - // well. The begin location is not inside a macro, so it's spelling - // location is the same. - // - // In the second case, the begin location of the decl is the call to the - // macro, at `MAKE_METHOD`. However its spelling location is inside the - // the macro at the location of `void`. This is where the comment is found - // again. - // - // In the third case, there's no correct single behaviour. We want to use - // the comment outside the macro for the definition that's inside the macro. - // There is also a definition outside the macro, and we want the comment to - // apply to both. The cases we care about here is NS_ENUM() and - // NS_OPTIONS(). In general, if an enum is defined inside a macro, we should - // try to find the comment there. - - // This is handling case 3 for NS_ENUM() and NS_OPTIONS(), which define - // enum types inside the macro. - if (isa(D)) { - SourceLocation MacroCallLoc = SourceMgr.getExpansionLoc(DeclLoc); - if (auto BufferRef = - SourceMgr.getBufferOrNone(SourceMgr.getFileID(MacroCallLoc)); - BufferRef.has_value()) { - llvm::StringRef buffer = BufferRef->getBuffer().substr( - SourceMgr.getFileOffset(MacroCallLoc)); - if (buffer.starts_with("NS_ENUM(") || - buffer.starts_with("NS_OPTIONS(")) { - // We want to use the comment on the call to NS_ENUM and NS_OPTIONS - // macros for the types defined inside the macros, which is at the - // expansion location. - return MacroCallLoc; - } - } + if (!D->getLocation().isMacroID()) { + Locations.emplace_back(BaseLocation); + } else { + const auto *DeclCtx = D->getDeclContext(); + + // When encountering definitions generated from a macro (that are not + // contained by another declaration in the macro) we need to try and find + // the comment at the location of the expansion but if there is no comment + // there we should retry to see if there is a comment inside the macro as + // well. To this end we return first BaseLocation to first look at the + // expansion site, the second value is the spelling location of the + // beginning of the declaration defined inside the macro. + if (!(DeclCtx && + Decl::castFromDeclContext(DeclCtx)->getLocation().isMacroID())) { + Locations.emplace_back(SourceMgr.getExpansionLoc(BaseLocation)); } - return SourceMgr.getSpellingLoc(D->getBeginLoc()); + + // We use Decl::getBeginLoc() and not just BaseLocation here to ensure that + // we don't refer to the macro argument location at the expansion site (this + // can happen if the name's spelling is provided via macro argument), and + // always to the declaration itself. + Locations.emplace_back(SourceMgr.getSpellingLoc(D->getBeginLoc())); } - return DeclLoc; + return Locations; } RawComment *ASTContext::getRawCommentForDeclNoCacheImpl( @@ -357,30 +290,36 @@ RawComment *ASTContext::getRawCommentForDeclNoCacheImpl( } RawComment *ASTContext::getRawCommentForDeclNoCache(const Decl *D) const { - const SourceLocation DeclLoc = getDeclLocForCommentSearch(D, SourceMgr); + const auto DeclLocs = getDeclLocsForCommentSearch(D, SourceMgr); - // If the declaration doesn't map directly to a location in a file, we - // can't find the comment. - if (DeclLoc.isInvalid() || !DeclLoc.isFileID()) - return nullptr; + for (const auto DeclLoc : DeclLocs) { + // If the declaration doesn't map directly to a location in a file, we + // can't find the comment. + if (DeclLoc.isInvalid() || !DeclLoc.isFileID()) + continue; - if (ExternalSource && !CommentsLoaded) { - ExternalSource->ReadComments(); - CommentsLoaded = true; - } + if (ExternalSource && !CommentsLoaded) { + ExternalSource->ReadComments(); + CommentsLoaded = true; + } - if (Comments.empty()) - return nullptr; + if (Comments.empty()) + continue; - const FileID File = SourceMgr.getDecomposedLoc(DeclLoc).first; - if (!File.isValid()) { - return nullptr; + const FileID File = SourceMgr.getDecomposedLoc(DeclLoc).first; + if (!File.isValid()) + continue; + + const auto CommentsInThisFile = Comments.getCommentsInFile(File); + if (!CommentsInThisFile || CommentsInThisFile->empty()) + continue; + + if (RawComment *Comment = + getRawCommentForDeclNoCacheImpl(D, DeclLoc, *CommentsInThisFile)) + return Comment; } - const auto CommentsInThisFile = Comments.getCommentsInFile(File); - if (!CommentsInThisFile || CommentsInThisFile->empty()) - return nullptr; - return getRawCommentForDeclNoCacheImpl(D, DeclLoc, *CommentsInThisFile); + return nullptr; } void ASTContext::addComment(const RawComment &RC) { @@ -584,7 +523,6 @@ void ASTContext::attachCommentsToJustParsedDecls(ArrayRef Decls, // declaration, but also comments that *follow* the declaration -- thanks to // the lookahead in the lexer: we've consumed the semicolon and looked // ahead through comments. - for (const Decl *D : Decls) { assert(D); if (D->isInvalidDecl()) @@ -592,19 +530,22 @@ void ASTContext::attachCommentsToJustParsedDecls(ArrayRef Decls, D = &adjustDeclToTemplate(*D); - const SourceLocation DeclLoc = getDeclLocForCommentSearch(D, SourceMgr); - - if (DeclLoc.isInvalid() || !DeclLoc.isFileID()) - continue; - if (DeclRawComments.count(D) > 0) continue; - if (RawComment *const DocComment = - getRawCommentForDeclNoCacheImpl(D, DeclLoc, *CommentsInThisFile)) { - cacheRawCommentForDecl(*D, *DocComment); - comments::FullComment *FC = DocComment->parse(*this, PP, D); - ParsedComments[D->getCanonicalDecl()] = FC; + const auto DeclLocs = getDeclLocsForCommentSearch(D, SourceMgr); + + for (const auto DeclLoc : DeclLocs) { + if (DeclLoc.isInvalid() || !DeclLoc.isFileID()) + continue; + + if (RawComment *const DocComment = getRawCommentForDeclNoCacheImpl( + D, DeclLoc, *CommentsInThisFile)) { + cacheRawCommentForDecl(*D, *DocComment); + comments::FullComment *FC = DocComment->parse(*this, PP, D); + ParsedComments[D->getCanonicalDecl()] = FC; + break; + } } } } @@ -1081,7 +1022,7 @@ void ASTContext::deduplicateMergedDefinitonsFor(NamedDecl *ND) { for (Module *&M : Merged) if (!Found.insert(M).second) M = nullptr; - llvm::erase_value(Merged, nullptr); + llvm::erase(Merged, nullptr); } ArrayRef @@ -9622,9 +9563,7 @@ bool ASTContext::areLaxCompatibleRVVTypes(QualType FirstType, return false; const auto *VecTy = SecondType->getAs(); - if (VecTy && - (VecTy->getVectorKind() == VectorType::RVVFixedLengthDataVector || - VecTy->getVectorKind() == VectorType::GenericVector)) { + if (VecTy && VecTy->getVectorKind() == VectorType::GenericVector) { const LangOptions::LaxVectorConversionKind LVCKind = getLangOpts().getLaxVectorConversions(); diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp index ce69bad36a1a1..f6f71ce6bfe0f 100644 --- a/clang/lib/AST/ExprConstant.cpp +++ b/clang/lib/AST/ExprConstant.cpp @@ -2411,10 +2411,15 @@ static bool CheckEvaluationResult(CheckEvaluationResultKind CERK, const FieldDecl *SubobjectDecl, CheckedTemporaries &CheckedTemps) { if (!Value.hasValue()) { - assert(SubobjectDecl && "SubobjectDecl shall be non-null"); - Info.FFDiag(DiagLoc, diag::note_constexpr_uninitialized) << SubobjectDecl; - Info.Note(SubobjectDecl->getLocation(), - diag::note_constexpr_subobject_declared_here); + if (SubobjectDecl) { + Info.FFDiag(DiagLoc, diag::note_constexpr_uninitialized) + << /*(name)*/ 1 << SubobjectDecl; + Info.Note(SubobjectDecl->getLocation(), + diag::note_constexpr_subobject_declared_here); + } else { + Info.FFDiag(DiagLoc, diag::note_constexpr_uninitialized) + << /*of type*/ 0 << Type; + } return false; } @@ -2732,53 +2737,6 @@ static bool truncateBitfieldValue(EvalInfo &Info, const Expr *E, return true; } -static bool EvalAndBitcastToAPInt(EvalInfo &Info, const Expr *E, - llvm::APInt &Res) { - APValue SVal; - if (!Evaluate(SVal, Info, E)) - return false; - if (SVal.isInt()) { - Res = SVal.getInt(); - return true; - } - if (SVal.isFloat()) { - Res = SVal.getFloat().bitcastToAPInt(); - return true; - } - if (SVal.isVector()) { - QualType VecTy = E->getType(); - unsigned VecSize = Info.Ctx.getTypeSize(VecTy); - QualType EltTy = VecTy->castAs()->getElementType(); - unsigned EltSize = Info.Ctx.getTypeSize(EltTy); - bool BigEndian = Info.Ctx.getTargetInfo().isBigEndian(); - Res = llvm::APInt::getZero(VecSize); - for (unsigned i = 0; i < SVal.getVectorLength(); i++) { - APValue &Elt = SVal.getVectorElt(i); - llvm::APInt EltAsInt; - if (Elt.isInt()) { - EltAsInt = Elt.getInt(); - } else if (Elt.isFloat()) { - EltAsInt = Elt.getFloat().bitcastToAPInt(); - } else { - // Don't try to handle vectors of anything other than int or float - // (not sure if it's possible to hit this case). - Info.FFDiag(E, diag::note_invalid_subexpr_in_const_expr); - return false; - } - unsigned BaseEltSize = EltAsInt.getBitWidth(); - if (BigEndian) - Res |= EltAsInt.zextOrTrunc(VecSize).rotr(i*EltSize+BaseEltSize); - else - Res |= EltAsInt.zextOrTrunc(VecSize).rotl(i*EltSize); - } - return true; - } - // Give up if the input isn't an int, float, or vector. For example, we - // reject "(v4i16)(intptr_t)&a". - Info.FFDiag(E, diag::note_invalid_subexpr_in_const_expr); - return false; -} - /// Perform the given integer operation, which is known to need at most BitWidth /// bits, and check for overflow in the original type (if that type was not an /// unsigned type). @@ -4872,8 +4830,13 @@ static bool HandleBaseToDerivedCast(EvalInfo &Info, const CastExpr *E, /// Get the value to use for a default-initialized object of type T. /// Return false if it encounters something invalid. -static bool getDefaultInitValue(QualType T, APValue &Result) { +static bool handleDefaultInitValue(QualType T, APValue &Result) { bool Success = true; + + // If there is already a value present don't overwrite it. + if (!Result.isAbsent()) + return true; + if (auto *RD = T->getAsCXXRecordDecl()) { if (RD->isInvalidDecl()) { Result = APValue(); @@ -4890,13 +4853,14 @@ static bool getDefaultInitValue(QualType T, APValue &Result) { for (CXXRecordDecl::base_class_const_iterator I = RD->bases_begin(), End = RD->bases_end(); I != End; ++I, ++Index) - Success &= getDefaultInitValue(I->getType(), Result.getStructBase(Index)); + Success &= + handleDefaultInitValue(I->getType(), Result.getStructBase(Index)); for (const auto *I : RD->fields()) { if (I->isUnnamedBitfield()) continue; - Success &= getDefaultInitValue(I->getType(), - Result.getStructField(I->getFieldIndex())); + Success &= handleDefaultInitValue( + I->getType(), Result.getStructField(I->getFieldIndex())); } return Success; } @@ -4906,7 +4870,7 @@ static bool getDefaultInitValue(QualType T, APValue &Result) { Result = APValue(APValue::UninitArray(), 0, AT->getSize().getZExtValue()); if (Result.hasArrayFiller()) Success &= - getDefaultInitValue(AT->getElementType(), Result.getArrayFiller()); + handleDefaultInitValue(AT->getElementType(), Result.getArrayFiller()); return Success; } @@ -4947,7 +4911,7 @@ static bool EvaluateVarDecl(EvalInfo &Info, const VarDecl *VD) { if (!InitE) { if (VD->getType()->isDependentType()) return Info.noteSideEffect(); - return getDefaultInitValue(VD->getType(), Val); + return handleDefaultInitValue(VD->getType(), Val); } if (InitE->isValueDependent()) return false; @@ -6049,7 +6013,7 @@ struct StartLifetimeOfUnionMemberHandler { return false; } APValue Result; - Failed = !getDefaultInitValue(Field->getType(), Result); + Failed = !handleDefaultInitValue(Field->getType(), Result); Subobj.setUnion(Field, Result); return true; } @@ -6401,7 +6365,7 @@ static bool HandleConstructorCall(const Expr *E, const LValue &This, for (; !declaresSameEntity(*FieldIt, FD); ++FieldIt) { assert(FieldIt != RD->field_end() && "missing field?"); if (!FieldIt->isUnnamedBitfield()) - Success &= getDefaultInitValue( + Success &= handleDefaultInitValue( FieldIt->getType(), Result.getStructField(FieldIt->getFieldIndex())); } @@ -6458,7 +6422,8 @@ static bool HandleConstructorCall(const Expr *E, const LValue &This, // FIXME: This immediately starts the lifetime of all members of // an anonymous struct. It would be preferable to strictly start // member lifetime in initialization order. - Success &= getDefaultInitValue(Info.Ctx.getRecordType(CD), *Value); + Success &= + handleDefaultInitValue(Info.Ctx.getRecordType(CD), *Value); } // Store Subobject as its parent before updating it for the last element // in the chain. @@ -6510,7 +6475,7 @@ static bool HandleConstructorCall(const Expr *E, const LValue &This, if (!RD->isUnion()) { for (; FieldIt != RD->field_end(); ++FieldIt) { if (!FieldIt->isUnnamedBitfield()) - Success &= getDefaultInitValue( + Success &= handleDefaultInitValue( FieldIt->getType(), Result.getStructField(FieldIt->getFieldIndex())); } @@ -6860,8 +6825,8 @@ static std::optional CheckDeleteKind(EvalInfo &Info, const Expr *E, return std::nullopt; } - QualType AllocType = Pointer.Base.getDynamicAllocType(); if (DeallocKind != (*Alloc)->getKind()) { + QualType AllocType = Pointer.Base.getDynamicAllocType(); Info.FFDiag(E, diag::note_constexpr_new_delete_mismatch) << DeallocKind << (*Alloc)->getKind() << AllocType; NoteLValueLocation(Info, Pointer.Base); @@ -7011,10 +6976,11 @@ class APValueToBufferConverter { return visitArray(Val, Ty, Offset); case APValue::Struct: return visitRecord(Val, Ty, Offset); + case APValue::Vector: + return visitVector(Val, Ty, Offset); case APValue::ComplexInt: case APValue::ComplexFloat: - case APValue::Vector: case APValue::FixedPoint: // FIXME: We should support these. @@ -7101,6 +7067,72 @@ class APValueToBufferConverter { return true; } + bool visitVector(const APValue &Val, QualType Ty, CharUnits Offset) { + const VectorType *VTy = Ty->castAs(); + QualType EltTy = VTy->getElementType(); + unsigned NElts = VTy->getNumElements(); + unsigned EltSize = + VTy->isExtVectorBoolType() ? 1 : Info.Ctx.getTypeSize(EltTy); + + if ((NElts * EltSize) % Info.Ctx.getCharWidth() != 0) { + // The vector's size in bits is not a multiple of the target's byte size, + // so its layout is unspecified. For now, we'll simply treat these cases + // as unsupported (this should only be possible with OpenCL bool vectors + // whose element count isn't a multiple of the byte size). + Info.FFDiag(BCE->getBeginLoc(), + diag::note_constexpr_bit_cast_invalid_vector) + << Ty.getCanonicalType() << EltSize << NElts + << Info.Ctx.getCharWidth(); + return false; + } + + if (EltTy->isRealFloatingType() && &Info.Ctx.getFloatTypeSemantics(EltTy) == + &APFloat::x87DoubleExtended()) { + // The layout for x86_fp80 vectors seems to be handled very inconsistently + // by both clang and LLVM, so for now we won't allow bit_casts involving + // it in a constexpr context. + Info.FFDiag(BCE->getBeginLoc(), + diag::note_constexpr_bit_cast_unsupported_type) + << EltTy; + return false; + } + + if (VTy->isExtVectorBoolType()) { + // Special handling for OpenCL bool vectors: + // Since these vectors are stored as packed bits, but we can't write + // individual bits to the BitCastBuffer, we'll buffer all of the elements + // together into an appropriately sized APInt and write them all out at + // once. Because we don't accept vectors where NElts * EltSize isn't a + // multiple of the char size, there will be no padding space, so we don't + // have to worry about writing data which should have been left + // uninitialized. + bool BigEndian = Info.Ctx.getTargetInfo().isBigEndian(); + + llvm::APInt Res = llvm::APInt::getZero(NElts); + for (unsigned I = 0; I < NElts; ++I) { + const llvm::APSInt &EltAsInt = Val.getVectorElt(I).getInt(); + assert(EltAsInt.isUnsigned() && EltAsInt.getBitWidth() == 1 && + "bool vector element must be 1-bit unsigned integer!"); + + Res.insertBits(EltAsInt, BigEndian ? (NElts - I - 1) : I); + } + + SmallVector Bytes(NElts / 8); + llvm::StoreIntToMemory(Res, &*Bytes.begin(), NElts / 8); + Buffer.writeObject(Offset, Bytes); + } else { + // Iterate over each of the elements and write them out to the buffer at + // the appropriate offset. + CharUnits EltSizeChars = Info.Ctx.getTypeSizeInChars(EltTy); + for (unsigned I = 0; I < NElts; ++I) { + if (!visit(Val.getVectorElt(I), EltTy, Offset + I * EltSizeChars)) + return false; + } + } + + return true; + } + bool visitInt(const APSInt &Val, QualType Ty, CharUnits Offset) { APSInt AdjustedVal = Val; unsigned Width = AdjustedVal.getBitWidth(); @@ -7109,7 +7141,7 @@ class APValueToBufferConverter { AdjustedVal = AdjustedVal.extend(Width); } - SmallVector Bytes(Width / 8); + SmallVector Bytes(Width / 8); llvm::StoreIntToMemory(AdjustedVal, &*Bytes.begin(), Width / 8); Buffer.writeObject(Offset, Bytes); return true; @@ -7310,6 +7342,77 @@ class BufferToAPValueConverter { return ArrayValue; } + std::optional visit(const VectorType *VTy, CharUnits Offset) { + QualType EltTy = VTy->getElementType(); + unsigned NElts = VTy->getNumElements(); + unsigned EltSize = + VTy->isExtVectorBoolType() ? 1 : Info.Ctx.getTypeSize(EltTy); + + if ((NElts * EltSize) % Info.Ctx.getCharWidth() != 0) { + // The vector's size in bits is not a multiple of the target's byte size, + // so its layout is unspecified. For now, we'll simply treat these cases + // as unsupported (this should only be possible with OpenCL bool vectors + // whose element count isn't a multiple of the byte size). + Info.FFDiag(BCE->getBeginLoc(), + diag::note_constexpr_bit_cast_invalid_vector) + << QualType(VTy, 0) << EltSize << NElts << Info.Ctx.getCharWidth(); + return std::nullopt; + } + + if (EltTy->isRealFloatingType() && &Info.Ctx.getFloatTypeSemantics(EltTy) == + &APFloat::x87DoubleExtended()) { + // The layout for x86_fp80 vectors seems to be handled very inconsistently + // by both clang and LLVM, so for now we won't allow bit_casts involving + // it in a constexpr context. + Info.FFDiag(BCE->getBeginLoc(), + diag::note_constexpr_bit_cast_unsupported_type) + << EltTy; + return std::nullopt; + } + + SmallVector Elts; + Elts.reserve(NElts); + if (VTy->isExtVectorBoolType()) { + // Special handling for OpenCL bool vectors: + // Since these vectors are stored as packed bits, but we can't read + // individual bits from the BitCastBuffer, we'll buffer all of the + // elements together into an appropriately sized APInt and write them all + // out at once. Because we don't accept vectors where NElts * EltSize + // isn't a multiple of the char size, there will be no padding space, so + // we don't have to worry about reading any padding data which didn't + // actually need to be accessed. + bool BigEndian = Info.Ctx.getTargetInfo().isBigEndian(); + + SmallVector Bytes; + Bytes.reserve(NElts / 8); + if (!Buffer.readObject(Offset, CharUnits::fromQuantity(NElts / 8), Bytes)) + return std::nullopt; + + APSInt SValInt(NElts, true); + llvm::LoadIntFromMemory(SValInt, &*Bytes.begin(), Bytes.size()); + + for (unsigned I = 0; I < NElts; ++I) { + llvm::APInt Elt = + SValInt.extractBits(1, (BigEndian ? NElts - I - 1 : I) * EltSize); + Elts.emplace_back( + APSInt(std::move(Elt), !EltTy->isSignedIntegerType())); + } + } else { + // Iterate over each of the elements and read them from the buffer at + // the appropriate offset. + CharUnits EltSizeChars = Info.Ctx.getTypeSizeInChars(EltTy); + for (unsigned I = 0; I < NElts; ++I) { + std::optional EltValue = + visitType(EltTy, Offset + I * EltSizeChars); + if (!EltValue) + return std::nullopt; + Elts.push_back(std::move(*EltValue)); + } + } + + return APValue(Elts.data(), Elts.size()); + } + std::optional visit(const Type *Ty, CharUnits Offset) { return unsupportedType(QualType(Ty, 0)); } @@ -7409,25 +7512,15 @@ static bool checkBitCastConstexprEligibility(EvalInfo *Info, return SourceOK; } -static bool handleLValueToRValueBitCast(EvalInfo &Info, APValue &DestValue, - APValue &SourceValue, +static bool handleRValueToRValueBitCast(EvalInfo &Info, APValue &DestValue, + const APValue &SourceRValue, const CastExpr *BCE) { assert(CHAR_BIT == 8 && Info.Ctx.getTargetInfo().getCharWidth() == 8 && "no host or target supports non 8-bit chars"); - assert(SourceValue.isLValue() && - "LValueToRValueBitcast requires an lvalue operand!"); if (!checkBitCastConstexprEligibility(&Info, Info.Ctx, BCE)) return false; - LValue SourceLValue; - APValue SourceRValue; - SourceLValue.setFrom(Info.Ctx, SourceValue); - if (!handleLValueToRValueConversion( - Info, BCE, BCE->getSubExpr()->getType().withConst(), SourceLValue, - SourceRValue, /*WantObjectRepresentation=*/true)) - return false; - // Read out SourceValue into a char buffer. std::optional Buffer = APValueToBufferConverter::convert(Info, SourceRValue, BCE); @@ -7444,6 +7537,25 @@ static bool handleLValueToRValueBitCast(EvalInfo &Info, APValue &DestValue, return true; } +static bool handleLValueToRValueBitCast(EvalInfo &Info, APValue &DestValue, + APValue &SourceValue, + const CastExpr *BCE) { + assert(CHAR_BIT == 8 && Info.Ctx.getTargetInfo().getCharWidth() == 8 && + "no host or target supports non 8-bit chars"); + assert(SourceValue.isLValue() && + "LValueToRValueBitcast requires an lvalue operand!"); + + LValue SourceLValue; + APValue SourceRValue; + SourceLValue.setFrom(Info.Ctx, SourceValue); + if (!handleLValueToRValueConversion( + Info, BCE, BCE->getSubExpr()->getType().withConst(), SourceLValue, + SourceRValue, /*WantObjectRepresentation=*/true)) + return false; + + return handleRValueToRValueBitCast(Info, DestValue, SourceRValue, BCE); +} + template class ExprEvaluatorBase : public ConstStmtVisitor { @@ -9545,6 +9657,8 @@ bool PointerExprEvaluator::VisitBuiltinCallExpr(const CallExpr *E, // Figure out how many T's we're copying. uint64_t TSize = Info.Ctx.getTypeSizeInChars(T).getQuantity(); + if (TSize == 0) + return false; if (!WChar) { uint64_t Remainder; llvm::APInt OrigN = N; @@ -9821,7 +9935,7 @@ bool PointerExprEvaluator::VisitCXXNewExpr(const CXXNewExpr *E) { } else if (Init) { if (!EvaluateInPlace(*Val, Info, Result, Init)) return false; - } else if (!getDefaultInitValue(AllocType, *Val)) { + } else if (!handleDefaultInitValue(AllocType, *Val)) { return false; } @@ -10231,7 +10345,7 @@ bool RecordExprEvaluator::VisitCXXConstructExpr(const CXXConstructExpr *E, if (ZeroInit) return ZeroInitialization(E, T); - return getDefaultInitValue(T, Result); + return handleDefaultInitValue(T, Result); } const FunctionDecl *Definition = nullptr; @@ -10526,41 +10640,22 @@ bool VectorExprEvaluator::VisitCastExpr(const CastExpr *E) { return Success(Elts, E); } case CK_BitCast: { - // Evaluate the operand into an APInt we can extract from. - llvm::APInt SValInt; - if (!EvalAndBitcastToAPInt(Info, SE, SValInt)) + APValue SVal; + if (!Evaluate(SVal, Info, SE)) + return false; + + if (!SVal.isInt() && !SVal.isFloat() && !SVal.isVector()) { + // Give up if the input isn't an int, float, or vector. For example, we + // reject "(v4i16)(intptr_t)&a". + Info.FFDiag(E, diag::note_constexpr_invalid_cast) + << 2 << Info.Ctx.getLangOpts().CPlusPlus; return false; - // Extract the elements - QualType EltTy = VTy->getElementType(); - unsigned EltSize = Info.Ctx.getTypeSize(EltTy); - bool BigEndian = Info.Ctx.getTargetInfo().isBigEndian(); - SmallVector Elts; - if (EltTy->isRealFloatingType()) { - const llvm::fltSemantics &Sem = Info.Ctx.getFloatTypeSemantics(EltTy); - unsigned FloatEltSize = EltSize; - if (&Sem == &APFloat::x87DoubleExtended()) - FloatEltSize = 80; - for (unsigned i = 0; i < NElts; i++) { - llvm::APInt Elt; - if (BigEndian) - Elt = SValInt.rotl(i * EltSize + FloatEltSize).trunc(FloatEltSize); - else - Elt = SValInt.rotr(i * EltSize).trunc(FloatEltSize); - Elts.push_back(APValue(APFloat(Sem, Elt))); - } - } else if (EltTy->isIntegerType()) { - for (unsigned i = 0; i < NElts; i++) { - llvm::APInt Elt; - if (BigEndian) - Elt = SValInt.rotl(i*EltSize+EltSize).zextOrTrunc(EltSize); - else - Elt = SValInt.rotr(i*EltSize).zextOrTrunc(EltSize); - Elts.push_back(APValue(APSInt(Elt, !EltTy->isSignedIntegerType()))); - } - } else { - return Error(E); } - return Success(Elts, E); + + if (!handleRValueToRValueBitCast(Info, Result, SVal, E)) + return false; + + return true; } default: return ExprEvaluatorBaseTy::VisitCastExpr(E); @@ -15653,7 +15748,7 @@ bool VarDecl::evaluateDestruction( APValue DestroyedValue; if (getEvaluatedValue() && !getEvaluatedValue()->isAbsent()) DestroyedValue = *getEvaluatedValue(); - else if (!getDefaultInitValue(getType(), DestroyedValue)) + else if (!handleDefaultInitValue(getType(), DestroyedValue)) return false; if (!EvaluateDestruction(getASTContext(), this, std::move(DestroyedValue), diff --git a/clang/lib/AST/Interp/ByteCodeExprGen.cpp b/clang/lib/AST/Interp/ByteCodeExprGen.cpp index ed971fe0f650f..485893d58f487 100644 --- a/clang/lib/AST/Interp/ByteCodeExprGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeExprGen.cpp @@ -168,7 +168,16 @@ bool ByteCodeExprGen::VisitCastExpr(const CastExpr *CE) { return this->emitCastPointerIntegral(T, CE); } - case CK_ArrayToPointerDecay: + case CK_ArrayToPointerDecay: { + if (!this->visit(SubExpr)) + return false; + if (!this->emitArrayDecay(CE)) + return false; + if (DiscardResult) + return this->emitPopPtr(CE); + return true; + } + case CK_AtomicToNonAtomic: case CK_ConstructorConversion: case CK_FunctionToPointerDecay: @@ -505,6 +514,9 @@ bool ByteCodeExprGen::VisitImplicitValueInitExpr(const ImplicitValueIni if (QT->isRecordType()) return false; + if (QT->isIncompleteArrayType()) + return true; + if (QT->isArrayType()) { const ArrayType *AT = QT->getAsArrayTypeUnsafe(); assert(AT); @@ -817,17 +829,27 @@ bool ByteCodeExprGen::VisitArrayInitLoopExpr( assert(Initializing); assert(!DiscardResult); // TODO: This compiles to quite a lot of bytecode if the array is larger. - // Investigate compiling this to a loop, or at least try to use - // the AILE's Common expr. + // Investigate compiling this to a loop. + const Expr *SubExpr = E->getSubExpr(); + const Expr *CommonExpr = E->getCommonExpr(); size_t Size = E->getArraySize().getZExtValue(); std::optional ElemT = classify(SubExpr->getType()); + // If the common expression is an opaque expression, we visit it + // here once so we have its value cached. + // FIXME: This might be necessary (or useful) for all expressions. + if (isa(CommonExpr)) { + if (!this->discard(CommonExpr)) + return false; + } + // So, every iteration, we execute an assignment here // where the LHS is on the stack (the target array) // and the RHS is our SubExpr. for (size_t I = 0; I != Size; ++I) { ArrayIndexScope IndexScope(this, I); + BlockScope BS(this); if (ElemT) { if (!this->visit(SubExpr)) @@ -853,7 +875,35 @@ template bool ByteCodeExprGen::VisitOpaqueValueExpr(const OpaqueValueExpr *E) { if (Initializing) return this->visitInitializer(E->getSourceExpr()); - return this->visit(E->getSourceExpr()); + + PrimType SubExprT = classify(E->getSourceExpr()).value_or(PT_Ptr); + if (auto It = OpaqueExprs.find(E); It != OpaqueExprs.end()) + return this->emitGetLocal(SubExprT, It->second, E); + + if (!this->visit(E->getSourceExpr())) + return false; + + // At this point we either have the evaluated source expression or a pointer + // to an object on the stack. We want to create a local variable that stores + // this value. + std::optional LocalIndex = + allocateLocalPrimitive(E, SubExprT, /*IsConst=*/true); + if (!LocalIndex) + return false; + if (!this->emitSetLocal(SubExprT, *LocalIndex, E)) + return false; + + // Here the local variable is created but the value is removed from the stack, + // so we put it back, because the caller might need it. + if (!DiscardResult) { + if (!this->emitGetLocal(SubExprT, *LocalIndex, E)) + return false; + } + + // FIXME: Ideally the cached value should be cleaned up later. + OpaqueExprs.insert({E, *LocalIndex}); + + return true; } template @@ -1264,9 +1314,7 @@ bool ByteCodeExprGen::VisitMaterializeTemporaryExpr( template bool ByteCodeExprGen::VisitCXXBindTemporaryExpr( const CXXBindTemporaryExpr *E) { - if (Initializing) - return this->visitInitializer(E->getSubExpr()); - return this->visit(E->getSubExpr()); + return this->delegate(E->getSubExpr()); } template @@ -1571,8 +1619,12 @@ bool ByteCodeExprGen::VisitOffsetOfExpr(const OffsetOfExpr *E) { template bool ByteCodeExprGen::VisitCXXScalarValueInitExpr( const CXXScalarValueInitExpr *E) { - return this->visitZeroInitializer(classifyPrim(E->getType()), E->getType(), - E); + QualType Ty = E->getType(); + + if (Ty->isVoidType()) + return true; + + return this->visitZeroInitializer(classifyPrim(Ty), Ty, E); } template bool ByteCodeExprGen::discard(const Expr *E) { @@ -2495,9 +2547,7 @@ bool ByteCodeExprGen::VisitUnaryOperator(const UnaryOperator *E) { return DiscardResult ? this->emitPop(*T, E) : true; case UO_AddrOf: // &x // We should already have a pointer when we get here. - if (!this->visit(SubExpr)) - return false; - return DiscardResult ? this->emitPop(*T, E) : true; + return this->delegate(SubExpr); case UO_Deref: // *x return dereference( SubExpr, DerefKind::Read, @@ -2678,19 +2728,28 @@ bool ByteCodeExprGen::emitRecordDestruction(const Descriptor *Desc) { // Arrays. if (Desc->isArray()) { const Descriptor *ElemDesc = Desc->ElemDesc; - const Record *ElemRecord = ElemDesc->ElemRecord; - assert(ElemRecord); // This is not a primitive array. + assert(ElemDesc); + + // Don't need to do anything for these. + if (ElemDesc->isPrimitiveArray()) + return this->emitPopPtr(SourceInfo{}); + + // If this is an array of record types, check if we need + // to call the element destructors at all. If not, try + // to save the work. + if (const Record *ElemRecord = ElemDesc->ElemRecord) { + if (const CXXDestructorDecl *Dtor = ElemRecord->getDestructor(); + !Dtor || Dtor->isTrivial()) + return this->emitPopPtr(SourceInfo{}); + } - if (const CXXDestructorDecl *Dtor = ElemRecord->getDestructor(); - Dtor && !Dtor->isTrivial()) { - for (ssize_t I = Desc->getNumElems() - 1; I >= 0; --I) { - if (!this->emitConstUint64(I, SourceInfo{})) - return false; - if (!this->emitArrayElemPtrUint64(SourceInfo{})) - return false; - if (!this->emitRecordDestruction(Desc->ElemDesc)) - return false; - } + for (ssize_t I = Desc->getNumElems() - 1; I >= 0; --I) { + if (!this->emitConstUint64(I, SourceInfo{})) + return false; + if (!this->emitArrayElemPtrUint64(SourceInfo{})) + return false; + if (!this->emitRecordDestruction(ElemDesc)) + return false; } return this->emitPopPtr(SourceInfo{}); } diff --git a/clang/lib/AST/Interp/ByteCodeStmtGen.cpp b/clang/lib/AST/Interp/ByteCodeStmtGen.cpp index 509abe3ae867f..b1ab5fcf9cb64 100644 --- a/clang/lib/AST/Interp/ByteCodeStmtGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeStmtGen.cpp @@ -255,6 +255,8 @@ bool ByteCodeStmtGen::visitStmt(const Stmt *S) { return visitAsmStmt(cast(S)); case Stmt::AttributedStmtClass: return visitAttributedStmt(cast(S)); + case Stmt::CXXTryStmtClass: + return visitCXXTryStmt(cast(S)); case Stmt::NullStmtClass: return true; default: { @@ -643,6 +645,12 @@ bool ByteCodeStmtGen::visitAttributedStmt(const AttributedStmt *S) { return this->visitStmt(S->getSubStmt()); } +template +bool ByteCodeStmtGen::visitCXXTryStmt(const CXXTryStmt *S) { + // Ignore all handlers. + return this->visitStmt(S->getTryBlock()); +} + namespace clang { namespace interp { diff --git a/clang/lib/AST/Interp/ByteCodeStmtGen.h b/clang/lib/AST/Interp/ByteCodeStmtGen.h index 31f9dbb8064c7..64e03587ab211 100644 --- a/clang/lib/AST/Interp/ByteCodeStmtGen.h +++ b/clang/lib/AST/Interp/ByteCodeStmtGen.h @@ -65,6 +65,7 @@ class ByteCodeStmtGen final : public ByteCodeExprGen { bool visitDefaultStmt(const DefaultStmt *S); bool visitAsmStmt(const AsmStmt *S); bool visitAttributedStmt(const AttributedStmt *S); + bool visitCXXTryStmt(const CXXTryStmt *S); bool emitLambdaStaticInvokerBody(const CXXMethodDecl *MD); diff --git a/clang/lib/AST/Interp/Context.cpp b/clang/lib/AST/Interp/Context.cpp index 04710cd0f2c28..cb96e56fb5e1a 100644 --- a/clang/lib/AST/Interp/Context.cpp +++ b/clang/lib/AST/Interp/Context.cpp @@ -158,10 +158,19 @@ const llvm::fltSemantics &Context::getFloatSemantics(QualType T) const { } bool Context::Run(State &Parent, const Function *Func, APValue &Result) { - InterpState State(Parent, *P, Stk, *this); - State.Current = new InterpFrame(State, Func, /*Caller=*/nullptr, {}); - if (Interpret(State, Result)) - return true; + + { + InterpState State(Parent, *P, Stk, *this); + State.Current = new InterpFrame(State, Func, /*Caller=*/nullptr, {}); + if (Interpret(State, Result)) { + assert(Stk.empty()); + return true; + } + + // State gets destroyed here, so the Stk.clear() below doesn't accidentally + // remove values the State's destructor might accedd. + } + Stk.clear(); return false; } diff --git a/clang/lib/AST/Interp/Descriptor.cpp b/clang/lib/AST/Interp/Descriptor.cpp index 3990282686fe3..59a952135a2d8 100644 --- a/clang/lib/AST/Interp/Descriptor.cpp +++ b/clang/lib/AST/Interp/Descriptor.cpp @@ -40,6 +40,9 @@ static void moveTy(Block *, const std::byte *Src, std::byte *Dst, template static void ctorArrayTy(Block *, std::byte *Ptr, bool, bool, bool, const Descriptor *D) { + new (Ptr) InitMapPtr(std::nullopt); + + Ptr += sizeof(InitMapPtr); for (unsigned I = 0, NE = D->getNumElems(); I < NE; ++I) { new (&reinterpret_cast(Ptr)[I]) T(); } @@ -47,11 +50,11 @@ static void ctorArrayTy(Block *, std::byte *Ptr, bool, bool, bool, template static void dtorArrayTy(Block *, std::byte *Ptr, const Descriptor *D) { - InitMap *IM = *reinterpret_cast(Ptr); - if (IM != (InitMap *)-1) - free(IM); + InitMapPtr &IMP = *reinterpret_cast(Ptr); - Ptr += sizeof(InitMap *); + if (IMP) + IMP = std::nullopt; + Ptr += sizeof(InitMapPtr); for (unsigned I = 0, NE = D->getNumElems(); I < NE; ++I) { reinterpret_cast(Ptr)[I].~T(); } @@ -209,7 +212,8 @@ static BlockMoveFn getMovePrim(PrimType Type) { } static BlockCtorFn getCtorArrayPrim(PrimType Type) { - COMPOSITE_TYPE_SWITCH(Type, return ctorArrayTy, return nullptr); + TYPE_SWITCH(Type, return ctorArrayTy); + llvm_unreachable("unknown Expr"); } static BlockDtorFn getDtorArrayPrim(PrimType Type) { @@ -218,7 +222,8 @@ static BlockDtorFn getDtorArrayPrim(PrimType Type) { } static BlockMoveFn getMoveArrayPrim(PrimType Type) { - COMPOSITE_TYPE_SWITCH(Type, return moveArrayTy, return nullptr); + TYPE_SWITCH(Type, return moveArrayTy); + llvm_unreachable("unknown Expr"); } /// Primitives. @@ -238,7 +243,7 @@ Descriptor::Descriptor(const DeclTy &D, PrimType Type, MetadataSize MD, bool IsMutable) : Source(D), ElemSize(primSize(Type)), Size(ElemSize * NumElems), MDSize(MD.value_or(0)), - AllocSize(align(Size) + sizeof(InitMap *) + MDSize), IsConst(IsConst), + AllocSize(align(Size) + sizeof(InitMapPtr) + MDSize), IsConst(IsConst), IsMutable(IsMutable), IsTemporary(IsTemporary), IsArray(true), CtorFn(getCtorArrayPrim(Type)), DtorFn(getDtorArrayPrim(Type)), MoveFn(getMoveArrayPrim(Type)) { @@ -249,14 +254,15 @@ Descriptor::Descriptor(const DeclTy &D, PrimType Type, MetadataSize MD, Descriptor::Descriptor(const DeclTy &D, PrimType Type, bool IsTemporary, UnknownSize) : Source(D), ElemSize(primSize(Type)), Size(UnknownSizeMark), MDSize(0), - AllocSize(alignof(void *)), IsConst(true), IsMutable(false), - IsTemporary(IsTemporary), IsArray(true), CtorFn(getCtorArrayPrim(Type)), - DtorFn(getDtorArrayPrim(Type)), MoveFn(getMoveArrayPrim(Type)) { + AllocSize(alignof(void *) + sizeof(InitMapPtr)), IsConst(true), + IsMutable(false), IsTemporary(IsTemporary), IsArray(true), + CtorFn(getCtorArrayPrim(Type)), DtorFn(getDtorArrayPrim(Type)), + MoveFn(getMoveArrayPrim(Type)) { assert(Source && "Missing source"); } /// Arrays of composite elements. -Descriptor::Descriptor(const DeclTy &D, Descriptor *Elem, MetadataSize MD, +Descriptor::Descriptor(const DeclTy &D, const Descriptor *Elem, MetadataSize MD, unsigned NumElems, bool IsConst, bool IsTemporary, bool IsMutable) : Source(D), ElemSize(Elem->getAllocSize() + sizeof(InlineDescriptor)), @@ -272,10 +278,10 @@ Descriptor::Descriptor(const DeclTy &D, Descriptor *Elem, MetadataSize MD, Descriptor::Descriptor(const DeclTy &D, Descriptor *Elem, bool IsTemporary, UnknownSize) : Source(D), ElemSize(Elem->getAllocSize() + sizeof(InlineDescriptor)), - Size(UnknownSizeMark), MDSize(0), AllocSize(alignof(void *)), - ElemDesc(Elem), IsConst(true), IsMutable(false), IsTemporary(IsTemporary), - IsArray(true), CtorFn(ctorArrayDesc), DtorFn(dtorArrayDesc), - MoveFn(moveArrayDesc) { + Size(UnknownSizeMark), MDSize(0), + AllocSize(alignof(void *) + sizeof(InitMapPtr)), ElemDesc(Elem), + IsConst(true), IsMutable(false), IsTemporary(IsTemporary), IsArray(true), + CtorFn(ctorArrayDesc), DtorFn(dtorArrayDesc), MoveFn(moveArrayDesc) { assert(Source && "Missing source"); } @@ -290,6 +296,13 @@ Descriptor::Descriptor(const DeclTy &D, Record *R, MetadataSize MD, assert(Source && "Missing source"); } +Descriptor::Descriptor(const DeclTy &D, MetadataSize MD) + : Source(D), ElemSize(1), Size(ElemSize), MDSize(MD.value_or(0)), + AllocSize(Size + MDSize), ElemRecord(nullptr), IsConst(true), + IsMutable(false), IsTemporary(false), IsDummy(true) { + assert(Source && "Missing source"); +} + QualType Descriptor::getType() const { if (auto *E = asExpr()) return E->getType(); @@ -314,21 +327,12 @@ SourceLocation Descriptor::getLocation() const { llvm_unreachable("Invalid descriptor type"); } -InitMap::InitMap(unsigned N) : UninitFields(N) { - std::fill_n(data(), (N + PER_FIELD - 1) / PER_FIELD, 0); -} - -InitMap::T *InitMap::data() { - auto *Start = reinterpret_cast(this) + align(sizeof(InitMap)); - return reinterpret_cast(Start); +InitMap::InitMap(unsigned N) + : UninitFields(N), Data(std::make_unique(numFields(N))) { + std::fill_n(data(), numFields(N), 0); } -const InitMap::T *InitMap::data() const { - auto *Start = reinterpret_cast(this) + align(sizeof(InitMap)); - return reinterpret_cast(Start); -} - -bool InitMap::initialize(unsigned I) { +bool InitMap::initializeElement(unsigned I) { unsigned Bucket = I / PER_FIELD; T Mask = T(1) << (I % PER_FIELD); if (!(data()[Bucket] & Mask)) { @@ -338,13 +342,7 @@ bool InitMap::initialize(unsigned I) { return UninitFields == 0; } -bool InitMap::isInitialized(unsigned I) const { +bool InitMap::isElementInitialized(unsigned I) const { unsigned Bucket = I / PER_FIELD; return data()[Bucket] & (T(1) << (I % PER_FIELD)); } - -InitMap *InitMap::allocate(unsigned N) { - const size_t NumFields = ((N + PER_FIELD - 1) / PER_FIELD); - const size_t Size = align(sizeof(InitMap)) + NumFields * PER_FIELD; - return new (malloc(Size)) InitMap(N); -} diff --git a/clang/lib/AST/Interp/Descriptor.h b/clang/lib/AST/Interp/Descriptor.h index 55a754c3505cc..8135f3d12f703 100644 --- a/clang/lib/AST/Interp/Descriptor.h +++ b/clang/lib/AST/Interp/Descriptor.h @@ -20,10 +20,12 @@ namespace clang { namespace interp { class Block; class Record; +struct InitMap; struct Descriptor; enum PrimType : unsigned; using DeclTy = llvm::PointerUnion; +using InitMapPtr = std::optional>>; /// Invoked whenever a block is created. The constructor method fills in the /// inline descriptors of all fields and array elements. It also initializes @@ -70,7 +72,7 @@ struct InlineDescriptor { /// Flag indicating if the field is mutable (if in a record). unsigned IsFieldMutable : 1; - Descriptor *Desc; + const Descriptor *Desc; }; /// Describes a memory block created by an allocation site. @@ -82,7 +84,7 @@ struct Descriptor final { const unsigned ElemSize; /// Size of the storage, in host bytes. const unsigned Size; - // Size of the metadata. + /// Size of the metadata. const unsigned MDSize; /// Size of the allocation (storage + metadata), in host bytes. const unsigned AllocSize; @@ -100,7 +102,7 @@ struct Descriptor final { /// Pointer to the record, if block contains records. Record *const ElemRecord = nullptr; /// Descriptor of the array element. - Descriptor *const ElemDesc = nullptr; + const Descriptor *const ElemDesc = nullptr; /// Flag indicating if the block is mutable. const bool IsConst = false; /// Flag indicating if a field is mutable. @@ -109,6 +111,8 @@ struct Descriptor final { const bool IsTemporary = false; /// Flag indicating if the block is an array. const bool IsArray = false; + /// Flag indicating if this is a dummy descriptor. + const bool IsDummy = false; /// Storage management methods. const BlockCtorFn CtorFn = nullptr; @@ -127,7 +131,7 @@ struct Descriptor final { Descriptor(const DeclTy &D, PrimType Type, bool IsTemporary, UnknownSize); /// Allocates a descriptor for an array of composites. - Descriptor(const DeclTy &D, Descriptor *Elem, MetadataSize MD, + Descriptor(const DeclTy &D, const Descriptor *Elem, MetadataSize MD, unsigned NumElems, bool IsConst, bool IsTemporary, bool IsMutable); /// Allocates a descriptor for an array of composites of unknown size. @@ -137,6 +141,8 @@ struct Descriptor final { Descriptor(const DeclTy &D, Record *R, MetadataSize MD, bool IsConst, bool IsTemporary, bool IsMutable); + Descriptor(const DeclTy &D, MetadataSize MD); + QualType getType() const; QualType getElemQualType() const; SourceLocation getLocation() const; @@ -190,12 +196,11 @@ struct Descriptor final { bool isArray() const { return IsArray; } /// Checks if the descriptor is of a record. bool isRecord() const { return !IsArray && ElemRecord; } + /// Checks if this is a dummy descriptor. + bool isDummy() const { return IsDummy; } }; /// Bitfield tracking the initialisation status of elements of primitive arrays. -/// A pointer to this is embedded at the end of all primitive arrays. -/// If the map was not yet created and nothing was initialized, the pointer to -/// this structure is 0. If the object was fully initialized, the pointer is -1. struct InitMap final { private: /// Type packing bits. @@ -203,26 +208,29 @@ struct InitMap final { /// Bits stored in a single field. static constexpr uint64_t PER_FIELD = sizeof(T) * CHAR_BIT; +public: /// Initializes the map with no fields set. - InitMap(unsigned N); + explicit InitMap(unsigned N); + +private: + friend class Pointer; /// Returns a pointer to storage. - T *data(); - const T *data() const; + T *data() { return Data.get(); } + const T *data() const { return Data.get(); } -public: /// Initializes an element. Returns true when object if fully initialized. - bool initialize(unsigned I); + bool initializeElement(unsigned I); /// Checks if an element was initialized. - bool isInitialized(unsigned I) const; - - /// Allocates a map holding N elements. - static InitMap *allocate(unsigned N); + bool isElementInitialized(unsigned I) const; -private: - /// Number of fields initialized. + static constexpr size_t numFields(unsigned N) { + return (N + PER_FIELD - 1) / PER_FIELD; + } + /// Number of fields not initialized. unsigned UninitFields; + std::unique_ptr Data; }; } // namespace interp diff --git a/clang/lib/AST/Interp/EvalEmitter.cpp b/clang/lib/AST/Interp/EvalEmitter.cpp index f46ef1067cf52..9bc42057c5f57 100644 --- a/clang/lib/AST/Interp/EvalEmitter.cpp +++ b/clang/lib/AST/Interp/EvalEmitter.cpp @@ -25,6 +25,14 @@ EvalEmitter::EvalEmitter(Context &Ctx, Program &P, State &Parent, new InterpFrame(S, /*Func=*/nullptr, /*Caller=*/nullptr, CodePtr()); } +EvalEmitter::~EvalEmitter() { + for (auto &[K, V] : Locals) { + Block *B = reinterpret_cast(V.get()); + if (B->isInitialized()) + B->invokeDtor(); + } +} + llvm::Expected EvalEmitter::interpretExpr(const Expr *E) { if (this->visitExpr(E)) return true; @@ -177,6 +185,12 @@ bool EvalEmitter::emitRetValue(const SourceInfo &Info) { } return Ok; } + + if (Ty->isIncompleteArrayType()) { + R = APValue(APValue::UninitArray(), 0, 0); + return true; + } + if (const auto *AT = Ty->getAsArrayTypeUnsafe()) { const size_t NumElems = Ptr.getNumElems(); QualType ElemTy = AT->getElementType(); diff --git a/clang/lib/AST/Interp/EvalEmitter.h b/clang/lib/AST/Interp/EvalEmitter.h index 1128e0fb09f0d..5a9be18c34a03 100644 --- a/clang/lib/AST/Interp/EvalEmitter.h +++ b/clang/lib/AST/Interp/EvalEmitter.h @@ -40,7 +40,7 @@ class EvalEmitter : public SourceMapper { EvalEmitter(Context &Ctx, Program &P, State &Parent, InterpStack &Stk, APValue &Result); - virtual ~EvalEmitter() {} + virtual ~EvalEmitter(); /// Define a label. void emitLabel(LabelTy Label); diff --git a/clang/lib/AST/Interp/Function.cpp b/clang/lib/AST/Interp/Function.cpp index 0b7cfc4e28883..357aff7fe6229 100644 --- a/clang/lib/AST/Interp/Function.cpp +++ b/clang/lib/AST/Interp/Function.cpp @@ -24,7 +24,7 @@ Function::Function(Program &P, const FunctionDecl *F, unsigned ArgSize, : P(P), Loc(F->getBeginLoc()), F(F), ArgSize(ArgSize), ParamTypes(std::move(ParamTypes)), Params(std::move(Params)), ParamOffsets(std::move(ParamOffsets)), HasThisPointer(HasThisPointer), - HasRVO(HasRVO) {} + HasRVO(HasRVO), Variadic(F->isVariadic()) {} Function::ParamDescriptor Function::getParamDescriptor(unsigned Offset) const { auto It = Params.find(Offset); diff --git a/clang/lib/AST/Interp/Function.h b/clang/lib/AST/Interp/Function.h index b93477c56346a..be9b1733635f7 100644 --- a/clang/lib/AST/Interp/Function.h +++ b/clang/lib/AST/Interp/Function.h @@ -173,6 +173,8 @@ class Function final { /// Checks if the function is defined. bool isDefined() const { return Defined; } + bool isVariadic() const { return Variadic; } + unsigned getBuiltinID() const { return F->getBuiltinID(); } bool isBuiltin() const { return F->getBuiltinID() != 0; } @@ -251,6 +253,7 @@ class Function final { /// If we've already compiled the function's body. bool HasBody = false; bool Defined = false; + bool Variadic = false; public: /// Dumps the disassembled bytecode to \c llvm::errs(). diff --git a/clang/lib/AST/Interp/IntegralAP.h b/clang/lib/AST/Interp/IntegralAP.h index 45e5b49546270..9aefea6d0c47e 100644 --- a/clang/lib/AST/Interp/IntegralAP.h +++ b/clang/lib/AST/Interp/IntegralAP.h @@ -35,10 +35,18 @@ template class IntegralAP final { friend IntegralAP; APInt V; - template static T truncateCast(const APInt &V) { + template + static T truncateCast(const APInt &V) { constexpr unsigned BitSize = sizeof(T) * 8; - if (BitSize >= V.getBitWidth()) - return std::is_signed_v ? V.getSExtValue() : V.getZExtValue(); + if (BitSize >= V.getBitWidth()) { + APInt Extended; + if constexpr (InputSigned) + Extended = V.sext(BitSize); + else + Extended = V.zext(BitSize); + return std::is_signed_v ? Extended.getSExtValue() + : Extended.getZExtValue(); + } return std::is_signed_v ? V.trunc(BitSize).getSExtValue() : V.trunc(BitSize).getZExtValue(); @@ -80,15 +88,10 @@ template class IntegralAP final { return V.ult(RHS.V); } - explicit operator bool() const { return !V.isZero(); } - explicit operator int8_t() const { return truncateCast(V); } - explicit operator uint8_t() const { return truncateCast(V); } - explicit operator int16_t() const { return truncateCast(V); } - explicit operator uint16_t() const { return truncateCast(V); } - explicit operator int32_t() const { return truncateCast(V); } - explicit operator uint32_t() const { return truncateCast(V); } - explicit operator int64_t() const { return truncateCast(V); } - explicit operator uint64_t() const { return truncateCast(V); } + template >> + explicit operator Ty() const { + return truncateCast(V); + } template static IntegralAP from(T Value, unsigned NumBits = 0) { assert(NumBits > 0); @@ -124,7 +127,7 @@ template class IntegralAP final { bool isNegative() const { return !V.isNonNegative(); } bool isMin() const { return V.isMinValue(); } bool isMax() const { return V.isMaxValue(); } - static bool isSigned() { return Signed; } + static constexpr bool isSigned() { return Signed; } bool isMinusOne() const { return Signed && V == -1; } unsigned countLeadingZeros() const { return V.countl_zero(); } diff --git a/clang/lib/AST/Interp/Interp.cpp b/clang/lib/AST/Interp/Interp.cpp index a4d6844ebe617..144b674451e35 100644 --- a/clang/lib/AST/Interp/Interp.cpp +++ b/clang/lib/AST/Interp/Interp.cpp @@ -121,18 +121,47 @@ static bool CheckGlobal(InterpState &S, CodePtr OpPC, const Pointer &Ptr) { namespace clang { namespace interp { +static void popArg(InterpState &S, const Expr *Arg) { + PrimType Ty = S.getContext().classify(Arg->getType()).value_or(PT_Ptr); + TYPE_SWITCH(Ty, S.Stk.discard()); +} + +void cleanupAfterFunctionCall(InterpState &S, CodePtr OpPC) { + assert(S.Current); + const Function *CurFunc = S.Current->getFunction(); + assert(CurFunc); + + // Certain builtin functions are declared as func-name(...), so the + // parameters are checked in Sema and only available through the CallExpr. + // The interp::Function we create for them has 0 parameters, so we need to + // remove them from the stack by checking the CallExpr. + // FIXME: This is potentially just a special case and could be handled more + // generally with the code just below? + if (CurFunc->needsRuntimeArgPop(S.getCtx())) { + const auto *CE = cast(S.Current->getExpr(OpPC)); + for (int32_t I = CE->getNumArgs() - 1; I >= 0; --I) { + popArg(S, CE->getArg(I)); + } + return; + } -bool popBuiltinArgs(InterpState &S, CodePtr OpPC) { - assert(S.Current && S.Current->getFunction()->needsRuntimeArgPop(S.getCtx())); - const Expr *E = S.Current->getExpr(OpPC); - assert(isa(E)); - const CallExpr *CE = cast(E); - for (int32_t I = CE->getNumArgs() - 1; I >= 0; --I) { - const Expr *A = CE->getArg(I); - PrimType Ty = S.getContext().classify(A->getType()).value_or(PT_Ptr); - TYPE_SWITCH(Ty, S.Stk.discard()); + if (S.Current->Caller && CurFunc->isVariadic()) { + // CallExpr we're look for is at the return PC of the current function, i.e. + // in the caller. + // This code path should be executed very rarely. + const auto *CE = + cast(S.Current->Caller->getExpr(S.Current->getRetPC())); + unsigned FixedParams = CurFunc->getNumParams(); + int32_t ArgsToPop = CE->getNumArgs() - FixedParams; + assert(ArgsToPop >= 0); + for (int32_t I = ArgsToPop - 1; I >= 0; --I) { + const Expr *A = CE->getArg(FixedParams + I); + popArg(S, A); + } } - return true; + // And in any case, remove the fixed parameters (the non-variadic ones) + // at the end. + S.Current->popArgs(); } bool CheckExtern(InterpState &S, CodePtr OpPC, const Pointer &Ptr) { @@ -186,6 +215,10 @@ bool CheckLive(InterpState &S, CodePtr OpPC, const Pointer &Ptr, return true; } +bool CheckDummy(InterpState &S, CodePtr OpPC, const Pointer &Ptr) { + return !Ptr.isZero() && !Ptr.isDummy(); +} + bool CheckNull(InterpState &S, CodePtr OpPC, const Pointer &Ptr, CheckSubobjectKind CSK) { if (!Ptr.isZero()) @@ -268,6 +301,8 @@ bool CheckInitialized(InterpState &S, CodePtr OpPC, const Pointer &Ptr, } bool CheckLoad(InterpState &S, CodePtr OpPC, const Pointer &Ptr) { + if (!CheckDummy(S, OpPC, Ptr)) + return false; if (!CheckLive(S, OpPC, Ptr, AK_Read)) return false; if (!CheckExtern(S, OpPC, Ptr)) @@ -404,7 +439,8 @@ bool CheckPure(InterpState &S, CodePtr OpPC, const CXXMethodDecl *MD) { static void DiagnoseUninitializedSubobject(InterpState &S, const SourceInfo &SI, const FieldDecl *SubObjDecl) { assert(SubObjDecl && "Subobject declaration does not exist"); - S.FFDiag(SI, diag::note_constexpr_uninitialized) << SubObjDecl; + S.FFDiag(SI, diag::note_constexpr_uninitialized) + << /*(name)*/ 1 << SubObjDecl; S.Note(SubObjDecl->getLocation(), diag::note_constexpr_subobject_declared_here); } @@ -454,6 +490,8 @@ static bool CheckFieldsInitialized(InterpState &S, CodePtr OpPC, if (FieldType->isRecordType()) { Result &= CheckFieldsInitialized(S, OpPC, FieldPtr, FieldPtr.getRecord()); + } else if (FieldType->isIncompleteArrayType()) { + // Nothing to do here. } else if (FieldType->isArrayType()) { const auto *CAT = cast(FieldType->getAsArrayTypeUnsafe()); @@ -555,8 +593,12 @@ bool CheckDeclRef(InterpState &S, CodePtr OpPC, const DeclRefExpr *DR) { const SourceInfo &E = S.Current->getSource(OpPC); if (isa(D)) { - S.FFDiag(E, diag::note_constexpr_function_param_value_unknown) << D; - S.Note(D->getLocation(), diag::note_declared_at) << D->getSourceRange(); + if (S.getLangOpts().CPlusPlus11) { + S.FFDiag(E, diag::note_constexpr_function_param_value_unknown) << D; + S.Note(D->getLocation(), diag::note_declared_at) << D->getSourceRange(); + } else { + S.FFDiag(E); + } } else if (const auto *VD = dyn_cast(D)) { if (!VD->getType().isConstQualified()) { S.FFDiag(E, diff --git a/clang/lib/AST/Interp/Interp.h b/clang/lib/AST/Interp/Interp.h index 7ef1e344224a3..7dd415d6e4605 100644 --- a/clang/lib/AST/Interp/Interp.h +++ b/clang/lib/AST/Interp/Interp.h @@ -55,6 +55,10 @@ bool CheckArray(InterpState &S, CodePtr OpPC, const Pointer &Ptr); /// Checks if a pointer is live and accessible. bool CheckLive(InterpState &S, CodePtr OpPC, const Pointer &Ptr, AccessKinds AK); + +/// Checks if a pointer is a dummy pointer. +bool CheckDummy(InterpState &S, CodePtr OpPC, const Pointer &Ptr); + /// Checks if a pointer is null. bool CheckNull(InterpState &S, CodePtr OpPC, const Pointer &Ptr, CheckSubobjectKind CSK); @@ -200,8 +204,7 @@ enum class ArithOp { Add, Sub }; // Returning values //===----------------------------------------------------------------------===// -/// Pop arguments of builtins defined as func-name(...). -bool popBuiltinArgs(InterpState &S, CodePtr OpPC); +void cleanupAfterFunctionCall(InterpState &S, CodePtr OpPC); template ::T> bool Ret(InterpState &S, CodePtr &PC, APValue &Result) { @@ -221,16 +224,8 @@ bool Ret(InterpState &S, CodePtr &PC, APValue &Result) { assert(S.Current); assert(S.Current->getFrameOffset() == S.Stk.size() && "Invalid frame"); - if (!S.checkingPotentialConstantExpression() || S.Current->Caller) { - // Certain builtin functions are declared as func-name(...), so the - // parameters are checked in Sema and only available through the CallExpr. - // The interp::Function we create for them has 0 parameters, so we need to - // remove them from the stack by checking the CallExpr. - if (S.Current->getFunction()->needsRuntimeArgPop(S.getCtx())) - popBuiltinArgs(S, PC); - else - S.Current->popArgs(); - } + if (!S.checkingPotentialConstantExpression() || S.Current->Caller) + cleanupAfterFunctionCall(S, PC); if (InterpFrame *Caller = S.Current->Caller) { PC = S.Current->getRetPC(); @@ -248,8 +243,9 @@ bool Ret(InterpState &S, CodePtr &PC, APValue &Result) { inline bool RetVoid(InterpState &S, CodePtr &PC, APValue &Result) { assert(S.Current->getFrameOffset() == S.Stk.size() && "Invalid frame"); + if (!S.checkingPotentialConstantExpression() || S.Current->Caller) - S.Current->popArgs(); + cleanupAfterFunctionCall(S, PC); if (InterpFrame *Caller = S.Current->Caller) { PC = S.Current->getRetPC(); @@ -1159,7 +1155,7 @@ inline bool GetPtrGlobal(InterpState &S, CodePtr OpPC, uint32_t I) { /// 2) Pushes Pointer.atField(Off) on the stack inline bool GetPtrField(InterpState &S, CodePtr OpPC, uint32_t Off) { const Pointer &Ptr = S.Stk.pop(); - if (!CheckNull(S, OpPC, Ptr, CSK_Field)) + if (S.inConstantContext() && !CheckNull(S, OpPC, Ptr, CSK_Field)) return false; if (!CheckExtern(S, OpPC, Ptr)) return false; @@ -1423,8 +1419,9 @@ bool OffsetHelper(InterpState &S, CodePtr OpPC, const T &Offset, // Compute the largest index into the array. T MaxIndex = T::from(Ptr.getNumElems(), Offset.bitWidth()); + bool Invalid = false; // Helper to report an invalid offset, computed as APSInt. - auto InvalidOffset = [&]() { + auto DiagInvalidOffset = [&]() -> void { const unsigned Bits = Offset.bitWidth(); APSInt APOffset(Offset.toAPSInt().extend(Bits + 2), false); APSInt APIndex(Index.toAPSInt().extend(Bits + 2), false); @@ -1434,28 +1431,31 @@ bool OffsetHelper(InterpState &S, CodePtr OpPC, const T &Offset, << NewIndex << /*array*/ static_cast(!Ptr.inArray()) << static_cast(MaxIndex); - return false; + Invalid = true; }; T MaxOffset = T::from(MaxIndex - Index, Offset.bitWidth()); if constexpr (Op == ArithOp::Add) { // If the new offset would be negative, bail out. if (Offset.isNegative() && (Offset.isMin() || -Offset > Index)) - return InvalidOffset(); + DiagInvalidOffset(); // If the new offset would be out of bounds, bail out. if (Offset.isPositive() && Offset > MaxOffset) - return InvalidOffset(); + DiagInvalidOffset(); } else { // If the new offset would be negative, bail out. if (Offset.isPositive() && Index < Offset) - return InvalidOffset(); + DiagInvalidOffset(); // If the new offset would be out of bounds, bail out. if (Offset.isNegative() && (Offset.isMin() || -Offset > MaxOffset)) - return InvalidOffset(); + DiagInvalidOffset(); } + if (Invalid && !Ptr.isDummy()) + return false; + // Offset is valid - compute it on unsigned. int64_t WideIndex = static_cast(Index); int64_t WideOffset = static_cast(Offset); @@ -1810,17 +1810,37 @@ inline bool ArrayElemPtr(InterpState &S, CodePtr OpPC) { const T &Offset = S.Stk.pop(); const Pointer &Ptr = S.Stk.peek(); + if (!CheckArray(S, OpPC, Ptr)) + return false; + if (!OffsetHelper(S, OpPC, Offset, Ptr)) return false; return NarrowPtr(S, OpPC); } +/// Just takes a pointer and checks if its' an incomplete +/// array type. +inline bool ArrayDecay(InterpState &S, CodePtr OpPC) { + const Pointer &Ptr = S.Stk.peek(); + + if (!Ptr.isUnknownSizeArray()) + return true; + + const SourceInfo &E = S.Current->getSource(OpPC); + S.FFDiag(E, diag::note_constexpr_unsupported_unsized_array); + + return false; +} + template ::T> inline bool ArrayElemPtrPop(InterpState &S, CodePtr OpPC) { const T &Offset = S.Stk.pop(); const Pointer &Ptr = S.Stk.pop(); + if (!CheckArray(S, OpPC, Ptr)) + return false; + if (!OffsetHelper(S, OpPC, Offset, Ptr)) return false; diff --git a/clang/lib/AST/Interp/InterpBlock.h b/clang/lib/AST/Interp/InterpBlock.h index 5112108e6f010..9d0c4859fd06c 100644 --- a/clang/lib/AST/Interp/InterpBlock.h +++ b/clang/lib/AST/Interp/InterpBlock.h @@ -49,11 +49,11 @@ enum PrimType : unsigned; class Block final { public: /// Creates a new block. - Block(const std::optional &DeclID, Descriptor *Desc, + Block(const std::optional &DeclID, const Descriptor *Desc, bool IsStatic = false, bool IsExtern = false) : DeclID(DeclID), IsStatic(IsStatic), IsExtern(IsExtern), Desc(Desc) {} - Block(Descriptor *Desc, bool IsStatic = false, bool IsExtern = false) + Block(const Descriptor *Desc, bool IsStatic = false, bool IsExtern = false) : DeclID((unsigned)-1), IsStatic(IsStatic), IsExtern(IsExtern), Desc(Desc) {} @@ -71,6 +71,7 @@ class Block final { unsigned getSize() const { return Desc->getAllocSize(); } /// Returns the declaration ID. std::optional getDeclID() const { return DeclID; } + bool isInitialized() const { return IsInitialized; } /// Returns a pointer to the stored data. /// You are allowed to read Desc->getSize() bytes from this address. @@ -104,12 +105,14 @@ class Block final { if (Desc->CtorFn) Desc->CtorFn(this, data(), Desc->IsConst, Desc->IsMutable, /*isActive=*/true, Desc); + IsInitialized = true; } /// Invokes the Destructor. void invokeDtor() { if (Desc->DtorFn) Desc->DtorFn(this, data(), Desc); + IsInitialized = false; } protected: @@ -117,8 +120,8 @@ class Block final { friend class DeadBlock; friend class InterpState; - Block(Descriptor *Desc, bool IsExtern, bool IsStatic, bool IsDead) - : IsStatic(IsStatic), IsExtern(IsExtern), IsDead(true), Desc(Desc) {} + Block(const Descriptor *Desc, bool IsExtern, bool IsStatic, bool IsDead) + : IsStatic(IsStatic), IsExtern(IsExtern), IsDead(true), Desc(Desc) {} /// Deletes a dead block at the end of its lifetime. void cleanup(); @@ -139,10 +142,14 @@ class Block final { bool IsStatic = false; /// Flag indicating if the block is an extern. bool IsExtern = false; - /// Flag indicating if the pointer is dead. + /// Flag indicating if the pointer is dead. This is only ever + /// set once, when converting the Block to a DeadBlock. bool IsDead = false; + /// Flag indicating if the block contents have been initialized + /// via invokeCtor. + bool IsInitialized = false; /// Pointer to the stack slot descriptor. - Descriptor *Desc; + const Descriptor *Desc; }; /// Descriptor for a dead block. diff --git a/clang/lib/AST/Interp/InterpBuiltin.cpp b/clang/lib/AST/Interp/InterpBuiltin.cpp index 7552c1b88cff6..e329794cb7924 100644 --- a/clang/lib/AST/Interp/InterpBuiltin.cpp +++ b/clang/lib/AST/Interp/InterpBuiltin.cpp @@ -152,6 +152,9 @@ static bool interp__builtin_strlen(InterpState &S, CodePtr OpPC, if (!CheckLive(S, OpPC, StrPtr, AK_Read)) return false; + if (!CheckDummy(S, OpPC, StrPtr)) + return false; + assert(StrPtr.getFieldDesc()->isPrimitiveArray()); size_t Len = 0; diff --git a/clang/lib/AST/Interp/InterpFrame.cpp b/clang/lib/AST/Interp/InterpFrame.cpp index 49db83a965ab0..b06923114c7a2 100644 --- a/clang/lib/AST/Interp/InterpFrame.cpp +++ b/clang/lib/AST/Interp/InterpFrame.cpp @@ -72,6 +72,19 @@ InterpFrame::InterpFrame(InterpState &S, const Function *Func, CodePtr RetPC) InterpFrame::~InterpFrame() { for (auto &Param : Params) S.deallocate(reinterpret_cast(Param.second.get())); + + // When destroying the InterpFrame, call the Dtor for all block + // that haven't been destroyed via a destroy() op yet. + // This happens when the execution is interruped midway-through. + if (Func) { + for (auto &Scope : Func->scopes()) { + for (auto &Local : Scope.locals()) { + Block *B = localBlock(Local.Offset); + if (B->isInitialized()) + B->invokeDtor(); + } + } + } } void InterpFrame::destroy(unsigned Idx) { diff --git a/clang/lib/AST/Interp/InterpState.cpp b/clang/lib/AST/Interp/InterpState.cpp index 4f050baea39e7..2cb87ef07fe58 100644 --- a/clang/lib/AST/Interp/InterpState.cpp +++ b/clang/lib/AST/Interp/InterpState.cpp @@ -65,9 +65,9 @@ void InterpState::deallocate(Block *B) { std::memcpy(D->rawData(), B->rawData(), Desc->getMetadataSize()); } + // We moved the contents over to the DeadBlock. + B->IsInitialized = false; } else { - // Free storage, if necessary. - if (Desc->DtorFn) - Desc->DtorFn(B, B->data(), Desc); + B->invokeDtor(); } } diff --git a/clang/lib/AST/Interp/Opcodes.td b/clang/lib/AST/Interp/Opcodes.td index e1e7e5e2efbb0..69068e87d5720 100644 --- a/clang/lib/AST/Interp/Opcodes.td +++ b/clang/lib/AST/Interp/Opcodes.td @@ -687,3 +687,5 @@ def InvalidCast : Opcode { def InvalidDeclRef : Opcode { let Args = [ArgDeclRef]; } + +def ArrayDecay : Opcode; diff --git a/clang/lib/AST/Interp/Pointer.cpp b/clang/lib/AST/Interp/Pointer.cpp index e04d29b8bd81b..e979b99b0fdd0 100644 --- a/clang/lib/AST/Interp/Pointer.cpp +++ b/clang/lib/AST/Interp/Pointer.cpp @@ -94,7 +94,7 @@ APValue Pointer::toAPValue() const { Offset = CharUnits::Zero(); } else { // Build the lvalue base from the block. - Descriptor *Desc = getDeclDesc(); + const Descriptor *Desc = getDeclDesc(); if (auto *VD = Desc->asValueDecl()) Base = VD; else if (auto *E = Desc->asExpr()) @@ -164,13 +164,16 @@ bool Pointer::isInitialized() const { if (Desc->isPrimitiveArray()) { if (isStatic() && Base == 0) return true; - // Primitive array field are stored in a bitset. - InitMap *Map = getInitMap(); - if (!Map) + + InitMapPtr &IM = getInitMap(); + + if (!IM) return false; - if (Map == (InitMap *)-1) + + if (IM->first) return true; - return Map->isInitialized(getIndex()); + + return IM->second->isElementInitialized(getIndex()); } // Field has its bit in an inline descriptor. @@ -187,15 +190,20 @@ void Pointer::initialize() const { if (isStatic() && Base == 0) return; - // Primitive array initializer. - InitMap *&Map = getInitMap(); - if (Map == (InitMap *)-1) + InitMapPtr &IM = getInitMap(); + if (!IM) + IM = + std::make_pair(false, std::make_shared(Desc->getNumElems())); + + assert(IM); + + // All initialized. + if (IM->first) return; - if (Map == nullptr) - Map = InitMap::allocate(Desc->getNumElems()); - if (Map->initialize(getIndex())) { - free(Map); - Map = (InitMap *)-1; + + if (IM->second->initializeElement(getIndex())) { + IM->first = true; + IM->second.reset(); } return; } diff --git a/clang/lib/AST/Interp/Pointer.h b/clang/lib/AST/Interp/Pointer.h index d5279e757f047..843bcad16b5d1 100644 --- a/clang/lib/AST/Interp/Pointer.h +++ b/clang/lib/AST/Interp/Pointer.h @@ -108,7 +108,7 @@ class Pointer { if (getFieldDesc()->ElemDesc) Off += sizeof(InlineDescriptor); else - Off += sizeof(InitMap *); + Off += sizeof(InitMapPtr); return Pointer(Pointee, Base, Base + Off); } @@ -147,7 +147,7 @@ class Pointer { if (inPrimitiveArray()) { if (Offset != Base) return *this; - return Pointer(Pointee, Base, Offset + sizeof(InitMap *)); + return Pointer(Pointee, Base, Offset + sizeof(InitMapPtr)); } // Pointer is to a field or array element - enter it. @@ -168,7 +168,7 @@ class Pointer { // Revert to an outer one-past-end pointer. unsigned Adjust; if (inPrimitiveArray()) - Adjust = sizeof(InitMap *); + Adjust = sizeof(InitMapPtr); else Adjust = sizeof(InlineDescriptor); return Pointer(Pointee, Base, Base + getSize() + Adjust); @@ -184,7 +184,8 @@ class Pointer { // Step into the containing array, if inside one. unsigned Next = Base - getInlineDesc()->Offset; - Descriptor *Desc = Next == 0 ? getDeclDesc() : getDescriptor(Next)->Desc; + const Descriptor *Desc = + Next == 0 ? getDeclDesc() : getDescriptor(Next)->Desc; if (!Desc->IsArray) return *this; return Pointer(Pointee, Next, Offset); @@ -198,7 +199,10 @@ class Pointer { bool isField() const { return Base != 0 && Base != RootPtrMark; } /// Accessor for information about the declaration site. - Descriptor *getDeclDesc() const { return Pointee->Desc; } + const Descriptor *getDeclDesc() const { + assert(Pointee); + return Pointee->Desc; + } SourceLocation getDeclLoc() const { return getDeclDesc()->getLocation(); } /// Returns a pointer to the object of which this pointer is a field. @@ -222,7 +226,7 @@ class Pointer { } /// Accessors for information about the innermost field. - Descriptor *getFieldDesc() const { + const Descriptor *getFieldDesc() const { if (Base == 0 || Base == RootPtrMark) return getDeclDesc(); return getInlineDesc()->Desc; @@ -257,7 +261,7 @@ class Pointer { if (getFieldDesc()->ElemDesc) Adjust = sizeof(InlineDescriptor); else - Adjust = sizeof(InitMap *); + Adjust = sizeof(InitMapPtr); } return Offset - Base - Adjust; } @@ -295,11 +299,17 @@ class Pointer { bool isUnion() const; /// Checks if the storage is extern. - bool isExtern() const { return Pointee->isExtern(); } + bool isExtern() const { return Pointee && Pointee->isExtern(); } /// Checks if the storage is static. - bool isStatic() const { return Pointee->isStatic(); } + bool isStatic() const { + assert(Pointee); + return Pointee->isStatic(); + } /// Checks if the storage is temporary. - bool isTemporary() const { return Pointee->isTemporary(); } + bool isTemporary() const { + assert(Pointee); + return Pointee->isTemporary(); + } /// Checks if the storage is a static temporary. bool isStaticTemporary() const { return isStatic() && isTemporary(); } @@ -313,6 +323,8 @@ class Pointer { bool isActive() const { return Base == 0 || getInlineDesc()->IsActive; } /// Checks if a structure is a base class. bool isBaseClass() const { return isField() && getInlineDesc()->IsBase; } + /// Checks if the pointer pointers to a dummy value. + bool isDummy() const { return getDeclDesc()->isDummy(); } /// Checks if an object or a subfield is mutable. bool isConst() const { @@ -320,7 +332,10 @@ class Pointer { } /// Returns the declaration ID. - std::optional getDeclID() const { return Pointee->getDeclID(); } + std::optional getDeclID() const { + assert(Pointee); + return Pointee->getDeclID(); + } /// Returns the byte offset from the start. unsigned getByteOffset() const { @@ -348,6 +363,8 @@ class Pointer { /// Checks if the index is one past end. bool isOnePastEnd() const { + if (!Pointee) + return false; return isElementPastEnd() || getSize() == getOffset(); } @@ -357,9 +374,10 @@ class Pointer { /// Dereferences the pointer, if it's live. template T &deref() const { assert(isLive() && "Invalid pointer"); + assert(Pointee); if (isArrayRoot()) return *reinterpret_cast(Pointee->rawData() + Base + - sizeof(InitMap *)); + sizeof(InitMapPtr)); return *reinterpret_cast(Pointee->rawData() + Offset); } @@ -367,7 +385,8 @@ class Pointer { /// Dereferences a primitive element. template T &elem(unsigned I) const { assert(I < getNumElems()); - return reinterpret_cast(Pointee->data() + sizeof(InitMap *))[I]; + assert(Pointee); + return reinterpret_cast(Pointee->data() + sizeof(InitMapPtr))[I]; } /// Initializes a field. @@ -418,6 +437,7 @@ class Pointer { private: friend class Block; friend class DeadBlock; + friend struct InitMap; Pointer(Block *Pointee, unsigned Base, unsigned Offset); @@ -427,13 +447,15 @@ class Pointer { /// Returns a descriptor at a given offset. InlineDescriptor *getDescriptor(unsigned Offset) const { assert(Offset != 0 && "Not a nested pointer"); + assert(Pointee); return reinterpret_cast(Pointee->rawData() + Offset) - 1; } - /// Returns a reference to the pointer which stores the initialization map. - InitMap *&getInitMap() const { - return *reinterpret_cast(Pointee->rawData() + Base); + /// Returns a reference to the InitMapPtr which stores the initialization map. + InitMapPtr &getInitMap() const { + assert(Pointee); + return *reinterpret_cast(Pointee->rawData() + Base); } /// The block the pointer is pointing to. diff --git a/clang/lib/AST/Interp/Program.cpp b/clang/lib/AST/Interp/Program.cpp index 65e170881e313..52e13398163ec 100644 --- a/clang/lib/AST/Interp/Program.cpp +++ b/clang/lib/AST/Interp/Program.cpp @@ -138,22 +138,23 @@ std::optional Program::getOrCreateGlobal(const ValueDecl *VD, return std::nullopt; } -std::optional Program::getOrCreateDummy(const ValueDecl *PD) { +std::optional Program::getOrCreateDummy(const ValueDecl *VD) { // Dedup blocks since they are immutable and pointers cannot be compared. - if (auto It = DummyParams.find(PD); - It != DummyParams.end()) + if (auto It = DummyParams.find(VD); It != DummyParams.end()) return It->second; - // Create a pointer to an incomplete array of the specified elements. - QualType ElemTy = PD->getType(); - QualType Ty = - Ctx.getASTContext().getIncompleteArrayType(ElemTy, ArrayType::Normal, 0); + // Create dummy descriptor. + Descriptor *Desc = allocateDescriptor(VD, std::nullopt); + // Allocate a block for storage. + unsigned I = Globals.size(); - if (auto Idx = createGlobal(PD, Ty, /*isStatic=*/true, /*isExtern=*/true)) { - DummyParams[PD] = *Idx; - return Idx; - } - return std::nullopt; + auto *G = new (Allocator, Desc->getAllocSize()) + Global(getCurrentDecl(), Desc, /*IsStatic=*/true, /*IsExtern=*/false); + G->block()->invokeCtor(); + + Globals.push_back(G); + DummyParams[VD] = I; + return I; } std::optional Program::createGlobal(const ValueDecl *VD, diff --git a/clang/lib/AST/Interp/Program.h b/clang/lib/AST/Interp/Program.h index d843fa06538f5..17342680102cf 100644 --- a/clang/lib/AST/Interp/Program.h +++ b/clang/lib/AST/Interp/Program.h @@ -83,7 +83,7 @@ class Program final { const Expr *Init = nullptr); /// Returns or creates a dummy value for unknown declarations. - std::optional getOrCreateDummy(const ValueDecl *PD); + std::optional getOrCreateDummy(const ValueDecl *VD); /// Creates a global and returns its index. std::optional createGlobal(const ValueDecl *VD, const Expr *E); diff --git a/clang/lib/AST/ItaniumMangle.cpp b/clang/lib/AST/ItaniumMangle.cpp index 27e8cbf6dc3f4..5efd23a38e739 100644 --- a/clang/lib/AST/ItaniumMangle.cpp +++ b/clang/lib/AST/ItaniumMangle.cpp @@ -2889,6 +2889,10 @@ static bool isTypeSubstitutable(Qualifiers Quals, const Type *Ty, return true; if (Ty->isOpenCLSpecificType()) return true; + // From Clang 18.0 we correctly treat SVE types as substitution candidates. + if (Ty->isSVESizelessBuiltinType() && + Ctx.getLangOpts().getClangABICompat() > LangOptions::ClangABI::Ver17) + return true; if (Ty->isBuiltinType()) return false; // Through to Clang 6.0, we accidentally treated undeduced auto types as @@ -3046,21 +3050,12 @@ void CXXNameMangler::mangleType(const BuiltinType *T) { // UNSUPPORTED: ::= De # IEEE 754r decimal floating point (128 bits) // UNSUPPORTED: ::= Df # IEEE 754r decimal floating point (32 bits) // ::= Dh # IEEE 754r half-precision floating point (16 bits) - // ::= DF _ # ISO/IEC TS 18661 binary floating point type _FloatN (N bits); + // ::= DF _ # ISO/IEC TS 18661 binary floating point + // type _FloatN (N bits); // ::= Di # char32_t // ::= Ds # char16_t // ::= Dn # std::nullptr_t (i.e., decltype(nullptr)) - // ::= [DS] DA # N1169 fixed-point [_Sat] T _Accum - // ::= [DS] DR # N1169 fixed-point [_Sat] T _Fract // ::= u # vendor extended type - // - // - // ::= s # short - // ::= t # unsigned short - // ::= i # plain - // ::= j # unsigned - // ::= l # long - // ::= m # unsigned long std::string type_name; // Normalize integer types as vendor extended types: // ui @@ -3205,77 +3200,30 @@ void CXXNameMangler::mangleType(const BuiltinType *T) { Out << "DF16_"; break; case BuiltinType::ShortAccum: - Out << "DAs"; - break; case BuiltinType::Accum: - Out << "DAi"; - break; case BuiltinType::LongAccum: - Out << "DAl"; - break; case BuiltinType::UShortAccum: - Out << "DAt"; - break; case BuiltinType::UAccum: - Out << "DAj"; - break; case BuiltinType::ULongAccum: - Out << "DAm"; - break; case BuiltinType::ShortFract: - Out << "DRs"; - break; case BuiltinType::Fract: - Out << "DRi"; - break; case BuiltinType::LongFract: - Out << "DRl"; - break; case BuiltinType::UShortFract: - Out << "DRt"; - break; case BuiltinType::UFract: - Out << "DRj"; - break; case BuiltinType::ULongFract: - Out << "DRm"; - break; case BuiltinType::SatShortAccum: - Out << "DSDAs"; - break; case BuiltinType::SatAccum: - Out << "DSDAi"; - break; case BuiltinType::SatLongAccum: - Out << "DSDAl"; - break; case BuiltinType::SatUShortAccum: - Out << "DSDAt"; - break; case BuiltinType::SatUAccum: - Out << "DSDAj"; - break; case BuiltinType::SatULongAccum: - Out << "DSDAm"; - break; case BuiltinType::SatShortFract: - Out << "DSDRs"; - break; case BuiltinType::SatFract: - Out << "DSDRi"; - break; case BuiltinType::SatLongFract: - Out << "DSDRl"; - break; case BuiltinType::SatUShortFract: - Out << "DSDRt"; - break; case BuiltinType::SatUFract: - Out << "DSDRj"; - break; case BuiltinType::SatULongFract: - Out << "DSDRm"; - break; + llvm_unreachable("Fixed point types are disabled for c++"); case BuiltinType::Half: Out << "Dh"; break; @@ -3372,9 +3320,16 @@ void CXXNameMangler::mangleType(const BuiltinType *T) { #define SVE_VECTOR_TYPE(InternalName, MangledName, Id, SingletonId, NumEls, \ ElBits, IsSigned, IsFP, IsBF) \ case BuiltinType::Id: \ - type_name = MangledName; \ - Out << (type_name == InternalName ? "u" : "") << type_name.size() \ - << type_name; \ + if (T->getKind() == BuiltinType::SveBFloat16 && \ + isCompatibleWith(LangOptions::ClangABI::Ver17)) { \ + /* Prior to Clang 18.0 we used this incorrect mangled name */ \ + type_name = "__SVBFloat16_t"; \ + Out << "u" << type_name.size() << type_name; \ + } else { \ + type_name = MangledName; \ + Out << (type_name == InternalName ? "u" : "") << type_name.size() \ + << type_name; \ + } \ break; #define SVE_PREDICATE_TYPE(InternalName, MangledName, Id, SingletonId, NumEls) \ case BuiltinType::Id: \ diff --git a/clang/lib/AST/JSONNodeDumper.cpp b/clang/lib/AST/JSONNodeDumper.cpp index beb07015f0bcb..25b94ec5616b1 100644 --- a/clang/lib/AST/JSONNodeDumper.cpp +++ b/clang/lib/AST/JSONNodeDumper.cpp @@ -315,12 +315,16 @@ std::string JSONNodeDumper::createPointerRepresentation(const void *Ptr) { llvm::json::Object JSONNodeDumper::createQualType(QualType QT, bool Desugar) { SplitQualType SQT = QT.split(); - llvm::json::Object Ret{{"qualType", QualType::getAsString(SQT, PrintPolicy)}}; + std::string SQTS = QualType::getAsString(SQT, PrintPolicy); + llvm::json::Object Ret{{"qualType", SQTS}}; if (Desugar && !QT.isNull()) { SplitQualType DSQT = QT.getSplitDesugaredType(); - if (DSQT != SQT) - Ret["desugaredQualType"] = QualType::getAsString(DSQT, PrintPolicy); + if (DSQT != SQT) { + std::string DSQTS = QualType::getAsString(DSQT, PrintPolicy); + if (DSQTS != SQTS) + Ret["desugaredQualType"] = DSQTS; + } if (const auto *TT = QT->getAs()) Ret["typeAliasDeclId"] = createPointerRepresentation(TT->getDecl()); } diff --git a/clang/lib/AST/OpenMPClause.cpp b/clang/lib/AST/OpenMPClause.cpp index b95b4fce180e7..4e19339a1361e 100644 --- a/clang/lib/AST/OpenMPClause.cpp +++ b/clang/lib/AST/OpenMPClause.cpp @@ -583,15 +583,17 @@ void OMPLinearClause::setUsedExprs(ArrayRef UE) { OMPLinearClause *OMPLinearClause::Create( const ASTContext &C, SourceLocation StartLoc, SourceLocation LParenLoc, OpenMPLinearClauseKind Modifier, SourceLocation ModifierLoc, - SourceLocation ColonLoc, SourceLocation EndLoc, ArrayRef VL, - ArrayRef PL, ArrayRef IL, Expr *Step, Expr *CalcStep, - Stmt *PreInit, Expr *PostUpdate) { + SourceLocation ColonLoc, SourceLocation StepModifierLoc, + SourceLocation EndLoc, ArrayRef VL, ArrayRef PL, + ArrayRef IL, Expr *Step, Expr *CalcStep, Stmt *PreInit, + Expr *PostUpdate) { // Allocate space for 5 lists (Vars, Inits, Updates, Finals), 2 expressions // (Step and CalcStep), list of used expression + step. void *Mem = C.Allocate(totalSizeToAlloc(5 * VL.size() + 2 + VL.size() + 1)); - OMPLinearClause *Clause = new (Mem) OMPLinearClause( - StartLoc, LParenLoc, Modifier, ModifierLoc, ColonLoc, EndLoc, VL.size()); + OMPLinearClause *Clause = + new (Mem) OMPLinearClause(StartLoc, LParenLoc, Modifier, ModifierLoc, + ColonLoc, StepModifierLoc, EndLoc, VL.size()); Clause->setVarRefs(VL); Clause->setPrivates(PL); Clause->setInits(IL); @@ -2207,16 +2209,20 @@ void OMPClausePrinter::VisitOMPInReductionClause(OMPInReductionClause *Node) { void OMPClausePrinter::VisitOMPLinearClause(OMPLinearClause *Node) { if (!Node->varlist_empty()) { OS << "linear"; + VisitOMPClauseList(Node, '('); + if (Node->getModifierLoc().isValid() || Node->getStep() != nullptr) { + OS << ": "; + } if (Node->getModifierLoc().isValid()) { - OS << '(' - << getOpenMPSimpleClauseTypeName(OMPC_linear, Node->getModifier()); + OS << getOpenMPSimpleClauseTypeName(OMPC_linear, Node->getModifier()); } - VisitOMPClauseList(Node, '('); - if (Node->getModifierLoc().isValid()) - OS << ')'; if (Node->getStep() != nullptr) { - OS << ": "; + if (Node->getModifierLoc().isValid()) { + OS << ", "; + } + OS << "step("; Node->getStep()->printPretty(OS, nullptr, Policy, 0); + OS << ")"; } OS << ")"; } diff --git a/clang/lib/AST/TextNodeDumper.cpp b/clang/lib/AST/TextNodeDumper.cpp index 15eb6c6191edf..ca609cf2d2060 100644 --- a/clang/lib/AST/TextNodeDumper.cpp +++ b/clang/lib/AST/TextNodeDumper.cpp @@ -692,13 +692,18 @@ void TextNodeDumper::dumpBareType(QualType T, bool Desugar) { ColorScope Color(OS, ShowColors, TypeColor); SplitQualType T_split = T.split(); - OS << "'" << QualType::getAsString(T_split, PrintPolicy) << "'"; + std::string T_str = QualType::getAsString(T_split, PrintPolicy); + OS << "'" << T_str << "'"; if (Desugar && !T.isNull()) { - // If the type is sugared, also dump a (shallow) desugared type. + // If the type is sugared, also dump a (shallow) desugared type when + // it is visibly different. SplitQualType D_split = T.getSplitDesugaredType(); - if (T_split != D_split) - OS << ":'" << QualType::getAsString(D_split, PrintPolicy) << "'"; + if (T_split != D_split) { + std::string D_str = QualType::getAsString(D_split, PrintPolicy); + if (T_str != D_str) + OS << ":'" << QualType::getAsString(D_split, PrintPolicy) << "'"; + } } } diff --git a/clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp b/clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp index 9f6984e1cf8f2..40de6cdf3a69e 100644 --- a/clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp +++ b/clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp @@ -145,26 +145,26 @@ Solver::Result DataflowAnalysisContext::querySolver( } bool DataflowAnalysisContext::flowConditionImplies(Atom Token, - const Formula &Val) { + const Formula &F) { // Returns true if and only if truth assignment of the flow condition implies - // that `Val` is also true. We prove whether or not this property holds by + // that `F` is also true. We prove whether or not this property holds by // reducing the problem to satisfiability checking. In other words, we attempt - // to show that assuming `Val` is false makes the constraints induced by the + // to show that assuming `F` is false makes the constraints induced by the // flow condition unsatisfiable. llvm::SetVector Constraints; Constraints.insert(&arena().makeAtomRef(Token)); - Constraints.insert(&arena().makeNot(Val)); + Constraints.insert(&arena().makeNot(F)); addTransitiveFlowConditionConstraints(Token, Constraints); return isUnsatisfiable(std::move(Constraints)); } -bool DataflowAnalysisContext::flowConditionIsTautology(Atom Token) { - // Returns true if and only if we cannot prove that the flow condition can - // ever be false. +bool DataflowAnalysisContext::flowConditionAllows(Atom Token, + const Formula &F) { llvm::SetVector Constraints; - Constraints.insert(&arena().makeNot(arena().makeAtomRef(Token))); + Constraints.insert(&arena().makeAtomRef(Token)); + Constraints.insert(&F); addTransitiveFlowConditionConstraints(Token, Constraints); - return isUnsatisfiable(std::move(Constraints)); + return isSatisfiable(std::move(Constraints)); } bool DataflowAnalysisContext::equivalentFormulas(const Formula &Val1, diff --git a/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp b/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp index 01c6cc69e2b9f..cf1e9eb7b1fd7 100644 --- a/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp +++ b/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp @@ -35,20 +35,6 @@ namespace dataflow { static constexpr int MaxCompositeValueDepth = 3; static constexpr int MaxCompositeValueSize = 1000; -/// Returns whether all declarations that `DeclToLoc1` and `DeclToLoc2` have in -/// common map to the same storage location in both maps. -bool declToLocConsistent( - const llvm::DenseMap &DeclToLoc1, - const llvm::DenseMap &DeclToLoc2) { - for (auto &Entry : DeclToLoc1) { - auto It = DeclToLoc2.find(Entry.first); - if (It != DeclToLoc2.end() && Entry.second != It->second) - return false; - } - - return true; -} - /// Returns a map consisting of key-value entries that are present in both maps. template llvm::DenseMap intersectDenseMaps(const llvm::DenseMap &Map1, @@ -662,7 +648,6 @@ Environment Environment::join(const Environment &EnvA, const Environment &EnvB, else JoinedEnv.ReturnLoc = nullptr; - assert(declToLocConsistent(EnvA.DeclToLoc, EnvB.DeclToLoc)); JoinedEnv.DeclToLoc = intersectDenseMaps(EnvA.DeclToLoc, EnvB.DeclToLoc); JoinedEnv.ExprToLoc = intersectDenseMaps(EnvA.ExprToLoc, EnvB.ExprToLoc); @@ -714,10 +699,7 @@ StorageLocation *Environment::getStorageLocation(const ValueDecl &D) const { return Loc; } -void Environment::removeDecl(const ValueDecl &D) { - assert(DeclToLoc.contains(&D)); - DeclToLoc.erase(&D); -} +void Environment::removeDecl(const ValueDecl &D) { DeclToLoc.erase(&D); } void Environment::setStorageLocation(const Expr &E, StorageLocation &Loc) { // `DeclRefExpr`s to builtin function types aren't glvalues, for some reason, @@ -947,12 +929,16 @@ StorageLocation &Environment::createObjectInternal(const ValueDecl *D, return Loc; } -void Environment::addToFlowCondition(const Formula &Val) { - DACtx->addFlowConditionConstraint(FlowConditionToken, Val); +void Environment::assume(const Formula &F) { + DACtx->addFlowConditionConstraint(FlowConditionToken, F); +} + +bool Environment::proves(const Formula &F) const { + return DACtx->flowConditionImplies(FlowConditionToken, F); } -bool Environment::flowConditionImplies(const Formula &Val) const { - return DACtx->flowConditionImplies(FlowConditionToken, Val); +bool Environment::allows(const Formula &F) const { + return DACtx->flowConditionAllows(FlowConditionToken, F); } void Environment::dump(raw_ostream &OS) const { diff --git a/clang/lib/Analysis/FlowSensitive/HTMLLogger.cpp b/clang/lib/Analysis/FlowSensitive/HTMLLogger.cpp index 8aef1d6f46089..8329367098b1d 100644 --- a/clang/lib/Analysis/FlowSensitive/HTMLLogger.cpp +++ b/clang/lib/Analysis/FlowSensitive/HTMLLogger.cpp @@ -114,11 +114,10 @@ class ModelDumper { // guaranteed true/false here is valuable and hard to determine by hand. if (auto *B = llvm::dyn_cast(&V)) { JOS.attribute("formula", llvm::to_string(B->formula())); - JOS.attribute( - "truth", Env.flowConditionImplies(B->formula()) ? "true" - : Env.flowConditionImplies(Env.arena().makeNot(B->formula())) - ? "false" - : "unknown"); + JOS.attribute("truth", Env.proves(B->formula()) ? "true" + : Env.proves(Env.arena().makeNot(B->formula())) + ? "false" + : "unknown"); } } void dump(const StorageLocation &L) { diff --git a/clang/lib/Analysis/FlowSensitive/Models/ChromiumCheckModel.cpp b/clang/lib/Analysis/FlowSensitive/Models/ChromiumCheckModel.cpp index 895f4ff04a172..f49087ababc44 100644 --- a/clang/lib/Analysis/FlowSensitive/Models/ChromiumCheckModel.cpp +++ b/clang/lib/Analysis/FlowSensitive/Models/ChromiumCheckModel.cpp @@ -59,7 +59,7 @@ bool ChromiumCheckModel::transfer(const CFGElement &Element, Environment &Env) { if (const auto *M = dyn_cast(Call->getDirectCallee())) { if (isCheckLikeMethod(CheckDecls, *M)) { // Mark this branch as unreachable. - Env.addToFlowCondition(Env.arena().makeLiteral(false)); + Env.assume(Env.arena().makeLiteral(false)); return true; } } diff --git a/clang/lib/Analysis/FlowSensitive/Models/UncheckedOptionalAccessModel.cpp b/clang/lib/Analysis/FlowSensitive/Models/UncheckedOptionalAccessModel.cpp index f61f26ff27804..55d0713639d90 100644 --- a/clang/lib/Analysis/FlowSensitive/Models/UncheckedOptionalAccessModel.cpp +++ b/clang/lib/Analysis/FlowSensitive/Models/UncheckedOptionalAccessModel.cpp @@ -413,7 +413,7 @@ bool isEmptyOptional(const Value &OptionalVal, const Environment &Env) { auto *HasValueVal = cast_or_null(OptionalVal.getProperty("has_value")); return HasValueVal != nullptr && - Env.flowConditionImplies(Env.arena().makeNot(HasValueVal->formula())); + Env.proves(Env.arena().makeNot(HasValueVal->formula())); } /// Returns true if and only if `OptionalVal` is initialized and known to be @@ -421,8 +421,7 @@ bool isEmptyOptional(const Value &OptionalVal, const Environment &Env) { bool isNonEmptyOptional(const Value &OptionalVal, const Environment &Env) { auto *HasValueVal = cast_or_null(OptionalVal.getProperty("has_value")); - return HasValueVal != nullptr && - Env.flowConditionImplies(HasValueVal->formula()); + return HasValueVal != nullptr && Env.proves(HasValueVal->formula()); } Value *getValueBehindPossiblePointer(const Expr &E, const Environment &Env) { @@ -490,8 +489,8 @@ void transferValueOrImpl( if (HasValueVal == nullptr) return; - Env.addToFlowCondition(ModelPred(Env, forceBoolValue(Env, *ValueOrPredExpr), - HasValueVal->formula())); + Env.assume(ModelPred(Env, forceBoolValue(Env, *ValueOrPredExpr), + HasValueVal->formula())); } void transferValueOrStringEmptyCall(const clang::Expr *ComparisonExpr, @@ -599,7 +598,7 @@ void transferAssignment(const CXXOperatorCallExpr *E, BoolValue &HasValueVal, LatticeTransferState &State) { assert(E->getNumArgs() > 0); - if (auto *Loc = cast( + if (auto *Loc = cast_or_null( State.Env.getStorageLocation(*E->getArg(0)))) { createOptionalValue(*Loc, HasValueVal, State.Env); @@ -717,8 +716,8 @@ void transferOptionalAndOptionalCmp(const clang::CXXOperatorCallExpr *CmpExpr, if (auto *RHasVal = getHasValue(Env, Env.getValue(*CmpExpr->getArg(1)))) { if (CmpExpr->getOperator() == clang::OO_ExclaimEqual) CmpValue = &A.makeNot(*CmpValue); - Env.addToFlowCondition(evaluateEquality(A, *CmpValue, LHasVal->formula(), - RHasVal->formula())); + Env.assume(evaluateEquality(A, *CmpValue, LHasVal->formula(), + RHasVal->formula())); } } @@ -729,7 +728,7 @@ void transferOptionalAndValueCmp(const clang::CXXOperatorCallExpr *CmpExpr, if (auto *HasVal = getHasValue(Env, Env.getValue(*E))) { if (CmpExpr->getOperator() == clang::OO_ExclaimEqual) CmpValue = &A.makeNot(*CmpValue); - Env.addToFlowCondition( + Env.assume( evaluateEquality(A, *CmpValue, HasVal->formula(), A.makeLiteral(true))); } } @@ -917,7 +916,7 @@ llvm::SmallVector diagnoseUnwrapCall(const Expr *ObjectExpr, if (auto *OptionalVal = getValueBehindPossiblePointer(*ObjectExpr, Env)) { auto *Prop = OptionalVal->getProperty("has_value"); if (auto *HasValueVal = cast_or_null(Prop)) { - if (Env.flowConditionImplies(HasValueVal->formula())) + if (Env.proves(HasValueVal->formula())) return {}; } } @@ -1004,14 +1003,13 @@ bool UncheckedOptionalAccessModel::merge(QualType Type, const Value &Val1, bool MustNonEmpty1 = isNonEmptyOptional(Val1, Env1); bool MustNonEmpty2 = isNonEmptyOptional(Val2, Env2); if (MustNonEmpty1 && MustNonEmpty2) - MergedEnv.addToFlowCondition(HasValueVal.formula()); + MergedEnv.assume(HasValueVal.formula()); else if ( // Only make the costly calls to `isEmptyOptional` if we got "unknown" // (false) for both calls to `isNonEmptyOptional`. !MustNonEmpty1 && !MustNonEmpty2 && isEmptyOptional(Val1, Env1) && isEmptyOptional(Val2, Env2)) - MergedEnv.addToFlowCondition( - MergedEnv.arena().makeNot(HasValueVal.formula())); + MergedEnv.assume(MergedEnv.arena().makeNot(HasValueVal.formula())); setHasValue(MergedVal, HasValueVal); return true; } diff --git a/clang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp b/clang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp index 72d807fc36705..e54fb2a01ddee 100644 --- a/clang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp +++ b/clang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp @@ -148,7 +148,7 @@ class TerminatorVisitor ConditionValue = false; } - Env.addToFlowCondition(Val->formula()); + Env.assume(Val->formula()); return {&Cond, ConditionValue}; } @@ -307,7 +307,7 @@ computeBlockInputState(const CFGBlock &Block, AnalysisContext &AC) { auto &StmtToBlock = AC.CFCtx.getStmtToBlock(); auto StmtBlock = StmtToBlock.find(Block.getTerminatorStmt()); assert(StmtBlock != StmtToBlock.end()); - llvm::erase_value(Preds, StmtBlock->getSecond()); + llvm::erase(Preds, StmtBlock->getSecond()); } } diff --git a/clang/lib/Analysis/UnsafeBufferUsage.cpp b/clang/lib/Analysis/UnsafeBufferUsage.cpp index 49cfa7c0d3e3b..e332a3609290a 100644 --- a/clang/lib/Analysis/UnsafeBufferUsage.cpp +++ b/clang/lib/Analysis/UnsafeBufferUsage.cpp @@ -8,7 +8,9 @@ #include "clang/Analysis/Analyses/UnsafeBufferUsage.h" #include "clang/AST/Decl.h" +#include "clang/AST/Expr.h" #include "clang/AST/RecursiveASTVisitor.h" +#include "clang/AST/StmtVisitor.h" #include "clang/ASTMatchers/ASTMatchFinder.h" #include "clang/Lex/Lexer.h" #include "clang/Lex/Preprocessor.h" @@ -22,6 +24,52 @@ using namespace llvm; using namespace clang; using namespace ast_matchers; +#ifndef NDEBUG +namespace { +class StmtDebugPrinter + : public ConstStmtVisitor { +public: + std::string VisitStmt(const Stmt *S) { return S->getStmtClassName(); } + + std::string VisitBinaryOperator(const BinaryOperator *BO) { + return "BinaryOperator(" + BO->getOpcodeStr().str() + ")"; + } + + std::string VisitUnaryOperator(const UnaryOperator *UO) { + return "UnaryOperator(" + UO->getOpcodeStr(UO->getOpcode()).str() + ")"; + } + + std::string VisitImplicitCastExpr(const ImplicitCastExpr *ICE) { + return "ImplicitCastExpr(" + std::string(ICE->getCastKindName()) + ")"; + } +}; + +// Returns a string of ancestor `Stmt`s of the given `DRE` in such a form: +// "DRE ==> parent-of-DRE ==> grandparent-of-DRE ==> ...". +static std::string getDREAncestorString(const DeclRefExpr *DRE, + ASTContext &Ctx) { + std::stringstream SS; + const Stmt *St = DRE; + StmtDebugPrinter StmtPriner; + + do { + SS << StmtPriner.Visit(St); + + DynTypedNodeList StParents = Ctx.getParents(*St); + + if (StParents.size() > 1) + return "unavailable due to multiple parents"; + if (StParents.size() == 0) + break; + St = StParents.begin()->get(); + if (St) + SS << " ==> "; + } while (St); + return SS.str(); +} +} // namespace +#endif /* NDEBUG */ + namespace clang::ast_matchers { // A `RecursiveASTVisitor` that traverses all descendants of a given node "n" // except for those belonging to a different callable of "n". @@ -2589,11 +2637,15 @@ void clang::checkUnsafeBufferUsage(const Decl *D, #ifndef NDEBUG auto AllUnclaimed = Tracker.getUnclaimedUses(it->first); for (auto UnclaimedDRE : AllUnclaimed) { - Handler.addDebugNoteForVar( - it->first, UnclaimedDRE->getBeginLoc(), - ("failed to produce fixit for '" + it->first->getNameAsString() + - "' : has an unclaimed use")); - } + std::string UnclaimedUseTrace = + getDREAncestorString(UnclaimedDRE, D->getASTContext()); + + Handler.addDebugNoteForVar( + it->first, UnclaimedDRE->getBeginLoc(), + ("failed to produce fixit for '" + it->first->getNameAsString() + + "' : has an unclaimed use\nThe unclaimed DRE trace: " + + UnclaimedUseTrace)); + } #endif it = FixablesForAllVars.byVar.erase(it); } else if (it->first->isInitCapture()) { diff --git a/clang/lib/Basic/IdentifierTable.cpp b/clang/lib/Basic/IdentifierTable.cpp index e5599d5455410..c4c5a6eeced28 100644 --- a/clang/lib/Basic/IdentifierTable.cpp +++ b/clang/lib/Basic/IdentifierTable.cpp @@ -512,63 +512,6 @@ unsigned llvm::DenseMapInfo::getHashValue(clang::Selector S) { return DenseMapInfo::getHashValue(S.getAsOpaquePtr()); } -namespace clang { - -/// One of these variable length records is kept for each -/// selector containing more than one keyword. We use a folding set -/// to unique aggregate names (keyword selectors in ObjC parlance). Access to -/// this class is provided strictly through Selector. -class alignas(IdentifierInfoAlignment) MultiKeywordSelector - : public detail::DeclarationNameExtra, - public llvm::FoldingSetNode { - MultiKeywordSelector(unsigned nKeys) : DeclarationNameExtra(nKeys) {} - -public: - // Constructor for keyword selectors. - MultiKeywordSelector(unsigned nKeys, IdentifierInfo **IIV) - : DeclarationNameExtra(nKeys) { - assert((nKeys > 1) && "not a multi-keyword selector"); - - // Fill in the trailing keyword array. - IdentifierInfo **KeyInfo = reinterpret_cast(this + 1); - for (unsigned i = 0; i != nKeys; ++i) - KeyInfo[i] = IIV[i]; - } - - // getName - Derive the full selector name and return it. - std::string getName() const; - - using DeclarationNameExtra::getNumArgs; - - using keyword_iterator = IdentifierInfo *const *; - - keyword_iterator keyword_begin() const { - return reinterpret_cast(this + 1); - } - - keyword_iterator keyword_end() const { - return keyword_begin() + getNumArgs(); - } - - IdentifierInfo *getIdentifierInfoForSlot(unsigned i) const { - assert(i < getNumArgs() && "getIdentifierInfoForSlot(): illegal index"); - return keyword_begin()[i]; - } - - static void Profile(llvm::FoldingSetNodeID &ID, keyword_iterator ArgTys, - unsigned NumArgs) { - ID.AddInteger(NumArgs); - for (unsigned i = 0; i != NumArgs; ++i) - ID.AddPointer(ArgTys[i]); - } - - void Profile(llvm::FoldingSetNodeID &ID) { - Profile(ID, keyword_begin(), getNumArgs()); - } -}; - -} // namespace clang. - bool Selector::isKeywordSelector(ArrayRef Names) const { assert(!Names.empty() && "must have >= 1 selector slots"); if (getNumArgs() != Names.size()) @@ -624,7 +567,7 @@ std::string MultiKeywordSelector::getName() const { } std::string Selector::getAsString() const { - if (InfoPtr == 0) + if (isNull()) return ""; if (getIdentifierInfoFlag() < MultiArg) { diff --git a/clang/lib/Basic/LangStandards.cpp b/clang/lib/Basic/LangStandards.cpp index af9cf4f273920..ab09c7221dda9 100644 --- a/clang/lib/Basic/LangStandards.cpp +++ b/clang/lib/Basic/LangStandards.cpp @@ -13,6 +13,39 @@ #include "llvm/TargetParser/Triple.h" using namespace clang; +StringRef clang::languageToString(Language L) { + switch (L) { + case Language::Unknown: + return "Unknown"; + case Language::Asm: + return "Asm"; + case Language::LLVM_IR: + return "LLVM IR"; + case Language::C: + return "C"; + case Language::CXX: + return "C++"; + case Language::ObjC: + return "Objective-C"; + case Language::ObjCXX: + return "Objective-C++"; + case Language::OpenCL: + return "OpenCL"; + case Language::OpenCLCXX: + return "OpenCLC++"; + case Language::CUDA: + return "CUDA"; + case Language::RenderScript: + return "RenderScript"; + case Language::HIP: + return "HIP"; + case Language::HLSL: + return "HLSL"; + } + + llvm_unreachable("unhandled language kind"); +} + #define LANGSTANDARD(id, name, lang, desc, features) \ static const LangStandard Lang_##id = {name, desc, features, Language::lang}; #include "clang/Basic/LangStandards.def" diff --git a/clang/lib/Basic/Module.cpp b/clang/lib/Basic/Module.cpp index 7879a11179b6d..cc2e5be98d32d 100644 --- a/clang/lib/Basic/Module.cpp +++ b/clang/lib/Basic/Module.cpp @@ -265,10 +265,10 @@ bool Module::fullModuleNameIs(ArrayRef nameParts) const { } OptionalDirectoryEntryRef Module::getEffectiveUmbrellaDir() const { - if (Umbrella && Umbrella.is()) - return Umbrella.get().getDir(); - if (Umbrella && Umbrella.is()) - return Umbrella.get(); + if (const auto *Hdr = std::get_if(&Umbrella)) + return Hdr->getDir(); + if (const auto *Dir = std::get_if(&Umbrella)) + return *Dir; return std::nullopt; } diff --git a/clang/lib/Basic/SourceManager.cpp b/clang/lib/Basic/SourceManager.cpp index c44ecacb3de3a..d627c233a3aa0 100644 --- a/clang/lib/Basic/SourceManager.cpp +++ b/clang/lib/Basic/SourceManager.cpp @@ -605,7 +605,7 @@ FileID SourceManager::createFileIDImpl(ContentCache &File, StringRef Filename, unsigned FileSize = File.getSize(); if (!(NextLocalOffset + FileSize + 1 > NextLocalOffset && NextLocalOffset + FileSize + 1 <= CurrentLoadedOffset)) { - Diag.Report(IncludePos, diag::err_include_too_large); + Diag.Report(IncludePos, diag::err_sloc_space_too_large); noteSLocAddressSpaceUsage(Diag); return FileID(); } @@ -663,10 +663,16 @@ SourceManager::createExpansionLocImpl(const ExpansionInfo &Info, return SourceLocation::getMacroLoc(LoadedOffset); } LocalSLocEntryTable.push_back(SLocEntry::get(NextLocalOffset, Info)); - // FIXME: Produce a proper diagnostic for this case. - assert(NextLocalOffset + Length + 1 > NextLocalOffset && - NextLocalOffset + Length + 1 <= CurrentLoadedOffset && - "Ran out of source locations!"); + if (NextLocalOffset + Length + 1 <= NextLocalOffset || + NextLocalOffset + Length + 1 > CurrentLoadedOffset) { + Diag.Report(SourceLocation(), diag::err_sloc_space_too_large); + // FIXME: call `noteSLocAddressSpaceUsage` to report details to users and + // use a source location from `Info` to point at an error. + // Currently, both cause Clang to run indefinitely, this needs to be fixed. + // FIXME: return an error instead of crashing. Returning invalid source + // locations causes compiler to run indefinitely. + llvm::report_fatal_error("ran out of source locations"); + } // See createFileID for that +1. NextLocalOffset += Length + 1; return SourceLocation::getMacroLoc(NextLocalOffset - (Length + 1)); diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp index 8130f90a27674..ea002bb464fcc 100644 --- a/clang/lib/Basic/Targets.cpp +++ b/clang/lib/Basic/Targets.cpp @@ -247,12 +247,8 @@ std::unique_ptr AllocateTarget(const llvm::Triple &Triple, switch (os) { case llvm::Triple::Linux: return std::make_unique>(Triple, Opts); - case llvm::Triple::FreeBSD: - return std::make_unique>(Triple, Opts); case llvm::Triple::NetBSD: return std::make_unique>(Triple, Opts); - case llvm::Triple::OpenBSD: - return std::make_unique>(Triple, Opts); case llvm::Triple::RTEMS: return std::make_unique>(Triple, Opts); case llvm::Triple::NaCl: @@ -487,15 +483,11 @@ std::unique_ptr AllocateTarget(const llvm::Triple &Triple, return std::make_unique(Triple, Opts); } - // The 'sparcel' architecture copies all the above cases except for Solaris. case llvm::Triple::sparcel: switch (os) { case llvm::Triple::Linux: return std::make_unique>(Triple, Opts); - case llvm::Triple::NetBSD: - return std::make_unique>(Triple, - Opts); case llvm::Triple::RTEMS: return std::make_unique>(Triple, Opts); diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp index 1e809283748b6..ce7e4d4639cea 100644 --- a/clang/lib/Basic/Targets/ARM.cpp +++ b/clang/lib/Basic/Targets/ARM.cpp @@ -258,6 +258,7 @@ ARMTargetInfo::ARMTargetInfo(const llvm::Triple &Triple, bool IsOpenBSD = Triple.isOSOpenBSD(); bool IsNetBSD = Triple.isOSNetBSD(); bool IsHaiku = Triple.isOSHaiku(); + bool IsOHOS = Triple.isOHOSFamily(); // FIXME: the isOSBinFormatMachO is a workaround for identifying a Darwin-like // environment where size_t is `unsigned long` rather than `unsigned int` @@ -324,7 +325,7 @@ ARMTargetInfo::ARMTargetInfo(const llvm::Triple &Triple, default: if (IsNetBSD) setABI("apcs-gnu"); - else if (IsFreeBSD || IsOpenBSD || IsHaiku) + else if (IsFreeBSD || IsOpenBSD || IsHaiku || IsOHOS) setABI("aapcs-linux"); else setABI("aapcs"); diff --git a/clang/lib/Basic/Targets/Mips.cpp b/clang/lib/Basic/Targets/Mips.cpp index cdf652c49f603..bc90d1b93d53f 100644 --- a/clang/lib/Basic/Targets/Mips.cpp +++ b/clang/lib/Basic/Targets/Mips.cpp @@ -149,6 +149,10 @@ void MipsTargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("_MIPS_FPSET", Twine(32)); else Builder.defineMacro("_MIPS_FPSET", Twine(16)); + if (NoOddSpreg) + Builder.defineMacro("_MIPS_SPFPSET", Twine(16)); + else + Builder.defineMacro("_MIPS_SPFPSET", Twine(32)); if (IsMips16) Builder.defineMacro("__mips16", Twine(1)); diff --git a/clang/lib/Basic/Targets/Mips.h b/clang/lib/Basic/Targets/Mips.h index 7ecbd8633cb34..f46b95abfd75c 100644 --- a/clang/lib/Basic/Targets/Mips.h +++ b/clang/lib/Basic/Targets/Mips.h @@ -53,6 +53,7 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo { bool HasMSA; bool DisableMadd4; bool UseIndirectJumpHazard; + bool NoOddSpreg; protected: enum FPModeEnum { FPXX, FP32, FP64 } FPMode; @@ -313,6 +314,8 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo { FloatABI = HardFloat; DspRev = NoDSP; FPMode = isFP64Default() ? FP64 : FPXX; + NoOddSpreg = false; + bool OddSpregGiven = false; for (const auto &Feature : Features) { if (Feature == "+single-float") @@ -349,8 +352,18 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo { IsNoABICalls = true; else if (Feature == "+use-indirect-jump-hazard") UseIndirectJumpHazard = true; + else if (Feature == "+nooddspreg") { + NoOddSpreg = true; + OddSpregGiven = false; + } else if (Feature == "-nooddspreg") { + NoOddSpreg = false; + OddSpregGiven = true; + } } + if (FPMode == FPXX && !OddSpregGiven) + NoOddSpreg = true; + setDataLayout(); return true; diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp index 0d87a3a4e8c20..5ce276e1af9ef 100644 --- a/clang/lib/Basic/Targets/PPC.cpp +++ b/clang/lib/Basic/Targets/PPC.cpp @@ -264,6 +264,10 @@ static void defineXLCompatMacros(MacroBuilder &Builder) { Builder.defineMacro("__builtin_minfe", "__builtin_ppc_minfe"); Builder.defineMacro("__builtin_minfl", "__builtin_ppc_minfl"); Builder.defineMacro("__builtin_minfs", "__builtin_ppc_minfs"); + Builder.defineMacro("__builtin_mffs", "__builtin_ppc_mffs"); + Builder.defineMacro("__builtin_mffsl", "__builtin_ppc_mffsl"); + Builder.defineMacro("__builtin_mtfsf", "__builtin_ppc_mtfsf"); + Builder.defineMacro("__builtin_set_fpscr_rn", "__builtin_ppc_set_fpscr_rn"); } /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp index d55ab76395c82..0b9ebeaf5e75b 100644 --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -23,6 +23,7 @@ using namespace clang; using namespace clang::targets; ArrayRef RISCVTargetInfo::getGCCRegNames() const { + // clang-format off static const char *const GCCRegNames[] = { // Integer registers "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", @@ -40,7 +41,12 @@ ArrayRef RISCVTargetInfo::getGCCRegNames() const { "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", - "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"}; + "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", + + // CSRs + "fflags", "frm", "vtype", "vl", "vxsat", "vxrm" + }; + // clang-format on return llvm::ArrayRef(GCCRegNames); } @@ -204,6 +210,11 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts, if (VScale && VScale->first && VScale->first == VScale->second) Builder.defineMacro("__riscv_v_fixed_vlen", Twine(VScale->first * llvm::RISCV::RVVBitsPerBlock)); + + if (FastUnalignedAccess) + Builder.defineMacro("__riscv_misaligned_fast"); + else + Builder.defineMacro("__riscv_misaligned_avoid"); } static constexpr Builtin::Info BuiltinInfo[] = { @@ -322,6 +333,8 @@ bool RISCVTargetInfo::handleTargetFeatures(std::vector &Features, if (ISAInfo->hasExtension("zfh") || ISAInfo->hasExtension("zhinx")) HasLegalHalfType = true; + FastUnalignedAccess = llvm::is_contained(Features, "+unaligned-scalar-mem"); + return true; } diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h index 6be0e49ca2f55..e5424d318401f 100644 --- a/clang/lib/Basic/Targets/RISCV.h +++ b/clang/lib/Basic/Targets/RISCV.h @@ -29,6 +29,9 @@ class RISCVTargetInfo : public TargetInfo { std::string ABI, CPU; std::unique_ptr ISAInfo; +private: + bool FastUnalignedAccess; + public: RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &) : TargetInfo(Triple) { diff --git a/clang/lib/CodeGen/BackendUtil.cpp b/clang/lib/CodeGen/BackendUtil.cpp index 70accce456d3c..83b81a38a7685 100644 --- a/clang/lib/CodeGen/BackendUtil.cpp +++ b/clang/lib/CodeGen/BackendUtil.cpp @@ -42,6 +42,7 @@ #include "llvm/Passes/PassBuilder.h" #include "llvm/Passes/PassPlugin.h" #include "llvm/Passes/StandardInstrumentations.h" +#include "llvm/ProfileData/InstrProfCorrelator.h" #include "llvm/Support/BuryPointer.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/MemoryBuffer.h" @@ -55,6 +56,7 @@ #include "llvm/Target/TargetOptions.h" #include "llvm/TargetParser/SubtargetFeature.h" #include "llvm/TargetParser/Triple.h" +#include "llvm/Transforms/HipStdPar/HipStdPar.h" #include "llvm/Transforms/IPO/EmbedBitcodePass.h" #include "llvm/Transforms/IPO/LowerTypeTests.h" #include "llvm/Transforms/IPO/ThinLTOBitcodeWriter.h" @@ -78,7 +80,6 @@ #include "llvm/Transforms/Scalar/EarlyCSE.h" #include "llvm/Transforms/Scalar/GVN.h" #include "llvm/Transforms/Scalar/JumpThreading.h" -#include "llvm/Transforms/HipStdPar/HipStdPar.h" #include "llvm/Transforms/Utils/Debugify.h" #include "llvm/Transforms/Utils/EntryExitInstrumenter.h" #include "llvm/Transforms/Utils/ModuleUtils.h" @@ -98,13 +99,18 @@ extern cl::opt PrintPipelinePasses; static cl::opt ClSanitizeOnOptimizerEarlyEP( "sanitizer-early-opt-ep", cl::Optional, cl::desc("Insert sanitizers on OptimizerEarlyEP."), cl::init(false)); -} + +extern cl::opt DebugInfoCorrelate; +extern cl::opt ProfileCorrelate; +} // namespace llvm namespace { // Default filename used for profile generation. std::string getDefaultProfileGenName() { - return DebugInfoCorrelate ? "default_%m.proflite" : "default_%m.profraw"; + return DebugInfoCorrelate || ProfileCorrelate != InstrProfCorrelator::NONE + ? "default_%m.proflite" + : "default_%m.profraw"; } class EmitAssemblyHelper { @@ -197,7 +203,7 @@ class EmitAssemblyHelper { void EmitAssembly(BackendAction Action, std::unique_ptr OS); }; -} +} // namespace static SanitizerCoverageOptions getSancovOptsFromCGOpts(const CodeGenOptions &CGOpts) { diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index e1211bb8949b6..dce5ee5888c45 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -7995,15 +7995,23 @@ enum SpecialRegisterAccessKind { Write, }; +// Generates the IR for __builtin_read_exec_*. +// Lowers the builtin to amdgcn_ballot intrinsic. static Value *EmitAMDGCNBallotForExec(CodeGenFunction &CGF, const CallExpr *E, llvm::Type *RegisterType, - llvm::Type *ValueType) { + llvm::Type *ValueType, bool isExecHi) { CodeGen::CGBuilderTy &Builder = CGF.Builder; CodeGen::CodeGenModule &CGM = CGF.CGM; - llvm::Type *ResultType = CGF.ConvertType(E->getType()); - Function *F = CGM.getIntrinsic(Intrinsic::amdgcn_ballot, {ResultType}); + Function *F = CGM.getIntrinsic(Intrinsic::amdgcn_ballot, {RegisterType}); llvm::Value *Call = Builder.CreateCall(F, {Builder.getInt1(true)}); + + if (isExecHi) { + Value *Rt2 = Builder.CreateLShr(Call, 32); + Rt2 = Builder.CreateTrunc(Rt2, CGF.Int32Ty); + return Rt2; + } + return Call; } @@ -17389,6 +17397,11 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID, Value *Op1 = EmitScalarExpr(E->getArg(1)); return Builder.CreateFDiv(Op0, Op1, "swdiv"); } + case PPC::BI__builtin_ppc_set_fpscr_rn: + return Builder.CreateCall(CGM.getIntrinsic(Intrinsic::ppc_setrnd), + {EmitScalarExpr(E->getArg(0))}); + case PPC::BI__builtin_ppc_mffs: + return Builder.CreateCall(CGM.getIntrinsic(Intrinsic::ppc_readflm)); } } @@ -17857,10 +17870,11 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID, return Builder.CreateCall(F, {Addr, Val, ZeroI32, ZeroI32, ZeroI1}); } case AMDGPU::BI__builtin_amdgcn_read_exec: + return EmitAMDGCNBallotForExec(*this, E, Int64Ty, Int64Ty, false); case AMDGPU::BI__builtin_amdgcn_read_exec_lo: - case AMDGPU::BI__builtin_amdgcn_read_exec_hi: { - return EmitAMDGCNBallotForExec(*this, E, Int64Ty, Int64Ty); - } + return EmitAMDGCNBallotForExec(*this, E, Int32Ty, Int32Ty, false); + case AMDGPU::BI__builtin_amdgcn_read_exec_hi: + return EmitAMDGCNBallotForExec(*this, E, Int64Ty, Int64Ty, true); case AMDGPU::BI__builtin_amdgcn_image_bvh_intersect_ray: case AMDGPU::BI__builtin_amdgcn_image_bvh_intersect_ray_h: case AMDGPU::BI__builtin_amdgcn_image_bvh_intersect_ray_l: diff --git a/clang/lib/CodeGen/CGCUDANV.cpp b/clang/lib/CodeGen/CGCUDANV.cpp index 8a1212f2272e8..66147f656071f 100644 --- a/clang/lib/CodeGen/CGCUDANV.cpp +++ b/clang/lib/CodeGen/CGCUDANV.cpp @@ -19,6 +19,7 @@ #include "clang/Basic/Cuda.h" #include "clang/CodeGen/CodeGenABITypes.h" #include "clang/CodeGen/ConstantInitBuilder.h" +#include "llvm/Frontend/Offloading/Utility.h" #include "llvm/IR/BasicBlock.h" #include "llvm/IR/Constants.h" #include "llvm/IR/DerivedTypes.h" @@ -555,7 +556,7 @@ llvm::Function *CGNVCUDARuntime::makeRegisterGlobalsFn() { llvm::Constant *NullPtr = llvm::ConstantPointerNull::get(VoidPtrTy); llvm::Value *Args[] = { &GpuBinaryHandlePtr, - Builder.CreateBitCast(KernelHandles[I.Kernel->getName()], VoidPtrTy), + KernelHandles[I.Kernel->getName()], KernelName, KernelName, llvm::ConstantInt::get(IntTy, -1), @@ -630,8 +631,8 @@ llvm::Function *CGNVCUDARuntime::makeRegisterGlobalsFn() { replaceManagedVar(Var, ManagedVar); llvm::Value *Args[] = { &GpuBinaryHandlePtr, - Builder.CreateBitCast(ManagedVar, VoidPtrTy), - Builder.CreateBitCast(Var, VoidPtrTy), + ManagedVar, + Var, VarName, llvm::ConstantInt::get(VarSizeTy, VarSize), llvm::ConstantInt::get(IntTy, Var->getAlignment())}; @@ -640,7 +641,7 @@ llvm::Function *CGNVCUDARuntime::makeRegisterGlobalsFn() { } else { llvm::Value *Args[] = { &GpuBinaryHandlePtr, - Builder.CreateBitCast(Var, VoidPtrTy), + Var, VarName, VarName, llvm::ConstantInt::get(IntTy, Info.Flags.isExtern()), @@ -654,15 +655,15 @@ llvm::Function *CGNVCUDARuntime::makeRegisterGlobalsFn() { case DeviceVarFlags::Surface: Builder.CreateCall( RegisterSurf, - {&GpuBinaryHandlePtr, Builder.CreateBitCast(Var, VoidPtrTy), VarName, - VarName, llvm::ConstantInt::get(IntTy, Info.Flags.getSurfTexType()), + {&GpuBinaryHandlePtr, Var, VarName, VarName, + llvm::ConstantInt::get(IntTy, Info.Flags.getSurfTexType()), llvm::ConstantInt::get(IntTy, Info.Flags.isExtern())}); break; case DeviceVarFlags::Texture: Builder.CreateCall( RegisterTex, - {&GpuBinaryHandlePtr, Builder.CreateBitCast(Var, VoidPtrTy), VarName, - VarName, llvm::ConstantInt::get(IntTy, Info.Flags.getSurfTexType()), + {&GpuBinaryHandlePtr, Var, VarName, VarName, + llvm::ConstantInt::get(IntTy, Info.Flags.getSurfTexType()), llvm::ConstantInt::get(IntTy, Info.Flags.isNormalized()), llvm::ConstantInt::get(IntTy, Info.Flags.isExtern())}); break; @@ -859,9 +860,8 @@ llvm::Function *CGNVCUDARuntime::makeModuleCtorFunction() { { CtorBuilder.SetInsertPoint(IfBlock); // GpuBinaryHandle = __hipRegisterFatBinary(&FatbinWrapper); - llvm::CallInst *RegisterFatbinCall = CtorBuilder.CreateCall( - RegisterFatbinFunc, - CtorBuilder.CreateBitCast(FatbinWrapper, VoidPtrTy)); + llvm::CallInst *RegisterFatbinCall = + CtorBuilder.CreateCall(RegisterFatbinFunc, FatbinWrapper); CtorBuilder.CreateStore(RegisterFatbinCall, GpuBinaryAddr); CtorBuilder.CreateBr(ExitBlock); } @@ -877,9 +877,8 @@ llvm::Function *CGNVCUDARuntime::makeModuleCtorFunction() { // Register binary with CUDA runtime. This is substantially different in // default mode vs. separate compilation! // GpuBinaryHandle = __cudaRegisterFatBinary(&FatbinWrapper); - llvm::CallInst *RegisterFatbinCall = CtorBuilder.CreateCall( - RegisterFatbinFunc, - CtorBuilder.CreateBitCast(FatbinWrapper, VoidPtrTy)); + llvm::CallInst *RegisterFatbinCall = + CtorBuilder.CreateCall(RegisterFatbinFunc, FatbinWrapper); GpuBinaryHandle = new llvm::GlobalVariable( TheModule, VoidPtrPtrTy, false, llvm::GlobalValue::InternalLinkage, llvm::ConstantPointerNull::get(VoidPtrPtrTy), "__cuda_gpubin_handle"); @@ -920,9 +919,7 @@ llvm::Function *CGNVCUDARuntime::makeModuleCtorFunction() { getRegisterLinkedBinaryFnTy(), RegisterLinkedBinaryName); assert(RegisterGlobalsFunc && "Expecting at least dummy function!"); - llvm::Value *Args[] = {RegisterGlobalsFunc, - CtorBuilder.CreateBitCast(FatbinWrapper, VoidPtrTy), - ModuleIDConstant, + llvm::Value *Args[] = {RegisterGlobalsFunc, FatbinWrapper, ModuleIDConstant, makeDummyFunction(getCallbackFnTy())}; CtorBuilder.CreateCall(RegisterLinkedBinaryFunc, Args); } @@ -1129,33 +1126,32 @@ void CGNVCUDARuntime::transformManagedVars() { // registered. The linker will provide a pointer to this section so we can // register the symbols with the linked device image. void CGNVCUDARuntime::createOffloadingEntries() { - llvm::OpenMPIRBuilder OMPBuilder(CGM.getModule()); - OMPBuilder.initialize(); - StringRef Section = CGM.getLangOpts().HIP ? "hip_offloading_entries" : "cuda_offloading_entries"; + llvm::Module &M = CGM.getModule(); for (KernelInfo &I : EmittedKernels) - OMPBuilder.emitOffloadingEntry(KernelHandles[I.Kernel->getName()], - getDeviceSideName(cast(I.D)), 0, - DeviceVarFlags::OffloadGlobalEntry, Section); + llvm::offloading::emitOffloadingEntry( + M, KernelHandles[I.Kernel->getName()], + getDeviceSideName(cast(I.D)), 0, + DeviceVarFlags::OffloadGlobalEntry, Section); for (VarInfo &I : DeviceVars) { uint64_t VarSize = CGM.getDataLayout().getTypeAllocSize(I.Var->getValueType()); if (I.Flags.getKind() == DeviceVarFlags::Variable) { - OMPBuilder.emitOffloadingEntry( - I.Var, getDeviceSideName(I.D), VarSize, + llvm::offloading::emitOffloadingEntry( + M, I.Var, getDeviceSideName(I.D), VarSize, I.Flags.isManaged() ? DeviceVarFlags::OffloadGlobalManagedEntry : DeviceVarFlags::OffloadGlobalEntry, Section); } else if (I.Flags.getKind() == DeviceVarFlags::Surface) { - OMPBuilder.emitOffloadingEntry(I.Var, getDeviceSideName(I.D), VarSize, - DeviceVarFlags::OffloadGlobalSurfaceEntry, - Section); + llvm::offloading::emitOffloadingEntry( + M, I.Var, getDeviceSideName(I.D), VarSize, + DeviceVarFlags::OffloadGlobalSurfaceEntry, Section); } else if (I.Flags.getKind() == DeviceVarFlags::Texture) { - OMPBuilder.emitOffloadingEntry(I.Var, getDeviceSideName(I.D), VarSize, - DeviceVarFlags::OffloadGlobalTextureEntry, - Section); + llvm::offloading::emitOffloadingEntry( + M, I.Var, getDeviceSideName(I.D), VarSize, + DeviceVarFlags::OffloadGlobalTextureEntry, Section); } } } diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp index 150450e916590..e1e1ad7e6a17b 100644 --- a/clang/lib/CodeGen/CGCall.cpp +++ b/clang/lib/CodeGen/CGCall.cpp @@ -3447,9 +3447,9 @@ static llvm::Value *tryRemoveRetainOfSelf(CodeGenFunction &CGF, const VarDecl *self = method->getSelfDecl(); if (!self->getType().isConstQualified()) return nullptr; - // Look for a retain call. Note: stripPointerCasts looks through returned arg - // functions, which would cause us to miss the retain. - llvm::CallInst *retainCall = dyn_cast(result); + // Look for a retain call. + llvm::CallInst *retainCall = + dyn_cast(result->stripPointerCasts()); if (!retainCall || retainCall->getCalledOperand() != CGF.CGM.getObjCEntrypoints().objc_retain) return nullptr; diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp b/clang/lib/CodeGen/CGDebugInfo.cpp index c430713b0d77d..0aaf678bf287c 100644 --- a/clang/lib/CodeGen/CGDebugInfo.cpp +++ b/clang/lib/CodeGen/CGDebugInfo.cpp @@ -1499,6 +1499,8 @@ CGDebugInfo::createBitFieldType(const FieldDecl *BitFieldDecl, llvm::DIScope *RecordTy, const RecordDecl *RD) { StringRef Name = BitFieldDecl->getName(); QualType Ty = BitFieldDecl->getType(); + if (BitFieldDecl->hasAttr()) + Ty = BitFieldDecl->getAttr()->getType(); SourceLocation Loc = BitFieldDecl->getLocation(); llvm::DIFile *VUnit = getOrCreateFile(Loc); llvm::DIType *DebugType = getOrCreateType(Ty, VUnit); @@ -4879,11 +4881,15 @@ CGDebugInfo::EmitDeclareOfAutoVariable(const VarDecl *VD, llvm::Value *Storage, const bool UsePointerValue) { assert(CGM.getCodeGenOpts().hasReducedDebugInfo()); - if (auto *DD = dyn_cast(VD)) + if (auto *DD = dyn_cast(VD)) { for (auto *B : DD->bindings()) { EmitDeclare(B, Storage, std::nullopt, Builder, VD->getType()->isReferenceType()); } + // Don't emit an llvm.dbg.declare for the composite storage as it doesn't + // correspond to a user variable. + return nullptr; + } return EmitDeclare(VD, Storage, std::nullopt, Builder, UsePointerValue); } diff --git a/clang/lib/CodeGen/CGDecl.cpp b/clang/lib/CodeGen/CGDecl.cpp index 4d4c94d008c9d..9e4319d27858e 100644 --- a/clang/lib/CodeGen/CGDecl.cpp +++ b/clang/lib/CodeGen/CGDecl.cpp @@ -1358,7 +1358,6 @@ llvm::Value *CodeGenFunction::EmitLifetimeStart(llvm::TypeSize Size, "Pointer should be in alloca address space"); llvm::Value *SizeV = llvm::ConstantInt::get( Int64Ty, Size.isScalable() ? -1 : Size.getFixedValue()); - Addr = Builder.CreateBitCast(Addr, AllocaInt8PtrTy); llvm::CallInst *C = Builder.CreateCall(CGM.getLLVMLifetimeStartFn(), {SizeV, Addr}); C->setDoesNotThrow(); @@ -1369,7 +1368,6 @@ void CodeGenFunction::EmitLifetimeEnd(llvm::Value *Size, llvm::Value *Addr) { assert(Addr->getType()->getPointerAddressSpace() == CGM.getDataLayout().getAllocaAddrSpace() && "Pointer should be in alloca address space"); - Addr = Builder.CreateBitCast(Addr, AllocaInt8PtrTy); llvm::CallInst *C = Builder.CreateCall(CGM.getLLVMLifetimeEndFn(), {Size, Addr}); C->setDoesNotThrow(); diff --git a/clang/lib/CodeGen/CGExprCXX.cpp b/clang/lib/CodeGen/CGExprCXX.cpp index 2e7059cc8f5b6..4bd8462ab5f8b 100644 --- a/clang/lib/CodeGen/CGExprCXX.cpp +++ b/clang/lib/CodeGen/CGExprCXX.cpp @@ -1106,9 +1106,7 @@ void CodeGenFunction::EmitNewArrayInitializer( // element. TODO: some of these stores can be trivially // observed to be unnecessary. if (EndOfInit.isValid()) { - auto FinishedPtr = - Builder.CreateBitCast(CurPtr.getPointer(), BeginPtr.getType()); - Builder.CreateStore(FinishedPtr, EndOfInit); + Builder.CreateStore(CurPtr.getPointer(), EndOfInit); } // FIXME: If the last initializer is an incomplete initializer list for // an array, and we have an array filler, we can fold together the two diff --git a/clang/lib/CodeGen/CGExprConstant.cpp b/clang/lib/CodeGen/CGExprConstant.cpp index 9b67a8b3335a1..c46f38d651972 100644 --- a/clang/lib/CodeGen/CGExprConstant.cpp +++ b/clang/lib/CodeGen/CGExprConstant.cpp @@ -1775,9 +1775,10 @@ llvm::Constant *ConstantEmitter::tryEmitPrivate(const Expr *E, QualType destType) { assert(!destType->isVoidType() && "can't emit a void constant"); - if (llvm::Constant *C = - ConstExprEmitter(*this).Visit(const_cast(E), destType)) - return C; + if (!destType->isReferenceType()) + if (llvm::Constant *C = + ConstExprEmitter(*this).Visit(const_cast(E), destType)) + return C; Expr::EvalResult Result; @@ -2151,6 +2152,9 @@ llvm::Constant *ConstantEmitter::tryEmitPrivate(const APValue &Value, Inits[I] = llvm::ConstantInt::get(CGM.getLLVMContext(), Elt.getInt()); else if (Elt.isFloat()) Inits[I] = llvm::ConstantFP::get(CGM.getLLVMContext(), Elt.getFloat()); + else if (Elt.isIndeterminate()) + Inits[I] = llvm::UndefValue::get(CGM.getTypes().ConvertType( + DestType->castAs()->getElementType())); else llvm_unreachable("unsupported vector element type"); } diff --git a/clang/lib/CodeGen/CGExprScalar.cpp b/clang/lib/CodeGen/CGExprScalar.cpp index c25ddeff9adc3..7633c6b17db88 100644 --- a/clang/lib/CodeGen/CGExprScalar.cpp +++ b/clang/lib/CodeGen/CGExprScalar.cpp @@ -2084,11 +2084,10 @@ Value *ScalarExprEmitter::VisitCastExpr(CastExpr *CE) { Value *Src = Visit(const_cast(E)); llvm::Type *SrcTy = Src->getType(); llvm::Type *DstTy = ConvertType(DestTy); - if (SrcTy->isPtrOrPtrVectorTy() && DstTy->isPtrOrPtrVectorTy() && - SrcTy->getPointerAddressSpace() != DstTy->getPointerAddressSpace()) { - llvm_unreachable("wrong cast for pointers in different address spaces" - "(must be an address space cast)!"); - } + assert( + (!SrcTy->isPtrOrPtrVectorTy() || !DstTy->isPtrOrPtrVectorTy() || + SrcTy->getPointerAddressSpace() == DstTy->getPointerAddressSpace()) && + "Address-space cast must be used to convert address spaces"); if (CGF.SanOpts.has(SanitizerKind::CFIUnrelatedCast)) { if (auto *PT = DestTy->getAs()) { diff --git a/clang/lib/CodeGen/CGNonTrivialStruct.cpp b/clang/lib/CodeGen/CGNonTrivialStruct.cpp index 3d2b1b8b2f78d..15c4a3e706c9d 100644 --- a/clang/lib/CodeGen/CGNonTrivialStruct.cpp +++ b/clang/lib/CodeGen/CGNonTrivialStruct.cpp @@ -367,8 +367,6 @@ template struct GenFuncBase { CGF.Builder.CreateNUWMul(BaseEltSizeVal, NumElts); llvm::Value *DstArrayEnd = CGF.Builder.CreateInBoundsGEP( CGF.Int8Ty, DstAddr.getPointer(), SizeInBytes); - DstArrayEnd = CGF.Builder.CreateBitCast( - DstArrayEnd, CGF.CGM.Int8PtrPtrTy, "dstarray.end"); llvm::BasicBlock *PreheaderBB = CGF.Builder.GetInsertBlock(); // Create the header block and insert the phi instructions. diff --git a/clang/lib/CodeGen/CGObjC.cpp b/clang/lib/CodeGen/CGObjC.cpp index 6c594b5db4bca..aa3a0ff57003d 100644 --- a/clang/lib/CodeGen/CGObjC.cpp +++ b/clang/lib/CodeGen/CGObjC.cpp @@ -3954,7 +3954,7 @@ static unsigned getBaseMachOPlatformID(const llvm::Triple &TT) { case llvm::Triple::DriverKit: return llvm::MachO::PLATFORM_DRIVERKIT; default: - return /*Unknown platform*/ 0; + return llvm::MachO::PLATFORM_UNKNOWN; } } diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.cpp b/clang/lib/CodeGen/CGOpenMPRuntime.cpp index aae1a0ea250ee..c1be7c2d03215 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntime.cpp +++ b/clang/lib/CodeGen/CGOpenMPRuntime.cpp @@ -6002,6 +6002,42 @@ void CGOpenMPRuntime::emitUsesAllocatorsFini(CodeGenFunction &CGF, {ThreadId, AllocatorVal}); } +void CGOpenMPRuntime::computeMinAndMaxThreadsAndTeams( + const OMPExecutableDirective &D, CodeGenFunction &CGF, + int32_t &MinThreadsVal, int32_t &MaxThreadsVal, int32_t &MinTeamsVal, + int32_t &MaxTeamsVal) { + + getNumTeamsExprForTargetDirective(CGF, D, MinTeamsVal, MaxTeamsVal); + getNumThreadsExprForTargetDirective(CGF, D, MaxThreadsVal, + /*UpperBoundOnly=*/true); + + for (auto *C : D.getClausesOfKind()) { + for (auto *A : C->getAttrs()) { + int32_t AttrMinThreadsVal = 1, AttrMaxThreadsVal = -1; + int32_t AttrMinBlocksVal = 1, AttrMaxBlocksVal = -1; + if (auto *Attr = dyn_cast(A)) + CGM.handleCUDALaunchBoundsAttr(nullptr, Attr, &AttrMaxThreadsVal, + &AttrMinBlocksVal, &AttrMaxBlocksVal); + else if (auto *Attr = dyn_cast(A)) + CGM.handleAMDGPUFlatWorkGroupSizeAttr( + nullptr, Attr, /*ReqdWGS=*/nullptr, &AttrMinThreadsVal, + &AttrMaxThreadsVal); + else + continue; + + MinThreadsVal = std::max(MinThreadsVal, AttrMinThreadsVal); + if (AttrMaxThreadsVal > 0) + MaxThreadsVal = MaxThreadsVal > 0 + ? std::min(MaxThreadsVal, AttrMaxThreadsVal) + : AttrMaxThreadsVal; + MinTeamsVal = std::max(MinTeamsVal, AttrMinBlocksVal); + if (AttrMaxBlocksVal > 0) + MaxTeamsVal = MaxTeamsVal > 0 ? std::min(MaxTeamsVal, AttrMaxBlocksVal) + : AttrMaxBlocksVal; + } + } +} + void CGOpenMPRuntime::emitTargetOutlinedFunctionHelper( const OMPExecutableDirective &D, StringRef ParentName, llvm::Function *&OutlinedFn, llvm::Constant *&OutlinedFnID, @@ -6020,15 +6056,7 @@ void CGOpenMPRuntime::emitTargetOutlinedFunctionHelper( return CGF.GenerateOpenMPCapturedStmtFunction(CS, D.getBeginLoc()); }; - // Get NumTeams and ThreadLimit attributes - int32_t DefaultValTeams = -1; - uint32_t DefaultValThreads = UINT32_MAX; - getNumTeamsExprForTargetDirective(CGF, D, DefaultValTeams); - getNumThreadsExprForTargetDirective(CGF, D, DefaultValThreads, - /*UpperBoundOnly=*/true); - OMPBuilder.emitTargetRegionFunction(EntryInfo, GenerateOutlinedFunction, - DefaultValTeams, DefaultValThreads, IsOffloadEntry, OutlinedFn, OutlinedFnID); if (!OutlinedFn) @@ -6038,14 +6066,8 @@ void CGOpenMPRuntime::emitTargetOutlinedFunctionHelper( for (auto *C : D.getClausesOfKind()) { for (auto *A : C->getAttrs()) { - if (auto *Attr = dyn_cast(A)) - CGM.handleCUDALaunchBoundsAttr(OutlinedFn, Attr); - else if (auto *Attr = dyn_cast(A)) - CGM.handleAMDGPUFlatWorkGroupSizeAttr(OutlinedFn, Attr); - else if (auto *Attr = dyn_cast(A)) + if (auto *Attr = dyn_cast(A)) CGM.handleAMDGPUWavesPerEUAttr(OutlinedFn, Attr); - else - llvm_unreachable("Unexpected attribute kind"); } } } @@ -6103,8 +6125,8 @@ const Stmt *CGOpenMPRuntime::getSingleCompoundChild(ASTContext &Ctx, } const Expr *CGOpenMPRuntime::getNumTeamsExprForTargetDirective( - CodeGenFunction &CGF, const OMPExecutableDirective &D, - int32_t &DefaultVal) { + CodeGenFunction &CGF, const OMPExecutableDirective &D, int32_t &MinTeamsVal, + int32_t &MaxTeamsVal) { OpenMPDirectiveKind DirectiveKind = D.getDirectiveKind(); assert(isOpenMPTargetExecutionDirective(DirectiveKind) && @@ -6125,22 +6147,22 @@ const Expr *CGOpenMPRuntime::getNumTeamsExprForTargetDirective( if (NumTeams->isIntegerConstantExpr(CGF.getContext())) if (auto Constant = NumTeams->getIntegerConstantExpr(CGF.getContext())) - DefaultVal = Constant->getExtValue(); + MinTeamsVal = MaxTeamsVal = Constant->getExtValue(); return NumTeams; } - DefaultVal = 0; + MinTeamsVal = MaxTeamsVal = 0; return nullptr; } if (isOpenMPParallelDirective(NestedDir->getDirectiveKind()) || isOpenMPSimdDirective(NestedDir->getDirectiveKind())) { - DefaultVal = 1; + MinTeamsVal = MaxTeamsVal = 1; return nullptr; } - DefaultVal = 1; + MinTeamsVal = MaxTeamsVal = 1; return nullptr; } // A value of -1 is used to check if we need to emit no teams region - DefaultVal = -1; + MinTeamsVal = MaxTeamsVal = -1; return nullptr; } case OMPD_target_teams_loop: @@ -6154,10 +6176,10 @@ const Expr *CGOpenMPRuntime::getNumTeamsExprForTargetDirective( D.getSingleClause()->getNumTeams(); if (NumTeams->isIntegerConstantExpr(CGF.getContext())) if (auto Constant = NumTeams->getIntegerConstantExpr(CGF.getContext())) - DefaultVal = Constant->getExtValue(); + MinTeamsVal = MaxTeamsVal = Constant->getExtValue(); return NumTeams; } - DefaultVal = 0; + MinTeamsVal = MaxTeamsVal = 0; return nullptr; } case OMPD_target_parallel: @@ -6165,7 +6187,7 @@ const Expr *CGOpenMPRuntime::getNumTeamsExprForTargetDirective( case OMPD_target_parallel_for_simd: case OMPD_target_parallel_loop: case OMPD_target_simd: - DefaultVal = 1; + MinTeamsVal = MaxTeamsVal = 1; return nullptr; case OMPD_parallel: case OMPD_for: @@ -6240,8 +6262,9 @@ llvm::Value *CGOpenMPRuntime::emitNumTeamsForTargetDirective( "Clauses associated with the teams directive expected to be emitted " "only for the host!"); CGBuilderTy &Bld = CGF.Builder; - int32_t DefaultNT = -1; - const Expr *NumTeams = getNumTeamsExprForTargetDirective(CGF, D, DefaultNT); + int32_t MinNT = -1, MaxNT = -1; + const Expr *NumTeams = + getNumTeamsExprForTargetDirective(CGF, D, MinNT, MaxNT); if (NumTeams != nullptr) { OpenMPDirectiveKind DirectiveKind = D.getDirectiveKind(); @@ -6271,7 +6294,8 @@ llvm::Value *CGOpenMPRuntime::emitNumTeamsForTargetDirective( } } - return llvm::ConstantInt::get(CGF.Int32Ty, DefaultNT); + assert(MinNT == MaxNT && "Num threads ranges require handling here."); + return llvm::ConstantInt::get(CGF.Int32Ty, MinNT); } /// Check for a num threads constant value (stored in \p DefaultVal), or @@ -6279,7 +6303,7 @@ llvm::Value *CGOpenMPRuntime::emitNumTeamsForTargetDirective( /// store the condition in \p CondVal. If \p E, and \p CondVal respectively, are /// nullptr, no expression evaluation is perfomed. static void getNumThreads(CodeGenFunction &CGF, const CapturedStmt *CS, - const Expr **E, uint32_t &UpperBound, + const Expr **E, int32_t &UpperBound, bool UpperBoundOnly, llvm::Value **CondVal) { const Stmt *Child = CGOpenMPRuntime::getSingleCompoundChild( CGF.getContext(), CS->getCapturedStmt()); @@ -6341,10 +6365,10 @@ static void getNumThreads(CodeGenFunction &CGF, const CapturedStmt *CS, UpperBound ? Constant->getZExtValue() : std::min(UpperBound, - static_cast(Constant->getZExtValue())); + static_cast(Constant->getZExtValue())); // If we haven't found a upper bound, remember we saw a thread limiting // clause. - if (UpperBound == UINT32_MAX) + if (UpperBound == -1) UpperBound = 0; if (!E) return; @@ -6370,7 +6394,7 @@ static void getNumThreads(CodeGenFunction &CGF, const CapturedStmt *CS, } const Expr *CGOpenMPRuntime::getNumThreadsExprForTargetDirective( - CodeGenFunction &CGF, const OMPExecutableDirective &D, uint32_t &UpperBound, + CodeGenFunction &CGF, const OMPExecutableDirective &D, int32_t &UpperBound, bool UpperBoundOnly, llvm::Value **CondVal, const Expr **ThreadLimitExpr) { assert((!CGF.getLangOpts().OpenMPIsTargetDevice || UpperBoundOnly) && "Clauses associated with the teams directive expected to be emitted " @@ -6387,11 +6411,11 @@ const Expr *CGOpenMPRuntime::getNumThreadsExprForTargetDirective( if (auto Constant = E->getIntegerConstantExpr(CGF.getContext())) UpperBound = UpperBound ? Constant->getZExtValue() : std::min(UpperBound, - uint32_t(Constant->getZExtValue())); + int32_t(Constant->getZExtValue())); } // If we haven't found a upper bound, remember we saw a thread limiting // clause. - if (UpperBound == UINT32_MAX) + if (UpperBound == -1) UpperBound = 0; if (EPtr) *EPtr = E; @@ -6535,7 +6559,7 @@ llvm::Value *CGOpenMPRuntime::emitNumThreadsForTargetDirective( llvm::Value *CondVal = nullptr; llvm::Value *ThreadLimitVal = nullptr; const Expr *ThreadLimitExpr = nullptr; - uint32_t UpperBound = -1; + int32_t UpperBound = -1; const Expr *NT = getNumThreadsExprForTargetDirective( CGF, D, UpperBound, /* UpperBoundOnly */ false, &CondVal, @@ -10230,11 +10254,6 @@ void CGOpenMPRuntime::emitTargetDataCalls( PrePostActionTy NoPrivAction; using InsertPointTy = llvm::OpenMPIRBuilder::InsertPointTy; - InsertPointTy AllocaIP(CGF.AllocaInsertPt->getParent(), - CGF.AllocaInsertPt->getIterator()); - InsertPointTy CodeGenIP(CGF.Builder.GetInsertBlock(), - CGF.Builder.GetInsertPoint()); - llvm::OpenMPIRBuilder::LocationDescription OmpLoc(CodeGenIP); llvm::Value *IfCondVal = nullptr; if (IfCond) @@ -10314,6 +10333,11 @@ void CGOpenMPRuntime::emitTargetDataCalls( // Source location for the ident struct llvm::Value *RTLoc = emitUpdateLocation(CGF, D.getBeginLoc()); + InsertPointTy AllocaIP(CGF.AllocaInsertPt->getParent(), + CGF.AllocaInsertPt->getIterator()); + InsertPointTy CodeGenIP(CGF.Builder.GetInsertBlock(), + CGF.Builder.GetInsertPoint()); + llvm::OpenMPIRBuilder::LocationDescription OmpLoc(CodeGenIP); CGF.Builder.restoreIP(OMPBuilder.createTargetData( OmpLoc, AllocaIP, CodeGenIP, DeviceID, IfCondVal, Info, GenMapInfoCB, /*MapperFunc=*/nullptr, BodyCB, DeviceAddrCB, CustomMapperCB, RTLoc)); diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.h b/clang/lib/CodeGen/CGOpenMPRuntime.h index 74b528d6cd7f8..0c4ad46e881b9 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntime.h +++ b/clang/lib/CodeGen/CGOpenMPRuntime.h @@ -311,6 +311,14 @@ class CGOpenMPRuntime { /// An OpenMP-IR-Builder instance. llvm::OpenMPIRBuilder OMPBuilder; + /// Helper to determine the min/max number of threads/teams for \p D. + void computeMinAndMaxThreadsAndTeams(const OMPExecutableDirective &D, + CodeGenFunction &CGF, + int32_t &MinThreadsVal, + int32_t &MaxThreadsVal, + int32_t &MinTeamsVal, + int32_t &MaxTeamsVal); + /// Helper to emit outlined function for 'target' directive. /// \param D Directive to emit. /// \param ParentName Name of the function that encloses the target region. @@ -637,7 +645,8 @@ class CGOpenMPRuntime { /// Otherwise, return nullptr. const Expr *getNumTeamsExprForTargetDirective(CodeGenFunction &CGF, const OMPExecutableDirective &D, - int32_t &DefaultVal); + int32_t &MinTeamsVal, + int32_t &MaxTeamsVal); llvm::Value *emitNumTeamsForTargetDirective(CodeGenFunction &CGF, const OMPExecutableDirective &D); @@ -648,7 +657,7 @@ class CGOpenMPRuntime { /// UpperBoundOnly is true, no expression evaluation is perfomed. const Expr *getNumThreadsExprForTargetDirective( CodeGenFunction &CGF, const OMPExecutableDirective &D, - uint32_t &UpperBound, bool UpperBoundOnly, + int32_t &UpperBound, bool UpperBoundOnly, llvm::Value **CondExpr = nullptr, const Expr **ThreadLimitExpr = nullptr); /// Emit an expression that denotes the number of threads a target region diff --git a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp index 56de8d39fe856..9d00ebae70280 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp +++ b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp @@ -757,13 +757,15 @@ void CGOpenMPRuntimeGPU::emitNonSPMDKernel(const OMPExecutableDirective &D, // Emit target region as a standalone region. class NVPTXPrePostActionTy : public PrePostActionTy { CGOpenMPRuntimeGPU::EntryFunctionState &EST; + const OMPExecutableDirective &D; public: - NVPTXPrePostActionTy(CGOpenMPRuntimeGPU::EntryFunctionState &EST) - : EST(EST) {} + NVPTXPrePostActionTy(CGOpenMPRuntimeGPU::EntryFunctionState &EST, + const OMPExecutableDirective &D) + : EST(EST), D(D) {} void Enter(CodeGenFunction &CGF) override { auto &RT = static_cast(CGF.CGM.getOpenMPRuntime()); - RT.emitKernelInit(CGF, EST, /* IsSPMD */ false); + RT.emitKernelInit(D, CGF, EST, /* IsSPMD */ false); // Skip target region initialization. RT.setLocThreadIdInsertPt(CGF, /*AtCurrentPoint=*/true); } @@ -772,7 +774,7 @@ void CGOpenMPRuntimeGPU::emitNonSPMDKernel(const OMPExecutableDirective &D, RT.clearLocThreadIdInsertPt(CGF); RT.emitKernelDeinit(CGF, EST, /* IsSPMD */ false); } - } Action(EST); + } Action(EST, D); CodeGen.setAction(Action); IsInTTDRegion = true; emitTargetOutlinedFunctionHelper(D, ParentName, OutlinedFn, OutlinedFnID, @@ -780,10 +782,17 @@ void CGOpenMPRuntimeGPU::emitNonSPMDKernel(const OMPExecutableDirective &D, IsInTTDRegion = false; } -void CGOpenMPRuntimeGPU::emitKernelInit(CodeGenFunction &CGF, +void CGOpenMPRuntimeGPU::emitKernelInit(const OMPExecutableDirective &D, + CodeGenFunction &CGF, EntryFunctionState &EST, bool IsSPMD) { + int32_t MinThreadsVal = 1, MaxThreadsVal = -1, MinTeamsVal = 1, + MaxTeamsVal = -1; + computeMinAndMaxThreadsAndTeams(D, CGF, MinThreadsVal, MaxThreadsVal, + MinTeamsVal, MaxTeamsVal); + CGBuilderTy &Bld = CGF.Builder; - Bld.restoreIP(OMPBuilder.createTargetInit(Bld, IsSPMD)); + Bld.restoreIP(OMPBuilder.createTargetInit( + Bld, IsSPMD, MinThreadsVal, MaxThreadsVal, MinTeamsVal, MaxTeamsVal)); if (!IsSPMD) emitGenericVarsProlog(CGF, EST.Loc); } @@ -815,19 +824,20 @@ void CGOpenMPRuntimeGPU::emitSPMDKernel(const OMPExecutableDirective &D, CGOpenMPRuntimeGPU::EntryFunctionState &EST; bool IsBareKernel; DataSharingMode Mode; + const OMPExecutableDirective &D; public: NVPTXPrePostActionTy(CGOpenMPRuntimeGPU &RT, CGOpenMPRuntimeGPU::EntryFunctionState &EST, - bool IsBareKernel) + bool IsBareKernel, const OMPExecutableDirective &D) : RT(RT), EST(EST), IsBareKernel(IsBareKernel), - Mode(RT.CurrentDataSharingMode) {} + Mode(RT.CurrentDataSharingMode), D(D) {} void Enter(CodeGenFunction &CGF) override { if (IsBareKernel) { RT.CurrentDataSharingMode = DataSharingMode::DS_CUDA; return; } - RT.emitKernelInit(CGF, EST, /* IsSPMD */ true); + RT.emitKernelInit(D, CGF, EST, /* IsSPMD */ true); // Skip target region initialization. RT.setLocThreadIdInsertPt(CGF, /*AtCurrentPoint=*/true); } @@ -839,7 +849,7 @@ void CGOpenMPRuntimeGPU::emitSPMDKernel(const OMPExecutableDirective &D, RT.clearLocThreadIdInsertPt(CGF); RT.emitKernelDeinit(CGF, EST, /* IsSPMD */ true); } - } Action(*this, EST, IsBareKernel); + } Action(*this, EST, IsBareKernel, D); CodeGen.setAction(Action); IsInTTDRegion = true; emitTargetOutlinedFunctionHelper(D, ParentName, OutlinedFn, OutlinedFnID, @@ -900,11 +910,7 @@ CGOpenMPRuntimeGPU::CGOpenMPRuntimeGPU(CodeGenModule &CGM) void CGOpenMPRuntimeGPU::emitProcBindClause(CodeGenFunction &CGF, ProcBindKind ProcBind, SourceLocation Loc) { - // Do nothing in case of SPMD mode and L0 parallel. - if (getExecutionMode() == CGOpenMPRuntimeGPU::EM_SPMD) - return; - - CGOpenMPRuntime::emitProcBindClause(CGF, ProcBind, Loc); + // Nothing to do. } void CGOpenMPRuntimeGPU::emitNumThreadsClause(CodeGenFunction &CGF, @@ -1046,10 +1052,8 @@ llvm::Function *CGOpenMPRuntimeGPU::emitTeamsOutlinedFunction( } void CGOpenMPRuntimeGPU::emitGenericVarsProlog(CodeGenFunction &CGF, - SourceLocation Loc, - bool WithSPMDCheck) { - if (getDataSharingMode() != CGOpenMPRuntimeGPU::DS_Generic && - getExecutionMode() != CGOpenMPRuntimeGPU::EM_SPMD) + SourceLocation Loc) { + if (getDataSharingMode() != CGOpenMPRuntimeGPU::DS_Generic) return; CGBuilderTy &Bld = CGF.Builder; @@ -1158,10 +1162,8 @@ void CGOpenMPRuntimeGPU::getKmpcFreeShared( {AddrSizePair.first, AddrSizePair.second}); } -void CGOpenMPRuntimeGPU::emitGenericVarsEpilog(CodeGenFunction &CGF, - bool WithSPMDCheck) { - if (getDataSharingMode() != CGOpenMPRuntimeGPU::DS_Generic && - getExecutionMode() != CGOpenMPRuntimeGPU::EM_SPMD) +void CGOpenMPRuntimeGPU::emitGenericVarsEpilog(CodeGenFunction &CGF) { + if (getDataSharingMode() != CGOpenMPRuntimeGPU::DS_Generic) return; const auto I = FunctionGlobalizedDecls.find(CGF.CurFn); @@ -3350,13 +3352,13 @@ void CGOpenMPRuntimeGPU::emitFunctionProlog(CodeGenFunction &CGF, Data.insert(std::make_pair(VD, MappedVarData())); } if (!NeedToDelayGlobalization) { - emitGenericVarsProlog(CGF, D->getBeginLoc(), /*WithSPMDCheck=*/true); + emitGenericVarsProlog(CGF, D->getBeginLoc()); struct GlobalizationScope final : EHScopeStack::Cleanup { GlobalizationScope() = default; void Emit(CodeGenFunction &CGF, Flags flags) override { static_cast(CGF.CGM.getOpenMPRuntime()) - .emitGenericVarsEpilog(CGF, /*WithSPMDCheck=*/true); + .emitGenericVarsEpilog(CGF); } }; CGF.EHStack.pushCleanup(NormalAndEHCleanup); diff --git a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.h b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.h index 86871dfce418f..46e1361f2f895 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.h +++ b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.h @@ -60,19 +60,18 @@ class CGOpenMPRuntimeGPU : public CGOpenMPRuntime { void syncCTAThreads(CodeGenFunction &CGF); /// Helper for target directive initialization. - void emitKernelInit(CodeGenFunction &CGF, EntryFunctionState &EST, - bool IsSPMD); + void emitKernelInit(const OMPExecutableDirective &D, CodeGenFunction &CGF, + EntryFunctionState &EST, bool IsSPMD); /// Helper for target directive finalization. void emitKernelDeinit(CodeGenFunction &CGF, EntryFunctionState &EST, bool IsSPMD); /// Helper for generic variables globalization prolog. - void emitGenericVarsProlog(CodeGenFunction &CGF, SourceLocation Loc, - bool WithSPMDCheck = false); + void emitGenericVarsProlog(CodeGenFunction &CGF, SourceLocation Loc); /// Helper for generic variables globalization epilog. - void emitGenericVarsEpilog(CodeGenFunction &CGF, bool WithSPMDCheck = false); + void emitGenericVarsEpilog(CodeGenFunction &CGF); // // Base class overrides. diff --git a/clang/lib/CodeGen/CMakeLists.txt b/clang/lib/CodeGen/CMakeLists.txt index 9fab15abe6404..da98848e3b443 100644 --- a/clang/lib/CodeGen/CMakeLists.txt +++ b/clang/lib/CodeGen/CMakeLists.txt @@ -11,6 +11,7 @@ set(LLVM_LINK_COMPONENTS Extensions FrontendHLSL FrontendOpenMP + FrontendOffloading HIPStdPar IPO IRPrinter @@ -31,6 +32,26 @@ set(LLVM_LINK_COMPONENTS TransformUtils ) +# Workaround for MSVC ARM64 performance regression: +# https://developercommunity.visualstudio.com/t/Compiling-a-specific-code-for-ARM64-with/10444970 +# Since /O1 and /O2 represent a set of optimizations, +# our goal is to disable the /Og flag while retaining the other optimizations from the /O1|/O2 set +if(MSVC AND NOT CMAKE_CXX_COMPILER_ID MATCHES Clang + AND MSVC_VERSION VERSION_GREATER_EQUAL 1932 + AND CMAKE_SYSTEM_PROCESSOR MATCHES "ARM64") + + string(TOUPPER "${CMAKE_BUILD_TYPE}" uppercase_CMAKE_BUILD_TYPE) + string(REGEX MATCHALL "/[Oo][12]" opt_flags "${CMAKE_CXX_FLAGS} ${CMAKE_CXX_FLAGS_${uppercase_CMAKE_BUILD_TYPE}}") + if (opt_flags) + if(opt_flags MATCHES "1$") + set(opt_flags "/Od;/Os;/Oy;/Ob2;/GF;/Gy") + elseif (opt_flags MATCHES "2$") + set(opt_flags "/Od;/Oi;/Ot;/Oy;/Ob2;/GF;/Gy") + endif() + set_source_files_properties(CGBuiltin.cpp PROPERTIES COMPILE_OPTIONS "${opt_flags}") + endif() +endif() + add_clang_library(clangCodeGen ABIInfo.cpp ABIInfoImpl.cpp diff --git a/clang/lib/CodeGen/CodeGenModule.h b/clang/lib/CodeGen/CodeGenModule.h index 073b471c6e3cc..793861f23b15f 100644 --- a/clang/lib/CodeGen/CodeGenModule.h +++ b/clang/lib/CodeGen/CodeGenModule.h @@ -1543,15 +1543,23 @@ class CodeGenModule : public CodeGenTypeCache { void moveLazyEmissionStates(CodeGenModule *NewBuilder); /// Emit the IR encoding to attach the CUDA launch bounds attribute to \p F. + /// If \p MaxThreadsVal is not nullptr, the max threads value is stored in it, + /// if a valid one was found. void handleCUDALaunchBoundsAttr(llvm::Function *F, - const CUDALaunchBoundsAttr *A); + const CUDALaunchBoundsAttr *A, + int32_t *MaxThreadsVal = nullptr, + int32_t *MinBlocksVal = nullptr, + int32_t *MaxClusterRankVal = nullptr); /// Emit the IR encoding to attach the AMD GPU flat-work-group-size attribute /// to \p F. Alternatively, the work group size can be taken from a \p - /// ReqdWGS. + /// ReqdWGS. If \p MinThreadsVal is not nullptr, the min threads value is + /// stored in it, if a valid one was found. If \p MaxThreadsVal is not + /// nullptr, the max threads value is stored in it, if a valid one was found. void handleAMDGPUFlatWorkGroupSizeAttr( llvm::Function *F, const AMDGPUFlatWorkGroupSizeAttr *A, - const ReqdWorkGroupSizeAttr *ReqdWGS = nullptr); + const ReqdWorkGroupSizeAttr *ReqdWGS = nullptr, + int32_t *MinThreadsVal = nullptr, int32_t *MaxThreadsVal = nullptr); /// Emit the IR encoding to attach the AMD GPU waves-per-eu attribute to \p F. void handleAMDGPUWavesPerEUAttr(llvm::Function *F, diff --git a/clang/lib/CodeGen/MicrosoftCXXABI.cpp b/clang/lib/CodeGen/MicrosoftCXXABI.cpp index d623f8f63ae56..b6f941052abee 100644 --- a/clang/lib/CodeGen/MicrosoftCXXABI.cpp +++ b/clang/lib/CodeGen/MicrosoftCXXABI.cpp @@ -4449,7 +4449,7 @@ void MicrosoftCXXABI::emitThrow(CodeGenFunction &CGF, const CXXThrowExpr *E) { // Call into the runtime to throw the exception. llvm::Value *Args[] = { - CGF.Builder.CreateBitCast(AI.getPointer(), CGM.Int8PtrTy), + AI.getPointer(), TI }; CGF.EmitNoreturnRuntimeCallOrInvoke(getThrowFn(), Args); diff --git a/clang/lib/CodeGen/SwiftCallingConv.cpp b/clang/lib/CodeGen/SwiftCallingConv.cpp index 055dd37043866..16fbf52a517db 100644 --- a/clang/lib/CodeGen/SwiftCallingConv.cpp +++ b/clang/lib/CodeGen/SwiftCallingConv.cpp @@ -409,9 +409,10 @@ void SwiftAggLowering::splitVectorEntry(unsigned index) { CharUnits begin = Entries[index].Begin; for (unsigned i = 0; i != numElts; ++i) { - Entries[index].Type = eltTy; - Entries[index].Begin = begin; - Entries[index].End = begin + eltSize; + unsigned idx = index + i; + Entries[idx].Type = eltTy; + Entries[idx].Begin = begin; + Entries[idx].End = begin + eltSize; begin += eltSize; } } diff --git a/clang/lib/CodeGen/Targets/AMDGPU.cpp b/clang/lib/CodeGen/Targets/AMDGPU.cpp index f6a614b3e4d54..0411846cf9b02 100644 --- a/clang/lib/CodeGen/Targets/AMDGPU.cpp +++ b/clang/lib/CodeGen/Targets/AMDGPU.cpp @@ -594,7 +594,8 @@ llvm::Value *AMDGPUTargetCodeGenInfo::createEnqueuedBlockKernel( void CodeGenModule::handleAMDGPUFlatWorkGroupSizeAttr( llvm::Function *F, const AMDGPUFlatWorkGroupSizeAttr *FlatWGS, - const ReqdWorkGroupSizeAttr *ReqdWGS) { + const ReqdWorkGroupSizeAttr *ReqdWGS, int32_t *MinThreadsVal, + int32_t *MaxThreadsVal) { unsigned Min = 0; unsigned Max = 0; if (FlatWGS) { @@ -607,8 +608,13 @@ void CodeGenModule::handleAMDGPUFlatWorkGroupSizeAttr( if (Min != 0) { assert(Min <= Max && "Min must be less than or equal Max"); + if (MinThreadsVal) + *MinThreadsVal = Min; + if (MaxThreadsVal) + *MaxThreadsVal = Max; std::string AttrVal = llvm::utostr(Min) + "," + llvm::utostr(Max); - F->addFnAttr("amdgpu-flat-work-group-size", AttrVal); + if (F) + F->addFnAttr("amdgpu-flat-work-group-size", AttrVal); } else assert(Max == 0 && "Max must be zero"); } diff --git a/clang/lib/CodeGen/Targets/NVPTX.cpp b/clang/lib/CodeGen/Targets/NVPTX.cpp index 64d019a10514d..d0dc7c258a03a 100644 --- a/clang/lib/CodeGen/Targets/NVPTX.cpp +++ b/clang/lib/CodeGen/Targets/NVPTX.cpp @@ -287,14 +287,23 @@ bool NVPTXTargetCodeGenInfo::shouldEmitStaticExternCAliases() const { } } -void CodeGenModule::handleCUDALaunchBoundsAttr( - llvm::Function *F, const CUDALaunchBoundsAttr *Attr) { +void CodeGenModule::handleCUDALaunchBoundsAttr(llvm::Function *F, + const CUDALaunchBoundsAttr *Attr, + int32_t *MaxThreadsVal, + int32_t *MinBlocksVal, + int32_t *MaxClusterRankVal) { // Create !{, metadata !"maxntidx", i32 } node llvm::APSInt MaxThreads(32); MaxThreads = Attr->getMaxThreads()->EvaluateKnownConstInt(getContext()); - if (MaxThreads > 0) - NVPTXTargetCodeGenInfo::addNVVMMetadata(F, "maxntidx", - MaxThreads.getExtValue()); + if (MaxThreads > 0) { + if (MaxThreadsVal) + *MaxThreadsVal = MaxThreads.getExtValue(); + if (F) { + // Create !{, metadata !"maxntidx", i32 } node + NVPTXTargetCodeGenInfo::addNVVMMetadata(F, "maxntidx", + MaxThreads.getExtValue()); + } + } // min and max blocks is an optional argument for CUDALaunchBoundsAttr. If it // was not specified in __launch_bounds__ or if the user specified a 0 value, @@ -302,18 +311,28 @@ void CodeGenModule::handleCUDALaunchBoundsAttr( if (Attr->getMinBlocks()) { llvm::APSInt MinBlocks(32); MinBlocks = Attr->getMinBlocks()->EvaluateKnownConstInt(getContext()); - if (MinBlocks > 0) - // Create !{, metadata !"minctasm", i32 } node - NVPTXTargetCodeGenInfo::addNVVMMetadata(F, "minctasm", - MinBlocks.getExtValue()); + if (MinBlocks > 0) { + if (MinBlocksVal) + *MinBlocksVal = MinBlocks.getExtValue(); + if (F) { + // Create !{, metadata !"minctasm", i32 } node + NVPTXTargetCodeGenInfo::addNVVMMetadata(F, "minctasm", + MinBlocks.getExtValue()); + } + } } if (Attr->getMaxBlocks()) { llvm::APSInt MaxBlocks(32); MaxBlocks = Attr->getMaxBlocks()->EvaluateKnownConstInt(getContext()); - if (MaxBlocks > 0) - // Create !{, metadata !"maxclusterrank", i32 } node - NVPTXTargetCodeGenInfo::addNVVMMetadata(F, "maxclusterrank", - MaxBlocks.getExtValue()); + if (MaxBlocks > 0) { + if (MaxClusterRankVal) + *MaxClusterRankVal = MaxBlocks.getExtValue(); + if (F) { + // Create !{, metadata !"maxclusterrank", i32 } node + NVPTXTargetCodeGenInfo::addNVVMMetadata(F, "maxclusterrank", + MaxBlocks.getExtValue()); + } + } } } diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp index f5fd900a6447f..bbbb30ae2201a 100644 --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -2593,7 +2593,7 @@ void Driver::BuildInputs(const ToolChain &TC, DerivedArgList &Args, // Warn -x after last input file has no effect auto LastXArg = Args.getLastArgValue(options::OPT_x); const llvm::StringSet<> ValidXArgs = {"cuda", "hip", "cui", "hipi"}; - if (!IsCLMode() || ValidXArgs.find(LastXArg) != ValidXArgs.end()) { + if (!IsCLMode() || ValidXArgs.contains(LastXArg)) { Arg *LastXArg = Args.getLastArgNoClaim(options::OPT_x); Arg *LastInputArg = Args.getLastArgNoClaim(options::OPT_INPUT); if (LastXArg && LastInputArg && diff --git a/clang/lib/Driver/Multilib.cpp b/clang/lib/Driver/Multilib.cpp index ba466af39e2dc..48a494d9fa38d 100644 --- a/clang/lib/Driver/Multilib.cpp +++ b/clang/lib/Driver/Multilib.cpp @@ -122,9 +122,8 @@ MultilibSet::expandFlags(const Multilib::flags_list &InFlags) const { const llvm::Regex Regex(RegexString); assert(Regex.isValid()); - if (llvm::find_if(InFlags, [&Regex](StringRef F) { - return Regex.match(F); - }) != InFlags.end()) { + if (llvm::any_of(InFlags, + [&Regex](StringRef F) { return Regex.match(F); })) { Result.insert(M.Flags.begin(), M.Flags.end()); } } diff --git a/clang/lib/Driver/ToolChains/AIX.h b/clang/lib/Driver/ToolChains/AIX.h index 04f9b2240999c..755d87e07ec50 100644 --- a/clang/lib/Driver/ToolChains/AIX.h +++ b/clang/lib/Driver/ToolChains/AIX.h @@ -19,7 +19,7 @@ namespace tools { /// Directly call system default assembler and linker. namespace aix { -class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { +class LLVM_LIBRARY_VISIBILITY Assembler final : public Tool { public: Assembler(const ToolChain &TC) : Tool("aix::Assembler", "assembler", TC) {} @@ -31,7 +31,7 @@ class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { const char *LinkingOutput) const override; }; -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("aix::Linker", "linker", TC) {} diff --git a/clang/lib/Driver/ToolChains/AMDGPU.cpp b/clang/lib/Driver/ToolChains/AMDGPU.cpp index d4b33ad551c43..cad206ea4df1b 100644 --- a/clang/lib/Driver/ToolChains/AMDGPU.cpp +++ b/clang/lib/Driver/ToolChains/AMDGPU.cpp @@ -951,7 +951,8 @@ RocmInstallationDetector::getCommonBitcodeLibs( auto AddBCLib = [&](StringRef BCFile) { BCLibs.push_back(BCFile.str()); }; AddBCLib(getOCMLPath()); - AddBCLib(getOCKLPath()); + if (!isOpenMP) + AddBCLib(getOCKLPath()); AddBCLib(getDenormalsAreZeroPath(DAZ)); AddBCLib(getUnsafeMathPath(UnsafeMathOpt || FastRelaxedMath)); AddBCLib(getFiniteOnlyPath(FiniteOnly || FastRelaxedMath)); diff --git a/clang/lib/Driver/ToolChains/AMDGPU.h b/clang/lib/Driver/ToolChains/AMDGPU.h index d10d487dd44c5..b3361b1e36079 100644 --- a/clang/lib/Driver/ToolChains/AMDGPU.h +++ b/clang/lib/Driver/ToolChains/AMDGPU.h @@ -26,7 +26,7 @@ namespace driver { namespace tools { namespace amdgpu { -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("amdgpu::Linker", "ld.lld", TC) {} bool isLinkJob() const override { return true; } diff --git a/clang/lib/Driver/ToolChains/AVR.h b/clang/lib/Driver/ToolChains/AVR.h index d432d81744b92..247188b7eaad7 100644 --- a/clang/lib/Driver/ToolChains/AVR.h +++ b/clang/lib/Driver/ToolChains/AVR.h @@ -49,7 +49,7 @@ class LLVM_LIBRARY_VISIBILITY AVRToolChain : public Generic_ELF { namespace tools { namespace AVR { -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const llvm::Triple &Triple, const ToolChain &TC) : Tool("AVR::Linker", "avr-ld", TC), Triple(Triple) {} diff --git a/clang/lib/Driver/ToolChains/BareMetal.h b/clang/lib/Driver/ToolChains/BareMetal.h index fc39a2a10e019..f602ef2be3542 100644 --- a/clang/lib/Driver/ToolChains/BareMetal.h +++ b/clang/lib/Driver/ToolChains/BareMetal.h @@ -98,7 +98,7 @@ class LLVM_LIBRARY_VISIBILITY StaticLibTool : public Tool { const char *LinkingOutput) const override; }; -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("baremetal::Linker", "ld.lld", TC) {} bool isLinkJob() const override { return true; } diff --git a/clang/lib/Driver/ToolChains/CSKYToolChain.h b/clang/lib/Driver/ToolChains/CSKYToolChain.h index 52b37539cc5f1..a57324a426416 100644 --- a/clang/lib/Driver/ToolChains/CSKYToolChain.h +++ b/clang/lib/Driver/ToolChains/CSKYToolChain.h @@ -44,7 +44,7 @@ class LLVM_LIBRARY_VISIBILITY CSKYToolChain : public Generic_ELF { namespace tools { namespace CSKY { -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("CSKY::Linker", "ld", TC) {} bool hasIntegratedCPP() const override { return false; } diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index 94c184435ae14..43a92adbef64b 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -1067,6 +1067,35 @@ static void handleAMDGPUCodeObjectVersionOptions(const Driver &D, } } +static bool hasClangPchSignature(const Driver &D, StringRef Path) { + if (llvm::ErrorOr> MemBuf = + D.getVFS().getBufferForFile(Path)) + return (*MemBuf)->getBuffer().startswith("CPCH"); + return false; +} + +static bool gchProbe(const Driver &D, StringRef Path) { + llvm::ErrorOr Status = D.getVFS().status(Path); + if (!Status) + return false; + + if (Status->isDirectory()) { + std::error_code EC; + for (llvm::vfs::directory_iterator DI = D.getVFS().dir_begin(Path, EC), DE; + !EC && DI != DE; DI = DI.increment(EC)) { + if (hasClangPchSignature(D, DI->path())) + return true; + } + D.Diag(diag::warn_drv_pch_ignoring_gch_dir) << Path; + return false; + } + + if (hasClangPchSignature(D, Path)) + return true; + D.Diag(diag::warn_drv_pch_ignoring_gch_file) << Path; + return false; +} + void Clang::AddPreprocessingOptions(Compilation &C, const JobAction &JA, const Driver &D, const ArgList &Args, ArgStringList &CmdArgs, @@ -1283,11 +1312,9 @@ void Clang::AddPreprocessingOptions(Compilation &C, const JobAction &JA, FoundPCH = true; if (!FoundPCH) { + // For GCC compat, probe for a file or directory ending in .gch instead. llvm::sys::path::replace_extension(P, "gch"); - if (D.getVFS().exists(P)) { - FoundPCH = true; - D.Diag(diag::warn_drv_include_probe_gch) << A->getAsString(Args) << P; - } + FoundPCH = gchProbe(D, P.str()); } if (FoundPCH) { @@ -3724,20 +3751,10 @@ bool Driver::getDefaultModuleCachePath(SmallVectorImpl &Result) { static bool RenderModulesOptions(Compilation &C, const Driver &D, const ArgList &Args, const InputInfo &Input, - const InputInfo &Output, const Arg *Std, + const InputInfo &Output, bool HaveStd20, ArgStringList &CmdArgs) { bool IsCXX = types::isCXX(Input.getType()); - // FIXME: Find a better way to determine whether the input has standard c++ - // modules support by default. - bool HaveStdCXXModules = - IsCXX && Std && - (Std->containsValue("c++2a") || Std->containsValue("gnu++2a") || - Std->containsValue("c++20") || Std->containsValue("gnu++20") || - Std->containsValue("c++2b") || Std->containsValue("gnu++2b") || - Std->containsValue("c++23") || Std->containsValue("gnu++23") || - Std->containsValue("c++2c") || Std->containsValue("gnu++2c") || - Std->containsValue("c++26") || Std->containsValue("gnu++26") || - Std->containsValue("c++latest") || Std->containsValue("gnu++latest")); + bool HaveStdCXXModules = IsCXX && HaveStd20; bool HaveModules = HaveStdCXXModules; // -fmodules enables the use of precompiled modules (off by default). @@ -5244,11 +5261,9 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, auto findMacroDefinition = [&](const std::string &Macro) { auto MacroDefs = Args.getAllArgValues(options::OPT_D); - return std::find_if(MacroDefs.begin(), MacroDefs.end(), - [&](const std::string &M) { - return M == Macro || - M.find(Macro + '=') != std::string::npos; - }) != MacroDefs.end(); + return llvm::any_of(MacroDefs, [&](const std::string &M) { + return M == Macro || M.find(Macro + '=') != std::string::npos; + }); }; // _UNIX03_WITHDRAWN is required for libcxx & porting. @@ -5707,18 +5722,33 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, if (Arg *A = Args.getLastArg(options::OPT_mcmodel_EQ)) { StringRef CM = A->getValue(); - if (CM == "small" || CM == "kernel" || CM == "medium" || CM == "large" || - CM == "tiny") { - if (Triple.isOSAIX() && CM == "medium") - CmdArgs.push_back("-mcmodel=large"); - else if (Triple.isAArch64() && (CM == "kernel" || CM == "medium")) - D.Diag(diag::err_drv_invalid_argument_to_option) - << CM << A->getOption().getName(); - else - A->render(Args, CmdArgs); + bool Ok = false; + if (Triple.isOSAIX() && CM == "medium") { + CM = "large"; + Ok = true; + } + if (Triple.isAArch64(64)) { + Ok = CM == "tiny" || CM == "small" || CM == "large"; + if (CM == "large" && RelocationModel != llvm::Reloc::Static) + D.Diag(diag::err_drv_argument_only_allowed_with) + << A->getAsString(Args) << "-fno-pic"; + } else if (Triple.isPPC64()) { + Ok = CM == "small" || CM == "medium" || CM == "large"; + } else if (Triple.isRISCV()) { + if (CM == "medlow") + CM = "small"; + else if (CM == "medany") + CM = "medium"; + Ok = CM == "small" || CM == "medium"; + } else if (Triple.getArch() == llvm::Triple::x86_64) { + Ok = llvm::is_contained({"small", "kernel", "medium", "large", "tiny"}, + CM); + } + if (Ok) { + CmdArgs.push_back(Args.MakeArgString("-mcmodel=" + CM)); } else { - D.Diag(diag::err_drv_invalid_argument_to_option) - << CM << A->getOption().getName(); + D.Diag(diag::err_drv_unsupported_option_argument_for_target) + << A->getSpelling() << CM << TripleStr; } } @@ -6842,14 +6872,6 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, (!IsWindowsMSVC || IsMSVC2015Compatible))) CmdArgs.push_back("-fno-threadsafe-statics"); - // -fno-delayed-template-parsing is default, except when targeting MSVC. - // Many old Windows SDK versions require this to parse. - // FIXME: MSVC introduced /Zc:twoPhase- to disable this behavior in their - // compiler. We should be able to disable this by default at some point. - if (Args.hasFlag(options::OPT_fdelayed_template_parsing, - options::OPT_fno_delayed_template_parsing, IsWindowsMSVC)) - CmdArgs.push_back("-fdelayed-template-parsing"); - // -fgnu-keywords default varies depending on language; only pass if // specified. Args.AddLastArg(CmdArgs, options::OPT_fgnu_keywords, @@ -6870,8 +6892,38 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, Args.AddLastArg(CmdArgs, options::OPT_finline_max_stacksize_EQ); + // FIXME: Find a better way to determine whether we are in C++20. + bool HaveCxx20 = + Std && + (Std->containsValue("c++2a") || Std->containsValue("gnu++2a") || + Std->containsValue("c++20") || Std->containsValue("gnu++20") || + Std->containsValue("c++2b") || Std->containsValue("gnu++2b") || + Std->containsValue("c++23") || Std->containsValue("gnu++23") || + Std->containsValue("c++2c") || Std->containsValue("gnu++2c") || + Std->containsValue("c++26") || Std->containsValue("gnu++26") || + Std->containsValue("c++latest") || Std->containsValue("gnu++latest")); bool HaveModules = - RenderModulesOptions(C, D, Args, Input, Output, Std, CmdArgs); + RenderModulesOptions(C, D, Args, Input, Output, HaveCxx20, CmdArgs); + + // -fdelayed-template-parsing is default when targeting MSVC. + // Many old Windows SDK versions require this to parse. + // + // According to + // https://learn.microsoft.com/en-us/cpp/build/reference/permissive-standards-conformance?view=msvc-170, + // MSVC actually defaults to -fno-delayed-template-parsing (/Zc:twoPhase- + // with MSVC CLI) if using C++20. So we match the behavior with MSVC here to + // not enable -fdelayed-template-parsing by default after C++20. + // + // FIXME: Given -fdelayed-template-parsing is a source of bugs, we should be + // able to disable this by default at some point. + if (Args.hasFlag(options::OPT_fdelayed_template_parsing, + options::OPT_fno_delayed_template_parsing, + IsWindowsMSVC && !HaveCxx20)) { + if (HaveCxx20) + D.Diag(clang::diag::warn_drv_delayed_template_parsing_after_cxx20); + + CmdArgs.push_back("-fdelayed-template-parsing"); + } if (Args.hasFlag(options::OPT_fpch_validate_input_files_content, options::OPT_fno_pch_validate_input_files_content, false)) diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp index 25fd940584624..ad012d3d0d4b4 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.cpp +++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp @@ -694,6 +694,16 @@ void tools::addLTOOptions(const ToolChain &ToolChain, const ArgList &Args, CmdArgs.push_back(Args.MakeArgString(Twine(PluginOptPrefix) + ParallelismOpt + Parallelism)); + // Pass down GlobalISel options. + if (Arg *A = Args.getLastArg(options::OPT_fglobal_isel, + options::OPT_fno_global_isel)) { + // Parsing -fno-global-isel explicitly gives architectures that enable GISel + // by default a chance to disable it. + CmdArgs.push_back(Args.MakeArgString( + Twine(PluginOptPrefix) + "-global-isel=" + + (A->getOption().matches(options::OPT_fglobal_isel) ? "1" : "0"))); + } + // If an explicit debugger tuning argument appeared, pass it along. if (Arg *A = Args.getLastArg(options::OPT_gTune_Group, options::OPT_ggdbN_Group)) { @@ -2041,10 +2051,11 @@ void tools::addX86AlignBranchArgs(const Driver &D, const ArgList &Args, /// convention has been to use the prefix “lib”. To avoid confusion with host /// archive libraries, we use prefix "libbc-" for the bitcode SDL archives. /// -bool tools::SDLSearch(const Driver &D, const llvm::opt::ArgList &DriverArgs, +static bool SDLSearch(const Driver &D, const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args, - SmallVector LibraryPaths, std::string Lib, - StringRef Arch, StringRef Target, bool isBitCodeSDL) { + const SmallVectorImpl &LibraryPaths, + StringRef Lib, StringRef Arch, StringRef Target, + bool isBitCodeSDL) { SmallVector SDLs; std::string LibDeviceLoc = "/libdevice"; @@ -2118,15 +2129,16 @@ bool tools::SDLSearch(const Driver &D, const llvm::opt::ArgList &DriverArgs, /// the library paths. If so, add a new command to clang-offload-bundler to /// unbundle this archive and create a temporary device specific archive. Name /// of this SDL is passed to the llvm-link tool. -bool tools::GetSDLFromOffloadArchive( +static void GetSDLFromOffloadArchive( Compilation &C, const Driver &D, const Tool &T, const JobAction &JA, const InputInfoList &Inputs, const llvm::opt::ArgList &DriverArgs, - llvm::opt::ArgStringList &CC1Args, SmallVector LibraryPaths, - StringRef Lib, StringRef Arch, StringRef Target, bool isBitCodeSDL) { + llvm::opt::ArgStringList &CC1Args, + const SmallVectorImpl &LibraryPaths, StringRef Lib, + StringRef Arch, StringRef Target, bool isBitCodeSDL) { // We don't support bitcode archive bundles for nvptx if (isBitCodeSDL && Arch.contains("nvptx")) - return false; + return; bool FoundAOB = false; std::string ArchiveOfBundles; @@ -2144,7 +2156,6 @@ bool tools::GetSDLFromOffloadArchive( Lib = Lib.drop_front(2); for (auto LPath : LibraryPaths) { ArchiveOfBundles.clear(); - SmallVector AOBFileNames; auto LibFile = (Lib.startswith(":") ? Lib.drop_front() : IsMSVC ? Lib + Ext : "lib" + Lib + Ext) @@ -2163,12 +2174,12 @@ bool tools::GetSDLFromOffloadArchive( } if (!FoundAOB) - return false; + return; llvm::file_magic Magic; auto EC = llvm::identify_magic(ArchiveOfBundles, Magic); if (EC || Magic != llvm::file_magic::archive) - return false; + return; StringRef Prefix = isBitCodeSDL ? "libbc-" : "lib"; std::string OutputLib = @@ -2223,7 +2234,7 @@ bool tools::GetSDLFromOffloadArchive( CC1Args.push_back(DriverArgs.MakeArgString(OutputLib)); - return true; + return; } // Wrapper function used by driver for adding SDLs during link phase. @@ -2295,7 +2306,7 @@ void tools::AddStaticDeviceLibs(Compilation *C, const Tool *T, static const StringRef HostOnlyArchives[] = { "omp", "cudart", "m", "gcc", "gcc_s", "pthread", "hip_hcc"}; for (auto SDLName : DriverArgs.getAllArgValues(options::OPT_l)) { - if (!HostOnlyArchives->contains(SDLName)) { + if (!llvm::is_contained(HostOnlyArchives, SDLName)) { SDLNames.insert(std::string("-l") + SDLName); } } diff --git a/clang/lib/Driver/ToolChains/CommonArgs.h b/clang/lib/Driver/ToolChains/CommonArgs.h index 096152bfbdcf6..f364c9793c9be 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.h +++ b/clang/lib/Driver/ToolChains/CommonArgs.h @@ -66,19 +66,6 @@ void AddStaticDeviceLibs(Compilation *C, const Tool *T, const JobAction *JA, llvm::opt::ArgStringList &CmdArgs, StringRef Arch, StringRef Target, bool isBitCodeSDL); -bool SDLSearch(const Driver &D, const llvm::opt::ArgList &DriverArgs, - llvm::opt::ArgStringList &CmdArgs, - SmallVector LibraryPaths, std::string Lib, - StringRef Arch, StringRef Target, bool isBitCodeSDL); - -bool GetSDLFromOffloadArchive(Compilation &C, const Driver &D, const Tool &T, - const JobAction &JA, const InputInfoList &Inputs, - const llvm::opt::ArgList &DriverArgs, - llvm::opt::ArgStringList &CC1Args, - SmallVector LibraryPaths, - StringRef Lib, StringRef Arch, StringRef Target, - bool isBitCodeSDL); - const char *SplitDebugName(const JobAction &JA, const llvm::opt::ArgList &Args, const InputInfo &Input, const InputInfo &Output); diff --git a/clang/lib/Driver/ToolChains/CrossWindows.h b/clang/lib/Driver/ToolChains/CrossWindows.h index 0ba17bc3e305c..c5df55a24296f 100644 --- a/clang/lib/Driver/ToolChains/CrossWindows.h +++ b/clang/lib/Driver/ToolChains/CrossWindows.h @@ -20,7 +20,7 @@ namespace driver { namespace tools { namespace CrossWindows { -class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { +class LLVM_LIBRARY_VISIBILITY Assembler final : public Tool { public: Assembler(const ToolChain &TC) : Tool("CrossWindows::Assembler", "as", TC) {} @@ -32,7 +32,7 @@ class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { const char *LinkingOutput) const override; }; -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("CrossWindows::Linker", "ld", TC) {} diff --git a/clang/lib/Driver/ToolChains/Cuda.h b/clang/lib/Driver/ToolChains/Cuda.h index f7c0c7ea1c98c..8a053f3393e12 100644 --- a/clang/lib/Driver/ToolChains/Cuda.h +++ b/clang/lib/Driver/ToolChains/Cuda.h @@ -81,7 +81,7 @@ namespace tools { namespace NVPTX { // Run ptxas, the NVPTX assembler. -class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { +class LLVM_LIBRARY_VISIBILITY Assembler final : public Tool { public: Assembler(const ToolChain &TC) : Tool("NVPTX::Assembler", "ptxas", TC) {} @@ -108,7 +108,7 @@ class LLVM_LIBRARY_VISIBILITY FatBinary : public Tool { }; // Runs nvlink, which links GPU object files ("cubin" files) into a single file. -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("NVPTX::Linker", "nvlink", TC) {} diff --git a/clang/lib/Driver/ToolChains/Darwin.cpp b/clang/lib/Driver/ToolChains/Darwin.cpp index 15b9889157b90..f28e08d81bf29 100644 --- a/clang/lib/Driver/ToolChains/Darwin.cpp +++ b/clang/lib/Driver/ToolChains/Darwin.cpp @@ -1400,7 +1400,7 @@ void Darwin::addProfileRTLibs(const ArgList &Args, addExportedSymbol(CmdArgs, "_reset_fn_list"); } - // Align __llvm_prf_{cnts,data} sections to the maximum expected page + // Align __llvm_prf_{cnts,bits,data} sections to the maximum expected page // alignment. This allows profile counters to be mmap()'d to disk. Note that // it's not enough to just page-align __llvm_prf_cnts: the following section // must also be page-aligned so that its data is not clobbered by mmap(). @@ -1410,7 +1410,7 @@ void Darwin::addProfileRTLibs(const ArgList &Args, // extra alignment also allows the same binary to be used with/without sync // enabled. if (!ForGCOV) { - for (auto IPSK : {llvm::IPSK_cnts, llvm::IPSK_data}) { + for (auto IPSK : {llvm::IPSK_cnts, llvm::IPSK_bitmap, llvm::IPSK_data}) { addSectalignToPage( Args, CmdArgs, "__DATA", llvm::getInstrProfSectionName(IPSK, llvm::Triple::MachO, diff --git a/clang/lib/Driver/ToolChains/DragonFly.cpp b/clang/lib/Driver/ToolChains/DragonFly.cpp index 3778c7773b6b9..ed7f751adc0ef 100644 --- a/clang/lib/Driver/ToolChains/DragonFly.cpp +++ b/clang/lib/Driver/ToolChains/DragonFly.cpp @@ -20,21 +20,19 @@ using namespace clang::driver::toolchains; using namespace clang; using namespace llvm::opt; -/// DragonFly Tools - -// For now, DragonFly Assemble does just about the same as for -// FreeBSD, but this may change soon. void dragonfly::Assembler::ConstructJob(Compilation &C, const JobAction &JA, const InputInfo &Output, const InputInfoList &Inputs, const ArgList &Args, const char *LinkingOutput) const { - claimNoWarnArgs(Args); + const auto &ToolChain = static_cast(getToolChain()); ArgStringList CmdArgs; + claimNoWarnArgs(Args); + // When building 32-bit code on DragonFly/pc64, we have to explicitly // instruct as in the base system to assemble 32-bit code. - if (getToolChain().getArch() == llvm::Triple::x86) + if (ToolChain.getArch() == llvm::Triple::x86) CmdArgs.push_back("--32"); Args.AddAllArgValues(CmdArgs, options::OPT_Wa_COMMA, options::OPT_Xassembler); @@ -45,7 +43,7 @@ void dragonfly::Assembler::ConstructJob(Compilation &C, const JobAction &JA, for (const auto &II : Inputs) CmdArgs.push_back(II.getFilename()); - const char *Exec = Args.MakeArgString(getToolChain().GetProgramPath("as")); + const char *Exec = Args.MakeArgString(ToolChain.GetProgramPath("as")); C.addCommand(std::make_unique(JA, *this, ResponseFileSupport::AtFileCurCP(), Exec, CmdArgs, Inputs, Output)); @@ -58,18 +56,23 @@ void dragonfly::Linker::ConstructJob(Compilation &C, const JobAction &JA, const char *LinkingOutput) const { const auto &ToolChain = static_cast(getToolChain()); const Driver &D = ToolChain.getDriver(); + const llvm::Triple::ArchType Arch = ToolChain.getArch(); ArgStringList CmdArgs; + bool Static = Args.hasArg(options::OPT_static); + bool Shared = Args.hasArg(options::OPT_shared); + bool Profiling = Args.hasArg(options::OPT_pg); + bool Pie = Args.hasArg(options::OPT_pie); if (!D.SysRoot.empty()) CmdArgs.push_back(Args.MakeArgString("--sysroot=" + D.SysRoot)); CmdArgs.push_back("--eh-frame-hdr"); - if (Args.hasArg(options::OPT_static)) { + if (Static) { CmdArgs.push_back("-Bstatic"); } else { if (Args.hasArg(options::OPT_rdynamic)) CmdArgs.push_back("-export-dynamic"); - if (Args.hasArg(options::OPT_shared)) + if (Shared) CmdArgs.push_back("-shared"); else if (!Args.hasArg(options::OPT_r)) { CmdArgs.push_back("-dynamic-linker"); @@ -81,7 +84,7 @@ void dragonfly::Linker::ConstructJob(Compilation &C, const JobAction &JA, // When building 32-bit code on DragonFly/pc64, we have to explicitly // instruct ld in the base system to link 32-bit code. - if (getToolChain().getArch() == llvm::Triple::x86) { + if (Arch == llvm::Triple::x86) { CmdArgs.push_back("-m"); CmdArgs.push_back("elf_i386"); } @@ -94,67 +97,76 @@ void dragonfly::Linker::ConstructJob(Compilation &C, const JobAction &JA, if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles, options::OPT_r)) { - if (!Args.hasArg(options::OPT_shared)) { - if (Args.hasArg(options::OPT_pg)) - CmdArgs.push_back( - Args.MakeArgString(getToolChain().GetFilePath("gcrt1.o"))); + const char *crt1 = nullptr; + const char *crtbegin = nullptr; + if (!Shared) { + if (Profiling) + crt1 = "gcrt1.o"; else { - if (Args.hasArg(options::OPT_pie)) - CmdArgs.push_back( - Args.MakeArgString(getToolChain().GetFilePath("Scrt1.o"))); + if (Pie) + crt1 = "Scrt1.o"; else - CmdArgs.push_back( - Args.MakeArgString(getToolChain().GetFilePath("crt1.o"))); + crt1 = "crt1.o"; } } - CmdArgs.push_back(Args.MakeArgString(getToolChain().GetFilePath("crti.o"))); - if (Args.hasArg(options::OPT_shared) || Args.hasArg(options::OPT_pie)) - CmdArgs.push_back( - Args.MakeArgString(getToolChain().GetFilePath("crtbeginS.o"))); + + if (Shared || Pie) + crtbegin = "crtbeginS.o"; else - CmdArgs.push_back( - Args.MakeArgString(getToolChain().GetFilePath("crtbegin.o"))); + crtbegin = "crtbegin.o"; + + if (crt1) + CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath(crt1))); + CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath("crti.o"))); + CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath(crtbegin))); } Args.addAllArgs(CmdArgs, {options::OPT_L, options::OPT_T_Group, options::OPT_s, options::OPT_t, options::OPT_r}); ToolChain.AddFilePathLibArgs(Args, CmdArgs); - AddLinkerInputs(getToolChain(), Inputs, Args, CmdArgs, JA); + AddLinkerInputs(ToolChain, Inputs, Args, CmdArgs, JA); if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nodefaultlibs, options::OPT_r)) { - if (!Args.hasArg(options::OPT_static)) { + if (!Static) { CmdArgs.push_back("-rpath"); CmdArgs.push_back("/usr/lib/gcc80"); } // Use the static OpenMP runtime with -static-openmp - bool StaticOpenMP = Args.hasArg(options::OPT_static_openmp) && - !Args.hasArg(options::OPT_static); + bool StaticOpenMP = Args.hasArg(options::OPT_static_openmp) && !Static; addOpenMPRuntime(CmdArgs, ToolChain, Args, StaticOpenMP); if (D.CCCIsCXX()) { - if (getToolChain().ShouldLinkCXXStdlib(Args)) - getToolChain().AddCXXStdlibLibArgs(Args, CmdArgs); + if (ToolChain.ShouldLinkCXXStdlib(Args)) + ToolChain.AddCXXStdlibLibArgs(Args, CmdArgs); + CmdArgs.push_back("-lm"); + } + + // Additional linker set-up and flags for Fortran. This is required in order + // to generate executables. As Fortran runtime depends on the C runtime, + // these dependencies need to be listed before the C runtime below (i.e. + // AddRunTimeLibs). + if (D.IsFlangMode()) { + addFortranRuntimeLibraryPath(ToolChain, Args, CmdArgs); + addFortranRuntimeLibs(ToolChain, CmdArgs); CmdArgs.push_back("-lm"); } if (Args.hasArg(options::OPT_pthread)) CmdArgs.push_back("-lpthread"); - if (!Args.hasArg(options::OPT_nolibc)) { + if (!Args.hasArg(options::OPT_nolibc)) CmdArgs.push_back("-lc"); - } - if (Args.hasArg(options::OPT_static) || - Args.hasArg(options::OPT_static_libgcc)) { + if (Static || Args.hasArg(options::OPT_static_libgcc)) { CmdArgs.push_back("-lgcc"); CmdArgs.push_back("-lgcc_eh"); } else { if (Args.hasArg(options::OPT_shared_libgcc)) { CmdArgs.push_back("-lgcc_pic"); - if (!Args.hasArg(options::OPT_shared)) + if (!Shared) CmdArgs.push_back("-lgcc"); } else { CmdArgs.push_back("-lgcc"); @@ -167,18 +179,19 @@ void dragonfly::Linker::ConstructJob(Compilation &C, const JobAction &JA, if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles, options::OPT_r)) { - if (Args.hasArg(options::OPT_shared) || Args.hasArg(options::OPT_pie)) - CmdArgs.push_back( - Args.MakeArgString(getToolChain().GetFilePath("crtendS.o"))); + const char *crtend = nullptr; + if (Shared || Pie) + crtend ="crtendS.o"; else - CmdArgs.push_back( - Args.MakeArgString(getToolChain().GetFilePath("crtend.o"))); - CmdArgs.push_back(Args.MakeArgString(getToolChain().GetFilePath("crtn.o"))); + crtend = "crtend.o"; + + CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath(crtend))); + CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath("crtn.o"))); } - getToolChain().addProfileRTLibs(Args, CmdArgs); + ToolChain.addProfileRTLibs(Args, CmdArgs); - const char *Exec = Args.MakeArgString(getToolChain().GetLinkerPath()); + const char *Exec = Args.MakeArgString(ToolChain.GetLinkerPath()); C.addCommand(std::make_unique(JA, *this, ResponseFileSupport::AtFileCurCP(), Exec, CmdArgs, Inputs, Output)); diff --git a/clang/lib/Driver/ToolChains/DragonFly.h b/clang/lib/Driver/ToolChains/DragonFly.h index 4dceb09a17364..715f6b45519ba 100644 --- a/clang/lib/Driver/ToolChains/DragonFly.h +++ b/clang/lib/Driver/ToolChains/DragonFly.h @@ -19,7 +19,7 @@ namespace tools { /// Directly call GNU Binutils assembler and linker namespace dragonfly { -class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { +class LLVM_LIBRARY_VISIBILITY Assembler final : public Tool { public: Assembler(const ToolChain &TC) : Tool("dragonfly::Assembler", "assembler", TC) {} @@ -32,7 +32,7 @@ class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { const char *LinkingOutput) const override; }; -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("dragonfly::Linker", "linker", TC) {} diff --git a/clang/lib/Driver/ToolChains/FreeBSD.cpp b/clang/lib/Driver/ToolChains/FreeBSD.cpp index 7a61159ba4a73..e7dcccc9e9fc4 100644 --- a/clang/lib/Driver/ToolChains/FreeBSD.cpp +++ b/clang/lib/Driver/ToolChains/FreeBSD.cpp @@ -88,8 +88,6 @@ void freebsd::Assembler::ConstructJob(Compilation &C, const JobAction &JA, CmdArgs.push_back("-meabi=5"); break; } - case llvm::Triple::sparc: - case llvm::Triple::sparcel: case llvm::Triple::sparcv9: { std::string CPU = getCPUName(D, Args, getToolChain().getTriple()); CmdArgs.push_back( @@ -131,8 +129,7 @@ void freebsd::Linker::ConstructJob(Compilation &C, const JobAction &JA, const InputInfoList &Inputs, const ArgList &Args, const char *LinkingOutput) const { - const toolchains::FreeBSD &ToolChain = - static_cast(getToolChain()); + const auto &ToolChain = static_cast(getToolChain()); const Driver &D = ToolChain.getDriver(); const llvm::Triple::ArchType Arch = ToolChain.getArch(); const bool IsPIE = @@ -167,7 +164,7 @@ void freebsd::Linker::ConstructJob(Compilation &C, const JobAction &JA, CmdArgs.push_back("/libexec/ld-elf.so.1"); } const llvm::Triple &T = ToolChain.getTriple(); - if (Arch == llvm::Triple::arm || Arch == llvm::Triple::sparc || T.isX86()) + if (Arch == llvm::Triple::arm || T.isX86()) CmdArgs.push_back("--hash-style=both"); CmdArgs.push_back("--enable-new-dtags"); } @@ -293,6 +290,20 @@ void freebsd::Linker::ConstructJob(Compilation &C, const JobAction &JA, else CmdArgs.push_back("-lm"); } + + // Additional linker set-up and flags for Fortran. This is required in order + // to generate executables. As Fortran runtime depends on the C runtime, + // these dependencies need to be listed before the C runtime below (i.e. + // AddRunTimeLibs). + if (D.IsFlangMode()) { + addFortranRuntimeLibraryPath(ToolChain, Args, CmdArgs); + addFortranRuntimeLibs(ToolChain, CmdArgs); + if (Profiling) + CmdArgs.push_back("-lm_p"); + else + CmdArgs.push_back("-lm"); + } + if (NeedsSanitizerDeps) linkSanitizerRuntimeDeps(ToolChain, Args, CmdArgs); if (NeedsXRayDeps) diff --git a/clang/lib/Driver/ToolChains/FreeBSD.h b/clang/lib/Driver/ToolChains/FreeBSD.h index 740274b314ba1..959cbf78ddc79 100644 --- a/clang/lib/Driver/ToolChains/FreeBSD.h +++ b/clang/lib/Driver/ToolChains/FreeBSD.h @@ -19,7 +19,7 @@ namespace tools { /// Directly call GNU Binutils assembler and linker namespace freebsd { -class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { +class LLVM_LIBRARY_VISIBILITY Assembler final : public Tool { public: Assembler(const ToolChain &TC) : Tool("freebsd::Assembler", "assembler", TC) {} @@ -32,7 +32,7 @@ class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { const char *LinkingOutput) const override; }; -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("freebsd::Linker", "linker", TC) {} diff --git a/clang/lib/Driver/ToolChains/Fuchsia.cpp b/clang/lib/Driver/ToolChains/Fuchsia.cpp index 300a57afd37af..00de63c155229 100644 --- a/clang/lib/Driver/ToolChains/Fuchsia.cpp +++ b/clang/lib/Driver/ToolChains/Fuchsia.cpp @@ -34,8 +34,7 @@ void fuchsia::Linker::ConstructJob(Compilation &C, const JobAction &JA, const InputInfoList &Inputs, const ArgList &Args, const char *LinkingOutput) const { - const toolchains::Fuchsia &ToolChain = - static_cast(getToolChain()); + const auto &ToolChain = static_cast(getToolChain()); const Driver &D = ToolChain.getDriver(); const llvm::Triple &Triple = ToolChain.getEffectiveTriple(); diff --git a/clang/lib/Driver/ToolChains/Fuchsia.h b/clang/lib/Driver/ToolChains/Fuchsia.h index 95e1785c9fac9..619968f585024 100644 --- a/clang/lib/Driver/ToolChains/Fuchsia.h +++ b/clang/lib/Driver/ToolChains/Fuchsia.h @@ -32,7 +32,7 @@ class LLVM_LIBRARY_VISIBILITY StaticLibTool : public Tool { const char *LinkingOutput) const override; }; -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("fuchsia::Linker", "ld.lld", TC) {} diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp index cdd911af9a733..5237951f84cce 100644 --- a/clang/lib/Driver/ToolChains/Gnu.cpp +++ b/clang/lib/Driver/ToolChains/Gnu.cpp @@ -376,8 +376,7 @@ void tools::gnutools::Linker::ConstructJob(Compilation &C, const JobAction &JA, // Generic_ELF, so the static_cast might return a reference to a invalid // instance (see PR45061). Ideally, the Linker constructor needs to take a // Generic_ELF instead. - const toolchains::Generic_ELF &ToolChain = - static_cast(getToolChain()); + const auto &ToolChain = static_cast(getToolChain()); const Driver &D = ToolChain.getDriver(); const llvm::Triple &Triple = getToolChain().getEffectiveTriple(); @@ -574,7 +573,7 @@ void tools::gnutools::Linker::ConstructJob(Compilation &C, const JobAction &JA, // Additional linker set-up and flags for Fortran. This is required in order // to generate executables. As Fortran runtime depends on the C runtime, // these dependencies need to be listed before the C runtime below (i.e. - // AddRuntTimeLibs). + // AddRunTimeLibs). if (D.IsFlangMode()) { addFortranRuntimeLibraryPath(ToolChain, Args, CmdArgs); addFortranRuntimeLibs(ToolChain, CmdArgs); @@ -2007,45 +2006,72 @@ Generic_GCC::GCCVersion Generic_GCC::GCCVersion::Parse(StringRef VersionText) { std::pair First = VersionText.split('.'); std::pair Second = First.second.split('.'); - GCCVersion GoodVersion = {VersionText.str(), -1, -1, -1, "", "", ""}; - if (First.first.getAsInteger(10, GoodVersion.Major) || GoodVersion.Major < 0) - return BadVersion; - GoodVersion.MajorStr = First.first.str(); - if (First.second.empty()) - return GoodVersion; + StringRef MajorStr = First.first; StringRef MinorStr = Second.first; - if (Second.second.empty()) { - if (size_t EndNumber = MinorStr.find_first_not_of("0123456789")) { - GoodVersion.PatchSuffix = std::string(MinorStr.substr(EndNumber)); - MinorStr = MinorStr.slice(0, EndNumber); - } - } - if (MinorStr.getAsInteger(10, GoodVersion.Minor) || GoodVersion.Minor < 0) - return BadVersion; - GoodVersion.MinorStr = MinorStr.str(); + StringRef PatchStr = Second.second; - // First look for a number prefix and parse that if present. Otherwise just - // stash the entire patch string in the suffix, and leave the number - // unspecified. This covers versions strings such as: - // 5 (handled above) + GCCVersion GoodVersion = {VersionText.str(), -1, -1, -1, "", "", ""}; + + // Parse version number strings such as: + // 5 // 4.4 // 4.4-patched // 4.4.0 // 4.4.x // 4.4.2-rc4 // 4.4.x-patched - // And retains any patch number it finds. - StringRef PatchText = Second.second; - if (!PatchText.empty()) { - if (size_t EndNumber = PatchText.find_first_not_of("0123456789")) { - // Try to parse the number and any suffix. - if (PatchText.slice(0, EndNumber).getAsInteger(10, GoodVersion.Patch) || - GoodVersion.Patch < 0) - return BadVersion; - GoodVersion.PatchSuffix = std::string(PatchText.substr(EndNumber)); + // 10-win32 + // Split on '.', handle 1, 2 or 3 such segments. Each segment must contain + // purely a number, except for the last one, where a non-number suffix + // is stored in PatchSuffix. The third segment is allowed to not contain + // a number at all. + + auto TryParseLastNumber = [&](StringRef Segment, int &Number, + std::string &OutStr) -> bool { + // Look for a number prefix and parse that, and split out any trailing + // string into GoodVersion.PatchSuffix. + + if (size_t EndNumber = Segment.find_first_not_of("0123456789")) { + StringRef NumberStr = Segment.slice(0, EndNumber); + if (NumberStr.getAsInteger(10, Number) || Number < 0) + return false; + OutStr = NumberStr; + GoodVersion.PatchSuffix = Segment.substr(EndNumber); + return true; } + return false; + }; + auto TryParseNumber = [](StringRef Segment, int &Number) -> bool { + if (Segment.getAsInteger(10, Number) || Number < 0) + return false; + return true; + }; + + if (MinorStr.empty()) { + // If no minor string, major is the last segment + if (!TryParseLastNumber(MajorStr, GoodVersion.Major, GoodVersion.MajorStr)) + return BadVersion; + return GoodVersion; } + if (!TryParseNumber(MajorStr, GoodVersion.Major)) + return BadVersion; + GoodVersion.MajorStr = MajorStr; + + if (PatchStr.empty()) { + // If no patch string, minor is the last segment + if (!TryParseLastNumber(MinorStr, GoodVersion.Minor, GoodVersion.MinorStr)) + return BadVersion; + return GoodVersion; + } + + if (!TryParseNumber(MinorStr, GoodVersion.Minor)) + return BadVersion; + GoodVersion.MinorStr = MinorStr; + + // For the last segment, tolerate a missing number. + std::string DummyStr; + TryParseLastNumber(PatchStr, GoodVersion.Patch, DummyStr); return GoodVersion; } diff --git a/clang/lib/Driver/ToolChains/HIPAMD.h b/clang/lib/Driver/ToolChains/HIPAMD.h index 7275b1a137ac8..d81a9733014cc 100644 --- a/clang/lib/Driver/ToolChains/HIPAMD.h +++ b/clang/lib/Driver/ToolChains/HIPAMD.h @@ -21,7 +21,7 @@ namespace tools { namespace AMDGCN { // Runs llvm-link/opt/llc/lld, which links multiple LLVM bitcode, together with // device library, then compiles it to ISA in a shared object. -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("AMDGCN::Linker", "amdgcn-link", TC) {} diff --git a/clang/lib/Driver/ToolChains/HIPSPV.h b/clang/lib/Driver/ToolChains/HIPSPV.h index 1eaef432171ec..ecd82e7052e48 100644 --- a/clang/lib/Driver/ToolChains/HIPSPV.h +++ b/clang/lib/Driver/ToolChains/HIPSPV.h @@ -20,7 +20,7 @@ namespace HIPSPV { // Runs llvm-link/opt/llc/lld, which links multiple LLVM bitcode, together with // device library, then compiles it to SPIR-V in a shared object. -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("HIPSPV::Linker", "hipspv-link", TC) {} diff --git a/clang/lib/Driver/ToolChains/Haiku.cpp b/clang/lib/Driver/ToolChains/Haiku.cpp index 9f56a0ea5d612..b940150788f65 100644 --- a/clang/lib/Driver/ToolChains/Haiku.cpp +++ b/clang/lib/Driver/ToolChains/Haiku.cpp @@ -23,8 +23,7 @@ void haiku::Linker::ConstructJob(Compilation &C, const JobAction &JA, const InputInfoList &Inputs, const ArgList &Args, const char *LinkingOutput) const { - const toolchains::Haiku &ToolChain = - static_cast(getToolChain()); + const auto &ToolChain = static_cast(getToolChain()); const Driver &D = ToolChain.getDriver(); const llvm::Triple::ArchType Arch = ToolChain.getArch(); const bool Static = Args.hasArg(options::OPT_static); @@ -96,6 +95,15 @@ void haiku::Linker::ConstructJob(Compilation &C, const JobAction &JA, if (D.CCCIsCXX() && ToolChain.ShouldLinkCXXStdlib(Args)) ToolChain.AddCXXStdlibLibArgs(Args, CmdArgs); + // Additional linker set-up and flags for Fortran. This is required in order + // to generate executables. As Fortran runtime depends on the C runtime, + // these dependencies need to be listed before the C runtime below (i.e. + // AddRunTimeLibs). + if (D.IsFlangMode()) { + addFortranRuntimeLibraryPath(ToolChain, Args, CmdArgs); + addFortranRuntimeLibs(ToolChain, CmdArgs); + } + CmdArgs.push_back("-lgcc"); CmdArgs.push_back("--push-state"); diff --git a/clang/lib/Driver/ToolChains/Hexagon.h b/clang/lib/Driver/ToolChains/Hexagon.h index 4799c3028ff9a..e35a224dced41 100644 --- a/clang/lib/Driver/ToolChains/Hexagon.h +++ b/clang/lib/Driver/ToolChains/Hexagon.h @@ -20,7 +20,7 @@ namespace hexagon { // For Hexagon, we do not need to instantiate tools for PreProcess, PreCompile // and Compile. // We simply use "clang -cc1" for those actions. -class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { +class LLVM_LIBRARY_VISIBILITY Assembler final : public Tool { public: Assembler(const ToolChain &TC) : Tool("hexagon::Assembler", "hexagon-as", TC) {} @@ -35,7 +35,7 @@ class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { const char *LinkingOutput) const override; }; -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("hexagon::Linker", "hexagon-ld", TC) {} diff --git a/clang/lib/Driver/ToolChains/MSP430.h b/clang/lib/Driver/ToolChains/MSP430.h index 2e838c027e0f8..a224c63754118 100644 --- a/clang/lib/Driver/ToolChains/MSP430.h +++ b/clang/lib/Driver/ToolChains/MSP430.h @@ -59,7 +59,7 @@ class LLVM_LIBRARY_VISIBILITY MSP430ToolChain : public Generic_ELF { namespace tools { namespace msp430 { -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("MSP430::Linker", "msp430-elf-ld", TC) {} bool hasIntegratedCPP() const override { return false; } diff --git a/clang/lib/Driver/ToolChains/MSVC.h b/clang/lib/Driver/ToolChains/MSVC.h index 0f687bc70ae47..fb27c621f2d1f 100644 --- a/clang/lib/Driver/ToolChains/MSVC.h +++ b/clang/lib/Driver/ToolChains/MSVC.h @@ -23,7 +23,7 @@ namespace tools { /// Visual studio tools. namespace visualstudio { -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("visualstudio::Linker", "linker", TC) {} diff --git a/clang/lib/Driver/ToolChains/MinGW.h b/clang/lib/Driver/ToolChains/MinGW.h index a71013912d0a3..75d629d5d1cb3 100644 --- a/clang/lib/Driver/ToolChains/MinGW.h +++ b/clang/lib/Driver/ToolChains/MinGW.h @@ -34,7 +34,7 @@ class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { const char *LinkingOutput) const override; }; -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("MinGW::Linker", "linker", TC) {} diff --git a/clang/lib/Driver/ToolChains/NaCl.cpp b/clang/lib/Driver/ToolChains/NaCl.cpp index 5be08c42b5287..22f038e5152ff 100644 --- a/clang/lib/Driver/ToolChains/NaCl.cpp +++ b/clang/lib/Driver/ToolChains/NaCl.cpp @@ -31,8 +31,7 @@ void nacltools::AssemblerARM::ConstructJob(Compilation &C, const JobAction &JA, const InputInfoList &Inputs, const ArgList &Args, const char *LinkingOutput) const { - const toolchains::NaClToolChain &ToolChain = - static_cast(getToolChain()); + const auto &ToolChain = static_cast(getToolChain()); InputInfo NaClMacros(types::TY_PP_Asm, ToolChain.GetNaClArmMacrosPath(), "nacl-arm-macros.s"); InputInfoList NewInputs; @@ -52,8 +51,7 @@ void nacltools::Linker::ConstructJob(Compilation &C, const JobAction &JA, const ArgList &Args, const char *LinkingOutput) const { - const toolchains::NaClToolChain &ToolChain = - static_cast(getToolChain()); + const auto &ToolChain = static_cast(getToolChain()); const Driver &D = ToolChain.getDriver(); const llvm::Triple::ArchType Arch = ToolChain.getArch(); const bool IsStatic = diff --git a/clang/lib/Driver/ToolChains/NaCl.h b/clang/lib/Driver/ToolChains/NaCl.h index 5e5fdb583bb60..01d4719e7b929 100644 --- a/clang/lib/Driver/ToolChains/NaCl.h +++ b/clang/lib/Driver/ToolChains/NaCl.h @@ -27,7 +27,7 @@ class LLVM_LIBRARY_VISIBILITY AssemblerARM : public gnutools::Assembler { const char *LinkingOutput) const override; }; -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("NaCl::Linker", "linker", TC) {} diff --git a/clang/lib/Driver/ToolChains/NetBSD.cpp b/clang/lib/Driver/ToolChains/NetBSD.cpp index 1c901f70f72ca..7a1d4561c6f2f 100644 --- a/clang/lib/Driver/ToolChains/NetBSD.cpp +++ b/clang/lib/Driver/ToolChains/NetBSD.cpp @@ -30,13 +30,12 @@ void netbsd::Assembler::ConstructJob(Compilation &C, const JobAction &JA, const InputInfoList &Inputs, const ArgList &Args, const char *LinkingOutput) const { - const toolchains::NetBSD &ToolChain = - static_cast(getToolChain()); + const auto &ToolChain = static_cast(getToolChain()); const Driver &D = ToolChain.getDriver(); const llvm::Triple &Triple = ToolChain.getTriple(); + ArgStringList CmdArgs; claimNoWarnArgs(Args); - ArgStringList CmdArgs; // GNU as needs different flags for creating the correct output format // on architectures with different ABIs or optional feature sets. @@ -78,8 +77,7 @@ void netbsd::Assembler::ConstructJob(Compilation &C, const JobAction &JA, break; } - case llvm::Triple::sparc: - case llvm::Triple::sparcel: { + case llvm::Triple::sparc: { CmdArgs.push_back("-32"); std::string CPU = getCPUName(D, Args, Triple); CmdArgs.push_back(sparc::getSparcAsmModeForCPU(CPU, Triple)); @@ -118,27 +116,29 @@ void netbsd::Linker::ConstructJob(Compilation &C, const JobAction &JA, const InputInfoList &Inputs, const ArgList &Args, const char *LinkingOutput) const { - const toolchains::NetBSD &ToolChain = - static_cast(getToolChain()); + const auto &ToolChain = static_cast(getToolChain()); const Driver &D = ToolChain.getDriver(); const llvm::Triple &Triple = ToolChain.getTriple(); - + const llvm::Triple::ArchType Arch = ToolChain.getArch(); + const bool Static = Args.hasArg(options::OPT_static); + const bool Shared = Args.hasArg(options::OPT_shared); + const bool Pie = Args.hasArg(options::OPT_pie); ArgStringList CmdArgs; if (!D.SysRoot.empty()) CmdArgs.push_back(Args.MakeArgString("--sysroot=" + D.SysRoot)); CmdArgs.push_back("--eh-frame-hdr"); - if (Args.hasArg(options::OPT_static)) { + if (Static) { CmdArgs.push_back("-Bstatic"); - if (Args.hasArg(options::OPT_pie)) { + if (Pie) { Args.AddAllArgs(CmdArgs, options::OPT_pie); CmdArgs.push_back("--no-dynamic-linker"); } } else { if (Args.hasArg(options::OPT_rdynamic)) CmdArgs.push_back("-export-dynamic"); - if (Args.hasArg(options::OPT_shared)) { + if (Shared) { CmdArgs.push_back("-shared"); } else if (!Args.hasArg(options::OPT_r)) { Args.AddAllArgs(CmdArgs, options::OPT_pie); @@ -149,7 +149,7 @@ void netbsd::Linker::ConstructJob(Compilation &C, const JobAction &JA, // Many NetBSD architectures support more than one ABI. // Determine the correct emulation for ld. - switch (ToolChain.getArch()) { + switch (Arch) { case llvm::Triple::x86: CmdArgs.push_back("-m"); CmdArgs.push_back("elf_i386"); @@ -193,13 +193,13 @@ void netbsd::Linker::ConstructJob(Compilation &C, const JobAction &JA, case llvm::Triple::mips64el: if (mips::hasMipsAbiArg(Args, "32")) { CmdArgs.push_back("-m"); - if (ToolChain.getArch() == llvm::Triple::mips64) + if (Arch == llvm::Triple::mips64) CmdArgs.push_back("elf32btsmip"); else CmdArgs.push_back("elf32ltsmip"); } else if (mips::hasMipsAbiArg(Args, "64")) { CmdArgs.push_back("-m"); - if (ToolChain.getArch() == llvm::Triple::mips64) + if (Arch == llvm::Triple::mips64) CmdArgs.push_back("elf64btsmip"); else CmdArgs.push_back("elf64ltsmip"); @@ -251,19 +251,20 @@ void netbsd::Linker::ConstructJob(Compilation &C, const JobAction &JA, if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles, options::OPT_r)) { - if (!Args.hasArg(options::OPT_shared)) { - CmdArgs.push_back( - Args.MakeArgString(ToolChain.GetFilePath("crt0.o"))); - } - CmdArgs.push_back( - Args.MakeArgString(ToolChain.GetFilePath("crti.o"))); - if (Args.hasArg(options::OPT_shared) || Args.hasArg(options::OPT_pie)) { - CmdArgs.push_back( - Args.MakeArgString(ToolChain.GetFilePath("crtbeginS.o"))); - } else { - CmdArgs.push_back( - Args.MakeArgString(ToolChain.GetFilePath("crtbegin.o"))); - } + const char *crt0 = nullptr; + const char *crtbegin = nullptr; + if (!Shared) + crt0 = "crt0.o"; + + if (Shared || Pie) + crtbegin = "crtbeginS.o"; + else + crtbegin = "crtbegin.o"; + + if (crt0) + CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath(crt0))); + CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath("crti.o"))); + CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath(crtbegin))); } Args.addAllArgs(CmdArgs, {options::OPT_L, options::OPT_T_Group, @@ -305,8 +306,7 @@ void netbsd::Linker::ConstructJob(Compilation &C, const JobAction &JA, if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nodefaultlibs, options::OPT_r)) { // Use the static OpenMP runtime with -static-openmp - bool StaticOpenMP = Args.hasArg(options::OPT_static_openmp) && - !Args.hasArg(options::OPT_static); + bool StaticOpenMP = Args.hasArg(options::OPT_static_openmp) && !Static; addOpenMPRuntime(CmdArgs, ToolChain, Args, StaticOpenMP); if (D.CCCIsCXX()) { @@ -314,6 +314,17 @@ void netbsd::Linker::ConstructJob(Compilation &C, const JobAction &JA, ToolChain.AddCXXStdlibLibArgs(Args, CmdArgs); CmdArgs.push_back("-lm"); } + + // Additional linker set-up and flags for Fortran. This is required in order + // to generate executables. As Fortran runtime depends on the C runtime, + // these dependencies need to be listed before the C runtime below (i.e. + // AddRunTimeLibs). + if (D.IsFlangMode()) { + addFortranRuntimeLibraryPath(ToolChain, Args, CmdArgs); + addFortranRuntimeLibs(ToolChain, CmdArgs); + CmdArgs.push_back("-lm"); + } + if (NeedsSanitizerDeps) linkSanitizerRuntimeDeps(ToolChain, Args, CmdArgs); if (NeedsXRayDeps) @@ -323,7 +334,7 @@ void netbsd::Linker::ConstructJob(Compilation &C, const JobAction &JA, CmdArgs.push_back("-lc"); if (useLibgcc) { - if (Args.hasArg(options::OPT_static)) { + if (Static) { // libgcc_eh depends on libc, so resolve as much as possible, // pull in any new requirements from libc and then get the rest // of libgcc. @@ -341,12 +352,13 @@ void netbsd::Linker::ConstructJob(Compilation &C, const JobAction &JA, if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles, options::OPT_r)) { - if (Args.hasArg(options::OPT_shared) || Args.hasArg(options::OPT_pie)) - CmdArgs.push_back( - Args.MakeArgString(ToolChain.GetFilePath("crtendS.o"))); + const char *crtend = nullptr; + if (Shared || Pie) + crtend = "crtendS.o"; else - CmdArgs.push_back( - Args.MakeArgString(ToolChain.GetFilePath("crtend.o"))); + crtend = "crtend.o"; + + CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath(crtend))); CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath("crtn.o"))); } diff --git a/clang/lib/Driver/ToolChains/NetBSD.h b/clang/lib/Driver/ToolChains/NetBSD.h index 044c4239c3f48..96303acaa0099 100644 --- a/clang/lib/Driver/ToolChains/NetBSD.h +++ b/clang/lib/Driver/ToolChains/NetBSD.h @@ -19,7 +19,7 @@ namespace tools { /// Directly call GNU Binutils assembler and linker namespace netbsd { -class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { +class LLVM_LIBRARY_VISIBILITY Assembler final : public Tool { public: Assembler(const ToolChain &TC) : Tool("netbsd::Assembler", "assembler", TC) {} @@ -31,7 +31,7 @@ class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { const char *LinkingOutput) const override; }; -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("netbsd::Linker", "linker", TC) {} diff --git a/clang/lib/Driver/ToolChains/OpenBSD.cpp b/clang/lib/Driver/ToolChains/OpenBSD.cpp index 2508ef57f827c..16a311be31be7 100644 --- a/clang/lib/Driver/ToolChains/OpenBSD.cpp +++ b/clang/lib/Driver/ToolChains/OpenBSD.cpp @@ -30,8 +30,7 @@ void openbsd::Assembler::ConstructJob(Compilation &C, const JobAction &JA, const InputInfoList &Inputs, const ArgList &Args, const char *LinkingOutput) const { - const toolchains::OpenBSD &ToolChain = - static_cast(getToolChain()); + const auto &ToolChain = static_cast(getToolChain()); const Driver &D = ToolChain.getDriver(); const llvm::Triple &Triple = ToolChain.getTriple(); @@ -45,8 +44,7 @@ void openbsd::Assembler::ConstructJob(Compilation &C, const JobAction &JA, CmdArgs.push_back("--32"); break; - case llvm::Triple::arm: - case llvm::Triple::armeb: { + case llvm::Triple::arm: { StringRef MArch, MCPU; arm::getARMArchCPUFromArgs(Args, MArch, MCPU, /*FromAs*/ true); std::string Arch = arm::getARMTargetCPU(MCPU, MArch, Triple); @@ -111,8 +109,7 @@ void openbsd::Linker::ConstructJob(Compilation &C, const JobAction &JA, const InputInfoList &Inputs, const ArgList &Args, const char *LinkingOutput) const { - const toolchains::OpenBSD &ToolChain = - static_cast(getToolChain()); + const auto &ToolChain = static_cast(getToolChain()); const Driver &D = ToolChain.getDriver(); const llvm::Triple::ArchType Arch = ToolChain.getArch(); ArgStringList CmdArgs; @@ -121,6 +118,7 @@ void openbsd::Linker::ConstructJob(Compilation &C, const JobAction &JA, bool Profiling = Args.hasArg(options::OPT_pg); bool Pie = Args.hasArg(options::OPT_pie); bool Nopie = Args.hasArg(options::OPT_nopie); + const bool Relocatable = Args.hasArg(options::OPT_r); // Silence warning for "clang -g foo.o -o foo" Args.ClaimAllArgs(options::OPT_g_Group); @@ -138,7 +136,7 @@ void openbsd::Linker::ConstructJob(Compilation &C, const JobAction &JA, else if (Arch == llvm::Triple::mips64el) CmdArgs.push_back("-EL"); - if (!Args.hasArg(options::OPT_nostdlib) && !Shared) { + if (!Args.hasArg(options::OPT_nostdlib) && !Shared && !Relocatable) { CmdArgs.push_back("-e"); CmdArgs.push_back("__start"); } @@ -149,10 +147,9 @@ void openbsd::Linker::ConstructJob(Compilation &C, const JobAction &JA, } else { if (Args.hasArg(options::OPT_rdynamic)) CmdArgs.push_back("-export-dynamic"); - CmdArgs.push_back("-Bdynamic"); if (Shared) { CmdArgs.push_back("-shared"); - } else if (!Args.hasArg(options::OPT_r)) { + } else if (!Relocatable) { CmdArgs.push_back("-dynamic-linker"); CmdArgs.push_back("/usr/libexec/ld.so"); } @@ -216,6 +213,20 @@ void openbsd::Linker::ConstructJob(Compilation &C, const JobAction &JA, else CmdArgs.push_back("-lm"); } + + // Additional linker set-up and flags for Fortran. This is required in order + // to generate executables. As Fortran runtime depends on the C runtime, + // these dependencies need to be listed before the C runtime below (i.e. + // AddRunTimeLibs). + if (D.IsFlangMode()) { + addFortranRuntimeLibraryPath(ToolChain, Args, CmdArgs); + addFortranRuntimeLibs(ToolChain, CmdArgs); + if (Profiling) + CmdArgs.push_back("-lm_p"); + else + CmdArgs.push_back("-lm"); + } + if (NeedsSanitizerDeps) { CmdArgs.push_back(ToolChain.getCompilerRTArgString(Args, "builtins")); linkSanitizerRuntimeDeps(ToolChain, Args, CmdArgs); diff --git a/clang/lib/Driver/ToolChains/OpenBSD.h b/clang/lib/Driver/ToolChains/OpenBSD.h index 486dbf1407c24..b4350e72d5d26 100644 --- a/clang/lib/Driver/ToolChains/OpenBSD.h +++ b/clang/lib/Driver/ToolChains/OpenBSD.h @@ -20,7 +20,7 @@ namespace tools { /// Directly call GNU Binutils assembler and linker namespace openbsd { -class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { +class LLVM_LIBRARY_VISIBILITY Assembler final : public Tool { public: Assembler(const ToolChain &TC) : Tool("openbsd::Assembler", "assembler", TC) {} @@ -33,7 +33,7 @@ class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { const char *LinkingOutput) const override; }; -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("openbsd::Linker", "linker", TC) {} diff --git a/clang/lib/Driver/ToolChains/PS4CPU.h b/clang/lib/Driver/ToolChains/PS4CPU.h index a51351d367be8..fee80e77462f3 100644 --- a/clang/lib/Driver/ToolChains/PS4CPU.h +++ b/clang/lib/Driver/ToolChains/PS4CPU.h @@ -27,7 +27,7 @@ void addProfileRTArgs(const ToolChain &TC, const llvm::opt::ArgList &Args, void addSanitizerArgs(const ToolChain &TC, const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CmdArgs); -class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { +class LLVM_LIBRARY_VISIBILITY Assembler final : public Tool { public: Assembler(const ToolChain &TC) : Tool("PScpu::Assembler", "assembler", TC) {} @@ -39,7 +39,7 @@ class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { const char *LinkingOutput) const override; }; -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("PScpu::Linker", "linker", TC) {} diff --git a/clang/lib/Driver/ToolChains/RISCVToolchain.h b/clang/lib/Driver/ToolChains/RISCVToolchain.h index de6960726f1cd..cec817ef7190b 100644 --- a/clang/lib/Driver/ToolChains/RISCVToolchain.h +++ b/clang/lib/Driver/ToolChains/RISCVToolchain.h @@ -46,7 +46,7 @@ class LLVM_LIBRARY_VISIBILITY RISCVToolChain : public Generic_ELF { namespace tools { namespace RISCV { -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("RISCV::Linker", "ld", TC) {} bool hasIntegratedCPP() const override { return false; } diff --git a/clang/lib/Driver/ToolChains/SPIRV.h b/clang/lib/Driver/ToolChains/SPIRV.h index 3cd613d9aac29..d4247ee0557f4 100644 --- a/clang/lib/Driver/ToolChains/SPIRV.h +++ b/clang/lib/Driver/ToolChains/SPIRV.h @@ -36,7 +36,7 @@ class LLVM_LIBRARY_VISIBILITY Translator : public Tool { const char *LinkingOutput) const override; }; -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("SPIRV::Linker", "spirv-link", TC) {} bool hasIntegratedCPP() const override { return false; } diff --git a/clang/lib/Driver/ToolChains/Solaris.cpp b/clang/lib/Driver/ToolChains/Solaris.cpp index ecff8ddc4ee76..3d5a710842eca 100644 --- a/clang/lib/Driver/ToolChains/Solaris.cpp +++ b/clang/lib/Driver/ToolChains/Solaris.cpp @@ -96,7 +96,8 @@ void solaris::Linker::ConstructJob(Compilation &C, const JobAction &JA, if (!LinkerIsGnuLd) CmdArgs.push_back("-C"); - if (!Args.hasArg(options::OPT_nostdlib, options::OPT_shared)) { + if (!Args.hasArg(options::OPT_nostdlib, options::OPT_shared, + options::OPT_r)) { CmdArgs.push_back("-e"); CmdArgs.push_back("_start"); } @@ -114,10 +115,8 @@ void solaris::Linker::ConstructJob(Compilation &C, const JobAction &JA, CmdArgs.push_back("-Bstatic"); CmdArgs.push_back("-dn"); } else { - CmdArgs.push_back("-Bdynamic"); - if (Args.hasArg(options::OPT_shared)) { + if (!Args.hasArg(options::OPT_r) && Args.hasArg(options::OPT_shared)) CmdArgs.push_back("-shared"); - } // libpthread has been folded into libc since Solaris 10, no need to do // anything for pthreads. Claim argument to avoid warning. @@ -127,8 +126,7 @@ void solaris::Linker::ConstructJob(Compilation &C, const JobAction &JA, if (LinkerIsGnuLd) { // Set the correct linker emulation for 32- and 64-bit Solaris. - const toolchains::Solaris &ToolChain = - static_cast(getToolChain()); + const auto &ToolChain = static_cast(getToolChain()); const llvm::Triple::ArchType Arch = ToolChain.getArch(); switch (Arch) { diff --git a/clang/lib/Driver/ToolChains/Solaris.h b/clang/lib/Driver/ToolChains/Solaris.h index b8f2497d7c8eb..9ec83b773da44 100644 --- a/clang/lib/Driver/ToolChains/Solaris.h +++ b/clang/lib/Driver/ToolChains/Solaris.h @@ -19,7 +19,7 @@ namespace tools { /// Directly call Solaris assembler and linker namespace solaris { -class LLVM_LIBRARY_VISIBILITY Assembler : public gnutools::Assembler { +class LLVM_LIBRARY_VISIBILITY Assembler final : public gnutools::Assembler { public: Assembler(const ToolChain &TC) : gnutools::Assembler(TC) {} @@ -33,7 +33,7 @@ class LLVM_LIBRARY_VISIBILITY Assembler : public gnutools::Assembler { bool isLinkerGnuLd(const ToolChain &TC, const llvm::opt::ArgList &Args); -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("solaris::Linker", "linker", TC) {} diff --git a/clang/lib/Driver/ToolChains/WebAssembly.h b/clang/lib/Driver/ToolChains/WebAssembly.h index 39589ffc1e3b6..ae60f464c1081 100644 --- a/clang/lib/Driver/ToolChains/WebAssembly.h +++ b/clang/lib/Driver/ToolChains/WebAssembly.h @@ -18,7 +18,7 @@ namespace driver { namespace tools { namespace wasm { -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: explicit Linker(const ToolChain &TC) : Tool("wasm::Linker", "linker", TC) {} bool isLinkJob() const override { return true; } diff --git a/clang/lib/Driver/ToolChains/XCore.h b/clang/lib/Driver/ToolChains/XCore.h index f2e66350243e5..95359a6e2542f 100644 --- a/clang/lib/Driver/ToolChains/XCore.h +++ b/clang/lib/Driver/ToolChains/XCore.h @@ -20,7 +20,7 @@ namespace XCore { // For XCore, we do not need to instantiate tools for PreProcess, PreCompile and // Compile. // We simply use "clang -cc1" for those actions. -class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { +class LLVM_LIBRARY_VISIBILITY Assembler final : public Tool { public: Assembler(const ToolChain &TC) : Tool("XCore::Assembler", "XCore-as", TC) {} @@ -31,7 +31,7 @@ class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { const char *LinkingOutput) const override; }; -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("XCore::Linker", "XCore-ld", TC) {} diff --git a/clang/lib/Driver/ToolChains/ZOS.h b/clang/lib/Driver/ToolChains/ZOS.h index 4b9b332c0f3fb..45204ba0a543c 100644 --- a/clang/lib/Driver/ToolChains/ZOS.h +++ b/clang/lib/Driver/ToolChains/ZOS.h @@ -19,7 +19,7 @@ namespace tools { /// Directly call system default assembler and linker. namespace zos { -class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { +class LLVM_LIBRARY_VISIBILITY Assembler final : public Tool { public: Assembler(const ToolChain &TC) : Tool("zos::Assembler", "assembler", TC) {} @@ -31,7 +31,7 @@ class LLVM_LIBRARY_VISIBILITY Assembler : public Tool { const char *LinkingOutput) const override; }; -class LLVM_LIBRARY_VISIBILITY Linker : public Tool { +class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("zos::Linker", "linker", TC) {} diff --git a/clang/lib/Format/ContinuationIndenter.cpp b/clang/lib/Format/ContinuationIndenter.cpp index 3b28f84fd8417..3a829cdedb77f 100644 --- a/clang/lib/Format/ContinuationIndenter.cpp +++ b/clang/lib/Format/ContinuationIndenter.cpp @@ -813,8 +813,10 @@ void ContinuationIndenter::addTokenOnCurrentLine(LineState &State, bool DryRun, CurrentState.ContainsUnwrappedBuilder = true; } - if (Current.is(TT_LambdaArrow) && Style.Language == FormatStyle::LK_Java) + if (Current.is(TT_TrailingReturnArrow) && + Style.Language == FormatStyle::LK_Java) { CurrentState.NoLineBreak = true; + } if (Current.isMemberAccess() && Previous.is(tok::r_paren) && (Previous.MatchingParen && (Previous.TotalLength - Previous.MatchingParen->TotalLength > 10))) { @@ -969,7 +971,7 @@ unsigned ContinuationIndenter::addTokenOnNewLine(LineState &State, // // is common and should be formatted like a free-standing function. The same // goes for wrapping before the lambda return type arrow. - if (Current.isNot(TT_LambdaArrow) && + if (Current.isNot(TT_TrailingReturnArrow) && (!Style.isJavaScript() || Current.NestingLevel != 0 || !PreviousNonComment || PreviousNonComment->isNot(tok::equal) || !Current.isOneOf(Keywords.kw_async, Keywords.kw_function))) { @@ -1548,7 +1550,7 @@ unsigned ContinuationIndenter::moveStateToNextToken(LineState &State, } if (Current.isOneOf(TT_BinaryOperator, TT_ConditionalExpr) && Newline) CurrentState.NestedBlockIndent = State.Column + Current.ColumnWidth + 1; - if (Current.isOneOf(TT_LambdaLSquare, TT_LambdaArrow)) + if (Current.isOneOf(TT_LambdaLSquare, TT_TrailingReturnArrow)) CurrentState.LastSpace = State.Column; if (Current.is(TT_RequiresExpression) && Style.RequiresExpressionIndentation == FormatStyle::REI_Keyword) { diff --git a/clang/lib/Format/Format.cpp b/clang/lib/Format/Format.cpp index 7b0ebe2cf621b..e1abcac5604a4 100644 --- a/clang/lib/Format/Format.cpp +++ b/clang/lib/Format/Format.cpp @@ -504,6 +504,22 @@ struct ScalarEnumerationTraits { } }; +template <> +struct MappingTraits< + FormatStyle::SpaceBeforeParensCustom::AfterPlacementOperatorStyle> { + static void + mapping(IO &IO, + FormatStyle::SpaceBeforeParensCustom::AfterPlacementOperatorStyle + &Value) { + IO.enumCase(Value, "Always", + FormatStyle::SpaceBeforeParensCustom::APO_Always); + IO.enumCase(Value, "Never", + FormatStyle::SpaceBeforeParensCustom::APO_Never); + IO.enumCase(Value, "Leave", + FormatStyle::SpaceBeforeParensCustom::APO_Leave); + } +}; + template <> struct MappingTraits { static void mapping(IO &IO, FormatStyle::RawStringFormat &Format) { IO.mapOptional("Language", Format.Language); @@ -679,6 +695,7 @@ template <> struct MappingTraits { Spacing.AfterFunctionDeclarationName); IO.mapOptional("AfterIfMacros", Spacing.AfterIfMacros); IO.mapOptional("AfterOverloadedOperator", Spacing.AfterOverloadedOperator); + IO.mapOptional("AfterPlacementOperator", Spacing.AfterPlacementOperator); IO.mapOptional("AfterRequiresInClause", Spacing.AfterRequiresInClause); IO.mapOptional("AfterRequiresInExpression", Spacing.AfterRequiresInExpression); @@ -817,8 +834,8 @@ template <> struct MappingTraits { StringRef BasedOnStyle; if (IO.outputting()) { - StringRef Styles[] = {"LLVM", "Google", "Chromium", "Mozilla", - "WebKit", "GNU", "Microsoft"}; + StringRef Styles[] = {"LLVM", "Google", "Chromium", "Mozilla", + "WebKit", "GNU", "Microsoft", "clang-format"}; for (StringRef StyleName : Styles) { FormatStyle PredefinedStyle; if (getPredefinedStyle(StyleName, Style.Language, &PredefinedStyle) && @@ -921,6 +938,8 @@ template <> struct MappingTraits { Style.AllowShortBlocksOnASingleLine); IO.mapOptional("AllowShortCaseLabelsOnASingleLine", Style.AllowShortCaseLabelsOnASingleLine); + IO.mapOptional("AllowShortCompoundRequirementOnASingleLine", + Style.AllowShortCompoundRequirementOnASingleLine); IO.mapOptional("AllowShortEnumsOnASingleLine", Style.AllowShortEnumsOnASingleLine); IO.mapOptional("AllowShortFunctionsOnASingleLine", @@ -1369,6 +1388,8 @@ static void expandPresetsSpaceBeforeParens(FormatStyle &Expanded) { switch (Expanded.SpaceBeforeParens) { case FormatStyle::SBPO_Never: + Expanded.SpaceBeforeParensOptions.AfterPlacementOperator = + FormatStyle::SpaceBeforeParensCustom::APO_Never; break; case FormatStyle::SBPO_ControlStatements: Expanded.SpaceBeforeParensOptions.AfterControlStatements = true; @@ -1422,6 +1443,7 @@ FormatStyle getLLVMStyle(FormatStyle::LanguageKind Language) { LLVMStyle.AllowAllParametersOfDeclarationOnNextLine = true; LLVMStyle.AllowShortBlocksOnASingleLine = FormatStyle::SBS_Never; LLVMStyle.AllowShortCaseLabelsOnASingleLine = false; + LLVMStyle.AllowShortCompoundRequirementOnASingleLine = true; LLVMStyle.AllowShortEnumsOnASingleLine = true; LLVMStyle.AllowShortFunctionsOnASingleLine = FormatStyle::SFS_All; LLVMStyle.AllowShortIfStatementsOnASingleLine = FormatStyle::SIS_Never; @@ -1454,7 +1476,7 @@ FormatStyle getLLVMStyle(FormatStyle::LanguageKind Language) { /*SplitEmptyFunction=*/true, /*SplitEmptyRecord=*/true, /*SplitEmptyNamespace=*/true}; - LLVMStyle.BreakAfterAttributes = FormatStyle::ABS_Never; + LLVMStyle.BreakAfterAttributes = FormatStyle::ABS_Leave; LLVMStyle.BreakAfterJavaFieldAnnotations = false; LLVMStyle.BreakArrays = true; LLVMStyle.BreakBeforeBinaryOperators = FormatStyle::BOS_None; @@ -1896,6 +1918,16 @@ FormatStyle getMicrosoftStyle(FormatStyle::LanguageKind Language) { return Style; } +FormatStyle getClangFormatStyle() { + FormatStyle Style = getLLVMStyle(); + Style.InsertBraces = true; + Style.InsertNewlineAtEOF = true; + Style.LineEnding = FormatStyle::LE_LF; + Style.RemoveBracesLLVM = true; + Style.RemoveParentheses = FormatStyle::RPS_ReturnStatement; + return Style; +} + FormatStyle getNoStyle() { FormatStyle NoStyle = getLLVMStyle(); NoStyle.DisableFormat = true; @@ -1920,6 +1952,8 @@ bool getPredefinedStyle(StringRef Name, FormatStyle::LanguageKind Language, *Style = getGNUStyle(); else if (Name.equals_insensitive("microsoft")) *Style = getMicrosoftStyle(Language); + else if (Name.equals_insensitive("clang-format")) + *Style = getClangFormatStyle(); else if (Name.equals_insensitive("none")) *Style = getNoStyle(); else if (Name.equals_insensitive("inheritparentconfig")) diff --git a/clang/lib/Format/FormatToken.h b/clang/lib/Format/FormatToken.h index 606e9e790ad83..87f6a76ec5bfd 100644 --- a/clang/lib/Format/FormatToken.h +++ b/clang/lib/Format/FormatToken.h @@ -67,6 +67,7 @@ namespace format { TYPE(DesignatedInitializerLSquare) \ TYPE(DesignatedInitializerPeriod) \ TYPE(DictLiteral) \ + TYPE(DoWhile) \ TYPE(ElseLBrace) \ TYPE(ElseRBrace) \ TYPE(EnumLBrace) \ @@ -99,7 +100,6 @@ namespace format { TYPE(JsTypeColon) \ TYPE(JsTypeOperator) \ TYPE(JsTypeOptionalQuestion) \ - TYPE(LambdaArrow) \ TYPE(LambdaLBrace) \ TYPE(LambdaLSquare) \ TYPE(LeadingJavaAnnotation) \ @@ -689,7 +689,7 @@ struct FormatToken { bool isMemberAccess() const { return isOneOf(tok::arrow, tok::period, tok::arrowstar) && !isOneOf(TT_DesignatedInitializerPeriod, TT_TrailingReturnArrow, - TT_LambdaArrow, TT_LeadingJavaAnnotation); + TT_LeadingJavaAnnotation); } bool isUnaryOperator() const { diff --git a/clang/lib/Format/SortJavaScriptImports.cpp b/clang/lib/Format/SortJavaScriptImports.cpp index 9afe85aeed437..8c6722e915344 100644 --- a/clang/lib/Format/SortJavaScriptImports.cpp +++ b/clang/lib/Format/SortJavaScriptImports.cpp @@ -548,10 +548,12 @@ class JavaScriptImportSorter : public TokenAnalyzer { nextToken(); if (Current->is(tok::r_brace)) break; - bool isTypeOnly = - Current->is(Keywords.kw_type) && Current->Next && - Current->Next->isOneOf(tok::identifier, tok::kw_default); - if (!isTypeOnly && !Current->isOneOf(tok::identifier, tok::kw_default)) + auto IsIdentifier = [](const auto *Tok) { + return Tok->isOneOf(tok::identifier, tok::kw_default, tok::kw_template); + }; + bool isTypeOnly = Current->is(Keywords.kw_type) && Current->Next && + IsIdentifier(Current->Next); + if (!isTypeOnly && !IsIdentifier(Current)) return false; JsImportedSymbol Symbol; @@ -565,7 +567,7 @@ class JavaScriptImportSorter : public TokenAnalyzer { if (Current->is(Keywords.kw_as)) { nextToken(); - if (!Current->isOneOf(tok::identifier, tok::kw_default)) + if (!IsIdentifier(Current)) return false; Symbol.Alias = Current->TokenText; nextToken(); diff --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp index 293f7286abe42..aee966145b8e5 100644 --- a/clang/lib/Format/TokenAnnotator.cpp +++ b/clang/lib/Format/TokenAnnotator.cpp @@ -766,7 +766,8 @@ class AnnotatingParser { } // An arrow after an ObjC method expression is not a lambda arrow. if (CurrentToken->getType() == TT_ObjCMethodExpr && - CurrentToken->Next && CurrentToken->Next->is(TT_LambdaArrow)) { + CurrentToken->Next && + CurrentToken->Next->is(TT_TrailingReturnArrow)) { CurrentToken->Next->overwriteFixedType(TT_Unknown); } Left->MatchingParen = CurrentToken; @@ -1409,10 +1410,8 @@ class AnnotatingParser { } break; case tok::arrow: - if (Tok->isNot(TT_LambdaArrow) && Tok->Previous && - Tok->Previous->is(tok::kw_noexcept)) { + if (Tok->Previous && Tok->Previous->is(tok::kw_noexcept)) Tok->setType(TT_TrailingReturnArrow); - } break; default: break; @@ -1689,11 +1688,11 @@ class AnnotatingParser { TT_LambdaLSquare, TT_LambdaLBrace, TT_AttributeMacro, TT_IfMacro, TT_ForEachMacro, TT_TypenameMacro, TT_FunctionLBrace, TT_ImplicitStringLiteral, TT_InlineASMBrace, TT_FatArrow, - TT_LambdaArrow, TT_NamespaceMacro, TT_OverloadedOperator, - TT_RegexLiteral, TT_TemplateString, TT_ObjCStringLiteral, - TT_UntouchableMacroFunc, TT_StatementAttributeLikeMacro, - TT_FunctionLikeOrFreestandingMacro, TT_ClassLBrace, TT_EnumLBrace, - TT_RecordLBrace, TT_StructLBrace, TT_UnionLBrace, TT_RequiresClause, + TT_NamespaceMacro, TT_OverloadedOperator, TT_RegexLiteral, + TT_TemplateString, TT_ObjCStringLiteral, TT_UntouchableMacroFunc, + TT_StatementAttributeLikeMacro, TT_FunctionLikeOrFreestandingMacro, + TT_ClassLBrace, TT_EnumLBrace, TT_RecordLBrace, TT_StructLBrace, + TT_UnionLBrace, TT_RequiresClause, TT_RequiresClauseInARequiresExpression, TT_RequiresExpression, TT_RequiresExpressionLParen, TT_RequiresExpressionLBrace, TT_BracedListLBrace)) { @@ -1876,7 +1875,7 @@ class AnnotatingParser { Contexts.back().IsExpression = true; } else if (Current.is(TT_TrailingReturnArrow)) { Contexts.back().IsExpression = false; - } else if (Current.is(TT_LambdaArrow) || Current.is(Keywords.kw_assert)) { + } else if (Current.is(Keywords.kw_assert)) { Contexts.back().IsExpression = Style.Language == FormatStyle::LK_Java; } else if (Current.Previous && Current.Previous->is(TT_CtorInitializerColon)) { @@ -2010,7 +2009,7 @@ class AnnotatingParser { AutoFound = true; } else if (Current.is(tok::arrow) && Style.Language == FormatStyle::LK_Java) { - Current.setType(TT_LambdaArrow); + Current.setType(TT_TrailingReturnArrow); } else if (Current.is(tok::arrow) && AutoFound && Line.MightBeFunctionDecl && Current.NestingLevel == 0 && !Current.Previous->isOneOf(tok::kw_operator, tok::identifier)) { @@ -2094,18 +2093,16 @@ class AnnotatingParser { !Current.Next->isOneOf(tok::semi, tok::colon, tok::l_brace, tok::comma, tok::period, tok::arrow, tok::coloncolon, tok::kw_noexcept)) { - if (FormatToken *AfterParen = Current.MatchingParen->Next) { - // Make sure this isn't the return type of an Obj-C block declaration - if (AfterParen->isNot(tok::caret)) { - if (FormatToken *BeforeParen = Current.MatchingParen->Previous) { - if (BeforeParen->is(tok::identifier) && - BeforeParen->isNot(TT_TypenameMacro) && - BeforeParen->TokenText == BeforeParen->TokenText.upper() && - (!BeforeParen->Previous || - BeforeParen->Previous->ClosesTemplateDeclaration)) { - Current.setType(TT_FunctionAnnotationRParen); - } - } + if (FormatToken *AfterParen = Current.MatchingParen->Next; + AfterParen && AfterParen->isNot(tok::caret)) { + // Make sure this isn't the return type of an Obj-C block declaration. + if (FormatToken *BeforeParen = Current.MatchingParen->Previous; + BeforeParen && BeforeParen->is(tok::identifier) && + BeforeParen->isNot(TT_TypenameMacro) && + BeforeParen->TokenText == BeforeParen->TokenText.upper() && + (!BeforeParen->Previous || + BeforeParen->Previous->ClosesTemplateDeclaration)) { + Current.setType(TT_FunctionAnnotationRParen); } } } @@ -2857,7 +2854,7 @@ class ExpressionParser { } if (Current->is(TT_JsComputedPropertyName)) return prec::Assignment; - if (Current->is(TT_LambdaArrow)) + if (Current->is(TT_TrailingReturnArrow)) return prec::Comma; if (Current->is(TT_FatArrow)) return prec::Assignment; @@ -3544,7 +3541,7 @@ void TokenAnnotator::calculateFormattingInformation(AnnotatedLine &Line) const { } } } - } else if (Current->SpacesRequiredBefore == 0 && + } else if (!Current->Finalized && Current->SpacesRequiredBefore == 0 && spaceRequiredBefore(Line, *Current)) { Current->SpacesRequiredBefore = 1; } @@ -3742,7 +3739,7 @@ unsigned TokenAnnotator::splitPenalty(const AnnotatedLine &Line, } if (Right.is(TT_PointerOrReference)) return 190; - if (Right.is(TT_LambdaArrow)) + if (Right.is(TT_TrailingReturnArrow)) return 110; if (Left.is(tok::equal) && Right.is(tok::l_brace)) return 160; @@ -4197,8 +4194,7 @@ bool TokenAnnotator::spaceRequiredBetween(const AnnotatedLine &Line, if ((Left.is(tok::l_brace) && Left.isNot(BK_Block)) || (Right.is(tok::r_brace) && Right.MatchingParen && Right.MatchingParen->isNot(BK_Block))) { - return Style.Cpp11BracedListStyle ? Style.SpacesInParensOptions.Other - : true; + return !Style.Cpp11BracedListStyle || Style.SpacesInParensOptions.Other; } if (Left.is(TT_BlockComment)) { // No whitespace in x(/*foo=*/1), except for JavaScript. @@ -4234,6 +4230,19 @@ bool TokenAnnotator::spaceRequiredBetween(const AnnotatedLine &Line, return Style.SpaceBeforeParensOptions.AfterIfMacros || spaceRequiredBeforeParens(Right); } + if (Style.SpaceBeforeParens == FormatStyle::SBPO_Custom && + Left.isOneOf(tok::kw_new, tok::kw_delete) && + Right.isNot(TT_OverloadedOperatorLParen) && + !(Line.MightBeFunctionDecl && Left.is(TT_FunctionDeclarationName))) { + if (Style.SpaceBeforeParensOptions.AfterPlacementOperator == + FormatStyle::SpaceBeforeParensCustom::APO_Always || + (Style.SpaceBeforeParensOptions.AfterPlacementOperator == + FormatStyle::SpaceBeforeParensCustom::APO_Leave && + Right.hasWhitespaceBefore())) { + return true; + } + return false; + } if (Line.Type == LT_ObjCDecl) return true; if (Left.is(tok::semi)) @@ -4732,10 +4741,9 @@ bool TokenAnnotator::spaceRequiredBefore(const AnnotatedLine &Line, return false; } - if (Right.isOneOf(TT_TrailingReturnArrow, TT_LambdaArrow) || - Left.isOneOf(TT_TrailingReturnArrow, TT_LambdaArrow)) { + if (Right.is(TT_TrailingReturnArrow) || Left.is(TT_TrailingReturnArrow)) return true; - } + if (Left.is(tok::comma) && Right.isNot(TT_OverloadedOperatorLParen) && // In an unexpanded macro call we only find the parentheses and commas // in a line; the commas and closing parenthesis do not require a space. @@ -5105,10 +5113,6 @@ bool TokenAnnotator::mustBreakBefore(const AnnotatedLine &Line, return true; if (Left.IsUnterminatedLiteral) return true; - if (Right.is(tok::lessless) && Right.Next && Left.is(tok::string_literal) && - Right.Next->is(tok::string_literal)) { - return true; - } if (Right.is(TT_RequiresClause)) { switch (Style.RequiresClausePosition) { case FormatStyle::RCPS_OwnLine: @@ -5716,8 +5720,8 @@ bool TokenAnnotator::canBreakBefore(const AnnotatedLine &Line, return Left.isOneOf(tok::comma, tok::coloncolon, tok::semi, tok::l_brace, tok::kw_class, tok::kw_struct, tok::comment) || Right.isMemberAccess() || - Right.isOneOf(TT_TrailingReturnArrow, TT_LambdaArrow, tok::lessless, - tok::colon, tok::l_square, tok::at) || + Right.isOneOf(TT_TrailingReturnArrow, tok::lessless, tok::colon, + tok::l_square, tok::at) || (Left.is(tok::r_paren) && Right.isOneOf(tok::identifier, tok::kw_const)) || (Left.is(tok::l_paren) && Right.isNot(tok::r_paren)) || diff --git a/clang/lib/Format/UnwrappedLineFormatter.cpp b/clang/lib/Format/UnwrappedLineFormatter.cpp index 0dcf3b7c8dd06..280485d9a90d1 100644 --- a/clang/lib/Format/UnwrappedLineFormatter.cpp +++ b/clang/lib/Format/UnwrappedLineFormatter.cpp @@ -520,6 +520,8 @@ class LineJoiner { // Try to merge records. if (TheLine->Last->is(TT_EnumLBrace)) { ShouldMerge = Style.AllowShortEnumsOnASingleLine; + } else if (TheLine->Last->is(TT_RequiresExpressionLBrace)) { + ShouldMerge = Style.AllowShortCompoundRequirementOnASingleLine; } else if (TheLine->Last->isOneOf(TT_ClassLBrace, TT_StructLBrace)) { // NOTE: We use AfterClass (whereas AfterStruct exists) for both classes // and structs, but it seems that wrapping is still handled correctly diff --git a/clang/lib/Format/UnwrappedLineParser.cpp b/clang/lib/Format/UnwrappedLineParser.cpp index 7bb487d020ea6..30f9bcbfa2930 100644 --- a/clang/lib/Format/UnwrappedLineParser.cpp +++ b/clang/lib/Format/UnwrappedLineParser.cpp @@ -2256,7 +2256,7 @@ bool UnwrappedLineParser::tryToParseLambda() { // This might or might not actually be a lambda arrow (this could be an // ObjC method invocation followed by a dereferencing arrow). We might // reset this back to TT_Unknown in TokenAnnotator. - FormatTok->setFinalizedType(TT_LambdaArrow); + FormatTok->setFinalizedType(TT_TrailingReturnArrow); SeenArrow = true; nextToken(); break; @@ -3137,6 +3137,8 @@ void UnwrappedLineParser::parseDoWhile() { return; } + FormatTok->setFinalizedType(TT_DoWhile); + // If in Whitesmiths mode, the line with the while() needs to be indented // to the same level as the block. if (Style.BreakBeforeBraces == FormatStyle::BS_Whitesmiths) diff --git a/clang/lib/Format/WhitespaceManager.cpp b/clang/lib/Format/WhitespaceManager.cpp index dc81060671c17..ff8b1e6e13a3f 100644 --- a/clang/lib/Format/WhitespaceManager.cpp +++ b/clang/lib/Format/WhitespaceManager.cpp @@ -980,7 +980,7 @@ void WhitespaceManager::alignConsecutiveDeclarations() { AlignTokens( Style, [](Change const &C) { - if (C.Tok->isOneOf(TT_FunctionDeclarationName, TT_FunctionTypeLParen)) + if (C.Tok->is(TT_FunctionDeclarationName)) return true; if (C.Tok->isNot(TT_StartOfName)) return false; @@ -1048,6 +1048,9 @@ void WhitespaceManager::alignChainedConditionals() { } void WhitespaceManager::alignTrailingComments() { + if (Style.AlignTrailingComments.Kind == FormatStyle::TCAS_Never) + return; + const int Size = Changes.size(); int MinColumn = 0; int StartOfSequence = 0; @@ -1118,16 +1121,48 @@ void WhitespaceManager::alignTrailingComments() { } } - // We don't want to align namespace end comments. - const bool DontAlignThisComment = - I > 0 && C.NewlinesBefore == 0 && - Changes[I - 1].Tok->is(TT_NamespaceRBrace); - if (Style.AlignTrailingComments.Kind == FormatStyle::TCAS_Never || - DontAlignThisComment) { + // We don't want to align comments which end a scope, which are here + // identified by most closing braces. + auto DontAlignThisComment = [](const auto *Tok) { + if (Tok->is(tok::semi)) { + Tok = Tok->getPreviousNonComment(); + if (!Tok) + return false; + } + if (Tok->is(tok::r_paren)) { + // Back up past the parentheses and a `TT_DoWhile` that may precede. + Tok = Tok->MatchingParen; + if (!Tok) + return false; + Tok = Tok->getPreviousNonComment(); + if (!Tok) + return false; + if (Tok->is(TT_DoWhile)) { + const auto *Prev = Tok->getPreviousNonComment(); + if (!Prev) { + // A do-while-loop without braces. + return true; + } + Tok = Prev; + } + } + + if (Tok->isNot(tok::r_brace)) + return false; + + while (Tok->Previous && Tok->Previous->is(tok::r_brace)) + Tok = Tok->Previous; + return Tok->NewlinesBefore > 0; + }; + + if (I > 0 && C.NewlinesBefore == 0 && + DontAlignThisComment(Changes[I - 1].Tok)) { alignTrailingComments(StartOfSequence, I, MinColumn); - MinColumn = ChangeMinColumn; - MaxColumn = ChangeMinColumn; - StartOfSequence = I; + // Reset to initial values, but skip this change for the next alignment + // pass. + MinColumn = 0; + MaxColumn = INT_MAX; + StartOfSequence = I + 1; } else if (BreakBeforeNext || Newlines > NewLineThreshold || (ChangeMinColumn > MaxColumn || ChangeMaxColumn < MinColumn) || // Break the comment sequence if the previous line did not end diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp index 4e6d7bb16f51b..fd6c250efeda2 100644 --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -3163,8 +3163,8 @@ static bool ParseHeaderSearchArgs(HeaderSearchOptions &Opts, ArgList &Args, StringRef Val = A->getValue(); if (Val.contains('=')) { auto Split = Val.split('='); - Opts.PrebuiltModuleFiles.insert( - {std::string(Split.first), std::string(Split.second)}); + Opts.PrebuiltModuleFiles.insert_or_assign( + std::string(Split.first), std::string(Split.second)); } } for (const auto *A : Args.filtered(OPT_fprebuilt_module_path)) diff --git a/clang/lib/Frontend/Rewrite/InclusionRewriter.cpp b/clang/lib/Frontend/Rewrite/InclusionRewriter.cpp index 28f7b0b9edfc5..2c3a253a67d5c 100644 --- a/clang/lib/Frontend/Rewrite/InclusionRewriter.cpp +++ b/clang/lib/Frontend/Rewrite/InclusionRewriter.cpp @@ -444,8 +444,11 @@ void InclusionRewriter::Process(FileID FileId, if (Mod) OS << "#pragma clang module end /*" << Mod->getFullModuleName(true) << "*/\n"; - OS << "#endif /* " << getIncludedFileName(Inc) - << " expanded by -frewrite-includes */" << LocalEOL; + // There's no #include, therefore no #if, for -include files. + if (FromFile != PredefinesBuffer) { + OS << "#endif /* " << getIncludedFileName(Inc) + << " expanded by -frewrite-includes */" << LocalEOL; + } // Add line marker to indicate we're returning from an included // file. diff --git a/clang/lib/Headers/immintrin.h b/clang/lib/Headers/immintrin.h index 642602be14e60..9bfe2fcdabdb3 100644 --- a/clang/lib/Headers/immintrin.h +++ b/clang/lib/Headers/immintrin.h @@ -291,11 +291,13 @@ #if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) || \ defined(__RDPID__) -/// Returns the value of the IA32_TSC_AUX MSR (0xc0000103). +/// Reads the value of the IA32_TSC_AUX MSR (0xc0000103). /// /// \headerfile /// /// This intrinsic corresponds to the RDPID instruction. +/// +/// \returns The 32-bit contents of the MSR. static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__, __target__("rdpid"))) _rdpid_u32(void) { return __builtin_ia32_rdpid(); diff --git a/clang/lib/Headers/llvm_libc_wrappers/string.h b/clang/lib/Headers/llvm_libc_wrappers/string.h index 027c415c1d0f8..b4fbf17c7e421 100644 --- a/clang/lib/Headers/llvm_libc_wrappers/string.h +++ b/clang/lib/Headers/llvm_libc_wrappers/string.h @@ -13,9 +13,6 @@ #error "This file is for GPU offloading compilation only" #endif -// FIXME: The GNU headers provide C++ standard compliant headers when in C++ -// mode and the LLVM libc does not. We cannot enable memchr, strchr, strchrnul, -// strpbrk, strrchr, strstr, or strcasestr until this is addressed. #include_next #if __has_include() @@ -26,8 +23,70 @@ #pragma omp begin declare target +// The GNU headers provide C++ standard compliant headers when in C++ mode and +// the LLVM libc does not. We need to manually provide the definitions using the +// same prototypes. +#if defined(__cplusplus) && defined(__GLIBC__) && \ + defined(__CORRECT_ISO_CPP_STRING_H_PROTO) + +#ifndef __LIBC_ATTRS +#define __LIBC_ATTRS +#endif + +extern "C" { +void *memccpy(void *__restrict, const void *__restrict, int, + size_t) __LIBC_ATTRS; +int memcmp(const void *, const void *, size_t) __LIBC_ATTRS; +void *memcpy(void *__restrict, const void *__restrict, size_t) __LIBC_ATTRS; +void *memmem(const void *, size_t, const void *, size_t) __LIBC_ATTRS; +void *memmove(void *, const void *, size_t) __LIBC_ATTRS; +void *mempcpy(void *__restrict, const void *__restrict, size_t) __LIBC_ATTRS; +void *memset(void *, int, size_t) __LIBC_ATTRS; +char *stpcpy(char *__restrict, const char *__restrict) __LIBC_ATTRS; +char *stpncpy(char *__restrict, const char *__restrict, size_t) __LIBC_ATTRS; +char *strcat(char *__restrict, const char *__restrict) __LIBC_ATTRS; +int strcmp(const char *, const char *) __LIBC_ATTRS; +int strcoll(const char *, const char *) __LIBC_ATTRS; +char *strcpy(char *__restrict, const char *__restrict) __LIBC_ATTRS; +size_t strcspn(const char *, const char *) __LIBC_ATTRS; +char *strdup(const char *) __LIBC_ATTRS; +size_t strlen(const char *) __LIBC_ATTRS; +char *strncat(char *, const char *, size_t) __LIBC_ATTRS; +int strncmp(const char *, const char *, size_t) __LIBC_ATTRS; +char *strncpy(char *__restrict, const char *__restrict, size_t) __LIBC_ATTRS; +char *strndup(const char *, size_t) __LIBC_ATTRS; +size_t strnlen(const char *, size_t) __LIBC_ATTRS; +size_t strspn(const char *, const char *) __LIBC_ATTRS; +char *strtok(char *__restrict, const char *) __LIBC_ATTRS; +char *strtok_r(char *__restrict, const char *__restrict, + char **__restrict) __LIBC_ATTRS; +size_t strxfrm(char *__restrict, const char *__restrict, size_t) __LIBC_ATTRS; +} + +extern "C++" { +char *strstr(char *, const char *) noexcept __LIBC_ATTRS; +const char *strstr(const char *, const char *) noexcept __LIBC_ATTRS; +char *strpbrk(char *, const char *) noexcept __LIBC_ATTRS; +const char *strpbrk(const char *, const char *) noexcept __LIBC_ATTRS; +char *strrchr(char *, int) noexcept __LIBC_ATTRS; +const char *strrchr(const char *, int) noexcept __LIBC_ATTRS; +char *strchr(char *, int) noexcept __LIBC_ATTRS; +const char *strchr(const char *, int) noexcept __LIBC_ATTRS; +char *strchrnul(char *, int) noexcept __LIBC_ATTRS; +const char *strchrnul(const char *, int) noexcept __LIBC_ATTRS; +char *strcasestr(char *, const char *) noexcept __LIBC_ATTRS; +const char *strcasestr(const char *, const char *) noexcept __LIBC_ATTRS; +void *memrchr(void *__s, int __c, size_t __n) noexcept __LIBC_ATTRS; +const void *memrchr(const void *__s, int __c, size_t __n) noexcept __LIBC_ATTRS; +void *memchr(void *__s, int __c, size_t __n) noexcept __LIBC_ATTRS; +const void *memchr(const void *__s, int __c, size_t __n) noexcept __LIBC_ATTRS; +} + +#else #include +#endif + #pragma omp end declare target #undef __LIBC_ATTRS diff --git a/clang/lib/Headers/ppc_wrappers/smmintrin.h b/clang/lib/Headers/ppc_wrappers/smmintrin.h index 349b395c4f00b..19cdecb18d2b8 100644 --- a/clang/lib/Headers/ppc_wrappers/smmintrin.h +++ b/clang/lib/Headers/ppc_wrappers/smmintrin.h @@ -14,7 +14,7 @@ #ifndef NO_WARN_X86_INTRINSICS /* This header is distributed to simplify porting x86_64 code that - makes explicit use of Intel intrinsics to powerp64/powerpc64le. + makes explicit use of Intel intrinsics to powerpc64/powerpc64le. It is the user's responsibility to determine if the results are acceptable and make additional changes as necessary. @@ -68,10 +68,10 @@ extern __inline __m128d __asm__("mffsce %0" : "=f"(__fpscr_save.__fr)); __enables_save.__fpscr = __fpscr_save.__fpscr & 0xf8; #else - __fpscr_save.__fr = __builtin_mffs(); + __fpscr_save.__fr = __builtin_ppc_mffs(); __enables_save.__fpscr = __fpscr_save.__fpscr & 0xf8; __fpscr_save.__fpscr &= ~0xf8; - __builtin_mtfsf(0b00000011, __fpscr_save.__fr); + __builtin_ppc_mtfsf(0b00000011, __fpscr_save.__fr); #endif /* Insert an artificial "read/write" reference to the variable read below, to ensure the compiler does not schedule @@ -83,10 +83,15 @@ extern __inline __m128d switch (__rounding) { case _MM_FROUND_TO_NEAREST_INT: - __fpscr_save.__fr = __builtin_mffsl(); +#ifdef _ARCH_PWR9 + __fpscr_save.__fr = __builtin_ppc_mffsl(); +#else + __fpscr_save.__fr = __builtin_ppc_mffs(); + __fpscr_save.__fpscr &= 0x70007f0ffL; +#endif __attribute__((fallthrough)); case _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC: - __builtin_set_fpscr_rn(0b00); + __builtin_ppc_set_fpscr_rn(0b00); /* Insert an artificial "read/write" reference to the variable read below, to ensure the compiler does not schedule a read/use of the variable before the FPSCR is modified, above. @@ -102,7 +107,7 @@ extern __inline __m128d This can be removed if and when GCC PR102783 is fixed. */ __asm__("" : : "wa"(__r)); - __builtin_set_fpscr_rn(__fpscr_save.__fpscr); + __builtin_ppc_set_fpscr_rn(__fpscr_save.__fpscr); break; case _MM_FROUND_TO_NEG_INF: case _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC: @@ -128,9 +133,14 @@ extern __inline __m128d */ __asm__("" : : "wa"(__r)); /* Restore enabled exceptions. */ - __fpscr_save.__fr = __builtin_mffsl(); +#ifdef _ARCH_PWR9 + __fpscr_save.__fr = __builtin_ppc_mffsl(); +#else + __fpscr_save.__fr = __builtin_ppc_mffs(); + __fpscr_save.__fpscr &= 0x70007f0ffL; +#endif __fpscr_save.__fpscr |= __enables_save.__fpscr; - __builtin_mtfsf(0b00000011, __fpscr_save.__fr); + __builtin_ppc_mtfsf(0b00000011, __fpscr_save.__fr); } return (__m128d)__r; } @@ -159,10 +169,10 @@ extern __inline __m128 __asm__("mffsce %0" : "=f"(__fpscr_save.__fr)); __enables_save.__fpscr = __fpscr_save.__fpscr & 0xf8; #else - __fpscr_save.__fr = __builtin_mffs(); + __fpscr_save.__fr = __builtin_ppc_mffs(); __enables_save.__fpscr = __fpscr_save.__fpscr & 0xf8; __fpscr_save.__fpscr &= ~0xf8; - __builtin_mtfsf(0b00000011, __fpscr_save.__fr); + __builtin_ppc_mtfsf(0b00000011, __fpscr_save.__fr); #endif /* Insert an artificial "read/write" reference to the variable read below, to ensure the compiler does not schedule @@ -174,10 +184,15 @@ extern __inline __m128 switch (__rounding) { case _MM_FROUND_TO_NEAREST_INT: - __fpscr_save.__fr = __builtin_mffsl(); +#ifdef _ARCH_PWR9 + __fpscr_save.__fr = __builtin_ppc_mffsl(); +#else + __fpscr_save.__fr = __builtin_ppc_mffs(); + __fpscr_save.__fpscr &= 0x70007f0ffL; +#endif __attribute__((fallthrough)); case _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC: - __builtin_set_fpscr_rn(0b00); + __builtin_ppc_set_fpscr_rn(0b00); /* Insert an artificial "read/write" reference to the variable read below, to ensure the compiler does not schedule a read/use of the variable before the FPSCR is modified, above. @@ -193,7 +208,7 @@ extern __inline __m128 This can be removed if and when GCC PR102783 is fixed. */ __asm__("" : : "wa"(__r)); - __builtin_set_fpscr_rn(__fpscr_save.__fpscr); + __builtin_ppc_set_fpscr_rn(__fpscr_save.__fpscr); break; case _MM_FROUND_TO_NEG_INF: case _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC: @@ -219,9 +234,14 @@ extern __inline __m128 */ __asm__("" : : "wa"(__r)); /* Restore enabled exceptions. */ - __fpscr_save.__fr = __builtin_mffsl(); +#ifdef _ARCH_PWR9 + __fpscr_save.__fr = __builtin_ppc_mffsl(); +#else + __fpscr_save.__fr = __builtin_ppc_mffs(); + __fpscr_save.__fpscr &= 0x70007f0ffL; +#endif __fpscr_save.__fpscr |= __enables_save.__fpscr; - __builtin_mtfsf(0b00000011, __fpscr_save.__fr); + __builtin_ppc_mtfsf(0b00000011, __fpscr_save.__fr); } return (__m128)__r; } diff --git a/clang/lib/Headers/stdckdint.h b/clang/lib/Headers/stdckdint.h index 22972d78d9077..20bc34ffb3023 100644 --- a/clang/lib/Headers/stdckdint.h +++ b/clang/lib/Headers/stdckdint.h @@ -21,7 +21,6 @@ /* C23 7.20.1 Defines several macros for performing checked integer arithmetic*/ -#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 202311L #define __STDC_VERSION_STDCKDINT_H__ 202311L // Both A and B shall be any integer type other than "plain" char, bool, a bit- @@ -38,7 +37,6 @@ #define ckd_add(R, A, B) __builtin_add_overflow((A), (B), (R)) #define ckd_sub(R, A, B) __builtin_sub_overflow((A), (B), (R)) #define ckd_mul(R, A, B) __builtin_mul_overflow((A), (B), (R)) -#endif #endif /* __STDC_HOSTED__ */ #endif /* __STDCKDINT_H */ diff --git a/clang/lib/Lex/HeaderSearch.cpp b/clang/lib/Lex/HeaderSearch.cpp index 4c8b64a374b47..cf1c0cc5284f3 100644 --- a/clang/lib/Lex/HeaderSearch.cpp +++ b/clang/lib/Lex/HeaderSearch.cpp @@ -1623,7 +1623,7 @@ bool HeaderSearch::findUsableModuleForHeader( ModuleMap::KnownHeader *SuggestedModule, bool IsSystemHeaderDir) { if (needModuleLookup(RequestingModule, SuggestedModule)) { // If there is a module that corresponds to this header, suggest it. - hasModuleMap(File.getName(), Root, IsSystemHeaderDir); + hasModuleMap(File.getNameAsRequested(), Root, IsSystemHeaderDir); return suggestModule(*this, File, RequestingModule, SuggestedModule); } return true; diff --git a/clang/lib/Lex/ModuleMap.cpp b/clang/lib/Lex/ModuleMap.cpp index f65a5f145c043..e4f3cdd3b163f 100644 --- a/clang/lib/Lex/ModuleMap.cpp +++ b/clang/lib/Lex/ModuleMap.cpp @@ -348,8 +348,8 @@ bool ModuleMap::resolveAsBuiltinHeader( if (!File) return false; + Module::Header H = {Header.FileName, Header.FileName, *File}; auto Role = headerKindToRole(Header.Kind); - Module::Header H = {Header.FileName, std::string(Path.str()), *File}; addHeader(Mod, H, Role); return true; } @@ -417,6 +417,13 @@ bool ModuleMap::isBuiltinHeader(FileEntryRef File) { isBuiltinHeaderName(llvm::sys::path::filename(File.getName())); } +bool ModuleMap::shouldImportRelativeToBuiltinIncludeDir(StringRef FileName, + Module *Module) const { + return LangOpts.BuiltinHeadersInSystemModules && BuiltinIncludeDir && + Module->IsSystem && !Module->isPartOfFramework() && + isBuiltinHeaderName(FileName); +} + ModuleMap::HeadersMap::iterator ModuleMap::findKnownHeader(FileEntryRef File) { resolveHeaderDirectives(File); HeadersMap::iterator Known = Headers.find(File); @@ -1398,16 +1405,17 @@ bool ModuleMap::resolveExports(Module *Mod, bool Complain) { } bool ModuleMap::resolveUses(Module *Mod, bool Complain) { - auto Unresolved = std::move(Mod->UnresolvedDirectUses); - Mod->UnresolvedDirectUses.clear(); + auto *Top = Mod->getTopLevelModule(); + auto Unresolved = std::move(Top->UnresolvedDirectUses); + Top->UnresolvedDirectUses.clear(); for (auto &UDU : Unresolved) { - Module *DirectUse = resolveModuleId(UDU, Mod, Complain); + Module *DirectUse = resolveModuleId(UDU, Top, Complain); if (DirectUse) - Mod->DirectUses.push_back(DirectUse); + Top->DirectUses.push_back(DirectUse); else - Mod->UnresolvedDirectUses.push_back(UDU); + Top->UnresolvedDirectUses.push_back(UDU); } - return !Mod->UnresolvedDirectUses.empty(); + return !Top->UnresolvedDirectUses.empty(); } bool ModuleMap::resolveConflicts(Module *Mod, bool Complain) { @@ -2426,7 +2434,8 @@ void ModuleMapParser::parseHeaderDecl(MMToken::TokenKind LeadingToken, Header.Kind = Map.headerRoleToKind(Role); // Check whether we already have an umbrella. - if (Header.IsUmbrella && ActiveModule->Umbrella) { + if (Header.IsUmbrella && + !std::holds_alternative(ActiveModule->Umbrella)) { Diags.Report(Header.FileNameLoc, diag::err_mmap_umbrella_clash) << ActiveModule->getFullModuleName(); HadError = true; @@ -2523,7 +2532,7 @@ void ModuleMapParser::parseUmbrellaDirDecl(SourceLocation UmbrellaLoc) { SourceLocation DirNameLoc = consumeToken(); // Check whether we already have an umbrella. - if (ActiveModule->Umbrella) { + if (!std::holds_alternative(ActiveModule->Umbrella)) { Diags.Report(DirNameLoc, diag::err_mmap_umbrella_clash) << ActiveModule->getFullModuleName(); HadError = true; diff --git a/clang/lib/Lex/PPDirectives.cpp b/clang/lib/Lex/PPDirectives.cpp index 2892d4b777846..6fd515a5f0c75 100644 --- a/clang/lib/Lex/PPDirectives.cpp +++ b/clang/lib/Lex/PPDirectives.cpp @@ -12,6 +12,7 @@ //===----------------------------------------------------------------------===// #include "clang/Basic/CharInfo.h" +#include "clang/Basic/DirectoryEntry.h" #include "clang/Basic/FileManager.h" #include "clang/Basic/IdentifierTable.h" #include "clang/Basic/LangOptions.h" @@ -21,6 +22,7 @@ #include "clang/Basic/TokenKinds.h" #include "clang/Lex/CodeCompletionHandler.h" #include "clang/Lex/HeaderSearch.h" +#include "clang/Lex/HeaderSearchOptions.h" #include "clang/Lex/LexDiagnostic.h" #include "clang/Lex/LiteralSupport.h" #include "clang/Lex/MacroInfo.h" @@ -982,7 +984,12 @@ OptionalFileEntryRef Preprocessor::LookupFile( // map file. if (!FileEnt) { if (FID == SourceMgr.getMainFileID() && MainFileDir) { - Includers.push_back(std::make_pair(std::nullopt, *MainFileDir)); + auto IncludeDir = + HeaderInfo.getModuleMap().shouldImportRelativeToBuiltinIncludeDir( + Filename, getCurrentModule()) + ? HeaderInfo.getModuleMap().getBuiltinDir() + : MainFileDir; + Includers.push_back(std::make_pair(std::nullopt, *IncludeDir)); BuildSystemModule = getCurrentModule()->IsSystem; } else if ((FileEnt = SourceMgr.getFileEntryRefForID( SourceMgr.getMainFileID()))) { diff --git a/clang/lib/Lex/PPMacroExpansion.cpp b/clang/lib/Lex/PPMacroExpansion.cpp index b371f8cf7a9c0..30c4abdbad8aa 100644 --- a/clang/lib/Lex/PPMacroExpansion.cpp +++ b/clang/lib/Lex/PPMacroExpansion.cpp @@ -1248,10 +1248,15 @@ static bool EvaluateHasIncludeCommon(Token &Tok, IdentifierInfo *II, if (Filename.empty()) return false; + // Passing this to LookupFile forces header search to check whether the found + // file belongs to a module. Skipping that check could incorrectly mark + // modular header as textual, causing issues down the line. + ModuleMap::KnownHeader KH; + // Search include directories. OptionalFileEntryRef File = PP.LookupFile(FilenameLoc, Filename, isAngled, LookupFrom, LookupFromFile, - nullptr, nullptr, nullptr, nullptr, nullptr, nullptr); + nullptr, nullptr, nullptr, &KH, nullptr, nullptr); if (PPCallbacks *Callbacks = PP.getPPCallbacks()) { SrcMgr::CharacteristicKind FileType = SrcMgr::C_User; diff --git a/clang/lib/Parse/ParseDecl.cpp b/clang/lib/Parse/ParseDecl.cpp index 14a28e5a31c57..78c3ab72979a0 100644 --- a/clang/lib/Parse/ParseDecl.cpp +++ b/clang/lib/Parse/ParseDecl.cpp @@ -4076,8 +4076,15 @@ void Parser::ParseDeclarationSpecifiers( case tok::kw_thread_local: if (getLangOpts().C23) Diag(Tok, diag::warn_c23_compat_keyword) << Tok.getName(); - isInvalid = DS.SetStorageClassSpecThread(DeclSpec::TSCS_thread_local, Loc, - PrevSpec, DiagID); + // We map thread_local to _Thread_local in C23 mode so it retains the C + // semantics rather than getting the C++ semantics. + // FIXME: diagnostics will show _Thread_local when the user wrote + // thread_local in source in C23 mode; we need some general way to + // identify which way the user spelled the keyword in source. + isInvalid = DS.SetStorageClassSpecThread( + getLangOpts().C23 ? DeclSpec::TSCS__Thread_local + : DeclSpec::TSCS_thread_local, + Loc, PrevSpec, DiagID); isStorageClass = true; break; case tok::kw__Thread_local: diff --git a/clang/lib/Parse/ParseExpr.cpp b/clang/lib/Parse/ParseExpr.cpp index 4d267c915ff24..dd2d9400b7747 100644 --- a/clang/lib/Parse/ParseExpr.cpp +++ b/clang/lib/Parse/ParseExpr.cpp @@ -1574,9 +1574,6 @@ ExprResult Parser::ParseCastExpression(CastParseKind ParseKind, case tok::kw_typename: case tok::kw_typeof: case tok::kw___vector: - case tok::kw__Accum: - case tok::kw__Fract: - case tok::kw__Sat: #define GENERIC_IMAGE_TYPE(ImgType, Id) case tok::kw_##ImgType##_t: #include "clang/Basic/OpenCLImageTypes.def" { diff --git a/clang/lib/Parse/ParseExprCXX.cpp b/clang/lib/Parse/ParseExprCXX.cpp index 79db094e098f8..99b4931004546 100644 --- a/clang/lib/Parse/ParseExprCXX.cpp +++ b/clang/lib/Parse/ParseExprCXX.cpp @@ -2354,15 +2354,6 @@ void Parser::ParseCXXSimpleTypeSpecifier(DeclSpec &DS) { case tok::kw_bool: DS.SetTypeSpecType(DeclSpec::TST_bool, Loc, PrevSpec, DiagID, Policy); break; - case tok::kw__Accum: - DS.SetTypeSpecType(DeclSpec::TST_accum, Loc, PrevSpec, DiagID, Policy); - break; - case tok::kw__Fract: - DS.SetTypeSpecType(DeclSpec::TST_fract, Loc, PrevSpec, DiagID, Policy); - break; - case tok::kw__Sat: - DS.SetTypeSpecSat(Loc, PrevSpec, DiagID); - break; #define GENERIC_IMAGE_TYPE(ImgType, Id) \ case tok::kw_##ImgType##_t: \ DS.SetTypeSpecType(DeclSpec::TST_##ImgType##_t, Loc, PrevSpec, DiagID, \ diff --git a/clang/lib/Parse/ParseOpenMP.cpp b/clang/lib/Parse/ParseOpenMP.cpp index 995834a78c795..3e7d8274aeefc 100644 --- a/clang/lib/Parse/ParseOpenMP.cpp +++ b/clang/lib/Parse/ParseOpenMP.cpp @@ -4198,6 +4198,10 @@ bool Parser::parseMapTypeModifiers(Sema::OpenMPVarListDataTy &Data) { TypeModifier == OMPC_MAP_MODIFIER_ompx_hold) { Data.MapTypeModifiers.push_back(TypeModifier); Data.MapTypeModifiersLoc.push_back(Tok.getLocation()); + if (PP.LookAhead(0).isNot(tok::comma) && + PP.LookAhead(0).isNot(tok::colon) && getLangOpts().OpenMP >= 52) + Diag(Tok.getLocation(), diag::err_omp_missing_comma) + << "map type modifier"; ConsumeToken(); } else if (TypeModifier == OMPC_MAP_MODIFIER_mapper) { Data.MapTypeModifiers.push_back(TypeModifier); @@ -4205,6 +4209,11 @@ bool Parser::parseMapTypeModifiers(Sema::OpenMPVarListDataTy &Data) { ConsumeToken(); if (parseMapperModifier(Data)) return true; + if (Tok.isNot(tok::comma) && Tok.isNot(tok::colon) && + getLangOpts().OpenMP >= 52) + Diag(Data.MapTypeModifiersLoc.back(), diag::err_omp_missing_comma) + << "map type modifier"; + } else { // For the case of unknown map-type-modifier or a map-type. // Map-type is followed by a colon; the function returns when it @@ -4392,6 +4401,25 @@ bool Parser::ParseOpenMPReservedLocator(OpenMPClauseKind Kind, return false; } +/// Parse step size expression. Returns true if parsing is successfull, +/// otherwise returns false. +static bool parseStepSize(Parser &P, Sema::OpenMPVarListDataTy &Data, + OpenMPClauseKind CKind, SourceLocation ELoc) { + ExprResult Tail = P.ParseAssignmentExpression(); + Sema &Actions = P.getActions(); + Tail = Actions.ActOnFinishFullExpr(Tail.get(), ELoc, + /*DiscardedValue*/ false); + if (Tail.isUsable()) { + Data.DepModOrTailExpr = Tail.get(); + Token CurTok = P.getCurToken(); + if (CurTok.isNot(tok::r_paren) && CurTok.isNot(tok::comma)) { + P.Diag(CurTok, diag::err_expected_punc) << "step expression"; + } + return true; + } + return false; +} + /// Parses clauses with list. bool Parser::ParseOpenMPVarList(OpenMPDirectiveKind DKind, OpenMPClauseKind Kind, @@ -4545,6 +4573,10 @@ bool Parser::ParseOpenMPVarList(OpenMPDirectiveKind DKind, Data.ExtraModifierLoc = ConsumeToken(); LinearT.consumeOpen(); NeedRParenForLinear = true; + if (getLangOpts().OpenMP >= 52) + Diag(Data.ExtraModifierLoc, diag::err_omp_deprecate_old_syntax) + << "linear-modifier(list)" << getOpenMPClauseName(Kind) + << "linear(list: [linear-modifier,] step(step-size))"; } } else if (Kind == OMPC_lastprivate) { // Try to parse modifier if any. @@ -4754,19 +4786,76 @@ bool Parser::ParseOpenMPVarList(OpenMPDirectiveKind DKind, if (NeedRParenForLinear) LinearT.consumeClose(); - // Parse ':' linear-step (or ':' alignment). + // Parse ':' linear modifiers (val, uval, ref or step(step-size)) + // or parse ':' alignment. const bool MustHaveTail = MayHaveTail && Tok.is(tok::colon); + bool StepFound = false; + bool ModifierFound = false; if (MustHaveTail) { Data.ColonLoc = Tok.getLocation(); SourceLocation ELoc = ConsumeToken(); - ExprResult Tail = ParseAssignmentExpression(); - Tail = - Actions.ActOnFinishFullExpr(Tail.get(), ELoc, /*DiscardedValue*/ false); - if (Tail.isUsable()) - Data.DepModOrTailExpr = Tail.get(); - else - SkipUntil(tok::comma, tok::r_paren, tok::annot_pragma_openmp_end, - StopBeforeMatch); + + if (getLangOpts().OpenMP >= 52 && Kind == OMPC_linear) { + while (Tok.isNot(tok::r_paren)) { + if (Tok.is(tok::identifier)) { + // identifier could be a linear kind (val, uval, ref) or step + // modifier or step size + OpenMPLinearClauseKind LinKind = + static_cast(getOpenMPSimpleClauseType( + Kind, Tok.isAnnotation() ? "" : PP.getSpelling(Tok), + getLangOpts())); + + if (LinKind == OMPC_LINEAR_step) { + if (StepFound) + Diag(Tok, diag::err_omp_multiple_step_or_linear_modifier) << 0; + + BalancedDelimiterTracker StepT(*this, tok::l_paren, + tok::annot_pragma_openmp_end); + SourceLocation StepModifierLoc = ConsumeToken(); + // parse '(' + if (StepT.consumeOpen()) + Diag(StepModifierLoc, diag::err_expected_lparen_after) << "step"; + + // parse step size expression + StepFound = parseStepSize(*this, Data, Kind, Tok.getLocation()); + if (StepFound) + Data.StepModifierLoc = StepModifierLoc; + + // parse ')' + StepT.consumeClose(); + } else if (LinKind >= 0 && LinKind < OMPC_LINEAR_step) { + if (ModifierFound) + Diag(Tok, diag::err_omp_multiple_step_or_linear_modifier) << 1; + + Data.ExtraModifier = LinKind; + Data.ExtraModifierLoc = ConsumeToken(); + ModifierFound = true; + } else { + StepFound = parseStepSize(*this, Data, Kind, Tok.getLocation()); + } + } else { + // parse an integer expression as step size + StepFound = parseStepSize(*this, Data, Kind, Tok.getLocation()); + } + + if (Tok.is(tok::comma)) + ConsumeToken(); + if (Tok.is(tok::r_paren) || Tok.is(tok::annot_pragma_openmp_end)) + break; + } + if (!StepFound && !ModifierFound) + Diag(ELoc, diag::err_expected_expression); + } else { + // for OMPC_aligned and OMPC_linear (with OpenMP <= 5.1) + ExprResult Tail = ParseAssignmentExpression(); + Tail = Actions.ActOnFinishFullExpr(Tail.get(), ELoc, + /*DiscardedValue*/ false); + if (Tail.isUsable()) + Data.DepModOrTailExpr = Tail.get(); + else + SkipUntil(tok::comma, tok::r_paren, tok::annot_pragma_openmp_end, + StopBeforeMatch); + } } // Parse ')'. @@ -4778,8 +4867,8 @@ bool Parser::ParseOpenMPVarList(OpenMPDirectiveKind DKind, ExitScope(); return (Kind != OMPC_depend && Kind != OMPC_doacross && Kind != OMPC_map && Vars.empty()) || - (MustHaveTail && !Data.DepModOrTailExpr) || InvalidReductionId || - IsInvalidMapperModifier || InvalidIterator; + (MustHaveTail && !Data.DepModOrTailExpr && StepFound) || + InvalidReductionId || IsInvalidMapperModifier || InvalidIterator; } /// Parsing of OpenMP clause 'private', 'firstprivate', 'lastprivate', diff --git a/clang/lib/Parse/ParseTentative.cpp b/clang/lib/Parse/ParseTentative.cpp index 8b653b1c4f8ea..28decc4fc43f9 100644 --- a/clang/lib/Parse/ParseTentative.cpp +++ b/clang/lib/Parse/ParseTentative.cpp @@ -1775,9 +1775,6 @@ Parser::isCXXDeclarationSpecifier(ImplicitTypenameContext AllowImplicitTypename, case tok::kw___ibm128: case tok::kw_void: case tok::annot_decltype: - case tok::kw__Accum: - case tok::kw__Fract: - case tok::kw__Sat: #define GENERIC_IMAGE_TYPE(ImgType, Id) case tok::kw_##ImgType##_t: #include "clang/Basic/OpenCLImageTypes.def" if (NextToken().is(tok::l_paren)) @@ -1897,9 +1894,6 @@ bool Parser::isCXXDeclarationSpecifierAType() { case tok::kw_void: case tok::kw___unknown_anytype: case tok::kw___auto_type: - case tok::kw__Accum: - case tok::kw__Fract: - case tok::kw__Sat: #define GENERIC_IMAGE_TYPE(ImgType, Id) case tok::kw_##ImgType##_t: #include "clang/Basic/OpenCLImageTypes.def" return true; diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp index 67533ccbdf347..acb765559e6a8 100644 --- a/clang/lib/Sema/Sema.cpp +++ b/clang/lib/Sema/Sema.cpp @@ -590,7 +590,11 @@ void Sema::diagnoseZeroToNullptrConversion(CastKind Kind, const Expr *E) { if (Kind != CK_NullToPointer && Kind != CK_NullToMemberPointer) return; - if (E->IgnoreParenImpCasts()->getType()->isNullPtrType()) + + const Expr *EStripped = E->IgnoreParenImpCasts(); + if (EStripped->getType()->isNullPtrType()) + return; + if (isa(EStripped)) return; if (Diags.isIgnored(diag::warn_zero_as_null_pointer_constant, @@ -612,6 +616,8 @@ void Sema::diagnoseZeroToNullptrConversion(CastKind Kind, const Expr *E) { // If it is a macro from system header, and if the macro name is not "NULL", // do not warn. + // Note that uses of "NULL" will be ignored above on systems that define it + // as __null. SourceLocation MaybeMacroLoc = E->getBeginLoc(); if (Diags.getSuppressSystemWarnings() && SourceMgr.isInSystemMacro(MaybeMacroLoc) && diff --git a/clang/lib/Sema/SemaCast.cpp b/clang/lib/Sema/SemaCast.cpp index 98b5879456e21..87e6d1a2198fc 100644 --- a/clang/lib/Sema/SemaCast.cpp +++ b/clang/lib/Sema/SemaCast.cpp @@ -3362,7 +3362,7 @@ ExprResult Sema::BuildCXXFunctionalCastExpr(TypeSourceInfo *CastTypeInfo, assert(LPLoc.isValid() && "List-initialization shouldn't get here."); CastOperation Op(*this, Type, CastExpr); Op.DestRange = CastTypeInfo->getTypeLoc().getSourceRange(); - Op.OpRange = SourceRange(Op.DestRange.getBegin(), CastExpr->getEndLoc()); + Op.OpRange = SourceRange(Op.DestRange.getBegin(), RPLoc); Op.CheckCXXCStyleCast(/*FunctionalCast=*/true, /*ListInit=*/false); if (Op.SrcExpr.isInvalid()) diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index f3c55d059e663..7972919d14201 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -14332,18 +14332,6 @@ static bool AnalyzeBitFieldAssignment(Sema &S, FieldDecl *Bitfield, Expr *Init, S.Diag(WidthExpr->getExprLoc(), diag::note_widen_bitfield) << BitsNeeded << ED << WidthExpr->getSourceRange(); } - } else if (OriginalInit->getType()->isIntegralType(S.Context)) { - IntRange LikelySourceRange = - GetExprRange(S.Context, Init, S.isConstantEvaluatedContext(), - /*Approximate=*/true); - - if (LikelySourceRange.Width > FieldWidth) { - Expr *WidthExpr = Bitfield->getBitWidth(); - S.Diag(InitLoc, diag::warn_bitfield_too_small_for_integral_type) - << Bitfield << FieldWidth << OriginalInit->getType() - << LikelySourceRange.Width; - S.Diag(WidthExpr->getExprLoc(), diag::note_declared_at); - } } return false; @@ -15241,6 +15229,7 @@ static void CheckImplicitConversion(Sema &S, Expr *E, QualType T, if (LikelySourceRange.Width > TargetRange.Width) { // If the source is a constant, use a default-on diagnostic. + // TODO: this should happen for bitfield stores, too. Expr::EvalResult Result; if (E->EvaluateAsInt(Result, S.Context, Expr::SE_AllowSideEffects, S.isConstantEvaluatedContext())) { diff --git a/clang/lib/Sema/SemaCoroutine.cpp b/clang/lib/Sema/SemaCoroutine.cpp index d2b0922a4bb9c..cfaa93fbea4dd 100644 --- a/clang/lib/Sema/SemaCoroutine.cpp +++ b/clang/lib/Sema/SemaCoroutine.cpp @@ -1198,6 +1198,11 @@ void Sema::CheckCompletedCoroutineBody(FunctionDecl *FD, Stmt *&Body) { if (FD->hasAttr()) Diag(FD->getLocation(), diag::warn_always_inline_coroutine); + // The design of coroutines means we cannot allow use of VLAs within one, so + // diagnose if we've seen a VLA in the body of this function. + if (Fn->FirstVLALoc.isValid()) + Diag(Fn->FirstVLALoc, diag::err_vla_in_coroutine_unsupported); + // [stmt.return.coroutine]p1: // A coroutine shall not enclose a return statement ([stmt.return]). if (Fn->FirstReturnLoc.isValid()) { diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp index b363b0db79f16..c4979b51e68f5 100644 --- a/clang/lib/Sema/SemaDecl.cpp +++ b/clang/lib/Sema/SemaDecl.cpp @@ -3922,18 +3922,6 @@ bool Sema::MergeFunctionDecl(FunctionDecl *New, NamedDecl *&OldD, Scope *S, } if (getLangOpts().CPlusPlus) { - // C++1z [over.load]p2 - // Certain function declarations cannot be overloaded: - // -- Function declarations that differ only in the return type, - // the exception specification, or both cannot be overloaded. - - // Check the exception specifications match. This may recompute the type of - // both Old and New if it resolved exception specifications, so grab the - // types again after this. Because this updates the type, we do this before - // any of the other checks below, which may update the "de facto" NewQType - // but do not necessarily update the type of New. - if (CheckEquivalentExceptionSpec(Old, New)) - return true; OldQType = Context.getCanonicalType(Old->getType()); NewQType = Context.getCanonicalType(New->getType()); @@ -4055,6 +4043,19 @@ bool Sema::MergeFunctionDecl(FunctionDecl *New, NamedDecl *&OldD, Scope *S, } } + // C++1z [over.load]p2 + // Certain function declarations cannot be overloaded: + // -- Function declarations that differ only in the return type, + // the exception specification, or both cannot be overloaded. + + // Check the exception specifications match. This may recompute the type of + // both Old and New if it resolved exception specifications, so grab the + // types again after this. Because this updates the type, we do this before + // any of the other checks below, which may update the "de facto" NewQType + // but do not necessarily update the type of New. + if (CheckEquivalentExceptionSpec(Old, New)) + return true; + // C++11 [dcl.attr.noreturn]p1: // The first declaration of a function shall specify the noreturn // attribute if any declaration of that function specifies the noreturn diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp index 5adf058bea56a..fc4e3ccf29a60 100644 --- a/clang/lib/Sema/SemaDeclAttr.cpp +++ b/clang/lib/Sema/SemaDeclAttr.cpp @@ -5916,6 +5916,43 @@ static void handleBuiltinAliasAttr(Sema &S, Decl *D, D->addAttr(::new (S.Context) BuiltinAliasAttr(S.Context, AL, Ident)); } +static void handlePreferredTypeAttr(Sema &S, Decl *D, const ParsedAttr &AL) { + if (!AL.hasParsedType()) { + S.Diag(AL.getLoc(), diag::err_attribute_wrong_number_arguments) << AL << 1; + return; + } + + TypeSourceInfo *ParmTSI = nullptr; + QualType QT = S.GetTypeFromParser(AL.getTypeArg(), &ParmTSI); + assert(ParmTSI && "no type source info for attribute argument"); + S.RequireCompleteType(ParmTSI->getTypeLoc().getBeginLoc(), QT, + diag::err_incomplete_type); + + if (QT->isEnumeralType()) { + auto IsCorrespondingType = [&](QualType LHS, QualType RHS) { + assert(LHS != RHS); + if (LHS->isSignedIntegerType()) + return LHS == S.getASTContext().getCorrespondingSignedType(RHS); + return LHS == S.getASTContext().getCorrespondingUnsignedType(RHS); + }; + QualType BitfieldType = + cast(D)->getType()->getCanonicalTypeUnqualified(); + QualType EnumUnderlyingType = QT->getAs() + ->getDecl() + ->getIntegerType() + ->getCanonicalTypeUnqualified(); + if (EnumUnderlyingType != BitfieldType && + !IsCorrespondingType(EnumUnderlyingType, BitfieldType)) { + S.Diag(ParmTSI->getTypeLoc().getBeginLoc(), + diag::warn_attribute_underlying_type_mismatch) + << EnumUnderlyingType << QT << BitfieldType; + return; + } + } + + D->addAttr(::new (S.Context) PreferredTypeAttr(S.Context, AL, ParmTSI)); +} + //===----------------------------------------------------------------------===// // Checker-specific attribute handlers. //===----------------------------------------------------------------------===// @@ -9636,6 +9673,10 @@ ProcessDeclAttribute(Sema &S, Scope *scope, Decl *D, const ParsedAttr &AL, handleBuiltinAliasAttr(S, D, AL); break; + case ParsedAttr::AT_PreferredType: + handlePreferredTypeAttr(S, D, AL); + break; + case ParsedAttr::AT_UsingIfExists: handleSimpleAttribute(S, D, AL); break; diff --git a/clang/lib/Sema/SemaDeclCXX.cpp b/clang/lib/Sema/SemaDeclCXX.cpp index 0193e476b3a78..beb7e5b177c6e 100644 --- a/clang/lib/Sema/SemaDeclCXX.cpp +++ b/clang/lib/Sema/SemaDeclCXX.cpp @@ -2457,7 +2457,8 @@ static bool CheckConstexprFunctionBody(Sema &SemaRef, const FunctionDecl *Dcl, !Expr::isPotentialConstantExpr(Dcl, Diags)) { SemaRef.Diag(Dcl->getLocation(), diag::ext_constexpr_function_never_constant_expr) - << isa(Dcl) << Dcl->isConsteval(); + << isa(Dcl) << Dcl->isConsteval() + << Dcl->getNameInfo().getSourceRange(); for (size_t I = 0, N = Diags.size(); I != N; ++I) SemaRef.Diag(Diags[I].first, Diags[I].second); // Don't return false here: we allow this for compatibility in @@ -7747,6 +7748,24 @@ bool Sema::CheckExplicitlyDefaultedSpecialMember(CXXMethodDecl *MD, HadError = true; } } + // [C++23][dcl.fct.def.default]/p2.2 + // if F2 has an implicit object parameter of type “reference to C”, + // F1 may be an explicit object member function whose explicit object + // parameter is of (possibly different) type “reference to C”, + // in which case the type of F1 would differ from the type of F2 + // in that the type of F1 has an additional parameter; + if (!Context.hasSameType( + ThisType.getNonReferenceType().getUnqualifiedType(), + Context.getRecordType(RD))) { + if (DeleteOnTypeMismatch) + ShouldDeleteForTypeMismatch = true; + else { + Diag(MD->getLocation(), + diag::err_defaulted_special_member_explicit_object_mismatch) + << (CSM == CXXMoveAssignment) << RD << MD->getSourceRange(); + HadError = true; + } + } } // Check for parameter type matching. @@ -11352,12 +11371,14 @@ void Sema::CheckExplicitObjectMemberFunction(Declarator &D, Diag(ExplicitObjectParam->getBeginLoc(), diag::err_explicit_object_parameter_nonmember) << D.getSourceRange() << /*static=*/0 << IsLambda; + D.setInvalidType(); } if (D.getDeclSpec().isVirtualSpecified()) { Diag(ExplicitObjectParam->getBeginLoc(), diag::err_explicit_object_parameter_nonmember) << D.getSourceRange() << /*virtual=*/1 << IsLambda; + D.setInvalidType(); } if (IsLambda && FTI.hasMutableQualifier()) { @@ -11373,16 +11394,19 @@ void Sema::CheckExplicitObjectMemberFunction(Declarator &D, Diag(ExplicitObjectParam->getLocation(), diag::err_explicit_object_parameter_nonmember) << D.getSourceRange() << /*non-member=*/2 << IsLambda; + D.setInvalidType(); return; } // CWG2674: constructors and destructors cannot have explicit parameters. if (Name.getNameKind() == DeclarationName::CXXConstructorName || - Name.getNameKind() == DeclarationName::CXXDestructorName) + Name.getNameKind() == DeclarationName::CXXDestructorName) { Diag(ExplicitObjectParam->getBeginLoc(), diag::err_explicit_object_parameter_constructor) << (Name.getNameKind() == DeclarationName::CXXDestructorName) << D.getSourceRange(); + D.setInvalidType(); + } } namespace { diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index ed0b150d52746..c2772bfb71c77 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -12143,8 +12143,7 @@ static void DiagnoseBadShiftValues(Sema& S, ExprResult &LHS, ExprResult &RHS, auto FXSema = S.Context.getFixedPointSemantics(LHSExprType); LeftSize = FXSema.getWidth() - (unsigned)FXSema.hasUnsignedPadding(); } - llvm::APInt LeftBits(Right.getBitWidth(), LeftSize); - if (Right.uge(LeftBits)) { + if (Right.uge(LeftSize)) { S.DiagRuntimeBehavior(Loc, RHS.get(), S.PDiag(diag::warn_shift_gt_typewidth) << RHS.get()->getSourceRange()); @@ -12186,7 +12185,7 @@ static void DiagnoseBadShiftValues(Sema& S, ExprResult &LHS, ExprResult &RHS, llvm::APInt ResultBits = static_cast(Right) + Left.getSignificantBits(); - if (LeftBits.uge(ResultBits)) + if (ResultBits.ule(LeftSize)) return; llvm::APSInt Result = Left.extend(ResultBits.getLimitedValue()); Result = Result.shl(Right); @@ -12200,7 +12199,7 @@ static void DiagnoseBadShiftValues(Sema& S, ExprResult &LHS, ExprResult &RHS, // bugs -- if the result is cast back to an unsigned type, it will have the // expected value. Thus we place this behind a different warning that can be // turned off separately if needed. - if (LeftBits == ResultBits - 1) { + if (ResultBits - 1 == LeftSize) { S.Diag(Loc, diag::warn_shift_result_sets_sign_bit) << HexResult << LHSType << LHS.get()->getSourceRange() << RHS.get()->getSourceRange(); @@ -18303,7 +18302,7 @@ void Sema::CheckUnusedVolatileAssignment(Expr *E) { if (auto *BO = dyn_cast(E->IgnoreParenImpCasts())) { if (BO->getOpcode() == BO_Assign) { auto &LHSs = ExprEvalContexts.back().VolatileAssignmentLHSs; - llvm::erase_value(LHSs, BO->getLHS()); + llvm::erase(LHSs, BO->getLHS()); } } } diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp index 1153049496d12..6344c9102330a 100644 --- a/clang/lib/Sema/SemaExprCXX.cpp +++ b/clang/lib/Sema/SemaExprCXX.cpp @@ -1333,6 +1333,7 @@ bool Sema::CheckCXXThisCapture(SourceLocation Loc, const bool Explicit, if (LSI && isGenericLambdaCallOperatorSpecialization(LSI->CallOperator)) { // This context can't implicitly capture 'this'; fail out. if (BuildAndDiagnose) { + LSI->CallOperator->setInvalidDecl(); Diag(Loc, diag::err_this_capture) << (Explicit && idx == MaxFunctionScopesIndex); if (!Explicit) @@ -1354,10 +1355,11 @@ bool Sema::CheckCXXThisCapture(SourceLocation Loc, const bool Explicit, continue; } // This context can't implicitly capture 'this'; fail out. - if (BuildAndDiagnose) + if (BuildAndDiagnose) { + LSI->CallOperator->setInvalidDecl(); Diag(Loc, diag::err_this_capture) << (Explicit && idx == MaxFunctionScopesIndex); - + } if (!Explicit) buildLambdaThisCaptureFixit(*this, LSI); return true; diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp index eb755e2a0c454..75f9e152dca92 100644 --- a/clang/lib/Sema/SemaOpenMP.cpp +++ b/clang/lib/Sema/SemaOpenMP.cpp @@ -18049,7 +18049,7 @@ OMPClause *Sema::ActOnOpenMPVarListClause(OpenMPClauseKind Kind, Res = ActOnOpenMPLinearClause( VarList, Data.DepModOrTailExpr, StartLoc, LParenLoc, static_cast(ExtraModifier), ExtraModifierLoc, - ColonLoc, EndLoc); + ColonLoc, Data.StepModifierLoc, EndLoc); break; case OMPC_aligned: Res = ActOnOpenMPAlignedClause(VarList, Data.DepModOrTailExpr, StartLoc, @@ -20134,7 +20134,7 @@ OMPClause *Sema::ActOnOpenMPInReductionClause( bool Sema::CheckOpenMPLinearModifier(OpenMPLinearClauseKind LinKind, SourceLocation LinLoc) { if ((!LangOpts.CPlusPlus && LinKind != OMPC_LINEAR_val) || - LinKind == OMPC_LINEAR_unknown) { + LinKind == OMPC_LINEAR_unknown || LinKind == OMPC_LINEAR_step) { Diag(LinLoc, diag::err_omp_wrong_linear_modifier) << LangOpts.CPlusPlus; return true; } @@ -20186,12 +20186,19 @@ bool Sema::CheckOpenMPLinearDecl(const ValueDecl *D, SourceLocation ELoc, OMPClause *Sema::ActOnOpenMPLinearClause( ArrayRef VarList, Expr *Step, SourceLocation StartLoc, SourceLocation LParenLoc, OpenMPLinearClauseKind LinKind, - SourceLocation LinLoc, SourceLocation ColonLoc, SourceLocation EndLoc) { + SourceLocation LinLoc, SourceLocation ColonLoc, + SourceLocation StepModifierLoc, SourceLocation EndLoc) { SmallVector Vars; SmallVector Privates; SmallVector Inits; SmallVector ExprCaptures; SmallVector ExprPostUpdates; + // OpenMP 5.2 [Section 5.4.6, linear clause] + // step-simple-modifier is exclusive, can't be used with 'val', 'uval', or + // 'ref' + if (LinLoc.isValid() && StepModifierLoc.isInvalid() && Step && + getLangOpts().OpenMP >= 52) + Diag(Step->getBeginLoc(), diag::err_omp_step_simple_modifier_exclusive); if (CheckOpenMPLinearModifier(LinKind, LinLoc)) LinKind = OMPC_LINEAR_val; for (Expr *RefExpr : VarList) { @@ -20311,8 +20318,8 @@ OMPClause *Sema::ActOnOpenMPLinearClause( } return OMPLinearClause::Create(Context, StartLoc, LParenLoc, LinKind, LinLoc, - ColonLoc, EndLoc, Vars, Privates, Inits, - StepExpr, CalcStepExpr, + ColonLoc, StepModifierLoc, EndLoc, Vars, + Privates, Inits, StepExpr, CalcStepExpr, buildPreInits(Context, ExprCaptures), buildPostUpdate(*this, ExprPostUpdates)); } diff --git a/clang/lib/Sema/SemaOverload.cpp b/clang/lib/Sema/SemaOverload.cpp index ce78994e65538..db386fef0661c 100644 --- a/clang/lib/Sema/SemaOverload.cpp +++ b/clang/lib/Sema/SemaOverload.cpp @@ -38,8 +38,10 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallString.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/Support/Casting.h" #include +#include #include #include @@ -960,18 +962,13 @@ static bool shouldAddReversedEqEq(Sema &S, SourceLocation OpLoc, return true; } // Otherwise the search scope is the namespace scope of which F is a member. - LookupResult NonMembers(S, NotEqOp, OpLoc, - Sema::LookupNameKind::LookupOperatorName); - S.LookupName(NonMembers, - S.getScopeForContext(EqFD->getEnclosingNamespaceContext())); - NonMembers.suppressAccessDiagnostics(); - for (NamedDecl *Op : NonMembers) { - auto *FD = Op->getAsFunction(); - if(auto* UD = dyn_cast(Op)) - FD = UD->getUnderlyingDecl()->getAsFunction(); - if (FunctionsCorrespond(S.Context, EqFD, FD) && - declaresSameEntity(cast(EqFD->getDeclContext()), - cast(Op->getDeclContext()))) + for (NamedDecl *Op : EqFD->getEnclosingNamespaceContext()->lookup(NotEqOp)) { + auto *NotEqFD = Op->getAsFunction(); + if (auto *UD = dyn_cast(Op)) + NotEqFD = UD->getUnderlyingDecl()->getAsFunction(); + if (FunctionsCorrespond(S.Context, EqFD, NotEqFD) && S.isVisible(NotEqFD) && + declaresSameEntity(cast(EqFD->getEnclosingNamespaceContext()), + cast(Op->getLexicalDeclContext()))) return false; } return true; @@ -12009,6 +12006,7 @@ static unsigned RankDeductionFailure(const DeductionFailureInfo &DFI) { } namespace { + struct CompareOverloadCandidatesForDisplay { Sema &S; SourceLocation Loc; @@ -12046,13 +12044,9 @@ struct CompareOverloadCandidatesForDisplay { if (L->Viable) { if (!R->Viable) return true; - // TODO: introduce a tri-valued comparison for overload - // candidates. Would be more worthwhile if we had a sort - // that could exploit it. - if (isBetterOverloadCandidate(S, *L, *R, SourceLocation(), CSK)) - return true; - if (isBetterOverloadCandidate(S, *R, *L, SourceLocation(), CSK)) - return false; + if (int Ord = CompareConversions(*L, *R)) + return Ord < 0; + // Use other tie breakers. } else if (R->Viable) return false; @@ -12104,30 +12098,8 @@ struct CompareOverloadCandidatesForDisplay { } // If there's any ordering between the defined conversions... - // FIXME: this might not be transitive. - assert(L->Conversions.size() == R->Conversions.size()); - - int leftBetter = 0; - unsigned I = (L->IgnoreObjectArgument || R->IgnoreObjectArgument); - for (unsigned E = L->Conversions.size(); I != E; ++I) { - switch (CompareImplicitConversionSequences(S, Loc, - L->Conversions[I], - R->Conversions[I])) { - case ImplicitConversionSequence::Better: - leftBetter++; - break; - - case ImplicitConversionSequence::Worse: - leftBetter--; - break; - - case ImplicitConversionSequence::Indistinguishable: - break; - } - } - if (leftBetter > 0) return true; - if (leftBetter < 0) return false; - + if (int Ord = CompareConversions(*L, *R)) + return Ord < 0; } else if (RFailureKind == ovl_fail_bad_conversion) return false; @@ -12149,10 +12121,66 @@ struct CompareOverloadCandidatesForDisplay { SourceLocation RLoc = GetLocationForCandidate(R); // Put candidates without locations (e.g. builtins) at the end. - if (LLoc.isInvalid()) return false; - if (RLoc.isInvalid()) return true; + if (LLoc.isValid() && RLoc.isValid()) + return S.SourceMgr.isBeforeInTranslationUnit(LLoc, RLoc); + if (LLoc.isValid() && !RLoc.isValid()) + return true; + if (RLoc.isValid() && !LLoc.isValid()) + return false; + assert(!LLoc.isValid() && !RLoc.isValid()); + // For builtins and other functions without locations, fallback to the order + // in which they were added into the candidate set. + return L < R; + } - return S.SourceMgr.isBeforeInTranslationUnit(LLoc, RLoc); +private: + struct ConversionSignals { + unsigned KindRank = 0; + ImplicitConversionRank Rank = ICR_Exact_Match; + + static ConversionSignals ForSequence(ImplicitConversionSequence &Seq) { + ConversionSignals Sig; + Sig.KindRank = Seq.getKindRank(); + if (Seq.isStandard()) + Sig.Rank = Seq.Standard.getRank(); + else if (Seq.isUserDefined()) + Sig.Rank = Seq.UserDefined.After.getRank(); + // We intend StaticObjectArgumentConversion to compare the same as + // StandardConversion with ICR_ExactMatch rank. + return Sig; + } + + static ConversionSignals ForObjectArgument() { + // We intend StaticObjectArgumentConversion to compare the same as + // StandardConversion with ICR_ExactMatch rank. Default give us that. + return {}; + } + }; + + // Returns -1 if conversions in L are considered better. + // 0 if they are considered indistinguishable. + // 1 if conversions in R are better. + int CompareConversions(const OverloadCandidate &L, + const OverloadCandidate &R) { + // We cannot use `isBetterOverloadCandidate` because it is defined + // according to the C++ standard and provides a partial order, but we need + // a total order as this function is used in sort. + assert(L.Conversions.size() == R.Conversions.size()); + for (unsigned I = 0, N = L.Conversions.size(); I != N; ++I) { + auto LS = L.IgnoreObjectArgument && I == 0 + ? ConversionSignals::ForObjectArgument() + : ConversionSignals::ForSequence(L.Conversions[I]); + auto RS = R.IgnoreObjectArgument + ? ConversionSignals::ForObjectArgument() + : ConversionSignals::ForSequence(R.Conversions[I]); + if (std::tie(LS.KindRank, LS.Rank) != std::tie(RS.KindRank, RS.Rank)) + return std::tie(LS.KindRank, LS.Rank) < std::tie(RS.KindRank, RS.Rank) + ? -1 + : 1; + } + // FIXME: find a way to compare templates for being more or less + // specialized that provides a strict weak ordering. + return 0; } }; } diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp b/clang/lib/Sema/SemaRISCVVectorLookup.cpp index ae584dc687199..acdf3260007bc 100644 --- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp +++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp @@ -205,6 +205,8 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics( static const std::pair FeatureCheckList[] = { {"64bit", RVV_REQ_RV64}, {"xsfvcp", RVV_REQ_Xsfvcp}, + {"xsfvqmaccdod", RVV_REQ_Xsfvqmaccdod}, + {"xsfvqmaccqoq", RVV_REQ_Xsfvqmaccqoq}, {"experimental-zvbb", RVV_REQ_Zvbb}, {"experimental-zvbc", RVV_REQ_Zvbc}, {"experimental-zvkb", RVV_REQ_Zvkb}, diff --git a/clang/lib/Sema/SemaTemplate.cpp b/clang/lib/Sema/SemaTemplate.cpp index f0197f7c102a8..c2477ec0063e4 100644 --- a/clang/lib/Sema/SemaTemplate.cpp +++ b/clang/lib/Sema/SemaTemplate.cpp @@ -2253,6 +2253,7 @@ struct ConvertConstructorToDeductionGuideTransform { Sema &SemaRef; ClassTemplateDecl *Template; + ClassTemplateDecl *NestedPattern = nullptr; DeclContext *DC = Template->getDeclContext(); CXXRecordDecl *Primary = Template->getTemplatedDecl(); @@ -2332,6 +2333,9 @@ struct ConvertConstructorToDeductionGuideTransform { Args.addOuterRetainedLevel(); } + if (NestedPattern) + Args.addOuterRetainedLevels(NestedPattern->getTemplateDepth()); + FunctionProtoTypeLoc FPTL = CD->getTypeSourceInfo()->getTypeLoc() .getAsAdjusted(); assert(FPTL && "no prototype for constructor declaration"); @@ -2441,10 +2445,17 @@ struct ConvertConstructorToDeductionGuideTransform { SmallVector ParamTypes; const FunctionProtoType *T = TL.getTypePtr(); + MultiLevelTemplateArgumentList OuterInstantiationArgs; + if (NestedPattern) + OuterInstantiationArgs = SemaRef.getTemplateInstantiationArgs(Template); + // -- The types of the function parameters are those of the constructor. for (auto *OldParam : TL.getParams()) { ParmVarDecl *NewParam = transformFunctionTypeParam(OldParam, Args, MaterializedTypedefs); + if (NestedPattern && NewParam) + NewParam = transformFunctionTypeParam(NewParam, OuterInstantiationArgs, + MaterializedTypedefs); if (!NewParam) return QualType(); ParamTypes.push_back(NewParam->getType()); @@ -2650,13 +2661,24 @@ void Sema::DeclareImplicitDeductionGuides(TemplateDecl *Template, if (BuildingDeductionGuides.isInvalid()) return; + // If the template is nested, then we need to use the original + // pattern to iterate over the constructors. + ClassTemplateDecl *Pattern = Transform.Template; + while (Pattern->getInstantiatedFromMemberTemplate()) { + if (Pattern->isMemberSpecialization()) + break; + Pattern = Pattern->getInstantiatedFromMemberTemplate(); + Transform.NestedPattern = Pattern; + } + // Convert declared constructors into deduction guide templates. // FIXME: Skip constructors for which deduction must necessarily fail (those // for which some class template parameter without a default argument never // appears in a deduced context). + ContextRAII SavedContext(*this, Pattern->getTemplatedDecl()); llvm::SmallPtrSet ProcessedCtors; bool AddedAny = false; - for (NamedDecl *D : LookupConstructors(Transform.Primary)) { + for (NamedDecl *D : LookupConstructors(Pattern->getTemplatedDecl())) { D = D->getUnderlyingDecl(); if (D->isInvalidDecl() || D->isImplicit()) continue; @@ -2702,6 +2724,8 @@ void Sema::DeclareImplicitDeductionGuides(TemplateDecl *Template, Transform.buildSimpleDeductionGuide(Transform.DeducedType)) ->getTemplatedDecl()) ->setDeductionCandidateKind(DeductionCandidate::Copy); + + SavedContext.pop(); } /// Diagnose the presence of a default template argument on a diff --git a/clang/lib/Sema/SemaTemplateDeduction.cpp b/clang/lib/Sema/SemaTemplateDeduction.cpp index 8f115f2177846..0b3f0247ea3be 100644 --- a/clang/lib/Sema/SemaTemplateDeduction.cpp +++ b/clang/lib/Sema/SemaTemplateDeduction.cpp @@ -3367,7 +3367,14 @@ Sema::TemplateDeductionResult Sema::SubstituteExplicitTemplateArguments( SmallVector ExceptionStorage; if (getLangOpts().CPlusPlus17 && SubstExceptionSpec(Function->getLocation(), EPI.ExceptionSpec, - ExceptionStorage, MLTAL)) + ExceptionStorage, + getTemplateInstantiationArgs( + FunctionTemplate, nullptr, /*Final=*/true, + /*Innermost=*/SugaredExplicitArgumentList, + /*RelativeToPrimary=*/false, + /*Pattern=*/nullptr, + /*ForConstraintInstantiation=*/false, + /*SkipForSpecialization=*/true))) return TDK_SubstitutionFailure; *FunctionType = BuildFunctionType(ResultType, ParamTypes, diff --git a/clang/lib/Sema/SemaTemplateInstantiate.cpp b/clang/lib/Sema/SemaTemplateInstantiate.cpp index effc97a033c5e..e09897318ba98 100644 --- a/clang/lib/Sema/SemaTemplateInstantiate.cpp +++ b/clang/lib/Sema/SemaTemplateInstantiate.cpp @@ -1335,6 +1335,11 @@ namespace { /// declaration. NamedDecl *TransformFirstQualifierInScope(NamedDecl *D, SourceLocation Loc); + bool TransformExceptionSpec(SourceLocation Loc, + FunctionProtoType::ExceptionSpecInfo &ESI, + SmallVectorImpl &Exceptions, + bool &Changed); + /// Rebuild the exception declaration and register the declaration /// as an instantiated local. VarDecl *RebuildExceptionDecl(VarDecl *ExceptionDecl, @@ -1617,6 +1622,18 @@ Decl *TemplateInstantiator::TransformDefinition(SourceLocation Loc, Decl *D) { return Inst; } +bool TemplateInstantiator::TransformExceptionSpec( + SourceLocation Loc, FunctionProtoType::ExceptionSpecInfo &ESI, + SmallVectorImpl &Exceptions, bool &Changed) { + if (ESI.Type == EST_Uninstantiated) { + ESI.NoexceptExpr = cast(ESI.SourceTemplate->getType()) + ->getNoexceptExpr(); + ESI.Type = EST_DependentNoexcept; + Changed = true; + } + return inherited::TransformExceptionSpec(Loc, ESI, Exceptions, Changed); +} + NamedDecl * TemplateInstantiator::TransformFirstQualifierInScope(NamedDecl *D, SourceLocation Loc) { @@ -2684,8 +2701,6 @@ bool Sema::SubstExceptionSpec(SourceLocation Loc, FunctionProtoType::ExceptionSpecInfo &ESI, SmallVectorImpl &ExceptionStorage, const MultiLevelTemplateArgumentList &Args) { - assert(ESI.Type != EST_Uninstantiated); - bool Changed = false; TemplateInstantiator Instantiator(*this, Args, Loc, DeclarationName()); return Instantiator.TransformExceptionSpec(Loc, ESI, ExceptionStorage, diff --git a/clang/lib/Sema/SemaType.cpp b/clang/lib/Sema/SemaType.cpp index b1bdf670f1788..dea77fae4cadb 100644 --- a/clang/lib/Sema/SemaType.cpp +++ b/clang/lib/Sema/SemaType.cpp @@ -2582,6 +2582,27 @@ QualType Sema::BuildArrayType(QualType T, ArrayType::ArraySizeModifier ASM, return QualType(); } + auto IsStaticAssertLike = [](const Expr *ArraySize, ASTContext &Context) { + if (!ArraySize) + return false; + + // If the array size expression is a conditional expression whose branches + // are both integer constant expressions, one negative and one positive, + // then it's assumed to be like an old-style static assertion. e.g., + // int old_style_assert[expr ? 1 : -1]; + // We will accept any integer constant expressions instead of assuming the + // values 1 and -1 are always used. + if (const auto *CondExpr = dyn_cast_if_present( + ArraySize->IgnoreParenImpCasts())) { + std::optional LHS = + CondExpr->getLHS()->getIntegerConstantExpr(Context); + std::optional RHS = + CondExpr->getRHS()->getIntegerConstantExpr(Context); + return LHS && RHS && LHS->isNegative() != RHS->isNegative(); + } + return false; + }; + // VLAs always produce at least a -Wvla diagnostic, sometimes an error. unsigned VLADiag; bool VLAIsError; @@ -2598,6 +2619,15 @@ QualType Sema::BuildArrayType(QualType T, ArrayType::ArraySizeModifier ASM, } else if (getLangOpts().OpenMP && isInOpenMPTaskUntiedContext()) { VLADiag = diag::err_openmp_vla_in_task_untied; VLAIsError = true; + } else if (getLangOpts().CPlusPlus) { + if (getLangOpts().CPlusPlus11 && IsStaticAssertLike(ArraySize, Context)) + VLADiag = getLangOpts().GNUMode + ? diag::ext_vla_cxx_in_gnu_mode_static_assert + : diag::ext_vla_cxx_static_assert; + else + VLADiag = getLangOpts().GNUMode ? diag::ext_vla_cxx_in_gnu_mode + : diag::ext_vla_cxx; + VLAIsError = false; } else { VLADiag = diag::ext_vla; VLAIsError = false; @@ -2676,12 +2706,18 @@ QualType Sema::BuildArrayType(QualType T, ArrayType::ArraySizeModifier ASM, } } - if (T->isVariableArrayType() && !Context.getTargetInfo().isVLASupported()) { - // CUDA device code and some other targets don't support VLAs. - bool IsCUDADevice = (getLangOpts().CUDA && getLangOpts().CUDAIsDevice); - targetDiag(Loc, - IsCUDADevice ? diag::err_cuda_vla : diag::err_vla_unsupported) - << (IsCUDADevice ? CurrentCUDATarget() : 0); + if (T->isVariableArrayType()) { + if (!Context.getTargetInfo().isVLASupported()) { + // CUDA device code and some other targets don't support VLAs. + bool IsCUDADevice = (getLangOpts().CUDA && getLangOpts().CUDAIsDevice); + targetDiag(Loc, + IsCUDADevice ? diag::err_cuda_vla : diag::err_vla_unsupported) + << (IsCUDADevice ? CurrentCUDATarget() : 0); + } else if (sema::FunctionScopeInfo *FSI = getCurFunction()) { + // VLAs are supported on this target, but we may need to do delayed + // checking that the VLA is not being used within a coroutine. + FSI->setHasVLA(Loc); + } } // If this is not C99, diagnose array size modifiers on non-VLAs. diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h index 8fafdd4f5caa1..17ebfe14cecad 100644 --- a/clang/lib/Sema/TreeTransform.h +++ b/clang/lib/Sema/TreeTransform.h @@ -1908,16 +1908,14 @@ class TreeTransform { /// /// By default, performs semantic analysis to build the new OpenMP clause. /// Subclasses may override this routine to provide different behavior. - OMPClause *RebuildOMPLinearClause(ArrayRef VarList, Expr *Step, - SourceLocation StartLoc, - SourceLocation LParenLoc, - OpenMPLinearClauseKind Modifier, - SourceLocation ModifierLoc, - SourceLocation ColonLoc, - SourceLocation EndLoc) { + OMPClause *RebuildOMPLinearClause( + ArrayRef VarList, Expr *Step, SourceLocation StartLoc, + SourceLocation LParenLoc, OpenMPLinearClauseKind Modifier, + SourceLocation ModifierLoc, SourceLocation ColonLoc, + SourceLocation StepModifierLoc, SourceLocation EndLoc) { return getSema().ActOnOpenMPLinearClause(VarList, Step, StartLoc, LParenLoc, Modifier, ModifierLoc, ColonLoc, - EndLoc); + StepModifierLoc, EndLoc); } /// Build a new OpenMP 'aligned' clause. @@ -10287,7 +10285,8 @@ TreeTransform::TransformOMPLinearClause(OMPLinearClause *C) { return nullptr; return getDerived().RebuildOMPLinearClause( Vars, Step.get(), C->getBeginLoc(), C->getLParenLoc(), C->getModifier(), - C->getModifierLoc(), C->getColonLoc(), C->getEndLoc()); + C->getModifierLoc(), C->getColonLoc(), C->getStepModifierLoc(), + C->getEndLoc()); } template @@ -11783,8 +11782,6 @@ TreeTransform::TransformDesignatedInitExpr(DesignatedInitExpr *E) { bool ExprChanged = false; for (const DesignatedInitExpr::Designator &D : E->designators()) { if (D.isFieldDesignator()) { - Desig.AddDesignator(Designator::CreateFieldDesignator( - D.getFieldName(), D.getDotLoc(), D.getFieldLoc())); if (D.getFieldDecl()) { FieldDecl *Field = cast_or_null( getDerived().TransformDecl(D.getFieldLoc(), D.getFieldDecl())); @@ -11792,12 +11789,16 @@ TreeTransform::TransformDesignatedInitExpr(DesignatedInitExpr *E) { // Rebuild the expression when the transformed FieldDecl is // different to the already assigned FieldDecl. ExprChanged = true; + if (Field->isAnonymousStructOrUnion()) + continue; } else { // Ensure that the designator expression is rebuilt when there isn't // a resolved FieldDecl in the designator as we don't want to assign // a FieldDecl to a pattern designator that will be instantiated again. ExprChanged = true; } + Desig.AddDesignator(Designator::CreateFieldDesignator( + D.getFieldName(), D.getDotLoc(), D.getFieldLoc())); continue; } diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp index cce403d7c6c44..42b48d230af7a 100644 --- a/clang/lib/Serialization/ASTReader.cpp +++ b/clang/lib/Serialization/ASTReader.cpp @@ -4175,7 +4175,7 @@ ASTReader::ReadModuleMapFileBlock(RecordData &Record, ModuleFile &F, return OutOfDate; } - llvm::SmallPtrSet AdditionalStoredMaps; + ModuleMap::AdditionalModMapsSet AdditionalStoredMaps; for (unsigned I = 0, N = Record[Idx++]; I < N; ++I) { // FIXME: we should use input files rather than storing names. std::string Filename = ReadPath(F, Record, Idx); @@ -10115,8 +10115,7 @@ void ASTReader::pushExternalDeclIntoScope(NamedDecl *D, DeclarationName Name) { // Adding the decl to IdResolver may have failed because it was already in // (even though it was not added in scope). If it is already in, make sure // it gets in the scope as well. - if (std::find(SemaObj->IdResolver.begin(Name), - SemaObj->IdResolver.end(), D) != SemaObj->IdResolver.end()) + if (llvm::is_contained(SemaObj->IdResolver.decls(Name), D)) SemaObj->TUScope->AddDecl(D); } } diff --git a/clang/lib/Serialization/ASTWriterDecl.cpp b/clang/lib/Serialization/ASTWriterDecl.cpp index 8a2ea7c7624ce..b3364113abf15 100644 --- a/clang/lib/Serialization/ASTWriterDecl.cpp +++ b/clang/lib/Serialization/ASTWriterDecl.cpp @@ -431,7 +431,7 @@ void ASTDeclWriter::VisitTypeAliasDecl(TypeAliasDecl *D) { } void ASTDeclWriter::VisitTagDecl(TagDecl *D) { - static_assert(DeclContext::NumTagDeclBits == 10, + static_assert(DeclContext::NumTagDeclBits == 23, "You need to update the serializer after you change the " "TagDeclBits"); @@ -459,7 +459,7 @@ void ASTDeclWriter::VisitTagDecl(TagDecl *D) { } void ASTDeclWriter::VisitEnumDecl(EnumDecl *D) { - static_assert(DeclContext::NumEnumDeclBits == 20, + static_assert(DeclContext::NumEnumDeclBits == 43, "You need to update the serializer after you change the " "EnumDeclBits"); @@ -506,7 +506,7 @@ void ASTDeclWriter::VisitEnumDecl(EnumDecl *D) { } void ASTDeclWriter::VisitRecordDecl(RecordDecl *D) { - static_assert(DeclContext::NumRecordDeclBits == 41, + static_assert(DeclContext::NumRecordDeclBits == 64, "You need to update the serializer after you change the " "RecordDeclBits"); @@ -578,7 +578,7 @@ void ASTDeclWriter::VisitDeclaratorDecl(DeclaratorDecl *D) { } void ASTDeclWriter::VisitFunctionDecl(FunctionDecl *D) { - static_assert(DeclContext::NumFunctionDeclBits == 31, + static_assert(DeclContext::NumFunctionDeclBits == 44, "You need to update the serializer after you change the " "FunctionDeclBits"); @@ -726,7 +726,7 @@ void ASTDeclWriter::VisitCXXDeductionGuideDecl(CXXDeductionGuideDecl *D) { } void ASTDeclWriter::VisitObjCMethodDecl(ObjCMethodDecl *D) { - static_assert(DeclContext::NumObjCMethodDeclBits == 24, + static_assert(DeclContext::NumObjCMethodDeclBits == 37, "You need to update the serializer after you change the " "ObjCMethodDeclBits"); @@ -788,7 +788,7 @@ void ASTDeclWriter::VisitObjCTypeParamDecl(ObjCTypeParamDecl *D) { } void ASTDeclWriter::VisitObjCContainerDecl(ObjCContainerDecl *D) { - static_assert(DeclContext::NumObjCContainerDeclBits == 51, + static_assert(DeclContext::NumObjCContainerDeclBits == 64, "You need to update the serializer after you change the " "ObjCContainerDeclBits"); @@ -1268,7 +1268,7 @@ void ASTDeclWriter::VisitCapturedDecl(CapturedDecl *CD) { } void ASTDeclWriter::VisitLinkageSpecDecl(LinkageSpecDecl *D) { - static_assert(DeclContext::NumLinkageSpecDeclBits == 4, + static_assert(DeclContext::NumLinkageSpecDeclBits == 17, "You need to update the serializer after you change the" "LinkageSpecDeclBits"); @@ -1479,7 +1479,7 @@ void ASTDeclWriter::VisitCXXMethodDecl(CXXMethodDecl *D) { } void ASTDeclWriter::VisitCXXConstructorDecl(CXXConstructorDecl *D) { - static_assert(DeclContext::NumCXXConstructorDeclBits == 20, + static_assert(DeclContext::NumCXXConstructorDeclBits == 64, "You need to update the serializer after you change the " "CXXConstructorDeclBits"); @@ -1960,7 +1960,7 @@ void ASTDeclWriter::VisitOMPRequiresDecl(OMPRequiresDecl *D) { } void ASTDeclWriter::VisitOMPDeclareReductionDecl(OMPDeclareReductionDecl *D) { - static_assert(DeclContext::NumOMPDeclareReductionDeclBits == 2, + static_assert(DeclContext::NumOMPDeclareReductionDeclBits == 15, "You need to update the serializer after you change the " "NumOMPDeclareReductionDeclBits"); diff --git a/clang/lib/StaticAnalyzer/Checkers/ArrayBoundCheckerV2.cpp b/clang/lib/StaticAnalyzer/Checkers/ArrayBoundCheckerV2.cpp index db4a2fcea9b2c..e80a06e385875 100644 --- a/clang/lib/StaticAnalyzer/Checkers/ArrayBoundCheckerV2.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/ArrayBoundCheckerV2.cpp @@ -32,15 +32,13 @@ using namespace taint; namespace { class ArrayBoundCheckerV2 : public Checker { - mutable std::unique_ptr BT; - mutable std::unique_ptr TaintBT; + BugType BT{this, "Out-of-bound access"}; + BugType TaintBT{this, "Out-of-bound access", categories::TaintedData}; - enum OOB_Kind { OOB_Precedes, OOB_Excedes }; + enum OOB_Kind { OOB_Precedes, OOB_Exceeds, OOB_Taint }; - void reportOOB(CheckerContext &C, ProgramStateRef errorState, - OOB_Kind kind) const; - void reportTaintOOB(CheckerContext &C, ProgramStateRef errorState, - SVal TaintedSVal) const; + void reportOOB(CheckerContext &C, ProgramStateRef ErrorState, OOB_Kind Kind, + SVal TaintedSVal = UnknownVal()) const; static bool isFromCtypeMacro(const Stmt *S, ASTContext &AC); @@ -48,26 +46,62 @@ class ArrayBoundCheckerV2 : void checkLocation(SVal l, bool isLoad, const Stmt *S, CheckerContext &C) const; }; +} // anonymous namespace -// FIXME: Eventually replace RegionRawOffset with this class. -class RegionRawOffsetV2 { -private: - const SubRegion *baseRegion; - NonLoc byteOffset; - -public: - RegionRawOffsetV2(const SubRegion *base, NonLoc offset) - : baseRegion(base), byteOffset(offset) { assert(base); } +/// For a given Location that can be represented as a symbolic expression +/// Arr[Idx] (or perhaps Arr[Idx1][Idx2] etc.), return the parent memory block +/// Arr and the distance of Location from the beginning of Arr (expressed in a +/// NonLoc that specifies the number of CharUnits). Returns nullopt when these +/// cannot be determined. +std::optional> +computeOffset(ProgramStateRef State, SValBuilder &SVB, SVal Location) { + QualType T = SVB.getArrayIndexType(); + auto EvalBinOp = [&SVB, State, T](BinaryOperatorKind Op, NonLoc L, NonLoc R) { + // We will use this utility to add and multiply values. + return SVB.evalBinOpNN(State, Op, L, R, T).getAs(); + }; - NonLoc getByteOffset() const { return byteOffset; } - const SubRegion *getRegion() const { return baseRegion; } + const SubRegion *OwnerRegion = nullptr; + std::optional Offset = SVB.makeZeroArrayIndex(); + + const ElementRegion *CurRegion = + dyn_cast_or_null(Location.getAsRegion()); + + while (CurRegion) { + const auto Index = CurRegion->getIndex().getAs(); + if (!Index) + return std::nullopt; + + QualType ElemType = CurRegion->getElementType(); + + // FIXME: The following early return was presumably added to safeguard the + // getTypeSizeInChars() call (which doesn't accept an incomplete type), but + // it seems that `ElemType` cannot be incomplete at this point. + if (ElemType->isIncompleteType()) + return std::nullopt; + + // Calculate Delta = Index * sizeof(ElemType). + NonLoc Size = SVB.makeArrayIndex( + SVB.getContext().getTypeSizeInChars(ElemType).getQuantity()); + auto Delta = EvalBinOp(BO_Mul, *Index, Size); + if (!Delta) + return std::nullopt; + + // Perform Offset += Delta. + Offset = EvalBinOp(BO_Add, *Offset, *Delta); + if (!Offset) + return std::nullopt; + + OwnerRegion = CurRegion->getSuperRegion()->getAs(); + // When this is just another ElementRegion layer, we need to continue the + // offset calculations: + CurRegion = dyn_cast_or_null(OwnerRegion); + } - static std::optional - computeOffset(ProgramStateRef State, SValBuilder &SVB, SVal Location); + if (OwnerRegion) + return std::make_pair(OwnerRegion, *Offset); - void dump() const; - void dumpToStream(raw_ostream &os) const; -}; + return std::nullopt; } // TODO: once the constraint manager is smart enough to handle non simplified @@ -86,8 +120,8 @@ getSimplifiedOffsets(NonLoc offset, nonloc::ConcreteInt extent, APSIntType(extent.getValue()).convert(SIE->getRHS()); switch (SIE->getOpcode()) { case BO_Mul: - // The constant should never be 0 here, since it the result of scaling - // based on the size of a type which is never 0. + // The constant should never be 0 here, becasue multiplication by zero + // is simplified by the engine. if ((extent.getValue() % constant) != 0) return std::pair(offset, extent); else @@ -163,16 +197,15 @@ void ArrayBoundCheckerV2::checkLocation(SVal location, bool isLoad, return; ProgramStateRef state = checkerContext.getState(); - SValBuilder &svalBuilder = checkerContext.getSValBuilder(); - const std::optional &RawOffset = - RegionRawOffsetV2::computeOffset(state, svalBuilder, location); + + const std::optional> &RawOffset = + computeOffset(state, svalBuilder, location); if (!RawOffset) return; - NonLoc ByteOffset = RawOffset->getByteOffset(); - const SubRegion *Reg = RawOffset->getRegion(); + auto [Reg, ByteOffset] = *RawOffset; // CHECK LOWER BOUND const MemSpaceRegion *Space = Reg->getMemorySpace(); @@ -207,12 +240,13 @@ void ArrayBoundCheckerV2::checkLocation(SVal location, bool isLoad, if (state_exceedsUpperBound) { if (!state_withinUpperBound) { // We know that the index definitely exceeds the upper bound. - reportOOB(checkerContext, state_exceedsUpperBound, OOB_Excedes); + reportOOB(checkerContext, state_exceedsUpperBound, OOB_Exceeds); return; } if (isTainted(state, ByteOffset)) { // Both cases are possible, but the index is tainted, so report. - reportTaintOOB(checkerContext, state_exceedsUpperBound, ByteOffset); + reportOOB(checkerContext, state_exceedsUpperBound, OOB_Taint, + ByteOffset); return; } } @@ -224,58 +258,40 @@ void ArrayBoundCheckerV2::checkLocation(SVal location, bool isLoad, checkerContext.addTransition(state); } -void ArrayBoundCheckerV2::reportTaintOOB(CheckerContext &checkerContext, - ProgramStateRef errorState, - SVal TaintedSVal) const { - ExplodedNode *errorNode = checkerContext.generateErrorNode(errorState); - if (!errorNode) - return; - - if (!TaintBT) - TaintBT.reset( - new BugType(this, "Out-of-bound access", categories::TaintedData)); - - SmallString<256> buf; - llvm::raw_svector_ostream os(buf); - os << "Out of bound memory access (index is tainted)"; - auto BR = - std::make_unique(*TaintBT, os.str(), errorNode); - - // Track back the propagation of taintedness. - for (SymbolRef Sym : getTaintedSymbols(errorState, TaintedSVal)) { - BR->markInteresting(Sym); - } - - checkerContext.emitReport(std::move(BR)); -} - -void ArrayBoundCheckerV2::reportOOB(CheckerContext &checkerContext, - ProgramStateRef errorState, - OOB_Kind kind) const { +void ArrayBoundCheckerV2::reportOOB(CheckerContext &C, + ProgramStateRef ErrorState, OOB_Kind Kind, + SVal TaintedSVal) const { - ExplodedNode *errorNode = checkerContext.generateErrorNode(errorState); - if (!errorNode) + ExplodedNode *ErrorNode = C.generateErrorNode(ErrorState); + if (!ErrorNode) return; - if (!BT) - BT.reset(new BugType(this, "Out-of-bound access")); + // FIXME: These diagnostics are preliminary, and they'll be replaced soon by + // a follow-up commit. - // FIXME: This diagnostics are preliminary. We should get far better - // diagnostics for explaining buffer overruns. + SmallString<128> Buf; + llvm::raw_svector_ostream Out(Buf); + Out << "Out of bound memory access "; - SmallString<256> buf; - llvm::raw_svector_ostream os(buf); - os << "Out of bound memory access "; - switch (kind) { + switch (Kind) { case OOB_Precedes: - os << "(accessed memory precedes memory block)"; + Out << "(accessed memory precedes memory block)"; + break; + case OOB_Exceeds: + Out << "(access exceeds upper limit of memory block)"; break; - case OOB_Excedes: - os << "(access exceeds upper limit of memory block)"; + case OOB_Taint: + Out << "(index is tainted)"; break; } - auto BR = std::make_unique(*BT, os.str(), errorNode); - checkerContext.emitReport(std::move(BR)); + auto BR = std::make_unique( + Kind == OOB_Taint ? TaintBT : BT, Out.str(), ErrorNode); + // Track back the propagation of taintedness, or do nothing if TaintedSVal is + // the default UnknownVal(). + for (SymbolRef Sym : getTaintedSymbols(ErrorState, TaintedSVal)) { + BR->markInteresting(Sym); + } + C.emitReport(std::move(BR)); } bool ArrayBoundCheckerV2::isFromCtypeMacro(const Stmt *S, ASTContext &ACtx) { @@ -297,67 +313,6 @@ bool ArrayBoundCheckerV2::isFromCtypeMacro(const Stmt *S, ASTContext &ACtx) { (MacroName == "isupper") || (MacroName == "isxdigit")); } -#ifndef NDEBUG -LLVM_DUMP_METHOD void RegionRawOffsetV2::dump() const { - dumpToStream(llvm::errs()); -} - -void RegionRawOffsetV2::dumpToStream(raw_ostream &os) const { - os << "raw_offset_v2{" << getRegion() << ',' << getByteOffset() << '}'; -} -#endif - -/// For a given Location that can be represented as a symbolic expression -/// Arr[Idx] (or perhaps Arr[Idx1][Idx2] etc.), return the parent memory block -/// Arr and the distance of Location from the beginning of Arr (expressed in a -/// NonLoc that specifies the number of CharUnits). Returns nullopt when these -/// cannot be determined. -std::optional -RegionRawOffsetV2::computeOffset(ProgramStateRef State, SValBuilder &SVB, - SVal Location) { - QualType T = SVB.getArrayIndexType(); - auto Calc = [&SVB, State, T](BinaryOperatorKind Op, NonLoc LHS, NonLoc RHS) { - // We will use this utility to add and multiply values. - return SVB.evalBinOpNN(State, Op, LHS, RHS, T).getAs(); - }; - - const MemRegion *Region = Location.getAsRegion(); - NonLoc Offset = SVB.makeZeroArrayIndex(); - - while (Region) { - if (const auto *ERegion = dyn_cast(Region)) { - if (const auto Index = ERegion->getIndex().getAs()) { - QualType ElemType = ERegion->getElementType(); - // If the element is an incomplete type, go no further. - if (ElemType->isIncompleteType()) - return std::nullopt; - - // Perform Offset += Index * sizeof(ElemType); then continue the offset - // calculations with SuperRegion: - NonLoc Size = SVB.makeArrayIndex( - SVB.getContext().getTypeSizeInChars(ElemType).getQuantity()); - if (auto Delta = Calc(BO_Mul, *Index, Size)) { - if (auto NewOffset = Calc(BO_Add, Offset, *Delta)) { - Offset = *NewOffset; - Region = ERegion->getSuperRegion(); - continue; - } - } - } - } else if (const auto *SRegion = dyn_cast(Region)) { - // NOTE: The dyn_cast<>() is expected to succeed, it'd be very surprising - // to see a MemSpaceRegion at this point. - // FIXME: We may return with {, 0} even if we didn't handle any - // ElementRegion layers. I think that this behavior was introduced - // accidentally by 8a4c760c204546aba566e302f299f7ed2e00e287 in 2011, so - // it may be useful to review it in the future. - return RegionRawOffsetV2(SRegion, Offset); - } - return std::nullopt; - } - return std::nullopt; -} - void ento::registerArrayBoundCheckerV2(CheckerManager &mgr) { mgr.registerChecker(); } diff --git a/clang/lib/StaticAnalyzer/Checkers/CXXDeleteChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/CXXDeleteChecker.cpp index 1a1f5c5302940..eb265f4dde68b 100644 --- a/clang/lib/StaticAnalyzer/Checkers/CXXDeleteChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/CXXDeleteChecker.cpp @@ -114,6 +114,9 @@ void DeleteWithNonVirtualDtorChecker::checkTypedDeleteExpr( if (!BaseClass || !DerivedClass) return; + if (!BaseClass->hasDefinition() || !DerivedClass->hasDefinition()) + return; + if (BaseClass->getDestructor()->isVirtual()) return; @@ -148,6 +151,9 @@ void CXXArrayDeleteChecker::checkTypedDeleteExpr( if (!BaseClass || !DerivedClass) return; + if (!BaseClass->hasDefinition() || !DerivedClass->hasDefinition()) + return; + if (DE->getOperatorDelete()->getOverloadedOperator() != OO_Array_Delete) return; diff --git a/clang/lib/StaticAnalyzer/Checkers/EnumCastOutOfRangeChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/EnumCastOutOfRangeChecker.cpp index 89be6a47250a2..5844f43991001 100644 --- a/clang/lib/StaticAnalyzer/Checkers/EnumCastOutOfRangeChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/EnumCastOutOfRangeChecker.cpp @@ -59,7 +59,8 @@ class ConstraintBasedEQEvaluator { // value can be matching. class EnumCastOutOfRangeChecker : public Checker> { mutable std::unique_ptr EnumValueCastOutOfRange; - void reportWarning(CheckerContext &C) const; + void reportWarning(CheckerContext &C, const CastExpr *CE, + const EnumDecl *E) const; public: void checkPreStmt(const CastExpr *CE, CheckerContext &C) const; @@ -72,21 +73,38 @@ EnumValueVector getDeclValuesForEnum(const EnumDecl *ED) { EnumValueVector DeclValues( std::distance(ED->enumerator_begin(), ED->enumerator_end())); llvm::transform(ED->enumerators(), DeclValues.begin(), - [](const EnumConstantDecl *D) { return D->getInitVal(); }); + [](const EnumConstantDecl *D) { return D->getInitVal(); }); return DeclValues; } } // namespace -void EnumCastOutOfRangeChecker::reportWarning(CheckerContext &C) const { +void EnumCastOutOfRangeChecker::reportWarning(CheckerContext &C, + const CastExpr *CE, + const EnumDecl *E) const { + assert(E && "valid EnumDecl* is expected"); if (const ExplodedNode *N = C.generateNonFatalErrorNode()) { if (!EnumValueCastOutOfRange) EnumValueCastOutOfRange.reset( new BugType(this, "Enum cast out of range")); - constexpr llvm::StringLiteral Msg = - "The value provided to the cast expression is not in the valid range" - " of values for the enum"; - C.emitReport(std::make_unique( - *EnumValueCastOutOfRange, Msg, N)); + + llvm::SmallString<128> Msg{"The value provided to the cast expression is " + "not in the valid range of values for "}; + StringRef EnumName{E->getName()}; + if (EnumName.empty()) { + Msg += "the enum"; + } else { + Msg += '\''; + Msg += EnumName; + Msg += '\''; + } + + auto BR = std::make_unique(*EnumValueCastOutOfRange, + Msg, N); + bugreporter::trackExpressionValue(N, CE->getSubExpr(), *BR); + BR->addNote("enum declared here", + PathDiagnosticLocation::create(E, C.getSourceManager()), + {E->getSourceRange()}); + C.emitReport(std::move(BR)); } } @@ -138,13 +156,13 @@ void EnumCastOutOfRangeChecker::checkPreStmt(const CastExpr *CE, return; // Check if any of the enum values possibly match. - bool PossibleValueMatch = llvm::any_of( - DeclValues, ConstraintBasedEQEvaluator(C, *ValueToCast)); + bool PossibleValueMatch = + llvm::any_of(DeclValues, ConstraintBasedEQEvaluator(C, *ValueToCast)); // If there is no value that can possibly match any of the enum values, then // warn. if (!PossibleValueMatch) - reportWarning(C); + reportWarning(C, CE, ED); } void ento::registerEnumCastOutOfRangeChecker(CheckerManager &mgr) { diff --git a/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp index bad86682c91e2..4b7103c20557c 100644 --- a/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp @@ -245,10 +245,10 @@ class StreamChecker : public Checker std::string { + if (BR.isInteresting(StreamSym) && &BR.getBugType() == &BT_ResourceLeak) + return Message; + return ""; + }); } const NoteTag *constructSetEofNoteTag(CheckerContext &C, @@ -646,8 +634,9 @@ void StreamChecker::evalFclose(const FnDescription *Desc, const CallEvent &Call, C.addTransition(StateFailure); } -void StreamChecker::preFread(const FnDescription *Desc, const CallEvent &Call, - CheckerContext &C) const { +void StreamChecker::preFreadFwrite(const FnDescription *Desc, + const CallEvent &Call, CheckerContext &C, + bool IsFread) const { ProgramStateRef State = C.getState(); SVal StreamVal = getStreamArg(Desc, Call); State = ensureStreamNonNull(StreamVal, Call.getArgExpr(Desc->StreamArgNo), C, @@ -661,6 +650,11 @@ void StreamChecker::preFread(const FnDescription *Desc, const CallEvent &Call, if (!State) return; + if (!IsFread) { + C.addTransition(State); + return; + } + SymbolRef Sym = StreamVal.getAsSymbol(); if (Sym && State->get(Sym)) { const StreamState *SS = State->get(Sym); @@ -671,24 +665,6 @@ void StreamChecker::preFread(const FnDescription *Desc, const CallEvent &Call, } } -void StreamChecker::preFwrite(const FnDescription *Desc, const CallEvent &Call, - CheckerContext &C) const { - ProgramStateRef State = C.getState(); - SVal StreamVal = getStreamArg(Desc, Call); - State = ensureStreamNonNull(StreamVal, Call.getArgExpr(Desc->StreamArgNo), C, - State); - if (!State) - return; - State = ensureStreamOpened(StreamVal, C, State); - if (!State) - return; - State = ensureNoFilePositionIndeterminate(StreamVal, C, State); - if (!State) - return; - - C.addTransition(State); -} - void StreamChecker::evalFreadFwrite(const FnDescription *Desc, const CallEvent &Call, CheckerContext &C, bool IsFread) const { @@ -1231,7 +1207,7 @@ StreamChecker::reportLeaks(const SmallVector &LeakedSyms, PathDiagnosticLocation LocUsedForUniqueing; if (const Stmt *StreamStmt = StreamOpenNode->getStmtForDiagnostics()) - LocUsedForUniqueing = PathDiagnosticLocation::createBegin( + LocUsedForUniqueing = PathDiagnosticLocation::createBegin( StreamStmt, C.getSourceManager(), StreamOpenNode->getLocationContext()); diff --git a/clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp b/clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp index 9b1d7ae3e6a32..c1f180f31338c 100644 --- a/clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp @@ -186,8 +186,7 @@ bool isPtrConversion(const FunctionDecl *F) { // FIXME: check # of params == 1 const auto FunctionName = safeGetName(F); if (FunctionName == "getPtr" || FunctionName == "WeakPtr" || - FunctionName == "makeWeakPtr" - + FunctionName == "dynamicDowncast" || FunctionName == "downcast" || FunctionName == "bitwise_cast") return true; diff --git a/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedCallArgsChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedCallArgsChecker.cpp index 4ae8c442fa707..407b6ba7a7642 100644 --- a/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedCallArgsChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedCallArgsChecker.cpp @@ -149,7 +149,7 @@ class UncountedCallArgsChecker auto name = safeGetName(Callee); if (name == "adoptRef" || name == "getPtr" || name == "WeakPtr" || - name == "makeWeakPtr" || name == "downcast" || name == "bitwise_cast" || + name == "dynamicDowncast" || name == "downcast" || name == "bitwise_cast" || name == "is" || name == "equal" || name == "hash" || name == "isType" // FIXME: Most/all of these should be implemented via attributes. diff --git a/clang/lib/StaticAnalyzer/Checkers/cert/InvalidPtrChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/cert/InvalidPtrChecker.cpp index aae1a17bc0ae5..e5dd907c660d8 100644 --- a/clang/lib/StaticAnalyzer/Checkers/cert/InvalidPtrChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/cert/InvalidPtrChecker.cpp @@ -30,7 +30,10 @@ namespace { class InvalidPtrChecker : public Checker { private: - BugType BT{this, "Use of invalidated pointer", categories::MemoryError}; + // For accurate emission of NoteTags, the BugType of this checker should have + // a unique address. + BugType InvalidPtrBugType{this, "Use of invalidated pointer", + categories::MemoryError}; void EnvpInvalidatingCall(const CallEvent &Call, CheckerContext &C) const; @@ -38,6 +41,15 @@ class InvalidPtrChecker CheckerContext &C) const; // SEI CERT ENV31-C + + // If set to true, consider getenv calls as invalidating operations on the + // environment variable buffer. This is implied in the standard, but in + // practice does not cause problems (in the commonly used environments). + bool InvalidatingGetEnv = false; + + // GetEnv can be treated invalidating and non-invalidating as well. + const CallDescription GetEnvCall{{"getenv"}, 1}; + const CallDescriptionMap EnvpInvalidatingFunctions = { {{{"setenv"}, 3}, &InvalidPtrChecker::EnvpInvalidatingCall}, {{{"unsetenv"}, 1}, &InvalidPtrChecker::EnvpInvalidatingCall}, @@ -51,7 +63,6 @@ class InvalidPtrChecker // SEI CERT ENV34-C const CallDescriptionMap PreviousCallInvalidatingFunctions = { - {{{"getenv"}, 1}, &InvalidPtrChecker::postPreviousReturnInvalidatingCall}, {{{"setlocale"}, 2}, &InvalidPtrChecker::postPreviousReturnInvalidatingCall}, {{{"strerror"}, 1}, @@ -62,6 +73,10 @@ class InvalidPtrChecker &InvalidPtrChecker::postPreviousReturnInvalidatingCall}, }; + // The private members of this checker corresponding to commandline options + // are set in this function. + friend void ento::registerInvalidPtrChecker(CheckerManager &); + public: // Obtain the environment pointer from 'main()' (if present). void checkBeginFunction(CheckerContext &C) const; @@ -76,6 +91,11 @@ class InvalidPtrChecker // Check if invalidated region is being dereferenced. void checkLocation(SVal l, bool isLoad, const Stmt *S, CheckerContext &C) const; + +private: + const NoteTag *createEnvInvalidationNote(CheckerContext &C, + ProgramStateRef State, + StringRef FunctionName) const; }; } // namespace @@ -84,33 +104,74 @@ class InvalidPtrChecker REGISTER_SET_WITH_PROGRAMSTATE(InvalidMemoryRegions, const MemRegion *) // Stores the region of the environment pointer of 'main' (if present). -REGISTER_TRAIT_WITH_PROGRAMSTATE(EnvPtrRegion, const MemRegion *) +REGISTER_TRAIT_WITH_PROGRAMSTATE(MainEnvPtrRegion, const MemRegion *) + +// Stores the regions of environments returned by getenv calls. +REGISTER_SET_WITH_PROGRAMSTATE(GetenvEnvPtrRegions, const MemRegion *) // Stores key-value pairs, where key is function declaration and value is // pointer to memory region returned by previous call of this function REGISTER_MAP_WITH_PROGRAMSTATE(PreviousCallResultMap, const FunctionDecl *, const MemRegion *) +const NoteTag *InvalidPtrChecker::createEnvInvalidationNote( + CheckerContext &C, ProgramStateRef State, StringRef FunctionName) const { + + const MemRegion *MainRegion = State->get(); + const auto GetenvRegions = State->get(); + + return C.getNoteTag([this, MainRegion, GetenvRegions, + FunctionName = std::string{FunctionName}]( + PathSensitiveBugReport &BR, llvm::raw_ostream &Out) { + // Only handle the BugType of this checker. + if (&BR.getBugType() != &InvalidPtrBugType) + return; + + // Mark all regions that were interesting before as NOT interesting now + // to avoid extra notes coming from invalidation points higher up the + // bugpath. This ensures that only the last invalidation point is marked + // with a note tag. + llvm::SmallVector InvalidLocationNames; + if (BR.isInteresting(MainRegion)) { + BR.markNotInteresting(MainRegion); + InvalidLocationNames.push_back("the environment parameter of 'main'"); + } + bool InterestingGetenvFound = false; + for (const MemRegion *MR : GetenvRegions) { + if (BR.isInteresting(MR)) { + BR.markNotInteresting(MR); + if (!InterestingGetenvFound) { + InterestingGetenvFound = true; + InvalidLocationNames.push_back( + "the environment returned by 'getenv'"); + } + } + } + + // Emit note tag message. + if (InvalidLocationNames.size() >= 1) + Out << '\'' << FunctionName << "' call may invalidate " + << InvalidLocationNames[0]; + if (InvalidLocationNames.size() == 2) + Out << ", and " << InvalidLocationNames[1]; + }); +} + void InvalidPtrChecker::EnvpInvalidatingCall(const CallEvent &Call, CheckerContext &C) const { - StringRef FunctionName = Call.getCalleeIdentifier()->getName(); + // This callevent invalidates all previously generated pointers to the + // environment. ProgramStateRef State = C.getState(); - const MemRegion *SymbolicEnvPtrRegion = State->get(); - if (!SymbolicEnvPtrRegion) - return; - - State = State->add(SymbolicEnvPtrRegion); + if (const MemRegion *MainEnvPtr = State->get()) + State = State->add(MainEnvPtr); + for (const MemRegion *EnvPtr : State->get()) + State = State->add(EnvPtr); - const NoteTag *Note = - C.getNoteTag([SymbolicEnvPtrRegion, FunctionName]( - PathSensitiveBugReport &BR, llvm::raw_ostream &Out) { - if (!BR.isInteresting(SymbolicEnvPtrRegion)) - return; - Out << '\'' << FunctionName - << "' call may invalidate the environment parameter of 'main'"; - }); + StringRef FunctionName = Call.getCalleeIdentifier()->getName(); + const NoteTag *InvalidationNote = + createEnvInvalidationNote(C, State, FunctionName); - C.addTransition(State, Note); + C.addTransition(State, InvalidationNote); } void InvalidPtrChecker::postPreviousReturnInvalidatingCall( @@ -124,9 +185,9 @@ void InvalidPtrChecker::postPreviousReturnInvalidatingCall( if (const MemRegion *const *Reg = State->get(FD)) { const MemRegion *PrevReg = *Reg; State = State->add(PrevReg); - Note = C.getNoteTag([PrevReg, FD](PathSensitiveBugReport &BR, - llvm::raw_ostream &Out) { - if (!BR.isInteresting(PrevReg)) + Note = C.getNoteTag([this, PrevReg, FD](PathSensitiveBugReport &BR, + llvm::raw_ostream &Out) { + if (!BR.isInteresting(PrevReg) || &BR.getBugType() != &InvalidPtrBugType) return; Out << '\''; FD->getNameForDiagnostic(Out, FD->getASTContext().getLangOpts(), true); @@ -146,16 +207,15 @@ void InvalidPtrChecker::postPreviousReturnInvalidatingCall( // Remember to this region. const auto *SymRegOfRetVal = cast(RetVal.getAsRegion()); - const MemRegion *MR = - const_cast(SymRegOfRetVal->getBaseRegion()); + const MemRegion *MR = SymRegOfRetVal->getBaseRegion(); State = State->set(FD, MR); ExplodedNode *Node = C.addTransition(State, Note); - const NoteTag *PreviousCallNote = - C.getNoteTag([MR](PathSensitiveBugReport &BR, llvm::raw_ostream &Out) { - if (!BR.isInteresting(MR)) + const NoteTag *PreviousCallNote = C.getNoteTag( + [this, MR](PathSensitiveBugReport &BR, llvm::raw_ostream &Out) { + if (!BR.isInteresting(MR) || &BR.getBugType() != &InvalidPtrBugType) return; - Out << '\'' << "'previous function call was here" << '\''; + Out << "previous function call was here"; }); C.addTransition(State, Node, PreviousCallNote); @@ -185,6 +245,18 @@ static const MemRegion *findInvalidatedSymbolicBase(ProgramStateRef State, // function call as an argument. void InvalidPtrChecker::checkPostCall(const CallEvent &Call, CheckerContext &C) const { + + ProgramStateRef State = C.getState(); + + // Model 'getenv' calls + if (GetEnvCall.matches(Call)) { + const MemRegion *Region = Call.getReturnValue().getAsRegion(); + if (Region) { + State = State->add(Region); + C.addTransition(State); + } + } + // Check if function invalidates 'envp' argument of 'main' if (const auto *Handler = EnvpInvalidatingFunctions.lookup(Call)) (this->**Handler)(Call, C); @@ -193,14 +265,16 @@ void InvalidPtrChecker::checkPostCall(const CallEvent &Call, if (const auto *Handler = PreviousCallInvalidatingFunctions.lookup(Call)) (this->**Handler)(Call, C); + // If pedantic mode is on, regard 'getenv' calls invalidating as well + if (InvalidatingGetEnv && GetEnvCall.matches(Call)) + postPreviousReturnInvalidatingCall(Call, C); + // Check if one of the arguments of the function call is invalidated // If call was inlined, don't report invalidated argument if (C.wasInlined) return; - ProgramStateRef State = C.getState(); - for (unsigned I = 0, NumArgs = Call.getNumArgs(); I < NumArgs; ++I) { if (const auto *SR = dyn_cast_or_null( @@ -218,8 +292,8 @@ void InvalidPtrChecker::checkPostCall(const CallEvent &Call, C.getASTContext().getPrintingPolicy()); Out << "' in a function call"; - auto Report = - std::make_unique(BT, Out.str(), ErrorNode); + auto Report = std::make_unique( + InvalidPtrBugType, Out.str(), ErrorNode); Report->markInteresting(InvalidatedSymbolicBase); Report->addRange(Call.getArgSourceRange(I)); C.emitReport(std::move(Report)); @@ -243,7 +317,7 @@ void InvalidPtrChecker::checkBeginFunction(CheckerContext &C) const { // Save the memory region pointed by the environment pointer parameter of // 'main'. - C.addTransition(State->set(EnvpReg)); + C.addTransition(State->set(EnvpReg)); } // Check if invalidated region is being dereferenced. @@ -262,13 +336,16 @@ void InvalidPtrChecker::checkLocation(SVal Loc, bool isLoad, const Stmt *S, return; auto Report = std::make_unique( - BT, "dereferencing an invalid pointer", ErrorNode); + InvalidPtrBugType, "dereferencing an invalid pointer", ErrorNode); Report->markInteresting(InvalidatedSymbolicBase); C.emitReport(std::move(Report)); } void ento::registerInvalidPtrChecker(CheckerManager &Mgr) { - Mgr.registerChecker(); + auto *Checker = Mgr.registerChecker(); + Checker->InvalidatingGetEnv = + Mgr.getAnalyzerOptions().getCheckerBooleanOption(Checker, + "InvalidatingGetEnv"); } bool ento::shouldRegisterInvalidPtrChecker(const CheckerManager &) { diff --git a/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp b/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp index 451ee91b94533..2e67fb953e456 100644 --- a/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp +++ b/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp @@ -2509,7 +2509,7 @@ void ExprEngine::processCFGBlockEntrance(const BlockEdge &L, if (BlockCount == AMgr.options.maxBlockVisitOnPath - 1 && AMgr.options.ShouldWidenLoops) { const Stmt *Term = nodeBuilder.getContext().getBlock()->getTerminatorStmt(); - if (!isa_and_nonnull(Term)) + if (!isa_and_nonnull(Term)) return; // Widen. const LocationContext *LCtx = Pred->getLocationContext(); diff --git a/clang/lib/StaticAnalyzer/Core/LoopWidening.cpp b/clang/lib/StaticAnalyzer/Core/LoopWidening.cpp index a3b29ff487e4e..9e42801760622 100644 --- a/clang/lib/StaticAnalyzer/Core/LoopWidening.cpp +++ b/clang/lib/StaticAnalyzer/Core/LoopWidening.cpp @@ -35,6 +35,8 @@ static const Expr *getLoopCondition(const Stmt *LoopStmt) { return cast(LoopStmt)->getCond(); case Stmt::DoStmtClass: return cast(LoopStmt)->getCond(); + case Stmt::CXXForRangeStmtClass: + return cast(LoopStmt)->getCond(); } } @@ -45,7 +47,7 @@ ProgramStateRef getWidenedLoopState(ProgramStateRef PrevState, const LocationContext *LCtx, unsigned BlockCount, const Stmt *LoopStmt) { - assert((isa(LoopStmt))); + assert((isa(LoopStmt))); // Invalidate values in the current state. // TODO Make this more conservative by only invalidating values that might diff --git a/clang/lib/Tooling/Inclusions/Stdlib/CMakeLists.txt b/clang/lib/Tooling/Inclusions/Stdlib/CMakeLists.txt index 0f52c3590ac9a..ed323ab3528b1 100644 --- a/clang/lib/Tooling/Inclusions/Stdlib/CMakeLists.txt +++ b/clang/lib/Tooling/Inclusions/Stdlib/CMakeLists.txt @@ -1,3 +1,23 @@ +# Workaround for MSVC ARM64 performance regression: +# https://developercommunity.visualstudio.com/t/Compiling-a-specific-code-for-ARM64-with/10444970 +# Since /O1 and /O2 represent a set of optimizations, +# our goal is to disable the /Og flag while retaining the other optimizations from the /O1|/O2 set +if(MSVC AND NOT CMAKE_CXX_COMPILER_ID MATCHES Clang + AND MSVC_VERSION VERSION_GREATER_EQUAL 1932 + AND CMAKE_SYSTEM_PROCESSOR MATCHES "ARM64") + + string(TOUPPER "${CMAKE_BUILD_TYPE}" uppercase_CMAKE_BUILD_TYPE) + string(REGEX MATCHALL "/[Oo][12]" opt_flags "${CMAKE_CXX_FLAGS} ${CMAKE_CXX_FLAGS_${uppercase_CMAKE_BUILD_TYPE}}") + if (opt_flags) + if(opt_flags MATCHES "1$") + set(opt_flags "/Od;/Os;/Oy;/Ob2;/GF;/Gy") + elseif (opt_flags MATCHES "2$") + set(opt_flags "/Od;/Oi;/Ot;/Oy;/Ob2;/GF;/Gy") + endif() + set_source_files_properties(StandardLibrary.cpp PROPERTIES COMPILE_OPTIONS "${opt_flags}") + endif() +endif() + add_clang_library(clangToolingInclusionsStdlib StandardLibrary.cpp diff --git a/clang/lib/Tooling/Inclusions/Stdlib/StandardLibrary.cpp b/clang/lib/Tooling/Inclusions/Stdlib/StandardLibrary.cpp index 664f3b76f6612..03f61d33e1f26 100644 --- a/clang/lib/Tooling/Inclusions/Stdlib/StandardLibrary.cpp +++ b/clang/lib/Tooling/Inclusions/Stdlib/StandardLibrary.cpp @@ -55,20 +55,28 @@ static const SymbolHeaderMapping *getMappingPerLang(Lang L) { } static int countSymbols(Lang Language) { - llvm::DenseSet Set; -#define SYMBOL(Name, NS, Header) Set.insert(#NS #Name); + ArrayRef Symbols; +#define SYMBOL(Name, NS, Header) #NS #Name, switch (Language) { - case Lang::C: + case Lang::C: { + static constexpr const char *CSymbols[] = { #include "CSymbolMap.inc" + }; + Symbols = CSymbols; break; - case Lang::CXX: + } + case Lang::CXX: { + static constexpr const char *CXXSymbols[] = { #include "StdSpecialSymbolMap.inc" #include "StdSymbolMap.inc" #include "StdTsSymbolMap.inc" + }; + Symbols = CXXSymbols; break; } + } #undef SYMBOL - return Set.size(); + return llvm::DenseSet(Symbols.begin(), Symbols.end()).size(); } static int initialize(Lang Language) { @@ -127,17 +135,33 @@ static int initialize(Lang Language) { NSSymbolMap &NSSymbols = AddNS(QName.take_front(NSLen)); NSSymbols.try_emplace(QName.drop_front(NSLen), SymIndex); }; -#define SYMBOL(Name, NS, Header) Add(#NS #Name, strlen(#NS), #Header); + + struct Symbol { + const char *QName; + unsigned NSLen; + const char *HeaderName; + }; +#define SYMBOL(Name, NS, Header) {#NS #Name, StringRef(#NS).size(), #Header}, switch (Language) { - case Lang::C: + case Lang::C: { + static constexpr Symbol CSymbols[] = { #include "CSymbolMap.inc" + }; + for (const Symbol &S : CSymbols) + Add(S.QName, S.NSLen, S.HeaderName); break; - case Lang::CXX: + } + case Lang::CXX: { + static constexpr Symbol CXXSymbols[] = { #include "StdSpecialSymbolMap.inc" #include "StdSymbolMap.inc" #include "StdTsSymbolMap.inc" + }; + for (const Symbol &S : CXXSymbols) + Add(S.QName, S.NSLen, S.HeaderName); break; } + } #undef SYMBOL Mapping->HeaderNames = new llvm::StringRef[Mapping->HeaderIDs->size()]; diff --git a/clang/lib/Tooling/Inclusions/Stdlib/StdSpecialSymbolMap.inc b/clang/lib/Tooling/Inclusions/Stdlib/StdSpecialSymbolMap.inc index 165c1fc2eebc2..0d351d688a329 100644 --- a/clang/lib/Tooling/Inclusions/Stdlib/StdSpecialSymbolMap.inc +++ b/clang/lib/Tooling/Inclusions/Stdlib/StdSpecialSymbolMap.inc @@ -367,6 +367,16 @@ SYMBOL(any_cast, std::, ) SYMBOL(div, std::, ) SYMBOL(abort, std::, ) +// These are C symbols that are not under std namespace. +SYMBOL(localtime_r, None, ) +SYMBOL(localtime_r, None, ) +SYMBOL(localtime_s, None, ) +SYMBOL(localtime_s, None, ) +SYMBOL(gmtime_r, None, ) +SYMBOL(gmtime_r, None, ) +SYMBOL(gmtime_s, None, ) +SYMBOL(gmtime_s, None, ) + // The std::placeholder symbols (_1, ..., _N) are listed in the cppreference // placeholder.html, but the index only contains a single entry with "_1, _2, ..., _N" // text, which are not handled by the script. diff --git a/clang/test/AST/HLSL/this-reference-template.hlsl b/clang/test/AST/HLSL/this-reference-template.hlsl index 3b7fba3efdc74..60e057986ebf8 100644 --- a/clang/test/AST/HLSL/this-reference-template.hlsl +++ b/clang/test/AST/HLSL/this-reference-template.hlsl @@ -35,12 +35,12 @@ void main() { // CHECK: -CXXMethodDecl 0x{{[0-9A-Fa-f]+}} line:8:5 used getFirst 'int ()' implicit_instantiation implicit-inline // CHECK-NEXT:-CompoundStmt 0x{{[0-9A-Fa-f]+}} // CHECK-NEXT:-ReturnStmt 0x{{[0-9A-Fa-f]+}} -// CHECK-NEXT:-ImplicitCastExpr 0x{{[0-9A-Fa-f]+}} 'int':'int' -// CHECK-NEXT:-MemberExpr 0x{{[0-9A-Fa-f]+}} 'int':'int' lvalue .First 0x{{[0-9A-Fa-f]+}} +// CHECK-NEXT:-ImplicitCastExpr 0x{{[0-9A-Fa-f]+}} 'int' +// CHECK-NEXT:-MemberExpr 0x{{[0-9A-Fa-f]+}} 'int' lvalue .First 0x{{[0-9A-Fa-f]+}} // CHECK-NEXT:-CXXThisExpr 0x{{[0-9A-Fa-f]+}} 'Pair' lvalue this // CHECK-NEXT:-CXXMethodDecl 0x{{[0-9A-Fa-f]+}} line:12:5 used getSecond 'float ()' implicit_instantiation implicit-inline // CHECK-NEXT:-CompoundStmt 0x{{[0-9A-Fa-f]+}} // CHECK-NEXT:-ReturnStmt 0x{{[0-9A-Fa-f]+}} -// CHECK-NEXT:-ImplicitCastExpr 0x{{[0-9A-Fa-f]+}} 'float':'float' -// CHECK-NEXT:-MemberExpr 0x{{[0-9A-Fa-f]+}} 'float':'float' lvalue .Second 0x{{[0-9A-Fa-f]+}} +// CHECK-NEXT:-ImplicitCastExpr 0x{{[0-9A-Fa-f]+}} 'float' +// CHECK-NEXT:-MemberExpr 0x{{[0-9A-Fa-f]+}} 'float' lvalue .Second 0x{{[0-9A-Fa-f]+}} // CHECK-NEXT:-CXXThisExpr 0x{{[0-9A-Fa-f]+}} 'Pair' lvalue implicit this diff --git a/clang/test/AST/Interp/arrays.cpp b/clang/test/AST/Interp/arrays.cpp index 18c4ae4354f54..34e0086fb9ee8 100644 --- a/clang/test/AST/Interp/arrays.cpp +++ b/clang/test/AST/Interp/arrays.cpp @@ -1,5 +1,7 @@ // RUN: %clang_cc1 -fexperimental-new-constant-interpreter -verify %s +// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -std=c++20 -verify %s // RUN: %clang_cc1 -verify=ref %s +// RUN: %clang_cc1 -verify=ref -std=c++20 %s constexpr int m = 3; constexpr const int *foo[][5] = { @@ -372,9 +374,6 @@ namespace ZeroInit { } namespace ArrayInitLoop { - /// FIXME: The ArrayInitLoop for the decomposition initializer in g() has - /// f(n) as its CommonExpr. We need to evaluate that exactly once and not - /// N times as we do right now. struct X { int arr[3]; }; @@ -386,8 +385,7 @@ namespace ArrayInitLoop { auto [a, b, c] = f(n).arr; return a + b + c; } - static_assert(g() == 6); // expected-error {{failed}} \ - // expected-note {{15 == 6}} + static_assert(g() == 6, ""); } namespace StringZeroFill { @@ -410,3 +408,149 @@ namespace StringZeroFill { static_assert(b[4] == '\0', ""); static_assert(b[5] == '\0', ""); } + +namespace NoInitMapLeak { +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wdivision-by-zero" +#pragma clang diagnostic ignored "-Wc++20-extensions" + constexpr int testLeak() { // expected-error {{never produces a constant expression}} \ + // ref-error {{never produces a constant expression}} + int a[2]; + a[0] = 1; + // interrupts interpretation. + (void)(1 / 0); // expected-note 2{{division by zero}} \ + // ref-note 2{{division by zero}} + + + return 1; + } +#pragma clang diagnostic pop + static_assert(testLeak() == 1, ""); // expected-error {{not an integral constant expression}} \ + // expected-note {{in call to 'testLeak()'}} \ + // ref-error {{not an integral constant expression}} \ + // ref-note {{in call to 'testLeak()'}} + + + constexpr int a[] = {1,2,3,4/0,5}; // expected-error {{must be initialized by a constant expression}} \ + // expected-note {{division by zero}} \ + // ref-error {{must be initialized by a constant expression}} \ + // ref-note {{division by zero}} \ + // ref-note {{declared here}} + + /// FIXME: This should fail in the new interpreter as well. + constexpr int b = a[0]; // ref-error {{must be initialized by a constant expression}} \ + // ref-note {{is not a constant expression}} \ + // ref-note {{declared here}} + static_assert(b == 1, ""); // ref-error {{not an integral constant expression}} \ + // ref-note {{not a constant expression}} + + constexpr int f() { // expected-error {{never produces a constant expression}} \ + // ref-error {{never produces a constant expression}} + int a[] = {19,2,3/0,4}; // expected-note 2{{division by zero}} \ + // expected-warning {{is undefined}} \ + // ref-note 2{{division by zero}} \ + // ref-warning {{is undefined}} + return 1; + } + static_assert(f() == 1, ""); // expected-error {{not an integral constant expression}} \ + // expected-note {{in call to}} \ + // ref-error {{not an integral constant expression}} \ + // ref-note {{in call to}} +} + +namespace Incomplete { + struct Foo { + char c; + int a[]; + }; + + constexpr Foo F{}; + constexpr const int *A = F.a; // ref-error {{must be initialized by a constant expression}} \ + // ref-note {{array-to-pointer decay of array member without known bound}} \ + // expected-error {{must be initialized by a constant expression}} \ + // expected-note {{array-to-pointer decay of array member without known bound}} + + constexpr const int *B = F.a + 1; // ref-error {{must be initialized by a constant expression}} \ + // ref-note {{array-to-pointer decay of array member without known bound}} \ + // expected-error {{must be initialized by a constant expression}} \ + // expected-note {{array-to-pointer decay of array member without known bound}} + + constexpr int C = *F.a; // ref-error {{must be initialized by a constant expression}} \ + // ref-note {{array-to-pointer decay of array member without known bound}} \ + // expected-error {{must be initialized by a constant expression}} \ + // expected-note {{array-to-pointer decay of array member without known bound}} + + + + /// These are from test/SemaCXX/constant-expression-cxx11.cpp + /// and are the only tests using the 'indexing of array without known bound' diagnostic. + /// We currently diagnose them differently. + extern int arr[]; // expected-note 3{{declared here}} + constexpr int *c = &arr[1]; // ref-error {{must be initialized by a constant expression}} \ + // ref-note {{indexing of array without known bound}} \ + // expected-error {{must be initialized by a constant expression}} \ + // expected-note {{read of non-constexpr variable 'arr'}} + constexpr int *d = &arr[1]; // ref-error {{must be initialized by a constant expression}} \ + // ref-note {{indexing of array without known bound}} \ + // expected-error {{must be initialized by a constant expression}} \ + // expected-note {{read of non-constexpr variable 'arr'}} + constexpr int *e = arr + 1; // ref-error {{must be initialized by a constant expression}} \ + // ref-note {{indexing of array without known bound}} \ + // expected-error {{must be initialized by a constant expression}} \ + // expected-note {{read of non-constexpr variable 'arr'}} +} + +namespace GH69115 { + /// This used to crash because we were trying to emit destructors for the + /// array. + constexpr int foo() { + int arr[2][2] = {1, 2, 3, 4}; + return 0; + } + static_assert(foo() == 0, ""); + + /// Test that we still emit the destructors for multi-dimensional + /// composite arrays. +#if __cplusplus >= 202002L + constexpr void assert(bool C) { + if (C) + return; + // Invalid in constexpr. + (void)(1 / 0); // expected-warning {{undefined}} \ + // ref-warning {{undefined}} + } + + class F { + public: + int a; + int *dtor; + int &idx; + constexpr F(int a, int *dtor, int &idx) : a(a), dtor(dtor), idx(idx) {} + constexpr ~F() noexcept(false){ + dtor[idx] = a; + ++idx; + } + }; + constexpr int foo2() { + int dtorIndices[] = {0, 0, 0, 0}; + int idx = 0; + + { + F arr[2][2] = {F(1, dtorIndices, idx), + F(2, dtorIndices, idx), + F(3, dtorIndices, idx), + F(4, dtorIndices, idx)}; + } + + /// Reverse-reverse order. + assert(idx == 4); + assert(dtorIndices[0] == 4); + assert(dtorIndices[1] == 3); + assert(dtorIndices[2] == 2); + assert(dtorIndices[3] == 1); + + return 0; + } + static_assert(foo2() == 0, ""); +#endif +} diff --git a/clang/test/AST/Interp/c.c b/clang/test/AST/Interp/c.c index 974ca72702f7d..6bfcded0a7864 100644 --- a/clang/test/AST/Interp/c.c +++ b/clang/test/AST/Interp/c.c @@ -3,6 +3,8 @@ // RUN: %clang_cc1 -verify=ref -std=c11 %s // RUN: %clang_cc1 -pedantic -verify=pedantic-ref -std=c11 %s +typedef __INTPTR_TYPE__ intptr_t; + _Static_assert(1, ""); _Static_assert(0 != 1, ""); _Static_assert(1.0 == 1.0, ""); // pedantic-ref-warning {{not an integer constant expression}} \ @@ -47,3 +49,35 @@ _Static_assert(&a != 0, ""); // ref-warning {{always true}} \ // expected-warning {{always true}} \ // pedantic-expected-warning {{always true}} \ // pedantic-expected-warning {{is a GNU extension}} +_Static_assert((&c + 1) != 0, ""); // pedantic-ref-warning {{is a GNU extension}} \ + // pedantic-expected-warning {{is a GNU extension}} +_Static_assert((&a + 100) != 0, ""); // pedantic-ref-warning {{is a GNU extension}} \ + // pedantic-ref-note {{100 of non-array}} \ + // pedantic-expected-note {{100 of non-array}} \ + // pedantic-expected-warning {{is a GNU extension}} +_Static_assert((&a - 100) != 0, ""); // pedantic-ref-warning {{is a GNU extension}} \ + // pedantic-expected-warning {{is a GNU extension}} \ + // pedantic-ref-note {{-100 of non-array}} \ + // pedantic-expected-note {{-100 of non-array}} +/// extern variable of a composite type. +/// FIXME: The 'cast from void*' note is missing in the new interpreter. +extern struct Test50S Test50; +_Static_assert(&Test50 != (void*)0, ""); // ref-warning {{always true}} \ + // pedantic-ref-warning {{always true}} \ + // pedantic-ref-warning {{is a GNU extension}} \ + // pedantic-ref-note {{cast from 'void *' is not allowed}} \ + // expected-warning {{always true}} \ + // pedantic-expected-warning {{always true}} \ + // pedantic-expected-warning {{is a GNU extension}} + +struct y {int x,y;}; +int a2[(intptr_t)&((struct y*)0)->y]; // expected-warning {{folded to constant array}} \ + // pedantic-expected-warning {{folded to constant array}} \ + // ref-warning {{folded to constant array}} \ + // pedantic-ref-warning {{folded to constant array}} + +const struct y *yy = (struct y*)0; +const intptr_t L = (intptr_t)(&(yy->y)); // expected-error {{not a compile-time constant}} \ + // pedantic-expected-error {{not a compile-time constant}} \ + // ref-error {{not a compile-time constant}} \ + // pedantic-ref-error {{not a compile-time constant}} diff --git a/clang/test/AST/Interp/cxx20.cpp b/clang/test/AST/Interp/cxx20.cpp index 197090b0a37d9..50a7c02925878 100644 --- a/clang/test/AST/Interp/cxx20.cpp +++ b/clang/test/AST/Interp/cxx20.cpp @@ -701,13 +701,12 @@ namespace ThreeWayCmp { static_assert(pa2 <=> pa1 == 1, ""); } -// FIXME: Interp should also be able to evaluate this snippet properly. namespace ConstexprArrayInitLoopExprDestructors { struct Highlander { int *p = 0; constexpr Highlander() {} - constexpr void set(int *p) { this->p = p; ++*p; if (*p != 1) throw "there can be only one"; } // expected-note {{not valid in a constant expression}} + constexpr void set(int *p) { this->p = p; ++*p; if (*p != 1) throw "there can be only one"; } constexpr ~Highlander() { --*p; } }; @@ -715,21 +714,41 @@ namespace ConstexprArrayInitLoopExprDestructors int *p; constexpr X(int *p) : p(p) {} constexpr X(const X &x, Highlander &&h = Highlander()) : p(x.p) { - h.set(p); // expected-note {{in call to '&Highlander()->set(&n)'}} + h.set(p); } }; constexpr int f() { int n = 0; X x[3] = {&n, &n, &n}; - auto [a, b, c] = x; // expected-note {{in call to 'X(x[0], Highlander())'}} + auto [a, b, c] = x; return n; } - static_assert(f() == 0); // expected-error {{not an integral constant expression}} \ - // expected-note {{in call to 'f()'}} + static_assert(f() == 0); +} + +namespace NonPrimitiveOpaqueValue +{ + struct X { + int x; + constexpr operator bool() const { return x != 0; } + }; - int main() { - return f(); + constexpr int ternary() { return X(0) ?: X(0); } + + static_assert(!ternary(), ""); +} + +namespace TryCatch { + constexpr int foo() { + int a = 10; + try { + ++a; + } catch(int m) { + --a; + } + return a; } + static_assert(foo() == 11); } diff --git a/clang/test/AST/Interp/functions.cpp b/clang/test/AST/Interp/functions.cpp index 68082576f2735..4bef9c2f7c0d1 100644 --- a/clang/test/AST/Interp/functions.cpp +++ b/clang/test/AST/Interp/functions.cpp @@ -350,3 +350,24 @@ namespace PtrReturn { } static_assert(a() == nullptr, ""); } + +namespace Variadic { + struct S { int a; bool b; }; + + constexpr void variadic_function(int a, ...) {} + constexpr int f1() { + variadic_function(1, S{'a', false}); + return 1; + } + static_assert(f1() == 1, ""); + + constexpr int variadic_function2(...) { + return 12; + } + static_assert(variadic_function2() == 12, ""); + static_assert(variadic_function2(1, 2, 3, 4, 5) == 12, ""); + static_assert(variadic_function2(1, variadic_function2()) == 12, ""); + + constexpr int (*VFP)(...) = variadic_function2; + static_assert(VFP() == 12, ""); +} diff --git a/clang/test/AST/Interp/intap.cpp b/clang/test/AST/Interp/intap.cpp index 27fae1b904351..02a860eb0986c 100644 --- a/clang/test/AST/Interp/intap.cpp +++ b/clang/test/AST/Interp/intap.cpp @@ -27,6 +27,9 @@ static_assert(BitIntZero2 == 0, ""); constexpr unsigned _BitInt(1) UBitIntZero1{}; static_assert(UBitIntZero1 == 0, ""); +constexpr unsigned _BitInt(2) BI1 = 3u; +static_assert(BI1 == 3, ""); + #ifdef __SIZEOF_INT128__ namespace i128 { diff --git a/clang/test/AST/Interp/literals.cpp b/clang/test/AST/Interp/literals.cpp index a83dcd2341115..ba24955d14503 100644 --- a/clang/test/AST/Interp/literals.cpp +++ b/clang/test/AST/Interp/literals.cpp @@ -1,7 +1,7 @@ -// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -fms-extensions -std=c++11 -verify %s -// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -fms-extensions -std=c++20 -verify %s -// RUN: %clang_cc1 -std=c++11 -fms-extensions -verify=ref %s -// RUN: %clang_cc1 -std=c++20 -fms-extensions -verify=ref %s +// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -Wno-vla -fms-extensions -std=c++11 -verify %s +// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -Wno-vla -fms-extensions -std=c++20 -verify %s +// RUN: %clang_cc1 -std=c++11 -fms-extensions -Wno-vla -verify=ref %s +// RUN: %clang_cc1 -std=c++20 -fms-extensions -Wno-vla -verify=ref %s #define INT_MIN (~__INT_MAX__) #define INT_MAX __INT_MAX__ @@ -56,6 +56,15 @@ namespace ScalarTypes { }; static_assert(getScalar() == First, ""); /// FIXME: Member pointers. + +#if __cplusplus >= 201402L + constexpr void Void(int n) { + void(n + 1); + void(); + } + constexpr int void_test = (Void(0), 1); + static_assert(void_test == 1, ""); +#endif } namespace IntegralCasts { diff --git a/clang/test/AST/Interp/records.cpp b/clang/test/AST/Interp/records.cpp index a2e878f6132d0..280eaf34898ce 100644 --- a/clang/test/AST/Interp/records.cpp +++ b/clang/test/AST/Interp/records.cpp @@ -1042,13 +1042,10 @@ namespace TemporaryObjectExpr { F f{12}; }; constexpr int foo(S x) { - return x.a; // expected-note {{read of uninitialized object}} \ - // ref-note {{read of uninitialized object}} + return x.a; // expected-note {{read of uninitialized object}} } static_assert(foo(S()) == 0, ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{in call to}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{in call to}} + // expected-note {{in call to}} }; #endif } @@ -1105,3 +1102,36 @@ namespace DelegatingConstructors { static_assert(d4.a == 10, ""); static_assert(d4.b == 12, ""); } + +namespace AccessOnNullptr { + struct F { + int a; + }; + + constexpr int a() { // expected-error {{never produces a constant expression}} \ + // ref-error {{never produces a constant expression}} + F *f = nullptr; + + f->a = 0; // expected-note 2{{cannot access field of null pointer}} \ + // ref-note 2{{cannot access field of null pointer}} + return f->a; + } + static_assert(a() == 0, ""); // expected-error {{not an integral constant expression}} \ + // expected-note {{in call to 'a()'}} \ + // ref-error {{not an integral constant expression}} \ + // ref-note {{in call to 'a()'}} + + constexpr int a2() { // expected-error {{never produces a constant expression}} \ + // ref-error {{never produces a constant expression}} + F *f = nullptr; + + + const int *a = &(f->a); // expected-note 2{{cannot access field of null pointer}} \ + // ref-note 2{{cannot access field of null pointer}} + return f->a; + } + static_assert(a2() == 0, ""); // expected-error {{not an integral constant expression}} \ + // expected-note {{in call to 'a2()'}} \ + // ref-error {{not an integral constant expression}} \ + // ref-note {{in call to 'a2()'}} +} diff --git a/clang/test/AST/ast-dump-APValue-anon-union.cpp b/clang/test/AST/ast-dump-APValue-anon-union.cpp index 906bfe4857ed0..0e6466ee1fd73 100644 --- a/clang/test/AST/ast-dump-APValue-anon-union.cpp +++ b/clang/test/AST/ast-dump-APValue-anon-union.cpp @@ -30,23 +30,23 @@ union U1 { void Test() { constexpr S0 s0{}; - // CHECK: | `-VarDecl {{.*}} col:{{.*}} s0 'const S0':'const S0' constexpr listinit + // CHECK: | `-VarDecl {{.*}} col:{{.*}} s0 'const S0' constexpr listinit // CHECK-NEXT: | |-value: Struct // CHECK-NEXT: | | `-field: Union .i Int 42 constexpr U0 u0a{}; - // CHECK: | `-VarDecl {{.*}} col:{{.*}} u0a 'const U0':'const U0' constexpr listinit + // CHECK: | `-VarDecl {{.*}} col:{{.*}} u0a 'const U0' constexpr listinit // CHECK-NEXT: | |-value: Union None constexpr U0 u0b{3.1415f}; - // CHECK: | `-VarDecl {{.*}} col:{{.*}} u0b 'const U0':'const U0' constexpr listinit + // CHECK: | `-VarDecl {{.*}} col:{{.*}} u0b 'const U0' constexpr listinit // CHECK-NEXT: | |-value: Union .U0::(anonymous union at {{.*}}) Union .f Float 3.141500e+00 constexpr U1 u1a{}; - // CHECK: | `-VarDecl {{.*}} col:{{.*}} u1a 'const U1':'const U1' constexpr listinit + // CHECK: | `-VarDecl {{.*}} col:{{.*}} u1a 'const U1' constexpr listinit // CHECK-NEXT: | |-value: Union .U1::(anonymous union at {{.*}}) Union .f Float 0.000000e+00 constexpr U1 u1b{3.1415f}; - // CHECK: `-VarDecl {{.*}} col:{{.*}} u1b 'const U1':'const U1' constexpr listinit + // CHECK: `-VarDecl {{.*}} col:{{.*}} u1b 'const U1' constexpr listinit // CHECK-NEXT: |-value: Union .U1::(anonymous union at {{.*}}) Union .f Float 3.141500e+00 } diff --git a/clang/test/AST/ast-dump-APValue-struct.cpp b/clang/test/AST/ast-dump-APValue-struct.cpp index 04d1877c293d1..4730404abc287 100644 --- a/clang/test/AST/ast-dump-APValue-struct.cpp +++ b/clang/test/AST/ast-dump-APValue-struct.cpp @@ -60,12 +60,12 @@ struct S5 : S4 { void Test() { constexpr S0 s0{}; - // CHECK: | `-VarDecl {{.*}} col:{{.*}} s0 'const S0':'const S0' constexpr listinit + // CHECK: | `-VarDecl {{.*}} col:{{.*}} s0 'const S0' constexpr listinit // CHECK-NEXT: | |-value: Struct // CHECK-NEXT: | | `-fields: Int 0, Union .j Int 0 constexpr S1 s1{}; - // CHECK: | `-VarDecl {{.*}} col:{{.*}} s1 'const S1':'const S1' constexpr listinit + // CHECK: | `-VarDecl {{.*}} col:{{.*}} s1 'const S1' constexpr listinit // CHECK-NEXT: | |-value: Struct // CHECK-NEXT: | | |-field: Int 0 // CHECK-NEXT: | | `-field: Union .s @@ -73,12 +73,12 @@ void Test() { // CHECK-NEXT: | | `-field: Int 0 constexpr S2 s2{}; - // CHECK: | `-VarDecl {{.*}} col:{{.*}} s2 'const S2':'const S2' constexpr listinit + // CHECK: | `-VarDecl {{.*}} col:{{.*}} s2 'const S2' constexpr listinit // CHECK-NEXT: | |-value: Struct // CHECK-NEXT: | | `-fields: Int 0, Union .u Union .j Int 0 constexpr S3 s3{}; - // CHECK: | `-VarDecl {{.*}} col:{{.*}} s3 'const S3':'const S3' constexpr listinit + // CHECK: | `-VarDecl {{.*}} col:{{.*}} s3 'const S3' constexpr listinit // CHECK-NEXT: | |-value: Struct // CHECK-NEXT: | | |-field: Int 0 // CHECK-NEXT: | | `-field: Union .u @@ -87,7 +87,7 @@ void Test() { // CHECK-NEXT: | | `-field: Int 0 constexpr S4 s4{}; - // CHECK: | `-VarDecl {{.*}} col:{{.*}} s4 'const S4':'const S4' constexpr listinit + // CHECK: | `-VarDecl {{.*}} col:{{.*}} s4 'const S4' constexpr listinit // CHECK-NEXT: | |-value: Struct // CHECK-NEXT: | | |-base: Struct // CHECK-NEXT: | | | `-fields: Int 0, Union .j Int 0 @@ -96,7 +96,7 @@ void Test() { // CHECK-NEXT: | | `-fields: Int 4, Int 5, Int 6 constexpr S5 s5{}; - // CHECK: `-VarDecl {{.*}} col:{{.*}} s5 'const S5':'const S5' constexpr listinit + // CHECK: `-VarDecl {{.*}} col:{{.*}} s5 'const S5' constexpr listinit // CHECK-NEXT: |-value: Struct // CHECK-NEXT: | |-base: Struct // CHECK-NEXT: | | |-base: Struct diff --git a/clang/test/AST/ast-dump-APValue-union.cpp b/clang/test/AST/ast-dump-APValue-union.cpp index b70b5ea484a6e..c717b6ece7382 100644 --- a/clang/test/AST/ast-dump-APValue-union.cpp +++ b/clang/test/AST/ast-dump-APValue-union.cpp @@ -39,25 +39,25 @@ union U3 { void Test() { constexpr U0 u0{}; - // CHECK: | `-VarDecl {{.*}} col:{{.*}} u0 'const U0':'const U0' constexpr listinit + // CHECK: | `-VarDecl {{.*}} col:{{.*}} u0 'const U0' constexpr listinit // CHECK-NEXT: | |-value: Union .i Int 42 constexpr U1 u1{}; - // CHECK: | `-VarDecl {{.*}} col:{{.*}} u1 'const U1':'const U1' constexpr listinit + // CHECK: | `-VarDecl {{.*}} col:{{.*}} u1 'const U1' constexpr listinit // CHECK-NEXT: | |-value: Union .uinner Union .f Float 3.141500e+00 constexpr U2 u2{}; - // CHECK: | `-VarDecl {{.*}} col:{{.*}} u2 'const U2':'const U2' constexpr listinit + // CHECK: | `-VarDecl {{.*}} col:{{.*}} u2 'const U2' constexpr listinit // CHECK-NEXT: | |-value: Union .uinner // CHECK-NEXT: | | `-Union .arr // CHECK-NEXT: | | `-Array size=2 // CHECK-NEXT: | | `-elements: Int 1, Int 2 constexpr U3 u3a = {.f = 3.1415}; - // CHECK: | `-VarDecl {{.*}} col:{{.*}} u3a 'const U3':'const U3' constexpr cinit + // CHECK: | `-VarDecl {{.*}} col:{{.*}} u3a 'const U3' constexpr cinit // CHECK-NEXT: | |-value: Union .f Float 3.141500e+00 constexpr U3 u3b = {.uinner = {}}; - // CHECK: `-VarDecl {{.*}} col:{{.*}} u3b 'const U3':'const U3' constexpr cinit + // CHECK: `-VarDecl {{.*}} col:{{.*}} u3b 'const U3' constexpr cinit // CHECK-NEXT: |-value: Union .uinner Union .d Float 3.141500e+00 } diff --git a/clang/test/AST/ast-dump-aarch64-sve-types.c b/clang/test/AST/ast-dump-aarch64-sve-types.c index dd14868c42b9b..b5a0b00b49280 100644 --- a/clang/test/AST/ast-dump-aarch64-sve-types.c +++ b/clang/test/AST/ast-dump-aarch64-sve-types.c @@ -42,8 +42,8 @@ // CHECK: TypedefDecl {{.*}} implicit __SVFloat64_t '__SVFloat64_t' // CHECK-NEXT: -BuiltinType {{.*}} '__SVFloat64_t' -// CHECK: TypedefDecl {{.*}} implicit __SVBFloat16_t '__SVBFloat16_t' -// CHECK-NEXT: -BuiltinType {{.*}} '__SVBFloat16_t' +// CHECK: TypedefDecl {{.*}} implicit __SVBfloat16_t '__SVBfloat16_t' +// CHECK-NEXT: -BuiltinType {{.*}} '__SVBfloat16_t' // CHECK: TypedefDecl {{.*}} implicit __SVBool_t '__SVBool_t' // CHECK-NEXT: -BuiltinType {{.*}} '__SVBool_t' diff --git a/clang/test/AST/ast-dump-attr.cpp b/clang/test/AST/ast-dump-attr.cpp index 8fd4a8f3a54c6..f5a7481571421 100644 --- a/clang/test/AST/ast-dump-attr.cpp +++ b/clang/test/AST/ast-dump-attr.cpp @@ -146,17 +146,17 @@ struct C { char a[16]; }; // CHECK: ClassTemplateSpecializationDecl {{.*}} struct my_union // CHECK: CXXRecordDecl {{.*}} implicit struct my_union // CHECK: FieldDecl {{.*}} buffer 'char[1024]' -// CHECK-NEXT: AlignedAttr {{.*}} alignas 'TestAligns::A':'TestAligns::A' -// CHECK-NEXT: AlignedAttr {{.*}} alignas 'TestAligns::B':'TestAligns::B' -// CHECK-NEXT: AlignedAttr {{.*}} alignas 'TestAligns::C':'TestAligns::C' +// CHECK-NEXT: AlignedAttr {{.*}} alignas 'TestAligns::A' +// CHECK-NEXT: AlignedAttr {{.*}} alignas 'TestAligns::B' +// CHECK-NEXT: AlignedAttr {{.*}} alignas 'TestAligns::C' my_union my_union_val; // CHECK: ClassTemplateSpecializationDecl {{.*}} struct my_union2 // CHECK: CXXRecordDecl {{.*}} implicit struct my_union2 // CHECK: FieldDecl {{.*}} buffer 'char[1024]' -// CHECK-NEXT: AlignedAttr {{.*}} _Alignas 'TestAligns::A':'TestAligns::A' -// CHECK-NEXT: AlignedAttr {{.*}} _Alignas 'TestAligns::B':'TestAligns::B' -// CHECK-NEXT: AlignedAttr {{.*}} _Alignas 'TestAligns::C':'TestAligns::C' +// CHECK-NEXT: AlignedAttr {{.*}} _Alignas 'TestAligns::A' +// CHECK-NEXT: AlignedAttr {{.*}} _Alignas 'TestAligns::B' +// CHECK-NEXT: AlignedAttr {{.*}} _Alignas 'TestAligns::C' my_union2 my_union2_val; } // namespace TestAligns diff --git a/clang/test/AST/ast-dump-decl-json.c b/clang/test/AST/ast-dump-decl-json.c index 55b918afaab5d..7f53cda5020b5 100644 --- a/clang/test/AST/ast-dump-decl-json.c +++ b/clang/test/AST/ast-dump-decl-json.c @@ -1351,7 +1351,6 @@ void testParmVarDecl(int TestParmVarDecl); // CHECK-NEXT: "isUsed": true, // CHECK-NEXT: "name": "x", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "enum Enum", // CHECK-NEXT: "qualType": "enum Enum" // CHECK-NEXT: } // CHECK-NEXT: }, @@ -1424,7 +1423,6 @@ void testParmVarDecl(int TestParmVarDecl); // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "enum Enum", // CHECK-NEXT: "qualType": "enum Enum" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", @@ -1446,7 +1444,6 @@ void testParmVarDecl(int TestParmVarDecl); // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "enum Enum", // CHECK-NEXT: "qualType": "enum Enum" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -1455,7 +1452,6 @@ void testParmVarDecl(int TestParmVarDecl); // CHECK-NEXT: "kind": "ParmVarDecl", // CHECK-NEXT: "name": "x", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "enum Enum", // CHECK-NEXT: "qualType": "enum Enum" // CHECK-NEXT: } // CHECK-NEXT: } diff --git a/clang/test/AST/ast-dump-decl-json.m b/clang/test/AST/ast-dump-decl-json.m index 9d82c6696cb52..f7067ac0d3b77 100644 --- a/clang/test/AST/ast-dump-decl-json.m +++ b/clang/test/AST/ast-dump-decl-json.m @@ -911,7 +911,6 @@ void f(void) { // CHECK-NEXT: }, // CHECK-NEXT: "name": "T", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: } diff --git a/clang/test/AST/ast-dump-decl.cpp b/clang/test/AST/ast-dump-decl.cpp index 017e640aeaea6..d74aa9045532e 100644 --- a/clang/test/AST/ast-dump-decl.cpp +++ b/clang/test/AST/ast-dump-decl.cpp @@ -248,19 +248,19 @@ namespace testFunctionTemplateDecl { // CHECK-NEXT: | |-TemplateArgument type 'testFunctionTemplateDecl::A' // CHECK-NEXT: | | `-RecordType 0{{.+}} 'testFunctionTemplateDecl::A' // CHECK-NEXT: | | `-CXXRecord 0x{{.+}} 'A' - // CHECK-NEXT: | |-ParmVarDecl 0x{{.+}} col:51 'testFunctionTemplateDecl::A':'testFunctionTemplateDecl::A' + // CHECK-NEXT: | |-ParmVarDecl 0x{{.+}} col:51 'testFunctionTemplateDecl::A' // CHECK-NEXT: | `-CompoundStmt 0x{{.+}} // CHECK-NEXT: |-Function 0x{{.+}} 'TestFunctionTemplate' 'void (B)' // CHECK-NEXT: |-FunctionDecl 0x{{.+}} col:29 TestFunctionTemplate 'void (testFunctionTemplateDecl::C)' // CHECK-NEXT: | |-TemplateArgument type 'testFunctionTemplateDecl::C' // CHECK-NEXT: | | `-RecordType 0{{.+}} 'testFunctionTemplateDecl::C' // CHECK-NEXT: | | `-CXXRecord 0x{{.+}} 'C' - // CHECK-NEXT: | `-ParmVarDecl 0x{{.+}} col:51 'testFunctionTemplateDecl::C':'testFunctionTemplateDecl::C' + // CHECK-NEXT: | `-ParmVarDecl 0x{{.+}} col:51 'testFunctionTemplateDecl::C' // CHECK-NEXT: `-FunctionDecl 0x{{.+}} col:29 TestFunctionTemplate 'void (testFunctionTemplateDecl::D)' // CHECK-NEXT: |-TemplateArgument type 'testFunctionTemplateDecl::D' // CHECK-NEXT: | `-RecordType 0{{.+}} 'testFunctionTemplateDecl::D' // CHECK-NEXT: | `-CXXRecord 0x{{.+}} 'D' - // CHECK-NEXT: |-ParmVarDecl 0x{{.+}} col:51 'testFunctionTemplateDecl::D':'testFunctionTemplateDecl::D' + // CHECK-NEXT: |-ParmVarDecl 0x{{.+}} col:51 'testFunctionTemplateDecl::D' // CHECK-NEXT: `-CompoundStmt 0x{{.+}} // CHECK: FunctionDecl 0x{{.+}} prev 0x{{.+}} <{{.+}}:[[@LINE-32]]:3, col:41> col:19 TestFunctionTemplate 'void (B)' @@ -500,7 +500,7 @@ namespace testCanonicalTemplate { // CHECK-NEXT: |-TemplateArgument type 'testCanonicalTemplate::A'{{$}} // CHECK-NEXT: | `-RecordType 0x{{.+}} 'testCanonicalTemplate::A'{{$}} // CHECK-NEXT: | `-CXXRecord 0x{{.+}} 'A'{{$}} - // CHECK-NEXT: `-ParmVarDecl 0x{{.*}} col:51 'testCanonicalTemplate::A':'testCanonicalTemplate::A'{{$}} + // CHECK-NEXT: `-ParmVarDecl 0x{{.*}} col:51 'testCanonicalTemplate::A'{{$}} // CHECK: FunctionTemplateDecl 0x{{.+}} prev 0x{{.+}} <{{.+}}:[[@LINE-12]]:3, col:51> col:29 TestFunctionTemplate{{$}} // CHECK-NEXT: |-TemplateTypeParmDecl 0x{{.+}} col:21 referenced typename depth 0 index 0 T{{$}} @@ -613,15 +613,15 @@ namespace testCanonicalTemplate { // CHECK: VarTemplateDecl 0x{{.+}} <{{.+}}:[[@LINE-11]]:7, col:43> col:43 TestVarTemplate{{$}} // CHECK-NEXT: |-TemplateTypeParmDecl 0x{{.+}} col:25 referenced typename depth 0 index 0 T{{$}} // CHECK-NEXT: |-VarDecl 0x{{.+}} col:43 TestVarTemplate 'const T' static{{$}} - // CHECK-NEXT: |-VarTemplateSpecializationDecl 0x{{.+}} parent 0x{{.+}} prev 0x{{.+}} col:14 referenced TestVarTemplate 'const int':'const int' implicit_instantiation cinit{{$}} + // CHECK-NEXT: |-VarTemplateSpecializationDecl 0x{{.+}} parent 0x{{.+}} prev 0x{{.+}} col:14 referenced TestVarTemplate 'const int' implicit_instantiation cinit{{$}} // CHECK-NEXT: | |-NestedNameSpecifier TypeSpec 'testCanonicalTemplate::S'{{$}} // CHECK-NEXT: | |-TemplateArgument type 'int'{{$}} // CHECK-NEXT: | | `-BuiltinType 0x{{.+}} 'int'{{$}} - // CHECK-NEXT: | `-InitListExpr 0x{{.+}} 'int':'int'{{$}} - // CHECK-NEXT: `-VarTemplateSpecializationDecl 0x{{.+}} col:43 referenced TestVarTemplate 'const int':'const int' implicit_instantiation static{{$}} + // CHECK-NEXT: | `-InitListExpr 0x{{.+}} 'int'{{$}} + // CHECK-NEXT: `-VarTemplateSpecializationDecl 0x{{.+}} col:43 referenced TestVarTemplate 'const int' implicit_instantiation static{{$}} // CHECK-NEXT: `-TemplateArgument type 'int'{{$}} - // CHECK: VarTemplateSpecializationDecl 0x{{.+}} <{{.+}}:[[@LINE-22]]:28, col:43> col:43 referenced TestVarTemplate 'const int':'const int' implicit_instantiation static{{$}} + // CHECK: VarTemplateSpecializationDecl 0x{{.+}} <{{.+}}:[[@LINE-22]]:28, col:43> col:43 referenced TestVarTemplate 'const int' implicit_instantiation static{{$}} // CHECK-NEXT:`-TemplateArgument type 'int'{{$}} // CHECK-NEXT: `-BuiltinType 0x{{.+}} 'int'{{$}} @@ -630,14 +630,14 @@ namespace testCanonicalTemplate { // CHECK-NEXT: |-VarDecl 0x{{.+}} parent 0x{{.+}} prev 0x{{.+}} col:14 TestVarTemplate 'const T' cinit{{$}} // CHECK-NEXT: | |-NestedNameSpecifier TypeSpec 'testCanonicalTemplate::S'{{$}} // CHECK-NEXT: | `-InitListExpr 0x{{.+}} 'void'{{$}} - // CHECK-NEXT: |-VarTemplateSpecialization 0x{{.+}} 'TestVarTemplate' 'const int':'const int'{{$}} - // CHECK-NEXT: `-VarTemplateSpecialization 0x{{.+}} 'TestVarTemplate' 'const int':'const int'{{$}} + // CHECK-NEXT: |-VarTemplateSpecialization 0x{{.+}} 'TestVarTemplate' 'const int'{{$}} + // CHECK-NEXT: `-VarTemplateSpecialization 0x{{.+}} 'TestVarTemplate' 'const int'{{$}} - // CHECK: VarTemplateSpecializationDecl 0x{{.+}} parent 0x{{.+}} prev 0x{{.+}} <{{.+}}:[[@LINE-31]]:3, col:34> col:14 referenced TestVarTemplate 'const int':'const int' implicit_instantiation cinit{{$}} + // CHECK: VarTemplateSpecializationDecl 0x{{.+}} parent 0x{{.+}} prev 0x{{.+}} <{{.+}}:[[@LINE-31]]:3, col:34> col:14 referenced TestVarTemplate 'const int' implicit_instantiation cinit{{$}} // CHECK-NEXT: |-NestedNameSpecifier TypeSpec 'testCanonicalTemplate::S'{{$}} // CHECK-NEXT: |-TemplateArgument type 'int'{{$}} // CHECK-NEXT: | `-BuiltinType 0x{{.+}} 'int'{{$}} - // CHECK-NEXT: `-InitListExpr 0x{{.+}} 'int':'int'{{$}} + // CHECK-NEXT: `-InitListExpr 0x{{.+}} 'int'{{$}} } template @@ -856,7 +856,7 @@ namespace TestConstexprVariableTemplateWithInitializer { inline constexpr in_place_type_t<_Tp> in_place_type{}; // CHECK: -VarTemplateDecl 0x{{.+}} col:41 in_place_type{{$}} // CHECK-NEXT: |-TemplateTypeParmDecl 0x{{.+}} col:22 referenced typename depth 0 index 0 _Tp{{$}} - // CHECK-NEXT: `-VarDecl 0x{{.+}} col:41 in_place_type 'const in_place_type_t<_Tp>':'const in_place_type_t<_Tp>' inline constexpr listinit{{$}} + // CHECK-NEXT: `-VarDecl 0x{{.+}} col:41 in_place_type 'const in_place_type_t<_Tp>' inline constexpr listinit{{$}} // CHECK-NEXT: `-InitListExpr 0x{{.+}} 'void'{{$}} template constexpr T call_init(0); diff --git a/clang/test/AST/ast-dump-decl.m b/clang/test/AST/ast-dump-decl.m index 0b259d522645d..5f09b6042f409 100644 --- a/clang/test/AST/ast-dump-decl.m +++ b/clang/test/AST/ast-dump-decl.m @@ -94,7 +94,7 @@ @interface TestGenericInterface : A

{ // CHECK: ObjCInterfaceDecl{{.*}} TestGenericInterface // CHECK-NEXT: -super ObjCInterface {{.+}} 'A' // CHECK-NEXT: -ObjCProtocol {{.+}} 'P' -// CHECK-NEXT: -ObjCTypeParamDecl {{.+}} col:33 T 'id':'id' +// CHECK-NEXT: -ObjCTypeParamDecl {{.+}} col:33 T 'id' @implementation TestObjCClass (TestObjCCategoryDecl) - (void) bar { diff --git a/clang/test/AST/ast-dump-expr-json.c b/clang/test/AST/ast-dump-expr-json.c index 14238283af3f2..e910864eeed65 100644 --- a/clang/test/AST/ast-dump-expr-json.c +++ b/clang/test/AST/ast-dump-expr-json.c @@ -4080,7 +4080,6 @@ void PrimaryExpressions(int a) { // CHECK-NEXT: "isUsed": true, // CHECK-NEXT: "name": "b", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "struct S", // CHECK-NEXT: "qualType": "struct S" // CHECK-NEXT: } // CHECK-NEXT: }, @@ -4530,7 +4529,6 @@ void PrimaryExpressions(int a) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "struct S", // CHECK-NEXT: "qualType": "struct S" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -4539,7 +4537,6 @@ void PrimaryExpressions(int a) { // CHECK-NEXT: "kind": "ParmVarDecl", // CHECK-NEXT: "name": "b", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "struct S", // CHECK-NEXT: "qualType": "struct S" // CHECK-NEXT: } // CHECK-NEXT: } @@ -4817,7 +4814,6 @@ void PrimaryExpressions(int a) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "struct S", // CHECK-NEXT: "qualType": "struct S" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", @@ -4839,7 +4835,6 @@ void PrimaryExpressions(int a) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "struct S", // CHECK-NEXT: "qualType": "struct S" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -4860,7 +4855,6 @@ void PrimaryExpressions(int a) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "struct S", // CHECK-NEXT: "qualType": "struct S" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", diff --git a/clang/test/AST/ast-dump-expr-json.cpp b/clang/test/AST/ast-dump-expr-json.cpp index eac0346d64319..0fb07b0b434cc 100644 --- a/clang/test/AST/ast-dump-expr-json.cpp +++ b/clang/test/AST/ast-dump-expr-json.cpp @@ -325,7 +325,6 @@ void TestNonADLCall3() { // CHECK-NEXT: "isUsed": true, // CHECK-NEXT: "name": "obj1", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "S", // CHECK-NEXT: "qualType": "S" // CHECK-NEXT: } // CHECK-NEXT: }, @@ -462,7 +461,6 @@ void TestNonADLCall3() { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "S", // CHECK-NEXT: "qualType": "S" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -471,7 +469,6 @@ void TestNonADLCall3() { // CHECK-NEXT: "kind": "ParmVarDecl", // CHECK-NEXT: "name": "obj1", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "S", // CHECK-NEXT: "qualType": "S" // CHECK-NEXT: } // CHECK-NEXT: } @@ -733,7 +730,6 @@ void TestNonADLCall3() { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "S", // CHECK-NEXT: "qualType": "S" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -742,7 +738,6 @@ void TestNonADLCall3() { // CHECK-NEXT: "kind": "ParmVarDecl", // CHECK-NEXT: "name": "obj1", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "S", // CHECK-NEXT: "qualType": "S" // CHECK-NEXT: } // CHECK-NEXT: } @@ -2539,7 +2534,6 @@ void TestNonADLCall3() { // CHECK-NEXT: "isUsed": true, // CHECK-NEXT: "name": "a", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "S", // CHECK-NEXT: "qualType": "S" // CHECK-NEXT: } // CHECK-NEXT: }, @@ -2672,7 +2666,6 @@ void TestNonADLCall3() { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "S", // CHECK-NEXT: "qualType": "S" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -2681,7 +2674,6 @@ void TestNonADLCall3() { // CHECK-NEXT: "kind": "ParmVarDecl", // CHECK-NEXT: "name": "a", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "S", // CHECK-NEXT: "qualType": "S" // CHECK-NEXT: } // CHECK-NEXT: } @@ -2848,7 +2840,6 @@ void TestNonADLCall3() { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int", // CHECK-NEXT: "qualType": "int" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", @@ -2948,7 +2939,6 @@ void TestNonADLCall3() { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "float", // CHECK-NEXT: "qualType": "float" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", @@ -2992,7 +2982,6 @@ void TestNonADLCall3() { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "S", // CHECK-NEXT: "qualType": "S" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -3001,7 +2990,6 @@ void TestNonADLCall3() { // CHECK-NEXT: "kind": "ParmVarDecl", // CHECK-NEXT: "name": "a", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "S", // CHECK-NEXT: "qualType": "S" // CHECK-NEXT: } // CHECK-NEXT: } @@ -3169,7 +3157,6 @@ void TestNonADLCall3() { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "S", // CHECK-NEXT: "qualType": "S" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -3178,7 +3165,6 @@ void TestNonADLCall3() { // CHECK-NEXT: "kind": "ParmVarDecl", // CHECK-NEXT: "name": "a", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "S", // CHECK-NEXT: "qualType": "S" // CHECK-NEXT: } // CHECK-NEXT: } @@ -3247,7 +3233,6 @@ void TestNonADLCall3() { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "S", // CHECK-NEXT: "qualType": "S" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -3256,7 +3241,6 @@ void TestNonADLCall3() { // CHECK-NEXT: "kind": "ParmVarDecl", // CHECK-NEXT: "name": "a", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "S", // CHECK-NEXT: "qualType": "S" // CHECK-NEXT: } // CHECK-NEXT: } @@ -3500,7 +3484,6 @@ void TestNonADLCall3() { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "S", // CHECK-NEXT: "qualType": "S" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -3509,7 +3492,6 @@ void TestNonADLCall3() { // CHECK-NEXT: "kind": "ParmVarDecl", // CHECK-NEXT: "name": "a", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "S", // CHECK-NEXT: "qualType": "S" // CHECK-NEXT: } // CHECK-NEXT: } @@ -3537,7 +3519,6 @@ void TestNonADLCall3() { // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", // CHECK-NEXT: "typeArg": { -// CHECK-NEXT: "desugaredQualType": "S", // CHECK-NEXT: "qualType": "S" // CHECK-NEXT: } // CHECK-NEXT: }, @@ -3562,11 +3543,9 @@ void TestNonADLCall3() { // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", // CHECK-NEXT: "typeArg": { -// CHECK-NEXT: "desugaredQualType": "const volatile S", // CHECK-NEXT: "qualType": "const volatile S" // CHECK-NEXT: }, // CHECK-NEXT: "adjustedTypeArg": { -// CHECK-NEXT: "desugaredQualType": "S", // CHECK-NEXT: "qualType": "S" // CHECK-NEXT: } // CHECK-NEXT: } @@ -6591,7 +6570,6 @@ void TestNonADLCall3() { // CHECK-NEXT: }, // CHECK-NEXT: "isImplicit": true, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int", // CHECK-NEXT: "qualType": "int" // CHECK-NEXT: } // CHECK-NEXT: } @@ -7858,7 +7836,6 @@ void TestNonADLCall3() { // CHECK-NEXT: "isUsed": true, // CHECK-NEXT: "name": "x", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "NS::X", // CHECK-NEXT: "qualType": "NS::X" // CHECK-NEXT: }, // CHECK-NEXT: "init": "call", @@ -7879,7 +7856,6 @@ void TestNonADLCall3() { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "NS::X", // CHECK-NEXT: "qualType": "NS::X" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", @@ -8030,7 +8006,6 @@ void TestNonADLCall3() { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "NS::X", // CHECK-NEXT: "qualType": "NS::X" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -8039,7 +8014,6 @@ void TestNonADLCall3() { // CHECK-NEXT: "kind": "VarDecl", // CHECK-NEXT: "name": "x", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "NS::X", // CHECK-NEXT: "qualType": "NS::X" // CHECK-NEXT: } // CHECK-NEXT: } @@ -8139,7 +8113,6 @@ void TestNonADLCall3() { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "NS::X", // CHECK-NEXT: "qualType": "NS::X" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", @@ -8187,7 +8160,6 @@ void TestNonADLCall3() { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "NS::X", // CHECK-NEXT: "qualType": "NS::X" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -8196,7 +8168,6 @@ void TestNonADLCall3() { // CHECK-NEXT: "kind": "VarDecl", // CHECK-NEXT: "name": "x", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "NS::X", // CHECK-NEXT: "qualType": "NS::X" // CHECK-NEXT: } // CHECK-NEXT: } @@ -8299,7 +8270,6 @@ void TestNonADLCall3() { // CHECK-NEXT: "isUsed": true, // CHECK-NEXT: "name": "x", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "NS::X", // CHECK-NEXT: "qualType": "NS::X" // CHECK-NEXT: }, // CHECK-NEXT: "init": "call", @@ -8320,7 +8290,6 @@ void TestNonADLCall3() { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "NS::X", // CHECK-NEXT: "qualType": "NS::X" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", @@ -8470,7 +8439,6 @@ void TestNonADLCall3() { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "NS::X", // CHECK-NEXT: "qualType": "NS::X" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -8479,7 +8447,6 @@ void TestNonADLCall3() { // CHECK-NEXT: "kind": "VarDecl", // CHECK-NEXT: "name": "x", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "NS::X", // CHECK-NEXT: "qualType": "NS::X" // CHECK-NEXT: } // CHECK-NEXT: } @@ -8582,7 +8549,6 @@ void TestNonADLCall3() { // CHECK-NEXT: "isUsed": true, // CHECK-NEXT: "name": "x", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "NS::X", // CHECK-NEXT: "qualType": "NS::X" // CHECK-NEXT: }, // CHECK-NEXT: "init": "call", @@ -8603,7 +8569,6 @@ void TestNonADLCall3() { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "NS::X", // CHECK-NEXT: "qualType": "NS::X" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", @@ -8799,7 +8764,6 @@ void TestNonADLCall3() { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "NS::X", // CHECK-NEXT: "qualType": "NS::X" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -8808,7 +8772,6 @@ void TestNonADLCall3() { // CHECK-NEXT: "kind": "VarDecl", // CHECK-NEXT: "name": "x", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "NS::X", // CHECK-NEXT: "qualType": "NS::X" // CHECK-NEXT: } // CHECK-NEXT: } @@ -8908,7 +8871,6 @@ void TestNonADLCall3() { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "NS::X", // CHECK-NEXT: "qualType": "NS::X" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", @@ -8956,7 +8918,6 @@ void TestNonADLCall3() { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "NS::X", // CHECK-NEXT: "qualType": "NS::X" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -8965,7 +8926,6 @@ void TestNonADLCall3() { // CHECK-NEXT: "kind": "VarDecl", // CHECK-NEXT: "name": "x", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "NS::X", // CHECK-NEXT: "qualType": "NS::X" // CHECK-NEXT: } // CHECK-NEXT: } diff --git a/clang/test/AST/ast-dump-expr-json.m b/clang/test/AST/ast-dump-expr-json.m index bbde4451f9fe3..3c502c0496308 100644 --- a/clang/test/AST/ast-dump-expr-json.m +++ b/clang/test/AST/ast-dump-expr-json.m @@ -764,7 +764,6 @@ void TestObjCBoolLiteral(void) { // CHECK-NEXT: "isUsed": true, // CHECK-NEXT: "name": "Obj", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: } @@ -825,7 +824,6 @@ void TestObjCBoolLiteral(void) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: }, @@ -848,7 +846,6 @@ void TestObjCBoolLiteral(void) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: }, @@ -858,7 +855,6 @@ void TestObjCBoolLiteral(void) { // CHECK-NEXT: "kind": "ParmVarDecl", // CHECK-NEXT: "name": "Obj", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: } @@ -2036,7 +2032,6 @@ void TestObjCBoolLiteral(void) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: }, @@ -2468,7 +2463,6 @@ void TestObjCBoolLiteral(void) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: }, @@ -2490,7 +2484,6 @@ void TestObjCBoolLiteral(void) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: }, @@ -2678,7 +2671,6 @@ void TestObjCBoolLiteral(void) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: }, @@ -2700,7 +2692,6 @@ void TestObjCBoolLiteral(void) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: }, @@ -2864,7 +2855,6 @@ void TestObjCBoolLiteral(void) { // CHECK-NEXT: "isUsed": true, // CHECK-NEXT: "name": "i", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: }, @@ -2886,7 +2876,6 @@ void TestObjCBoolLiteral(void) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: }, @@ -3163,7 +3152,6 @@ void TestObjCBoolLiteral(void) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: }, @@ -3312,7 +3300,6 @@ void TestObjCBoolLiteral(void) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: }, @@ -3788,7 +3775,6 @@ void TestObjCBoolLiteral(void) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: }, @@ -3810,7 +3796,6 @@ void TestObjCBoolLiteral(void) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: }, @@ -3998,7 +3983,6 @@ void TestObjCBoolLiteral(void) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: }, @@ -4020,7 +4004,6 @@ void TestObjCBoolLiteral(void) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: }, @@ -4113,7 +4096,6 @@ void TestObjCBoolLiteral(void) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: }, @@ -4208,7 +4190,6 @@ void TestObjCBoolLiteral(void) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: }, @@ -4231,7 +4212,6 @@ void TestObjCBoolLiteral(void) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: }, @@ -4241,7 +4221,6 @@ void TestObjCBoolLiteral(void) { // CHECK-NEXT: "kind": "VarDecl", // CHECK-NEXT: "name": "i", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: } @@ -4263,7 +4242,6 @@ void TestObjCBoolLiteral(void) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: }, @@ -4584,7 +4562,6 @@ void TestObjCBoolLiteral(void) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: }, @@ -4681,7 +4658,6 @@ void TestObjCBoolLiteral(void) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: }, diff --git a/clang/test/AST/ast-dump-expr.c b/clang/test/AST/ast-dump-expr.c index 8605cd4bbaa16..959d61ec9794b 100644 --- a/clang/test/AST/ast-dump-expr.c +++ b/clang/test/AST/ast-dump-expr.c @@ -259,7 +259,7 @@ void PostfixOperators(int *a, struct S b, struct S *c) { b.a; // CHECK: ImplicitCastExpr // CHECK-NEXT: MemberExpr 0x{{[^ ]*}} 'int' lvalue .a 0x{{[^ ]*}} - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'struct S':'struct S' lvalue ParmVar 0x{{[^ ]*}} 'b' 'struct S':'struct S' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'struct S' lvalue ParmVar 0x{{[^ ]*}} 'b' 'struct S' c->a; // CHECK: ImplicitCastExpr @@ -280,8 +280,8 @@ void PostfixOperators(int *a, struct S b, struct S *c) { (struct S){1}; // CHECK: ImplicitCastExpr - // CHECK-NEXT: CompoundLiteralExpr 0x{{[^ ]*}} 'struct S':'struct S' lvalue - // CHECK-NEXT: InitListExpr 0x{{[^ ]*}} 'struct S':'struct S' + // CHECK-NEXT: CompoundLiteralExpr 0x{{[^ ]*}} 'struct S' lvalue + // CHECK-NEXT: InitListExpr 0x{{[^ ]*}} 'struct S' // CHECK-NEXT: IntegerLiteral 0x{{[^ ]*}} 'int' 1 } diff --git a/clang/test/AST/ast-dump-expr.cpp b/clang/test/AST/ast-dump-expr.cpp index 1c07aa066462b..69e65e22d61d0 100644 --- a/clang/test/AST/ast-dump-expr.cpp +++ b/clang/test/AST/ast-dump-expr.cpp @@ -59,7 +59,7 @@ void Throw() { void PointerToMember(S obj1, S *obj2, int S::* data, void (S::*call)(int)) { obj1.*data; // CHECK: BinaryOperator 0x{{[^ ]*}} 'int' lvalue '.*' - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'S':'S' lvalue ParmVar 0x{{[^ ]*}} 'obj1' 'S':'S' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'S' lvalue ParmVar 0x{{[^ ]*}} 'obj1' 'S' // CHECK-NEXT: ImplicitCastExpr // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int S::*' lvalue ParmVar 0x{{[^ ]*}} 'data' 'int S::*' @@ -74,7 +74,7 @@ void PointerToMember(S obj1, S *obj2, int S::* data, void (S::*call)(int)) { // CHECK: CXXMemberCallExpr 0x{{[^ ]*}} 'void' // CHECK-NEXT: ParenExpr 0x{{[^ ]*}} '' // CHECK-NEXT: BinaryOperator 0x{{[^ ]*}} '' '.*' - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'S':'S' lvalue ParmVar 0x{{[^ ]*}} 'obj1' 'S':'S' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'S' lvalue ParmVar 0x{{[^ ]*}} 'obj1' 'S' // CHECK-NEXT: ImplicitCastExpr // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'void (S::*)(int)' lvalue ParmVar 0x{{[^ ]*}} 'call' 'void (S::*)(int)' // CHECK-NEXT: IntegerLiteral 0x{{[^ ]*}} 'int' 12 @@ -178,7 +178,7 @@ void PostfixExpressions(S a, S *p, U *r) { a.func(0); // CHECK: CXXMemberCallExpr 0x{{[^ ]*}} 'void' // CHECK-NEXT: MemberExpr 0x{{[^ ]*}} '' .func 0x{{[^ ]*}} - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'S':'S' lvalue ParmVar 0x{{[^ ]*}} 'a' 'S':'S' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'S' lvalue ParmVar 0x{{[^ ]*}} 'a' 'S' // CHECK-NEXT: IntegerLiteral 0x{{[^ ]*}} 'int' 0 p->func(0); @@ -190,16 +190,16 @@ void PostfixExpressions(S a, S *p, U *r) { // FIXME: there is no mention that this used the template keyword. p->template foo(); - // CHECK: CXXMemberCallExpr 0x{{[^ ]*}} 'int':'int' + // CHECK: CXXMemberCallExpr 0x{{[^ ]*}} 'int' // CHECK-NEXT: MemberExpr 0x{{[^ ]*}} '' ->foo 0x{{[^ ]*}} // CHECK-NEXT: ImplicitCastExpr // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'S *' lvalue ParmVar 0x{{[^ ]*}} 'p' 'S *' // FIXME: there is no mention that this used the template keyword. a.template foo(); - // CHECK: CXXMemberCallExpr 0x{{[^ ]*}} 'float':'float' + // CHECK: CXXMemberCallExpr 0x{{[^ ]*}} 'float' // CHECK-NEXT: MemberExpr 0x{{[^ ]*}} '' .foo 0x{{[^ ]*}} - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'S':'S' lvalue ParmVar 0x{{[^ ]*}} 'a' 'S':'S' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'S' lvalue ParmVar 0x{{[^ ]*}} 'a' 'S' p->~S(); // CHECK: CXXMemberCallExpr 0x{{[^ ]*}} 'void' @@ -210,14 +210,14 @@ void PostfixExpressions(S a, S *p, U *r) { a.~S(); // CHECK: CXXMemberCallExpr 0x{{[^ ]*}} 'void' // CHECK-NEXT: MemberExpr 0x{{[^ ]*}} '' .~S 0x{{[^ ]*}} - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'S':'S' lvalue ParmVar 0x{{[^ ]*}} 'a' 'S':'S' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'S' lvalue ParmVar 0x{{[^ ]*}} 'a' 'S' // FIXME: there seems to be no way to distinguish the construct below from // the construct above. a.~decltype(a)(); // CHECK: CXXMemberCallExpr 0x{{[^ ]*}} 'void' // CHECK-NEXT: MemberExpr 0x{{[^ ]*}} '' .~S 0x{{[^ ]*}} - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'S':'S' lvalue ParmVar 0x{{[^ ]*}} 'a' 'S':'S' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'S' lvalue ParmVar 0x{{[^ ]*}} 'a' 'S' // FIXME: similarly, there is no way to distinguish the construct below from // the p->~S() case. @@ -233,13 +233,13 @@ void PostfixExpressions(S a, S *p, U *r) { r->template U::~U(); // CHECK: CXXMemberCallExpr 0x{{[^ ]*}} 'void' // CHECK-NEXT: MemberExpr 0x{{[^ ]*}} '' ->~U 0x{{[^ ]*}} - // CHECK-NEXT: NestedNameSpecifier TypeSpecWithTemplate 'U':'U' + // CHECK-NEXT: NestedNameSpecifier TypeSpecWithTemplate 'U' // CHECK-NEXT: ImplicitCastExpr // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'U *' lvalue ParmVar 0x{{[^ ]*}} 'r' 'U *' typeid(a); // CHECK: CXXTypeidExpr 0x{{[^ ]*}} 'const std::type_info' lvalue - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'S':'S' lvalue ParmVar 0x{{[^ ]*}} 'a' 'S':'S' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'S' lvalue ParmVar 0x{{[^ ]*}} 'a' 'S' // FIXME: no type information is printed for the argument. typeid(S); @@ -448,7 +448,7 @@ void PrimaryExpressions(Ts... a) { // CHECK-NEXT: CXXMethodDecl 0x{{[^ ]*}} col:3 operator() 'auto () const -> auto' inline // CHECK-NEXT: CompoundStmt // CHECK-NEXT: FieldDecl 0x{{[^ ]*}} col:4 implicit 'Ts...' - // CHECK-NEXT: FieldDecl 0x{{[^ ]*}} col:10 implicit 'int':'int' + // CHECK-NEXT: FieldDecl 0x{{[^ ]*}} col:10 implicit 'int' // CHECK-NEXT: ParenListExpr 0x{{[^ ]*}} 'NULL TYPE' // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'Ts' lvalue ParmVar 0x{{[^ ]*}} 'a' 'Ts...' // CHECK-NEXT: IntegerLiteral 0x{{[^ ]*}} 'int' 12 diff --git a/clang/test/AST/ast-dump-fpfeatures.cpp b/clang/test/AST/ast-dump-fpfeatures.cpp index 9228b6e7238be..da0011602a728 100644 --- a/clang/test/AST/ast-dump-fpfeatures.cpp +++ b/clang/test/AST/ast-dump-fpfeatures.cpp @@ -140,7 +140,7 @@ float func_15(float x, float y) { // CHECK: FunctionDecl {{.*}} func_14 'float (float, float)' // CHECK: CompoundStmt // CHECK-NEXT: ReturnStmt -// CHECK-NEXT: BinaryOperator {{.*}} 'float':'float' '+' ConstRoundingMode=towardzero +// CHECK-NEXT: BinaryOperator {{.*}} 'float' '+' ConstRoundingMode=towardzero float func_16(float x, float y) { #pragma STDC FENV_ROUND FE_TOWARDZERO diff --git a/clang/test/AST/ast-dump-funcs.cpp b/clang/test/AST/ast-dump-funcs.cpp index 7d47893d4596d..61fb5d4eb654e 100644 --- a/clang/test/AST/ast-dump-funcs.cpp +++ b/clang/test/AST/ast-dump-funcs.cpp @@ -32,7 +32,7 @@ struct S { // CHECK-NEXT: CXXCtorInitializer Field 0x{{[^ ]*}} 'j' 'int' // CHECK-NEXT: IntegerLiteral 0x{{[^ ]*}} 'int' 0 // CHECK-NEXT: CXXCtorInitializer Field 0x{{[^ ]*}} 'r' 'R' - // CHECK-NEXT: CXXConstructExpr 0x{{[^ ]*}} 'R':'R' 'void () noexcept' + // CHECK-NEXT: CXXConstructExpr 0x{{[^ ]*}} 'R' 'void () noexcept' // CHECK-NEXT: CompoundStmt 0x{{[^ ]*}} void a(); diff --git a/clang/test/AST/ast-dump-functionprototype.cpp b/clang/test/AST/ast-dump-functionprototype.cpp index 4ba57bd5ace0e..d831e5da2d320 100644 --- a/clang/test/AST/ast-dump-functionprototype.cpp +++ b/clang/test/AST/ast-dump-functionprototype.cpp @@ -5,7 +5,7 @@ struct B {}; typedef void (type1)() noexcept(10 > 5); -// CHECK: TypedefDecl {{.*}} type1 'void () noexcept(10 > 5)':'void () noexcept(10 > 5)' +// CHECK: TypedefDecl {{.*}} type1 'void () noexcept(10 > 5)' // CHECK-NEXT: `-ParenType {{.*}} // CHECK-NEXT: `-FunctionProtoType {{.*}} 'void () noexcept(10 > 5)' exceptionspec_noexcept_true cdecl // CHECK-NEXT: |-NoexceptExpr: ConstantExpr {{.*}} 'bool' @@ -14,9 +14,9 @@ typedef void (type1)() noexcept(10 > 5); typedef void (type2)() throw(A, B); -// CHECK: TypedefDecl {{.*}} type2 'void () throw(A, B)':'void () throw(A, B)' +// CHECK: TypedefDecl {{.*}} type2 'void () throw(A, B)' // CHECK-NEXT: `-ParenType {{.*}} // CHECK-NEXT: `-FunctionProtoType {{.*}} 'void () throw(A, B)' exceptionspec_dynamic cdecl -// CHECK-NEXT: |-Exceptions: 'A':'A', 'B':'B' +// CHECK-NEXT: |-Exceptions: 'A', 'B' // CHECK-NEXT: `-BuiltinType {{.*}} 'void' diff --git a/clang/test/AST/ast-dump-lambda.cpp b/clang/test/AST/ast-dump-lambda.cpp index 56d09b92df0e6..ef8789cd97d3e 100644 --- a/clang/test/AST/ast-dump-lambda.cpp +++ b/clang/test/AST/ast-dump-lambda.cpp @@ -229,7 +229,7 @@ template void test(Ts... a) { // CHECK-NEXT: | | |-CXXMethodDecl {{.*}} col:3{{( imported)?}} operator() 'auto () const -> auto' inline // CHECK-NEXT: | | | `-CompoundStmt {{.*}} // CHECK-NEXT: | | |-FieldDecl {{.*}} col:4{{( imported)?}} implicit 'Ts...' -// CHECK-NEXT: | | `-FieldDecl {{.*}} col:10{{( imported)?}} implicit 'int':'int' +// CHECK-NEXT: | | `-FieldDecl {{.*}} col:10{{( imported)?}} implicit 'int' // CHECK-NEXT: | |-ParenListExpr {{.*}} 'NULL TYPE' // CHECK-NEXT: | | `-DeclRefExpr {{.*}} 'Ts' lvalue ParmVar {{.*}} 'a' 'Ts...' // CHECK-NEXT: | |-IntegerLiteral {{.*}} 'int' 12 diff --git a/clang/test/AST/ast-dump-objc-arc-json.m b/clang/test/AST/ast-dump-objc-arc-json.m index 5792c8bf58776..86ca28e283a5b 100644 --- a/clang/test/AST/ast-dump-objc-arc-json.m +++ b/clang/test/AST/ast-dump-objc-arc-json.m @@ -22,7 +22,6 @@ id TestCompoundLiteral(id a) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "id", // CHECK-NEXT: "qualType": "id", // CHECK-NEXT: "typeAliasDeclId": "0x{{.*}}" // CHECK-NEXT: }, diff --git a/clang/test/AST/ast-dump-openmp-begin-declare-variant_reference.cpp b/clang/test/AST/ast-dump-openmp-begin-declare-variant_reference.cpp index ef1d2033c5d10..1937a5d1c3eb3 100644 --- a/clang/test/AST/ast-dump-openmp-begin-declare-variant_reference.cpp +++ b/clang/test/AST/ast-dump-openmp-begin-declare-variant_reference.cpp @@ -121,7 +121,7 @@ int test(float &&f, short &&s) { // CHECK-NEXT: | | | `-LValueReferenceType [[ADDR_7:0x[a-z0-9]*]] 'float &' // CHECK-NEXT: | | | `-BuiltinType [[ADDR_8:0x[a-z0-9]*]] 'float' // CHECK-NEXT: | | |-CXXRecordDecl [[ADDR_9:0x[a-z0-9]*]] col:29 implicit struct remove_reference -// CHECK-NEXT: | | `-TypedefDecl [[ADDR_10:0x[a-z0-9]*]] col:67 referenced type 'float':'float' +// CHECK-NEXT: | | `-TypedefDecl [[ADDR_10:0x[a-z0-9]*]] col:67 referenced type 'float' // CHECK-NEXT: | | `-SubstTemplateTypeParmType [[ADDR_11:0x[a-z0-9]*]] 'float' sugar class depth 0 index 0 _Tp // CHECK-NEXT: | | |-ClassTemplateSpecialization [[ADDR_6]] 'remove_reference' // CHECK-NEXT: | | `-BuiltinType [[ADDR_8]] 'float' @@ -137,7 +137,7 @@ int test(float &&f, short &&s) { // CHECK-NEXT: | | `-LValueReferenceType [[ADDR_15:0x[a-z0-9]*]] 'short &' // CHECK-NEXT: | | `-BuiltinType [[ADDR_16:0x[a-z0-9]*]] 'short' // CHECK-NEXT: | |-CXXRecordDecl [[ADDR_17:0x[a-z0-9]*]] col:29 implicit struct remove_reference -// CHECK-NEXT: | `-TypedefDecl [[ADDR_18:0x[a-z0-9]*]] col:67 referenced type 'short':'short' +// CHECK-NEXT: | `-TypedefDecl [[ADDR_18:0x[a-z0-9]*]] col:67 referenced type 'short' // CHECK-NEXT: | `-SubstTemplateTypeParmType [[ADDR_19:0x[a-z0-9]*]] 'short' sugar class depth 0 index 0 _Tp // CHECK-NEXT: | |-ClassTemplateSpecialization [[ADDR_14]] 'remove_reference' // CHECK-NEXT: | `-BuiltinType [[ADDR_16]] 'short' diff --git a/clang/test/AST/ast-dump-openmp-begin-declare-variant_template_1.cpp b/clang/test/AST/ast-dump-openmp-begin-declare-variant_template_1.cpp index 5916958b94625..0dfed6ffa240d 100644 --- a/clang/test/AST/ast-dump-openmp-begin-declare-variant_template_1.cpp +++ b/clang/test/AST/ast-dump-openmp-begin-declare-variant_template_1.cpp @@ -124,14 +124,14 @@ int test() { // CHECK-NEXT: | |-CallExpr [[ADDR_63:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | | |-ImplicitCastExpr [[ADDR_64:0x[a-z0-9]*]] 'int (*)(double)' // CHECK-NEXT: | | | `-DeclRefExpr [[ADDR_65:0x[a-z0-9]*]] 'int (double)' {{.*}}Function [[ADDR_44]] 'also_after' 'int (double)' -// CHECK-NEXT: | | `-CXXFunctionalCastExpr [[ADDR_66:0x[a-z0-9]*]] 'double':'double' functional cast to double -// CHECK-NEXT: | | `-ImplicitCastExpr [[ADDR_67:0x[a-z0-9]*]] 'double':'double' part_of_explicit_cast +// CHECK-NEXT: | | `-CXXFunctionalCastExpr [[ADDR_66:0x[a-z0-9]*]] 'double' functional cast to double +// CHECK-NEXT: | | `-ImplicitCastExpr [[ADDR_67:0x[a-z0-9]*]] 'double' part_of_explicit_cast // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_58]] 'int' 0 // CHECK-NEXT: | `-CallExpr [[ADDR_68:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | |-ImplicitCastExpr [[ADDR_69:0x[a-z0-9]*]] 'int (*)(double)' // CHECK-NEXT: | | `-DeclRefExpr [[ADDR_25]] 'int (double)' Function [[ADDR_26]] 'also_after[implementation={vendor(llvm)}]' 'int (double)' -// CHECK-NEXT: | `-CXXFunctionalCastExpr [[ADDR_66]] 'double':'double' functional cast to double -// CHECK-NEXT: | `-ImplicitCastExpr [[ADDR_67]] 'double':'double' part_of_explicit_cast +// CHECK-NEXT: | `-CXXFunctionalCastExpr [[ADDR_66]] 'double' functional cast to double +// CHECK-NEXT: | `-ImplicitCastExpr [[ADDR_67]] 'double' part_of_explicit_cast // CHECK-NEXT: | `-IntegerLiteral [[ADDR_58]] 'int' 0 // CHECK-NEXT: |-TypedefDecl [[ADDR_70:0x[a-z0-9]*]] col:14 referenced Ty 'int (*)({{.*}})' // CHECK-NEXT: | `-PointerType [[ADDR_71:0x[a-z0-9]*]] 'int (*)({{.*}})' diff --git a/clang/test/AST/ast-dump-openmp-begin-declare-variant_template_2.cpp b/clang/test/AST/ast-dump-openmp-begin-declare-variant_template_2.cpp index 9613e86634927..da46cef7f3f1b 100644 --- a/clang/test/AST/ast-dump-openmp-begin-declare-variant_template_2.cpp +++ b/clang/test/AST/ast-dump-openmp-begin-declare-variant_template_2.cpp @@ -66,7 +66,7 @@ int test() { // CHECK-NEXT: | `-FunctionDecl [[ADDR_10:0x[a-z0-9]*]] line:5:5 used also_before 'int (double)' // CHECK-NEXT: | |-TemplateArgument type 'double' // CHECK-NEXT: | | `-BuiltinType [[ADDR_11:0x[a-z0-9]*]] 'double' -// CHECK-NEXT: | |-ParmVarDecl [[ADDR_12:0x[a-z0-9]*]] col:18 'double':'double' +// CHECK-NEXT: | |-ParmVarDecl [[ADDR_12:0x[a-z0-9]*]] col:18 'double' // CHECK-NEXT: | |-CompoundStmt [[ADDR_13:0x[a-z0-9]*]] // CHECK-NEXT: | | `-ReturnStmt [[ADDR_14:0x[a-z0-9]*]] // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_6]] 'int' 1 @@ -97,7 +97,7 @@ int test() { // CHECK-NEXT: | `-FunctionDecl [[ADDR_17]] line:18:1 also_before[implementation={extension(allow_templates)}] 'int (double)' // CHECK-NEXT: | |-TemplateArgument type 'double' // CHECK-NEXT: | | `-BuiltinType [[ADDR_11]] 'double' -// CHECK-NEXT: | |-ParmVarDecl [[ADDR_37:0x[a-z0-9]*]] col:18 'double':'double' +// CHECK-NEXT: | |-ParmVarDecl [[ADDR_37:0x[a-z0-9]*]] col:18 'double' // CHECK-NEXT: | `-CompoundStmt [[ADDR_38:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_39:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_36]] 'int' 0 @@ -110,7 +110,7 @@ int test() { // CHECK-NEXT: | `-FunctionDecl [[ADDR_47:0x[a-z0-9]*]] line:44:5 used also_after 'int (char)' // CHECK-NEXT: | |-TemplateArgument type 'char' // CHECK-NEXT: | | `-BuiltinType [[ADDR_48:0x[a-z0-9]*]] 'char' -// CHECK-NEXT: | |-ParmVarDecl [[ADDR_49:0x[a-z0-9]*]] col:17 'char':'char' +// CHECK-NEXT: | |-ParmVarDecl [[ADDR_49:0x[a-z0-9]*]] col:17 'char' // CHECK-NEXT: | |-CompoundStmt [[ADDR_50:0x[a-z0-9]*]] // CHECK-NEXT: | | `-ReturnStmt [[ADDR_51:0x[a-z0-9]*]] // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_52:0x[a-z0-9]*]] 'int' 6 @@ -126,7 +126,7 @@ int test() { // CHECK-NEXT: | `-FunctionDecl [[ADDR_55]] line:22:1 also_after[implementation={extension(allow_templates)}] 'int (char)' // CHECK-NEXT: | |-TemplateArgument type 'char' // CHECK-NEXT: | | `-BuiltinType [[ADDR_48]] 'char' -// CHECK-NEXT: | |-ParmVarDecl [[ADDR_60:0x[a-z0-9]*]] col:17 'char':'char' +// CHECK-NEXT: | |-ParmVarDecl [[ADDR_60:0x[a-z0-9]*]] col:17 'char' // CHECK-NEXT: | `-CompoundStmt [[ADDR_61:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_62:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_59]] 'int' 0 @@ -213,7 +213,7 @@ int test() { // CHECK-NEXT: | `-FunctionDecl [[ADDR_128:0x[a-z0-9]*]] line:48:5 used also_after_mismatch 'int (int)' // CHECK-NEXT: | |-TemplateArgument type 'int' // CHECK-NEXT: | | `-BuiltinType [[ADDR_129:0x[a-z0-9]*]] 'int' -// CHECK-NEXT: | |-ParmVarDecl [[ADDR_130:0x[a-z0-9]*]] col:26 'int':'int' +// CHECK-NEXT: | |-ParmVarDecl [[ADDR_130:0x[a-z0-9]*]] col:26 'int' // CHECK-NEXT: | `-CompoundStmt [[ADDR_131:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_132:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_127]] 'int' 0 @@ -244,12 +244,12 @@ int test() { // CHECK-NEXT: | | |-CallExpr [[ADDR_155:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | | | |-ImplicitCastExpr [[ADDR_156:0x[a-z0-9]*]] 'int (*)(char)' // CHECK-NEXT: | | | | `-DeclRefExpr [[ADDR_157:0x[a-z0-9]*]] 'int (char)' {{.*}}Function [[ADDR_47]] 'also_after' 'int (char)' (FunctionTemplate [[ADDR_114]] 'also_after') -// CHECK-NEXT: | | | `-ImplicitCastExpr [[ADDR_158:0x[a-z0-9]*]] 'char':'char' +// CHECK-NEXT: | | | `-ImplicitCastExpr [[ADDR_158:0x[a-z0-9]*]] 'char' // CHECK-NEXT: | | | `-IntegerLiteral [[ADDR_159:0x[a-z0-9]*]] 'int' 0 // CHECK-NEXT: | | `-CallExpr [[ADDR_160:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | | |-ImplicitCastExpr [[ADDR_161:0x[a-z0-9]*]] 'int (*)(char)' // CHECK-NEXT: | | | `-DeclRefExpr [[ADDR_54]] 'int (char)' {{.*}}Function [[ADDR_55]] 'also_after[implementation={extension(allow_templates)}]' 'int (char)' -// CHECK-NEXT: | | `-ImplicitCastExpr [[ADDR_162:0x[a-z0-9]*]] 'char':'char' +// CHECK-NEXT: | | `-ImplicitCastExpr [[ADDR_162:0x[a-z0-9]*]] 'char' // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_159]] 'int' 0 // CHECK-NEXT: | `-CallExpr [[ADDR_163:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | |-ImplicitCastExpr [[ADDR_164:0x[a-z0-9]*]] 'int (*)(int)' diff --git a/clang/test/AST/ast-dump-openmp-begin-declare-variant_template_3.cpp b/clang/test/AST/ast-dump-openmp-begin-declare-variant_template_3.cpp index 60619801735f2..ad269506042c8 100644 --- a/clang/test/AST/ast-dump-openmp-begin-declare-variant_template_3.cpp +++ b/clang/test/AST/ast-dump-openmp-begin-declare-variant_template_3.cpp @@ -97,14 +97,14 @@ int test() { // CHECK-NEXT: | |-FunctionDecl [[ADDR_32:0x[a-z0-9]*]] line:10:5 used also_before 'int (int)' // CHECK-NEXT: | | |-TemplateArgument type 'int' // CHECK-NEXT: | | | `-BuiltinType [[ADDR_9]] 'int' -// CHECK-NEXT: | | |-ParmVarDecl [[ADDR_33:0x[a-z0-9]*]] col:19 s 'int':'int' +// CHECK-NEXT: | | |-ParmVarDecl [[ADDR_33:0x[a-z0-9]*]] col:19 s 'int' // CHECK-NEXT: | | `-CompoundStmt [[ADDR_34:0x[a-z0-9]*]] // CHECK-NEXT: | | `-ReturnStmt [[ADDR_35:0x[a-z0-9]*]] // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_28]] 'int' 0 // CHECK-NEXT: | `-FunctionDecl [[ADDR_36:0x[a-z0-9]*]] line:10:5 used also_before 'int (double)' // CHECK-NEXT: | |-TemplateArgument type 'double' // CHECK-NEXT: | | `-BuiltinType [[ADDR_21]] 'double' -// CHECK-NEXT: | |-ParmVarDecl [[ADDR_37:0x[a-z0-9]*]] col:19 s 'double':'double' +// CHECK-NEXT: | |-ParmVarDecl [[ADDR_37:0x[a-z0-9]*]] col:19 s 'double' // CHECK-NEXT: | `-CompoundStmt [[ADDR_38:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_39:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_28]] 'int' 0 @@ -116,7 +116,7 @@ int test() { // CHECK-NEXT: | | |-DeclStmt [[ADDR_44:0x[a-z0-9]*]] // CHECK-NEXT: | | | `-VarDecl [[ADDR_45:0x[a-z0-9]*]] col:10 referenced t 'double' // CHECK-NEXT: | | |-DeclStmt [[ADDR_46:0x[a-z0-9]*]] -// CHECK-NEXT: | | | `-VarDecl [[ADDR_47:0x[a-z0-9]*]] col:8 q 'S':'S' callinit +// CHECK-NEXT: | | | `-VarDecl [[ADDR_47:0x[a-z0-9]*]] col:8 q 'S' callinit // CHECK-NEXT: | | | `-ParenListExpr [[ADDR_48:0x[a-z0-9]*]] 'NULL TYPE' // CHECK-NEXT: | | | |-IntegerLiteral [[ADDR_49:0x[a-z0-9]*]] 'int' 1 // CHECK-NEXT: | | | `-UnaryOperator [[ADDR_50:0x[a-z0-9]*]] 'double *' prefix '&' cannot overflow @@ -126,11 +126,11 @@ int test() { // CHECK-NEXT: | |-FunctionDecl [[ADDR_54:0x[a-z0-9]*]] line:16:1 also_before[implementation={extension(allow_templates)}] 'int (S)' // CHECK-NEXT: | | |-TemplateArgument type 'int' // CHECK-NEXT: | | | `-BuiltinType [[ADDR_9]] 'int' -// CHECK-NEXT: | | `-ParmVarDecl [[ADDR_55:0x[a-z0-9]*]] col:22 s 'S':'S' +// CHECK-NEXT: | | `-ParmVarDecl [[ADDR_55:0x[a-z0-9]*]] col:22 s 'S' // CHECK-NEXT: | `-FunctionDecl [[ADDR_56:0x[a-z0-9]*]] line:16:1 also_before[implementation={extension(allow_templates)}] 'int (S)' // CHECK-NEXT: | |-TemplateArgument type 'double' // CHECK-NEXT: | | `-BuiltinType [[ADDR_21]] 'double' -// CHECK-NEXT: | `-ParmVarDecl [[ADDR_57:0x[a-z0-9]*]] col:22 s 'S':'S' +// CHECK-NEXT: | `-ParmVarDecl [[ADDR_57:0x[a-z0-9]*]] col:22 s 'S' // CHECK-NEXT: |-FunctionTemplateDecl [[ADDR_58:0x[a-z0-9]*]] col:5 implicit special // CHECK-NEXT: | |-TemplateTypeParmDecl [[ADDR_59:0x[a-z0-9]*]] col:20 referenced typename depth 0 index 0 T // CHECK-NEXT: | |-FunctionDecl [[ADDR_60:0x[a-z0-9]*]] col:5 special 'int (S)' @@ -140,7 +140,7 @@ int test() { // CHECK-NEXT: | `-FunctionDecl [[ADDR_65:0x[a-z0-9]*]] col:5 used special 'int (S)' // CHECK-NEXT: | |-TemplateArgument type 'int' // CHECK-NEXT: | | `-BuiltinType [[ADDR_9]] 'int' -// CHECK-NEXT: | |-ParmVarDecl [[ADDR_66:0x[a-z0-9]*]] col:18 s 'S':'S' +// CHECK-NEXT: | |-ParmVarDecl [[ADDR_66:0x[a-z0-9]*]] col:18 s 'S' // CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_67:0x[a-z0-9]*]] <> Implicit implementation={extension(allow_templates)} // CHECK-NEXT: | `-DeclRefExpr [[ADDR_68:0x[a-z0-9]*]] 'int (S)' {{.*}}Function [[ADDR_69:0x[a-z0-9]*]] 'special[implementation={extension(allow_templates)}]' 'int (S)' // CHECK-NEXT: |-FunctionTemplateDecl [[ADDR_70:0x[a-z0-9]*]] line:23:1 special[implementation={extension(allow_templates)}] @@ -151,7 +151,7 @@ int test() { // CHECK-NEXT: | | |-DeclStmt [[ADDR_72:0x[a-z0-9]*]] // CHECK-NEXT: | | | `-VarDecl [[ADDR_73:0x[a-z0-9]*]] col:5 referenced t 'T' // CHECK-NEXT: | | |-DeclStmt [[ADDR_74:0x[a-z0-9]*]] -// CHECK-NEXT: | | | `-VarDecl [[ADDR_75:0x[a-z0-9]*]] col:8 q 'S':'S' callinit +// CHECK-NEXT: | | | `-VarDecl [[ADDR_75:0x[a-z0-9]*]] col:8 q 'S' callinit // CHECK-NEXT: | | | `-ParenListExpr [[ADDR_76:0x[a-z0-9]*]] 'NULL TYPE' // CHECK-NEXT: | | | |-IntegerLiteral [[ADDR_77:0x[a-z0-9]*]] 'int' 0 // CHECK-NEXT: | | | `-UnaryOperator [[ADDR_78:0x[a-z0-9]*]] '' prefix '&' cannot overflow @@ -161,16 +161,16 @@ int test() { // CHECK-NEXT: | `-FunctionDecl [[ADDR_69]] line:23:1 special[implementation={extension(allow_templates)}] 'int (S)' // CHECK-NEXT: | |-TemplateArgument type 'int' // CHECK-NEXT: | | `-BuiltinType [[ADDR_9]] 'int' -// CHECK-NEXT: | |-ParmVarDecl [[ADDR_82:0x[a-z0-9]*]] col:18 s 'S':'S' +// CHECK-NEXT: | |-ParmVarDecl [[ADDR_82:0x[a-z0-9]*]] col:18 s 'S' // CHECK-NEXT: | `-CompoundStmt [[ADDR_83:0x[a-z0-9]*]] // CHECK-NEXT: | |-DeclStmt [[ADDR_84:0x[a-z0-9]*]] -// CHECK-NEXT: | | `-VarDecl [[ADDR_85:0x[a-z0-9]*]] col:5 used t 'int':'int' +// CHECK-NEXT: | | `-VarDecl [[ADDR_85:0x[a-z0-9]*]] col:5 used t 'int' // CHECK-NEXT: | |-DeclStmt [[ADDR_86:0x[a-z0-9]*]] -// CHECK-NEXT: | | `-VarDecl [[ADDR_87:0x[a-z0-9]*]] col:8 q 'S':'S' callinit -// CHECK-NEXT: | | `-CXXConstructExpr [[ADDR_88:0x[a-z0-9]*]] 'S':'S' 'void (int, int *)' +// CHECK-NEXT: | | `-VarDecl [[ADDR_87:0x[a-z0-9]*]] col:8 q 'S' callinit +// CHECK-NEXT: | | `-CXXConstructExpr [[ADDR_88:0x[a-z0-9]*]] 'S' 'void (int, int *)' // CHECK-NEXT: | | |-IntegerLiteral [[ADDR_77]] 'int' 0 // CHECK-NEXT: | | `-UnaryOperator [[ADDR_89:0x[a-z0-9]*]] 'int *' prefix '&' cannot overflow -// CHECK-NEXT: | | `-DeclRefExpr [[ADDR_90:0x[a-z0-9]*]] 'int':'int' {{.*}}Var [[ADDR_85]] 't' 'int':'int' +// CHECK-NEXT: | | `-DeclRefExpr [[ADDR_90:0x[a-z0-9]*]] 'int' {{.*}}Var [[ADDR_85]] 't' 'int' // CHECK-NEXT: | `-ReturnStmt [[ADDR_91:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_81]] 'int' 0 // CHECK-NEXT: |-FunctionTemplateDecl [[ADDR_92:0x[a-z0-9]*]] col:5 implicit also_after @@ -187,7 +187,7 @@ int test() { // CHECK-NEXT: | |-DeclStmt [[ADDR_101:0x[a-z0-9]*]] // CHECK-NEXT: | | `-VarDecl [[ADDR_102:0x[a-z0-9]*]] col:10 referenced t 'double' // CHECK-NEXT: | |-DeclStmt [[ADDR_103:0x[a-z0-9]*]] -// CHECK-NEXT: | | `-VarDecl [[ADDR_104:0x[a-z0-9]*]] col:8 q 'S':'S' callinit +// CHECK-NEXT: | | `-VarDecl [[ADDR_104:0x[a-z0-9]*]] col:8 q 'S' callinit // CHECK-NEXT: | | `-ParenListExpr [[ADDR_105:0x[a-z0-9]*]] 'NULL TYPE' // CHECK-NEXT: | | |-FloatingLiteral [[ADDR_106:0x[a-z0-9]*]] 'double' 2.000000e+00 // CHECK-NEXT: | | `-UnaryOperator [[ADDR_107:0x[a-z0-9]*]] 'double *' prefix '&' cannot overflow @@ -204,14 +204,14 @@ int test() { // CHECK-NEXT: | |-FunctionDecl [[ADDR_118:0x[a-z0-9]*]] line:38:5 used also_after 'int (int)' // CHECK-NEXT: | | |-TemplateArgument type 'int' // CHECK-NEXT: | | | `-BuiltinType [[ADDR_9]] 'int' -// CHECK-NEXT: | | |-ParmVarDecl [[ADDR_119:0x[a-z0-9]*]] col:18 s 'int':'int' +// CHECK-NEXT: | | |-ParmVarDecl [[ADDR_119:0x[a-z0-9]*]] col:18 s 'int' // CHECK-NEXT: | | `-CompoundStmt [[ADDR_120:0x[a-z0-9]*]] // CHECK-NEXT: | | `-ReturnStmt [[ADDR_121:0x[a-z0-9]*]] // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_117]] 'int' 0 // CHECK-NEXT: | `-FunctionDecl [[ADDR_122:0x[a-z0-9]*]] line:38:5 used also_after 'int (double)' // CHECK-NEXT: | |-TemplateArgument type 'double' // CHECK-NEXT: | | `-BuiltinType [[ADDR_21]] 'double' -// CHECK-NEXT: | |-ParmVarDecl [[ADDR_123:0x[a-z0-9]*]] col:18 s 'double':'double' +// CHECK-NEXT: | |-ParmVarDecl [[ADDR_123:0x[a-z0-9]*]] col:18 s 'double' // CHECK-NEXT: | `-CompoundStmt [[ADDR_124:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_125:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_117]] 'int' 0 @@ -243,19 +243,19 @@ int test() { // CHECK-NEXT: |-CallExpr [[ADDR_151:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | |-ImplicitCastExpr [[ADDR_152:0x[a-z0-9]*]] 'int (*)(S)' // CHECK-NEXT: | | `-DeclRefExpr [[ADDR_153:0x[a-z0-9]*]] 'int (S)' {{.*}}Function [[ADDR_65]] 'special' 'int (S)' (FunctionTemplate [[ADDR_58]] 'special') -// CXX11-NEXT: | `-CXXConstructExpr [[ADDR_154:0x[a-z0-9]*]] 'S':'S' 'void (S &&) noexcept' elidable -// CXX11-NEXT: | `-MaterializeTemporaryExpr [[ADDR_155:0x[a-z0-9]*]] 'S':'S' xvalue -// CHECK-NEXT: | `-CXXTemporaryObjectExpr [[ADDR_156:0x[a-z0-9]*]] 'S':'S' 'void (int, int *)' +// CXX11-NEXT: | `-CXXConstructExpr [[ADDR_154:0x[a-z0-9]*]] 'S' 'void (S &&) noexcept' elidable +// CXX11-NEXT: | `-MaterializeTemporaryExpr [[ADDR_155:0x[a-z0-9]*]] 'S' xvalue +// CHECK-NEXT: | `-CXXTemporaryObjectExpr [[ADDR_156:0x[a-z0-9]*]] 'S' 'void (int, int *)' // CHECK-NEXT: | |-IntegerLiteral [[ADDR_157:0x[a-z0-9]*]] 'int' 0 // CHECK-NEXT: | `-ImplicitCastExpr [[ADDR_158:0x[a-z0-9]*]] 'int *' // CHECK-NEXT: | `-IntegerLiteral [[ADDR_159:0x[a-z0-9]*]] 'int' 0 // CHECK-NEXT: `-CallExpr [[ADDR_160:0x[a-z0-9]*]] 'int' // CHECK-NEXT: |-ImplicitCastExpr [[ADDR_161:0x[a-z0-9]*]] 'int (*)(S)' // CHECK-NEXT: | `-DeclRefExpr [[ADDR_68]] 'int (S)' {{.*}}Function [[ADDR_69]] 'special[implementation={extension(allow_templates)}]' 'int (S)' -// CXX11-NEXT: `-CXXConstructExpr [[ADDR_162:0x[a-z0-9]*]] 'S':'S' 'void (S &&) noexcept' elidable -// CXX11-NEXT: `-MaterializeTemporaryExpr [[ADDR_163:0x[a-z0-9]*]] 'S':'S' xvalue -// CXX11-NEXT: `-CXXTemporaryObjectExpr [[ADDR_156]] 'S':'S' 'void (int, int *)' -// CXX17-NEXT: `-CXXTemporaryObjectExpr [[ADDR_156]] 'S':'S' 'void (int, int *)' +// CXX11-NEXT: `-CXXConstructExpr [[ADDR_162:0x[a-z0-9]*]] 'S' 'void (S &&) noexcept' elidable +// CXX11-NEXT: `-MaterializeTemporaryExpr [[ADDR_163:0x[a-z0-9]*]] 'S' xvalue +// CXX11-NEXT: `-CXXTemporaryObjectExpr [[ADDR_156]] 'S' 'void (int, int *)' +// CXX17-NEXT: `-CXXTemporaryObjectExpr [[ADDR_156]] 'S' 'void (int, int *)' // CHECK-NEXT: |-IntegerLiteral [[ADDR_157]] 'int' 0 // CHECK-NEXT: `-ImplicitCastExpr [[ADDR_158]] 'int *' // CHECK-NEXT: `-IntegerLiteral [[ADDR_159]] 'int' 0 diff --git a/clang/test/AST/ast-dump-overloaded-operators.cpp b/clang/test/AST/ast-dump-overloaded-operators.cpp index dc6d7bdc9b085..639a0d9874eb0 100644 --- a/clang/test/AST/ast-dump-overloaded-operators.cpp +++ b/clang/test/AST/ast-dump-overloaded-operators.cpp @@ -31,14 +31,14 @@ void test() { // CHECK-NEXT: |-CXXOperatorCallExpr {{.*}} 'void' '+' // CHECK-NEXT: | |-ImplicitCastExpr {{.*}} 'void (*)(E, E)' // CHECK-NEXT: | | `-DeclRefExpr {{.*}} 'void (E, E)' lvalue Function {{.*}} 'operator+' 'void (E, E)' -// CHECK-NEXT: | |-ImplicitCastExpr {{.*}} 'E':'E' -// CHECK-NEXT: | | `-DeclRefExpr {{.*}} 'E':'E' lvalue Var {{.*}} 'e' 'E' -// CHECK-NEXT: | `-ImplicitCastExpr {{.*}} 'E':'E' -// CHECK-NEXT: | `-DeclRefExpr {{.*}} 'E':'E' lvalue Var {{.*}} 'e' 'E' +// CHECK-NEXT: | |-ImplicitCastExpr {{.*}} 'E' +// CHECK-NEXT: | | `-DeclRefExpr {{.*}} 'E' lvalue Var {{.*}} 'e' 'E' +// CHECK-NEXT: | `-ImplicitCastExpr {{.*}} 'E' +// CHECK-NEXT: | `-DeclRefExpr {{.*}} 'E' lvalue Var {{.*}} 'e' 'E' // CHECK-NEXT: `-CXXOperatorCallExpr {{.*}} 'void' ',' // CHECK-NEXT: |-ImplicitCastExpr {{.*}} 'void (*)(E, E)' // CHECK-NEXT: | `-DeclRefExpr {{.*}} 'void (E, E)' lvalue Function {{.*}} 'operator,' 'void (E, E)' -// CHECK-NEXT: |-ImplicitCastExpr {{.*}} 'E':'E' -// CHECK-NEXT: | `-DeclRefExpr {{.*}} 'E':'E' lvalue Var {{.*}} 'e' 'E' -// CHECK-NEXT: `-ImplicitCastExpr {{.*}} 'E':'E' -// CHECK-NEXT: `-DeclRefExpr {{.*}} 'E':'E' lvalue Var {{.*}} 'e' 'E' +// CHECK-NEXT: |-ImplicitCastExpr {{.*}} 'E' +// CHECK-NEXT: | `-DeclRefExpr {{.*}} 'E' lvalue Var {{.*}} 'e' 'E' +// CHECK-NEXT: `-ImplicitCastExpr {{.*}} 'E' +// CHECK-NEXT: `-DeclRefExpr {{.*}} 'E' lvalue Var {{.*}} 'e' 'E' diff --git a/clang/test/AST/ast-dump-records-json.cpp b/clang/test/AST/ast-dump-records-json.cpp index bc53d03176f66..a7eb8771d3f02 100644 --- a/clang/test/AST/ast-dump-records-json.cpp +++ b/clang/test/AST/ast-dump-records-json.cpp @@ -3266,7 +3266,6 @@ struct Derived6 : virtual public Bases... { // CHECK-NEXT: { // CHECK-NEXT: "access": "public", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "Base1", // CHECK-NEXT: "qualType": "Base1" // CHECK-NEXT: }, // CHECK-NEXT: "writtenAccess": "none" @@ -3378,7 +3377,6 @@ struct Derived6 : virtual public Bases... { // CHECK-NEXT: { // CHECK-NEXT: "access": "private", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "Base1", // CHECK-NEXT: "qualType": "Base1" // CHECK-NEXT: }, // CHECK-NEXT: "writtenAccess": "private" @@ -3479,7 +3477,6 @@ struct Derived6 : virtual public Bases... { // CHECK-NEXT: "access": "public", // CHECK-NEXT: "isVirtual": true, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "Base1", // CHECK-NEXT: "qualType": "Base1" // CHECK-NEXT: }, // CHECK-NEXT: "writtenAccess": "none" @@ -3718,7 +3715,6 @@ struct Derived6 : virtual public Bases... { // CHECK-NEXT: { // CHECK-NEXT: "access": "public", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "Base1", // CHECK-NEXT: "qualType": "Base1" // CHECK-NEXT: }, // CHECK-NEXT: "writtenAccess": "none" @@ -3727,7 +3723,6 @@ struct Derived6 : virtual public Bases... { // CHECK-NEXT: "access": "public", // CHECK-NEXT: "isVirtual": true, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "Base2", // CHECK-NEXT: "qualType": "Base2" // CHECK-NEXT: }, // CHECK-NEXT: "writtenAccess": "none" @@ -3735,7 +3730,6 @@ struct Derived6 : virtual public Bases... { // CHECK-NEXT: { // CHECK-NEXT: "access": "protected", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "Base3", // CHECK-NEXT: "qualType": "Base3" // CHECK-NEXT: }, // CHECK-NEXT: "writtenAccess": "protected" @@ -3975,7 +3969,6 @@ struct Derived6 : virtual public Bases... { // CHECK-NEXT: "access": "protected", // CHECK-NEXT: "isVirtual": true, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "Base1", // CHECK-NEXT: "qualType": "Base1" // CHECK-NEXT: }, // CHECK-NEXT: "writtenAccess": "protected" diff --git a/clang/test/AST/ast-dump-records.cpp b/clang/test/AST/ast-dump-records.cpp index 7a93b69d37ba6..bfd8892698d4b 100644 --- a/clang/test/AST/ast-dump-records.cpp +++ b/clang/test/AST/ast-dump-records.cpp @@ -301,10 +301,10 @@ class NonTrivial { struct CheckFullExpression { // CHECK: |-CXXRecordDecl {{.*}} struct CheckFullExpression definition NonTrivial value = NonTrivial(); -// CHECK: | |-FieldDecl {{.*}} value 'NonTrivial':'NonTrivial' -// CHECK-NEXT: | | `-ExprWithCleanups {{.*}} 'NonTrivial':'NonTrivial' -// CHECK-NEXT: | | `-CXXBindTemporaryExpr {{.*}} 'NonTrivial':'NonTrivial' (CXXTemporary{{.*}}) -// CHECK-NEXT: | | `-CXXTemporaryObjectExpr {{.*}} 'NonTrivial':'NonTrivial' 'void ()' +// CHECK: | |-FieldDecl {{.*}} value 'NonTrivial' +// CHECK-NEXT: | | `-ExprWithCleanups {{.*}} 'NonTrivial' +// CHECK-NEXT: | | `-CXXBindTemporaryExpr {{.*}} 'NonTrivial' (CXXTemporary{{.*}}) +// CHECK-NEXT: | | `-CXXTemporaryObjectExpr {{.*}} 'NonTrivial' 'void ()' }; struct CheckNoCleanup { diff --git a/clang/test/AST/ast-dump-recovery.cpp b/clang/test/AST/ast-dump-recovery.cpp index 278b9fc000b57..cfb013585ad74 100644 --- a/clang/test/AST/ast-dump-recovery.cpp +++ b/clang/test/AST/ast-dump-recovery.cpp @@ -202,27 +202,27 @@ void InvalidInitalizer(int x) { // CHECK-NEXT: `-InitListExpr Bar b2 = {1}; // CHECK: `-VarDecl {{.*}} b3 'Bar' - // CHECK-NEXT: `-RecoveryExpr {{.*}} 'Bar':'Bar' contains-errors + // CHECK-NEXT: `-RecoveryExpr {{.*}} 'Bar' contains-errors // CHECK-NEXT: `-DeclRefExpr {{.*}} 'x' 'int' Bar b3 = Bar(x); // CHECK: `-VarDecl {{.*}} b4 'Bar' - // CHECK-NEXT: `-RecoveryExpr {{.*}} 'Bar':'Bar' contains-errors + // CHECK-NEXT: `-RecoveryExpr {{.*}} 'Bar' contains-errors // CHECK-NEXT: `-InitListExpr {{.*}} 'void' // CHECK-NEXT: `-DeclRefExpr {{.*}} 'x' 'int' Bar b4 = Bar{x}; // CHECK: `-VarDecl {{.*}} b5 'Bar' - // CHECK-NEXT: `-CXXUnresolvedConstructExpr {{.*}} 'Bar':'Bar' contains-errors 'Bar' + // CHECK-NEXT: `-CXXUnresolvedConstructExpr {{.*}} 'Bar' contains-errors 'Bar' // CHECK-NEXT: `-RecoveryExpr {{.*}} contains-errors // CHECK-NEXT: `-UnresolvedLookupExpr {{.*}} 'invalid' Bar b5 = Bar(invalid()); // CHECK: `-VarDecl {{.*}} b6 'Bar' - // CHECK-NEXT: `-CXXUnresolvedConstructExpr {{.*}} 'Bar':'Bar' contains-errors 'Bar' + // CHECK-NEXT: `-CXXUnresolvedConstructExpr {{.*}} 'Bar' contains-errors 'Bar' // CHECK-NEXT: `-InitListExpr {{.*}} contains-errors // CHECK-NEXT: `-RecoveryExpr {{.*}} contains-errors // CHECK-NEXT: `-UnresolvedLookupExpr {{.*}} 'invalid' Bar b6 = Bar{invalid()}; - // CHECK: RecoveryExpr {{.*}} 'Bar':'Bar' contains-errors + // CHECK: RecoveryExpr {{.*}} 'Bar' contains-errors // CHECK-NEXT: `-IntegerLiteral {{.*}} 'int' 1 Bar(1); @@ -326,7 +326,7 @@ void CtorInitializer() { // CHECK-NEXT: | `-RecoveryExpr {{.*}} '' // CHECK-NEXT: | `-UnresolvedLookupExpr {{.*}} '' // CHECK-NEXT: |-CXXCtorInitializer Field {{.*}} 's' 'S' - // CHECK-NEXT: | `-RecoveryExpr {{.*}} 'S':'S' contains-errors + // CHECK-NEXT: | `-RecoveryExpr {{.*}} 'S' contains-errors // CHECK-NEXT: | |-IntegerLiteral {{.*}} 1 // CHECK-NEXT: | `-IntegerLiteral {{.*}} 2 }; diff --git a/clang/test/AST/ast-dump-stmt-json.cpp b/clang/test/AST/ast-dump-stmt-json.cpp index 8e42a2e276b46..667a12a012024 100644 --- a/clang/test/AST/ast-dump-stmt-json.cpp +++ b/clang/test/AST/ast-dump-stmt-json.cpp @@ -2265,7 +2265,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "isReferenced": true, // CHECK-NEXT: "name": "obj", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "DependentScopeMemberExprWrapper", // CHECK-NEXT: "qualType": "DependentScopeMemberExprWrapper" // CHECK-NEXT: } // CHECK-NEXT: } @@ -2331,7 +2330,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "DependentScopeMemberExprWrapper", // CHECK-NEXT: "qualType": "DependentScopeMemberExprWrapper" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -2340,7 +2338,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "kind": "VarDecl", // CHECK-NEXT: "name": "obj", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "DependentScopeMemberExprWrapper", // CHECK-NEXT: "qualType": "DependentScopeMemberExprWrapper" // CHECK-NEXT: } // CHECK-NEXT: } @@ -2429,7 +2426,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "DependentScopeMemberExprWrapper", // CHECK-NEXT: "qualType": "DependentScopeMemberExprWrapper" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -2438,7 +2434,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "kind": "VarDecl", // CHECK-NEXT: "name": "obj", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "DependentScopeMemberExprWrapper", // CHECK-NEXT: "qualType": "DependentScopeMemberExprWrapper" // CHECK-NEXT: } // CHECK-NEXT: } @@ -2593,7 +2588,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "DependentScopeMemberExprWrapper", // CHECK-NEXT: "qualType": "DependentScopeMemberExprWrapper" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -2602,7 +2596,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "kind": "VarDecl", // CHECK-NEXT: "name": "obj", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "DependentScopeMemberExprWrapper", // CHECK-NEXT: "qualType": "DependentScopeMemberExprWrapper" // CHECK-NEXT: } // CHECK-NEXT: } @@ -2779,7 +2772,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "isReferenced": true, // CHECK-NEXT: "name": "obj", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "OtherDependentScopeMemberExprWrapper", // CHECK-NEXT: "qualType": "OtherDependentScopeMemberExprWrapper" // CHECK-NEXT: } // CHECK-NEXT: } @@ -2867,7 +2859,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "OtherDependentScopeMemberExprWrapper", // CHECK-NEXT: "qualType": "OtherDependentScopeMemberExprWrapper" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -2876,7 +2867,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "kind": "VarDecl", // CHECK-NEXT: "name": "obj", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "OtherDependentScopeMemberExprWrapper", // CHECK-NEXT: "qualType": "OtherDependentScopeMemberExprWrapper" // CHECK-NEXT: } // CHECK-NEXT: } @@ -3037,7 +3027,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "U", // CHECK-NEXT: "qualType": "U" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", @@ -3066,7 +3055,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "U", // CHECK-NEXT: "qualType": "U" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", @@ -4563,7 +4551,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "isUsed": true, // CHECK-NEXT: "name": "__begin1", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "init": "c", @@ -4663,7 +4650,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "isUsed": true, // CHECK-NEXT: "name": "__end1", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "init": "c", @@ -4804,7 +4790,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", @@ -4826,7 +4811,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -4835,7 +4819,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "kind": "VarDecl", // CHECK-NEXT: "name": "__begin1", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: } // CHECK-NEXT: } @@ -4858,7 +4841,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", @@ -4880,7 +4862,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -4889,7 +4870,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "kind": "VarDecl", // CHECK-NEXT: "name": "__end1", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: } // CHECK-NEXT: } @@ -4914,7 +4894,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -4937,7 +4916,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -4946,7 +4924,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "kind": "VarDecl", // CHECK-NEXT: "name": "__begin1", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: } // CHECK-NEXT: } @@ -5055,7 +5032,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", @@ -5077,7 +5053,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -5086,7 +5061,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "kind": "VarDecl", // CHECK-NEXT: "name": "__begin1", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: } // CHECK-NEXT: } @@ -5160,7 +5134,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "isUsed": true, // CHECK-NEXT: "name": "C", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "Container", // CHECK-NEXT: "qualType": "Container" // CHECK-NEXT: }, // CHECK-NEXT: "init": "call", @@ -5181,7 +5154,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "Container", // CHECK-NEXT: "qualType": "Container" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", @@ -5275,7 +5247,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "Container", // CHECK-NEXT: "qualType": "Container" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -5284,7 +5255,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "kind": "VarDecl", // CHECK-NEXT: "name": "C", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "Container", // CHECK-NEXT: "qualType": "Container" // CHECK-NEXT: } // CHECK-NEXT: } @@ -5333,7 +5303,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "isUsed": true, // CHECK-NEXT: "name": "__begin1", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "init": "c", @@ -5418,7 +5387,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "Container", // CHECK-NEXT: "qualType": "Container" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -5481,7 +5449,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "isUsed": true, // CHECK-NEXT: "name": "__end1", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "init": "c", @@ -5566,7 +5533,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "Container", // CHECK-NEXT: "qualType": "Container" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -5626,7 +5592,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", @@ -5648,7 +5613,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -5657,7 +5621,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "kind": "VarDecl", // CHECK-NEXT: "name": "__begin1", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: } // CHECK-NEXT: } @@ -5680,7 +5643,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", @@ -5702,7 +5664,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -5711,7 +5672,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "kind": "VarDecl", // CHECK-NEXT: "name": "__end1", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: } // CHECK-NEXT: } @@ -5736,7 +5696,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -5759,7 +5718,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -5768,7 +5726,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "kind": "VarDecl", // CHECK-NEXT: "name": "__begin1", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: } // CHECK-NEXT: } @@ -5877,7 +5834,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", @@ -5899,7 +5855,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -5908,7 +5863,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "kind": "VarDecl", // CHECK-NEXT: "name": "__begin1", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: } // CHECK-NEXT: } @@ -6120,7 +6074,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "isUsed": true, // CHECK-NEXT: "name": "__begin1", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "init": "c", @@ -6220,7 +6173,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "isUsed": true, // CHECK-NEXT: "name": "__end1", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "init": "c", @@ -6361,7 +6313,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", @@ -6383,7 +6334,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -6392,7 +6342,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "kind": "VarDecl", // CHECK-NEXT: "name": "__begin1", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: } // CHECK-NEXT: } @@ -6415,7 +6364,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", @@ -6437,7 +6385,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -6446,7 +6393,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "kind": "VarDecl", // CHECK-NEXT: "name": "__end1", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: } // CHECK-NEXT: } @@ -6471,7 +6417,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -6494,7 +6439,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -6503,7 +6447,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "kind": "VarDecl", // CHECK-NEXT: "name": "__begin1", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: } // CHECK-NEXT: } @@ -6612,7 +6555,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", @@ -6634,7 +6576,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -6643,7 +6584,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "kind": "VarDecl", // CHECK-NEXT: "name": "__begin1", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "int *", // CHECK-NEXT: "qualType": "int *" // CHECK-NEXT: } // CHECK-NEXT: } diff --git a/clang/test/AST/ast-dump-stmt.cpp b/clang/test/AST/ast-dump-stmt.cpp index 4be66756e6c1e..407584e5b82de 100644 --- a/clang/test/AST/ast-dump-stmt.cpp +++ b/clang/test/AST/ast-dump-stmt.cpp @@ -99,8 +99,8 @@ void TestUnionInitList() U us[3] = {1}; // CHECK: VarDecl {{.+}} col:5 us 'U[3]' cinit // CHECK-NEXT: `-InitListExpr {{.+}} 'U[3]' -// CHECK-NEXT: |-array_filler: InitListExpr {{.+}} 'U':'U' field Field {{.+}} 'i' 'int' -// CHECK-NEXT: `-InitListExpr {{.+}} 'U':'U' field Field {{.+}} 'i' 'int' +// CHECK-NEXT: |-array_filler: InitListExpr {{.+}} 'U' field Field {{.+}} 'i' 'int' +// CHECK-NEXT: `-InitListExpr {{.+}} 'U' field Field {{.+}} 'i' 'int' // CHECK-NEXT: `-IntegerLiteral {{.+}} 'int' 1 } @@ -198,28 +198,28 @@ void TestIteration() { // CHECK-NEXT: VarDecl 0x{{[^ ]*}} col:16 implicit used __range1 'int (&)[10]' cinit // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int[10]' lvalue Var 0x{{[^ ]*}} 'vals' 'int[10]' // CHECK-NEXT: DeclStmt - // CHECK-NEXT: VarDecl 0x{{[^ ]*}} col:14 implicit used __begin1 'int *':'int *' cinit + // CHECK-NEXT: VarDecl 0x{{[^ ]*}} col:14 implicit used __begin1 'int *' cinit // CHECK-NEXT: ImplicitCastExpr // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int[10]' lvalue Var 0x{{[^ ]*}} '__range1' 'int (&)[10]' // CHECK-NEXT: DeclStmt - // CHECK-NEXT: VarDecl 0x{{[^ ]*}} col:14 implicit used __end1 'int *':'int *' cinit + // CHECK-NEXT: VarDecl 0x{{[^ ]*}} col:14 implicit used __end1 'int *' cinit // CHECK-NEXT: BinaryOperator 0x{{[^ ]*}} 'int *' '+' // CHECK-NEXT: ImplicitCastExpr // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int[10]' lvalue Var 0x{{[^ ]*}} '__range1' 'int (&)[10]' // CHECK-NEXT: IntegerLiteral 0x{{[^ ]*}} 'long' 10 // CHECK-NEXT: BinaryOperator 0x{{[^ ]*}} 'bool' '!=' // CHECK-NEXT: ImplicitCastExpr - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *':'int *' lvalue Var 0x{{[^ ]*}} '__begin1' 'int *':'int *' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *' lvalue Var 0x{{[^ ]*}} '__begin1' 'int *' // CHECK-NEXT: ImplicitCastExpr - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *':'int *' lvalue Var 0x{{[^ ]*}} '__end1' 'int *':'int *' - // CHECK-NEXT: UnaryOperator 0x{{[^ ]*}} 'int *':'int *' lvalue prefix '++' - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *':'int *' lvalue Var 0x{{[^ ]*}} '__begin1' 'int *':'int *' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *' lvalue Var 0x{{[^ ]*}} '__end1' 'int *' + // CHECK-NEXT: UnaryOperator 0x{{[^ ]*}} 'int *' lvalue prefix '++' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *' lvalue Var 0x{{[^ ]*}} '__begin1' 'int *' // CHECK-NEXT: DeclStmt // CHECK-NEXT: VarDecl 0x{{[^ ]*}} col:12 v 'int' cinit // CHECK-NEXT: ImplicitCastExpr // CHECK-NEXT: UnaryOperator 0x{{[^ ]*}} 'int' lvalue prefix '*' cannot overflow // CHECK-NEXT: ImplicitCastExpr - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *':'int *' lvalue Var 0x{{[^ ]*}} '__begin1' 'int *':'int *' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *' lvalue Var 0x{{[^ ]*}} '__begin1' 'int *' // CHECK-NEXT: NullStmt Container C; @@ -229,32 +229,32 @@ void TestIteration() { // CHECK-NEXT: <<>> // CHECK-NEXT: DeclStmt // CHECK-NEXT: VarDecl 0x{{[^ ]*}} col:16 implicit used __range1 'Container &' cinit - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'Container':'Container' lvalue Var 0x{{[^ ]*}} 'C' 'Container':'Container' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'Container' lvalue Var 0x{{[^ ]*}} 'C' 'Container' // CHECK-NEXT: DeclStmt - // CHECK-NEXT: VarDecl 0x{{[^ ]*}} col:14 implicit used __begin1 'int *':'int *' cinit + // CHECK-NEXT: VarDecl 0x{{[^ ]*}} col:14 implicit used __begin1 'int *' cinit // CHECK-NEXT: CXXMemberCallExpr 0x{{[^ ]*}} 'int *' // CHECK-NEXT: MemberExpr 0x{{[^ ]*}} '' .begin 0x{{[^ ]*}} // CHECK-NEXT: ImplicitCastExpr - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'Container':'Container' lvalue Var 0x{{[^ ]*}} '__range1' 'Container &' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'Container' lvalue Var 0x{{[^ ]*}} '__range1' 'Container &' // CHECK-NEXT: DeclStmt - // CHECK-NEXT: VarDecl 0x{{[^ ]*}} col:14 implicit used __end1 'int *':'int *' cinit + // CHECK-NEXT: VarDecl 0x{{[^ ]*}} col:14 implicit used __end1 'int *' cinit // CHECK-NEXT: CXXMemberCallExpr 0x{{[^ ]*}} 'int *' // CHECK-NEXT: MemberExpr 0x{{[^ ]*}} '' .end 0x{{[^ ]*}} // CHECK-NEXT: ImplicitCastExpr - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'Container':'Container' lvalue Var 0x{{[^ ]*}} '__range1' 'Container &' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'Container' lvalue Var 0x{{[^ ]*}} '__range1' 'Container &' // CHECK-NEXT: BinaryOperator 0x{{[^ ]*}} 'bool' '!=' // CHECK-NEXT: ImplicitCastExpr - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *':'int *' lvalue Var 0x{{[^ ]*}} '__begin1' 'int *':'int *' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *' lvalue Var 0x{{[^ ]*}} '__begin1' 'int *' // CHECK-NEXT: ImplicitCastExpr - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *':'int *' lvalue Var 0x{{[^ ]*}} '__end1' 'int *':'int *' - // CHECK-NEXT: UnaryOperator 0x{{[^ ]*}} 'int *':'int *' lvalue prefix '++' - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *':'int *' lvalue Var 0x{{[^ ]*}} '__begin1' 'int *':'int *' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *' lvalue Var 0x{{[^ ]*}} '__end1' 'int *' + // CHECK-NEXT: UnaryOperator 0x{{[^ ]*}} 'int *' lvalue prefix '++' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *' lvalue Var 0x{{[^ ]*}} '__begin1' 'int *' // CHECK-NEXT: DeclStmt // CHECK-NEXT: VarDecl 0x{{[^ ]*}} col:12 v 'int' cinit // CHECK-NEXT: ImplicitCastExpr // CHECK-NEXT: UnaryOperator 0x{{[^ ]*}} 'int' lvalue prefix '*' cannot overflow // CHECK-NEXT: ImplicitCastExpr - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *':'int *' lvalue Var 0x{{[^ ]*}} '__begin1' 'int *':'int *' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *' lvalue Var 0x{{[^ ]*}} '__begin1' 'int *' // CHECK-NEXT: NullStmt for (int a; int v : vals) @@ -266,27 +266,27 @@ void TestIteration() { // CHECK-NEXT: VarDecl 0x{{[^ ]*}} col:23 implicit used __range1 'int (&)[10]' cinit // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int[10]' lvalue Var 0x{{[^ ]*}} 'vals' 'int[10]' // CHECK-NEXT: DeclStmt - // CHECK-NEXT: VarDecl 0x{{[^ ]*}} col:21 implicit used __begin1 'int *':'int *' cinit + // CHECK-NEXT: VarDecl 0x{{[^ ]*}} col:21 implicit used __begin1 'int *' cinit // CHECK-NEXT: ImplicitCastExpr // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int[10]' lvalue Var 0x{{[^ ]*}} '__range1' 'int (&)[10]' // CHECK-NEXT: DeclStmt - // CHECK-NEXT: VarDecl 0x{{[^ ]*}} col:21 implicit used __end1 'int *':'int *' cinit + // CHECK-NEXT: VarDecl 0x{{[^ ]*}} col:21 implicit used __end1 'int *' cinit // CHECK-NEXT: BinaryOperator 0x{{[^ ]*}} 'int *' '+' // CHECK-NEXT: ImplicitCastExpr // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int[10]' lvalue Var 0x{{[^ ]*}} '__range1' 'int (&)[10]' // CHECK-NEXT: IntegerLiteral 0x{{[^ ]*}} 'long' 10 // CHECK-NEXT: BinaryOperator 0x{{[^ ]*}} 'bool' '!=' // CHECK-NEXT: ImplicitCastExpr - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *':'int *' lvalue Var 0x{{[^ ]*}} '__begin1' 'int *':'int *' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *' lvalue Var 0x{{[^ ]*}} '__begin1' 'int *' // CHECK-NEXT: ImplicitCastExpr - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *':'int *' lvalue Var 0x{{[^ ]*}} '__end1' 'int *':'int *' - // CHECK-NEXT: UnaryOperator 0x{{[^ ]*}} 'int *':'int *' lvalue prefix '++' - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *':'int *' lvalue Var 0x{{[^ ]*}} '__begin1' 'int *':'int *' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *' lvalue Var 0x{{[^ ]*}} '__end1' 'int *' + // CHECK-NEXT: UnaryOperator 0x{{[^ ]*}} 'int *' lvalue prefix '++' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *' lvalue Var 0x{{[^ ]*}} '__begin1' 'int *' // CHECK-NEXT: DeclStmt // CHECK-NEXT: VarDecl 0x{{[^ ]*}} col:19 v 'int' cinit // CHECK-NEXT: ImplicitCastExpr // CHECK-NEXT: UnaryOperator 0x{{[^ ]*}} 'int' lvalue prefix '*' cannot overflow // CHECK-NEXT: ImplicitCastExpr - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *':'int *' lvalue Var 0x{{[^ ]*}} '__begin1' 'int *':'int *' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *' lvalue Var 0x{{[^ ]*}} '__begin1' 'int *' // CHECK-NEXT: NullStmt } diff --git a/clang/test/AST/ast-dump-stmt.m b/clang/test/AST/ast-dump-stmt.m index 1d349ece966f8..e0fc16b3fa825 100644 --- a/clang/test/AST/ast-dump-stmt.m +++ b/clang/test/AST/ast-dump-stmt.m @@ -55,4 +55,4 @@ id TestCompoundLiteral(id a) { // CHECK: FunctionDecl{{.*}}TestCompoundLiteral // CHECK: ExprWithCleanups // CHECK-NEXT: cleanup CompoundLiteralExpr -// CHECK: CompoundLiteralExpr{{.*}}'S':'S' lvalue +// CHECK: CompoundLiteralExpr{{.*}}'S' lvalue diff --git a/clang/test/AST/ast-dump-template-decls-json.cpp b/clang/test/AST/ast-dump-template-decls-json.cpp index f51ef937d91db..00a656cd05917 100644 --- a/clang/test/AST/ast-dump-template-decls-json.cpp +++ b/clang/test/AST/ast-dump-template-decls-json.cpp @@ -826,7 +826,6 @@ void i(); // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "Uy", // CHECK-NEXT: "qualType": "Uy" // CHECK-NEXT: } // CHECK-NEXT: } diff --git a/clang/test/AST/ast-dump-template-decls.cpp b/clang/test/AST/ast-dump-template-decls.cpp index 847a437e0f85e..142bc9e6ad9a0 100644 --- a/clang/test/AST/ast-dump-template-decls.cpp +++ b/clang/test/AST/ast-dump-template-decls.cpp @@ -171,7 +171,7 @@ template class E {}; using test1 = D; // CHECK: TypeAliasDecl 0x{{[^ ]*}} col:7 test1 'D':'subst_default_argument::E>' // CHECK: TemplateSpecializationType 0x{{[^ ]*}} 'A' sugar A -// CHECK-NEXT: |-TemplateArgument type 'int':'int' +// CHECK-NEXT: |-TemplateArgument type 'int' // CHECK-NEXT: | `-SubstTemplateTypeParmType 0x{{[^ ]*}} 'int' sugar class depth 0 index 1 D2 // CHECK-NEXT: | |-TypeAliasTemplate 0x{{[^ ]*}} 'D' // CHECK-NEXT: | `-BuiltinType 0x{{[^ ]*}} 'int' diff --git a/clang/test/AST/ast-dump-template-json-win32-mangler-crash.cpp b/clang/test/AST/ast-dump-template-json-win32-mangler-crash.cpp index f6d1caa121f2a..8c03b58abb0ed 100644 --- a/clang/test/AST/ast-dump-template-json-win32-mangler-crash.cpp +++ b/clang/test/AST/ast-dump-template-json-win32-mangler-crash.cpp @@ -532,7 +532,6 @@ int main() // CHECK-NEXT: }, // CHECK-NEXT: "name": "type", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "integral_constant<_Ty, _Val>", // CHECK-NEXT: "qualType": "integral_constant<_Ty, _Val>" // CHECK-NEXT: }, // CHECK-NEXT: "inner": [ @@ -872,7 +871,6 @@ int main() // CHECK-NEXT: }, // CHECK-NEXT: "name": "bool_constant", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "integral_constant", // CHECK-NEXT: "qualType": "integral_constant" // CHECK-NEXT: }, // CHECK-NEXT: "inner": [ diff --git a/clang/test/AST/ast-dump-temporaries-json.cpp b/clang/test/AST/ast-dump-temporaries-json.cpp index a8b14de29fcf9..0fd2762cee1a7 100644 --- a/clang/test/AST/ast-dump-temporaries-json.cpp +++ b/clang/test/AST/ast-dump-temporaries-json.cpp @@ -36,7 +36,6 @@ void MaterializeTemp() { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "const S", // CHECK-NEXT: "qualType": "const S" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -58,7 +57,6 @@ void MaterializeTemp() { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "const S", // CHECK-NEXT: "qualType": "const S" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "lvalue", @@ -89,7 +87,6 @@ void MaterializeTemp() { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "const S", // CHECK-NEXT: "qualType": "const S" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", @@ -111,7 +108,6 @@ void MaterializeTemp() { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "S", // CHECK-NEXT: "qualType": "S" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", @@ -141,7 +137,6 @@ void MaterializeTemp() { // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "S", // CHECK-NEXT: "qualType": "S" // CHECK-NEXT: }, // CHECK-NEXT: "valueCategory": "prvalue", diff --git a/clang/test/AST/ast-dump-types-json.cpp b/clang/test/AST/ast-dump-types-json.cpp index 0a92483fb1c7f..c1bb9266fa869 100644 --- a/clang/test/AST/ast-dump-types-json.cpp +++ b/clang/test/AST/ast-dump-types-json.cpp @@ -101,7 +101,6 @@ using ::TestUsingShadowDeclType; // CHECK-NEXT: }, // CHECK-NEXT: "name": "TestElaboratedType2", // CHECK-NEXT: "type": { -// CHECK-NEXT: "desugaredQualType": "NS::S", // CHECK-NEXT: "qualType": "NS::S" // CHECK-NEXT: }, // CHECK-NEXT: "inner": [ diff --git a/clang/test/AST/coroutine-locals-cleanup.cpp b/clang/test/AST/coroutine-locals-cleanup.cpp index 6eb6fc0948cbb..ce106b8e230a1 100644 --- a/clang/test/AST/coroutine-locals-cleanup.cpp +++ b/clang/test/AST/coroutine-locals-cleanup.cpp @@ -85,7 +85,7 @@ Task bar() { // CHECK: CaseStmt // CHECK: ExprWithCleanups {{.*}} 'void' // CHECK-NEXT: CoawaitExpr -// CHECK-NEXT: CXXBindTemporaryExpr {{.*}} 'Task':'Task' (CXXTemporary {{.*}}) +// CHECK-NEXT: CXXBindTemporaryExpr {{.*}} 'Task' (CXXTemporary {{.*}}) // CHECK: MaterializeTemporaryExpr {{.*}} 'Awaiter':'Task::Awaiter' // CHECK: ExprWithCleanups {{.*}} 'bool' // CHECK-NEXT: CXXMemberCallExpr {{.*}} 'bool' @@ -98,7 +98,7 @@ Task bar() { // CHECK: CaseStmt // CHECK: ExprWithCleanups {{.*}} 'void' // CHECK-NEXT: CoawaitExpr -// CHECK-NEXT: CXXBindTemporaryExpr {{.*}} 'Task':'Task' (CXXTemporary {{.*}}) +// CHECK-NEXT: CXXBindTemporaryExpr {{.*}} 'Task' (CXXTemporary {{.*}}) // CHECK: MaterializeTemporaryExpr {{.*}} 'Awaiter':'Task::Awaiter' // CHECK: ExprWithCleanups {{.*}} 'bool' // CHECK-NEXT: CXXMemberCallExpr {{.*}} 'bool' diff --git a/clang/test/AST/float16.cpp b/clang/test/AST/float16.cpp index 9e0d70b9a1c00..a9e1144cf0958 100644 --- a/clang/test/AST/float16.cpp +++ b/clang/test/AST/float16.cpp @@ -85,7 +85,7 @@ auto C = -1.0f16 + B; //CHECK-NEXT: | `-ImplicitCastExpr {{.*}} '__fp16' //CHECK-NEXT: | `-UnaryOperator {{.*}} 'double' prefix '-' //CHECK-NEXT: | `-FloatingLiteral {{.*}} 'double' 1.000000e-01 -//CHECK-NEXT: |-VarDecl {{.*}} C 'float':'float' cinit +//CHECK-NEXT: |-VarDecl {{.*}} C 'float' cinit //CHECK-NEXT: | `-BinaryOperator {{.*}} 'float' '+' //CHECK-NEXT: | |-ImplicitCastExpr {{.*}} 'float' //CHECK-NEXT: | | `-UnaryOperator {{.*}} '_Float16' prefix '-' @@ -100,7 +100,7 @@ auto C = -1.0f16 + B; //CHECK-NATIVE: | `-ImplicitCastExpr {{.*}} '__fp16' //CHECK-NATIVE: | `-UnaryOperator {{.*}} 'double' prefix '-' //CHECK-NATIVE: | `-FloatingLiteral {{.*}} 'double' 1.000000e-01 -//CHECK-NATIVE: |-VarDecl {{.*}} C '__fp16':'__fp16' cinit +//CHECK-NATIVE: |-VarDecl {{.*}} C '__fp16' cinit //CHECK-NATIVE: | `-BinaryOperator {{.*}} '__fp16' '+' //CHECK-NATIVE: | |-ImplicitCastExpr {{.*}} '__fp16' //CHECK-NATIVE: | | `-UnaryOperator {{.*}} '_Float16' prefix '-' @@ -178,12 +178,12 @@ template C func1t(C arg) { //CHECK-NEXT: | | `-FloatingLiteral {{.*}} '_Float16' 2.000000e+00 //CHECK-NEXT: | `-FunctionDecl {{.*}} used func1t '_Float16 (_Float16)' //CHECK-NEXT: | |-TemplateArgument type '_Float16' -//CHECK: | |-ParmVarDecl {{.*}} used arg '_Float16':'_Float16' +//CHECK: | |-ParmVarDecl {{.*}} used arg '_Float16' //CHECK-NEXT: | `-CompoundStmt //CHECK-NEXT: | `-ReturnStmt //CHECK-NEXT: | `-BinaryOperator {{.*}} '_Float16' '*' -//CHECK-NEXT: | |-ImplicitCastExpr {{.*}} '_Float16':'_Float16' -//CHECK-NEXT: | | `-DeclRefExpr {{.*}} '_Float16':'_Float16' lvalue ParmVar {{.*}} 'arg' '_Float16':'_Float16' +//CHECK-NEXT: | |-ImplicitCastExpr {{.*}} '_Float16' +//CHECK-NEXT: | | `-DeclRefExpr {{.*}} '_Float16' lvalue ParmVar {{.*}} 'arg' '_Float16' //CHECK-NEXT: | `-FloatingLiteral {{.*}} '_Float16' 2.000000e+00 @@ -223,14 +223,14 @@ int main(void) { //CHECK-NEXT: | `-FloatingLiteral {{.*}} 'double' 1.000977e+00 C1 c1(f1l); -//CHECK: | `-VarDecl{{.*}} used c1 'C1':'C1' callinit -//CHECK-NEXT: | `-CXXConstructExpr {{.*}} 'C1':'C1' 'void (_Float16) +//CHECK: | `-VarDecl{{.*}} used c1 'C1' callinit +//CHECK-NEXT: | `-CXXConstructExpr {{.*}} 'C1' 'void (_Float16) //CHECK-NEXT: | `-ImplicitCastExpr {{.*}} '_Float16' //CHECK-NEXT: | `-DeclRefExpr {{.*}} '_Float16' lvalue Var 0x{{.*}} 'f1l' '_Float16' S1<_Float16> s1 = { 132.f16 }; -//CHECK: | `-VarDecl {{.*}} used s1 'S1<_Float16>':'S1<_Float16>' cinit -//CHECK-NEXT: | `-InitListExpr {{.*}} 'S1<_Float16>':'S1<_Float16>' +//CHECK: | `-VarDecl {{.*}} used s1 'S1<_Float16>' cinit +//CHECK-NEXT: | `-InitListExpr {{.*}} 'S1<_Float16>' //CHECK-NEXT: | `-FloatingLiteral {{.*}} '_Float16' 1.320000e+02 _Float16 f4l = func1n(f1l) + func1f(f2l) + c1.func1c(f3l) + c1.func2c(f1l) + @@ -255,37 +255,37 @@ int main(void) { //CHECK-NEXT: | | | | | | | `-DeclRefExpr {{.*}} '_Float16' lvalue Var {{.*}} 'f2l' '_Float16' //CHECK-NEXT: | | | | | | `-CXXMemberCallExpr {{.*}} '_Float16' //CHECK-NEXT: | | | | | | |-MemberExpr {{.*}} '' .func1c {{.*}} -//CHECK-NEXT: | | | | | | | `-DeclRefExpr {{.*}} 'C1':'C1' lvalue Var {{.*}} 'c1' 'C1':'C1' +//CHECK-NEXT: | | | | | | | `-DeclRefExpr {{.*}} 'C1' lvalue Var {{.*}} 'c1' 'C1' //CHECK-NEXT: | | | | | | `-ImplicitCastExpr {{.*}} '_Float16' //CHECK-NEXT: | | | | | | `-DeclRefExpr {{.*}} '_Float16' lvalue Var {{.*}} 'f3l' '_Float16' //CHECK-NEXT: | | | | | `-CallExpr {{.*}} '_Float16' //CHECK-NEXT: | | | | | |-ImplicitCastExpr {{.*}} '_Float16 (*)(_Float16)' //CHECK-NEXT: | | | | | | `-MemberExpr {{.*}} '_Float16 (_Float16)' lvalue .func2c {{.*}} -//CHECK-NEXT: | | | | | | `-DeclRefExpr {{.*}} 'C1':'C1' lvalue Var {{.*}} 'c1' 'C1':'C1' +//CHECK-NEXT: | | | | | | `-DeclRefExpr {{.*}} 'C1' lvalue Var {{.*}} 'c1' 'C1' //CHECK-NEXT: | | | | | `-ImplicitCastExpr {{.*}} '_Float16' //CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} '_Float16' lvalue Var {{.*}} 'f1l' '_Float16' -//CHECK-NEXT: | | | | `-CallExpr {{.*}} '_Float16':'_Float16' +//CHECK-NEXT: | | | | `-CallExpr {{.*}} '_Float16' //CHECK-NEXT: | | | | |-ImplicitCastExpr {{.*}} '_Float16 (*)(_Float16)' //CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} '_Float16 (_Float16)' lvalue Function {{.*}} 'func1t' '_Float16 (_Float16)' (FunctionTemplate {{.*}} 'func1t') //CHECK-NEXT: | | | | `-ImplicitCastExpr {{.*}} '_Float16' //CHECK-NEXT: | | | | `-DeclRefExpr {{.*}} '_Float16' lvalue Var {{.*}} 'f1l' '_Float16' //CHECK-NEXT: | | | `-ImplicitCastExpr {{.*}} '_Float16' //CHECK-NEXT: | | | `-MemberExpr {{.*}} '_Float16' lvalue .mem2 {{.*}} -//CHECK-NEXT: | | | `-DeclRefExpr {{.*}} 'S1<_Float16>':'S1<_Float16>' lvalue Var {{.*}} 's1' 'S1<_Float16>':'S1<_Float16>' +//CHECK-NEXT: | | | `-DeclRefExpr {{.*}} 'S1<_Float16>' lvalue Var {{.*}} 's1' 'S1<_Float16>' //CHECK-NEXT: | | `-ImplicitCastExpr {{.*}} '_Float16' //CHECK-NEXT: | | `-DeclRefExpr {{.*}} '_Float16' lvalue Var {{.*}} 'f1n' '_Float16' //CHECK-NEXT: | `-ImplicitCastExpr {{.*}} '_Float16' //CHECK-NEXT: | `-DeclRefExpr {{.*}} '_Float16' lvalue Var {{.*}} 'f2n' '_Float16' auto f5l = -1.f16, *f6l = &f2l, f7l = func1t(f3l); -//CHECK: | |-VarDecl {{.*}} f5l '_Float16':'_Float16' cinit +//CHECK: | |-VarDecl {{.*}} f5l '_Float16' cinit //CHECK-NEXT: | | `-UnaryOperator {{.*}} '_Float16' prefix '-' //CHECK-NEXT: | | `-FloatingLiteral {{.*}} '_Float16' 1.000000e+00 //CHECK-NEXT: | |-VarDecl {{.*}} f6l '_Float16 *' cinit //CHECK-NEXT: | | `-UnaryOperator {{.*}} '_Float16 *' prefix '&' //CHECK-NEXT: | | `-DeclRefExpr {{.*}} '_Float16' lvalue Var {{.*}} 'f2l' '_Float16' -//CHECK-NEXT: | `-VarDecl {{.*}} f7l '_Float16':'_Float16' cinit -//CHECK-NEXT: | `-CallExpr {{.*}} '_Float16':'_Float16' +//CHECK-NEXT: | `-VarDecl {{.*}} f7l '_Float16' cinit +//CHECK-NEXT: | `-CallExpr {{.*}} '_Float16' //CHECK-NEXT: | |-ImplicitCastExpr {{.*}} '_Float16 (*)(_Float16)' //CHECK-NEXT: | | `-DeclRefExpr {{.*}} '_Float16 (_Float16)' lvalue Function {{.*}} 'func1t' '_Float16 (_Float16)' (FunctionTemplate {{.*}} 'func1t') //CHECK-NEXT: | `-ImplicitCastExpr {{.*}} '_Float16' diff --git a/clang/test/AST/nrvo.c b/clang/test/AST/nrvo.c index a3e12759ad0d9..078445cd972c4 100644 --- a/clang/test/AST/nrvo.c +++ b/clang/test/AST/nrvo.c @@ -7,11 +7,11 @@ struct A f1(void) { // CHECK-NEXT: CompoundStmt 0x{{[^ ]*}} struct A a; // CHECK-NEXT: DeclStmt 0x{{[^ ]*}} - // CHECK-NEXT: VarDecl 0x{{[^ ]*}} col:12 used a 'struct A':'struct A' nrvo + // CHECK-NEXT: VarDecl 0x{{[^ ]*}} col:12 used a 'struct A' nrvo return a; // CHECK-NEXT: ReturnStmt 0x{{[^ ]*}} - // CHECK-NEXT: ImplicitCastExpr 0x{{[^ ]*}} 'struct A':'struct A' - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'struct A':'struct A' lvalue Var 0x{{[^ ]*}} 'a' 'struct A':'struct A' + // CHECK-NEXT: ImplicitCastExpr 0x{{[^ ]*}} 'struct A' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'struct A' lvalue Var 0x{{[^ ]*}} 'a' 'struct A' } void f2(void) { @@ -20,10 +20,10 @@ void f2(void) { // CHECK-NEXT: CompoundStmt 0x{{[^ ]*}} struct A a; // CHECK-NEXT: DeclStmt 0x{{[^ ]*}} - // CHECK-NEXT: VarDecl 0x{{[^ ]*}} col:14 used a 'struct A':'struct A' nrvo + // CHECK-NEXT: VarDecl 0x{{[^ ]*}} col:14 used a 'struct A' nrvo return a; // CHECK-NEXT: ReturnStmt 0x{{[^ ]*}} - // CHECK-NEXT: ImplicitCastExpr 0x{{[^ ]*}} 'struct A':'struct A' - // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'struct A':'struct A' lvalue Var 0x{{[^ ]*}} 'a' 'struct A':'struct A' + // CHECK-NEXT: ImplicitCastExpr 0x{{[^ ]*}} 'struct A' + // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'struct A' lvalue Var 0x{{[^ ]*}} 'a' 'struct A' }(); } diff --git a/clang/test/AST/sourceranges.cpp b/clang/test/AST/sourceranges.cpp index 40135bd2e17c6..f78d34c1ee7e3 100644 --- a/clang/test/AST/sourceranges.cpp +++ b/clang/test/AST/sourceranges.cpp @@ -49,14 +49,14 @@ void construct() { A a = A(12); // CHECK: CXXConstructExpr {{0x[0-9a-fA-F]+}} 'A':'foo::A' 'void (int){{( __attribute__\(\(thiscall\)\))?}}' D d = D(12); - // CHECK: CXXConstructExpr {{0x[0-9a-fA-F]+}} 'D':'D' 'void (int){{( __attribute__\(\(thiscall\)\))?}}' + // CHECK: CXXConstructExpr {{0x[0-9a-fA-F]+}} 'D' 'void (int){{( __attribute__\(\(thiscall\)\))?}}' } namespace PR38987 { struct A { A(); }; template void f() { T{}; } template void f(); -// CHECK: CXXTemporaryObjectExpr {{.*}} 'PR38987::A':'PR38987::A' +// CHECK: CXXTemporaryObjectExpr {{.*}} 'PR38987::A' } void abort() __attribute__((noreturn)); diff --git a/clang/test/Analysis/Checkers/WebKit/call-args-dynamic-downcast.cpp b/clang/test/Analysis/Checkers/WebKit/call-args-dynamic-downcast.cpp new file mode 100644 index 0000000000000..28156623d9a0f --- /dev/null +++ b/clang/test/Analysis/Checkers/WebKit/call-args-dynamic-downcast.cpp @@ -0,0 +1,35 @@ +// RUN: %clang_analyze_cc1 -analyzer-checker=alpha.webkit.UncountedCallArgsChecker -verify %s +// expected-no-diagnostics + +class Base { +public: + inline void ref(); + inline void deref(); +}; + +class Derived : public Base { +public: + virtual ~Derived(); + + void ref() const; + void deref() const; +}; + +class SubDerived final : public Derived { +}; + +class OtherObject { +public: + Derived* obj(); +}; + +template +inline Target* dynamicDowncast(Source* source) +{ + return static_cast(source); +} + +void foo(OtherObject* other) +{ + dynamicDowncast(other->obj()); +} diff --git a/clang/test/Analysis/Checkers/WebKit/call-args.cpp b/clang/test/Analysis/Checkers/WebKit/call-args.cpp index a56c4222adb51..716219836e6b4 100644 --- a/clang/test/Analysis/Checkers/WebKit/call-args.cpp +++ b/clang/test/Analysis/Checkers/WebKit/call-args.cpp @@ -262,22 +262,6 @@ namespace param_forwarding_method { } } -namespace make_ref { - void makeRef(RefCountable*) {} - void makeRefPtr(RefCountable*) {} - void makeWeakPtr(RefCountable*) {} - void makeWeakPtr(RefCountable&) {} - - void foo() { - makeRef(provide()); - makeRefPtr(provide()); - RefPtr a(provide()); - Ref b(provide()); - makeWeakPtr(provide()); - makeWeakPtr(*provide()); - } -} - namespace downcast { void consume_ref_countable(RefCountable*) {} RefCountable* downcast(RefCountable*) { return nullptr; } diff --git a/clang/test/Analysis/analyzer-config.c b/clang/test/Analysis/analyzer-config.c index 794ef8b9cc086..8abfbf84983d8 100644 --- a/clang/test/Analysis/analyzer-config.c +++ b/clang/test/Analysis/analyzer-config.c @@ -11,6 +11,7 @@ // CHECK-NEXT: alpha.osx.cocoa.DirectIvarAssignment:AnnotatedFunctions = false // CHECK-NEXT: alpha.security.MmapWriteExec:MmapProtExec = 0x04 // CHECK-NEXT: alpha.security.MmapWriteExec:MmapProtRead = 0x01 +// CHECK-NEXT: alpha.security.cert.env.InvalidPtr:InvalidatingGetEnv = false // CHECK-NEXT: alpha.security.taint.TaintPropagation:Config = "" // CHECK-NEXT: alpha.unix.Errno:AllowErrnoReadOutsideConditionExpressions = true // CHECK-NEXT: apply-fixits = false diff --git a/clang/test/Analysis/cert/env34-c-cert-examples.c b/clang/test/Analysis/cert/env34-c-cert-examples.c index 19ca73f34c7ee..6d6659e55d86b 100644 --- a/clang/test/Analysis/cert/env34-c-cert-examples.c +++ b/clang/test/Analysis/cert/env34-c-cert-examples.c @@ -1,15 +1,48 @@ +// Default options. // RUN: %clang_analyze_cc1 \ // RUN: -analyzer-checker=core,alpha.security.cert.env.InvalidPtr \ // RUN: -verify -Wno-unused %s +// +// Test the laxer handling of getenv function (this is the default). +// RUN: %clang_analyze_cc1 \ +// RUN: -analyzer-checker=core,alpha.security.cert.env.InvalidPtr \ +// RUN: -analyzer-config alpha.security.cert.env.InvalidPtr:InvalidatingGetEnv=false \ +// RUN: -verify -Wno-unused %s +// +// Test the stricter handling of getenv function. +// RUN: %clang_analyze_cc1 \ +// RUN: -analyzer-checker=core,alpha.security.cert.env.InvalidPtr \ +// RUN: -analyzer-config alpha.security.cert.env.InvalidPtr:InvalidatingGetEnv=true \ +// RUN: -verify=expected,pedantic -Wno-unused %s #include "../Inputs/system-header-simulator.h" char *getenv(const char *name); +int setenv(const char *name, const char *value, int overwrite); int strcmp(const char*, const char*); char *strdup(const char*); void free(void *memblock); void *malloc(size_t size); -void incorrect_usage(void) { +void incorrect_usage_setenv_getenv_invalidation(void) { + char *tmpvar; + char *tempvar; + + tmpvar = getenv("TMP"); + + if (!tmpvar) + return; + + setenv("TEMP", "", 1); //setenv can invalidate env + + if (!tmpvar) + return; + + if (strcmp(tmpvar, "") == 0) { // body of strcmp is unknown + // expected-warning@-1{{use of invalidated pointer 'tmpvar' in a function call}} + } +} + +void incorrect_usage_double_getenv_invalidation(void) { char *tmpvar; char *tempvar; @@ -18,13 +51,13 @@ void incorrect_usage(void) { if (!tmpvar) return; - tempvar = getenv("TEMP"); + tempvar = getenv("TEMP"); //getenv should not invalidate env in non-pedantic mode if (!tempvar) return; if (strcmp(tmpvar, tempvar) == 0) { // body of strcmp is unknown - // expected-warning@-1{{use of invalidated pointer 'tmpvar' in a function call}} + // pedantic-warning@-1{{use of invalidated pointer 'tmpvar' in a function call}} } } diff --git a/clang/test/Analysis/cert/env34-c.c b/clang/test/Analysis/cert/env34-c.c index dc7b0340c311e..94bc2cf95ccc9 100644 --- a/clang/test/Analysis/cert/env34-c.c +++ b/clang/test/Analysis/cert/env34-c.c @@ -1,5 +1,6 @@ // RUN: %clang_analyze_cc1 \ // RUN: -analyzer-checker=alpha.security.cert.env.InvalidPtr\ +// RUN: -analyzer-config alpha.security.cert.env.InvalidPtr:InvalidatingGetEnv=true \ // RUN: -analyzer-output=text -verify -Wno-unused %s #include "../Inputs/system-header-simulator.h" diff --git a/clang/test/Analysis/cfg-openmp.cpp b/clang/test/Analysis/cfg-openmp.cpp index 9ab14af4bc753..d7de34bdaa0ec 100644 --- a/clang/test/Analysis/cfg-openmp.cpp +++ b/clang/test/Analysis/cfg-openmp.cpp @@ -22,7 +22,7 @@ void target_has_device_addr(int argc) { } // OMP51-LABEL: void target_s_has_device_addr(int argc) void target_s_has_device_addr(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // OMP51-DAG: [B3] // OMP51-DAG: [[#TSB:]]: x // OMP51-DAG: [[#TSB+1]]: [B3.[[#TSB]]] (ImplicitCastExpr, LValueToRValue, int) @@ -35,14 +35,14 @@ void target_s_has_device_addr(int argc) { // OMP51-DAG: [[#TS+3]]: fp // OMP51-DAG: [[#TS+4]]: rd // OMP51-DAG: [[#TS+5]]: lin -// OMP51-DAG: [[#TS+6]]: step +// OMP51-DAG: [[#TS+6]]: step_sz // OMP51-DAG: [[#TS+7]]: [B1.[[#TS+6]]] (ImplicitCastExpr, LValueToRValue, int) // OMP51-DAG: [[#TS+8]]: [B3.[[#TSB+2]]] // OMP51-DAG: [[#TS+9]]: [B3.[[#TSB]]] -// OMP51-DAG: [[#TS+10]]: #pragma omp target simd if(cond) firstprivate(fp) reduction(+: rd) linear(lin: step) has_device_addr(map) +// OMP51-DAG: [[#TS+10]]: #pragma omp target simd if(cond) firstprivate(fp) reduction(+: rd) linear(lin: step(step_sz)) has_device_addr(map) // OMP51-DAG: for (int i = 0; // OMP51-DAG: [B3.[[#TSB+3]]]; -#pragma omp target simd if(cond) firstprivate(fp) reduction(+:rd) linear(lin: step) has_device_addr(map) +#pragma omp target simd if(cond) firstprivate(fp) reduction(+:rd) linear(lin: step_sz) has_device_addr(map) for (int i = 0; i < 10; ++i) argc = x; } @@ -129,9 +129,9 @@ void xxx(int argc) { // CHECK-NEXT: 3: int fp; // CHECK-NEXT: 4: int rd; // CHECK-NEXT: 5: int lin; -// CHECK-NEXT: 6: int step; +// CHECK-NEXT: 6: int step_sz; // CHECK-NEXT: 7: int map; - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-NEXT: [[#ATOM:]]: x // CHECK-NEXT: [[#ATOM+1]]: [B1.[[#ATOM]]] (ImplicitCastExpr, LValueToRValue, int) // CHECK-NEXT: [[#ATOM+2]]: argc @@ -294,7 +294,7 @@ void xxx(int argc) { // CHECK-LABEL: void dpf(int argc) void dpf(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B3] // CHECK-DAG: [[#DPFB:]]: x // CHECK-DAG: [[#DPFB+1]]: [B3.[[#DPFB]]] (ImplicitCastExpr, LValueToRValue, int) @@ -316,7 +316,7 @@ void dpf(int argc) { // CHECK-LABEL: void dpfs(int argc) void dpfs(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B3] // CHECK-DAG: [[#DPFSB:]]: x // CHECK-DAG: [[#DPFSB+1]]: [B3.[[#DPFSB]]] (ImplicitCastExpr, LValueToRValue, int) @@ -338,7 +338,7 @@ void dpfs(int argc) { // CHECK-LABEL: void ds(int argc) void ds(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B3] // CHECK-DAG: [[#DSB:]]: x // CHECK-DAG: [[#DSB+1]]: [B3.[[#DSB]]] (ImplicitCastExpr, LValueToRValue, int) @@ -355,7 +355,7 @@ void ds(int argc) { // CHECK-LABEL: void for_fn(int argc) void for_fn(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B3] // CHECK-DAG: [[#FORB:]]: x // CHECK-DAG: [[#FORB+1]]: [B3.[[#FORB]]] (ImplicitCastExpr, LValueToRValue, int) @@ -363,19 +363,19 @@ void for_fn(int argc) { // CHECK-DAG: [[#FORB+3]]: [B3.[[#FORB+2]]] = [B3.[[#FORB+1]]] // CHECK-DAG: [B1] // CHECK-DAG: [[#FOR:]]: lin -// CHECK-DAG: [[#FOR+1]]: step +// CHECK-DAG: [[#FOR+1]]: step_sz // CHECK-DAG: [[#FOR+2]]: [B1.[[#FOR+1]]] (ImplicitCastExpr, LValueToRValue, int) -// CHECK-DAG: [[#FOR+3]]: #pragma omp for linear(lin: step) +// CHECK-DAG: [[#FOR+3]]: #pragma omp for linear(lin: step(step_sz)) // CHECK-DAG: for (int i = 0; // CHECK-DAG: [B3.[[#FORB+3]]]; -#pragma omp for linear(lin : step) +#pragma omp for linear(lin : step_sz) for (int i = 0; i < 10; ++i) argc = x; } // CHECK-LABEL: void fs(int argc) void fs(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B3] // CHECK-DAG: [[#FSB:]]: x // CHECK-DAG: [[#FSB+1]]: [B3.[[#FSB]]] (ImplicitCastExpr, LValueToRValue, int) @@ -383,19 +383,19 @@ void fs(int argc) { // CHECK-DAG: [[#FSB+3]]: [B3.[[#FSB+2]]] = [B3.[[#FSB+1]]] // CHECK-DAG: [B1] // CHECK-DAG: [[#FS:]]: lin -// CHECK-DAG: [[#FS+1]]: step +// CHECK-DAG: [[#FS+1]]: step_sz // CHECK-DAG: [[#FS+2]]: [B1.[[#FS+1]]] (ImplicitCastExpr, LValueToRValue, int) -// CHECK-DAG: [[#FS+3]]: #pragma omp for simd linear(lin: step) +// CHECK-DAG: [[#FS+3]]: #pragma omp for simd linear(lin: step(step_sz)) // CHECK-DAG: for (int i = 0; // CHECK-DAG: [B3.[[#FSB+3]]]; -#pragma omp for simd linear(lin: step) +#pragma omp for simd linear(lin: step_sz) for (int i = 0; i < 10; ++i) argc = x; } // CHECK-LABEL: void ord(int argc) void ord(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B3] // CHECK-DAG: [[#ORDB:]]: x // CHECK-DAG: [[#ORDB+1]]: [B3.[[#ORDB]]] (ImplicitCastExpr, LValueToRValue, int) @@ -416,7 +416,7 @@ void ord(int argc) { // CHECK-LABEL: void pf(int argc) void pf(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B3] // CHECK-DAG: [[#PFB:]]: x // CHECK-DAG: [[#PFB+1]]: [B3.[[#PFB]]] (ImplicitCastExpr, LValueToRValue, int) @@ -429,19 +429,19 @@ void pf(int argc) { // CHECK-DAG: [[#PF+3]]: fp // CHECK-DAG: [[#PF+4]]: rd // CHECK-DAG: [[#PF+5]]: lin -// CHECK-DAG: [[#PF+6]]: step +// CHECK-DAG: [[#PF+6]]: step_sz // CHECK-DAG: [[#PF+7]]: [B1.[[#PF+6]]] (ImplicitCastExpr, LValueToRValue, int) -// CHECK-DAG: [[#PF+8]]: #pragma omp parallel for if(cond) firstprivate(fp) reduction(&: rd) linear(lin: step) +// CHECK-DAG: [[#PF+8]]: #pragma omp parallel for if(cond) firstprivate(fp) reduction(&: rd) linear(lin: step(step_sz)) // CHECK-DAG: for (int i = 0; // CHECK-DAG: [B3.[[#PFB+3]]]; -#pragma omp parallel for if(cond) firstprivate(fp) reduction(&:rd) linear(lin: step) +#pragma omp parallel for if(cond) firstprivate(fp) reduction(&:rd) linear(lin: step_sz) for (int i = 0; i < 10; ++i) argc = x; } // CHECK-LABEL: void pfs(int argc) void pfs(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B3] // CHECK-DAG: [[#PFSB:]]: x // CHECK-DAG: [[#PFSB+1]]: [B3.[[#PFSB]]] (ImplicitCastExpr, LValueToRValue, int) @@ -454,19 +454,19 @@ void pfs(int argc) { // CHECK-DAG: [[#PFS+3]]: fp // CHECK-DAG: [[#PFS+4]]: rd // CHECK-DAG: [[#PFS+5]]: lin -// CHECK-DAG: [[#PFS+6]]: step +// CHECK-DAG: [[#PFS+6]]: step_sz // CHECK-DAG: [[#PFS+7]]: [B1.[[#PFS+6]]] (ImplicitCastExpr, LValueToRValue, int) -// CHECK-DAG: [[#PFS+8]]: #pragma omp parallel for simd if(cond) firstprivate(fp) reduction(|: rd) linear(lin: step) +// CHECK-DAG: [[#PFS+8]]: #pragma omp parallel for simd if(cond) firstprivate(fp) reduction(|: rd) linear(lin: step(step_sz)) // CHECK-DAG: for (int i = 0; // CHECK-DAG: [B3.[[#PFSB+3]]]; -#pragma omp parallel for simd if(cond) firstprivate(fp) reduction(|:rd) linear(lin: step) +#pragma omp parallel for simd if(cond) firstprivate(fp) reduction(|:rd) linear(lin: step_sz) for (int i = 0; i < 10; ++i) argc = x; } // CHECK-LABEL: void simd(int argc) void simd(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B3] // CHECK-DAG: [[#SIMDB:]]: x // CHECK-DAG: [[#SIMDB+1]]: [B3.[[#SIMDB]]] (ImplicitCastExpr, LValueToRValue, int) @@ -474,19 +474,19 @@ void simd(int argc) { // CHECK-DAG: [[#SIMDB+3]]: [B3.[[#SIMDB+2]]] = [B3.[[#SIMDB+1]]] // CHECK-DAG: [B1] // CHECK-DAG: [[#SIMD:]]: lin -// CHECK-DAG: [[#SIMD+1]]: step +// CHECK-DAG: [[#SIMD+1]]: step_sz // CHECK-DAG: [[#SIMD+2]]: [B1.[[#SIMD+1]]] (ImplicitCastExpr, LValueToRValue, int) -// CHECK-DAG: [[#SIMD+3]]: #pragma omp simd linear(lin: step) +// CHECK-DAG: [[#SIMD+3]]: #pragma omp simd linear(lin: step(step_sz)) // CHECK-DAG: for (int i = 0; // CHECK-DAG: [B3.[[#SIMDB+3]]]; -#pragma omp simd linear(lin: step) +#pragma omp simd linear(lin: step_sz) for (int i = 0; i < 10; ++i) argc = x; } // CHECK-LABEL: void tpf(int argc) void tpf(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B3] // CHECK-DAG: [[#TPFB:]]: x // CHECK-DAG: [[#TPFB+1]]: [B3.[[#TPFB]]] (ImplicitCastExpr, LValueToRValue, int) @@ -499,22 +499,22 @@ void tpf(int argc) { // CHECK-DAG: [[#TPF+3]]: fp // CHECK-DAG: [[#TPF+4]]: rd // CHECK-DAG: [[#TPF+5]]: lin -// CHECK-DAG: [[#TPF+6]]: step +// CHECK-DAG: [[#TPF+6]]: step_sz // CHECK-DAG: [[#TPF+7]]: [B1.[[#TPF+6]]] (ImplicitCastExpr, LValueToRValue, int) // CHECK-DAG: [[#TPF+8]]: map // CHECK-DAG: [[#TPF+9]]: [B3.[[#TPFB+2]]] // CHECK-DAG: [[#TPF+10]]: [B3.[[#TPFB]]] -// CHECK-DAG: [[#TPF+11]]: #pragma omp target parallel for if(parallel: cond) firstprivate(fp) reduction(max: rd) linear(lin: step) map(tofrom: map) +// CHECK-DAG: [[#TPF+11]]: #pragma omp target parallel for if(parallel: cond) firstprivate(fp) reduction(max: rd) linear(lin: step(step_sz)) map(tofrom: map) // CHECK-DAG: for (int i = 0; // CHECK-DAG: [B3.[[#TPFB+3]]]; -#pragma omp target parallel for if(parallel:cond) firstprivate(fp) reduction(max:rd) linear(lin: step) map(map) +#pragma omp target parallel for if(parallel:cond) firstprivate(fp) reduction(max:rd) linear(lin: step_sz) map(map) for (int i = 0; i < 10; ++i) argc = x; } // CHECK-LABEL: void tpfs(int argc) void tpfs(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B3] // CHECK-DAG: [[#TPFSB:]]: x // CHECK-DAG: [[#TPFSB+1]]: [B3.[[#TPFSB]]] (ImplicitCastExpr, LValueToRValue, int) @@ -527,22 +527,22 @@ void tpfs(int argc) { // CHECK-DAG: [[#TPFS+3]]: fp // CHECK-DAG: [[#TPFS+4]]: rd // CHECK-DAG: [[#TPFS+5]]: lin -// CHECK-DAG: [[#TPFS+6]]: step +// CHECK-DAG: [[#TPFS+6]]: step_sz // CHECK-DAG: [[#TPFS+7]]: [B1.[[#TPFS+6]]] (ImplicitCastExpr, LValueToRValue, int) // CHECK-DAG: [[#TPFS+8]]: map // CHECK-DAG: [[#TPFS+9]]: [B3.[[#TPFSB+2]]] // CHECK-DAG: [[#TPFS+10]]: [B3.[[#TPFSB]]] -// CHECK-DAG: [[#TPFS+11]]: #pragma omp target parallel for simd if(target: cond) firstprivate(fp) reduction(*: rd) linear(lin: step) map(tofrom: map) +// CHECK-DAG: [[#TPFS+11]]: #pragma omp target parallel for simd if(target: cond) firstprivate(fp) reduction(*: rd) linear(lin: step(step_sz)) map(tofrom: map) // CHECK-DAG: for (int i = 0; // CHECK-DAG: [B3.[[#TPFSB+3]]]; -#pragma omp target parallel for simd if(target:cond) firstprivate(fp) reduction(*:rd) linear(lin: step) map(tofrom:map) +#pragma omp target parallel for simd if(target:cond) firstprivate(fp) reduction(*:rd) linear(lin: step_sz) map(tofrom:map) for (int i = 0; i < 10; ++i) argc = x; } // CHECK-LABEL: void ts(int argc) void ts(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B3] // CHECK-DAG: [[#TSB:]]: x // CHECK-DAG: [[#TSB+1]]: [B3.[[#TSB]]] (ImplicitCastExpr, LValueToRValue, int) @@ -555,21 +555,21 @@ void ts(int argc) { // CHECK-DAG: [[#TS+3]]: fp // CHECK-DAG: [[#TS+4]]: rd // CHECK-DAG: [[#TS+5]]: lin -// CHECK-DAG: [[#TS+6]]: step +// CHECK-DAG: [[#TS+6]]: step_sz // CHECK-DAG: [[#TS+7]]: [B1.[[#TS+6]]] (ImplicitCastExpr, LValueToRValue, int) // CHECK-DAG: [[#TS+8]]: [B3.[[#TSB+2]]] // CHECK-DAG: [[#TS+9]]: [B3.[[#TSB]]] -// CHECK-DAG: [[#TS+10]]: #pragma omp target simd if(cond) firstprivate(fp) reduction(+: rd) linear(lin: step) map(alloc: map) +// CHECK-DAG: [[#TS+10]]: #pragma omp target simd if(cond) firstprivate(fp) reduction(+: rd) linear(lin: step(step_sz)) map(alloc: map) // CHECK-DAG: for (int i = 0; // CHECK-DAG: [B3.[[#TSB+3]]]; -#pragma omp target simd if(cond) firstprivate(fp) reduction(+:rd) linear(lin: step) map(alloc:map) +#pragma omp target simd if(cond) firstprivate(fp) reduction(+:rd) linear(lin: step_sz) map(alloc:map) for (int i = 0; i < 10; ++i) argc = x; } // CHECK-LABEL: void ttd(int argc) void ttd(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B3] // CHECK-DAG: [[#TTDB:]]: x // CHECK-DAG: [[#TTDB+1]]: [B3.[[#TTDB]]] (ImplicitCastExpr, LValueToRValue, int) @@ -593,7 +593,7 @@ void ttd(int argc) { // CHECK-LABEL: void ttdpf(int argc) void ttdpf(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B3] // CHECK-DAG: [[#TTDPFB:]]: x // CHECK-DAG: [[#TTDPFB+1]]: [B3.[[#TTDPFB]]] (ImplicitCastExpr, LValueToRValue, int) @@ -617,7 +617,7 @@ void ttdpf(int argc) { // CHECK-LABEL: void ttdpfs(int argc) void ttdpfs(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B3] // CHECK-DAG: [[#TTDPFSB:]]: x // CHECK-DAG: [[#TTDPFSB+1]]: [B3.[[#TTDPFSB]]] (ImplicitCastExpr, LValueToRValue, int) @@ -641,7 +641,7 @@ void ttdpfs(int argc) { // CHECK-LABEL: void ttds(int argc) void ttds(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B3] // CHECK-DAG: [[#TTDSB:]]: x // CHECK-DAG: [[#TTDSB+1]]: [B3.[[#TTDSB]]] (ImplicitCastExpr, LValueToRValue, int) @@ -666,7 +666,7 @@ void ttds(int argc) { // CHECK-LABEL: void tl(int argc) void tl(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B3] // CHECK-DAG: [[#TLB:]]: x // CHECK-DAG: [[#TLB+1]]: [B3.[[#TLB]]] (ImplicitCastExpr, LValueToRValue, int) @@ -690,7 +690,7 @@ void tl(int argc) { // CHECK-LABEL: void maskedtaskloop(int argc) void maskedtaskloop(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B3] // CHECK-DAG: [[#MTLB:]]: x // CHECK-DAG: [[#MTLB+1]]: [B3.[[#MTLB]]] (ImplicitCastExpr, LValueToRValue, int) @@ -714,7 +714,7 @@ void maskedtaskloop(int argc) { // CHECK-LABEL: void parallelmaskedtaskloop(int argc) void parallelmaskedtaskloop(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B3] // CHECK-DAG: [[#PMTLB:]]: x // CHECK-DAG: [[#PMTLB+1]]: [B3.[[#PMTLB]]] (ImplicitCastExpr, LValueToRValue, int) @@ -738,7 +738,7 @@ void parallelmaskedtaskloop(int argc) { // CHECK-LABEL: void parallelmaskedtasksimdloop(int argc) void parallelmaskedtasksimdloop(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B3] // CHECK-DAG: [[#PMTLSB:]]: x // CHECK-DAG: [[#PMTLSB+1]]: [B3.[[#PMTLSB]]] (ImplicitCastExpr, LValueToRValue, int) @@ -762,7 +762,7 @@ void parallelmaskedtasksimdloop(int argc) { // CHECK-LABEL: void tls(int argc) void tls(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B3] // CHECK-DAG: [[#TLSB:]]: x // CHECK-DAG: [[#TLSB+1]]: [B3.[[#TLSB]]] (ImplicitCastExpr, LValueToRValue, int) @@ -775,21 +775,21 @@ void tls(int argc) { // CHECK-DAG: [[#TLS+3]]: fp // CHECK-DAG: [[#TLS+4]]: rd // CHECK-DAG: [[#TLS+5]]: lin -// CHECK-DAG: [[#TLS+6]]: step +// CHECK-DAG: [[#TLS+6]]: step_sz // CHECK-DAG: [[#TLS+7]]: [B1.[[#TLS+6]]] (ImplicitCastExpr, LValueToRValue, int) // CHECK-DAG: [[#TLS+8]]: [B3.[[#TLSB+2]]] // CHECK-DAG: [[#TLS+9]]: [B3.[[#TLSB]]] -// CHECK-DAG: [[#TLS+10]]: #pragma omp taskloop simd if(cond) firstprivate(fp) reduction(+: rd) linear(lin: step) +// CHECK-DAG: [[#TLS+10]]: #pragma omp taskloop simd if(cond) firstprivate(fp) reduction(+: rd) linear(lin: step(step_sz)) // CHECK-DAG: for (int i = 0; // CHECK-DAG: [B3.[[#TLSB+3]]]; -#pragma omp taskloop simd if(cond) firstprivate(fp) reduction(+:rd) linear(lin: step) +#pragma omp taskloop simd if(cond) firstprivate(fp) reduction(+:rd) linear(lin: step_sz) for (int i = 0; i < 10; ++i) argc = x; } // CHECK-LABEL: void maskedtaskloopsimd(int argc) void maskedtaskloopsimd(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B3] // CHECK-DAG: [[#MTLSB:]]: x // CHECK-DAG: [[#MTLSB+1]]: [B3.[[#MTLSB]]] (ImplicitCastExpr, LValueToRValue, int) @@ -802,21 +802,21 @@ void maskedtaskloopsimd(int argc) { // CHECK-DAG: [[#MTLS+3]]: fp // CHECK-DAG: [[#MTLS+4]]: rd // CHECK-DAG: [[#MTLS+5]]: lin -// CHECK-DAG: [[#MTLS+6]]: step +// CHECK-DAG: [[#MTLS+6]]: step_sz // CHECK-DAG: [[#MTLS+7]]: [B1.[[#MTLS+6]]] (ImplicitCastExpr, LValueToRValue, int) // CHECK-DAG: [[#MTLS+8]]: [B3.[[#MTLSB+2]]] // CHECK-DAG: [[#MTLS+9]]: [B3.[[#MTLSB]]] -// CHECK-DAG: [[#MTLS+10]]: #pragma omp masked taskloop simd if(cond) firstprivate(fp) reduction(+: rd) linear(lin: step) +// CHECK-DAG: [[#MTLS+10]]: #pragma omp masked taskloop simd if(cond) firstprivate(fp) reduction(+: rd) linear(lin: step(step_sz)) // CHECK-DAG: for (int i = 0; // CHECK-DAG: [B3.[[#MTLSB+3]]]; -#pragma omp masked taskloop simd if(cond) firstprivate(fp) reduction(+:rd) linear(lin: step) +#pragma omp masked taskloop simd if(cond) firstprivate(fp) reduction(+:rd) linear(lin: step_sz) for (int i = 0; i < 10; ++i) argc = x; } // CHECK-LABEL: void tdpf(int argc) void tdpf(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B1] // CHECK-DAG: [[#TDPF:]]: [B1.{{.+}}] // CHECK-DAG: [[#TDPF+1]]: [B1.[[#TDPF+6]]] (ImplicitCastExpr, LValueToRValue, int) @@ -845,7 +845,7 @@ void tdpf(int argc) { // CHECK-LABEL: void tdpfs(int argc) void tdpfs(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B1] // CHECK-DAG: [[#TDPFS:]]: [B1.{{.+}}] // CHECK-DAG: [[#TDPFS+1]]: [B1.[[#TDPFS+6]]] (ImplicitCastExpr, LValueToRValue, int) @@ -874,7 +874,7 @@ void tdpfs(int argc) { // CHECK-LABEL: void tds(int argc) void tds(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B1] // CHECK-DAG: [[#TDS:]]: #pragma omp teams distribute simd firstprivate(fp) reduction(+: rd) // CHECK-DAG: [[#TDS-2]]: [B1.[[#TDS+1]]] @@ -899,7 +899,7 @@ void tds(int argc) { // CHECK-LABEL: void teamsloop(int argc) void teamsloop(int argc) { - int x, cond, fp, rd, lin, step, map; + int x, cond, fp, rd, lin, step_sz, map; // CHECK-DAG: [B1] // CHECK-DAG: [[#TDS:]]: #pragma omp teams loop firstprivate(fp) reduction(+: rd) // CHECK-DAG: [[#TDS-2]]: [B1.[[#TDS+1]]] diff --git a/clang/test/Analysis/enum-cast-out-of-range.c b/clang/test/Analysis/enum-cast-out-of-range.c index 3282cba653d71..4e5c9bb9ffdec 100644 --- a/clang/test/Analysis/enum-cast-out-of-range.c +++ b/clang/test/Analysis/enum-cast-out-of-range.c @@ -1,7 +1,9 @@ // RUN: %clang_analyze_cc1 \ // RUN: -analyzer-checker=core,alpha.cplusplus.EnumCastOutOfRange \ +// RUN: -analyzer-output text \ // RUN: -verify %s +// expected-note@+1 + {{enum declared here}} enum En_t { En_0 = -4, En_1, @@ -11,17 +13,23 @@ enum En_t { }; void unscopedUnspecifiedCStyle(void) { - enum En_t Below = (enum En_t)(-5); // expected-warning {{not in the valid range}} + enum En_t Below = (enum En_t)(-5); // expected-warning {{not in the valid range of values for 'En_t'}} + // expected-note@-1 {{not in the valid range of values for 'En_t'}} enum En_t NegVal1 = (enum En_t)(-4); // OK. enum En_t NegVal2 = (enum En_t)(-3); // OK. - enum En_t InRange1 = (enum En_t)(-2); // expected-warning {{not in the valid range}} - enum En_t InRange2 = (enum En_t)(-1); // expected-warning {{not in the valid range}} - enum En_t InRange3 = (enum En_t)(0); // expected-warning {{not in the valid range}} + enum En_t InRange1 = (enum En_t)(-2); // expected-warning {{not in the valid range of values for 'En_t'}} + // expected-note@-1 {{not in the valid range of values for 'En_t'}} + enum En_t InRange2 = (enum En_t)(-1); // expected-warning {{not in the valid range of values for 'En_t'}} + // expected-note@-1 {{not in the valid range of values for 'En_t'}} + enum En_t InRange3 = (enum En_t)(0); // expected-warning {{not in the valid range of values for 'En_t'}} + // expected-note@-1 {{not in the valid range of values for 'En_t'}} enum En_t PosVal1 = (enum En_t)(1); // OK. enum En_t PosVal2 = (enum En_t)(2); // OK. - enum En_t InRange4 = (enum En_t)(3); // expected-warning {{not in the valid range}} + enum En_t InRange4 = (enum En_t)(3); // expected-warning {{not in the valid range of values for 'En_t'}} + // expected-note@-1 {{not in the valid range of values for 'En_t'}} enum En_t PosVal3 = (enum En_t)(4); // OK. - enum En_t Above = (enum En_t)(5); // expected-warning {{not in the valid range}} + enum En_t Above = (enum En_t)(5); // expected-warning {{not in the valid range of values for 'En_t'}} + // expected-note@-1 {{not in the valid range of values for 'En_t'}} } enum En_t unused; @@ -32,3 +40,27 @@ void unusedExpr(void) { // generate a warning having nothing to do with this checker. unused; // expected-warning {{expression result unused}} } + +// Test typedef-ed anonymous enums +typedef enum { // expected-note {{enum declared here}} + TD_0 = 0, +} TD_t; + +void testTypeDefEnum(void) { + (void)(TD_t)(-1); // expected-warning {{not in the valid range of values for the enum}} + // expected-note@-1 {{not in the valid range of values for the enum}} +} + +// Test expression tracking +void set(int* p, int v) { + *p = v; // expected-note {{The value -1 is assigned to 'i'}} +} + + +void testTrackExpression(int i) { + set(&i, -1); // expected-note {{Passing the value -1 via 2nd parameter 'v'}} + // expected-note@-1 {{Calling 'set'}} + // expected-note@-2 {{Returning from 'set'}} + (void)(enum En_t)(i); // expected-warning {{not in the valid range of values for 'En_t'}} + // expected-note@-1 {{not in the valid range of values for 'En_t'}} +} diff --git a/clang/test/Analysis/enum-cast-out-of-range.cpp b/clang/test/Analysis/enum-cast-out-of-range.cpp index abc1431e5be14..0eb740664ecdc 100644 --- a/clang/test/Analysis/enum-cast-out-of-range.cpp +++ b/clang/test/Analysis/enum-cast-out-of-range.cpp @@ -2,6 +2,7 @@ // RUN: -analyzer-checker=core,alpha.cplusplus.EnumCastOutOfRange \ // RUN: -std=c++11 -verify %s +// expected-note@+1 + {{enum declared here}} enum unscoped_unspecified_t { unscoped_unspecified_0 = -4, unscoped_unspecified_1, @@ -10,6 +11,7 @@ enum unscoped_unspecified_t { unscoped_unspecified_4 = 4 }; +// expected-note@+1 + {{enum declared here}} enum unscoped_specified_t : int { unscoped_specified_0 = -4, unscoped_specified_1, @@ -18,6 +20,7 @@ enum unscoped_specified_t : int { unscoped_specified_4 = 4 }; +// expected-note@+1 + {{enum declared here}} enum class scoped_unspecified_t { scoped_unspecified_0 = -4, scoped_unspecified_1, @@ -26,6 +29,7 @@ enum class scoped_unspecified_t { scoped_unspecified_4 = 4 }; +// expected-note@+1 + {{enum declared here}} enum class scoped_specified_t : int { scoped_specified_0 = -4, scoped_specified_1, @@ -39,115 +43,115 @@ struct S { }; void unscopedUnspecified() { - unscoped_unspecified_t InvalidBeforeRangeBegin = static_cast(-5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + unscoped_unspecified_t InvalidBeforeRangeBegin = static_cast(-5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_unspecified_t'}} unscoped_unspecified_t ValidNegativeValue1 = static_cast(-4); // OK. unscoped_unspecified_t ValidNegativeValue2 = static_cast(-3); // OK. - unscoped_unspecified_t InvalidInsideRange1 = static_cast(-2); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} - unscoped_unspecified_t InvalidInsideRange2 = static_cast(-1); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} - unscoped_unspecified_t InvalidInsideRange3 = static_cast(0); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + unscoped_unspecified_t InvalidInsideRange1 = static_cast(-2); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_unspecified_t'}} + unscoped_unspecified_t InvalidInsideRange2 = static_cast(-1); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_unspecified_t'}} + unscoped_unspecified_t InvalidInsideRange3 = static_cast(0); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_unspecified_t'}} unscoped_unspecified_t ValidPositiveValue1 = static_cast(1); // OK. unscoped_unspecified_t ValidPositiveValue2 = static_cast(2); // OK. - unscoped_unspecified_t InvalidInsideRange4 = static_cast(3); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + unscoped_unspecified_t InvalidInsideRange4 = static_cast(3); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_unspecified_t'}} unscoped_unspecified_t ValidPositiveValue3 = static_cast(4); // OK. - unscoped_unspecified_t InvalidAfterRangeEnd = static_cast(5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + unscoped_unspecified_t InvalidAfterRangeEnd = static_cast(5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_unspecified_t'}} } void unscopedSpecified() { - unscoped_specified_t InvalidBeforeRangeBegin = static_cast(-5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + unscoped_specified_t InvalidBeforeRangeBegin = static_cast(-5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_specified_t'}} unscoped_specified_t ValidNegativeValue1 = static_cast(-4); // OK. unscoped_specified_t ValidNegativeValue2 = static_cast(-3); // OK. - unscoped_specified_t InvalidInsideRange1 = static_cast(-2); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} - unscoped_specified_t InvalidInsideRange2 = static_cast(-1); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} - unscoped_specified_t InvalidInsideRange3 = static_cast(0); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + unscoped_specified_t InvalidInsideRange1 = static_cast(-2); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_specified_t'}} + unscoped_specified_t InvalidInsideRange2 = static_cast(-1); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_specified_t'}} + unscoped_specified_t InvalidInsideRange3 = static_cast(0); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_specified_t'}} unscoped_specified_t ValidPositiveValue1 = static_cast(1); // OK. unscoped_specified_t ValidPositiveValue2 = static_cast(2); // OK. - unscoped_specified_t InvalidInsideRange4 = static_cast(3); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + unscoped_specified_t InvalidInsideRange4 = static_cast(3); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_specified_t'}} unscoped_specified_t ValidPositiveValue3 = static_cast(4); // OK. - unscoped_specified_t InvalidAfterRangeEnd = static_cast(5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + unscoped_specified_t InvalidAfterRangeEnd = static_cast(5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_specified_t'}} } void scopedUnspecified() { - scoped_unspecified_t InvalidBeforeRangeBegin = static_cast(-5); // expected-warning{{The value provided to the cast expression is not in the valid range of values for the enum}} + scoped_unspecified_t InvalidBeforeRangeBegin = static_cast(-5); // expected-warning{{The value provided to the cast expression is not in the valid range of values for 'scoped_unspecified_t'}} scoped_unspecified_t ValidNegativeValue1 = static_cast(-4); // OK. scoped_unspecified_t ValidNegativeValue2 = static_cast(-3); // OK. - scoped_unspecified_t InvalidInsideRange1 = static_cast(-2); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} - scoped_unspecified_t InvalidInsideRange2 = static_cast(-1); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} - scoped_unspecified_t InvalidInsideRange3 = static_cast(0); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + scoped_unspecified_t InvalidInsideRange1 = static_cast(-2); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_unspecified_t'}} + scoped_unspecified_t InvalidInsideRange2 = static_cast(-1); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_unspecified_t'}} + scoped_unspecified_t InvalidInsideRange3 = static_cast(0); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_unspecified_t'}} scoped_unspecified_t ValidPositiveValue1 = static_cast(1); // OK. scoped_unspecified_t ValidPositiveValue2 = static_cast(2); // OK. - scoped_unspecified_t InvalidInsideRange4 = static_cast(3); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + scoped_unspecified_t InvalidInsideRange4 = static_cast(3); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_unspecified_t'}} scoped_unspecified_t ValidPositiveValue3 = static_cast(4); // OK. - scoped_unspecified_t InvalidAfterRangeEnd = static_cast(5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + scoped_unspecified_t InvalidAfterRangeEnd = static_cast(5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_unspecified_t'}} } void scopedSpecified() { - scoped_specified_t InvalidBeforeRangeBegin = static_cast(-5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + scoped_specified_t InvalidBeforeRangeBegin = static_cast(-5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_specified_t'}} scoped_specified_t ValidNegativeValue1 = static_cast(-4); // OK. scoped_specified_t ValidNegativeValue2 = static_cast(-3); // OK. - scoped_specified_t InvalidInsideRange1 = static_cast(-2); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} - scoped_specified_t InvalidInsideRange2 = static_cast(-1); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} - scoped_specified_t InvalidInsideRange3 = static_cast(0); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + scoped_specified_t InvalidInsideRange1 = static_cast(-2); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_specified_t'}} + scoped_specified_t InvalidInsideRange2 = static_cast(-1); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_specified_t'}} + scoped_specified_t InvalidInsideRange3 = static_cast(0); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_specified_t'}} scoped_specified_t ValidPositiveValue1 = static_cast(1); // OK. scoped_specified_t ValidPositiveValue2 = static_cast(2); // OK. - scoped_specified_t InvalidInsideRange4 = static_cast(3); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + scoped_specified_t InvalidInsideRange4 = static_cast(3); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_specified_t'}} scoped_specified_t ValidPositiveValue3 = static_cast(4); // OK. - scoped_specified_t InvalidAfterRangeEnd = static_cast(5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + scoped_specified_t InvalidAfterRangeEnd = static_cast(5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_specified_t'}} } void unscopedUnspecifiedCStyle() { - unscoped_unspecified_t InvalidBeforeRangeBegin = (unscoped_unspecified_t)(-5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + unscoped_unspecified_t InvalidBeforeRangeBegin = (unscoped_unspecified_t)(-5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_unspecified_t'}} unscoped_unspecified_t ValidNegativeValue1 = (unscoped_unspecified_t)(-4); // OK. unscoped_unspecified_t ValidNegativeValue2 = (unscoped_unspecified_t)(-3); // OK. - unscoped_unspecified_t InvalidInsideRange1 = (unscoped_unspecified_t)(-2); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} - unscoped_unspecified_t InvalidInsideRange2 = (unscoped_unspecified_t)(-1); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} - unscoped_unspecified_t InvalidInsideRange3 = (unscoped_unspecified_t)(0); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + unscoped_unspecified_t InvalidInsideRange1 = (unscoped_unspecified_t)(-2); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_unspecified_t'}} + unscoped_unspecified_t InvalidInsideRange2 = (unscoped_unspecified_t)(-1); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_unspecified_t'}} + unscoped_unspecified_t InvalidInsideRange3 = (unscoped_unspecified_t)(0); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_unspecified_t'}} unscoped_unspecified_t ValidPositiveValue1 = (unscoped_unspecified_t)(1); // OK. unscoped_unspecified_t ValidPositiveValue2 = (unscoped_unspecified_t)(2); // OK. - unscoped_unspecified_t InvalidInsideRange4 = (unscoped_unspecified_t)(3); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + unscoped_unspecified_t InvalidInsideRange4 = (unscoped_unspecified_t)(3); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_unspecified_t'}} unscoped_unspecified_t ValidPositiveValue3 = (unscoped_unspecified_t)(4); // OK. - unscoped_unspecified_t InvalidAfterRangeEnd = (unscoped_unspecified_t)(5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + unscoped_unspecified_t InvalidAfterRangeEnd = (unscoped_unspecified_t)(5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_unspecified_t'}} } void unscopedSpecifiedCStyle() { - unscoped_specified_t InvalidBeforeRangeBegin = (unscoped_specified_t)(-5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + unscoped_specified_t InvalidBeforeRangeBegin = (unscoped_specified_t)(-5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_specified_t'}} unscoped_specified_t ValidNegativeValue1 = (unscoped_specified_t)(-4); // OK. unscoped_specified_t ValidNegativeValue2 = (unscoped_specified_t)(-3); // OK. - unscoped_specified_t InvalidInsideRange1 = (unscoped_specified_t)(-2); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} - unscoped_specified_t InvalidInsideRange2 = (unscoped_specified_t)(-1); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} - unscoped_specified_t InvalidInsideRange3 = (unscoped_specified_t)(0); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + unscoped_specified_t InvalidInsideRange1 = (unscoped_specified_t)(-2); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_specified_t'}} + unscoped_specified_t InvalidInsideRange2 = (unscoped_specified_t)(-1); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_specified_t'}} + unscoped_specified_t InvalidInsideRange3 = (unscoped_specified_t)(0); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_specified_t'}} unscoped_specified_t ValidPositiveValue1 = (unscoped_specified_t)(1); // OK. unscoped_specified_t ValidPositiveValue2 = (unscoped_specified_t)(2); // OK. - unscoped_specified_t InvalidInsideRange4 = (unscoped_specified_t)(3); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + unscoped_specified_t InvalidInsideRange4 = (unscoped_specified_t)(3); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_specified_t'}} unscoped_specified_t ValidPositiveValue3 = (unscoped_specified_t)(4); // OK. - unscoped_specified_t InvalidAfterRangeEnd = (unscoped_specified_t)(5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + unscoped_specified_t InvalidAfterRangeEnd = (unscoped_specified_t)(5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_specified_t'}} } void scopedUnspecifiedCStyle() { - scoped_unspecified_t InvalidBeforeRangeBegin = (scoped_unspecified_t)(-5); // expected-warning{{The value provided to the cast expression is not in the valid range of values for the enum}} + scoped_unspecified_t InvalidBeforeRangeBegin = (scoped_unspecified_t)(-5); // expected-warning{{The value provided to the cast expression is not in the valid range of values for 'scoped_unspecified_t'}} scoped_unspecified_t ValidNegativeValue1 = (scoped_unspecified_t)(-4); // OK. scoped_unspecified_t ValidNegativeValue2 = (scoped_unspecified_t)(-3); // OK. - scoped_unspecified_t InvalidInsideRange1 = (scoped_unspecified_t)(-2); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} - scoped_unspecified_t InvalidInsideRange2 = (scoped_unspecified_t)(-1); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} - scoped_unspecified_t InvalidInsideRange3 = (scoped_unspecified_t)(0); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + scoped_unspecified_t InvalidInsideRange1 = (scoped_unspecified_t)(-2); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_unspecified_t'}} + scoped_unspecified_t InvalidInsideRange2 = (scoped_unspecified_t)(-1); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_unspecified_t'}} + scoped_unspecified_t InvalidInsideRange3 = (scoped_unspecified_t)(0); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_unspecified_t'}} scoped_unspecified_t ValidPositiveValue1 = (scoped_unspecified_t)(1); // OK. scoped_unspecified_t ValidPositiveValue2 = (scoped_unspecified_t)(2); // OK. - scoped_unspecified_t InvalidInsideRange4 = (scoped_unspecified_t)(3); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + scoped_unspecified_t InvalidInsideRange4 = (scoped_unspecified_t)(3); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_unspecified_t'}} scoped_unspecified_t ValidPositiveValue3 = (scoped_unspecified_t)(4); // OK. - scoped_unspecified_t InvalidAfterRangeEnd = (scoped_unspecified_t)(5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + scoped_unspecified_t InvalidAfterRangeEnd = (scoped_unspecified_t)(5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_unspecified_t'}} } void scopedSpecifiedCStyle() { - scoped_specified_t InvalidBeforeRangeBegin = (scoped_specified_t)(-5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + scoped_specified_t InvalidBeforeRangeBegin = (scoped_specified_t)(-5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_specified_t'}} scoped_specified_t ValidNegativeValue1 = (scoped_specified_t)(-4); // OK. scoped_specified_t ValidNegativeValue2 = (scoped_specified_t)(-3); // OK. - scoped_specified_t InvalidInsideRange1 = (scoped_specified_t)(-2); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} - scoped_specified_t InvalidInsideRange2 = (scoped_specified_t)(-1); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} - scoped_specified_t InvalidInsideRange3 = (scoped_specified_t)(0); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + scoped_specified_t InvalidInsideRange1 = (scoped_specified_t)(-2); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_specified_t'}} + scoped_specified_t InvalidInsideRange2 = (scoped_specified_t)(-1); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_specified_t'}} + scoped_specified_t InvalidInsideRange3 = (scoped_specified_t)(0); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_specified_t'}} scoped_specified_t ValidPositiveValue1 = (scoped_specified_t)(1); // OK. scoped_specified_t ValidPositiveValue2 = (scoped_specified_t)(2); // OK. - scoped_specified_t InvalidInsideRange4 = (scoped_specified_t)(3); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + scoped_specified_t InvalidInsideRange4 = (scoped_specified_t)(3); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_specified_t'}} scoped_specified_t ValidPositiveValue3 = (scoped_specified_t)(4); // OK. - scoped_specified_t InvalidAfterRangeEnd = (scoped_specified_t)(5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + scoped_specified_t InvalidAfterRangeEnd = (scoped_specified_t)(5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_specified_t'}} } unscoped_unspecified_t unused; @@ -165,12 +169,12 @@ void rangeConstrained1(int input) { void rangeConstrained2(int input) { if (input < -5) - auto value = static_cast(input); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + auto value = static_cast(input); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_specified_t'}} } void rangeConstrained3(int input) { if (input >= -2 && input <= -1) - auto value = static_cast(input); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + auto value = static_cast(input); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_specified_t'}} } void rangeConstrained4(int input) { @@ -190,13 +194,13 @@ void rangeConstrained6(int input) { void rangeConstrained7(int input) { if (input >= 3 && input <= 3) - auto value = static_cast(input); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + auto value = static_cast(input); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'scoped_specified_t'}} } void enumBitFieldAssignment() { S s; s.E = static_cast(4); // OK. - s.E = static_cast(5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for the enum}} + s.E = static_cast(5); // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'unscoped_unspecified_t'}} } diff --git a/clang/test/Analysis/invalid-ptr-checker.c b/clang/test/Analysis/invalid-ptr-checker.c new file mode 100644 index 0000000000000..e8ffee7fb479d --- /dev/null +++ b/clang/test/Analysis/invalid-ptr-checker.c @@ -0,0 +1,63 @@ +// RUN: %clang_analyze_cc1 \ +// RUN: -analyzer-checker=alpha.security.cert.env.InvalidPtr \ +// RUN: -analyzer-config alpha.security.cert.env.InvalidPtr:InvalidatingGetEnv=false \ +// RUN: -analyzer-output=text -verify -Wno-unused %s +// +// RUN: %clang_analyze_cc1 \ +// RUN: -analyzer-checker=alpha.security.cert.env.InvalidPtr \ +// RUN: -analyzer-config \ +// RUN: alpha.security.cert.env.InvalidPtr:InvalidatingGetEnv=true \ +// RUN: -analyzer-output=text -verify=expected,pedantic -Wno-unused %s + +#include "Inputs/system-header-simulator.h" + +char *getenv(const char *name); +int setenv(const char *name, const char *value, int overwrite); +int strcmp(const char *, const char *); + +int custom_env_handler(const char **envp); + +void getenv_after_getenv(void) { + char *v1 = getenv("V1"); + // pedantic-note@-1{{previous function call was here}} + + char *v2 = getenv("V2"); + // pedantic-note@-1{{'getenv' call may invalidate the result of the previous 'getenv'}} + + strcmp(v1, v2); + // pedantic-warning@-1{{use of invalidated pointer 'v1' in a function call}} + // pedantic-note@-2{{use of invalidated pointer 'v1' in a function call}} +} + +void setenv_after_getenv(void) { + char *v1 = getenv("VAR1"); + + setenv("VAR2", "...", 1); + // expected-note@-1{{'setenv' call may invalidate the environment returned by 'getenv'}} + + strcmp(v1, ""); + // expected-warning@-1{{use of invalidated pointer 'v1' in a function call}} + // expected-note@-2{{use of invalidated pointer 'v1' in a function call}} +} + +int main(int argc, const char *argv[], const char *envp[]) { + setenv("VAR", "...", 0); + // expected-note@-1 2 {{'setenv' call may invalidate the environment parameter of 'main'}} + + *envp; + // expected-warning@-1 2 {{dereferencing an invalid pointer}} + // expected-note@-2 2 {{dereferencing an invalid pointer}} +} + +void multiple_invalidation_no_duplicate_notes(void) { + char *v1 = getenv("VAR1"); + + setenv("VAR2", "...", 1); // no note here + + setenv("VAR3", "...", 1); + // expected-note@-1{{'setenv' call may invalidate the environment returned by 'getenv'}} + + strcmp(v1, ""); + // expected-warning@-1{{use of invalidated pointer 'v1' in a function call}} + // expected-note@-2{{use of invalidated pointer 'v1' in a function call}} +} diff --git a/clang/test/Analysis/lambdas.cpp b/clang/test/Analysis/lambdas.cpp index c7463ef7ca500..554ed342a4279 100644 --- a/clang/test/Analysis/lambdas.cpp +++ b/clang/test/Analysis/lambdas.cpp @@ -194,8 +194,9 @@ void testFunctionPointerCapture() { // Captured variable-length array. void testVariableLengthArrayCaptured() { - int n = 2; - int array[n]; + int n = 2; // expected-note {{declared here}} + int array[n]; // expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{read of non-const variable 'n' is not allowed in a constant expression}} array[0] = 7; int i = [&]{ diff --git a/clang/test/Analysis/loop-widening-notes.cpp b/clang/test/Analysis/loop-widening-notes.cpp index 0ba71d030d058..a3f030dfe9882 100644 --- a/clang/test/Analysis/loop-widening-notes.cpp +++ b/clang/test/Analysis/loop-widening-notes.cpp @@ -70,3 +70,15 @@ int test_for_loop() { return flag_d / num; // no-crash expected-warning {{Division by zero}} // expected-note@-1 {{Division by zero}} } + +int test_for_range_loop() { + int arr[10] = {0}; + for(auto x : arr) { // expected-note {{Assigning value}} + ++x; + } + if (arr[0] == 0) // expected-note {{Assuming the condition is true}} + // expected-note@-1 {{Taking true branch}} + return 1/arr[0]; // expected-warning {{Division by zero}} + // expected-note@-1 {{Division by zero}} + return 0; +} diff --git a/clang/test/C/drs/dr253.c b/clang/test/C/drs/dr253.c index 3eae0a01586a7..1c6f610dbcca1 100644 --- a/clang/test/C/drs/dr253.c +++ b/clang/test/C/drs/dr253.c @@ -19,7 +19,7 @@ struct fred y [] = { { { "abc" }, 1 }, [0] = { .s[0] = 'q' } }; // CHECK: VarDecl 0x{{.*}} col:13 y 'struct fred[1]' cinit // CHECK-NEXT: InitListExpr 0x{{.*}} 'struct fred[1]' -// CHECK-NEXT: InitListExpr 0x{{.*}} 'struct fred':'struct fred' +// CHECK-NEXT: InitListExpr 0x{{.*}} 'struct fred' // CHECK-NEXT: InitListExpr 0x{{.*}} 'char[6]' // CHECK-NEXT: array_filler // CHECK-NEXT: ImplicitCastExpr diff --git a/clang/test/CXX/basic/basic.types/p10.cpp b/clang/test/CXX/basic/basic.types/p10.cpp index d41b394bb60f2..a543f248e5371 100644 --- a/clang/test/CXX/basic/basic.types/p10.cpp +++ b/clang/test/CXX/basic/basic.types/p10.cpp @@ -20,7 +20,7 @@ constexpr int f2(S &) { return 0; } struct BeingDefined; extern BeingDefined beingdefined; -struct BeingDefined { +struct BeingDefined { static constexpr BeingDefined& t = beingdefined; }; @@ -136,11 +136,15 @@ struct ArrBad { }; constexpr int f(ArrBad) { return 0; } // expected-error {{1st parameter type 'ArrBad' is not a literal type}} -constexpr int arb(int n) { - int a[n]; // expected-error {{variable of non-literal type 'int[n]' cannot be defined in a constexpr function}} +constexpr int arb(int n) { // expected-note {{declared here}} + int a[n]; // expected-error {{variable of non-literal type 'int[n]' cannot be defined in a constexpr function}} \ + expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{function parameter 'n' with unknown value cannot be used in a constant expression}} } -// expected-warning@+1 {{variable length array folded to constant array as an extension}} -constexpr long Overflow[(1 << 30) << 2]{}; // expected-warning {{requires 34 bits to represent}} +constexpr long Overflow[(1 << 30) << 2]{}; // expected-warning {{requires 34 bits to represent}} \ + expected-warning {{variable length array folded to constant array as an extension}} \ + expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{signed left shift discards bits}} namespace inherited_ctor { struct A { constexpr A(int); }; diff --git a/clang/test/CXX/dcl.dcl/dcl.spec/dcl.typedef/p2-0x.cpp b/clang/test/CXX/dcl.dcl/dcl.spec/dcl.typedef/p2-0x.cpp index 5ef917fe356c5..0e9e4637ca05e 100644 --- a/clang/test/CXX/dcl.dcl/dcl.spec/dcl.typedef/p2-0x.cpp +++ b/clang/test/CXX/dcl.dcl/dcl.spec/dcl.typedef/p2-0x.cpp @@ -34,8 +34,10 @@ namespace IllegalSyntax { namespace VariableLengthArrays { using T = int[42]; // ok - int n = 32; - using T = int[n]; // expected-error {{variable length array declaration not allowed at file scope}} + int n = 32; // expected-note {{declared here}} + using T = int[n]; // expected-error {{variable length array declaration not allowed at file scope}} \ + expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{read of non-const variable 'n' is not allowed in a constant expression}} const int m = 42; using U = int[m]; @@ -43,9 +45,11 @@ namespace VariableLengthArrays { using U = int; // expected-error {{type alias redefinition with different types ('int' vs 'int[42]')}} void f() { - int n = 42; + int n = 42; // expected-note {{declared here}} goto foo; // expected-error {{cannot jump}} - using T = int[n]; // expected-note {{bypasses initialization of VLA type alias}} + using T = int[n]; // expected-note {{bypasses initialization of VLA type alias}} \ + expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{read of non-const variable 'n' is not allowed in a constant expression}} foo: ; } } diff --git a/clang/test/CXX/dcl.decl/dcl.init/dcl.init.general/p16-cxx20.cpp b/clang/test/CXX/dcl.decl/dcl.init/dcl.init.general/p16-cxx20.cpp new file mode 100644 index 0000000000000..1ad205d769c38 --- /dev/null +++ b/clang/test/CXX/dcl.decl/dcl.init/dcl.init.general/p16-cxx20.cpp @@ -0,0 +1,18 @@ +// RUN: %clang_cc1 -fsyntax-only -verify -std=c++20 %s + +// If the initializer is (), the object is value-initialized. + +// expected-no-diagnostics +namespace GH69890 { +struct A { + constexpr A() {} + int x; +}; + +struct B : A { + int y; +}; + +static_assert(B().x == 0); +static_assert(B().y == 0); +} diff --git a/clang/test/CXX/dcl.decl/dcl.init/dcl.init.ref/p4-ast.cpp b/clang/test/CXX/dcl.decl/dcl.init/dcl.init.ref/p4-ast.cpp index 4fc0a05ae1eca..32c4ddd921bba 100644 --- a/clang/test/CXX/dcl.decl/dcl.init/dcl.init.ref/p4-ast.cpp +++ b/clang/test/CXX/dcl.decl/dcl.init/dcl.init.ref/p4-ast.cpp @@ -3,7 +3,7 @@ void f() noexcept; // CHECK: VarDecl {{.*}} ref 'void (&)()' cinit -// CHECK-NEXT: ImplicitCastExpr {{.*}} 'void ()':'void ()' lvalue +// CHECK-NEXT: ImplicitCastExpr {{.*}} 'void ()' lvalue // CHECK-NEXT: DeclRefExpr {{.*}} 'void () noexcept' lvalue Function {{.*}} 'f' 'void () noexcept' void (&ref)() = f; @@ -13,6 +13,6 @@ struct X { } x; // CHECK: VarDecl {{.*}} xp 'void (&)()' cinit -// CHECK-NEXT: ImplicitCastExpr {{.*}} 'void ()':'void ()' lvalue -// CHECK-NEXT: ImplicitCastExpr {{.*}} 'void () noexcept':'void () noexcept' lvalue +// CHECK-NEXT: ImplicitCastExpr {{.*}} 'void ()' lvalue +// CHECK-NEXT: ImplicitCastExpr {{.*}} 'void () noexcept' lvalue void (&xp)() = x; diff --git a/clang/test/CXX/drs/dr25xx.cpp b/clang/test/CXX/drs/dr25xx.cpp index f1b5a1c26fec1..3644e4c328b1b 100644 --- a/clang/test/CXX/drs/dr25xx.cpp +++ b/clang/test/CXX/drs/dr25xx.cpp @@ -85,8 +85,7 @@ using ::dr2521::operator""_div; #if __cplusplus >= 202302L namespace dr2553 { // dr2553: 18 struct B { - virtual void f(this B&); // expected-error {{an explicit object parameter cannot appear in a virtual function}} \ - // expected-note {{here}} + virtual void f(this B&); // expected-error {{an explicit object parameter cannot appear in a virtual function}} static void f(this B&); // expected-error {{an explicit object parameter cannot appear in a static function}} virtual void g(); // expected-note {{here}} }; @@ -94,10 +93,6 @@ struct D : B { void g(this D&); // expected-error {{an explicit object parameter cannot appear in a virtual function}} }; -struct D2 : B { - void f(this B&); // expected-error {{an explicit object parameter cannot appear in a virtual function}} -}; - } #endif diff --git a/clang/test/CXX/expr/expr.prim/expr.prim.lambda/p4.cpp b/clang/test/CXX/expr/expr.prim/expr.prim.lambda/p4.cpp index ffac9112491fe..d933f76500430 100644 --- a/clang/test/CXX/expr/expr.prim/expr.prim.lambda/p4.cpp +++ b/clang/test/CXX/expr/expr.prim/expr.prim.lambda/p4.cpp @@ -44,21 +44,23 @@ X infer_X_return_type_2(X x) { } struct Incomplete; // expected-note 2{{forward declaration of 'Incomplete'}} -void test_result_type(int N) { +void test_result_type(int N) { // expected-note {{declared here}} auto l1 = [] () -> Incomplete { }; // expected-error{{incomplete result type 'Incomplete' in lambda expression}} - typedef int vla[N]; + typedef int vla[N]; // expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{function parameter 'N' with unknown value cannot be used in a constant expression}} auto l2 = [] () -> vla { }; // expected-error{{function cannot return array type 'vla' (aka 'int[N]')}} } template -void test_result_type_tpl(int N) { +void test_result_type_tpl(int N) { // expected-note 2{{declared here}} auto l1 = []() -> T {}; // expected-error{{incomplete result type 'Incomplete' in lambda expression}} // expected-note@-1{{while substituting into a lambda expression here}} - typedef int vla[N]; + typedef int vla[N]; // expected-warning 2{{variable length arrays in C++ are a Clang extension}} \ + expected-note 2{{function parameter 'N' with unknown value cannot be used in a constant expression}} auto l2 = []() -> vla {}; // expected-error{{function cannot return array type 'vla' (aka 'int[N]')}} } void test_result_type_call() { - test_result_type_tpl(10); // expected-note {{requested here}} + test_result_type_tpl(10); // expected-note 2{{requested here}} } diff --git a/clang/test/CXX/over/over.match/over.match.funcs/over.match.oper/p2468R2.cppm b/clang/test/CXX/over/over.match/over.match.funcs/over.match.oper/p2468R2.cppm new file mode 100644 index 0000000000000..05891618991da --- /dev/null +++ b/clang/test/CXX/over/over.match/over.match.funcs/over.match.oper/p2468R2.cppm @@ -0,0 +1,24 @@ +// RUN: rm -rf %t +// RUN: mkdir %t +// RUN: split-file %s %t +// +// RUN: %clang_cc1 -std=c++20 %t/A.cppm -emit-module-interface -o %t/A.pcm +// RUN: %clang_cc1 -std=c++20 -fprebuilt-module-path=%t -I%t %t/p2468r2.cpp -verify + +//--- A.cppm +module; +export module A; +export { +namespace NS { +struct S {}; +bool operator==(S, int); +} // namespace NS +} + +namespace NS { bool operator!=(S, int); } // Not visible. + + +//--- p2468r2.cpp +// expected-no-diagnostics +import A; +bool x = 0 == NS::S(); // Ok. operator!= from module A is not visible. diff --git a/clang/test/CXX/over/over.match/over.match.funcs/over.match.oper/p3-2a.cpp b/clang/test/CXX/over/over.match/over.match.funcs/over.match.oper/p3-2a.cpp index 5c6804eb7726b..d83a176ec07ee 100644 --- a/clang/test/CXX/over/over.match/over.match.funcs/over.match.oper/p3-2a.cpp +++ b/clang/test/CXX/over/over.match/over.match.funcs/over.match.oper/p3-2a.cpp @@ -324,6 +324,108 @@ bool x = X() == X(); // expected-warning {{ambiguous}} } } // namespace P2468R2 +namespace ADL_GH68901{ +namespace test1 { +namespace A { +struct S {}; +bool operator==(S, int); // expected-note {{no known conversion from 'int' to 'S' for 1st argument}} +bool a = 0 == A::S(); // Ok. Operator!= not visible. +bool operator!=(S, int); +} // namespace A +bool a = 0 == A::S(); // expected-error {{invalid operands to binary expression ('int' and 'A::S')}} +} // namespace test1 + +namespace test2 { +namespace B { +struct Derived {}; +struct Base : Derived {}; + +bool operator==(Derived& a, Base& b); +bool operator!=(Derived& a, Base& b); +} // namespace B + +bool foo() { + B::Base a,b; + return a == b; +} +} // namespace test2 + + +namespace template_ { +namespace ns { +template struct A {}; +template struct B : A {}; + +template bool operator==(B, A); // expected-note {{candidate template ignored: could not match 'B' against 'A'}} +template bool operator!=(B, A); +} + +void test() { + ns::A a; + ns::B b; + a == b; // expected-error {{invalid operands to binary expression}} +} +} // namespace test3 + +namespace using_not_eq { +namespace A { +struct S {}; +namespace B { +bool operator!=(S, int); +} +bool operator==(S, int); // expected-note {{candidate}} +using B::operator!=; +} // namespace A +bool a = 0 == A::S(); // expected-error {{invalid operands to binary expression}} +} // namespace reversed_lookup_not_like_ADL + +namespace using_eqeq { +namespace A { +struct S {}; +namespace B { +bool operator==(S, int); // expected-note {{candidate}} +bool operator!=(S, int); +} +using B::operator==; +} // namespace A +bool a = 0 == A::S(); // expected-error {{invalid operands to binary expression}} +} + +} //namespace ADL_GH68901 + +namespace function_scope_operator_eqeq { +// For non-members, we always lookup for matching operator!= in the namespace scope of +// operator== (and not in the scope of operator==). +struct X { operator int(); }; +namespace test1{ +bool h(X x) { + bool operator==(X, int); // expected-note {{reversed}} + return x == x; // expected-warning {{ambiguous}} +} + +bool g(X x) { + bool operator==(X, int); // expected-note {{reversed}} + bool operator!=(X, int); + return x == x; // expected-warning {{ambiguous}} +} +} // namespace test1 + +namespace test2 { +bool operator!=(X, int); + +bool h(X x) { + bool operator==(X, int); + return x == x; +} + +bool i(X x) { + bool operator==(X, int); + bool operator!=(X, int); + return x == x; +} +} // namespace test2 +} // namespace function_scope_operator_eqeq + #else // NO_ERRORS namespace problem_cases { diff --git a/clang/test/CXX/temp/temp.arg/temp.arg.type/p2.cpp b/clang/test/CXX/temp/temp.arg/temp.arg.type/p2.cpp index 539baecdb6a5b..1e314da313990 100644 --- a/clang/test/CXX/temp/temp.arg/temp.arg.type/p2.cpp +++ b/clang/test/CXX/temp/temp.arg/temp.arg.type/p2.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -fsyntax-only -verify %s +// RUN: %clang_cc1 -fsyntax-only -verify -Wvla %s // RUN: %clang_cc1 -fsyntax-only -verify -std=c++98 %s // RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 %s @@ -19,13 +19,17 @@ enum {e}; // expected-note@-2 {{unnamed type used in template argument was declared here}} #endif -void test_f0(int n) { +void test_f0(int n) { // #here int i = f0(0, e); #if __cplusplus <= 199711L // expected-warning@-2 {{template argument uses unnamed type}} #endif - int vla[n]; + int vla[n]; // expected-warning {{variable length arrays in C++ are a Clang extension}} +#if __cplusplus > 199711L + // expected-note@-2 {{function parameter 'n' with unknown value cannot be used in a constant expression}} + // expected-note@#here {{declared here}} +#endif f0(0, vla); // expected-error{{no matching function for call to 'f0'}} } diff --git a/clang/test/CXX/temp/temp.decls/temp.variadic/p5.cpp b/clang/test/CXX/temp/temp.decls/temp.variadic/p5.cpp index 10af03eeaf0a9..7536339c14a2e 100644 --- a/clang/test/CXX/temp/temp.decls/temp.variadic/p5.cpp +++ b/clang/test/CXX/temp/temp.decls/temp.variadic/p5.cpp @@ -27,12 +27,12 @@ struct ExpansionLengthMismatch { }; }; -ExpansionLengthMismatch::Inner::type +ExpansionLengthMismatch::Inner::type *il_pairs; tuple, pair >*il_pairs_2 = il_pairs; ExpansionLengthMismatch::Inner::type // expected-note{{in instantiation of template class 'ExpansionLengthMismatch::Inner' requested here}} - *il_pairs_bad; + *il_pairs_bad; // An appearance of a name of a parameter pack that is not expanded is @@ -40,7 +40,7 @@ ExpansionLengthMismatch::Inner::t // Test for unexpanded parameter packs in each of the type nodes. template -struct TestPPName +struct TestPPName : public Types, public T // expected-error{{base type contains unexpanded parameter pack 'Types'}} { // BuiltinType is uninteresting @@ -60,33 +60,35 @@ struct TestPPName // MemberPointerType typedef Types TestPPName::* member_pointer_1; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} - typedef int Types::*member_pointer_2; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} + typedef int Types::*member_pointer_2; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} // ConstantArrayType - typedef Types constant_array[17]; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} + typedef Types constant_array[17]; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} // IncompleteArrayType - typedef Types incomplete_array[]; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} + typedef Types incomplete_array[]; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} // VariableArrayType - void f(int i) { - Types variable_array[i]; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} + void f(int i) { // expected-note {{declared here}} + Types variable_array[i]; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} \ + expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{function parameter 'i' with unknown value cannot be used in a constant expression}} } // DependentSizedArrayType - typedef Types dependent_sized_array[N]; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} + typedef Types dependent_sized_array[N]; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} // DependentSizedExtVectorType - typedef Types dependent_sized_ext_vector __attribute__((ext_vector_type(N))); // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} + typedef Types dependent_sized_ext_vector __attribute__((ext_vector_type(N))); // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} // VectorType is uninteresting // ExtVectorType - typedef Types ext_vector __attribute__((ext_vector_type(4))); // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} + typedef Types ext_vector __attribute__((ext_vector_type(4))); // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} // FunctionProtoType - typedef Types (function_type_1)(int); // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} - typedef int (function_type_2)(Types); // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} + typedef Types (function_type_1)(int); // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} + typedef int (function_type_2)(Types); // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} // FunctionNoProtoType is uninteresting // UnresolvedUsingType is uninteresting @@ -94,34 +96,34 @@ struct TestPPName // TypedefType is uninteresting // TypeOfExprType - typedef __typeof__((static_cast(0))) typeof_expr; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} + typedef __typeof__((static_cast(0))) typeof_expr; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} // TypeOfType - typedef __typeof__(Types) typeof_type; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} + typedef __typeof__(Types) typeof_type; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} // DecltypeType - typedef decltype((static_cast(0))) typeof_expr; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} + typedef decltype((static_cast(0))) typeof_expr; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} // RecordType is uninteresting // EnumType is uninteresting // ElaboratedType is uninteresting // TemplateTypeParmType - typedef Types template_type_parm; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} + typedef Types template_type_parm; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} // SubstTemplateTypeParmType is uninteresting // TemplateSpecializationType - typedef pair template_specialization; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} + typedef pair template_specialization; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} // InjectedClassName is uninteresting. // DependentNameType - typedef typename Types::type dependent_name; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} + typedef typename Types::type dependent_name; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} // DependentTemplateSpecializationType - typedef typename Types::template apply dependent_name_1; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} - typedef typename T::template apply dependent_name_2; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} + typedef typename Types::template apply dependent_name_1; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} + typedef typename T::template apply dependent_name_2; // expected-error{{declaration type contains unexpanded parameter pack 'Types'}} // ObjCObjectType is uninteresting // ObjCInterfaceType is uninteresting @@ -194,7 +196,7 @@ struct alignas(Types) TestUnexpandedDecls : T{ // expected-error{{expression con } T in_class_member_init = static_cast(0); // expected-error{{initializer contains unexpanded parameter pack 'Types'}} - TestUnexpandedDecls() : + TestUnexpandedDecls() : Types(static_cast(0)), // expected-error{{initializer contains unexpanded parameter pack 'Types'}} Types(static_cast(0))..., in_class_member_init(static_cast(0)) {} // expected-error{{initializer contains unexpanded parameter pack 'Types'}} @@ -202,7 +204,7 @@ struct alignas(Types) TestUnexpandedDecls : T{ // expected-error{{expression con void default_function_args(T = static_cast(0)); // expected-error{{default argument contains unexpanded parameter pack 'Types'}} template // expected-error{{default argument contains unexpanded parameter pack 'Types'}} - struct default_template_args_1; + struct default_template_args_1; template(0)> // expected-error{{default argument contains unexpanded parameter pack 'Types'}} struct default_template_args_2; template class = Types::template apply> // expected-error{{default argument contains unexpanded parameter pack 'Types'}} @@ -390,13 +392,13 @@ struct MemberTemplatePPNames { // Example from working paper namespace WorkingPaperExample { - template struct Tuple {}; + template struct Tuple {}; template struct Pair {}; - - template struct zip { + + template struct zip { template struct with { typedef Tuple ... > type; // expected-error{{pack expansion contains parameter packs 'Args1' and 'Args2' that have different lengths (1 vs. 2)}} - }; + }; }; typedef zip::with::type T1; // T1 is Tuple, Pair> @@ -407,9 +409,9 @@ namespace WorkingPaperExample { template void f(Args...); template void h(Args...); - template + template void g(Args ... args) { - f(const_cast(&args)...); // OK: "Args" and "args" are expanded within f + f(const_cast(&args)...); // OK: "Args" and "args" are expanded within f f(5 ...); // expected-error{{pack expansion does not contain any unexpanded parameter packs}} f(args); // expected-error{{expression contains unexpanded parameter pack 'args'}} f(h(args ...) + args ...); diff --git a/clang/test/ClangScanDeps/modules-has-include-umbrella-header.c b/clang/test/ClangScanDeps/modules-has-include-umbrella-header.c new file mode 100644 index 0000000000000..e9363b2e14b07 --- /dev/null +++ b/clang/test/ClangScanDeps/modules-has-include-umbrella-header.c @@ -0,0 +1,76 @@ +// This test checks that __has_include() in a module does +// not clobber #include in importers of said module. + +// RUN: rm -rf %t +// RUN: split-file %s %t + +//--- cdb.json.template +[{ + "file": "DIR/tu.c", + "directory": "DIR", + "command": "clang DIR/tu.c -fmodules -fmodules-cache-path=DIR/cache -I DIR/modules -F DIR/frameworks -o DIR/tu.o" +}] + +//--- frameworks/FW.framework/Modules/module.private.modulemap +framework module FW_Private { + umbrella header "A.h" + module * { export * } +} +//--- frameworks/FW.framework/PrivateHeaders/A.h +#include +//--- frameworks/FW.framework/PrivateHeaders/B.h +#include "dependency.h" + +//--- modules/module.modulemap +module Poison { header "poison.h" } +module Import { header "import.h" } +module Dependency { header "dependency.h" } +//--- modules/poison.h +#if __has_include() +#define HAS_B 1 +#else +#define HAS_B 0 +#endif +//--- modules/import.h +#include +//--- modules/dependency.h + +//--- tu.c +#include "poison.h" + +#if __has_include() +#endif + +#include "import.h" + +#include + +// RUN: sed -e "s|DIR|%/t|g" %t/cdb.json.template > %t/cdb.json +// RUN: clang-scan-deps -compilation-database %t/cdb.json -format experimental-full > %t/deps.json +// RUN: cat %t/deps.json | sed 's:\\\\\?:/:g' | FileCheck %s -DPREFIX=%/t + +// Let's check that the TU actually depends on `FW_Private` (and does not treat FW/B.h as textual). +// CHECK: { +// CHECK: "translation-units": [ +// CHECK-NEXT: { +// CHECK-NEXT: "commands": [ +// CHECK-NEXT: { +// CHECK-NEXT: "clang-context-hash": "{{.*}}", +// CHECK-NEXT: "clang-module-deps": [ +// CHECK-NEXT: { +// CHECK-NEXT: "context-hash": "{{.*}}", +// CHECK-NEXT: "module-name": "FW_Private" +// CHECK-NEXT: } +// CHECK: ], +// CHECK-NEXT: "command-line": [ +// CHECK: ], +// CHECK-NEXT: "executable": "clang", +// CHECK-NEXT: "file-deps": [ +// CHECK-NEXT: "[[PREFIX]]/tu.c" +// CHECK-NEXT: ], +// CHECK-NEXT: "input-file": "[[PREFIX]]/tu.c" +// CHECK-NEXT: } +// CHECK: ] +// CHECK: } +// CHECK: ] +// CHECK: } diff --git a/clang/test/CodeGen/64bit-swiftcall.c b/clang/test/CodeGen/64bit-swiftcall.c index 5290de2471e8e..da6f18248c2af 100644 --- a/clang/test/CodeGen/64bit-swiftcall.c +++ b/clang/test/CodeGen/64bit-swiftcall.c @@ -985,8 +985,8 @@ struct { } s; } union_het_vecint; TEST(union_het_vecint) -// CHECK: define{{.*}} swiftcc void @return_union_het_vecint(ptr noalias sret([[UNION:.+]]) -// CHECK: define{{.*}} swiftcc void @take_union_het_vecint(ptr +// CHECK: define{{.*}} swiftcc { i64, i64, i64, i64 } @return_union_het_vecint() +// CHECK: define{{.*}} swiftcc void @take_union_het_vecint(i64 %0, i64 %1, i64 %2, i64 %3) typedef struct { float3 f3; @@ -1044,3 +1044,20 @@ typedef struct { // CHECK-LABEL: use_atomic_padded(i64 %0, i64 %1) SWIFTCALL void use_atomic_padded(atomic_padded a) {} + + +typedef union { + float4 v; + float3 v2; + struct { + float a; + float b; + float c; + float d; + }; +} vector_union; + +TEST(vector_union) + +// CHECK-LABEL: define swiftcc { float, float, float, float } @return_vector_union() +// CHECK-LABEL: define swiftcc void @take_vector_union(float %0, float %1, float %2, float %3) diff --git a/clang/test/CodeGen/LoongArch/abi-lp64d-empty-structs.c b/clang/test/CodeGen/LoongArch/abi-lp64d-empty-structs.c index fb90bf556c19b..d0daafac336ec 100644 --- a/clang/test/CodeGen/LoongArch/abi-lp64d-empty-structs.c +++ b/clang/test/CodeGen/LoongArch/abi-lp64d-empty-structs.c @@ -81,9 +81,62 @@ struct s8 test_s8(struct s8 a) { return a; } +/// Note: Below tests check how empty structs are passed while above tests check +/// empty structs as fields of container struct are ignored when flattening +/// structs to examine whether the container structs can be passed via FARs. + // CHECK-C: define{{.*}} void @test_s9() // CHECK-CXX: define{{.*}} i64 @_Z7test_s92s9(i64 {{.*}}) struct s9 { struct empty e; }; struct s9 test_s9(struct s9 a) { return a; } + +// CHECK-C: define{{.*}} void @test_s10() +// CHECK-CXX: define{{.*}} void @_Z8test_s103s10() +struct s10 { }; +struct s10 test_s10(struct s10 a) { + return a; +} + +// CHECK-C: define{{.*}} void @test_s11() +// CHECK-CXX: define{{.*}} i64 @_Z8test_s113s11(i64 {{.*}}) +struct s11 { struct { } s; }; +struct s11 test_s11(struct s11 a) { + return a; +} + +// CHECK-C: define{{.*}} void @test_s12() +// CHECK-CXX: define{{.*}} void @_Z8test_s123s12() +struct s12 { int i[0]; }; +struct s12 test_s12(struct s12 a) { + return a; +} + +// CHECK-C: define{{.*}} void @test_s13() +// CHECK-CXX: define{{.*}} void @_Z8test_s133s13() +struct s13 { struct { } s[0]; }; +struct s13 test_s13(struct s13 a) { + return a; +} + +// CHECK-C: define{{.*}} void @test_s14() +// CHECK-CXX: define{{.*}} i64 @_Z8test_s143s14(i64 {{.*}}) +struct s14 { struct { } s[1]; }; +struct s14 test_s14(struct s14 a) { + return a; +} + +// CHECK-C: define{{.*}} void @test_s15() +// CHECK-CXX: define{{.*}} void @_Z8test_s153s15() +struct s15 { int : 0; }; +struct s15 test_s15(struct s15 a) { + return a; +} + +// CHECK-C: define{{.*}} void @test_s16() +// CHECK-CXX: define{{.*}} void @_Z8test_s163s16() +struct s16 { int : 1; }; +struct s16 test_s16(struct s16 a) { + return a; +} diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc.c b/clang/test/CodeGen/PowerPC/builtins-ppc.c index ccc91b6560845..c13edf44cdcbd 100644 --- a/clang/test/CodeGen/PowerPC/builtins-ppc.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc.c @@ -1,5 +1,8 @@ // REQUIRES: powerpc-registered-target -// RUN: %clang_cc1 -triple powerpc-unknown-unknown -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -triple powerpc-unknown-unknown -emit-llvm %s -o - \ +// RUN: | FileCheck %s +// RUN: %clang_cc1 -triple powerpc-unknown-unknown -emit-llvm %s -o - \ +// RUN: -target-cpu pwr9 | FileCheck %s --check-prefixes=P9,CHECK void test_eh_return_data_regno() { @@ -26,6 +29,9 @@ void test_builtin_ppc_setrnd() { // CHECK: call double @llvm.ppc.setrnd(i32 %2) res = __builtin_setrnd(x); + + // CHECK: call double @llvm.ppc.setrnd(i32 %4) + res = __builtin_ppc_set_fpscr_rn(x); } void test_builtin_ppc_flm() { @@ -33,7 +39,10 @@ void test_builtin_ppc_flm() { // CHECK: call double @llvm.ppc.readflm() res = __builtin_readflm(); - // CHECK: call double @llvm.ppc.setflm(double %1) + // CHECK: call double @llvm.ppc.readflm() + res = __builtin_ppc_mffs(); + + // CHECK: call double @llvm.ppc.setflm(double %2) res = __builtin_setflm(res); #ifdef _ARCH_PWR9 diff --git a/clang/test/CodeGen/PowerPC/ppc-emmintrin.c b/clang/test/CodeGen/PowerPC/ppc-emmintrin.c index e2d26e611ac81..15d291496c20a 100644 --- a/clang/test/CodeGen/PowerPC/ppc-emmintrin.c +++ b/clang/test/CodeGen/PowerPC/ppc-emmintrin.c @@ -8,6 +8,11 @@ // RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ // RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK-P10 +// RUN: %clang -x c++ -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ +// RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -fsyntax-only +// RUN: %clang -x c++ -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ +// RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -fsyntax-only + // RUN: %clang -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ // RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE // RUN: %clang -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ diff --git a/clang/test/CodeGen/PowerPC/ppc-mmintrin.c b/clang/test/CodeGen/PowerPC/ppc-mmintrin.c index 4cb5b8540092f..1dc6292ae3244 100644 --- a/clang/test/CodeGen/PowerPC/ppc-mmintrin.c +++ b/clang/test/CodeGen/PowerPC/ppc-mmintrin.c @@ -9,6 +9,11 @@ // RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr9 -DNO_WARN_X86_INTRINSICS %s \ // RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n| FileCheck %s --check-prefixes=CHECK-P9,CHECK,CHECK-LE +// RUN: %clang -x c++ -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -DNO_WARN_X86_INTRINSICS %s \ +// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -fsyntax-only +// RUN: %clang -x c++ -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr9 -DNO_WARN_X86_INTRINSICS %s \ +// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -fsyntax-only + // RUN: %clang -S -emit-llvm -target powerpc64-unknown-freebsd13.0 -mcpu=pwr8 -DNO_WARN_X86_INTRINSICS %s \ // RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK-P8,CHECK,CHECK-BE // RUN: %clang -S -emit-llvm -target powerpc64le-unknown-freebsd13.0 -mcpu=pwr8 -DNO_WARN_X86_INTRINSICS %s \ diff --git a/clang/test/CodeGen/PowerPC/ppc-pmmintrin.c b/clang/test/CodeGen/PowerPC/ppc-pmmintrin.c index 39194427978ad..6e152c549498d 100644 --- a/clang/test/CodeGen/PowerPC/ppc-pmmintrin.c +++ b/clang/test/CodeGen/PowerPC/ppc-pmmintrin.c @@ -13,6 +13,9 @@ // RUN: %clang -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr8 -DNO_MM_MALLOC -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ // RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s +// RUN: %clang -x c++ -S -emit-llvm -target powerpc64le-gnu-linux -mcpu=pwr8 -DNO_MM_MALLOC -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ +// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -fsyntax-only + #include __m128d resd, md1, md2; diff --git a/clang/test/CodeGen/PowerPC/ppc-smmintrin.c b/clang/test/CodeGen/PowerPC/ppc-smmintrin.c index 220b65c1ce164..7daef71a61c32 100644 --- a/clang/test/CodeGen/PowerPC/ppc-smmintrin.c +++ b/clang/test/CodeGen/PowerPC/ppc-smmintrin.c @@ -15,6 +15,11 @@ // RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ // RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefix=P10 +// RUN: %clang -x c++ -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ +// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -fsyntax-only +// RUN: %clang -x c++ -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ +// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -fsyntax-only + // RUN: %clang -S -emit-llvm -target powerpc64le-unknown-freebsd13.0 -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ // RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s // RUN: %clang -S -emit-llvm -target powerpc64-unknown-freebsd13.0 -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ @@ -239,44 +244,48 @@ test_round() { // CHECK-LABEL: @test_round // CHECK-LABEL: define available_externally <4 x float> @_mm_round_ps(<4 x float> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef signext %{{[0-9a-zA-Z_.]+}}) -// CHECK: call signext i32 @__builtin_mffs() -// CHECK: call signext i32 @__builtin_mtfsf(i32 noundef signext 3, double noundef %{{[0-9a-zA-Z_.]+}}) +// CHECK: call double @llvm.ppc.readflm() +// CHECK: call void @llvm.ppc.mtfsf(i32 3, double %{{[0-9a-zA-Z_.]+}}) // CHECK: %{{[0-9a-zA-Z_.]+}} = call <4 x float> asm "", "=^wa,0" -// CHECK: call signext i32 @__builtin_mffsl() -// CHECK: call signext i32 @__builtin_set_fpscr_rn(i32 noundef signext 0) +// CHECK: call double @llvm.ppc.readflm() +// P10: call double @llvm.ppc.mffsl() +// CHECK: call double @llvm.ppc.setrnd(i32 0) // CHECK: %{{[0-9a-zA-Z_.]+}} = call <4 x float> asm "", "=^wa,0" // CHECK: call <4 x float> @vec_rint(float vector[4]) // CHECK: call void asm sideeffect "", "^wa" -// CHECK: call signext i32 @__builtin_set_fpscr_rn(i64 noundef %{{[0-9a-zA-Z_.]+}}) +// CHECK: call double @llvm.ppc.setrnd(i32 %{{[0-9a-zA-Z_.]+}}) // CHECK: call <4 x float> @vec_floor(float vector[4]) // CHECK: call <4 x float> @vec_ceil(float vector[4]) // CHECK: call <4 x float> @vec_trunc(float vector[4]) // CHECK: call <4 x float> @vec_rint(float vector[4]) // CHECK: call void asm sideeffect "", "^wa" -// CHECK: call signext i32 @__builtin_mffsl() -// CHECK: call signext i32 @__builtin_mtfsf(i32 noundef signext 3, double noundef %{{[0-9a-zA-Z_.]+}}) +// CHECK: call double @llvm.ppc.readflm() +// P10: call double @llvm.ppc.mffsl() +// CHECK: call void @llvm.ppc.mtfsf(i32 3, double %{{[0-9a-zA-Z_.]+}}) // CHECK-LABEL: define available_externally <4 x float> @_mm_round_ss(<4 x float> noundef %{{[0-9a-zA-Z_.]+}}, <4 x float> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef signext %{{[0-9a-zA-Z_.]+}}) // CHECK: call <4 x float> @_mm_round_ps(<4 x float> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef signext %{{[0-9a-zA-Z_.]+}}) // CHECK: extractelement <4 x float> %{{[0-9a-zA-Z_.]+}}, i32 0 // CHECK-LABEL: define available_externally <2 x double> @_mm_round_pd(<2 x double> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef signext %{{[0-9a-zA-Z_.]+}}) -// CHECK: call signext i32 @__builtin_mffs() -// CHECK: call signext i32 @__builtin_mtfsf(i32 noundef signext 3, double noundef %{{[0-9a-zA-Z_.]+}}) +// CHECK: call double @llvm.ppc.readflm() +// CHECK: call void @llvm.ppc.mtfsf(i32 3, double %{{[0-9a-zA-Z_.]+}}) // CHECK: %{{[0-9a-zA-Z_.]+}} = call <2 x double> asm "", "=^wa,0" -// CHECK: call signext i32 @__builtin_mffsl() -// CHECK: call signext i32 @__builtin_set_fpscr_rn(i32 noundef signext 0) +// CHECK: call double @llvm.ppc.readflm() +// P10: call double @llvm.ppc.mffsl() +// CHECK: call double @llvm.ppc.setrnd(i32 0) // CHECK: %{{[0-9a-zA-Z_.]+}} = call <2 x double> asm "", "=^wa,0" // CHECK: call <2 x double> @vec_rint(double vector[2]) // CHECK: call void asm sideeffect "", "^wa" -// CHECK: call signext i32 @__builtin_set_fpscr_rn(i64 noundef %{{[0-9a-zA-Z_.]+}}) +// CHECK: call double @llvm.ppc.setrnd(i32 %{{[0-9a-zA-Z_.]+}}) // CHECK: call <2 x double> @vec_floor(double vector[2]) // CHECK: call <2 x double> @vec_ceil(double vector[2]) // CHECK: call <2 x double> @vec_trunc(double vector[2]) // CHECK: call <2 x double> @vec_rint(double vector[2]) // CHECK: call void asm sideeffect "", "^wa" -// CHECK: call signext i32 @__builtin_mffsl() -// CHECK: call signext i32 @__builtin_mtfsf(i32 noundef signext 3, double noundef %{{[0-9a-zA-Z_.]+}}) +// CHECK: call double @llvm.ppc.readflm() +// P10: call double @llvm.ppc.mffsl() +// CHECK: call void @llvm.ppc.mtfsf(i32 3, double %{{[0-9a-zA-Z_.]+}}) // CHECK-LABEL: define available_externally <2 x double> @_mm_round_sd(<2 x double> noundef %{{[0-9a-zA-Z_.]+}}, <2 x double> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef signext %{{[0-9a-zA-Z_.]+}}) // CHECK: call <2 x double> @_mm_round_pd(<2 x double> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef signext %{{[0-9a-zA-Z_.]+}}) diff --git a/clang/test/CodeGen/PowerPC/ppc-tmmintrin.c b/clang/test/CodeGen/PowerPC/ppc-tmmintrin.c index 60633e34b56b9..40d3839dcf026 100644 --- a/clang/test/CodeGen/PowerPC/ppc-tmmintrin.c +++ b/clang/test/CodeGen/PowerPC/ppc-tmmintrin.c @@ -13,6 +13,9 @@ // RUN: %clang -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ // RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE +// RUN: %clang -x c++ -S -emit-llvm -target powerpc64le-gnu-linux -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ +// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -fsyntax-only + #include __m64 res, m1, m2; diff --git a/clang/test/CodeGen/PowerPC/ppc-x86gprintrin.c b/clang/test/CodeGen/PowerPC/ppc-x86gprintrin.c index 238ce7c7ee574..ac90a5f8c530b 100644 --- a/clang/test/CodeGen/PowerPC/ppc-x86gprintrin.c +++ b/clang/test/CodeGen/PowerPC/ppc-x86gprintrin.c @@ -12,6 +12,9 @@ // RUN: %clang -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr7 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ // RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s +// RUN: %clang -x c++ -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr7 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ +// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -fsyntax-only + #include unsigned short us; diff --git a/clang/test/CodeGen/RISCV/riscv-inline-asm-clobber.c b/clang/test/CodeGen/RISCV/riscv-inline-asm-clobber.c new file mode 100644 index 0000000000000..8aa80386f205f --- /dev/null +++ b/clang/test/CodeGen/RISCV/riscv-inline-asm-clobber.c @@ -0,0 +1,44 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv32 -O2 -emit-llvm %s -o - \ +// RUN: | FileCheck %s +// RUN: %clang_cc1 -triple riscv64 -O2 -emit-llvm %s -o - \ +// RUN: | FileCheck %s + +// Test RISC-V specific clobbered registers in inline assembly. + +// CHECK-LABEL: define {{.*}} void @test_fflags +// CHECK: tail call void asm sideeffect "", "~{fflags}"() +void test_fflags(void) { + asm volatile ("" :::"fflags"); +} + +// CHECK-LABEL: define {{.*}} void @test_frm +// CHECK: tail call void asm sideeffect "", "~{frm}"() +void test_frm(void) { + asm volatile ("" :::"frm"); +} + +// CHECK-LABEL: define {{.*}} void @test_vtype +// CHECK: tail call void asm sideeffect "", "~{vtype}"() +void test_vtype(void) { + asm volatile ("" :::"vtype"); +} + +// CHECK-LABEL: define {{.*}} void @test_vl +// CHECK: tail call void asm sideeffect "", "~{vl}"() +void test_vl(void) { + asm volatile ("" :::"vl"); +} + +// CHECK-LABEL: define {{.*}} void @test_vxsat +// CHECK: tail call void asm sideeffect "", "~{vxsat}"() +void test_vxsat(void) { + asm volatile ("" :::"vxsat"); +} + +// CHECK-LABEL: define {{.*}} void @test_vxrm +// CHECK: tail call void asm sideeffect "", "~{vxrm}"() +void test_vxrm(void) { + asm volatile ("" :::"vxrm"); +} diff --git a/clang/test/CodeGen/RISCV/riscv-sdata-module-flag.c b/clang/test/CodeGen/RISCV/riscv-sdata-module-flag.c index e758b384bc6eb..9bd69e7995877 100644 --- a/clang/test/CodeGen/RISCV/riscv-sdata-module-flag.c +++ b/clang/test/CodeGen/RISCV/riscv-sdata-module-flag.c @@ -27,8 +27,6 @@ // RUN: | FileCheck %s -check-prefix=RV64-ANDROID // RUN: %clang --target=riscv64-unknown-elf %s -S -emit-llvm -fpic -o - \ // RUN: | FileCheck %s -check-prefix=RV64-PIC -// RUN: %clang --target=riscv64-unknown-elf %s -S -emit-llvm -mcmodel=large -o - \ -// RUN: | FileCheck %s -check-prefix=RV64-LARGE void test(void) {} diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c index aa5bebe38dd6b..ae9153eff155e 100644 --- a/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c +++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c @@ -1,7 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple riscv32 -target-feature +zbc -emit-llvm %s -o - \ +// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \ // RUN: | FileCheck %s -check-prefix=RV32ZBC // RUN: %clang_cc1 -triple riscv64 -target-feature +zbc -emit-llvm %s -o - \ +// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \ // RUN: | FileCheck %s -check-prefix=RV64ZBC #include @@ -9,14 +11,8 @@ #if __riscv_xlen == 64 // RV64ZBC-LABEL: @clmul_64( // RV64ZBC-NEXT: entry: -// RV64ZBC-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// RV64ZBC-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// RV64ZBC-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8 -// RV64ZBC-NEXT: store i64 [[B:%.*]], ptr [[B_ADDR]], align 8 -// RV64ZBC-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 -// RV64ZBC-NEXT: [[TMP1:%.*]] = load i64, ptr [[B_ADDR]], align 8 -// RV64ZBC-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.clmul.i64(i64 [[TMP0]], i64 [[TMP1]]) -// RV64ZBC-NEXT: ret i64 [[TMP2]] +// RV64ZBC-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.clmul.i64(i64 [[A:%.*]], i64 [[B:%.*]]) +// RV64ZBC-NEXT: ret i64 [[TMP0]] // uint64_t clmul_64(uint64_t a, uint64_t b) { return __builtin_riscv_clmul_64(a, b); @@ -24,14 +20,8 @@ uint64_t clmul_64(uint64_t a, uint64_t b) { // RV64ZBC-LABEL: @clmulh_64( // RV64ZBC-NEXT: entry: -// RV64ZBC-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// RV64ZBC-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// RV64ZBC-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8 -// RV64ZBC-NEXT: store i64 [[B:%.*]], ptr [[B_ADDR]], align 8 -// RV64ZBC-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 -// RV64ZBC-NEXT: [[TMP1:%.*]] = load i64, ptr [[B_ADDR]], align 8 -// RV64ZBC-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.clmulh.i64(i64 [[TMP0]], i64 [[TMP1]]) -// RV64ZBC-NEXT: ret i64 [[TMP2]] +// RV64ZBC-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.clmulh.i64(i64 [[A:%.*]], i64 [[B:%.*]]) +// RV64ZBC-NEXT: ret i64 [[TMP0]] // uint64_t clmulh_64(uint64_t a, uint64_t b) { return __builtin_riscv_clmulh_64(a, b); @@ -39,14 +29,8 @@ uint64_t clmulh_64(uint64_t a, uint64_t b) { // RV64ZBC-LABEL: @clmulr_64( // RV64ZBC-NEXT: entry: -// RV64ZBC-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// RV64ZBC-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// RV64ZBC-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8 -// RV64ZBC-NEXT: store i64 [[B:%.*]], ptr [[B_ADDR]], align 8 -// RV64ZBC-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 -// RV64ZBC-NEXT: [[TMP1:%.*]] = load i64, ptr [[B_ADDR]], align 8 -// RV64ZBC-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.clmulr.i64(i64 [[TMP0]], i64 [[TMP1]]) -// RV64ZBC-NEXT: ret i64 [[TMP2]] +// RV64ZBC-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.clmulr.i64(i64 [[A:%.*]], i64 [[B:%.*]]) +// RV64ZBC-NEXT: ret i64 [[TMP0]] // uint64_t clmulr_64(uint64_t a, uint64_t b) { return __builtin_riscv_clmulr_64(a, b); @@ -55,25 +39,13 @@ uint64_t clmulr_64(uint64_t a, uint64_t b) { // RV32ZBC-LABEL: @clmul_32( // RV32ZBC-NEXT: entry: -// RV32ZBC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// RV32ZBC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// RV32ZBC-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// RV32ZBC-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// RV32ZBC-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// RV32ZBC-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// RV32ZBC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[TMP0]], i32 [[TMP1]]) -// RV32ZBC-NEXT: ret i32 [[TMP2]] +// RV32ZBC-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[A:%.*]], i32 [[B:%.*]]) +// RV32ZBC-NEXT: ret i32 [[TMP0]] // // RV64ZBC-LABEL: @clmul_32( // RV64ZBC-NEXT: entry: -// RV64ZBC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// RV64ZBC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// RV64ZBC-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// RV64ZBC-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// RV64ZBC-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// RV64ZBC-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// RV64ZBC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[TMP0]], i32 [[TMP1]]) -// RV64ZBC-NEXT: ret i32 [[TMP2]] +// RV64ZBC-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[A:%.*]], i32 [[B:%.*]]) +// RV64ZBC-NEXT: ret i32 [[TMP0]] // uint32_t clmul_32(uint32_t a, uint32_t b) { return __builtin_riscv_clmul_32(a, b); @@ -82,14 +54,8 @@ uint32_t clmul_32(uint32_t a, uint32_t b) { #if __riscv_xlen == 32 // RV32ZBC-LABEL: @clmulh_32( // RV32ZBC-NEXT: entry: -// RV32ZBC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// RV32ZBC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// RV32ZBC-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// RV32ZBC-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// RV32ZBC-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// RV32ZBC-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// RV32ZBC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmulh.i32(i32 [[TMP0]], i32 [[TMP1]]) -// RV32ZBC-NEXT: ret i32 [[TMP2]] +// RV32ZBC-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.clmulh.i32(i32 [[A:%.*]], i32 [[B:%.*]]) +// RV32ZBC-NEXT: ret i32 [[TMP0]] // uint32_t clmulh_32(uint32_t a, uint32_t b) { return __builtin_riscv_clmulh_32(a, b); @@ -97,14 +63,8 @@ uint32_t clmulh_32(uint32_t a, uint32_t b) { // RV32ZBC-LABEL: @clmulr_32( // RV32ZBC-NEXT: entry: -// RV32ZBC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// RV32ZBC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// RV32ZBC-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// RV32ZBC-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// RV32ZBC-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// RV32ZBC-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// RV32ZBC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmulr.i32(i32 [[TMP0]], i32 [[TMP1]]) -// RV32ZBC-NEXT: ret i32 [[TMP2]] +// RV32ZBC-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.clmulr.i32(i32 [[A:%.*]], i32 [[B:%.*]]) +// RV32ZBC-NEXT: ret i32 [[TMP0]] // uint32_t clmulr_32(uint32_t a, uint32_t b) { return __builtin_riscv_clmulr_32(a, b); diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmacc_2x8x2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmacc_2x8x2.c new file mode 100644 index 0000000000000..29ebeea7a04e0 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmacc_2x8x2.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_2x8x2_i32m1 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmacc_2x8x2_i32m1(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmacc_2x8x2_i32m1(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_2x8x2_i32m2 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmacc_2x8x2_i32m2(vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmacc_2x8x2_i32m2(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_2x8x2_i32m4 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmacc_2x8x2_i32m4(vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmacc_2x8x2_i32m4(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_2x8x2_i32m8 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmacc_2x8x2_i32m8(vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmacc_2x8x2_i32m8(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmacc_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmacc_4x8x4.c new file mode 100644 index 0000000000000..935cb2e007d35 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmacc_4x8x4.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m1 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmacc_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmacc_4x8x4_i32m1(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m2 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmacc_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmacc_4x8x4_i32m2(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m4 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmacc_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmacc_4x8x4_i32m4(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m8 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmacc_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmacc_4x8x4_i32m8(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c new file mode 100644 index 0000000000000..a1f95d2c150f2 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_2x8x2_i32m1 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmaccsu_2x8x2_i32m1(vint32m1_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_2x8x2_i32m1(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_2x8x2_i32m2 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmaccsu_2x8x2_i32m2(vint32m2_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_2x8x2_i32m2(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_2x8x2_i32m4 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmaccsu_2x8x2_i32m4(vint32m4_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_2x8x2_i32m4(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_2x8x2_i32m8 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmaccsu_2x8x2_i32m8(vint32m8_t vd, vint8m1_t vs1, vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_2x8x2_i32m8(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c new file mode 100644 index 0000000000000..f34517b24bcf2 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m1 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_4x8x4_i32m1(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m2 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_4x8x4_i32m2(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m4 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_4x8x4_i32m4(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m8 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_4x8x4_i32m8(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c new file mode 100644 index 0000000000000..9f887562e12b4 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_2x8x2_i32m1 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmaccu_2x8x2_i32m1(vint32m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_2x8x2_i32m1(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_2x8x2_i32m2 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmaccu_2x8x2_i32m2(vint32m2_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_2x8x2_i32m2(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_2x8x2_i32m4 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmaccu_2x8x2_i32m4(vint32m4_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_2x8x2_i32m4(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_2x8x2_i32m8 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmaccu_2x8x2_i32m8(vint32m8_t vd, vuint8m1_t vs1, vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_2x8x2_i32m8(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c new file mode 100644 index 0000000000000..ab7f6627ad1fb --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m1 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmaccu_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_4x8x4_i32m1(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m2 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmaccu_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_4x8x4_i32m2(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m4 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmaccu_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_4x8x4_i32m4(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m8 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmaccu_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_4x8x4_i32m8(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c new file mode 100644 index 0000000000000..2921228700d2b --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_2x8x2_i32m1 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmaccus_2x8x2_i32m1(vint32m1_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_2x8x2_i32m1(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_2x8x2_i32m2 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmaccus_2x8x2_i32m2(vint32m2_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_2x8x2_i32m2(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_2x8x2_i32m4 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmaccus_2x8x2_i32m4(vint32m4_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_2x8x2_i32m4(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_2x8x2_i32m8 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmaccus_2x8x2_i32m8(vint32m8_t vd, vuint8m1_t vs1, vint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_2x8x2_i32m8(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c new file mode 100644 index 0000000000000..d0bcdcbf40cc3 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m1 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmaccus_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_4x8x4_i32m1(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m2 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmaccus_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_4x8x4_i32m2(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m4 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmaccus_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_4x8x4_i32m4(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m8 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmaccus_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_4x8x4_i32m8(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c index 5f474f8a5f555..721fde373ab12 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c @@ -1,4 +1,4 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: -target-feature +zvfh -disable-O0-optnone \ @@ -7,534 +7,2189 @@ #include -// CHECK-RV64-LABEL: define dso_local @test_vundefined_f16mf4 -// CHECK-RV64-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_f16mf4( +// CHECK-RV64-SAME: ) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vfloat16mf4_t test_vundefined_f16mf4() { - return __riscv_vundefined_f16mf4(); -} +vfloat16mf4_t test_vundefined_f16mf4() { return __riscv_vundefined_f16mf4(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_f16mf2 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_f16mf2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vfloat16mf2_t test_vundefined_f16mf2() { - return __riscv_vundefined_f16mf2(); -} +vfloat16mf2_t test_vundefined_f16mf2() { return __riscv_vundefined_f16mf2(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_f16m1 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_f16m1( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vfloat16m1_t test_vundefined_f16m1() { - return __riscv_vundefined_f16m1(); -} +vfloat16m1_t test_vundefined_f16m1() { return __riscv_vundefined_f16m1(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_f16m2 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_f16m2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vfloat16m2_t test_vundefined_f16m2() { - return __riscv_vundefined_f16m2(); -} +vfloat16m2_t test_vundefined_f16m2() { return __riscv_vundefined_f16m2(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_f16m4 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_f16m4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vfloat16m4_t test_vundefined_f16m4() { - return __riscv_vundefined_f16m4(); -} +vfloat16m4_t test_vundefined_f16m4() { return __riscv_vundefined_f16m4(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_f16m8 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_f16m8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vfloat16m8_t test_vundefined_f16m8() { - return __riscv_vundefined_f16m8(); -} +vfloat16m8_t test_vundefined_f16m8() { return __riscv_vundefined_f16m8(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_f32mf2 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_f32mf2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vfloat32mf2_t test_vundefined_f32mf2() { - return __riscv_vundefined_f32mf2(); -} +vfloat32mf2_t test_vundefined_f32mf2() { return __riscv_vundefined_f32mf2(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_f32m1 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_f32m1( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vfloat32m1_t test_vundefined_f32m1() { - return __riscv_vundefined_f32m1(); -} +vfloat32m1_t test_vundefined_f32m1() { return __riscv_vundefined_f32m1(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_f32m2 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_f32m2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vfloat32m2_t test_vundefined_f32m2() { - return __riscv_vundefined_f32m2(); -} +vfloat32m2_t test_vundefined_f32m2() { return __riscv_vundefined_f32m2(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_f32m4 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_f32m4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vfloat32m4_t test_vundefined_f32m4() { - return __riscv_vundefined_f32m4(); -} +vfloat32m4_t test_vundefined_f32m4() { return __riscv_vundefined_f32m4(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_f32m8 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_f32m8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vfloat32m8_t test_vundefined_f32m8() { - return __riscv_vundefined_f32m8(); -} +vfloat32m8_t test_vundefined_f32m8() { return __riscv_vundefined_f32m8(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_f64m1 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_f64m1( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vfloat64m1_t test_vundefined_f64m1() { - return __riscv_vundefined_f64m1(); -} +vfloat64m1_t test_vundefined_f64m1() { return __riscv_vundefined_f64m1(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_f64m2 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_f64m2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vfloat64m2_t test_vundefined_f64m2() { - return __riscv_vundefined_f64m2(); -} +vfloat64m2_t test_vundefined_f64m2() { return __riscv_vundefined_f64m2(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_f64m4 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_f64m4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vfloat64m4_t test_vundefined_f64m4() { - return __riscv_vundefined_f64m4(); -} +vfloat64m4_t test_vundefined_f64m4() { return __riscv_vundefined_f64m4(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_f64m8 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_f64m8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vfloat64m8_t test_vundefined_f64m8() { - return __riscv_vundefined_f64m8(); -} +vfloat64m8_t test_vundefined_f64m8() { return __riscv_vundefined_f64m8(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_i8mf8 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_i8mf8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vint8mf8_t test_vundefined_i8mf8() { - return __riscv_vundefined_i8mf8(); -} +vint8mf8_t test_vundefined_i8mf8() { return __riscv_vundefined_i8mf8(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_i8mf4 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_i8mf4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vint8mf4_t test_vundefined_i8mf4() { - return __riscv_vundefined_i8mf4(); -} +vint8mf4_t test_vundefined_i8mf4() { return __riscv_vundefined_i8mf4(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_i8mf2 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_i8mf2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vint8mf2_t test_vundefined_i8mf2() { - return __riscv_vundefined_i8mf2(); -} +vint8mf2_t test_vundefined_i8mf2() { return __riscv_vundefined_i8mf2(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_i8m1 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_i8m1( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vint8m1_t test_vundefined_i8m1() { - return __riscv_vundefined_i8m1(); -} +vint8m1_t test_vundefined_i8m1() { return __riscv_vundefined_i8m1(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_i8m2 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_i8m2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vint8m2_t test_vundefined_i8m2() { - return __riscv_vundefined_i8m2(); -} +vint8m2_t test_vundefined_i8m2() { return __riscv_vundefined_i8m2(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_i8m4 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_i8m4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vint8m4_t test_vundefined_i8m4() { - return __riscv_vundefined_i8m4(); -} +vint8m4_t test_vundefined_i8m4() { return __riscv_vundefined_i8m4(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_i8m8 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_i8m8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vint8m8_t test_vundefined_i8m8() { - return __riscv_vundefined_i8m8(); -} +vint8m8_t test_vundefined_i8m8() { return __riscv_vundefined_i8m8(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_i16mf4 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_i16mf4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vint16mf4_t test_vundefined_i16mf4() { - return __riscv_vundefined_i16mf4(); -} +vint16mf4_t test_vundefined_i16mf4() { return __riscv_vundefined_i16mf4(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_i16mf2 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_i16mf2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vint16mf2_t test_vundefined_i16mf2() { - return __riscv_vundefined_i16mf2(); -} +vint16mf2_t test_vundefined_i16mf2() { return __riscv_vundefined_i16mf2(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_i16m1 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_i16m1( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vint16m1_t test_vundefined_i16m1() { - return __riscv_vundefined_i16m1(); -} +vint16m1_t test_vundefined_i16m1() { return __riscv_vundefined_i16m1(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_i16m2 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_i16m2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vint16m2_t test_vundefined_i16m2() { - return __riscv_vundefined_i16m2(); -} +vint16m2_t test_vundefined_i16m2() { return __riscv_vundefined_i16m2(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_i16m4 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_i16m4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vint16m4_t test_vundefined_i16m4() { - return __riscv_vundefined_i16m4(); -} +vint16m4_t test_vundefined_i16m4() { return __riscv_vundefined_i16m4(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_i16m8 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_i16m8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vint16m8_t test_vundefined_i16m8() { - return __riscv_vundefined_i16m8(); -} +vint16m8_t test_vundefined_i16m8() { return __riscv_vundefined_i16m8(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_i32mf2 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_i32mf2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vint32mf2_t test_vundefined_i32mf2() { - return __riscv_vundefined_i32mf2(); -} +vint32mf2_t test_vundefined_i32mf2() { return __riscv_vundefined_i32mf2(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_i32m1 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_i32m1( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vint32m1_t test_vundefined_i32m1() { - return __riscv_vundefined_i32m1(); -} +vint32m1_t test_vundefined_i32m1() { return __riscv_vundefined_i32m1(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_i32m2 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_i32m2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vint32m2_t test_vundefined_i32m2() { - return __riscv_vundefined_i32m2(); -} +vint32m2_t test_vundefined_i32m2() { return __riscv_vundefined_i32m2(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_i32m4 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_i32m4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vint32m4_t test_vundefined_i32m4() { - return __riscv_vundefined_i32m4(); -} +vint32m4_t test_vundefined_i32m4() { return __riscv_vundefined_i32m4(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_i32m8 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_i32m8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vint32m8_t test_vundefined_i32m8() { - return __riscv_vundefined_i32m8(); -} +vint32m8_t test_vundefined_i32m8() { return __riscv_vundefined_i32m8(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_i64m1 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_i64m1( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vint64m1_t test_vundefined_i64m1() { - return __riscv_vundefined_i64m1(); -} +vint64m1_t test_vundefined_i64m1() { return __riscv_vundefined_i64m1(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_i64m2 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_i64m2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vint64m2_t test_vundefined_i64m2() { - return __riscv_vundefined_i64m2(); -} +vint64m2_t test_vundefined_i64m2() { return __riscv_vundefined_i64m2(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_i64m4 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_i64m4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vint64m4_t test_vundefined_i64m4() { - return __riscv_vundefined_i64m4(); -} +vint64m4_t test_vundefined_i64m4() { return __riscv_vundefined_i64m4(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_i64m8 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_i64m8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vint64m8_t test_vundefined_i64m8() { - return __riscv_vundefined_i64m8(); -} +vint64m8_t test_vundefined_i64m8() { return __riscv_vundefined_i64m8(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_u8mf8 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_u8mf8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vuint8mf8_t test_vundefined_u8mf8() { - return __riscv_vundefined_u8mf8(); -} +vuint8mf8_t test_vundefined_u8mf8() { return __riscv_vundefined_u8mf8(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_u8mf4 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_u8mf4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vuint8mf4_t test_vundefined_u8mf4() { - return __riscv_vundefined_u8mf4(); -} +vuint8mf4_t test_vundefined_u8mf4() { return __riscv_vundefined_u8mf4(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_u8mf2 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_u8mf2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vuint8mf2_t test_vundefined_u8mf2() { - return __riscv_vundefined_u8mf2(); -} +vuint8mf2_t test_vundefined_u8mf2() { return __riscv_vundefined_u8mf2(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_u8m1 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_u8m1( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vuint8m1_t test_vundefined_u8m1() { - return __riscv_vundefined_u8m1(); -} +vuint8m1_t test_vundefined_u8m1() { return __riscv_vundefined_u8m1(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_u8m2 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_u8m2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vuint8m2_t test_vundefined_u8m2() { - return __riscv_vundefined_u8m2(); -} +vuint8m2_t test_vundefined_u8m2() { return __riscv_vundefined_u8m2(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_u8m4 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_u8m4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vuint8m4_t test_vundefined_u8m4() { - return __riscv_vundefined_u8m4(); -} +vuint8m4_t test_vundefined_u8m4() { return __riscv_vundefined_u8m4(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_u8m8 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_u8m8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vuint8m8_t test_vundefined_u8m8() { - return __riscv_vundefined_u8m8(); -} +vuint8m8_t test_vundefined_u8m8() { return __riscv_vundefined_u8m8(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_u16mf4 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_u16mf4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vuint16mf4_t test_vundefined_u16mf4() { - return __riscv_vundefined_u16mf4(); -} +vuint16mf4_t test_vundefined_u16mf4() { return __riscv_vundefined_u16mf4(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_u16mf2 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_u16mf2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vuint16mf2_t test_vundefined_u16mf2() { - return __riscv_vundefined_u16mf2(); -} +vuint16mf2_t test_vundefined_u16mf2() { return __riscv_vundefined_u16mf2(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_u16m1 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_u16m1( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vuint16m1_t test_vundefined_u16m1() { - return __riscv_vundefined_u16m1(); -} +vuint16m1_t test_vundefined_u16m1() { return __riscv_vundefined_u16m1(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_u16m2 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_u16m2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vuint16m2_t test_vundefined_u16m2() { - return __riscv_vundefined_u16m2(); -} +vuint16m2_t test_vundefined_u16m2() { return __riscv_vundefined_u16m2(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_u16m4 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_u16m4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vuint16m4_t test_vundefined_u16m4() { - return __riscv_vundefined_u16m4(); -} +vuint16m4_t test_vundefined_u16m4() { return __riscv_vundefined_u16m4(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_u16m8 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_u16m8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vuint16m8_t test_vundefined_u16m8() { - return __riscv_vundefined_u16m8(); -} +vuint16m8_t test_vundefined_u16m8() { return __riscv_vundefined_u16m8(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_u32mf2 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_u32mf2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vuint32mf2_t test_vundefined_u32mf2() { - return __riscv_vundefined_u32mf2(); -} +vuint32mf2_t test_vundefined_u32mf2() { return __riscv_vundefined_u32mf2(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_u32m1 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_u32m1( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vuint32m1_t test_vundefined_u32m1() { - return __riscv_vundefined_u32m1(); -} +vuint32m1_t test_vundefined_u32m1() { return __riscv_vundefined_u32m1(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_u32m2 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_u32m2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vuint32m2_t test_vundefined_u32m2() { - return __riscv_vundefined_u32m2(); -} +vuint32m2_t test_vundefined_u32m2() { return __riscv_vundefined_u32m2(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_u32m4 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_u32m4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vuint32m4_t test_vundefined_u32m4() { - return __riscv_vundefined_u32m4(); -} +vuint32m4_t test_vundefined_u32m4() { return __riscv_vundefined_u32m4(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_u32m8 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_u32m8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vuint32m8_t test_vundefined_u32m8() { - return __riscv_vundefined_u32m8(); -} +vuint32m8_t test_vundefined_u32m8() { return __riscv_vundefined_u32m8(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_u64m1 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_u64m1( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vuint64m1_t test_vundefined_u64m1() { - return __riscv_vundefined_u64m1(); -} +vuint64m1_t test_vundefined_u64m1() { return __riscv_vundefined_u64m1(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_u64m2 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_u64m2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vuint64m2_t test_vundefined_u64m2() { - return __riscv_vundefined_u64m2(); -} +vuint64m2_t test_vundefined_u64m2() { return __riscv_vundefined_u64m2(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_u64m4 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_u64m4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vuint64m4_t test_vundefined_u64m4() { - return __riscv_vundefined_u64m4(); -} +vuint64m4_t test_vundefined_u64m4() { return __riscv_vundefined_u64m4(); } -// CHECK-RV64-LABEL: define dso_local @test_vundefined_u64m8 -// CHECK-RV64-SAME: () #[[ATTR0]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_u64m8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: ret poison // -vuint64m8_t test_vundefined_u64m8() { - return __riscv_vundefined_u64m8(); +vuint64m8_t test_vundefined_u64m8() { return __riscv_vundefined_u64m8(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_f16mf4x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vfloat16mf4x2_t test_vundefined_f16mf4x2() { + return __riscv_vundefined_f16mf4x2(); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_f16mf4x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vfloat16mf4x3_t test_vundefined_f16mf4x3() { + return __riscv_vundefined_f16mf4x3(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_f16mf4x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vfloat16mf4x4_t test_vundefined_f16mf4x4() { + return __riscv_vundefined_f16mf4x4(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_f16mf4x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vfloat16mf4x5_t test_vundefined_f16mf4x5() { + return __riscv_vundefined_f16mf4x5(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_f16mf4x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vfloat16mf4x6_t test_vundefined_f16mf4x6() { + return __riscv_vundefined_f16mf4x6(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_f16mf4x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vfloat16mf4x7_t test_vundefined_f16mf4x7() { + return __riscv_vundefined_f16mf4x7(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_f16mf4x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vfloat16mf4x8_t test_vundefined_f16mf4x8() { + return __riscv_vundefined_f16mf4x8(); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_f16mf2x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vfloat16mf2x2_t test_vundefined_f16mf2x2() { + return __riscv_vundefined_f16mf2x2(); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_f16mf2x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vfloat16mf2x3_t test_vundefined_f16mf2x3() { + return __riscv_vundefined_f16mf2x3(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_f16mf2x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vfloat16mf2x4_t test_vundefined_f16mf2x4() { + return __riscv_vundefined_f16mf2x4(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_f16mf2x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vfloat16mf2x5_t test_vundefined_f16mf2x5() { + return __riscv_vundefined_f16mf2x5(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_f16mf2x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vfloat16mf2x6_t test_vundefined_f16mf2x6() { + return __riscv_vundefined_f16mf2x6(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_f16mf2x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vfloat16mf2x7_t test_vundefined_f16mf2x7() { + return __riscv_vundefined_f16mf2x7(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_f16mf2x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vfloat16mf2x8_t test_vundefined_f16mf2x8() { + return __riscv_vundefined_f16mf2x8(); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_f16m1x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vfloat16m1x2_t test_vundefined_f16m1x2() { + return __riscv_vundefined_f16m1x2(); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_f16m1x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vfloat16m1x3_t test_vundefined_f16m1x3() { + return __riscv_vundefined_f16m1x3(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_f16m1x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vfloat16m1x4_t test_vundefined_f16m1x4() { + return __riscv_vundefined_f16m1x4(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_f16m1x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vfloat16m1x5_t test_vundefined_f16m1x5() { + return __riscv_vundefined_f16m1x5(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_f16m1x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vfloat16m1x6_t test_vundefined_f16m1x6() { + return __riscv_vundefined_f16m1x6(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_f16m1x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vfloat16m1x7_t test_vundefined_f16m1x7() { + return __riscv_vundefined_f16m1x7(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_f16m1x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vfloat16m1x8_t test_vundefined_f16m1x8() { + return __riscv_vundefined_f16m1x8(); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_f16m2x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vfloat16m2x2_t test_vundefined_f16m2x2() { + return __riscv_vundefined_f16m2x2(); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_f16m2x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vfloat16m2x3_t test_vundefined_f16m2x3() { + return __riscv_vundefined_f16m2x3(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_f16m2x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vfloat16m2x4_t test_vundefined_f16m2x4() { + return __riscv_vundefined_f16m2x4(); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_f16m4x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vfloat16m4x2_t test_vundefined_f16m4x2() { + return __riscv_vundefined_f16m4x2(); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_f32mf2x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vfloat32mf2x2_t test_vundefined_f32mf2x2() { + return __riscv_vundefined_f32mf2x2(); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_f32mf2x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vfloat32mf2x3_t test_vundefined_f32mf2x3() { + return __riscv_vundefined_f32mf2x3(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_f32mf2x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vfloat32mf2x4_t test_vundefined_f32mf2x4() { + return __riscv_vundefined_f32mf2x4(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_f32mf2x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vfloat32mf2x5_t test_vundefined_f32mf2x5() { + return __riscv_vundefined_f32mf2x5(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_f32mf2x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vfloat32mf2x6_t test_vundefined_f32mf2x6() { + return __riscv_vundefined_f32mf2x6(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_f32mf2x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vfloat32mf2x7_t test_vundefined_f32mf2x7() { + return __riscv_vundefined_f32mf2x7(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_f32mf2x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vfloat32mf2x8_t test_vundefined_f32mf2x8() { + return __riscv_vundefined_f32mf2x8(); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_f32m1x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vfloat32m1x2_t test_vundefined_f32m1x2() { + return __riscv_vundefined_f32m1x2(); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_f32m1x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vfloat32m1x3_t test_vundefined_f32m1x3() { + return __riscv_vundefined_f32m1x3(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_f32m1x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vfloat32m1x4_t test_vundefined_f32m1x4() { + return __riscv_vundefined_f32m1x4(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_f32m1x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vfloat32m1x5_t test_vundefined_f32m1x5() { + return __riscv_vundefined_f32m1x5(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_f32m1x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vfloat32m1x6_t test_vundefined_f32m1x6() { + return __riscv_vundefined_f32m1x6(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_f32m1x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vfloat32m1x7_t test_vundefined_f32m1x7() { + return __riscv_vundefined_f32m1x7(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_f32m1x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vfloat32m1x8_t test_vundefined_f32m1x8() { + return __riscv_vundefined_f32m1x8(); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_f32m2x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vfloat32m2x2_t test_vundefined_f32m2x2() { + return __riscv_vundefined_f32m2x2(); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_f32m2x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vfloat32m2x3_t test_vundefined_f32m2x3() { + return __riscv_vundefined_f32m2x3(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_f32m2x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vfloat32m2x4_t test_vundefined_f32m2x4() { + return __riscv_vundefined_f32m2x4(); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_f32m4x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vfloat32m4x2_t test_vundefined_f32m4x2() { + return __riscv_vundefined_f32m4x2(); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_f64m1x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vfloat64m1x2_t test_vundefined_f64m1x2() { + return __riscv_vundefined_f64m1x2(); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_f64m1x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vfloat64m1x3_t test_vundefined_f64m1x3() { + return __riscv_vundefined_f64m1x3(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_f64m1x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vfloat64m1x4_t test_vundefined_f64m1x4() { + return __riscv_vundefined_f64m1x4(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_f64m1x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vfloat64m1x5_t test_vundefined_f64m1x5() { + return __riscv_vundefined_f64m1x5(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_f64m1x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vfloat64m1x6_t test_vundefined_f64m1x6() { + return __riscv_vundefined_f64m1x6(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_f64m1x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vfloat64m1x7_t test_vundefined_f64m1x7() { + return __riscv_vundefined_f64m1x7(); } +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_f64m1x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vfloat64m1x8_t test_vundefined_f64m1x8() { + return __riscv_vundefined_f64m1x8(); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_f64m2x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vfloat64m2x2_t test_vundefined_f64m2x2() { + return __riscv_vundefined_f64m2x2(); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_f64m2x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vfloat64m2x3_t test_vundefined_f64m2x3() { + return __riscv_vundefined_f64m2x3(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_f64m2x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vfloat64m2x4_t test_vundefined_f64m2x4() { + return __riscv_vundefined_f64m2x4(); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_f64m4x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vfloat64m4x2_t test_vundefined_f64m4x2() { + return __riscv_vundefined_f64m4x2(); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_i8mf8x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vint8mf8x2_t test_vundefined_i8mf8x2() { return __riscv_vundefined_i8mf8x2(); } + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_i8mf8x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vint8mf8x3_t test_vundefined_i8mf8x3() { return __riscv_vundefined_i8mf8x3(); } + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_i8mf8x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vint8mf8x4_t test_vundefined_i8mf8x4() { return __riscv_vundefined_i8mf8x4(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_i8mf8x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vint8mf8x5_t test_vundefined_i8mf8x5() { return __riscv_vundefined_i8mf8x5(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_i8mf8x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vint8mf8x6_t test_vundefined_i8mf8x6() { return __riscv_vundefined_i8mf8x6(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_i8mf8x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vint8mf8x7_t test_vundefined_i8mf8x7() { return __riscv_vundefined_i8mf8x7(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_i8mf8x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vint8mf8x8_t test_vundefined_i8mf8x8() { return __riscv_vundefined_i8mf8x8(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_i8mf4x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vint8mf4x2_t test_vundefined_i8mf4x2() { return __riscv_vundefined_i8mf4x2(); } + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_i8mf4x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vint8mf4x3_t test_vundefined_i8mf4x3() { return __riscv_vundefined_i8mf4x3(); } + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_i8mf4x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vint8mf4x4_t test_vundefined_i8mf4x4() { return __riscv_vundefined_i8mf4x4(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_i8mf4x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vint8mf4x5_t test_vundefined_i8mf4x5() { return __riscv_vundefined_i8mf4x5(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_i8mf4x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vint8mf4x6_t test_vundefined_i8mf4x6() { return __riscv_vundefined_i8mf4x6(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_i8mf4x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vint8mf4x7_t test_vundefined_i8mf4x7() { return __riscv_vundefined_i8mf4x7(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_i8mf4x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vint8mf4x8_t test_vundefined_i8mf4x8() { return __riscv_vundefined_i8mf4x8(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_i8mf2x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vint8mf2x2_t test_vundefined_i8mf2x2() { return __riscv_vundefined_i8mf2x2(); } + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_i8mf2x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vint8mf2x3_t test_vundefined_i8mf2x3() { return __riscv_vundefined_i8mf2x3(); } + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_i8mf2x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vint8mf2x4_t test_vundefined_i8mf2x4() { return __riscv_vundefined_i8mf2x4(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_i8mf2x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vint8mf2x5_t test_vundefined_i8mf2x5() { return __riscv_vundefined_i8mf2x5(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_i8mf2x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vint8mf2x6_t test_vundefined_i8mf2x6() { return __riscv_vundefined_i8mf2x6(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_i8mf2x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vint8mf2x7_t test_vundefined_i8mf2x7() { return __riscv_vundefined_i8mf2x7(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_i8mf2x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vint8mf2x8_t test_vundefined_i8mf2x8() { return __riscv_vundefined_i8mf2x8(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_i8m1x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vint8m1x2_t test_vundefined_i8m1x2() { return __riscv_vundefined_i8m1x2(); } + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_i8m1x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vint8m1x3_t test_vundefined_i8m1x3() { return __riscv_vundefined_i8m1x3(); } + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_i8m1x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vint8m1x4_t test_vundefined_i8m1x4() { return __riscv_vundefined_i8m1x4(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_i8m1x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vint8m1x5_t test_vundefined_i8m1x5() { return __riscv_vundefined_i8m1x5(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_i8m1x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vint8m1x6_t test_vundefined_i8m1x6() { return __riscv_vundefined_i8m1x6(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_i8m1x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vint8m1x7_t test_vundefined_i8m1x7() { return __riscv_vundefined_i8m1x7(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_i8m1x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vint8m1x8_t test_vundefined_i8m1x8() { return __riscv_vundefined_i8m1x8(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_i8m2x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vint8m2x2_t test_vundefined_i8m2x2() { return __riscv_vundefined_i8m2x2(); } + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_i8m2x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vint8m2x3_t test_vundefined_i8m2x3() { return __riscv_vundefined_i8m2x3(); } + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_i8m2x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vint8m2x4_t test_vundefined_i8m2x4() { return __riscv_vundefined_i8m2x4(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_i8m4x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vint8m4x2_t test_vundefined_i8m4x2() { return __riscv_vundefined_i8m4x2(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_i16mf4x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vint16mf4x2_t test_vundefined_i16mf4x2() { + return __riscv_vundefined_i16mf4x2(); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_i16mf4x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vint16mf4x3_t test_vundefined_i16mf4x3() { + return __riscv_vundefined_i16mf4x3(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_i16mf4x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vint16mf4x4_t test_vundefined_i16mf4x4() { + return __riscv_vundefined_i16mf4x4(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_i16mf4x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vint16mf4x5_t test_vundefined_i16mf4x5() { + return __riscv_vundefined_i16mf4x5(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_i16mf4x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vint16mf4x6_t test_vundefined_i16mf4x6() { + return __riscv_vundefined_i16mf4x6(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_i16mf4x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vint16mf4x7_t test_vundefined_i16mf4x7() { + return __riscv_vundefined_i16mf4x7(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_i16mf4x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vint16mf4x8_t test_vundefined_i16mf4x8() { + return __riscv_vundefined_i16mf4x8(); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_i16mf2x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vint16mf2x2_t test_vundefined_i16mf2x2() { + return __riscv_vundefined_i16mf2x2(); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_i16mf2x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vint16mf2x3_t test_vundefined_i16mf2x3() { + return __riscv_vundefined_i16mf2x3(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_i16mf2x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vint16mf2x4_t test_vundefined_i16mf2x4() { + return __riscv_vundefined_i16mf2x4(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_i16mf2x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vint16mf2x5_t test_vundefined_i16mf2x5() { + return __riscv_vundefined_i16mf2x5(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_i16mf2x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vint16mf2x6_t test_vundefined_i16mf2x6() { + return __riscv_vundefined_i16mf2x6(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_i16mf2x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vint16mf2x7_t test_vundefined_i16mf2x7() { + return __riscv_vundefined_i16mf2x7(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_i16mf2x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vint16mf2x8_t test_vundefined_i16mf2x8() { + return __riscv_vundefined_i16mf2x8(); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_i16m1x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vint16m1x2_t test_vundefined_i16m1x2() { return __riscv_vundefined_i16m1x2(); } + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_i16m1x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vint16m1x3_t test_vundefined_i16m1x3() { return __riscv_vundefined_i16m1x3(); } + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_i16m1x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vint16m1x4_t test_vundefined_i16m1x4() { return __riscv_vundefined_i16m1x4(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_i16m1x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vint16m1x5_t test_vundefined_i16m1x5() { return __riscv_vundefined_i16m1x5(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_i16m1x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vint16m1x6_t test_vundefined_i16m1x6() { return __riscv_vundefined_i16m1x6(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_i16m1x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vint16m1x7_t test_vundefined_i16m1x7() { return __riscv_vundefined_i16m1x7(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_i16m1x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vint16m1x8_t test_vundefined_i16m1x8() { return __riscv_vundefined_i16m1x8(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_i16m2x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vint16m2x2_t test_vundefined_i16m2x2() { return __riscv_vundefined_i16m2x2(); } + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_i16m2x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vint16m2x3_t test_vundefined_i16m2x3() { return __riscv_vundefined_i16m2x3(); } + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_i16m2x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vint16m2x4_t test_vundefined_i16m2x4() { return __riscv_vundefined_i16m2x4(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_i16m4x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vint16m4x2_t test_vundefined_i16m4x2() { return __riscv_vundefined_i16m4x2(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_i32mf2x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vint32mf2x2_t test_vundefined_i32mf2x2() { + return __riscv_vundefined_i32mf2x2(); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_i32mf2x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vint32mf2x3_t test_vundefined_i32mf2x3() { + return __riscv_vundefined_i32mf2x3(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_i32mf2x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vint32mf2x4_t test_vundefined_i32mf2x4() { + return __riscv_vundefined_i32mf2x4(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_i32mf2x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vint32mf2x5_t test_vundefined_i32mf2x5() { + return __riscv_vundefined_i32mf2x5(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_i32mf2x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vint32mf2x6_t test_vundefined_i32mf2x6() { + return __riscv_vundefined_i32mf2x6(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_i32mf2x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vint32mf2x7_t test_vundefined_i32mf2x7() { + return __riscv_vundefined_i32mf2x7(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_i32mf2x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vint32mf2x8_t test_vundefined_i32mf2x8() { + return __riscv_vundefined_i32mf2x8(); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_i32m1x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vint32m1x2_t test_vundefined_i32m1x2() { return __riscv_vundefined_i32m1x2(); } + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_i32m1x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vint32m1x3_t test_vundefined_i32m1x3() { return __riscv_vundefined_i32m1x3(); } + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_i32m1x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vint32m1x4_t test_vundefined_i32m1x4() { return __riscv_vundefined_i32m1x4(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_i32m1x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vint32m1x5_t test_vundefined_i32m1x5() { return __riscv_vundefined_i32m1x5(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_i32m1x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vint32m1x6_t test_vundefined_i32m1x6() { return __riscv_vundefined_i32m1x6(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_i32m1x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vint32m1x7_t test_vundefined_i32m1x7() { return __riscv_vundefined_i32m1x7(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_i32m1x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vint32m1x8_t test_vundefined_i32m1x8() { return __riscv_vundefined_i32m1x8(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_i32m2x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vint32m2x2_t test_vundefined_i32m2x2() { return __riscv_vundefined_i32m2x2(); } + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_i32m2x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vint32m2x3_t test_vundefined_i32m2x3() { return __riscv_vundefined_i32m2x3(); } + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_i32m2x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vint32m2x4_t test_vundefined_i32m2x4() { return __riscv_vundefined_i32m2x4(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_i32m4x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vint32m4x2_t test_vundefined_i32m4x2() { return __riscv_vundefined_i32m4x2(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_i64m1x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vint64m1x2_t test_vundefined_i64m1x2() { return __riscv_vundefined_i64m1x2(); } + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_i64m1x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vint64m1x3_t test_vundefined_i64m1x3() { return __riscv_vundefined_i64m1x3(); } + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_i64m1x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vint64m1x4_t test_vundefined_i64m1x4() { return __riscv_vundefined_i64m1x4(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_i64m1x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vint64m1x5_t test_vundefined_i64m1x5() { return __riscv_vundefined_i64m1x5(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_i64m1x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vint64m1x6_t test_vundefined_i64m1x6() { return __riscv_vundefined_i64m1x6(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_i64m1x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vint64m1x7_t test_vundefined_i64m1x7() { return __riscv_vundefined_i64m1x7(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_i64m1x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vint64m1x8_t test_vundefined_i64m1x8() { return __riscv_vundefined_i64m1x8(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_i64m2x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vint64m2x2_t test_vundefined_i64m2x2() { return __riscv_vundefined_i64m2x2(); } + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_i64m2x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vint64m2x3_t test_vundefined_i64m2x3() { return __riscv_vundefined_i64m2x3(); } + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_i64m2x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vint64m2x4_t test_vundefined_i64m2x4() { return __riscv_vundefined_i64m2x4(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_i64m4x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vint64m4x2_t test_vundefined_i64m4x2() { return __riscv_vundefined_i64m4x2(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_u8mf8x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vuint8mf8x2_t test_vundefined_u8mf8x2() { return __riscv_vundefined_u8mf8x2(); } + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_u8mf8x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vuint8mf8x3_t test_vundefined_u8mf8x3() { return __riscv_vundefined_u8mf8x3(); } + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_u8mf8x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vuint8mf8x4_t test_vundefined_u8mf8x4() { return __riscv_vundefined_u8mf8x4(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_u8mf8x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vuint8mf8x5_t test_vundefined_u8mf8x5() { return __riscv_vundefined_u8mf8x5(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_u8mf8x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vuint8mf8x6_t test_vundefined_u8mf8x6() { return __riscv_vundefined_u8mf8x6(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_u8mf8x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vuint8mf8x7_t test_vundefined_u8mf8x7() { return __riscv_vundefined_u8mf8x7(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_u8mf8x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vuint8mf8x8_t test_vundefined_u8mf8x8() { return __riscv_vundefined_u8mf8x8(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_u8mf4x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vuint8mf4x2_t test_vundefined_u8mf4x2() { return __riscv_vundefined_u8mf4x2(); } + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_u8mf4x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vuint8mf4x3_t test_vundefined_u8mf4x3() { return __riscv_vundefined_u8mf4x3(); } + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_u8mf4x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vuint8mf4x4_t test_vundefined_u8mf4x4() { return __riscv_vundefined_u8mf4x4(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_u8mf4x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vuint8mf4x5_t test_vundefined_u8mf4x5() { return __riscv_vundefined_u8mf4x5(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_u8mf4x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vuint8mf4x6_t test_vundefined_u8mf4x6() { return __riscv_vundefined_u8mf4x6(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_u8mf4x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vuint8mf4x7_t test_vundefined_u8mf4x7() { return __riscv_vundefined_u8mf4x7(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_u8mf4x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vuint8mf4x8_t test_vundefined_u8mf4x8() { return __riscv_vundefined_u8mf4x8(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_u8mf2x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vuint8mf2x2_t test_vundefined_u8mf2x2() { return __riscv_vundefined_u8mf2x2(); } + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_u8mf2x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vuint8mf2x3_t test_vundefined_u8mf2x3() { return __riscv_vundefined_u8mf2x3(); } + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_u8mf2x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vuint8mf2x4_t test_vundefined_u8mf2x4() { return __riscv_vundefined_u8mf2x4(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_u8mf2x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vuint8mf2x5_t test_vundefined_u8mf2x5() { return __riscv_vundefined_u8mf2x5(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_u8mf2x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vuint8mf2x6_t test_vundefined_u8mf2x6() { return __riscv_vundefined_u8mf2x6(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_u8mf2x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vuint8mf2x7_t test_vundefined_u8mf2x7() { return __riscv_vundefined_u8mf2x7(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_u8mf2x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vuint8mf2x8_t test_vundefined_u8mf2x8() { return __riscv_vundefined_u8mf2x8(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_u8m1x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vuint8m1x2_t test_vundefined_u8m1x2() { return __riscv_vundefined_u8m1x2(); } + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_u8m1x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vuint8m1x3_t test_vundefined_u8m1x3() { return __riscv_vundefined_u8m1x3(); } + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_u8m1x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vuint8m1x4_t test_vundefined_u8m1x4() { return __riscv_vundefined_u8m1x4(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_u8m1x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vuint8m1x5_t test_vundefined_u8m1x5() { return __riscv_vundefined_u8m1x5(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_u8m1x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vuint8m1x6_t test_vundefined_u8m1x6() { return __riscv_vundefined_u8m1x6(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_u8m1x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vuint8m1x7_t test_vundefined_u8m1x7() { return __riscv_vundefined_u8m1x7(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_u8m1x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vuint8m1x8_t test_vundefined_u8m1x8() { return __riscv_vundefined_u8m1x8(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_u8m2x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vuint8m2x2_t test_vundefined_u8m2x2() { return __riscv_vundefined_u8m2x2(); } + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_u8m2x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vuint8m2x3_t test_vundefined_u8m2x3() { return __riscv_vundefined_u8m2x3(); } + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_u8m2x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vuint8m2x4_t test_vundefined_u8m2x4() { return __riscv_vundefined_u8m2x4(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_u8m4x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vuint8m4x2_t test_vundefined_u8m4x2() { return __riscv_vundefined_u8m4x2(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_u16mf4x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vuint16mf4x2_t test_vundefined_u16mf4x2() { + return __riscv_vundefined_u16mf4x2(); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_u16mf4x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vuint16mf4x3_t test_vundefined_u16mf4x3() { + return __riscv_vundefined_u16mf4x3(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_u16mf4x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vuint16mf4x4_t test_vundefined_u16mf4x4() { + return __riscv_vundefined_u16mf4x4(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_u16mf4x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vuint16mf4x5_t test_vundefined_u16mf4x5() { + return __riscv_vundefined_u16mf4x5(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_u16mf4x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vuint16mf4x6_t test_vundefined_u16mf4x6() { + return __riscv_vundefined_u16mf4x6(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_u16mf4x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vuint16mf4x7_t test_vundefined_u16mf4x7() { + return __riscv_vundefined_u16mf4x7(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_u16mf4x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vuint16mf4x8_t test_vundefined_u16mf4x8() { + return __riscv_vundefined_u16mf4x8(); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_u16mf2x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vuint16mf2x2_t test_vundefined_u16mf2x2() { + return __riscv_vundefined_u16mf2x2(); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_u16mf2x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vuint16mf2x3_t test_vundefined_u16mf2x3() { + return __riscv_vundefined_u16mf2x3(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_u16mf2x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vuint16mf2x4_t test_vundefined_u16mf2x4() { + return __riscv_vundefined_u16mf2x4(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_u16mf2x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vuint16mf2x5_t test_vundefined_u16mf2x5() { + return __riscv_vundefined_u16mf2x5(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_u16mf2x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vuint16mf2x6_t test_vundefined_u16mf2x6() { + return __riscv_vundefined_u16mf2x6(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_u16mf2x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vuint16mf2x7_t test_vundefined_u16mf2x7() { + return __riscv_vundefined_u16mf2x7(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_u16mf2x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vuint16mf2x8_t test_vundefined_u16mf2x8() { + return __riscv_vundefined_u16mf2x8(); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_u16m1x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vuint16m1x2_t test_vundefined_u16m1x2() { return __riscv_vundefined_u16m1x2(); } + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_u16m1x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vuint16m1x3_t test_vundefined_u16m1x3() { return __riscv_vundefined_u16m1x3(); } + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_u16m1x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vuint16m1x4_t test_vundefined_u16m1x4() { return __riscv_vundefined_u16m1x4(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_u16m1x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vuint16m1x5_t test_vundefined_u16m1x5() { return __riscv_vundefined_u16m1x5(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_u16m1x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vuint16m1x6_t test_vundefined_u16m1x6() { return __riscv_vundefined_u16m1x6(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_u16m1x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vuint16m1x7_t test_vundefined_u16m1x7() { return __riscv_vundefined_u16m1x7(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_u16m1x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vuint16m1x8_t test_vundefined_u16m1x8() { return __riscv_vundefined_u16m1x8(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_u16m2x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vuint16m2x2_t test_vundefined_u16m2x2() { return __riscv_vundefined_u16m2x2(); } + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_u16m2x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vuint16m2x3_t test_vundefined_u16m2x3() { return __riscv_vundefined_u16m2x3(); } + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_u16m2x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vuint16m2x4_t test_vundefined_u16m2x4() { return __riscv_vundefined_u16m2x4(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_u16m4x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vuint16m4x2_t test_vundefined_u16m4x2() { return __riscv_vundefined_u16m4x2(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_u32mf2x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vuint32mf2x2_t test_vundefined_u32mf2x2() { + return __riscv_vundefined_u32mf2x2(); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_u32mf2x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vuint32mf2x3_t test_vundefined_u32mf2x3() { + return __riscv_vundefined_u32mf2x3(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_u32mf2x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vuint32mf2x4_t test_vundefined_u32mf2x4() { + return __riscv_vundefined_u32mf2x4(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_u32mf2x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vuint32mf2x5_t test_vundefined_u32mf2x5() { + return __riscv_vundefined_u32mf2x5(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_u32mf2x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vuint32mf2x6_t test_vundefined_u32mf2x6() { + return __riscv_vundefined_u32mf2x6(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_u32mf2x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vuint32mf2x7_t test_vundefined_u32mf2x7() { + return __riscv_vundefined_u32mf2x7(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_u32mf2x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vuint32mf2x8_t test_vundefined_u32mf2x8() { + return __riscv_vundefined_u32mf2x8(); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_u32m1x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vuint32m1x2_t test_vundefined_u32m1x2() { return __riscv_vundefined_u32m1x2(); } + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_u32m1x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vuint32m1x3_t test_vundefined_u32m1x3() { return __riscv_vundefined_u32m1x3(); } + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_u32m1x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vuint32m1x4_t test_vundefined_u32m1x4() { return __riscv_vundefined_u32m1x4(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_u32m1x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vuint32m1x5_t test_vundefined_u32m1x5() { return __riscv_vundefined_u32m1x5(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_u32m1x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vuint32m1x6_t test_vundefined_u32m1x6() { return __riscv_vundefined_u32m1x6(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_u32m1x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vuint32m1x7_t test_vundefined_u32m1x7() { return __riscv_vundefined_u32m1x7(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_u32m1x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vuint32m1x8_t test_vundefined_u32m1x8() { return __riscv_vundefined_u32m1x8(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_u32m2x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vuint32m2x2_t test_vundefined_u32m2x2() { return __riscv_vundefined_u32m2x2(); } + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_u32m2x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vuint32m2x3_t test_vundefined_u32m2x3() { return __riscv_vundefined_u32m2x3(); } + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_u32m2x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vuint32m2x4_t test_vundefined_u32m2x4() { return __riscv_vundefined_u32m2x4(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_u32m4x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vuint32m4x2_t test_vundefined_u32m4x2() { return __riscv_vundefined_u32m4x2(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_u64m1x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vuint64m1x2_t test_vundefined_u64m1x2() { return __riscv_vundefined_u64m1x2(); } + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_u64m1x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vuint64m1x3_t test_vundefined_u64m1x3() { return __riscv_vundefined_u64m1x3(); } + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_u64m1x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vuint64m1x4_t test_vundefined_u64m1x4() { return __riscv_vundefined_u64m1x4(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_u64m1x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vuint64m1x5_t test_vundefined_u64m1x5() { return __riscv_vundefined_u64m1x5(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_u64m1x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vuint64m1x6_t test_vundefined_u64m1x6() { return __riscv_vundefined_u64m1x6(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_u64m1x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vuint64m1x7_t test_vundefined_u64m1x7() { return __riscv_vundefined_u64m1x7(); } + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_u64m1x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vuint64m1x8_t test_vundefined_u64m1x8() { return __riscv_vundefined_u64m1x8(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_u64m2x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vuint64m2x2_t test_vundefined_u64m2x2() { return __riscv_vundefined_u64m2x2(); } + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_u64m2x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vuint64m2x3_t test_vundefined_u64m2x3() { return __riscv_vundefined_u64m2x3(); } + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_u64m2x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vuint64m2x4_t test_vundefined_u64m2x4() { return __riscv_vundefined_u64m2x4(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_u64m4x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vuint64m4x2_t test_vundefined_u64m4x2() { return __riscv_vundefined_u64m4x2(); } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmacc_2x8x2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmacc_2x8x2.c new file mode 100644 index 0000000000000..bef04c570710c --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmacc_2x8x2.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_2x8x2_i32m1 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmacc_2x8x2_i32m1(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmacc_2x8x2(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_2x8x2_i32m2 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmacc_2x8x2_i32m2(vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmacc_2x8x2(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_2x8x2_i32m4 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmacc_2x8x2_i32m4(vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmacc_2x8x2(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_2x8x2_i32m8 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmacc_2x8x2_i32m8(vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmacc_2x8x2(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmacc_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmacc_4x8x4.c new file mode 100644 index 0000000000000..839d09c4f9a98 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmacc_4x8x4.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m1 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmacc_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmacc_4x8x4(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m2 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmacc_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmacc_4x8x4(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m4 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmacc_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmacc_4x8x4(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m8 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmacc_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmacc_4x8x4(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccsu_2x8x2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccsu_2x8x2.c new file mode 100644 index 0000000000000..da0f632a3a9f5 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccsu_2x8x2.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_2x8x2_i32m1 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmaccsu_2x8x2_i32m1(vint32m1_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_2x8x2(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_2x8x2_i32m2 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmaccsu_2x8x2_i32m2(vint32m2_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_2x8x2(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_2x8x2_i32m4 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmaccsu_2x8x2_i32m4(vint32m4_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_2x8x2(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_2x8x2_i32m8 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmaccsu_2x8x2_i32m8(vint32m8_t vd, vint8m1_t vs1, vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_2x8x2(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccsu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccsu_4x8x4.c new file mode 100644 index 0000000000000..b18853043e924 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccsu_4x8x4.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m1 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_4x8x4(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m2 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_4x8x4(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m4 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_4x8x4(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m8 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_4x8x4(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccu_2x8x2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccu_2x8x2.c new file mode 100644 index 0000000000000..c58182cf3c08e --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccu_2x8x2.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_2x8x2_i32m1 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmaccu_2x8x2_i32m1(vint32m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_2x8x2(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_2x8x2_i32m2 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmaccu_2x8x2_i32m2(vint32m2_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_2x8x2(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_2x8x2_i32m4 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmaccu_2x8x2_i32m4(vint32m4_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_2x8x2(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_2x8x2_i32m8 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmaccu_2x8x2_i32m8(vint32m8_t vd, vuint8m1_t vs1, vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_2x8x2(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccu_4x8x4.c new file mode 100644 index 0000000000000..4cb966b08f237 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccu_4x8x4.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m1 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmaccu_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_4x8x4(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m2 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmaccu_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_4x8x4(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m4 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmaccu_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_4x8x4(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m8 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmaccu_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_4x8x4(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccus_2x8x2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccus_2x8x2.c new file mode 100644 index 0000000000000..a16f576e539db --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccus_2x8x2.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_2x8x2_i32m1 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmaccus_2x8x2_i32m1(vint32m1_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_2x8x2(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_2x8x2_i32m2 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmaccus_2x8x2_i32m2(vint32m2_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_2x8x2(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_2x8x2_i32m4 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmaccus_2x8x2_i32m4(vint32m4_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_2x8x2(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_2x8x2_i32m8 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmaccus_2x8x2_i32m8(vint32m8_t vd, vuint8m1_t vs1, vint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_2x8x2(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccus_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccus_4x8x4.c new file mode 100644 index 0000000000000..f558151f88a3f --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccus_4x8x4.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m1 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmaccus_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_4x8x4(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m2 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmaccus_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_4x8x4(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m4 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmaccus_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_4x8x4(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m8 +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmaccus_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_4x8x4(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmacc_2x8x2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmacc_2x8x2.c new file mode 100644 index 0000000000000..b4f0729d2fdde --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmacc_2x8x2.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_2x8x2_i32m1_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmacc_2x8x2_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmacc_2x8x2_i32m1_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_2x8x2_i32m2_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmacc_2x8x2_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmacc_2x8x2_i32m2_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_2x8x2_i32m4_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmacc_2x8x2_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmacc_2x8x2_i32m4_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_2x8x2_i32m8_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmacc_2x8x2_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmacc_2x8x2_i32m8_tu(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmacc_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmacc_4x8x4.c new file mode 100644 index 0000000000000..05c10840cabfa --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmacc_4x8x4.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m1_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmacc_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmacc_4x8x4_i32m1_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m2_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmacc_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmacc_4x8x4_i32m2_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m4_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmacc_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmacc_4x8x4_i32m4_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m8_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmacc_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmacc_4x8x4_i32m8_tu(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccsu_2x8x2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccsu_2x8x2.c new file mode 100644 index 0000000000000..612f8c3cfa613 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccsu_2x8x2.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_2x8x2_i32m1_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmaccsu_2x8x2_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_2x8x2_i32m1_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_2x8x2_i32m2_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmaccsu_2x8x2_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_2x8x2_i32m2_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_2x8x2_i32m4_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmaccsu_2x8x2_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_2x8x2_i32m4_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_2x8x2_i32m8_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmaccsu_2x8x2_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_2x8x2_i32m8_tu(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccsu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccsu_4x8x4.c new file mode 100644 index 0000000000000..bce1a4e9443fd --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccsu_4x8x4.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m1_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_4x8x4_i32m1_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m2_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_4x8x4_i32m2_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m4_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_4x8x4_i32m4_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m8_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_4x8x4_i32m8_tu(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccu_2x8x2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccu_2x8x2.c new file mode 100644 index 0000000000000..6ffe84df87c2c --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccu_2x8x2.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_2x8x2_i32m1_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmaccu_2x8x2_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_2x8x2_i32m1_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_2x8x2_i32m2_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmaccu_2x8x2_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_2x8x2_i32m2_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_2x8x2_i32m4_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmaccu_2x8x2_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_2x8x2_i32m4_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_2x8x2_i32m8_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmaccu_2x8x2_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_2x8x2_i32m8_tu(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccu_4x8x4.c new file mode 100644 index 0000000000000..36aaae9caebf6 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccu_4x8x4.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m1_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmaccu_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_4x8x4_i32m1_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m2_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmaccu_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_4x8x4_i32m2_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m4_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmaccu_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_4x8x4_i32m4_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m8_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmaccu_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_4x8x4_i32m8_tu(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccus_2x8x2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccus_2x8x2.c new file mode 100644 index 0000000000000..ebfd33f1b67a9 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccus_2x8x2.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_2x8x2_i32m1_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmaccus_2x8x2_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_2x8x2_i32m1_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_2x8x2_i32m2_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmaccus_2x8x2_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_2x8x2_i32m2_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_2x8x2_i32m4_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmaccus_2x8x2_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_2x8x2_i32m4_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_2x8x2_i32m8_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmaccus_2x8x2_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_2x8x2_i32m8_tu(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccus_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccus_4x8x4.c new file mode 100644 index 0000000000000..f5ac2bf0f1f3a --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccus_4x8x4.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m1_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmaccus_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_4x8x4_i32m1_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m2_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmaccus_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_4x8x4_i32m2_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m4_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmaccus_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_4x8x4_i32m4_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m8_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmaccus_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_4x8x4_i32m8_tu(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmacc_2x8x2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmacc_2x8x2.c new file mode 100644 index 0000000000000..6d7ca5ab4ee79 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmacc_2x8x2.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_2x8x2_i32m1_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmacc_2x8x2_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmacc_2x8x2_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_2x8x2_i32m2_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmacc_2x8x2_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmacc_2x8x2_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_2x8x2_i32m4_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmacc_2x8x2_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmacc_2x8x2_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_2x8x2_i32m8_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmacc_2x8x2_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmacc_2x8x2_tu(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmacc_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmacc_4x8x4.c new file mode 100644 index 0000000000000..531bc2b2b9425 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmacc_4x8x4.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m1_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmacc_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmacc_4x8x4_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m2_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmacc_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmacc_4x8x4_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m4_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmacc_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmacc_4x8x4_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m8_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmacc_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmacc_4x8x4_tu(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccsu_2x8x2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccsu_2x8x2.c new file mode 100644 index 0000000000000..ba6dae595bd34 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccsu_2x8x2.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_2x8x2_i32m1_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmaccsu_2x8x2_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_2x8x2_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_2x8x2_i32m2_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmaccsu_2x8x2_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_2x8x2_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_2x8x2_i32m4_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmaccsu_2x8x2_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_2x8x2_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_2x8x2_i32m8_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmaccsu_2x8x2_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_2x8x2_tu(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccsu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccsu_4x8x4.c new file mode 100644 index 0000000000000..23bba523aaa44 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccsu_4x8x4.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m1_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_4x8x4_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m2_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_4x8x4_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m4_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_4x8x4_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m8_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmaccsu_4x8x4_tu(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccu_2x8x2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccu_2x8x2.c new file mode 100644 index 0000000000000..9e15b053da244 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccu_2x8x2.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_2x8x2_i32m1_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmaccu_2x8x2_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_2x8x2_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_2x8x2_i32m2_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmaccu_2x8x2_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_2x8x2_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_2x8x2_i32m4_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmaccu_2x8x2_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_2x8x2_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_2x8x2_i32m8_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmaccu_2x8x2_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_2x8x2_tu(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccu_4x8x4.c new file mode 100644 index 0000000000000..950688c6c7851 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccu_4x8x4.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m1_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmaccu_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_4x8x4_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m2_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmaccu_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_4x8x4_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m4_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmaccu_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_4x8x4_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m8_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmaccu_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmaccu_4x8x4_tu(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccus_2x8x2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccus_2x8x2.c new file mode 100644 index 0000000000000..3108560c5be45 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccus_2x8x2.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_2x8x2_i32m1_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmaccus_2x8x2_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_2x8x2_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_2x8x2_i32m2_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmaccus_2x8x2_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_2x8x2_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_2x8x2_i32m4_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmaccus_2x8x2_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_2x8x2_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_2x8x2_i32m8_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmaccus_2x8x2_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_2x8x2_tu(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccus_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccus_4x8x4.c new file mode 100644 index 0000000000000..7bdce95043ee4 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccus_4x8x4.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m1_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_sf_vqmaccus_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_4x8x4_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m2_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_sf_vqmaccus_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_4x8x4_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m4_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_sf_vqmaccus_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_4x8x4_tu(vd, vs1, vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m8_tu +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vqmaccus_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vint8m8_t vs2, size_t vl) { + return __riscv_sf_vqmaccus_4x8x4_tu(vd, vs1, vs2, vl); +} diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c index 1b181bd59e7c8..cf4ec7afe3d7d 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c @@ -22,7 +22,7 @@ // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.addha.nxv4i32(i32 0, [[TMP0]], [[TMP1]], [[ZN]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z21test_svaddha_za32_u32u10__SVBool_tu10__SVBool_tu12__SVUint32_t( +// CHECK-CXX-LABEL: define dso_local void @_Z21test_svaddha_za32_u32u10__SVBool_tS_u12__SVUint32_t( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PN]]) @@ -42,7 +42,7 @@ void test_svaddha_za32_u32(svbool_t pn, svbool_t pm, svuint32_t zn) { // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.addha.nxv4i32(i32 3, [[TMP0]], [[TMP1]], [[ZN]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z23test_svaddha_za32_u32_1u10__SVBool_tu10__SVBool_tu12__SVUint32_t( +// CHECK-CXX-LABEL: define dso_local void @_Z23test_svaddha_za32_u32_1u10__SVBool_tS_u12__SVUint32_t( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PN]]) @@ -62,7 +62,7 @@ void test_svaddha_za32_u32_1(svbool_t pn, svbool_t pm, svuint32_t zn) { // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.addha.nxv4i32(i32 0, [[TMP0]], [[TMP1]], [[ZN]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z21test_svaddha_za32_s32u10__SVBool_tu10__SVBool_tu11__SVInt32_t( +// CHECK-CXX-LABEL: define dso_local void @_Z21test_svaddha_za32_s32u10__SVBool_tS_u11__SVInt32_t( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PN]]) @@ -82,7 +82,7 @@ void test_svaddha_za32_s32(svbool_t pn, svbool_t pm, svint32_t zn) { // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.addha.nxv4i32(i32 3, [[TMP0]], [[TMP1]], [[ZN]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z23test_svaddha_za32_s32_1u10__SVBool_tu10__SVBool_tu11__SVInt32_t( +// CHECK-CXX-LABEL: define dso_local void @_Z23test_svaddha_za32_s32_1u10__SVBool_tS_u11__SVInt32_t( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PN]]) @@ -102,7 +102,7 @@ void test_svaddha_za32_s32_1(svbool_t pn, svbool_t pm, svint32_t zn) { // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.addva.nxv4i32(i32 0, [[TMP0]], [[TMP1]], [[ZN]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z21test_svaddva_za32_u32u10__SVBool_tu10__SVBool_tu12__SVUint32_t( +// CHECK-CXX-LABEL: define dso_local void @_Z21test_svaddva_za32_u32u10__SVBool_tS_u12__SVUint32_t( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PN]]) @@ -122,7 +122,7 @@ void test_svaddva_za32_u32(svbool_t pn, svbool_t pm, svuint32_t zn) { // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.addva.nxv4i32(i32 3, [[TMP0]], [[TMP1]], [[ZN]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z23test_svaddva_za32_u32_1u10__SVBool_tu10__SVBool_tu12__SVUint32_t( +// CHECK-CXX-LABEL: define dso_local void @_Z23test_svaddva_za32_u32_1u10__SVBool_tS_u12__SVUint32_t( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PN]]) @@ -142,7 +142,7 @@ void test_svaddva_za32_u32_1(svbool_t pn, svbool_t pm, svuint32_t zn) { // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.addva.nxv4i32(i32 0, [[TMP0]], [[TMP1]], [[ZN]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z21test_svaddva_za32_s32u10__SVBool_tu10__SVBool_tu11__SVInt32_t( +// CHECK-CXX-LABEL: define dso_local void @_Z21test_svaddva_za32_s32u10__SVBool_tS_u11__SVInt32_t( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PN]]) @@ -162,7 +162,7 @@ void test_svaddva_za32_s32(svbool_t pn, svbool_t pm, svint32_t zn) { // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.addva.nxv4i32(i32 3, [[TMP0]], [[TMP1]], [[ZN]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z23test_svaddva_za32_s32_1u10__SVBool_tu10__SVBool_tu11__SVInt32_t( +// CHECK-CXX-LABEL: define dso_local void @_Z23test_svaddva_za32_s32_1u10__SVBool_tS_u11__SVInt32_t( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PN]]) diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c index fdccafbebf006..ce866fc7a0905 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c @@ -22,7 +22,7 @@ // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.addha.nxv2i64(i32 0, [[TMP0]], [[TMP1]], [[ZN]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z21test_svaddha_za64_u64u10__SVBool_tu10__SVBool_tu12__SVUint64_t( +// CHECK-CXX-LABEL: define dso_local void @_Z21test_svaddha_za64_u64u10__SVBool_tS_u12__SVUint64_t( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN]]) @@ -42,7 +42,7 @@ void test_svaddha_za64_u64(svbool_t pn, svbool_t pm, svuint64_t zn) { // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.addha.nxv2i64(i32 7, [[TMP0]], [[TMP1]], [[ZN]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z23test_svaddha_za64_u64_1u10__SVBool_tu10__SVBool_tu12__SVUint64_t( +// CHECK-CXX-LABEL: define dso_local void @_Z23test_svaddha_za64_u64_1u10__SVBool_tS_u12__SVUint64_t( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN]]) @@ -62,7 +62,7 @@ void test_svaddha_za64_u64_1(svbool_t pn, svbool_t pm, svuint64_t zn) { // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.addha.nxv2i64(i32 0, [[TMP0]], [[TMP1]], [[ZN]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z21test_svaddha_za64_s64u10__SVBool_tu10__SVBool_tu11__SVInt64_t( +// CHECK-CXX-LABEL: define dso_local void @_Z21test_svaddha_za64_s64u10__SVBool_tS_u11__SVInt64_t( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN]]) @@ -82,7 +82,7 @@ void test_svaddha_za64_s64(svbool_t pn, svbool_t pm, svint64_t zn) { // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.addha.nxv2i64(i32 7, [[TMP0]], [[TMP1]], [[ZN]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z23test_svaddha_za64_s64_1u10__SVBool_tu10__SVBool_tu11__SVInt64_t( +// CHECK-CXX-LABEL: define dso_local void @_Z23test_svaddha_za64_s64_1u10__SVBool_tS_u11__SVInt64_t( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN]]) @@ -102,7 +102,7 @@ void test_svaddha_za64_s64_1(svbool_t pn, svbool_t pm, svint64_t zn) { // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.addva.nxv2i64(i32 0, [[TMP0]], [[TMP1]], [[ZN]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z21test_svaddva_za64_u64u10__SVBool_tu10__SVBool_tu12__SVUint64_t( +// CHECK-CXX-LABEL: define dso_local void @_Z21test_svaddva_za64_u64u10__SVBool_tS_u12__SVUint64_t( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN]]) @@ -122,7 +122,7 @@ void test_svaddva_za64_u64(svbool_t pn, svbool_t pm, svuint64_t zn) { // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.addva.nxv2i64(i32 7, [[TMP0]], [[TMP1]], [[ZN]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z23test_svaddva_za64_u64_1u10__SVBool_tu10__SVBool_tu12__SVUint64_t( +// CHECK-CXX-LABEL: define dso_local void @_Z23test_svaddva_za64_u64_1u10__SVBool_tS_u12__SVUint64_t( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN]]) @@ -142,7 +142,7 @@ void test_svaddva_za64_u64_1(svbool_t pn, svbool_t pm, svuint64_t zn) { // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.addva.nxv2i64(i32 0, [[TMP0]], [[TMP1]], [[ZN]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z21test_svaddva_za64_s64u10__SVBool_tu10__SVBool_tu11__SVInt64_t( +// CHECK-CXX-LABEL: define dso_local void @_Z21test_svaddva_za64_s64u10__SVBool_tS_u11__SVInt64_t( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN]]) @@ -162,7 +162,7 @@ void test_svaddva_za64_s64(svbool_t pn, svbool_t pm, svint64_t zn) { // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.addva.nxv2i64(i32 7, [[TMP0]], [[TMP1]], [[ZN]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z23test_svaddva_za64_s64_1u10__SVBool_tu10__SVBool_tu11__SVInt64_t( +// CHECK-CXX-LABEL: define dso_local void @_Z23test_svaddva_za64_s64_1u10__SVBool_tS_u11__SVInt64_t( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN]]) diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za32.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za32.c index f1382b699f637..02ce353291a82 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za32.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za32.c @@ -20,7 +20,7 @@ // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.smopa.wide.nxv16i8(i32 0, [[PN]], [[PM]], [[ZN]], [[ZM]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z19test_svmopa_za32_s8u10__SVBool_tu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CHECK-CXX-LABEL: define dso_local void @_Z19test_svmopa_za32_s8u10__SVBool_tS_u10__SVInt8_tS0_( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.smopa.wide.nxv16i8(i32 0, [[PN]], [[PM]], [[ZN]], [[ZM]]) @@ -36,7 +36,7 @@ void test_svmopa_za32_s8(svbool_t pn, svbool_t pm, svint8_t zn, svint8_t zm) { // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.umopa.wide.nxv16i8(i32 0, [[PN]], [[PM]], [[ZN]], [[ZM]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z19test_svmopa_za32_u8u10__SVBool_tu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CHECK-CXX-LABEL: define dso_local void @_Z19test_svmopa_za32_u8u10__SVBool_tS_u11__SVUint8_tS0_( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.umopa.wide.nxv16i8(i32 0, [[PN]], [[PM]], [[ZN]], [[ZM]]) @@ -54,7 +54,7 @@ void test_svmopa_za32_u8(svbool_t pn, svbool_t pm, svuint8_t zn, svuint8_t zm) { // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.mopa.wide.nxv8bf16(i32 0, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z21test_svmopa_za32_bf16u10__SVBool_tu10__SVBool_tu14__SVBFloat16_tu14__SVBFloat16_t( +// CHECK-CXX-LABEL: define dso_local void @_Z21test_svmopa_za32_bf16u10__SVBool_tS_u14__SVBfloat16_tS0_( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) @@ -74,7 +74,7 @@ void test_svmopa_za32_bf16(svbool_t pn, svbool_t pm, svbfloat16_t zn, svbfloat16 // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.mopa.wide.nxv8f16(i32 1, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z20test_svmopa_za32_f16u10__SVBool_tu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CHECK-CXX-LABEL: define dso_local void @_Z20test_svmopa_za32_f16u10__SVBool_tS_u13__SVFloat16_tS0_( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) @@ -94,7 +94,7 @@ void test_svmopa_za32_f16(svbool_t pn, svbool_t pm, svfloat16_t zn, svfloat16_t // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.mopa.nxv4f32(i32 1, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z20test_svmopa_za32_f32u10__SVBool_tu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CHECK-CXX-LABEL: define dso_local void @_Z20test_svmopa_za32_f32u10__SVBool_tS_u13__SVFloat32_tS0_( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PN]]) @@ -112,7 +112,7 @@ void test_svmopa_za32_f32(svbool_t pn, svbool_t pm, svfloat32_t zn, svfloat32_t // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.sumopa.wide.nxv16i8(i32 0, [[PN]], [[PM]], [[ZN]], [[ZM]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z21test_svsumopa_za32_s8u10__SVBool_tu10__SVBool_tu10__SVInt8_tu11__SVUint8_t( +// CHECK-CXX-LABEL: define dso_local void @_Z21test_svsumopa_za32_s8u10__SVBool_tS_u10__SVInt8_tu11__SVUint8_t( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.sumopa.wide.nxv16i8(i32 0, [[PN]], [[PM]], [[ZN]], [[ZM]]) @@ -128,7 +128,7 @@ void test_svsumopa_za32_s8(svbool_t pn, svbool_t pm, svint8_t zn, svuint8_t zm) // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.usmopa.wide.nxv16i8(i32 0, [[PN]], [[PM]], [[ZN]], [[ZM]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z21test_svusmopa_za32_u8u10__SVBool_tu10__SVBool_tu11__SVUint8_tu10__SVInt8_t( +// CHECK-CXX-LABEL: define dso_local void @_Z21test_svusmopa_za32_u8u10__SVBool_tS_u11__SVUint8_tu10__SVInt8_t( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.usmopa.wide.nxv16i8(i32 0, [[PN]], [[PM]], [[ZN]], [[ZM]]) diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za64.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za64.c index e60a764e18e9a..1490f4fcbd936 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za64.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za64.c @@ -22,7 +22,7 @@ // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.smopa.wide.nxv8i16(i32 7, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z20test_svmopa_za64_s16u10__SVBool_tu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CHECK-CXX-LABEL: define dso_local void @_Z20test_svmopa_za64_s16u10__SVBool_tS_u11__SVInt16_tS0_( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) @@ -42,7 +42,7 @@ void test_svmopa_za64_s16(svbool_t pn, svbool_t pm, svint16_t zn, svint16_t zm) // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.umopa.wide.nxv8i16(i32 0, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z20test_svmopa_za64_u16u10__SVBool_tu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CHECK-CXX-LABEL: define dso_local void @_Z20test_svmopa_za64_u16u10__SVBool_tS_u12__SVUint16_tS0_( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) @@ -62,7 +62,7 @@ void test_svmopa_za64_u16(svbool_t pn, svbool_t pm, svuint16_t zn, svuint16_t zm // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.mopa.nxv2f64(i32 7, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z20test_svmopa_za64_f64u10__SVBool_tu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CHECK-CXX-LABEL: define dso_local void @_Z20test_svmopa_za64_f64u10__SVBool_tS_u13__SVFloat64_tS0_( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN]]) @@ -82,7 +82,7 @@ void test_svmopa_za64_f64(svbool_t pn, svbool_t pm, svfloat64_t zn, svfloat64_t // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.sumopa.wide.nxv8i16(i32 0, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z22test_svsumopa_za64_s16u10__SVBool_tu10__SVBool_tu11__SVInt16_tu12__SVUint16_t( +// CHECK-CXX-LABEL: define dso_local void @_Z22test_svsumopa_za64_s16u10__SVBool_tS_u11__SVInt16_tu12__SVUint16_t( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) @@ -102,7 +102,7 @@ void test_svsumopa_za64_s16(svbool_t pn, svbool_t pm, svint16_t zn, svuint16_t z // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.usmopa.wide.nxv8i16(i32 7, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z22test_svusmopa_za64_u16u10__SVBool_tu10__SVBool_tu12__SVUint16_tu11__SVInt16_t( +// CHECK-CXX-LABEL: define dso_local void @_Z22test_svusmopa_za64_u16u10__SVBool_tS_u12__SVUint16_tu11__SVInt16_t( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za32.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za32.c index 2524dab52a9c0..0de817fd9924e 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za32.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za32.c @@ -20,7 +20,7 @@ // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.smops.wide.nxv16i8(i32 0, [[PN]], [[PM]], [[ZN]], [[ZM]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z19test_svmops_za32_s8u10__SVBool_tu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CHECK-CXX-LABEL: define dso_local void @_Z19test_svmops_za32_s8u10__SVBool_tS_u10__SVInt8_tS0_( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.smops.wide.nxv16i8(i32 0, [[PN]], [[PM]], [[ZN]], [[ZM]]) @@ -36,7 +36,7 @@ void test_svmops_za32_s8(svbool_t pn, svbool_t pm, svint8_t zn, svint8_t zm) { // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.umops.wide.nxv16i8(i32 0, [[PN]], [[PM]], [[ZN]], [[ZM]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z19test_svmops_za32_u8u10__SVBool_tu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CHECK-CXX-LABEL: define dso_local void @_Z19test_svmops_za32_u8u10__SVBool_tS_u11__SVUint8_tS0_( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.umops.wide.nxv16i8(i32 0, [[PN]], [[PM]], [[ZN]], [[ZM]]) @@ -54,7 +54,7 @@ void test_svmops_za32_u8(svbool_t pn, svbool_t pm, svuint8_t zn, svuint8_t zm) { // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.mops.wide.nxv8bf16(i32 0, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z21test_svmops_za32_bf16u10__SVBool_tu10__SVBool_tu14__SVBFloat16_tu14__SVBFloat16_t( +// CHECK-CXX-LABEL: define dso_local void @_Z21test_svmops_za32_bf16u10__SVBool_tS_u14__SVBfloat16_tS0_( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) @@ -74,7 +74,7 @@ void test_svmops_za32_bf16(svbool_t pn, svbool_t pm, svbfloat16_t zn, svbfloat16 // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.mops.wide.nxv8f16(i32 1, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z20test_svmops_za32_f16u10__SVBool_tu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CHECK-CXX-LABEL: define dso_local void @_Z20test_svmops_za32_f16u10__SVBool_tS_u13__SVFloat16_tS0_( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) @@ -94,7 +94,7 @@ void test_svmops_za32_f16(svbool_t pn, svbool_t pm, svfloat16_t zn, svfloat16_t // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.mops.nxv4f32(i32 1, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z20test_svmops_za32_f32u10__SVBool_tu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CHECK-CXX-LABEL: define dso_local void @_Z20test_svmops_za32_f32u10__SVBool_tS_u13__SVFloat32_tS0_( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PN]]) @@ -112,7 +112,7 @@ void test_svmops_za32_f32(svbool_t pn, svbool_t pm, svfloat32_t zn, svfloat32_t // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.sumops.wide.nxv16i8(i32 0, [[PN]], [[PM]], [[ZN]], [[ZM]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z21test_svsumops_za32_s8u10__SVBool_tu10__SVBool_tu10__SVInt8_tu11__SVUint8_t( +// CHECK-CXX-LABEL: define dso_local void @_Z21test_svsumops_za32_s8u10__SVBool_tS_u10__SVInt8_tu11__SVUint8_t( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.sumops.wide.nxv16i8(i32 0, [[PN]], [[PM]], [[ZN]], [[ZM]]) @@ -128,7 +128,7 @@ void test_svsumops_za32_s8(svbool_t pn, svbool_t pm, svint8_t zn, svuint8_t zm) // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.usmops.wide.nxv16i8(i32 0, [[PN]], [[PM]], [[ZN]], [[ZM]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z21test_svusmops_za32_u8u10__SVBool_tu10__SVBool_tu11__SVUint8_tu10__SVInt8_t( +// CHECK-CXX-LABEL: define dso_local void @_Z21test_svusmops_za32_u8u10__SVBool_tS_u11__SVUint8_tu10__SVInt8_t( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.usmops.wide.nxv16i8(i32 0, [[PN]], [[PM]], [[ZN]], [[ZM]]) diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c index 75ec07ffa3df6..f1866661d9e61 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c @@ -22,7 +22,7 @@ // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.smops.wide.nxv8i16(i32 7, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z20test_svmops_za64_s16u10__SVBool_tu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CHECK-CXX-LABEL: define dso_local void @_Z20test_svmops_za64_s16u10__SVBool_tS_u11__SVInt16_tS0_( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) @@ -42,7 +42,7 @@ void test_svmops_za64_s16(svbool_t pn, svbool_t pm, svint16_t zn, svint16_t zm) // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.umops.wide.nxv8i16(i32 0, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z20test_svmops_za64_u16u10__SVBool_tu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CHECK-CXX-LABEL: define dso_local void @_Z20test_svmops_za64_u16u10__SVBool_tS_u12__SVUint16_tS0_( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) @@ -62,7 +62,7 @@ void test_svmops_za64_u16(svbool_t pn, svbool_t pm, svuint16_t zn, svuint16_t zm // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.mops.nxv2f64(i32 7, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z20test_svmops_za64_f64u10__SVBool_tu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CHECK-CXX-LABEL: define dso_local void @_Z20test_svmops_za64_f64u10__SVBool_tS_u13__SVFloat64_tS0_( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN]]) @@ -82,7 +82,7 @@ void test_svmops_za64_f64(svbool_t pn, svbool_t pm, svfloat64_t zn, svfloat64_t // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.sumops.wide.nxv8i16(i32 0, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z22test_svsumops_za64_s16u10__SVBool_tu10__SVBool_tu11__SVInt16_tu12__SVUint16_t( +// CHECK-CXX-LABEL: define dso_local void @_Z22test_svsumops_za64_s16u10__SVBool_tS_u11__SVInt16_tu12__SVUint16_t( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) @@ -102,7 +102,7 @@ void test_svsumops_za64_s16(svbool_t pn, svbool_t pm, svint16_t zn, svuint16_t z // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.usmops.wide.nxv8i16(i32 7, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z22test_svusmops_za64_u16u10__SVBool_tu10__SVBool_tu12__SVUint16_tu11__SVInt16_t( +// CHECK-CXX-LABEL: define dso_local void @_Z22test_svusmops_za64_u16u10__SVBool_tS_u12__SVUint16_tu11__SVInt16_t( // CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_read.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_read.c index fc5f798d72a18..5c824fef724d5 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_read.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_read.c @@ -364,7 +364,7 @@ svfloat16_t test_svread_hor_za16_f16_1(svfloat16_t zd, svbool_t pg, uint32_t sli // CHECK-C-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sme.read.horiz.nxv8bf16( [[ZD]], [[TMP0]], i32 0, i32 [[SLICE_BASE]]) // CHECK-C-NEXT: ret [[TMP1]] // -// CHECK-CXX-LABEL: define dso_local @_Z25test_svread_hor_za16_bf16u14__SVBFloat16_tu10__SVBool_tj( +// CHECK-CXX-LABEL: define dso_local @_Z25test_svread_hor_za16_bf16u14__SVBfloat16_tu10__SVBool_tj( // CHECK-CXX-SAME: [[ZD:%.*]], [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG]]) @@ -383,7 +383,7 @@ svbfloat16_t test_svread_hor_za16_bf16(svbfloat16_t zd, svbool_t pg, uint32_t sl // CHECK-C-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sme.read.horiz.nxv8bf16( [[ZD]], [[TMP0]], i32 1, i32 [[ADD]]) // CHECK-C-NEXT: ret [[TMP1]] // -// CHECK-CXX-LABEL: define dso_local @_Z27test_svread_hor_za16_bf16_1u14__SVBFloat16_tu10__SVBool_tj( +// CHECK-CXX-LABEL: define dso_local @_Z27test_svread_hor_za16_bf16_1u14__SVBfloat16_tu10__SVBool_tj( // CHECK-CXX-SAME: [[ZD:%.*]], [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[ADD:%.*]] = add i32 [[SLICE_BASE]], 7 @@ -797,7 +797,7 @@ svfloat16_t test_svread_hor_za128_f16_1(svfloat16_t zd, svbool_t pg, uint32_t sl // CHECK-C-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sme.readq.horiz.nxv8bf16( [[ZD]], [[TMP0]], i32 0, i32 [[SLICE_BASE]]) // CHECK-C-NEXT: ret [[TMP1]] // -// CHECK-CXX-LABEL: define dso_local @_Z26test_svread_hor_za128_bf16u14__SVBFloat16_tu10__SVBool_tj( +// CHECK-CXX-LABEL: define dso_local @_Z26test_svread_hor_za128_bf16u14__SVBfloat16_tu10__SVBool_tj( // CHECK-CXX-SAME: [[ZD:%.*]], [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG]]) @@ -815,7 +815,7 @@ svbfloat16_t test_svread_hor_za128_bf16(svbfloat16_t zd, svbool_t pg, uint32_t s // CHECK-C-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sme.readq.horiz.nxv8bf16( [[ZD]], [[TMP0]], i32 15, i32 [[SLICE_BASE]]) // CHECK-C-NEXT: ret [[TMP1]] // -// CHECK-CXX-LABEL: define dso_local @_Z28test_svread_hor_za128_bf16_1u14__SVBFloat16_tu10__SVBool_tj( +// CHECK-CXX-LABEL: define dso_local @_Z28test_svread_hor_za128_bf16_1u14__SVBfloat16_tu10__SVBool_tj( // CHECK-CXX-SAME: [[ZD:%.*]], [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG]]) @@ -1248,7 +1248,7 @@ svfloat16_t test_svread_ver_za16_f16_1(svfloat16_t zd, svbool_t pg, uint32_t sli // CHECK-C-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sme.read.vert.nxv8bf16( [[ZD]], [[TMP0]], i32 0, i32 [[SLICE_BASE]]) // CHECK-C-NEXT: ret [[TMP1]] // -// CHECK-CXX-LABEL: define dso_local @_Z25test_svread_ver_za16_bf16u14__SVBFloat16_tu10__SVBool_tj( +// CHECK-CXX-LABEL: define dso_local @_Z25test_svread_ver_za16_bf16u14__SVBfloat16_tu10__SVBool_tj( // CHECK-CXX-SAME: [[ZD:%.*]], [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG]]) @@ -1267,7 +1267,7 @@ svbfloat16_t test_svread_ver_za16_bf16(svbfloat16_t zd, svbool_t pg, uint32_t sl // CHECK-C-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sme.read.vert.nxv8bf16( [[ZD]], [[TMP0]], i32 1, i32 [[ADD]]) // CHECK-C-NEXT: ret [[TMP1]] // -// CHECK-CXX-LABEL: define dso_local @_Z27test_svread_ver_za16_bf16_1u14__SVBFloat16_tu10__SVBool_tj( +// CHECK-CXX-LABEL: define dso_local @_Z27test_svread_ver_za16_bf16_1u14__SVBfloat16_tu10__SVBool_tj( // CHECK-CXX-SAME: [[ZD:%.*]], [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[ADD:%.*]] = add i32 [[SLICE_BASE]], 7 @@ -1681,7 +1681,7 @@ svfloat16_t test_svread_ver_za128_f16_1(svfloat16_t zd, svbool_t pg, uint32_t sl // CHECK-C-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sme.readq.vert.nxv8bf16( [[ZD]], [[TMP0]], i32 0, i32 [[SLICE_BASE]]) // CHECK-C-NEXT: ret [[TMP1]] // -// CHECK-CXX-LABEL: define dso_local @_Z26test_svread_ver_za128_bf16u14__SVBFloat16_tu10__SVBool_tj( +// CHECK-CXX-LABEL: define dso_local @_Z26test_svread_ver_za128_bf16u14__SVBfloat16_tu10__SVBool_tj( // CHECK-CXX-SAME: [[ZD:%.*]], [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG]]) @@ -1699,7 +1699,7 @@ svbfloat16_t test_svread_ver_za128_bf16(svbfloat16_t zd, svbool_t pg, uint32_t s // CHECK-C-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sme.readq.vert.nxv8bf16( [[ZD]], [[TMP0]], i32 15, i32 [[SLICE_BASE]]) // CHECK-C-NEXT: ret [[TMP1]] // -// CHECK-CXX-LABEL: define dso_local @_Z28test_svread_ver_za128_bf16_1u14__SVBFloat16_tu10__SVBool_tj( +// CHECK-CXX-LABEL: define dso_local @_Z28test_svread_ver_za128_bf16_1u14__SVBfloat16_tu10__SVBool_tj( // CHECK-CXX-SAME: [[ZD:%.*]], [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG]]) diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_write.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_write.c index 0919968e5ae1b..7ff3f2804e32c 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_write.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_write.c @@ -364,7 +364,7 @@ void test_svwrite_hor_za16_f16_1(uint32_t slice_base, svbool_t pg, svfloat16_t z // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.write.horiz.nxv8bf16(i32 0, i32 [[SLICE_BASE]], [[TMP0]], [[ZN]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z26test_svwrite_hor_za16_bf16ju10__SVBool_tu14__SVBFloat16_t( +// CHECK-CXX-LABEL: define dso_local void @_Z26test_svwrite_hor_za16_bf16ju10__SVBool_tu14__SVBfloat16_t( // CHECK-CXX-SAME: i32 noundef [[SLICE_BASE:%.*]], [[PG:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG]]) @@ -383,7 +383,7 @@ void test_svwrite_hor_za16_bf16(uint32_t slice_base, svbool_t pg, svbfloat16_t z // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.write.horiz.nxv8bf16(i32 1, i32 [[ADD]], [[TMP0]], [[ZN]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z28test_svwrite_hor_za16_bf16_1ju10__SVBool_tu14__SVBFloat16_t( +// CHECK-CXX-LABEL: define dso_local void @_Z28test_svwrite_hor_za16_bf16_1ju10__SVBool_tu14__SVBfloat16_t( // CHECK-CXX-SAME: i32 noundef [[SLICE_BASE:%.*]], [[PG:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[ADD:%.*]] = add i32 [[SLICE_BASE]], 7 @@ -797,7 +797,7 @@ void test_svwrite_hor_za128_f16_1(uint32_t slice_base, svbool_t pg, svfloat16_t // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.writeq.horiz.nxv8bf16(i32 0, i32 [[SLICE_BASE]], [[TMP0]], [[ZN]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z27test_svwrite_hor_za128_bf16ju10__SVBool_tu14__SVBFloat16_t( +// CHECK-CXX-LABEL: define dso_local void @_Z27test_svwrite_hor_za128_bf16ju10__SVBool_tu14__SVBfloat16_t( // CHECK-CXX-SAME: i32 noundef [[SLICE_BASE:%.*]], [[PG:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG]]) @@ -815,7 +815,7 @@ void test_svwrite_hor_za128_bf16(uint32_t slice_base, svbool_t pg, svbfloat16_t // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.writeq.horiz.nxv8bf16(i32 15, i32 [[SLICE_BASE]], [[TMP0]], [[ZN]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z29test_svwrite_hor_za128_bf16_1ju10__SVBool_tu14__SVBFloat16_t( +// CHECK-CXX-LABEL: define dso_local void @_Z29test_svwrite_hor_za128_bf16_1ju10__SVBool_tu14__SVBfloat16_t( // CHECK-CXX-SAME: i32 noundef [[SLICE_BASE:%.*]], [[PG:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG]]) @@ -1248,7 +1248,7 @@ void test_svwrite_ver_za16_f16_1(uint32_t slice_base, svbool_t pg, svfloat16_t z // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.write.vert.nxv8bf16(i32 0, i32 [[SLICE_BASE]], [[TMP0]], [[ZN]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z26test_svwrite_ver_za16_bf16ju10__SVBool_tu14__SVBFloat16_t( +// CHECK-CXX-LABEL: define dso_local void @_Z26test_svwrite_ver_za16_bf16ju10__SVBool_tu14__SVBfloat16_t( // CHECK-CXX-SAME: i32 noundef [[SLICE_BASE:%.*]], [[PG:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG]]) @@ -1267,7 +1267,7 @@ void test_svwrite_ver_za16_bf16(uint32_t slice_base, svbool_t pg, svbfloat16_t z // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.write.vert.nxv8bf16(i32 1, i32 [[ADD]], [[TMP0]], [[ZN]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z28test_svwrite_ver_za16_bf16_1ju10__SVBool_tu14__SVBFloat16_t( +// CHECK-CXX-LABEL: define dso_local void @_Z28test_svwrite_ver_za16_bf16_1ju10__SVBool_tu14__SVBfloat16_t( // CHECK-CXX-SAME: i32 noundef [[SLICE_BASE:%.*]], [[PG:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[ADD:%.*]] = add i32 [[SLICE_BASE]], 7 @@ -1681,7 +1681,7 @@ void test_svwrite_ver_za128_f16_1(uint32_t slice_base, svbool_t pg, svfloat16_t // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.writeq.vert.nxv8bf16(i32 0, i32 [[SLICE_BASE]], [[TMP0]], [[ZN]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z27test_svwrite_ver_za128_bf16ju10__SVBool_tu14__SVBFloat16_t( +// CHECK-CXX-LABEL: define dso_local void @_Z27test_svwrite_ver_za128_bf16ju10__SVBool_tu14__SVBfloat16_t( // CHECK-CXX-SAME: i32 noundef [[SLICE_BASE:%.*]], [[PG:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG]]) @@ -1699,7 +1699,7 @@ void test_svwrite_ver_za128_bf16(uint32_t slice_base, svbool_t pg, svbfloat16_t // CHECK-C-NEXT: tail call void @llvm.aarch64.sme.writeq.vert.nxv8bf16(i32 15, i32 [[SLICE_BASE]], [[TMP0]], [[ZN]]) // CHECK-C-NEXT: ret void // -// CHECK-CXX-LABEL: define dso_local void @_Z29test_svwrite_ver_za128_bf16_1ju10__SVBool_tu14__SVBFloat16_t( +// CHECK-CXX-LABEL: define dso_local void @_Z29test_svwrite_ver_za128_bf16_1ju10__SVBool_tu14__SVBfloat16_t( // CHECK-CXX-SAME: i32 noundef [[SLICE_BASE:%.*]], [[PG:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-CXX-NEXT: entry: // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abd.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abd.c index be9fb775842a5..d02f1efa0bcc3 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abd.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abd.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sabd.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svabd_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svabd_s8_zu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sabd.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -38,7 +38,7 @@ svint8_t test_svabd_s8_z(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sabd.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_s16_zu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -57,7 +57,7 @@ svint16_t test_svabd_s16_z(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sabd.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -76,7 +76,7 @@ svint32_t test_svabd_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sabd.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -94,7 +94,7 @@ svint64_t test_svabd_s64_z(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uabd.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svabd_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svabd_u8_zu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uabd.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -112,7 +112,7 @@ svuint8_t test_svabd_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uabd.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_u16_zu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -131,7 +131,7 @@ svuint16_t test_svabd_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uabd.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_u32_zu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -150,7 +150,7 @@ svuint32_t test_svabd_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uabd.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_u64_zu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -167,7 +167,7 @@ svuint64_t test_svabd_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svabd_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svabd_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -183,7 +183,7 @@ svint8_t test_svabd_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sabd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sabd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -200,7 +200,7 @@ svint16_t test_svabd_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sabd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sabd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -217,7 +217,7 @@ svint32_t test_svabd_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sabd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sabd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -233,7 +233,7 @@ svint64_t test_svabd_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svabd_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svabd_u8_mu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -249,7 +249,7 @@ svuint8_t test_svabd_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uabd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_u16_mu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uabd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -266,7 +266,7 @@ svuint16_t test_svabd_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uabd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uabd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -283,7 +283,7 @@ svuint32_t test_svabd_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uabd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uabd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -299,7 +299,7 @@ svuint64_t test_svabd_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabd.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svabd_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svabd_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabd.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -315,7 +315,7 @@ svint8_t test_svabd_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sabd.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sabd.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -332,7 +332,7 @@ svint16_t test_svabd_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sabd.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sabd.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -349,7 +349,7 @@ svint32_t test_svabd_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sabd.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sabd.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -365,7 +365,7 @@ svint64_t test_svabd_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabd.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svabd_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svabd_u8_xu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabd.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -381,7 +381,7 @@ svuint8_t test_svabd_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uabd.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_u16_xu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uabd.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -398,7 +398,7 @@ svuint16_t test_svabd_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uabd.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uabd.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -415,7 +415,7 @@ svuint32_t test_svabd_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uabd.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uabd.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -941,7 +941,7 @@ svuint64_t test_svabd_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fabd.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_f16_zu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -960,7 +960,7 @@ svfloat16_t test_svabd_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fabd.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_f32_zu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -979,7 +979,7 @@ svfloat32_t test_svabd_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fabd.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_f64_zu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -997,7 +997,7 @@ svfloat64_t test_svabd_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fabd.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_f16_mu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fabd.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1014,7 +1014,7 @@ svfloat16_t test_svabd_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fabd.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_f32_mu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fabd.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1031,7 +1031,7 @@ svfloat32_t test_svabd_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fabd.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_f64_mu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fabd.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1048,7 +1048,7 @@ svfloat64_t test_svabd_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fabd.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_f16_xu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fabd.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1065,7 +1065,7 @@ svfloat16_t test_svabd_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fabd.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_f32_xu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fabd.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1082,7 +1082,7 @@ svfloat32_t test_svabd_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fabd.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svabd_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svabd_f64_xu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fabd.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abs.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abs.c index ed82b2e900806..9fd368f51d6a7 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abs.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abs.c @@ -85,7 +85,7 @@ svint64_t test_svabs_s64_z(svbool_t pg, svint64_t op) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.abs.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svabs_s8_mu10__SVInt8_tu10__SVBool_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svabs_s8_mu10__SVInt8_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.abs.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -101,7 +101,7 @@ svint8_t test_svabs_s8_m(svint8_t inactive, svbool_t pg, svint8_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.abs.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svabs_s16_mu11__SVInt16_tu10__SVBool_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svabs_s16_mu11__SVInt16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.abs.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -118,7 +118,7 @@ svint16_t test_svabs_s16_m(svint16_t inactive, svbool_t pg, svint16_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.abs.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svabs_s32_mu11__SVInt32_tu10__SVBool_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svabs_s32_mu11__SVInt32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.abs.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -135,7 +135,7 @@ svint32_t test_svabs_s32_m(svint32_t inactive, svbool_t pg, svint32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.abs.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svabs_s64_mu11__SVInt64_tu10__SVBool_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svabs_s64_mu11__SVInt64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.abs.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -269,7 +269,7 @@ svfloat64_t test_svabs_f64_z(svbool_t pg, svfloat64_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fabs.nxv8f16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svabs_f16_mu13__SVFloat16_tu10__SVBool_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svabs_f16_mu13__SVFloat16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fabs.nxv8f16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -286,7 +286,7 @@ svfloat16_t test_svabs_f16_m(svfloat16_t inactive, svbool_t pg, svfloat16_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fabs.nxv4f32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svabs_f32_mu13__SVFloat32_tu10__SVBool_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svabs_f32_mu13__SVFloat32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fabs.nxv4f32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -303,7 +303,7 @@ svfloat32_t test_svabs_f32_m(svfloat32_t inactive, svbool_t pg, svfloat32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fabs.nxv2f64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svabs_f64_mu13__SVFloat64_tu10__SVBool_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svabs_f64_mu13__SVFloat64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fabs.nxv2f64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acge.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acge.c index 525d3a42ad3eb..46ba89e2cf779 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acge.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acge.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z15test_svacge_f16u10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z15test_svacge_f16u10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.facge.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -40,7 +40,7 @@ svbool_t test_svacge_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z15test_svacge_f32u10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z15test_svacge_f32u10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.facge.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -59,7 +59,7 @@ svbool_t test_svacge_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z15test_svacge_f64u10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z15test_svacge_f64u10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.facge.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acgt.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acgt.c index 90749f7ed1fee..bcdd6439511d7 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acgt.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acgt.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z15test_svacgt_f16u10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z15test_svacgt_f16u10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.facgt.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -40,7 +40,7 @@ svbool_t test_svacgt_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z15test_svacgt_f32u10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z15test_svacgt_f32u10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.facgt.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -59,7 +59,7 @@ svbool_t test_svacgt_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z15test_svacgt_f64u10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z15test_svacgt_f64u10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.facgt.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acle.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acle.c index 50834d5eddc3b..9d4f58875d034 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acle.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acle.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z15test_svacle_f16u10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z15test_svacle_f16u10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.facge.nxv8f16( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -40,7 +40,7 @@ svbool_t test_svacle_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z15test_svacle_f32u10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z15test_svacle_f32u10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.facge.nxv4f32( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -59,7 +59,7 @@ svbool_t test_svacle_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z15test_svacle_f64u10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z15test_svacle_f64u10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.facge.nxv2f64( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_aclt.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_aclt.c index 63f0d24e4d5f5..1e5e7a30dbc9c 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_aclt.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_aclt.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z15test_svaclt_f16u10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z15test_svaclt_f16u10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.facgt.nxv8f16( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -40,7 +40,7 @@ svbool_t test_svaclt_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z15test_svaclt_f32u10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z15test_svaclt_f32u10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.facgt.nxv4f32( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -59,7 +59,7 @@ svbool_t test_svaclt_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z15test_svaclt_f64u10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z15test_svaclt_f64u10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.facgt.nxv2f64( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_add.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_add.c index 19bdc9d0816bf..708fa0c0548e4 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_add.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_add.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svadd_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svadd_s8_zu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -38,7 +38,7 @@ svint8_t test_svadd_s8_z(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.add.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_s16_zu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -57,7 +57,7 @@ svint16_t test_svadd_s16_z(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.add.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -76,7 +76,7 @@ svint32_t test_svadd_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.add.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -94,7 +94,7 @@ svint64_t test_svadd_s64_z(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svadd_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svadd_u8_zu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -112,7 +112,7 @@ svuint8_t test_svadd_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.add.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_u16_zu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -131,7 +131,7 @@ svuint16_t test_svadd_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.add.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_u32_zu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -150,7 +150,7 @@ svuint32_t test_svadd_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.add.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_u64_zu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -167,7 +167,7 @@ svuint64_t test_svadd_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.add.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svadd_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svadd_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.add.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -183,7 +183,7 @@ svint8_t test_svadd_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -200,7 +200,7 @@ svint16_t test_svadd_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -217,7 +217,7 @@ svint32_t test_svadd_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -233,7 +233,7 @@ svint64_t test_svadd_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.add.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svadd_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svadd_u8_mu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.add.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -249,7 +249,7 @@ svuint8_t test_svadd_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_u16_mu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -266,7 +266,7 @@ svuint16_t test_svadd_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -283,7 +283,7 @@ svuint32_t test_svadd_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -299,7 +299,7 @@ svuint64_t test_svadd_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.add.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svadd_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svadd_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.add.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -315,7 +315,7 @@ svint8_t test_svadd_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -332,7 +332,7 @@ svint16_t test_svadd_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -349,7 +349,7 @@ svint32_t test_svadd_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -365,7 +365,7 @@ svint64_t test_svadd_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.add.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svadd_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svadd_u8_xu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.add.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -381,7 +381,7 @@ svuint8_t test_svadd_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_u16_xu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -398,7 +398,7 @@ svuint16_t test_svadd_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -415,7 +415,7 @@ svuint32_t test_svadd_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.add.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -941,7 +941,7 @@ svuint64_t test_svadd_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fadd.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_f16_zu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -960,7 +960,7 @@ svfloat16_t test_svadd_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fadd.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_f32_zu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -979,7 +979,7 @@ svfloat32_t test_svadd_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fadd.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_f64_zu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -997,7 +997,7 @@ svfloat64_t test_svadd_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fadd.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_f16_mu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fadd.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1014,7 +1014,7 @@ svfloat16_t test_svadd_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fadd.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_f32_mu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fadd.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1031,7 +1031,7 @@ svfloat32_t test_svadd_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fadd.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_f64_mu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fadd.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1048,7 +1048,7 @@ svfloat64_t test_svadd_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fadd.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_f16_xu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fadd.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1065,7 +1065,7 @@ svfloat16_t test_svadd_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fadd.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_f32_xu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fadd.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1082,7 +1082,7 @@ svfloat32_t test_svadd_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fadd.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svadd_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svadd_f64_xu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fadd.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrb.c index d78e0e73258ee..75fd603099cd5 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrb.c @@ -49,7 +49,7 @@ svuint64_t test_svadrb_u64base_s64offset(svuint64_t bases, svint64_t offsets) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adrb.nxv4i32( [[BASES:%.*]], [[OFFSETS:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z29test_svadrb_u32base_u32offsetu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z29test_svadrb_u32base_u32offsetu12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adrb.nxv4i32( [[BASES:%.*]], [[OFFSETS:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -64,7 +64,7 @@ svuint32_t test_svadrb_u32base_u32offset(svuint32_t bases, svuint32_t offsets) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adrb.nxv2i64( [[BASES:%.*]], [[OFFSETS:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z29test_svadrb_u64base_u64offsetu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z29test_svadrb_u64base_u64offsetu12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adrb.nxv2i64( [[BASES:%.*]], [[OFFSETS:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrd.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrd.c index 993f2778af703..27d29a559a8ef 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrd.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrd.c @@ -49,7 +49,7 @@ svuint64_t test_svadrd_u64base_s64index(svuint64_t bases, svint64_t indices) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adrd.nxv4i32( [[BASES:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z28test_svadrd_u32base_u32indexu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z28test_svadrd_u32base_u32indexu12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adrd.nxv4i32( [[BASES:%.*]], [[INDICES:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -64,7 +64,7 @@ svuint32_t test_svadrd_u32base_u32index(svuint32_t bases, svuint32_t indices) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adrd.nxv2i64( [[BASES:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z28test_svadrd_u64base_u64indexu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z28test_svadrd_u64base_u64indexu12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adrd.nxv2i64( [[BASES:%.*]], [[INDICES:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrh.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrh.c index d87dd4f20184f..30d28bbbc9965 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrh.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrh.c @@ -49,7 +49,7 @@ svuint64_t test_svadrh_u64base_s64index(svuint64_t bases, svint64_t indices) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adrh.nxv4i32( [[BASES:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z28test_svadrh_u32base_u32indexu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z28test_svadrh_u32base_u32indexu12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adrh.nxv4i32( [[BASES:%.*]], [[INDICES:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -64,7 +64,7 @@ svuint32_t test_svadrh_u32base_u32index(svuint32_t bases, svuint32_t indices) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adrh.nxv2i64( [[BASES:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z28test_svadrh_u64base_u64indexu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z28test_svadrh_u64base_u64indexu12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adrh.nxv2i64( [[BASES:%.*]], [[INDICES:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrw.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrw.c index 8f019c897f43a..fe75ac64781c7 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrw.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrw.c @@ -49,7 +49,7 @@ svuint64_t test_svadrw_u64base_s64index(svuint64_t bases, svint64_t indices) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adrw.nxv4i32( [[BASES:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z28test_svadrw_u32base_u32indexu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z28test_svadrw_u32base_u32indexu12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adrw.nxv4i32( [[BASES:%.*]], [[INDICES:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -64,7 +64,7 @@ svuint32_t test_svadrw_u32base_u32index(svuint32_t bases, svuint32_t indices) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adrw.nxv2i64( [[BASES:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z28test_svadrw_u64base_u64indexu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z28test_svadrw_u64base_u64indexu12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adrw.nxv2i64( [[BASES:%.*]], [[INDICES:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_and.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_and.c index 157e919c3a29b..0ae5018044749 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_and.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_and.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svand_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svand_s8_zu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -38,7 +38,7 @@ svint8_t test_svand_s8_z(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.and.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svand_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svand_s16_zu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -57,7 +57,7 @@ svint16_t test_svand_s16_z(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.and.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svand_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svand_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -76,7 +76,7 @@ svint32_t test_svand_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.and.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svand_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svand_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -94,7 +94,7 @@ svint64_t test_svand_s64_z(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svand_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svand_u8_zu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -112,7 +112,7 @@ svuint8_t test_svand_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.and.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svand_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svand_u16_zu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -131,7 +131,7 @@ svuint16_t test_svand_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.and.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svand_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svand_u32_zu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -150,7 +150,7 @@ svuint32_t test_svand_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.and.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svand_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svand_u64_zu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -167,7 +167,7 @@ svuint64_t test_svand_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svand_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svand_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -183,7 +183,7 @@ svint8_t test_svand_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svand_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svand_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -200,7 +200,7 @@ svint16_t test_svand_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svand_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svand_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -217,7 +217,7 @@ svint32_t test_svand_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svand_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svand_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -233,7 +233,7 @@ svint64_t test_svand_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svand_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svand_u8_mu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -249,7 +249,7 @@ svuint8_t test_svand_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svand_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svand_u16_mu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -266,7 +266,7 @@ svuint16_t test_svand_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svand_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svand_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -283,7 +283,7 @@ svuint32_t test_svand_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svand_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svand_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -299,7 +299,7 @@ svuint64_t test_svand_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svand_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svand_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -315,7 +315,7 @@ svint8_t test_svand_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svand_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svand_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -332,7 +332,7 @@ svint16_t test_svand_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svand_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svand_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -349,7 +349,7 @@ svint32_t test_svand_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svand_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svand_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -365,7 +365,7 @@ svint64_t test_svand_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svand_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svand_u8_xu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -381,7 +381,7 @@ svuint8_t test_svand_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svand_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svand_u16_xu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -398,7 +398,7 @@ svuint16_t test_svand_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svand_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svand_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -415,7 +415,7 @@ svuint32_t test_svand_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svand_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svand_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.and.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -939,7 +939,7 @@ svuint64_t test_svand_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.z.nxv16i1( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svand_b_zu10__SVBool_tu10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z14test_svand_b_zu10__SVBool_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.z.nxv16i1( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfdot.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfdot.c index ff72185e38adf..4e8e16ac88b5c 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfdot.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfdot.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfdot( [[X:%.*]], [[Y:%.*]], [[Z:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_bfdot_f32u13__SVFloat32_tu14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z14test_bfdot_f32u13__SVFloat32_tu14__SVBfloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfdot( [[X:%.*]], [[Y:%.*]], [[Z:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svfloat32_t test_bfdot_f32(svfloat32_t x, svbfloat16_t y, svbfloat16_t z) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfdot.lane.v2( [[X:%.*]], [[Y:%.*]], [[Z:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_bfdot_lane_0_f32u13__SVFloat32_tu14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z21test_bfdot_lane_0_f32u13__SVFloat32_tu14__SVBfloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfdot.lane.v2( [[X:%.*]], [[Y:%.*]], [[Z:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -48,7 +48,7 @@ svfloat32_t test_bfdot_lane_0_f32(svfloat32_t x, svbfloat16_t y, svbfloat16_t z) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfdot.lane.v2( [[X:%.*]], [[Y:%.*]], [[Z:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_bfdot_lane_3_f32u13__SVFloat32_tu14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z21test_bfdot_lane_3_f32u13__SVFloat32_tu14__SVBfloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfdot.lane.v2( [[X:%.*]], [[Y:%.*]], [[Z:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -64,7 +64,7 @@ svfloat32_t test_bfdot_lane_3_f32(svfloat32_t x, svbfloat16_t y, svbfloat16_t z) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfdot( [[X:%.*]], [[Y:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_bfdot_n_f32u13__SVFloat32_tu14__SVBFloat16_tu6__bf16( +// CPP-CHECK-LABEL: @_Z16test_bfdot_n_f32u13__SVFloat32_tu14__SVBfloat16_tu6__bf16( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, bfloat [[Z:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmlalb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmlalb.c index 98195b96c28bd..fe40e9878f1d0 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmlalb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmlalb.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfmlalb( [[X:%.*]], [[Y:%.*]], [[Z:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svbfmlalb_f32u13__SVFloat32_tu14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svbfmlalb_f32u13__SVFloat32_tu14__SVBfloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfmlalb( [[X:%.*]], [[Y:%.*]], [[Z:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svfloat32_t test_svbfmlalb_f32(svfloat32_t x, svbfloat16_t y, svbfloat16_t z) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfmlalb.lane.v2( [[X:%.*]], [[Y:%.*]], [[Z:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_bfmlalb_lane_0_f32u13__SVFloat32_tu14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z23test_bfmlalb_lane_0_f32u13__SVFloat32_tu14__SVBfloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfmlalb.lane.v2( [[X:%.*]], [[Y:%.*]], [[Z:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -48,7 +48,7 @@ svfloat32_t test_bfmlalb_lane_0_f32(svfloat32_t x, svbfloat16_t y, svbfloat16_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfmlalb.lane.v2( [[X:%.*]], [[Y:%.*]], [[Z:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_bfmlalb_lane_7_f32u13__SVFloat32_tu14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z23test_bfmlalb_lane_7_f32u13__SVFloat32_tu14__SVBfloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfmlalb.lane.v2( [[X:%.*]], [[Y:%.*]], [[Z:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -64,7 +64,7 @@ svfloat32_t test_bfmlalb_lane_7_f32(svfloat32_t x, svbfloat16_t y, svbfloat16_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfmlalb( [[X:%.*]], [[Y:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_bfmlalb_n_f32u13__SVFloat32_tu14__SVBFloat16_tu6__bf16( +// CPP-CHECK-LABEL: @_Z18test_bfmlalb_n_f32u13__SVFloat32_tu14__SVBfloat16_tu6__bf16( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, bfloat [[Z:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmlalt.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmlalt.c index 666e35f897293..d1209b713d3a4 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmlalt.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmlalt.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfmlalt( [[X:%.*]], [[Y:%.*]], [[Z:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svbfmlalt_f32u13__SVFloat32_tu14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svbfmlalt_f32u13__SVFloat32_tu14__SVBfloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfmlalt( [[X:%.*]], [[Y:%.*]], [[Z:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svfloat32_t test_svbfmlalt_f32(svfloat32_t x, svbfloat16_t y, svbfloat16_t z) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfmlalt.lane.v2( [[X:%.*]], [[Y:%.*]], [[Z:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_bfmlalt_lane_0_f32u13__SVFloat32_tu14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z23test_bfmlalt_lane_0_f32u13__SVFloat32_tu14__SVBfloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfmlalt.lane.v2( [[X:%.*]], [[Y:%.*]], [[Z:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -48,7 +48,7 @@ svfloat32_t test_bfmlalt_lane_0_f32(svfloat32_t x, svbfloat16_t y, svbfloat16_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfmlalt.lane.v2( [[X:%.*]], [[Y:%.*]], [[Z:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_bfmlalt_lane_7_f32u13__SVFloat32_tu14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z23test_bfmlalt_lane_7_f32u13__SVFloat32_tu14__SVBfloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfmlalt.lane.v2( [[X:%.*]], [[Y:%.*]], [[Z:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -64,7 +64,7 @@ svfloat32_t test_bfmlalt_lane_7_f32(svfloat32_t x, svbfloat16_t y, svbfloat16_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfmlalt( [[X:%.*]], [[Y:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_bfmlalt_n_f32u13__SVFloat32_tu14__SVBFloat16_tu6__bf16( +// CPP-CHECK-LABEL: @_Z18test_bfmlalt_n_f32u13__SVFloat32_tu14__SVBfloat16_tu6__bf16( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, bfloat [[Z:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmmla.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmmla.c index 3d19cfef93f1b..b88674d6668a5 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmmla.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmmla.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfmmla( [[X:%.*]], [[Y:%.*]], [[Z:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_bfmmla_f32u13__SVFloat32_tu14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z15test_bfmmla_f32u13__SVFloat32_tu14__SVBfloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfmmla( [[X:%.*]], [[Y:%.*]], [[Z:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bic.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bic.c index 0043eaf50667c..01e97b4991512 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bic.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bic.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svbic_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svbic_s8_zu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -38,7 +38,7 @@ svint8_t test_svbic_s8_z(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.bic.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svbic_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svbic_s16_zu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -57,7 +57,7 @@ svint16_t test_svbic_s16_z(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.bic.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svbic_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svbic_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -76,7 +76,7 @@ svint32_t test_svbic_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.bic.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svbic_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svbic_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -94,7 +94,7 @@ svint64_t test_svbic_s64_z(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svbic_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svbic_u8_zu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -112,7 +112,7 @@ svuint8_t test_svbic_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.bic.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svbic_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svbic_u16_zu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -131,7 +131,7 @@ svuint16_t test_svbic_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.bic.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svbic_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svbic_u32_zu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -150,7 +150,7 @@ svuint32_t test_svbic_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.bic.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svbic_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svbic_u64_zu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -167,7 +167,7 @@ svuint64_t test_svbic_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbic_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svbic_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -183,7 +183,7 @@ svint8_t test_svbic_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svbic_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svbic_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -200,7 +200,7 @@ svint16_t test_svbic_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svbic_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svbic_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -217,7 +217,7 @@ svint32_t test_svbic_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svbic_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svbic_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -233,7 +233,7 @@ svint64_t test_svbic_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbic_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svbic_u8_mu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -249,7 +249,7 @@ svuint8_t test_svbic_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svbic_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svbic_u16_mu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -266,7 +266,7 @@ svuint16_t test_svbic_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svbic_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svbic_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -283,7 +283,7 @@ svuint32_t test_svbic_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svbic_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svbic_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -299,7 +299,7 @@ svuint64_t test_svbic_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbic_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svbic_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -315,7 +315,7 @@ svint8_t test_svbic_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svbic_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svbic_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -332,7 +332,7 @@ svint16_t test_svbic_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svbic_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svbic_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -349,7 +349,7 @@ svint32_t test_svbic_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svbic_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svbic_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -365,7 +365,7 @@ svint64_t test_svbic_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbic_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svbic_u8_xu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -381,7 +381,7 @@ svuint8_t test_svbic_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svbic_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svbic_u16_xu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -398,7 +398,7 @@ svuint16_t test_svbic_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svbic_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svbic_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -415,7 +415,7 @@ svuint32_t test_svbic_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svbic_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svbic_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.bic.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -939,7 +939,7 @@ svuint64_t test_svbic_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.z.nxv16i1( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svbic_b_zu10__SVBool_tu10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z14test_svbic_b_zu10__SVBool_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bic.z.nxv16i1( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brka.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brka.c index e79d3fefc9533..557d902d00244 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brka.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brka.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.brka.z.nxv16i1( [[PG:%.*]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbrka_b_zu10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svbrka_b_zu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.brka.z.nxv16i1( [[PG:%.*]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svbool_t test_svbrka_b_z(svbool_t pg, svbool_t op) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.brka.nxv16i1( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbrka_b_mu10__SVBool_tu10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svbrka_b_mu10__SVBool_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.brka.nxv16i1( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkb.c index ed70a4931abd6..7d86ef7459ca9 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkb.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.brkb.z.nxv16i1( [[PG:%.*]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbrkb_b_zu10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svbrkb_b_zu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.brkb.z.nxv16i1( [[PG:%.*]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svbool_t test_svbrkb_b_z(svbool_t pg, svbool_t op) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.brkb.nxv16i1( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbrkb_b_mu10__SVBool_tu10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svbrkb_b_mu10__SVBool_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.brkb.nxv16i1( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkn.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkn.c index 852c938fea4a9..eafa2768618f3 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkn.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkn.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.brkn.z.nxv16i1( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbrkn_b_zu10__SVBool_tu10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svbrkn_b_zu10__SVBool_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.brkn.z.nxv16i1( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkpa.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkpa.c index d991d8ca546b3..298ec4203e6c4 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkpa.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkpa.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.brkpa.z.nxv16i1( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svbrkpa_b_zu10__SVBool_tu10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z16test_svbrkpa_b_zu10__SVBool_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.brkpa.z.nxv16i1( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkpb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkpb.c index 39b50873203fb..f2131e26688c5 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkpb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkpb.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.brkpb.z.nxv16i1( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svbrkpb_b_zu10__SVBool_tu10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z16test_svbrkpb_b_zu10__SVBool_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.brkpb.z.nxv16i1( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cadd.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cadd.c index 163c8f750b0d2..83bf636b62265 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cadd.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cadd.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fcadd.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]], i32 90) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svcadd_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svcadd_f16_zu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -40,7 +40,7 @@ svfloat16_t test_svcadd_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fcadd.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]], i32 270) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z19test_svcadd_f16_z_1u10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z19test_svcadd_f16_z_1u10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -59,7 +59,7 @@ svfloat16_t test_svcadd_f16_z_1(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fcadd.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]], i32 90) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svcadd_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svcadd_f32_zu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -78,7 +78,7 @@ svfloat32_t test_svcadd_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fcadd.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]], i32 90) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svcadd_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svcadd_f64_zu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -96,7 +96,7 @@ svfloat64_t test_svcadd_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcadd.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], i32 90) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svcadd_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svcadd_f16_mu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcadd.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], i32 90) @@ -113,7 +113,7 @@ svfloat16_t test_svcadd_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcadd.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], i32 90) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svcadd_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svcadd_f32_mu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcadd.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], i32 90) @@ -130,7 +130,7 @@ svfloat32_t test_svcadd_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcadd.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], i32 90) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svcadd_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svcadd_f64_mu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcadd.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], i32 90) @@ -147,7 +147,7 @@ svfloat64_t test_svcadd_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcadd.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], i32 90) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svcadd_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svcadd_f16_xu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcadd.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], i32 90) @@ -164,7 +164,7 @@ svfloat16_t test_svcadd_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcadd.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], i32 90) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svcadd_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svcadd_f32_xu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcadd.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], i32 90) @@ -181,7 +181,7 @@ svfloat32_t test_svcadd_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcadd.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], i32 90) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svcadd_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svcadd_f64_xu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcadd.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], i32 90) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clasta-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clasta-bfloat.c index 7a67348c6b01d..ad052135cc899 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clasta-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clasta-bfloat.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clasta.nxv8bf16( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svclasta_bf16u10__SVBool_tu14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svclasta_bf16u10__SVBool_tu14__SVBfloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clasta.nxv8bf16( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) @@ -38,7 +38,7 @@ svbfloat16_t test_svclasta_bf16(svbool_t pg, svbfloat16_t fallback, svbfloat16_t // CHECK-NEXT: [[TMP1:%.*]] = tail call bfloat @llvm.aarch64.sve.clasta.n.nxv8bf16( [[TMP0]], bfloat [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret bfloat [[TMP1]] // -// CPP-CHECK-LABEL: @_Z20test_svclasta_n_bf16u10__SVBool_tu6__bf16u14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z20test_svclasta_n_bf16u10__SVBool_tu6__bf16u14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call bfloat @llvm.aarch64.sve.clasta.n.nxv8bf16( [[TMP0]], bfloat [[FALLBACK:%.*]], [[DATA:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clasta.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clasta.c index 8050594971b96..86679e91ce862 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clasta.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clasta.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.clasta.nxv16i8( [[PG:%.*]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svclasta_s8u10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svclasta_s8u10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.clasta.nxv16i8( [[PG:%.*]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svclasta_s8(svbool_t pg, svint8_t fallback, svint8_t data) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clasta.nxv8i16( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svclasta_s16u10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svclasta_s16u10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clasta.nxv8i16( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) @@ -52,7 +52,7 @@ svint16_t test_svclasta_s16(svbool_t pg, svint16_t fallback, svint16_t data) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clasta.nxv4i32( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svclasta_s32u10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svclasta_s32u10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clasta.nxv4i32( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) @@ -69,7 +69,7 @@ svint32_t test_svclasta_s32(svbool_t pg, svint32_t fallback, svint32_t data) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clasta.nxv2i64( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svclasta_s64u10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svclasta_s64u10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clasta.nxv2i64( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) @@ -85,7 +85,7 @@ svint64_t test_svclasta_s64(svbool_t pg, svint64_t fallback, svint64_t data) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.clasta.nxv16i8( [[PG:%.*]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svclasta_u8u10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svclasta_u8u10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.clasta.nxv16i8( [[PG:%.*]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -101,7 +101,7 @@ svuint8_t test_svclasta_u8(svbool_t pg, svuint8_t fallback, svuint8_t data) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clasta.nxv8i16( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svclasta_u16u10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svclasta_u16u10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clasta.nxv8i16( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) @@ -118,7 +118,7 @@ svuint16_t test_svclasta_u16(svbool_t pg, svuint16_t fallback, svuint16_t data) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clasta.nxv4i32( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svclasta_u32u10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svclasta_u32u10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clasta.nxv4i32( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) @@ -135,7 +135,7 @@ svuint32_t test_svclasta_u32(svbool_t pg, svuint32_t fallback, svuint32_t data) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clasta.nxv2i64( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svclasta_u64u10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svclasta_u64u10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clasta.nxv2i64( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) @@ -152,7 +152,7 @@ svuint64_t test_svclasta_u64(svbool_t pg, svuint64_t fallback, svuint64_t data) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clasta.nxv8f16( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svclasta_f16u10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svclasta_f16u10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clasta.nxv8f16( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) @@ -169,7 +169,7 @@ svfloat16_t test_svclasta_f16(svbool_t pg, svfloat16_t fallback, svfloat16_t dat // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clasta.nxv4f32( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svclasta_f32u10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svclasta_f32u10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clasta.nxv4f32( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) @@ -186,7 +186,7 @@ svfloat32_t test_svclasta_f32(svbool_t pg, svfloat32_t fallback, svfloat32_t dat // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clasta.nxv2f64( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svclasta_f64u10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svclasta_f64u10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clasta.nxv2f64( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clastb-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clastb-bfloat.c index 7d22ec911094c..9fa5197dd1416 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clastb-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clastb-bfloat.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clastb.nxv8bf16( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svclastb_bf16u10__SVBool_tu14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svclastb_bf16u10__SVBool_tu14__SVBfloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clastb.nxv8bf16( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) @@ -38,7 +38,7 @@ svbfloat16_t test_svclastb_bf16(svbool_t pg, svbfloat16_t fallback, svbfloat16_t // CHECK-NEXT: [[TMP1:%.*]] = tail call bfloat @llvm.aarch64.sve.clastb.n.nxv8bf16( [[TMP0]], bfloat [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret bfloat [[TMP1]] // -// CPP-CHECK-LABEL: @_Z20test_svclastb_n_bf16u10__SVBool_tu6__bf16u14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z20test_svclastb_n_bf16u10__SVBool_tu6__bf16u14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call bfloat @llvm.aarch64.sve.clastb.n.nxv8bf16( [[TMP0]], bfloat [[FALLBACK:%.*]], [[DATA:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clastb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clastb.c index 3d5683c22af7d..cad080834a64f 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clastb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clastb.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.clastb.nxv16i8( [[PG:%.*]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svclastb_s8u10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svclastb_s8u10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.clastb.nxv16i8( [[PG:%.*]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svclastb_s8(svbool_t pg, svint8_t fallback, svint8_t data) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clastb.nxv8i16( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svclastb_s16u10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svclastb_s16u10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clastb.nxv8i16( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) @@ -52,7 +52,7 @@ svint16_t test_svclastb_s16(svbool_t pg, svint16_t fallback, svint16_t data) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clastb.nxv4i32( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svclastb_s32u10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svclastb_s32u10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clastb.nxv4i32( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) @@ -69,7 +69,7 @@ svint32_t test_svclastb_s32(svbool_t pg, svint32_t fallback, svint32_t data) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clastb.nxv2i64( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svclastb_s64u10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svclastb_s64u10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clastb.nxv2i64( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) @@ -85,7 +85,7 @@ svint64_t test_svclastb_s64(svbool_t pg, svint64_t fallback, svint64_t data) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.clastb.nxv16i8( [[PG:%.*]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svclastb_u8u10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svclastb_u8u10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.clastb.nxv16i8( [[PG:%.*]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -101,7 +101,7 @@ svuint8_t test_svclastb_u8(svbool_t pg, svuint8_t fallback, svuint8_t data) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clastb.nxv8i16( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svclastb_u16u10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svclastb_u16u10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clastb.nxv8i16( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) @@ -118,7 +118,7 @@ svuint16_t test_svclastb_u16(svbool_t pg, svuint16_t fallback, svuint16_t data) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clastb.nxv4i32( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svclastb_u32u10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svclastb_u32u10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clastb.nxv4i32( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) @@ -135,7 +135,7 @@ svuint32_t test_svclastb_u32(svbool_t pg, svuint32_t fallback, svuint32_t data) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clastb.nxv2i64( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svclastb_u64u10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svclastb_u64u10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clastb.nxv2i64( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) @@ -152,7 +152,7 @@ svuint64_t test_svclastb_u64(svbool_t pg, svuint64_t fallback, svuint64_t data) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clastb.nxv8f16( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svclastb_f16u10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svclastb_f16u10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clastb.nxv8f16( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) @@ -169,7 +169,7 @@ svfloat16_t test_svclastb_f16(svbool_t pg, svfloat16_t fallback, svfloat16_t dat // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clastb.nxv4f32( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svclastb_f32u10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svclastb_f32u10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clastb.nxv4f32( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) @@ -186,7 +186,7 @@ svfloat32_t test_svclastb_f32(svbool_t pg, svfloat32_t fallback, svfloat32_t dat // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clastb.nxv2f64( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svclastb_f64u10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svclastb_f64u10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clastb.nxv2f64( [[TMP0]], [[FALLBACK:%.*]], [[DATA:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clz.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clz.c index 1878753a85bf9..e87054766ae62 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clz.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clz.c @@ -217,7 +217,7 @@ svuint64_t test_svclz_s64_m(svuint64_t inactive, svbool_t pg, svint64_t op) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.clz.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svclz_u8_mu11__SVUint8_tu10__SVBool_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svclz_u8_mu11__SVUint8_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.clz.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -233,7 +233,7 @@ svuint8_t test_svclz_u8_m(svuint8_t inactive, svbool_t pg, svuint8_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clz.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svclz_u16_mu12__SVUint16_tu10__SVBool_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svclz_u16_mu12__SVUint16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clz.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -250,7 +250,7 @@ svuint16_t test_svclz_u16_m(svuint16_t inactive, svbool_t pg, svuint16_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clz.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svclz_u32_mu12__SVUint32_tu10__SVBool_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svclz_u32_mu12__SVUint32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clz.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -267,7 +267,7 @@ svuint32_t test_svclz_u32_m(svuint32_t inactive, svbool_t pg, svuint32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clz.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svclz_u64_mu12__SVUint64_tu10__SVBool_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svclz_u64_mu12__SVUint64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.clz.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmla.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmla.c index a183709b0a36f..60d8f93852d0b 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmla.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmla.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fcmla.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_f16_zu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -40,7 +40,7 @@ svfloat16_t test_svcmla_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svf // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fcmla.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z19test_svcmla_f16_z_1u10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z19test_svcmla_f16_z_1u10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -59,7 +59,7 @@ svfloat16_t test_svcmla_f16_z_1(svbool_t pg, svfloat16_t op1, svfloat16_t op2, s // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fcmla.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z19test_svcmla_f16_z_2u10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z19test_svcmla_f16_z_2u10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -78,7 +78,7 @@ svfloat16_t test_svcmla_f16_z_2(svbool_t pg, svfloat16_t op1, svfloat16_t op2, s // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fcmla.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z19test_svcmla_f16_z_3u10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z19test_svcmla_f16_z_3u10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -97,7 +97,7 @@ svfloat16_t test_svcmla_f16_z_3(svbool_t pg, svfloat16_t op1, svfloat16_t op2, s // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fcmla.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_f32_zu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -116,7 +116,7 @@ svfloat32_t test_svcmla_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svf // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fcmla.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_f64_zu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -134,7 +134,7 @@ svfloat64_t test_svcmla_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmla.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_f16_mu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmla.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) @@ -151,7 +151,7 @@ svfloat16_t test_svcmla_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmla.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_f32_mu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmla.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) @@ -168,7 +168,7 @@ svfloat32_t test_svcmla_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmla.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_f64_mu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmla.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) @@ -185,7 +185,7 @@ svfloat64_t test_svcmla_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmla.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_f16_xu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmla.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) @@ -202,7 +202,7 @@ svfloat16_t test_svcmla_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmla.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_f32_xu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmla.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) @@ -219,7 +219,7 @@ svfloat32_t test_svcmla_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmla.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_f64_xu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmla.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) @@ -235,7 +235,7 @@ svfloat64_t test_svcmla_f64_x(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svf // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fcmla.lane.nxv8f16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0, i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z20test_svcmla_lane_f16u13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z20test_svcmla_lane_f16u13__SVFloat16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fcmla.lane.nxv8f16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0, i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -250,7 +250,7 @@ svfloat16_t test_svcmla_lane_f16(svfloat16_t op1, svfloat16_t op2, svfloat16_t o // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fcmla.lane.nxv8f16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3, i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z22test_svcmla_lane_f16_1u13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z22test_svcmla_lane_f16_1u13__SVFloat16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fcmla.lane.nxv8f16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3, i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -265,7 +265,7 @@ svfloat16_t test_svcmla_lane_f16_1(svfloat16_t op1, svfloat16_t op2, svfloat16_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fcmla.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0, i32 180) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z20test_svcmla_lane_f32u13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z20test_svcmla_lane_f32u13__SVFloat32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fcmla.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0, i32 180) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -280,7 +280,7 @@ svfloat32_t test_svcmla_lane_f32(svfloat32_t op1, svfloat32_t op2, svfloat32_t o // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fcmla.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1, i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z22test_svcmla_lane_f32_1u13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z22test_svcmla_lane_f32_1u13__SVFloat32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fcmla.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1, i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpeq.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpeq.c index 8c93be522664f..faa5a7300ba7b 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpeq.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpeq.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmpeq.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcmpeq_s8u10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svcmpeq_s8u10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmpeq.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -36,7 +36,7 @@ svbool_t test_svcmpeq_s8(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpeq_s16u10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpeq_s16u10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmpeq.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -55,7 +55,7 @@ svbool_t test_svcmpeq_s16(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpeq_s32u10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpeq_s32u10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmpeq.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -74,7 +74,7 @@ svbool_t test_svcmpeq_s32(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpeq_s64u10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpeq_s64u10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmpeq.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -91,7 +91,7 @@ svbool_t test_svcmpeq_s64(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmpeq.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcmpeq_u8u10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svcmpeq_u8u10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmpeq.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -108,7 +108,7 @@ svbool_t test_svcmpeq_u8(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpeq_u16u10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpeq_u16u10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmpeq.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -127,7 +127,7 @@ svbool_t test_svcmpeq_u16(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpeq_u32u10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpeq_u32u10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmpeq.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -146,7 +146,7 @@ svbool_t test_svcmpeq_u32(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpeq_u64u10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpeq_u64u10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmpeq.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -394,7 +394,7 @@ svbool_t test_svcmpeq_n_u32(svbool_t pg, svuint32_t op1, uint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpeq_f16u10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpeq_f16u10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmpeq.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -413,7 +413,7 @@ svbool_t test_svcmpeq_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpeq_f32u10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpeq_f32u10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmpeq.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -432,7 +432,7 @@ svbool_t test_svcmpeq_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpeq_f64u10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpeq_f64u10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmpeq.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpge.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpge.c index 699536adb81fc..379d885c5963a 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpge.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpge.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmpge.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcmpge_s8u10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svcmpge_s8u10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmpge.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -36,7 +36,7 @@ svbool_t test_svcmpge_s8(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpge_s16u10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpge_s16u10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmpge.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -55,7 +55,7 @@ svbool_t test_svcmpge_s16(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpge_s32u10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpge_s32u10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmpge.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -74,7 +74,7 @@ svbool_t test_svcmpge_s32(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpge_s64u10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpge_s64u10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmpge.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -91,7 +91,7 @@ svbool_t test_svcmpge_s64(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmphs.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcmpge_u8u10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svcmpge_u8u10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmphs.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -108,7 +108,7 @@ svbool_t test_svcmpge_u8(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpge_u16u10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpge_u16u10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmphs.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -127,7 +127,7 @@ svbool_t test_svcmpge_u16(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpge_u32u10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpge_u32u10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmphs.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -146,7 +146,7 @@ svbool_t test_svcmpge_u32(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpge_u64u10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpge_u64u10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmphs.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -447,7 +447,7 @@ svbool_t test_svcmpge_n_u32(svbool_t pg, svuint32_t op1, uint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpge_f16u10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpge_f16u10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmpge.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -466,7 +466,7 @@ svbool_t test_svcmpge_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpge_f32u10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpge_f32u10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmpge.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -485,7 +485,7 @@ svbool_t test_svcmpge_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpge_f64u10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpge_f64u10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmpge.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpgt.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpgt.c index 08e40d8d93da3..ef170fc56c915 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpgt.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpgt.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmpgt.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcmpgt_s8u10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svcmpgt_s8u10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmpgt.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -36,7 +36,7 @@ svbool_t test_svcmpgt_s8(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpgt_s16u10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpgt_s16u10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmpgt.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -55,7 +55,7 @@ svbool_t test_svcmpgt_s16(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpgt_s32u10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpgt_s32u10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmpgt.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -74,7 +74,7 @@ svbool_t test_svcmpgt_s32(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpgt_s64u10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpgt_s64u10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmpgt.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -91,7 +91,7 @@ svbool_t test_svcmpgt_s64(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmphi.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcmpgt_u8u10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svcmpgt_u8u10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmphi.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -108,7 +108,7 @@ svbool_t test_svcmpgt_u8(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpgt_u16u10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpgt_u16u10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmphi.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -127,7 +127,7 @@ svbool_t test_svcmpgt_u16(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpgt_u32u10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpgt_u32u10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmphi.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -146,7 +146,7 @@ svbool_t test_svcmpgt_u32(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpgt_u64u10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpgt_u64u10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmphi.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -447,7 +447,7 @@ svbool_t test_svcmpgt_n_u32(svbool_t pg, svuint32_t op1, uint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpgt_f16u10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpgt_f16u10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmpgt.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -466,7 +466,7 @@ svbool_t test_svcmpgt_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpgt_f32u10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpgt_f32u10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmpgt.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -485,7 +485,7 @@ svbool_t test_svcmpgt_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpgt_f64u10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpgt_f64u10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmpgt.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmple.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmple.c index 5695c9e008446..9f5ff00464e3b 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmple.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmple.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmpge.nxv16i8( [[PG:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcmple_s8u10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svcmple_s8u10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmpge.nxv16i8( [[PG:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -36,7 +36,7 @@ svbool_t test_svcmple_s8(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmple_s16u10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svcmple_s16u10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmpge.nxv8i16( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -55,7 +55,7 @@ svbool_t test_svcmple_s16(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmple_s32u10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svcmple_s32u10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmpge.nxv4i32( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -74,7 +74,7 @@ svbool_t test_svcmple_s32(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmple_s64u10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svcmple_s64u10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmpge.nxv2i64( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -91,7 +91,7 @@ svbool_t test_svcmple_s64(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmphs.nxv16i8( [[PG:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcmple_u8u10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svcmple_u8u10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmphs.nxv16i8( [[PG:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -108,7 +108,7 @@ svbool_t test_svcmple_u8(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmple_u16u10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svcmple_u16u10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmphs.nxv8i16( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -127,7 +127,7 @@ svbool_t test_svcmple_u16(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmple_u32u10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svcmple_u32u10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmphs.nxv4i32( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -146,7 +146,7 @@ svbool_t test_svcmple_u32(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmple_u64u10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svcmple_u64u10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmphs.nxv2i64( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -447,7 +447,7 @@ svbool_t test_svcmple_n_u32(svbool_t pg, svuint32_t op1, uint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmple_f16u10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svcmple_f16u10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmpge.nxv8f16( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -466,7 +466,7 @@ svbool_t test_svcmple_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmple_f32u10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svcmple_f32u10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmpge.nxv4f32( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -485,7 +485,7 @@ svbool_t test_svcmple_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmple_f64u10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svcmple_f64u10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmpge.nxv2f64( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmplt.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmplt.c index 7fdf200ec24e9..d4eb138c5daf9 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmplt.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmplt.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmpgt.nxv16i8( [[PG:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcmplt_s8u10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svcmplt_s8u10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmpgt.nxv16i8( [[PG:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -36,7 +36,7 @@ svbool_t test_svcmplt_s8(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmplt_s16u10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svcmplt_s16u10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmpgt.nxv8i16( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -55,7 +55,7 @@ svbool_t test_svcmplt_s16(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmplt_s32u10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svcmplt_s32u10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmpgt.nxv4i32( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -74,7 +74,7 @@ svbool_t test_svcmplt_s32(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmplt_s64u10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svcmplt_s64u10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmpgt.nxv2i64( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -91,7 +91,7 @@ svbool_t test_svcmplt_s64(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmphi.nxv16i8( [[PG:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcmplt_u8u10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svcmplt_u8u10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmphi.nxv16i8( [[PG:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -108,7 +108,7 @@ svbool_t test_svcmplt_u8(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmplt_u16u10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svcmplt_u16u10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmphi.nxv8i16( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -127,7 +127,7 @@ svbool_t test_svcmplt_u16(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmplt_u32u10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svcmplt_u32u10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmphi.nxv4i32( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -146,7 +146,7 @@ svbool_t test_svcmplt_u32(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmplt_u64u10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svcmplt_u64u10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmphi.nxv2i64( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -447,7 +447,7 @@ svbool_t test_svcmplt_n_u32(svbool_t pg, svuint32_t op1, uint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmplt_f16u10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svcmplt_f16u10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmpgt.nxv8f16( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -466,7 +466,7 @@ svbool_t test_svcmplt_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmplt_f32u10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svcmplt_f32u10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmpgt.nxv4f32( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -485,7 +485,7 @@ svbool_t test_svcmplt_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmplt_f64u10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svcmplt_f64u10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmpgt.nxv2f64( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpne.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpne.c index d981834815526..ed01232d5eb4c 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpne.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpne.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmpne.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcmpne_s8u10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svcmpne_s8u10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmpne.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -36,7 +36,7 @@ svbool_t test_svcmpne_s8(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpne_s16u10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpne_s16u10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmpne.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -55,7 +55,7 @@ svbool_t test_svcmpne_s16(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpne_s32u10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpne_s32u10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmpne.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -74,7 +74,7 @@ svbool_t test_svcmpne_s32(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpne_s64u10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpne_s64u10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmpne.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -91,7 +91,7 @@ svbool_t test_svcmpne_s64(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmpne.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcmpne_u8u10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svcmpne_u8u10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmpne.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -108,7 +108,7 @@ svbool_t test_svcmpne_u8(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpne_u16u10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpne_u16u10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmpne.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -127,7 +127,7 @@ svbool_t test_svcmpne_u16(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpne_u32u10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpne_u32u10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmpne.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -146,7 +146,7 @@ svbool_t test_svcmpne_u32(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpne_u64u10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpne_u64u10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cmpne.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -394,7 +394,7 @@ svbool_t test_svcmpne_n_u32(svbool_t pg, svuint32_t op1, uint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpne_f16u10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpne_f16u10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmpne.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -413,7 +413,7 @@ svbool_t test_svcmpne_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpne_f32u10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpne_f32u10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmpne.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -432,7 +432,7 @@ svbool_t test_svcmpne_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpne_f64u10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpne_f64u10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmpne.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpuo.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpuo.c index 88ba63368eafd..ca626e01fce46 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpuo.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpuo.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpuo_f16u10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpuo_f16u10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmpuo.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -40,7 +40,7 @@ svbool_t test_svcmpuo_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpuo_f32u10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpuo_f32u10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmpuo.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -59,7 +59,7 @@ svbool_t test_svcmpuo_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svcmpuo_f64u10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svcmpuo_f64u10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcmpuo.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnot.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnot.c index 7e17de8c406bb..c6e10292a2826 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnot.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnot.c @@ -151,7 +151,7 @@ svuint64_t test_svcnot_u64_z(svbool_t pg, svuint64_t op) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cnot.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svcnot_s8_mu10__SVInt8_tu10__SVBool_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svcnot_s8_mu10__SVInt8_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cnot.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -167,7 +167,7 @@ svint8_t test_svcnot_s8_m(svint8_t inactive, svbool_t pg, svint8_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cnot.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svcnot_s16_mu11__SVInt16_tu10__SVBool_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svcnot_s16_mu11__SVInt16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cnot.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -184,7 +184,7 @@ svint16_t test_svcnot_s16_m(svint16_t inactive, svbool_t pg, svint16_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cnot.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svcnot_s32_mu11__SVInt32_tu10__SVBool_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svcnot_s32_mu11__SVInt32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cnot.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -201,7 +201,7 @@ svint32_t test_svcnot_s32_m(svint32_t inactive, svbool_t pg, svint32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cnot.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svcnot_s64_mu11__SVInt64_tu10__SVBool_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svcnot_s64_mu11__SVInt64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cnot.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -217,7 +217,7 @@ svint64_t test_svcnot_s64_m(svint64_t inactive, svbool_t pg, svint64_t op) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cnot.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svcnot_u8_mu11__SVUint8_tu10__SVBool_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svcnot_u8_mu11__SVUint8_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cnot.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -233,7 +233,7 @@ svuint8_t test_svcnot_u8_m(svuint8_t inactive, svbool_t pg, svuint8_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cnot.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svcnot_u16_mu12__SVUint16_tu10__SVBool_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svcnot_u16_mu12__SVUint16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cnot.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -250,7 +250,7 @@ svuint16_t test_svcnot_u16_m(svuint16_t inactive, svbool_t pg, svuint16_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cnot.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svcnot_u32_mu12__SVUint32_tu10__SVBool_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svcnot_u32_mu12__SVUint32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cnot.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -267,7 +267,7 @@ svuint32_t test_svcnot_u32_m(svuint32_t inactive, svbool_t pg, svuint32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cnot.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svcnot_u64_mu12__SVUint64_tu10__SVBool_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svcnot_u64_mu12__SVUint64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cnot.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnt-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnt-bfloat.c index a9055f2acdd78..5d1f27a70073f 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnt-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnt-bfloat.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cnt.nxv8bf16( zeroinitializer, [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svcnt_bf16_zu10__SVBool_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svcnt_bf16_zu10__SVBool_tu14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cnt.nxv8bf16( zeroinitializer, [[TMP0]], [[OP:%.*]]) @@ -38,7 +38,7 @@ svuint16_t test_svcnt_bf16_z(svbool_t pg, svbfloat16_t op) { // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cnt.nxv8bf16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svcnt_bf16_mu12__SVUint16_tu10__SVBool_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svcnt_bf16_mu12__SVUint16_tu10__SVBool_tu14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cnt.nxv8bf16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -54,7 +54,7 @@ svuint16_t test_svcnt_bf16_m(svuint16_t inactive, svbool_t pg, svbfloat16_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cnt.nxv8bf16( undef, [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svcnt_bf16_xu10__SVBool_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svcnt_bf16_xu10__SVBool_tu14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cnt.nxv8bf16( undef, [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnt.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnt.c index 5547a3bc83866..ba5be9b7097ed 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnt.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnt.c @@ -268,7 +268,7 @@ svuint64_t test_svcnt_s64_m(svuint64_t inactive, svbool_t pg, svint64_t op) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cnt.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcnt_u8_mu11__SVUint8_tu10__SVBool_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svcnt_u8_mu11__SVUint8_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cnt.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -284,7 +284,7 @@ svuint8_t test_svcnt_u8_m(svuint8_t inactive, svbool_t pg, svuint8_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cnt.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svcnt_u16_mu12__SVUint16_tu10__SVBool_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svcnt_u16_mu12__SVUint16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cnt.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -301,7 +301,7 @@ svuint16_t test_svcnt_u16_m(svuint16_t inactive, svbool_t pg, svuint16_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cnt.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svcnt_u32_mu12__SVUint32_tu10__SVBool_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svcnt_u32_mu12__SVUint32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cnt.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -318,7 +318,7 @@ svuint32_t test_svcnt_u32_m(svuint32_t inactive, svbool_t pg, svuint32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cnt.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svcnt_u64_mu12__SVUint64_tu10__SVBool_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svcnt_u64_mu12__SVUint64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.cnt.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntp.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntp.c index 087591d12e778..8a3c1ba2cc4e0 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntp.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntp.c @@ -10,7 +10,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.nxv16i1( [[PG:%.*]], [[OP:%.*]]) // CHECK-NEXT: ret i64 [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svcntp_b8u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z14test_svcntp_b8u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.nxv16i1( [[PG:%.*]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret i64 [[TMP0]] @@ -27,7 +27,7 @@ uint64_t test_svcntp_b8(svbool_t pg, svbool_t op) // CHECK-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.nxv8i1( [[TMP0]], [[TMP1]]) // CHECK-NEXT: ret i64 [[TMP2]] // -// CPP-CHECK-LABEL: @_Z15test_svcntp_b16u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svcntp_b16u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[OP:%.*]]) @@ -46,7 +46,7 @@ uint64_t test_svcntp_b16(svbool_t pg, svbool_t op) // CHECK-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.nxv4i1( [[TMP0]], [[TMP1]]) // CHECK-NEXT: ret i64 [[TMP2]] // -// CPP-CHECK-LABEL: @_Z15test_svcntp_b32u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svcntp_b32u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[OP:%.*]]) @@ -65,7 +65,7 @@ uint64_t test_svcntp_b32(svbool_t pg, svbool_t op) // CHECK-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.nxv2i1( [[TMP0]], [[TMP1]]) // CHECK-NEXT: ret i64 [[TMP2]] // -// CPP-CHECK-LABEL: @_Z15test_svcntp_b64u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svcntp_b64u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2-bfloat.c index 2605d574b8304..e063802fbd936 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2-bfloat.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv16bf16.nxv8bf16( [[TMP0]], [[X1:%.*]], i64 8) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svcreate2_bf16u14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z19test_svcreate2_bf16u14__SVBfloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv16bf16.nxv8bf16( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv16bf16.nxv8bf16( [[TMP0]], [[X1:%.*]], i64 8) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2.c index 08e4280064a6b..38ef35b15d454 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv32i8.nxv16i8( [[TMP0]], [[X1:%.*]], i64 16) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svcreate2_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svcreate2_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv32i8.nxv16i8( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv32i8.nxv16i8( [[TMP0]], [[X1:%.*]], i64 16) @@ -38,7 +38,7 @@ svint8x2_t test_svcreate2_s8(svint8_t x0, svint8_t x1) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv16i16.nxv8i16( [[TMP0]], [[X1:%.*]], i64 8) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate2_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate2_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv16i16.nxv8i16( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv16i16.nxv8i16( [[TMP0]], [[X1:%.*]], i64 8) @@ -55,7 +55,7 @@ svint16x2_t test_svcreate2_s16(svint16_t x0, svint16_t x1) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( [[TMP0]], [[X1:%.*]], i64 4) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate2_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate2_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( [[TMP0]], [[X1:%.*]], i64 4) @@ -72,7 +72,7 @@ svint32x2_t test_svcreate2_s32(svint32_t x0, svint32_t x1) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv4i64.nxv2i64( [[TMP0]], [[X1:%.*]], i64 2) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate2_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate2_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv4i64.nxv2i64( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv4i64.nxv2i64( [[TMP0]], [[X1:%.*]], i64 2) @@ -89,7 +89,7 @@ svint64x2_t test_svcreate2_s64(svint64_t x0, svint64_t x1) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv32i8.nxv16i8( [[TMP0]], [[X1:%.*]], i64 16) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svcreate2_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z17test_svcreate2_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv32i8.nxv16i8( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv32i8.nxv16i8( [[TMP0]], [[X1:%.*]], i64 16) @@ -106,7 +106,7 @@ svuint8x2_t test_svcreate2_u8(svuint8_t x0, svuint8_t x1) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv16i16.nxv8i16( [[TMP0]], [[X1:%.*]], i64 8) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate2_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate2_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv16i16.nxv8i16( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv16i16.nxv8i16( [[TMP0]], [[X1:%.*]], i64 8) @@ -123,7 +123,7 @@ svuint16x2_t test_svcreate2_u16(svuint16_t x0, svuint16_t x1) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( [[TMP0]], [[X1:%.*]], i64 4) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate2_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate2_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( [[TMP0]], [[X1:%.*]], i64 4) @@ -140,7 +140,7 @@ svuint32x2_t test_svcreate2_u32(svuint32_t x0, svuint32_t x1) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv4i64.nxv2i64( [[TMP0]], [[X1:%.*]], i64 2) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate2_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate2_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv4i64.nxv2i64( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv4i64.nxv2i64( [[TMP0]], [[X1:%.*]], i64 2) @@ -157,7 +157,7 @@ svuint64x2_t test_svcreate2_u64(svuint64_t x0, svuint64_t x1) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv16f16.nxv8f16( [[TMP0]], [[X1:%.*]], i64 8) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate2_f16u13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate2_f16u13__SVFloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv16f16.nxv8f16( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv16f16.nxv8f16( [[TMP0]], [[X1:%.*]], i64 8) @@ -174,7 +174,7 @@ svfloat16x2_t test_svcreate2_f16(svfloat16_t x0, svfloat16_t x1) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( [[TMP0]], [[X1:%.*]], i64 4) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate2_f32u13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate2_f32u13__SVFloat32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( [[TMP0]], [[X1:%.*]], i64 4) @@ -191,7 +191,7 @@ svfloat32x2_t test_svcreate2_f32(svfloat32_t x0, svfloat32_t x1) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv4f64.nxv2f64( [[TMP0]], [[X1:%.*]], i64 2) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate2_f64u13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate2_f64u13__SVFloat64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv4f64.nxv2f64( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv4f64.nxv2f64( [[TMP0]], [[X1:%.*]], i64 2) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create3-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create3-bfloat.c index 760708cfb7a05..27ac0e20893bf 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create3-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create3-bfloat.c @@ -22,7 +22,7 @@ // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv24bf16.nxv8bf16( [[TMP1]], [[X2:%.*]], i64 16) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z19test_svcreate3_bf16u14__SVBFloat16_tu14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z19test_svcreate3_bf16u14__SVBfloat16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv24bf16.nxv8bf16( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv24bf16.nxv8bf16( [[TMP0]], [[X1:%.*]], i64 8) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create3.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create3.c index 325997ab6f91b..357bced51b142 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create3.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create3.c @@ -22,7 +22,7 @@ // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv48i8.nxv16i8( [[TMP1]], [[X2:%.*]], i64 32) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svcreate3_s8u10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svcreate3_s8u10__SVInt8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv48i8.nxv16i8( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv48i8.nxv16i8( [[TMP0]], [[X1:%.*]], i64 16) @@ -41,7 +41,7 @@ svint8x3_t test_svcreate3_s8(svint8_t x0, svint8_t x1, svint8_t x2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv24i16.nxv8i16( [[TMP1]], [[X2:%.*]], i64 16) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate3_s16u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate3_s16u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv24i16.nxv8i16( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv24i16.nxv8i16( [[TMP0]], [[X1:%.*]], i64 8) @@ -60,7 +60,7 @@ svint16x3_t test_svcreate3_s16(svint16_t x0, svint16_t x1, svint16_t x2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv12i32.nxv4i32( [[TMP1]], [[X2:%.*]], i64 8) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate3_s32u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate3_s32u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv12i32.nxv4i32( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv12i32.nxv4i32( [[TMP0]], [[X1:%.*]], i64 4) @@ -79,7 +79,7 @@ svint32x3_t test_svcreate3_s32(svint32_t x0, svint32_t x1, svint32_t x2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv6i64.nxv2i64( [[TMP1]], [[X2:%.*]], i64 4) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate3_s64u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate3_s64u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv6i64.nxv2i64( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv6i64.nxv2i64( [[TMP0]], [[X1:%.*]], i64 2) @@ -98,7 +98,7 @@ svint64x3_t test_svcreate3_s64(svint64_t x0, svint64_t x1, svint64_t x2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv48i8.nxv16i8( [[TMP1]], [[X2:%.*]], i64 32) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svcreate3_u8u11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z17test_svcreate3_u8u11__SVUint8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv48i8.nxv16i8( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv48i8.nxv16i8( [[TMP0]], [[X1:%.*]], i64 16) @@ -117,7 +117,7 @@ svuint8x3_t test_svcreate3_u8(svuint8_t x0, svuint8_t x1, svuint8_t x2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv24i16.nxv8i16( [[TMP1]], [[X2:%.*]], i64 16) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate3_u16u12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate3_u16u12__SVUint16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv24i16.nxv8i16( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv24i16.nxv8i16( [[TMP0]], [[X1:%.*]], i64 8) @@ -136,7 +136,7 @@ svuint16x3_t test_svcreate3_u16(svuint16_t x0, svuint16_t x1, svuint16_t x2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv12i32.nxv4i32( [[TMP1]], [[X2:%.*]], i64 8) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate3_u32u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate3_u32u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv12i32.nxv4i32( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv12i32.nxv4i32( [[TMP0]], [[X1:%.*]], i64 4) @@ -155,7 +155,7 @@ svuint32x3_t test_svcreate3_u32(svuint32_t x0, svuint32_t x1, svuint32_t x2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv6i64.nxv2i64( [[TMP1]], [[X2:%.*]], i64 4) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate3_u64u12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate3_u64u12__SVUint64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv6i64.nxv2i64( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv6i64.nxv2i64( [[TMP0]], [[X1:%.*]], i64 2) @@ -174,7 +174,7 @@ svuint64x3_t test_svcreate3_u64(svuint64_t x0, svuint64_t x1, svuint64_t x2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv24f16.nxv8f16( [[TMP1]], [[X2:%.*]], i64 16) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate3_f16u13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate3_f16u13__SVFloat16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv24f16.nxv8f16( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv24f16.nxv8f16( [[TMP0]], [[X1:%.*]], i64 8) @@ -193,7 +193,7 @@ svfloat16x3_t test_svcreate3_f16(svfloat16_t x0, svfloat16_t x1, svfloat16_t x2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv12f32.nxv4f32( [[TMP1]], [[X2:%.*]], i64 8) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate3_f32u13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate3_f32u13__SVFloat32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv12f32.nxv4f32( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv12f32.nxv4f32( [[TMP0]], [[X1:%.*]], i64 4) @@ -212,7 +212,7 @@ svfloat32x3_t test_svcreate3_f32(svfloat32_t x0, svfloat32_t x1, svfloat32_t x2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv6f64.nxv2f64( [[TMP1]], [[X2:%.*]], i64 4) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate3_f64u13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate3_f64u13__SVFloat64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv6f64.nxv2f64( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv6f64.nxv2f64( [[TMP0]], [[X1:%.*]], i64 2) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4-bfloat.c index e3af56c5d1339..723771da7cad9 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4-bfloat.c @@ -23,7 +23,7 @@ // CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TMP2]], [[X4:%.*]], i64 24) // CHECK-NEXT: ret [[TMP3]] // -// CPP-CHECK-LABEL: @_Z19test_svcreate4_bf16u14__SVBFloat16_tu14__SVBFloat16_tu14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z19test_svcreate4_bf16u14__SVBfloat16_tS_S_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TMP0]], [[X1:%.*]], i64 8) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4.c index 7e0c2a7f00d1d..fb03f571f70b6 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4.c @@ -23,7 +23,7 @@ // CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.insert.nxv64i8.nxv16i8( [[TMP2]], [[X4:%.*]], i64 48) // CHECK-NEXT: ret [[TMP3]] // -// CPP-CHECK-LABEL: @_Z17test_svcreate4_s8u10__SVInt8_tu10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svcreate4_s8u10__SVInt8_tS_S_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv64i8.nxv16i8( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv64i8.nxv16i8( [[TMP0]], [[X1:%.*]], i64 16) @@ -44,7 +44,7 @@ svint8x4_t test_svcreate4_s8(svint8_t x0, svint8_t x1, svint8_t x2, svint8_t x4) // CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP2]], [[X4:%.*]], i64 24) // CHECK-NEXT: ret [[TMP3]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate4_s16u11__SVInt16_tu11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate4_s16u11__SVInt16_tS_S_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP0]], [[X1:%.*]], i64 8) @@ -65,7 +65,7 @@ svint16x4_t test_svcreate4_s16(svint16_t x0, svint16_t x1, svint16_t x2, svint16 // CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP2]], [[X4:%.*]], i64 12) // CHECK-NEXT: ret [[TMP3]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate4_s32u11__SVInt32_tu11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate4_s32u11__SVInt32_tS_S_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP0]], [[X1:%.*]], i64 4) @@ -86,7 +86,7 @@ svint32x4_t test_svcreate4_s32(svint32_t x0, svint32_t x1, svint32_t x2, svint32 // CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.insert.nxv8i64.nxv2i64( [[TMP2]], [[X4:%.*]], i64 6) // CHECK-NEXT: ret [[TMP3]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate4_s64u11__SVInt64_tu11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate4_s64u11__SVInt64_tS_S_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv8i64.nxv2i64( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv8i64.nxv2i64( [[TMP0]], [[X1:%.*]], i64 2) @@ -107,7 +107,7 @@ svint64x4_t test_svcreate4_s64(svint64_t x0, svint64_t x1, svint64_t x2, svint64 // CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.insert.nxv64i8.nxv16i8( [[TMP2]], [[X4:%.*]], i64 48) // CHECK-NEXT: ret [[TMP3]] // -// CPP-CHECK-LABEL: @_Z17test_svcreate4_u8u11__SVUint8_tu11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z17test_svcreate4_u8u11__SVUint8_tS_S_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv64i8.nxv16i8( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv64i8.nxv16i8( [[TMP0]], [[X1:%.*]], i64 16) @@ -128,7 +128,7 @@ svuint8x4_t test_svcreate4_u8(svuint8_t x0, svuint8_t x1, svuint8_t x2, svuint8_ // CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP2]], [[X4:%.*]], i64 24) // CHECK-NEXT: ret [[TMP3]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate4_u16u12__SVUint16_tu12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate4_u16u12__SVUint16_tS_S_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP0]], [[X1:%.*]], i64 8) @@ -149,7 +149,7 @@ svuint16x4_t test_svcreate4_u16(svuint16_t x0, svuint16_t x1, svuint16_t x2, svu // CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP2]], [[X4:%.*]], i64 12) // CHECK-NEXT: ret [[TMP3]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate4_u32u12__SVUint32_tu12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate4_u32u12__SVUint32_tS_S_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP0]], [[X1:%.*]], i64 4) @@ -170,7 +170,7 @@ svuint32x4_t test_svcreate4_u32(svuint32_t x0, svuint32_t x1, svuint32_t x2, svu // CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.insert.nxv8i64.nxv2i64( [[TMP2]], [[X4:%.*]], i64 6) // CHECK-NEXT: ret [[TMP3]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate4_u64u12__SVUint64_tu12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate4_u64u12__SVUint64_tS_S_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv8i64.nxv2i64( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv8i64.nxv2i64( [[TMP0]], [[X1:%.*]], i64 2) @@ -191,7 +191,7 @@ svuint64x4_t test_svcreate4_u64(svuint64_t x0, svuint64_t x1, svuint64_t x2, svu // CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.insert.nxv32f16.nxv8f16( [[TMP2]], [[X4:%.*]], i64 24) // CHECK-NEXT: ret [[TMP3]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate4_f16u13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate4_f16u13__SVFloat16_tS_S_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv32f16.nxv8f16( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv32f16.nxv8f16( [[TMP0]], [[X1:%.*]], i64 8) @@ -212,7 +212,7 @@ svfloat16x4_t test_svcreate4_f16(svfloat16_t x0, svfloat16_t x1, svfloat16_t x2, // CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP2]], [[X4:%.*]], i64 12) // CHECK-NEXT: ret [[TMP3]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate4_f32u13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate4_f32u13__SVFloat32_tS_S_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP0]], [[X1:%.*]], i64 4) @@ -233,7 +233,7 @@ svfloat32x4_t test_svcreate4_f32(svfloat32_t x0, svfloat32_t x1, svfloat32_t x2, // CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.insert.nxv8f64.nxv2f64( [[TMP2]], [[X4:%.*]], i64 6) // CHECK-NEXT: ret [[TMP3]] // -// CPP-CHECK-LABEL: @_Z18test_svcreate4_f64u13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z18test_svcreate4_f64u13__SVFloat64_tS_S_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv8f64.nxv2f64( poison, [[X0:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.insert.nxv8f64.nxv2f64( [[TMP0]], [[X1:%.*]], i64 2) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvt-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvt-bfloat.c index 495d05cd311b4..bcc508ef25a15 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvt-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvt-bfloat.c @@ -53,7 +53,7 @@ svbfloat16_t test_svcvt_bf16_f32_z(svbool_t pg, svfloat32_t op) { // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcvt.bf16f32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z21test_svcvt_bf16_f32_mu14__SVBFloat16_tu10__SVBool_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z21test_svcvt_bf16_f32_mu14__SVBfloat16_tu10__SVBool_tu13__SVFloat32_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcvt.bf16f32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvtnt.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvtnt.c index d0ca0bd107895..9c0e0cbea20fd 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvtnt.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvtnt.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcvtnt.bf16f32( [[EVEN:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z23test_svcvtnt_bf16_f32_xu14__SVBFloat16_tu10__SVBool_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z23test_svcvtnt_bf16_f32_xu14__SVBfloat16_tu10__SVBool_tu13__SVFloat32_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcvtnt.bf16f32( [[EVEN:%.*]], [[TMP0]], [[OP:%.*]]) @@ -37,7 +37,7 @@ svbfloat16_t test_svcvtnt_bf16_f32_x(svbfloat16_t even, svbool_t pg, svfloat32_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcvtnt.bf16f32( [[EVEN:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z23test_svcvtnt_bf16_f32_mu14__SVBFloat16_tu10__SVBool_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z23test_svcvtnt_bf16_f32_mu14__SVBfloat16_tu10__SVBool_tu13__SVFloat32_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fcvtnt.bf16f32( [[EVEN:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_div.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_div.c index 7774e14c9c69e..544f7737d4750 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_div.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_div.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sdiv.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svdiv_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svdiv_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -40,7 +40,7 @@ svint32_t test_svdiv_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sdiv.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svdiv_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svdiv_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -59,7 +59,7 @@ svint64_t test_svdiv_s64_z(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.udiv.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svdiv_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svdiv_u32_zu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -78,7 +78,7 @@ svuint32_t test_svdiv_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.udiv.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svdiv_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svdiv_u64_zu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -96,7 +96,7 @@ svuint64_t test_svdiv_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sdiv.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svdiv_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svdiv_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sdiv.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -113,7 +113,7 @@ svint32_t test_svdiv_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sdiv.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svdiv_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svdiv_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sdiv.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -130,7 +130,7 @@ svint64_t test_svdiv_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.udiv.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svdiv_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svdiv_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.udiv.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -147,7 +147,7 @@ svuint32_t test_svdiv_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.udiv.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svdiv_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svdiv_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.udiv.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -164,7 +164,7 @@ svuint64_t test_svdiv_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sdiv.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svdiv_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svdiv_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sdiv.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -181,7 +181,7 @@ svint32_t test_svdiv_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sdiv.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svdiv_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svdiv_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sdiv.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -198,7 +198,7 @@ svint64_t test_svdiv_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.udiv.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svdiv_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svdiv_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.udiv.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -215,7 +215,7 @@ svuint32_t test_svdiv_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.udiv.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svdiv_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svdiv_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.udiv.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -493,7 +493,7 @@ svuint64_t test_svdiv_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fdiv.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svdiv_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svdiv_f16_zu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -512,7 +512,7 @@ svfloat16_t test_svdiv_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fdiv.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svdiv_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svdiv_f32_zu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -531,7 +531,7 @@ svfloat32_t test_svdiv_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fdiv.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svdiv_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svdiv_f64_zu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -549,7 +549,7 @@ svfloat64_t test_svdiv_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fdiv.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svdiv_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svdiv_f16_mu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fdiv.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -566,7 +566,7 @@ svfloat16_t test_svdiv_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fdiv.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svdiv_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svdiv_f32_mu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fdiv.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -583,7 +583,7 @@ svfloat32_t test_svdiv_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fdiv.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svdiv_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svdiv_f64_mu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fdiv.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -600,7 +600,7 @@ svfloat64_t test_svdiv_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fdiv.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svdiv_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svdiv_f16_xu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fdiv.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -617,7 +617,7 @@ svfloat16_t test_svdiv_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fdiv.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svdiv_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svdiv_f32_xu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fdiv.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -634,7 +634,7 @@ svfloat32_t test_svdiv_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fdiv.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svdiv_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svdiv_f64_xu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fdiv.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_divr.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_divr.c index 3bcf95fb33f35..eaab3fdcd872e 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_divr.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_divr.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sdivr.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svdivr_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svdivr_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -40,7 +40,7 @@ svint32_t test_svdivr_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sdivr.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svdivr_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svdivr_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -59,7 +59,7 @@ svint64_t test_svdivr_s64_z(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.udivr.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svdivr_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svdivr_u32_zu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -78,7 +78,7 @@ svuint32_t test_svdivr_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.udivr.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svdivr_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svdivr_u64_zu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -96,7 +96,7 @@ svuint64_t test_svdivr_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sdivr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svdivr_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svdivr_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sdivr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -113,7 +113,7 @@ svint32_t test_svdivr_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sdivr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svdivr_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svdivr_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sdivr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -130,7 +130,7 @@ svint64_t test_svdivr_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.udivr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svdivr_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svdivr_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.udivr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -147,7 +147,7 @@ svuint32_t test_svdivr_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.udivr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svdivr_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svdivr_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.udivr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -164,7 +164,7 @@ svuint64_t test_svdivr_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sdiv.u.nxv4i32( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svdivr_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svdivr_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sdiv.u.nxv4i32( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -181,7 +181,7 @@ svint32_t test_svdivr_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sdiv.u.nxv2i64( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svdivr_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svdivr_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sdiv.u.nxv2i64( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -198,7 +198,7 @@ svint64_t test_svdivr_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.udiv.u.nxv4i32( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svdivr_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svdivr_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.udiv.u.nxv4i32( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -215,7 +215,7 @@ svuint32_t test_svdivr_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.udiv.u.nxv2i64( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svdivr_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svdivr_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.udiv.u.nxv2i64( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -493,7 +493,7 @@ svuint64_t test_svdivr_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fdivr.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svdivr_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svdivr_f16_zu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -512,7 +512,7 @@ svfloat16_t test_svdivr_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fdivr.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svdivr_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svdivr_f32_zu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -531,7 +531,7 @@ svfloat32_t test_svdivr_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fdivr.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svdivr_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svdivr_f64_zu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -549,7 +549,7 @@ svfloat64_t test_svdivr_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fdivr.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svdivr_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svdivr_f16_mu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fdivr.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -566,7 +566,7 @@ svfloat16_t test_svdivr_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fdivr.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svdivr_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svdivr_f32_mu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fdivr.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -583,7 +583,7 @@ svfloat32_t test_svdivr_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fdivr.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svdivr_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svdivr_f64_mu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fdivr.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -600,7 +600,7 @@ svfloat64_t test_svdivr_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fdiv.u.nxv8f16( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svdivr_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svdivr_f16_xu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fdiv.u.nxv8f16( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -617,7 +617,7 @@ svfloat16_t test_svdivr_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fdiv.u.nxv4f32( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svdivr_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svdivr_f32_xu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fdiv.u.nxv4f32( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -634,7 +634,7 @@ svfloat32_t test_svdivr_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fdiv.u.nxv2f64( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svdivr_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svdivr_f64_xu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fdiv.u.nxv2f64( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dot.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dot.c index 38ad45eeeae2a..16204f7836d3a 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dot.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dot.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sdot.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svdot_s32u11__SVInt32_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z14test_svdot_s32u11__SVInt32_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sdot.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svint32_t test_svdot_s32(svint32_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sdot.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svdot_s64u11__SVInt64_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z14test_svdot_s64u11__SVInt64_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sdot.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -49,7 +49,7 @@ svint64_t test_svdot_s64(svint64_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.udot.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svdot_u32u12__SVUint32_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svdot_u32u12__SVUint32_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.udot.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -64,7 +64,7 @@ svuint32_t test_svdot_u32(svuint32_t op1, svuint8_t op2, svuint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.udot.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svdot_u64u12__SVUint64_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z14test_svdot_u64u12__SVUint64_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.udot.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -155,7 +155,7 @@ svuint64_t test_svdot_n_u64(svuint64_t op1, svuint16_t op2, uint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sdot.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svdot_lane_s32u11__SVInt32_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z19test_svdot_lane_s32u11__SVInt32_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sdot.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -170,7 +170,7 @@ svint32_t test_svdot_lane_s32(svint32_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sdot.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svdot_lane_s32_1u11__SVInt32_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z21test_svdot_lane_s32_1u11__SVInt32_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sdot.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -185,7 +185,7 @@ svint32_t test_svdot_lane_s32_1(svint32_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sdot.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svdot_lane_s64u11__SVInt64_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z19test_svdot_lane_s64u11__SVInt64_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sdot.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -200,7 +200,7 @@ svint64_t test_svdot_lane_s64(svint64_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sdot.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svdot_lane_s64_1u11__SVInt64_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z21test_svdot_lane_s64_1u11__SVInt64_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sdot.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -215,7 +215,7 @@ svint64_t test_svdot_lane_s64_1(svint64_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.udot.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svdot_lane_u32u12__SVUint32_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z19test_svdot_lane_u32u12__SVUint32_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.udot.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -230,7 +230,7 @@ svuint32_t test_svdot_lane_u32(svuint32_t op1, svuint8_t op2, svuint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.udot.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svdot_lane_u64u12__SVUint64_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z19test_svdot_lane_u64u12__SVUint64_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.udot.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dup-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dup-bfloat.c index 2c361ef442e34..c239c6f9c4311 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dup-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dup-bfloat.c @@ -55,7 +55,7 @@ svbfloat16_t test_svdup_n_bf16_z(svbool_t pg, bfloat16_t op) { // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dup.nxv8bf16( [[INACTIVE:%.*]], [[TMP0]], bfloat [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svdup_n_bf16_mu14__SVBFloat16_tu10__SVBool_tu6__bf16( +// CPP-CHECK-LABEL: @_Z19test_svdup_n_bf16_mu14__SVBfloat16_tu10__SVBool_tu6__bf16( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dup.nxv8bf16( [[INACTIVE:%.*]], [[TMP0]], bfloat [[OP:%.*]]) @@ -90,7 +90,7 @@ svbfloat16_t test_svdup_n_bf16_x(svbool_t pg, bfloat16_t op) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbl.nxv8bf16( [[DATA:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z20test_svdup_lane_bf16u14__SVBFloat16_tt( +// CPP-CHECK-LABEL: @_Z20test_svdup_lane_bf16u14__SVBfloat16_tt( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[INDEX:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq-bfloat.c index 7db98c1bb0502..5d238ffeca94a 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq-bfloat.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv8bf16( [[DATA:%.*]], i64 [[INDEX:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svdupq_lane_bf16u14__SVBFloat16_tm( +// CPP-CHECK-LABEL: @_Z21test_svdupq_lane_bf16u14__SVBfloat16_tm( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv8bf16( [[DATA:%.*]], i64 [[INDEX:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_eor.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_eor.c index cdeeaff0c4076..90ecc17f68750 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_eor.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_eor.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_sveor_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_sveor_s8_zu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -38,7 +38,7 @@ svint8_t test_sveor_s8_z(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.eor.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_sveor_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_sveor_s16_zu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -57,7 +57,7 @@ svint16_t test_sveor_s16_z(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.eor.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_sveor_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_sveor_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -76,7 +76,7 @@ svint32_t test_sveor_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.eor.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_sveor_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_sveor_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -94,7 +94,7 @@ svint64_t test_sveor_s64_z(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_sveor_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_sveor_u8_zu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -112,7 +112,7 @@ svuint8_t test_sveor_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.eor.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_sveor_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_sveor_u16_zu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -131,7 +131,7 @@ svuint16_t test_sveor_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.eor.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_sveor_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_sveor_u32_zu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -150,7 +150,7 @@ svuint32_t test_sveor_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.eor.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_sveor_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_sveor_u64_zu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -167,7 +167,7 @@ svuint64_t test_sveor_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_sveor_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_sveor_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -183,7 +183,7 @@ svint8_t test_sveor_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_sveor_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_sveor_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -200,7 +200,7 @@ svint16_t test_sveor_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_sveor_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_sveor_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -217,7 +217,7 @@ svint32_t test_sveor_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_sveor_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_sveor_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -233,7 +233,7 @@ svint64_t test_sveor_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_sveor_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_sveor_u8_mu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -249,7 +249,7 @@ svuint8_t test_sveor_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_sveor_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_sveor_u16_mu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -266,7 +266,7 @@ svuint16_t test_sveor_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_sveor_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_sveor_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -283,7 +283,7 @@ svuint32_t test_sveor_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_sveor_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_sveor_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -299,7 +299,7 @@ svuint64_t test_sveor_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_sveor_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_sveor_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -315,7 +315,7 @@ svint8_t test_sveor_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_sveor_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_sveor_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -332,7 +332,7 @@ svint16_t test_sveor_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_sveor_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_sveor_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -349,7 +349,7 @@ svint32_t test_sveor_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_sveor_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_sveor_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -365,7 +365,7 @@ svint64_t test_sveor_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_sveor_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_sveor_u8_xu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -381,7 +381,7 @@ svuint8_t test_sveor_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_sveor_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_sveor_u16_xu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -398,7 +398,7 @@ svuint16_t test_sveor_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_sveor_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_sveor_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -415,7 +415,7 @@ svuint32_t test_sveor_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_sveor_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_sveor_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.eor.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -939,7 +939,7 @@ svuint64_t test_sveor_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.z.nxv16i1( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_sveor_b_zu10__SVBool_tu10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z14test_sveor_b_zu10__SVBool_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.z.nxv16i1( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext-bfloat.c index 656598f39c82f..40ffbf9ad3855 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext-bfloat.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]], i32 127) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svext_bf16u14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z15test_svext_bf16u14__SVBfloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]], i32 127) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext.c index ccfed86fbd560..8f813b14b4052 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z13test_svext_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z13test_svext_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svint8_t test_svext_s8(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 255) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svext_s8_1u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svext_s8_1u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 255) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -49,7 +49,7 @@ svint8_t test_svext_s8_1(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svext_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z14test_svext_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -64,7 +64,7 @@ svint16_t test_svext_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 127) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svext_s16_1u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svext_s16_1u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 127) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -79,7 +79,7 @@ svint16_t test_svext_s16_1(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svext_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z14test_svext_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -94,7 +94,7 @@ svint32_t test_svext_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 63) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svext_s32_1u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svext_s32_1u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 63) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -109,7 +109,7 @@ svint32_t test_svext_s32_1(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svext_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z14test_svext_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -124,7 +124,7 @@ svint64_t test_svext_s64(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 31) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svext_s64_1u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svext_s64_1u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 31) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -139,7 +139,7 @@ svint64_t test_svext_s64_1(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 255) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z13test_svext_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z13test_svext_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 255) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -154,7 +154,7 @@ svuint8_t test_svext_u8(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 127) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svext_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z14test_svext_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 127) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -169,7 +169,7 @@ svuint16_t test_svext_u16(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 63) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svext_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z14test_svext_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 63) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -184,7 +184,7 @@ svuint32_t test_svext_u32(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 31) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svext_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z14test_svext_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 31) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -199,7 +199,7 @@ svuint64_t test_svext_u64(svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv8f16( [[OP1:%.*]], [[OP2:%.*]], i32 127) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svext_f16u13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z14test_svext_f16u13__SVFloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv8f16( [[OP1:%.*]], [[OP2:%.*]], i32 127) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -214,7 +214,7 @@ svfloat16_t test_svext_f16(svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], i32 63) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svext_f32u13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z14test_svext_f32u13__SVFloat32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], i32 63) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -229,7 +229,7 @@ svfloat32_t test_svext_f32(svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv2f64( [[OP1:%.*]], [[OP2:%.*]], i32 31) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svext_f64u13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z14test_svext_f64u13__SVFloat64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ext.nxv2f64( [[OP1:%.*]], [[OP2:%.*]], i32 31) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_extb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_extb.c index 7fe8aa5c677ec..b7359ac5aa029 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_extb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_extb.c @@ -122,7 +122,7 @@ svuint64_t test_svextb_u64_z(svbool_t pg, svuint64_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sxtb.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svextb_s16_mu11__SVInt16_tu10__SVBool_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svextb_s16_mu11__SVInt16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sxtb.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -139,7 +139,7 @@ svint16_t test_svextb_s16_m(svint16_t inactive, svbool_t pg, svint16_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sxtb.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svextb_s32_mu11__SVInt32_tu10__SVBool_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svextb_s32_mu11__SVInt32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sxtb.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -156,7 +156,7 @@ svint32_t test_svextb_s32_m(svint32_t inactive, svbool_t pg, svint32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sxtb.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svextb_s64_mu11__SVInt64_tu10__SVBool_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svextb_s64_mu11__SVInt64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sxtb.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -173,7 +173,7 @@ svint64_t test_svextb_s64_m(svint64_t inactive, svbool_t pg, svint64_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uxtb.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svextb_u16_mu12__SVUint16_tu10__SVBool_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svextb_u16_mu12__SVUint16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uxtb.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -190,7 +190,7 @@ svuint16_t test_svextb_u16_m(svuint16_t inactive, svbool_t pg, svuint16_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uxtb.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svextb_u32_mu12__SVUint32_tu10__SVBool_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svextb_u32_mu12__SVUint32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uxtb.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -207,7 +207,7 @@ svuint32_t test_svextb_u32_m(svuint32_t inactive, svbool_t pg, svuint32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uxtb.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svextb_u64_mu12__SVUint64_tu10__SVBool_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svextb_u64_mu12__SVUint64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uxtb.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_exth.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_exth.c index 90c4c7a6b35ce..f2604bdc29890 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_exth.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_exth.c @@ -88,7 +88,7 @@ svuint64_t test_svexth_u64_z(svbool_t pg, svuint64_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sxth.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svexth_s32_mu11__SVInt32_tu10__SVBool_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svexth_s32_mu11__SVInt32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sxth.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -105,7 +105,7 @@ svint32_t test_svexth_s32_m(svint32_t inactive, svbool_t pg, svint32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sxth.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svexth_s64_mu11__SVInt64_tu10__SVBool_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svexth_s64_mu11__SVInt64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sxth.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -122,7 +122,7 @@ svint64_t test_svexth_s64_m(svint64_t inactive, svbool_t pg, svint64_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uxth.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svexth_u32_mu12__SVUint32_tu10__SVBool_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svexth_u32_mu12__SVUint32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uxth.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -139,7 +139,7 @@ svuint32_t test_svexth_u32_m(svuint32_t inactive, svbool_t pg, svuint32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uxth.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svexth_u64_mu12__SVUint64_tu10__SVBool_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svexth_u64_mu12__SVUint64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uxth.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_extw.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_extw.c index 63c8bd937149f..4decf7b9eb2a9 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_extw.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_extw.c @@ -54,7 +54,7 @@ svuint64_t test_svextw_u64_z(svbool_t pg, svuint64_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sxtw.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svextw_s64_mu11__SVInt64_tu10__SVBool_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svextw_s64_mu11__SVInt64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sxtw.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -71,7 +71,7 @@ svint64_t test_svextw_s64_m(svint64_t inactive, svbool_t pg, svint64_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uxtw.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svextw_u64_mu12__SVUint64_tu10__SVBool_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svextw_u64_mu12__SVUint64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uxtw.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_insr-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_insr-bfloat.c index 25c248e830db0..bf8c84fdaece8 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_insr-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_insr-bfloat.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.insr.nxv8bf16( [[OP1:%.*]], bfloat [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svinsr_n_bf16u14__SVBFloat16_tu6__bf16( +// CPP-CHECK-LABEL: @_Z18test_svinsr_n_bf16u14__SVBfloat16_tu6__bf16( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.insr.nxv8bf16( [[OP1:%.*]], bfloat [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lasta-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lasta-bfloat.c index 64f2d522a40dc..ee79462675b67 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lasta-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lasta-bfloat.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call bfloat @llvm.aarch64.sve.lasta.nxv8bf16( [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret bfloat [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svlasta_bf16u10__SVBool_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svlasta_bf16u10__SVBool_tu14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call bfloat @llvm.aarch64.sve.lasta.nxv8bf16( [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lastb-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lastb-bfloat.c index fd5ee8869a0dc..1b885b8762f55 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lastb-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lastb-bfloat.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call bfloat @llvm.aarch64.sve.lastb.nxv8bf16( [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret bfloat [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svlastb_bf16u10__SVBool_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svlastb_bf16u10__SVBool_tu14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call bfloat @llvm.aarch64.sve.lastb.nxv8bf16( [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len-bfloat.c index 24e742698775b..7a5561d7c6fd4 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len-bfloat.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 3 // CHECK-NEXT: ret i64 [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svlen_bf16u14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z15test_svlen_bf16u14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.vscale.i64() // CPP-CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 3 diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lsl.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lsl.c index 53a90bfc2966a..06b302c234880 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lsl.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lsl.c @@ -94,7 +94,7 @@ svint64_t test_svlsl_s64_z(svbool_t pg, svint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsl.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svlsl_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svlsl_u8_zu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsl.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -112,7 +112,7 @@ svuint8_t test_svlsl_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.lsl.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svlsl_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svlsl_u16_zu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -131,7 +131,7 @@ svuint16_t test_svlsl_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.lsl.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svlsl_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svlsl_u32_zu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -150,7 +150,7 @@ svuint32_t test_svlsl_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.lsl.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svlsl_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svlsl_u64_zu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -233,7 +233,7 @@ svint64_t test_svlsl_s64_m(svbool_t pg, svint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.lsl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svlsl_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svlsl_u8_mu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.lsl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -249,7 +249,7 @@ svuint8_t test_svlsl_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svlsl_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svlsl_u16_mu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -266,7 +266,7 @@ svuint16_t test_svlsl_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svlsl_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svlsl_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -283,7 +283,7 @@ svuint32_t test_svlsl_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svlsl_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svlsl_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -365,7 +365,7 @@ svint64_t test_svlsl_s64_x(svbool_t pg, svint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.lsl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svlsl_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svlsl_u8_xu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.lsl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -381,7 +381,7 @@ svuint8_t test_svlsl_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svlsl_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svlsl_u16_xu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -398,7 +398,7 @@ svuint16_t test_svlsl_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svlsl_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svlsl_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -415,7 +415,7 @@ svuint32_t test_svlsl_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svlsl_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svlsl_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lsr.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lsr.c index 25ede10f9676b..470042a0e7f56 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lsr.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lsr.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsr.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svlsr_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svlsr_u8_zu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsr.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -38,7 +38,7 @@ svuint8_t test_svlsr_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.lsr.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svlsr_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svlsr_u16_zu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -57,7 +57,7 @@ svuint16_t test_svlsr_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.lsr.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svlsr_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svlsr_u32_zu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -76,7 +76,7 @@ svuint32_t test_svlsr_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.lsr.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svlsr_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svlsr_u64_zu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -93,7 +93,7 @@ svuint64_t test_svlsr_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.lsr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svlsr_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svlsr_u8_mu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.lsr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -109,7 +109,7 @@ svuint8_t test_svlsr_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svlsr_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svlsr_u16_mu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -126,7 +126,7 @@ svuint16_t test_svlsr_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svlsr_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svlsr_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -143,7 +143,7 @@ svuint32_t test_svlsr_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svlsr_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svlsr_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -159,7 +159,7 @@ svuint64_t test_svlsr_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.lsr.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svlsr_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svlsr_u8_xu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.lsr.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -175,7 +175,7 @@ svuint8_t test_svlsr_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsr.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svlsr_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svlsr_u16_xu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsr.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -192,7 +192,7 @@ svuint16_t test_svlsr_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsr.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svlsr_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svlsr_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsr.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -209,7 +209,7 @@ svuint32_t test_svlsr_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsr.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svlsr_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svlsr_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.lsr.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mad.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mad.c index aed25d63e03c4..0077cca86ee98 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mad.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mad.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mad.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svmad_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svmad_s8_zu10__SVBool_tu10__SVInt8_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mad.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]], [[OP3:%.*]]) @@ -38,7 +38,7 @@ svint8_t test_svmad_s8_z(svbool_t pg, svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mad.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_s16_zu10__SVBool_tu11__SVInt16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -57,7 +57,7 @@ svint16_t test_svmad_s16_z(svbool_t pg, svint16_t op1, svint16_t op2, svint16_t // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mad.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_s32_zu10__SVBool_tu11__SVInt32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -76,7 +76,7 @@ svint32_t test_svmad_s32_z(svbool_t pg, svint32_t op1, svint32_t op2, svint32_t // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mad.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_s64_zu10__SVBool_tu11__SVInt64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -94,7 +94,7 @@ svint64_t test_svmad_s64_z(svbool_t pg, svint64_t op1, svint64_t op2, svint64_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mad.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svmad_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svmad_u8_zu10__SVBool_tu11__SVUint8_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mad.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]], [[OP3:%.*]]) @@ -112,7 +112,7 @@ svuint8_t test_svmad_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2, svuint8_t o // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mad.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_u16_zu10__SVBool_tu12__SVUint16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -131,7 +131,7 @@ svuint16_t test_svmad_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2, svuint1 // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mad.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_u32_zu10__SVBool_tu12__SVUint32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -150,7 +150,7 @@ svuint32_t test_svmad_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2, svuint3 // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mad.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_u64_zu10__SVBool_tu12__SVUint64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -167,7 +167,7 @@ svuint64_t test_svmad_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2, svuint6 // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mad.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmad_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svmad_s8_mu10__SVBool_tu10__SVInt8_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mad.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -183,7 +183,7 @@ svint8_t test_svmad_s8_m(svbool_t pg, svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mad.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_s16_mu10__SVBool_tu11__SVInt16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mad.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -200,7 +200,7 @@ svint16_t test_svmad_s16_m(svbool_t pg, svint16_t op1, svint16_t op2, svint16_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mad.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_s32_mu10__SVBool_tu11__SVInt32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mad.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -217,7 +217,7 @@ svint32_t test_svmad_s32_m(svbool_t pg, svint32_t op1, svint32_t op2, svint32_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mad.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_s64_mu10__SVBool_tu11__SVInt64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mad.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -233,7 +233,7 @@ svint64_t test_svmad_s64_m(svbool_t pg, svint64_t op1, svint64_t op2, svint64_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mad.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmad_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svmad_u8_mu10__SVBool_tu11__SVUint8_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mad.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -249,7 +249,7 @@ svuint8_t test_svmad_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2, svuint8_t o // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mad.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_u16_mu10__SVBool_tu12__SVUint16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mad.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -266,7 +266,7 @@ svuint16_t test_svmad_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2, svuint1 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mad.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_u32_mu10__SVBool_tu12__SVUint32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mad.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -283,7 +283,7 @@ svuint32_t test_svmad_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2, svuint3 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mad.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_u64_mu10__SVBool_tu12__SVUint64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mad.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -299,7 +299,7 @@ svuint64_t test_svmad_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2, svuint6 // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv16i8( [[PG:%.*]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmad_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svmad_s8_xu10__SVBool_tu10__SVInt8_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv16i8( [[PG:%.*]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -315,7 +315,7 @@ svint8_t test_svmad_s8_x(svbool_t pg, svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv8i16( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_s16_xu10__SVBool_tu11__SVInt16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv8i16( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) @@ -332,7 +332,7 @@ svint16_t test_svmad_s16_x(svbool_t pg, svint16_t op1, svint16_t op2, svint16_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv4i32( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_s32_xu10__SVBool_tu11__SVInt32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv4i32( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) @@ -349,7 +349,7 @@ svint32_t test_svmad_s32_x(svbool_t pg, svint32_t op1, svint32_t op2, svint32_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv2i64( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_s64_xu10__SVBool_tu11__SVInt64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv2i64( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) @@ -365,7 +365,7 @@ svint64_t test_svmad_s64_x(svbool_t pg, svint64_t op1, svint64_t op2, svint64_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv16i8( [[PG:%.*]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmad_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svmad_u8_xu10__SVBool_tu11__SVUint8_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv16i8( [[PG:%.*]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -381,7 +381,7 @@ svuint8_t test_svmad_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2, svuint8_t o // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv8i16( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_u16_xu10__SVBool_tu12__SVUint16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv8i16( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) @@ -398,7 +398,7 @@ svuint16_t test_svmad_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2, svuint1 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv4i32( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_u32_xu10__SVBool_tu12__SVUint32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv4i32( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) @@ -415,7 +415,7 @@ svuint32_t test_svmad_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2, svuint3 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv2i64( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_u64_xu10__SVBool_tu12__SVUint64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv2i64( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) @@ -434,7 +434,7 @@ svuint64_t test_svmad_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2, svuint6 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mad.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmad_n_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_ta( +// CPP-CHECK-LABEL: @_Z17test_svmad_n_s8_zu10__SVBool_tu10__SVInt8_tS0_a( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -456,7 +456,7 @@ svint8_t test_svmad_n_s8_z(svbool_t pg, svint8_t op1, svint8_t op2, int8_t op3) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mad.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_ts( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_s16_zu10__SVBool_tu11__SVInt16_tS0_s( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 @@ -479,7 +479,7 @@ svint16_t test_svmad_n_s16_z(svbool_t pg, svint16_t op1, svint16_t op2, int16_t // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mad.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_ti( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_s32_zu10__SVBool_tu11__SVInt32_tS0_i( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 @@ -502,7 +502,7 @@ svint32_t test_svmad_n_s32_z(svbool_t pg, svint32_t op1, svint32_t op2, int32_t // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mad.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_tl( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_s64_zu10__SVBool_tu11__SVInt64_tS0_l( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 @@ -524,7 +524,7 @@ svint64_t test_svmad_n_s64_z(svbool_t pg, svint64_t op1, svint64_t op2, int64_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mad.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmad_n_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_th( +// CPP-CHECK-LABEL: @_Z17test_svmad_n_u8_zu10__SVBool_tu11__SVUint8_tS0_h( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -546,7 +546,7 @@ svuint8_t test_svmad_n_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2, uint8_t o // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mad.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_tt( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_u16_zu10__SVBool_tu12__SVUint16_tS0_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 @@ -569,7 +569,7 @@ svuint16_t test_svmad_n_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2, uint1 // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mad.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_u32_zu10__SVBool_tu12__SVUint32_tS0_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 @@ -592,7 +592,7 @@ svuint32_t test_svmad_n_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2, uint3 // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mad.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_u64_zu10__SVBool_tu12__SVUint64_tS0_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 @@ -613,7 +613,7 @@ svuint64_t test_svmad_n_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2, uint6 // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mad.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svmad_n_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_ta( +// CPP-CHECK-LABEL: @_Z17test_svmad_n_s8_mu10__SVBool_tu10__SVInt8_tS0_a( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -633,7 +633,7 @@ svint8_t test_svmad_n_s8_m(svbool_t pg, svint8_t op1, svint8_t op2, int8_t op3) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mad.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_ts( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_s16_mu10__SVBool_tu11__SVInt16_tS0_s( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 @@ -654,7 +654,7 @@ svint16_t test_svmad_n_s16_m(svbool_t pg, svint16_t op1, svint16_t op2, int16_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mad.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_ti( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_s32_mu10__SVBool_tu11__SVInt32_tS0_i( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 @@ -675,7 +675,7 @@ svint32_t test_svmad_n_s32_m(svbool_t pg, svint32_t op1, svint32_t op2, int32_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mad.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_tl( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_s64_mu10__SVBool_tu11__SVInt64_tS0_l( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 @@ -695,7 +695,7 @@ svint64_t test_svmad_n_s64_m(svbool_t pg, svint64_t op1, svint64_t op2, int64_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mad.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svmad_n_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_th( +// CPP-CHECK-LABEL: @_Z17test_svmad_n_u8_mu10__SVBool_tu11__SVUint8_tS0_h( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -715,7 +715,7 @@ svuint8_t test_svmad_n_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2, uint8_t o // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mad.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_tt( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_u16_mu10__SVBool_tu12__SVUint16_tS0_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 @@ -736,7 +736,7 @@ svuint16_t test_svmad_n_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2, uint1 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mad.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_u32_mu10__SVBool_tu12__SVUint32_tS0_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 @@ -757,7 +757,7 @@ svuint32_t test_svmad_n_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2, uint3 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mad.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_u64_mu10__SVBool_tu12__SVUint64_tS0_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 @@ -777,7 +777,7 @@ svuint64_t test_svmad_n_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2, uint6 // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv16i8( [[PG:%.*]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svmad_n_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_ta( +// CPP-CHECK-LABEL: @_Z17test_svmad_n_s8_xu10__SVBool_tu10__SVInt8_tS0_a( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -797,7 +797,7 @@ svint8_t test_svmad_n_s8_x(svbool_t pg, svint8_t op1, svint8_t op2, int8_t op3) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv8i16( [[TMP0]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_ts( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_s16_xu10__SVBool_tu11__SVInt16_tS0_s( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 @@ -818,7 +818,7 @@ svint16_t test_svmad_n_s16_x(svbool_t pg, svint16_t op1, svint16_t op2, int16_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv4i32( [[TMP0]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_ti( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_s32_xu10__SVBool_tu11__SVInt32_tS0_i( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 @@ -839,7 +839,7 @@ svint32_t test_svmad_n_s32_x(svbool_t pg, svint32_t op1, svint32_t op2, int32_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv2i64( [[TMP0]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_tl( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_s64_xu10__SVBool_tu11__SVInt64_tS0_l( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 @@ -859,7 +859,7 @@ svint64_t test_svmad_n_s64_x(svbool_t pg, svint64_t op1, svint64_t op2, int64_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv16i8( [[PG:%.*]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svmad_n_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_th( +// CPP-CHECK-LABEL: @_Z17test_svmad_n_u8_xu10__SVBool_tu11__SVUint8_tS0_h( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -879,7 +879,7 @@ svuint8_t test_svmad_n_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2, uint8_t o // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv8i16( [[TMP0]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_tt( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_u16_xu10__SVBool_tu12__SVUint16_tS0_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 @@ -900,7 +900,7 @@ svuint16_t test_svmad_n_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2, uint1 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv4i32( [[TMP0]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_u32_xu10__SVBool_tu12__SVUint32_tS0_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 @@ -921,7 +921,7 @@ svuint32_t test_svmad_n_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2, uint3 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv2i64( [[TMP0]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_u64_xu10__SVBool_tu12__SVUint64_tS0_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 @@ -941,7 +941,7 @@ svuint64_t test_svmad_n_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2, uint6 // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmad.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_f16_zu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -960,7 +960,7 @@ svfloat16_t test_svmad_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfl // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmad.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_f32_zu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -979,7 +979,7 @@ svfloat32_t test_svmad_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfl // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmad.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_f64_zu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -997,7 +997,7 @@ svfloat64_t test_svmad_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmad.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_f16_mu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmad.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -1014,7 +1014,7 @@ svfloat16_t test_svmad_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmad.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_f32_mu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmad.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -1031,7 +1031,7 @@ svfloat32_t test_svmad_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmad.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_f64_mu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmad.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -1048,7 +1048,7 @@ svfloat64_t test_svmad_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.u.nxv8f16( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_f16_xu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.u.nxv8f16( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) @@ -1065,7 +1065,7 @@ svfloat16_t test_svmad_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.u.nxv4f32( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_f32_xu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.u.nxv4f32( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) @@ -1082,7 +1082,7 @@ svfloat32_t test_svmad_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.u.nxv2f64( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmad_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svmad_f64_xu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.u.nxv2f64( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) @@ -1102,7 +1102,7 @@ svfloat64_t test_svmad_f64_x(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfl // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmad.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tDh( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_f16_zu10__SVBool_tu13__SVFloat16_tS0_Dh( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, half [[OP3:%.*]], i64 0 @@ -1125,7 +1125,7 @@ svfloat16_t test_svmad_n_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, fl // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmad.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tf( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_f32_zu10__SVBool_tu13__SVFloat32_tS0_f( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, float [[OP3:%.*]], i64 0 @@ -1148,7 +1148,7 @@ svfloat32_t test_svmad_n_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, fl // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmad.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_td( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_f64_zu10__SVBool_tu13__SVFloat64_tS0_d( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, double [[OP3:%.*]], i64 0 @@ -1170,7 +1170,7 @@ svfloat64_t test_svmad_n_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, fl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmad.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tDh( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_f16_mu10__SVBool_tu13__SVFloat16_tS0_Dh( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, half [[OP3:%.*]], i64 0 @@ -1191,7 +1191,7 @@ svfloat16_t test_svmad_n_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, fl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmad.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tf( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_f32_mu10__SVBool_tu13__SVFloat32_tS0_f( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, float [[OP3:%.*]], i64 0 @@ -1212,7 +1212,7 @@ svfloat32_t test_svmad_n_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, fl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmad.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_td( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_f64_mu10__SVBool_tu13__SVFloat64_tS0_d( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, double [[OP3:%.*]], i64 0 @@ -1233,7 +1233,7 @@ svfloat64_t test_svmad_n_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, fl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.u.nxv8f16( [[TMP0]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tDh( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_f16_xu10__SVBool_tu13__SVFloat16_tS0_Dh( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, half [[OP3:%.*]], i64 0 @@ -1254,7 +1254,7 @@ svfloat16_t test_svmad_n_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, fl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.u.nxv4f32( [[TMP0]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tf( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_f32_xu10__SVBool_tu13__SVFloat32_tS0_f( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, float [[OP3:%.*]], i64 0 @@ -1275,7 +1275,7 @@ svfloat32_t test_svmad_n_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, fl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.u.nxv2f64( [[TMP0]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmad_n_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_td( +// CPP-CHECK-LABEL: @_Z18test_svmad_n_f64_xu10__SVBool_tu13__SVFloat64_tS0_d( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, double [[OP3:%.*]], i64 0 diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_matmul_fp32.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_matmul_fp32.c index 11900c3c68063..9ed96f0ca3683 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_matmul_fp32.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_matmul_fp32.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmmla.nxv4f32( [[X:%.*]], [[Y:%.*]], [[Z:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmmla_f32u13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z15test_svmmla_f32u13__SVFloat32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmmla.nxv4f32( [[X:%.*]], [[Y:%.*]], [[Z:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_matmul_fp64.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_matmul_fp64.c index 6f3fdfbaa8b04..235262177296c 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_matmul_fp64.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_matmul_fp64.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmmla.nxv2f64( [[X:%.*]], [[Y:%.*]], [[Z:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmmla_f64u13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z15test_svmmla_f64u13__SVFloat64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmmla.nxv2f64( [[X:%.*]], [[Y:%.*]], [[Z:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_max.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_max.c index 78a331bd04f05..eacb3f6d42052 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_max.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_max.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smax.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svmax_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svmax_s8_zu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smax.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -38,7 +38,7 @@ svint8_t test_svmax_s8_z(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.smax.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_s16_zu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -57,7 +57,7 @@ svint16_t test_svmax_s16_z(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.smax.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -76,7 +76,7 @@ svint32_t test_svmax_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.smax.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -94,7 +94,7 @@ svint64_t test_svmax_s64_z(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umax.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svmax_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svmax_u8_zu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umax.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -112,7 +112,7 @@ svuint8_t test_svmax_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.umax.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_u16_zu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -131,7 +131,7 @@ svuint16_t test_svmax_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.umax.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_u32_zu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -150,7 +150,7 @@ svuint32_t test_svmax_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.umax.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_u64_zu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -167,7 +167,7 @@ svuint64_t test_svmax_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smax.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmax_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svmax_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smax.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -183,7 +183,7 @@ svint8_t test_svmax_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smax.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smax.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -200,7 +200,7 @@ svint16_t test_svmax_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smax.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smax.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -217,7 +217,7 @@ svint32_t test_svmax_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smax.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smax.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -233,7 +233,7 @@ svint64_t test_svmax_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umax.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmax_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svmax_u8_mu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umax.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -249,7 +249,7 @@ svuint8_t test_svmax_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umax.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_u16_mu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umax.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -266,7 +266,7 @@ svuint16_t test_svmax_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umax.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umax.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -283,7 +283,7 @@ svuint32_t test_svmax_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umax.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umax.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -299,7 +299,7 @@ svuint64_t test_svmax_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smax.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmax_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svmax_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smax.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -315,7 +315,7 @@ svint8_t test_svmax_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smax.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smax.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -332,7 +332,7 @@ svint16_t test_svmax_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smax.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smax.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -349,7 +349,7 @@ svint32_t test_svmax_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smax.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smax.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -365,7 +365,7 @@ svint64_t test_svmax_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umax.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmax_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svmax_u8_xu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umax.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -381,7 +381,7 @@ svuint8_t test_svmax_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umax.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_u16_xu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umax.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -398,7 +398,7 @@ svuint16_t test_svmax_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umax.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umax.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -415,7 +415,7 @@ svuint32_t test_svmax_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umax.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umax.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -941,7 +941,7 @@ svuint64_t test_svmax_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmax.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_f16_zu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -960,7 +960,7 @@ svfloat16_t test_svmax_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmax.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_f32_zu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -979,7 +979,7 @@ svfloat32_t test_svmax_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmax.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_f64_zu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -997,7 +997,7 @@ svfloat64_t test_svmax_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmax.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_f16_mu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmax.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1014,7 +1014,7 @@ svfloat16_t test_svmax_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmax.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_f32_mu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmax.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1031,7 +1031,7 @@ svfloat32_t test_svmax_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmax.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_f64_mu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmax.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1048,7 +1048,7 @@ svfloat64_t test_svmax_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmax.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_f16_xu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmax.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1065,7 +1065,7 @@ svfloat16_t test_svmax_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmax.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_f32_xu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmax.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1082,7 +1082,7 @@ svfloat32_t test_svmax_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmax.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmax_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svmax_f64_xu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmax.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_maxnm.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_maxnm.c index 1bd68b08da176..6cdce39e49ac5 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_maxnm.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_maxnm.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmaxnm.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmaxnm_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svmaxnm_f16_zu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -40,7 +40,7 @@ svfloat16_t test_svmaxnm_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmaxnm.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmaxnm_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z18test_svmaxnm_f32_zu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -59,7 +59,7 @@ svfloat32_t test_svmaxnm_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmaxnm.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmaxnm_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z18test_svmaxnm_f64_zu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -77,7 +77,7 @@ svfloat64_t test_svmaxnm_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxnm.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmaxnm_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svmaxnm_f16_mu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxnm.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -94,7 +94,7 @@ svfloat16_t test_svmaxnm_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxnm.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmaxnm_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z18test_svmaxnm_f32_mu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxnm.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -111,7 +111,7 @@ svfloat32_t test_svmaxnm_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxnm.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmaxnm_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z18test_svmaxnm_f64_mu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxnm.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -128,7 +128,7 @@ svfloat64_t test_svmaxnm_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxnm.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmaxnm_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svmaxnm_f16_xu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxnm.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -145,7 +145,7 @@ svfloat16_t test_svmaxnm_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxnm.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmaxnm_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z18test_svmaxnm_f32_xu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxnm.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -162,7 +162,7 @@ svfloat32_t test_svmaxnm_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxnm.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmaxnm_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z18test_svmaxnm_f64_xu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxnm.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_min.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_min.c index b2db3b284ec5e..502f74b7e35ea 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_min.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_min.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smin.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svmin_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svmin_s8_zu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smin.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -38,7 +38,7 @@ svint8_t test_svmin_s8_z(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.smin.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_s16_zu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -57,7 +57,7 @@ svint16_t test_svmin_s16_z(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.smin.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -76,7 +76,7 @@ svint32_t test_svmin_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.smin.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -94,7 +94,7 @@ svint64_t test_svmin_s64_z(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umin.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svmin_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svmin_u8_zu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umin.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -112,7 +112,7 @@ svuint8_t test_svmin_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.umin.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_u16_zu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -131,7 +131,7 @@ svuint16_t test_svmin_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.umin.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_u32_zu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -150,7 +150,7 @@ svuint32_t test_svmin_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.umin.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_u64_zu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -167,7 +167,7 @@ svuint64_t test_svmin_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smin.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmin_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svmin_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smin.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -183,7 +183,7 @@ svint8_t test_svmin_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smin.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smin.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -200,7 +200,7 @@ svint16_t test_svmin_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smin.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smin.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -217,7 +217,7 @@ svint32_t test_svmin_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smin.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smin.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -233,7 +233,7 @@ svint64_t test_svmin_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umin.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmin_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svmin_u8_mu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umin.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -249,7 +249,7 @@ svuint8_t test_svmin_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umin.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_u16_mu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umin.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -266,7 +266,7 @@ svuint16_t test_svmin_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umin.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umin.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -283,7 +283,7 @@ svuint32_t test_svmin_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umin.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umin.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -299,7 +299,7 @@ svuint64_t test_svmin_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smin.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmin_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svmin_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smin.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -315,7 +315,7 @@ svint8_t test_svmin_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smin.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smin.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -332,7 +332,7 @@ svint16_t test_svmin_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smin.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smin.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -349,7 +349,7 @@ svint32_t test_svmin_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smin.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smin.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -365,7 +365,7 @@ svint64_t test_svmin_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umin.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmin_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svmin_u8_xu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umin.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -381,7 +381,7 @@ svuint8_t test_svmin_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umin.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_u16_xu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umin.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -398,7 +398,7 @@ svuint16_t test_svmin_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umin.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umin.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -415,7 +415,7 @@ svuint32_t test_svmin_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umin.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umin.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -941,7 +941,7 @@ svuint64_t test_svmin_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmin.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_f16_zu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -960,7 +960,7 @@ svfloat16_t test_svmin_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmin.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_f32_zu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -979,7 +979,7 @@ svfloat32_t test_svmin_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmin.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_f64_zu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -997,7 +997,7 @@ svfloat64_t test_svmin_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmin.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_f16_mu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmin.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1014,7 +1014,7 @@ svfloat16_t test_svmin_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmin.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_f32_mu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmin.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1031,7 +1031,7 @@ svfloat32_t test_svmin_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmin.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_f64_mu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmin.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1048,7 +1048,7 @@ svfloat64_t test_svmin_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmin.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_f16_xu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmin.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1065,7 +1065,7 @@ svfloat16_t test_svmin_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmin.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_f32_xu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmin.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1082,7 +1082,7 @@ svfloat32_t test_svmin_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmin.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmin_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svmin_f64_xu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmin.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_minnm.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_minnm.c index 44717484859a2..0c6791c6ae197 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_minnm.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_minnm.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fminnm.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svminnm_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svminnm_f16_zu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -40,7 +40,7 @@ svfloat16_t test_svminnm_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fminnm.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svminnm_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z18test_svminnm_f32_zu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -59,7 +59,7 @@ svfloat32_t test_svminnm_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fminnm.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svminnm_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z18test_svminnm_f64_zu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -77,7 +77,7 @@ svfloat64_t test_svminnm_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminnm.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svminnm_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svminnm_f16_mu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminnm.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -94,7 +94,7 @@ svfloat16_t test_svminnm_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminnm.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svminnm_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z18test_svminnm_f32_mu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminnm.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -111,7 +111,7 @@ svfloat32_t test_svminnm_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminnm.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svminnm_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z18test_svminnm_f64_mu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminnm.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -128,7 +128,7 @@ svfloat64_t test_svminnm_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminnm.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svminnm_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svminnm_f16_xu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminnm.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -145,7 +145,7 @@ svfloat16_t test_svminnm_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminnm.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svminnm_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z18test_svminnm_f32_xu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminnm.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -162,7 +162,7 @@ svfloat32_t test_svminnm_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminnm.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svminnm_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z18test_svminnm_f64_xu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminnm.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mla.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mla.c index 1a6d79646cf3a..9920d243751c5 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mla.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mla.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svmla_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svmla_s8_zu10__SVBool_tu10__SVInt8_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]], [[OP3:%.*]]) @@ -38,7 +38,7 @@ svint8_t test_svmla_s8_z(svbool_t pg, svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mla.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_s16_zu10__SVBool_tu11__SVInt16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -57,7 +57,7 @@ svint16_t test_svmla_s16_z(svbool_t pg, svint16_t op1, svint16_t op2, svint16_t // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mla.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_s32_zu10__SVBool_tu11__SVInt32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -76,7 +76,7 @@ svint32_t test_svmla_s32_z(svbool_t pg, svint32_t op1, svint32_t op2, svint32_t // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mla.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_s64_zu10__SVBool_tu11__SVInt64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -94,7 +94,7 @@ svint64_t test_svmla_s64_z(svbool_t pg, svint64_t op1, svint64_t op2, svint64_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svmla_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svmla_u8_zu10__SVBool_tu11__SVUint8_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]], [[OP3:%.*]]) @@ -112,7 +112,7 @@ svuint8_t test_svmla_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2, svuint8_t o // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mla.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_u16_zu10__SVBool_tu12__SVUint16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -131,7 +131,7 @@ svuint16_t test_svmla_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2, svuint1 // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mla.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_u32_zu10__SVBool_tu12__SVUint32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -150,7 +150,7 @@ svuint32_t test_svmla_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2, svuint3 // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mla.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_u64_zu10__SVBool_tu12__SVUint64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -167,7 +167,7 @@ svuint64_t test_svmla_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2, svuint6 // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmla_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svmla_s8_mu10__SVBool_tu10__SVInt8_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -183,7 +183,7 @@ svint8_t test_svmla_s8_m(svbool_t pg, svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_s16_mu10__SVBool_tu11__SVInt16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -200,7 +200,7 @@ svint16_t test_svmla_s16_m(svbool_t pg, svint16_t op1, svint16_t op2, svint16_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_s32_mu10__SVBool_tu11__SVInt32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -217,7 +217,7 @@ svint32_t test_svmla_s32_m(svbool_t pg, svint32_t op1, svint32_t op2, svint32_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_s64_mu10__SVBool_tu11__SVInt64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -233,7 +233,7 @@ svint64_t test_svmla_s64_m(svbool_t pg, svint64_t op1, svint64_t op2, svint64_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmla_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svmla_u8_mu10__SVBool_tu11__SVUint8_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -249,7 +249,7 @@ svuint8_t test_svmla_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2, svuint8_t o // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_u16_mu10__SVBool_tu12__SVUint16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -266,7 +266,7 @@ svuint16_t test_svmla_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2, svuint1 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_u32_mu10__SVBool_tu12__SVUint32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -283,7 +283,7 @@ svuint32_t test_svmla_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2, svuint3 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_u64_mu10__SVBool_tu12__SVUint64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -299,7 +299,7 @@ svuint64_t test_svmla_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2, svuint6 // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmla_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svmla_s8_xu10__SVBool_tu10__SVInt8_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -315,7 +315,7 @@ svint8_t test_svmla_s8_x(svbool_t pg, svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_s16_xu10__SVBool_tu11__SVInt16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -332,7 +332,7 @@ svint16_t test_svmla_s16_x(svbool_t pg, svint16_t op1, svint16_t op2, svint16_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_s32_xu10__SVBool_tu11__SVInt32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -349,7 +349,7 @@ svint32_t test_svmla_s32_x(svbool_t pg, svint32_t op1, svint32_t op2, svint32_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_s64_xu10__SVBool_tu11__SVInt64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -365,7 +365,7 @@ svint64_t test_svmla_s64_x(svbool_t pg, svint64_t op1, svint64_t op2, svint64_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmla_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svmla_u8_xu10__SVBool_tu11__SVUint8_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -381,7 +381,7 @@ svuint8_t test_svmla_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2, svuint8_t o // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_u16_xu10__SVBool_tu12__SVUint16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -398,7 +398,7 @@ svuint16_t test_svmla_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2, svuint1 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_u32_xu10__SVBool_tu12__SVUint32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -415,7 +415,7 @@ svuint32_t test_svmla_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2, svuint3 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_u64_xu10__SVBool_tu12__SVUint64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -434,7 +434,7 @@ svuint64_t test_svmla_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2, svuint6 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmla_n_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_ta( +// CPP-CHECK-LABEL: @_Z17test_svmla_n_s8_zu10__SVBool_tu10__SVInt8_tS0_a( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -456,7 +456,7 @@ svint8_t test_svmla_n_s8_z(svbool_t pg, svint8_t op1, svint8_t op2, int8_t op3) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mla.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_ts( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_s16_zu10__SVBool_tu11__SVInt16_tS0_s( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 @@ -479,7 +479,7 @@ svint16_t test_svmla_n_s16_z(svbool_t pg, svint16_t op1, svint16_t op2, int16_t // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mla.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_ti( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_s32_zu10__SVBool_tu11__SVInt32_tS0_i( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 @@ -502,7 +502,7 @@ svint32_t test_svmla_n_s32_z(svbool_t pg, svint32_t op1, svint32_t op2, int32_t // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mla.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_tl( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_s64_zu10__SVBool_tu11__SVInt64_tS0_l( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 @@ -524,7 +524,7 @@ svint64_t test_svmla_n_s64_z(svbool_t pg, svint64_t op1, svint64_t op2, int64_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmla_n_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_th( +// CPP-CHECK-LABEL: @_Z17test_svmla_n_u8_zu10__SVBool_tu11__SVUint8_tS0_h( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -546,7 +546,7 @@ svuint8_t test_svmla_n_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2, uint8_t o // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mla.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_tt( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_u16_zu10__SVBool_tu12__SVUint16_tS0_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 @@ -569,7 +569,7 @@ svuint16_t test_svmla_n_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2, uint1 // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mla.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_u32_zu10__SVBool_tu12__SVUint32_tS0_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 @@ -592,7 +592,7 @@ svuint32_t test_svmla_n_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2, uint3 // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mla.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_u64_zu10__SVBool_tu12__SVUint64_tS0_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 @@ -613,7 +613,7 @@ svuint64_t test_svmla_n_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2, uint6 // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svmla_n_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_ta( +// CPP-CHECK-LABEL: @_Z17test_svmla_n_s8_mu10__SVBool_tu10__SVInt8_tS0_a( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -633,7 +633,7 @@ svint8_t test_svmla_n_s8_m(svbool_t pg, svint8_t op1, svint8_t op2, int8_t op3) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_ts( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_s16_mu10__SVBool_tu11__SVInt16_tS0_s( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 @@ -654,7 +654,7 @@ svint16_t test_svmla_n_s16_m(svbool_t pg, svint16_t op1, svint16_t op2, int16_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_ti( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_s32_mu10__SVBool_tu11__SVInt32_tS0_i( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 @@ -675,7 +675,7 @@ svint32_t test_svmla_n_s32_m(svbool_t pg, svint32_t op1, svint32_t op2, int32_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_tl( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_s64_mu10__SVBool_tu11__SVInt64_tS0_l( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 @@ -695,7 +695,7 @@ svint64_t test_svmla_n_s64_m(svbool_t pg, svint64_t op1, svint64_t op2, int64_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svmla_n_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_th( +// CPP-CHECK-LABEL: @_Z17test_svmla_n_u8_mu10__SVBool_tu11__SVUint8_tS0_h( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -715,7 +715,7 @@ svuint8_t test_svmla_n_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2, uint8_t o // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_tt( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_u16_mu10__SVBool_tu12__SVUint16_tS0_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 @@ -736,7 +736,7 @@ svuint16_t test_svmla_n_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2, uint1 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_u32_mu10__SVBool_tu12__SVUint32_tS0_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 @@ -757,7 +757,7 @@ svuint32_t test_svmla_n_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2, uint3 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_u64_mu10__SVBool_tu12__SVUint64_tS0_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 @@ -777,7 +777,7 @@ svuint64_t test_svmla_n_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2, uint6 // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svmla_n_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_ta( +// CPP-CHECK-LABEL: @_Z17test_svmla_n_s8_xu10__SVBool_tu10__SVInt8_tS0_a( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -797,7 +797,7 @@ svint8_t test_svmla_n_s8_x(svbool_t pg, svint8_t op1, svint8_t op2, int8_t op3) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_ts( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_s16_xu10__SVBool_tu11__SVInt16_tS0_s( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 @@ -818,7 +818,7 @@ svint16_t test_svmla_n_s16_x(svbool_t pg, svint16_t op1, svint16_t op2, int16_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_ti( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_s32_xu10__SVBool_tu11__SVInt32_tS0_i( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 @@ -839,7 +839,7 @@ svint32_t test_svmla_n_s32_x(svbool_t pg, svint32_t op1, svint32_t op2, int32_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_tl( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_s64_xu10__SVBool_tu11__SVInt64_tS0_l( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 @@ -859,7 +859,7 @@ svint64_t test_svmla_n_s64_x(svbool_t pg, svint64_t op1, svint64_t op2, int64_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svmla_n_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_th( +// CPP-CHECK-LABEL: @_Z17test_svmla_n_u8_xu10__SVBool_tu11__SVUint8_tS0_h( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -879,7 +879,7 @@ svuint8_t test_svmla_n_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2, uint8_t o // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_tt( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_u16_xu10__SVBool_tu12__SVUint16_tS0_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 @@ -900,7 +900,7 @@ svuint16_t test_svmla_n_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2, uint1 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_u32_xu10__SVBool_tu12__SVUint32_tS0_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 @@ -921,7 +921,7 @@ svuint32_t test_svmla_n_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2, uint3 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mla.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_u64_xu10__SVBool_tu12__SVUint64_tS0_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 @@ -941,7 +941,7 @@ svuint64_t test_svmla_n_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2, uint6 // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmla.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_f16_zu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -960,7 +960,7 @@ svfloat16_t test_svmla_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfl // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmla.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_f32_zu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -979,7 +979,7 @@ svfloat32_t test_svmla_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfl // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmla.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_f64_zu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -997,7 +997,7 @@ svfloat64_t test_svmla_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_f16_mu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -1014,7 +1014,7 @@ svfloat16_t test_svmla_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_f32_mu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -1031,7 +1031,7 @@ svfloat32_t test_svmla_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_f64_mu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -1048,7 +1048,7 @@ svfloat64_t test_svmla_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_f16_xu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -1065,7 +1065,7 @@ svfloat16_t test_svmla_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_f32_xu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -1082,7 +1082,7 @@ svfloat32_t test_svmla_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmla_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svmla_f64_xu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -1102,7 +1102,7 @@ svfloat64_t test_svmla_f64_x(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfl // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmla.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tDh( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_f16_zu10__SVBool_tu13__SVFloat16_tS0_Dh( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, half [[OP3:%.*]], i64 0 @@ -1125,7 +1125,7 @@ svfloat16_t test_svmla_n_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, fl // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmla.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tf( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_f32_zu10__SVBool_tu13__SVFloat32_tS0_f( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, float [[OP3:%.*]], i64 0 @@ -1148,7 +1148,7 @@ svfloat32_t test_svmla_n_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, fl // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmla.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_td( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_f64_zu10__SVBool_tu13__SVFloat64_tS0_d( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, double [[OP3:%.*]], i64 0 @@ -1170,7 +1170,7 @@ svfloat64_t test_svmla_n_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, fl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tDh( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_f16_mu10__SVBool_tu13__SVFloat16_tS0_Dh( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, half [[OP3:%.*]], i64 0 @@ -1191,7 +1191,7 @@ svfloat16_t test_svmla_n_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, fl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tf( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_f32_mu10__SVBool_tu13__SVFloat32_tS0_f( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, float [[OP3:%.*]], i64 0 @@ -1212,7 +1212,7 @@ svfloat32_t test_svmla_n_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, fl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_td( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_f64_mu10__SVBool_tu13__SVFloat64_tS0_d( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, double [[OP3:%.*]], i64 0 @@ -1233,7 +1233,7 @@ svfloat64_t test_svmla_n_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, fl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tDh( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_f16_xu10__SVBool_tu13__SVFloat16_tS0_Dh( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, half [[OP3:%.*]], i64 0 @@ -1254,7 +1254,7 @@ svfloat16_t test_svmla_n_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, fl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tf( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_f32_xu10__SVBool_tu13__SVFloat32_tS0_f( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, float [[OP3:%.*]], i64 0 @@ -1275,7 +1275,7 @@ svfloat32_t test_svmla_n_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, fl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmla.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmla_n_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_td( +// CPP-CHECK-LABEL: @_Z18test_svmla_n_f64_xu10__SVBool_tu13__SVFloat64_tS0_d( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, double [[OP3:%.*]], i64 0 @@ -1293,7 +1293,7 @@ svfloat64_t test_svmla_n_f64_x(svbool_t pg, svfloat64_t op1, svfloat64_t op2, fl // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmla.lane.nxv8f16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmla_lane_f16u13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z19test_svmla_lane_f16u13__SVFloat16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmla.lane.nxv8f16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -1308,7 +1308,7 @@ svfloat16_t test_svmla_lane_f16(svfloat16_t op1, svfloat16_t op2, svfloat16_t op // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmla.lane.nxv8f16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmla_lane_f16_1u13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z21test_svmla_lane_f16_1u13__SVFloat16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmla.lane.nxv8f16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -1323,7 +1323,7 @@ svfloat16_t test_svmla_lane_f16_1(svfloat16_t op1, svfloat16_t op2, svfloat16_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmla.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmla_lane_f32u13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z19test_svmla_lane_f32u13__SVFloat32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmla.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -1338,7 +1338,7 @@ svfloat32_t test_svmla_lane_f32(svfloat32_t op1, svfloat32_t op2, svfloat32_t op // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmla.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmla_lane_f32_1u13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z21test_svmla_lane_f32_1u13__SVFloat32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmla.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -1353,7 +1353,7 @@ svfloat32_t test_svmla_lane_f32_1(svfloat32_t op1, svfloat32_t op2, svfloat32_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmla.lane.nxv2f64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmla_lane_f64u13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z19test_svmla_lane_f64u13__SVFloat64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmla.lane.nxv2f64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -1368,7 +1368,7 @@ svfloat64_t test_svmla_lane_f64(svfloat64_t op1, svfloat64_t op2, svfloat64_t op // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmla.lane.nxv2f64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmla_lane_f64_1u13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z21test_svmla_lane_f64_1u13__SVFloat64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmla.lane.nxv2f64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mls.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mls.c index e2afbecb86d52..73537d40648a8 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mls.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mls.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svmls_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svmls_s8_zu10__SVBool_tu10__SVInt8_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]], [[OP3:%.*]]) @@ -38,7 +38,7 @@ svint8_t test_svmls_s8_z(svbool_t pg, svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mls.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_s16_zu10__SVBool_tu11__SVInt16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -57,7 +57,7 @@ svint16_t test_svmls_s16_z(svbool_t pg, svint16_t op1, svint16_t op2, svint16_t // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mls.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_s32_zu10__SVBool_tu11__SVInt32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -76,7 +76,7 @@ svint32_t test_svmls_s32_z(svbool_t pg, svint32_t op1, svint32_t op2, svint32_t // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mls.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_s64_zu10__SVBool_tu11__SVInt64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -94,7 +94,7 @@ svint64_t test_svmls_s64_z(svbool_t pg, svint64_t op1, svint64_t op2, svint64_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svmls_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svmls_u8_zu10__SVBool_tu11__SVUint8_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]], [[OP3:%.*]]) @@ -112,7 +112,7 @@ svuint8_t test_svmls_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2, svuint8_t o // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mls.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_u16_zu10__SVBool_tu12__SVUint16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -131,7 +131,7 @@ svuint16_t test_svmls_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2, svuint1 // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mls.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_u32_zu10__SVBool_tu12__SVUint32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -150,7 +150,7 @@ svuint32_t test_svmls_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2, svuint3 // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mls.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_u64_zu10__SVBool_tu12__SVUint64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -167,7 +167,7 @@ svuint64_t test_svmls_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2, svuint6 // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmls_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svmls_s8_mu10__SVBool_tu10__SVInt8_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -183,7 +183,7 @@ svint8_t test_svmls_s8_m(svbool_t pg, svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_s16_mu10__SVBool_tu11__SVInt16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -200,7 +200,7 @@ svint16_t test_svmls_s16_m(svbool_t pg, svint16_t op1, svint16_t op2, svint16_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_s32_mu10__SVBool_tu11__SVInt32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -217,7 +217,7 @@ svint32_t test_svmls_s32_m(svbool_t pg, svint32_t op1, svint32_t op2, svint32_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_s64_mu10__SVBool_tu11__SVInt64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -233,7 +233,7 @@ svint64_t test_svmls_s64_m(svbool_t pg, svint64_t op1, svint64_t op2, svint64_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmls_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svmls_u8_mu10__SVBool_tu11__SVUint8_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -249,7 +249,7 @@ svuint8_t test_svmls_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2, svuint8_t o // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_u16_mu10__SVBool_tu12__SVUint16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -266,7 +266,7 @@ svuint16_t test_svmls_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2, svuint1 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_u32_mu10__SVBool_tu12__SVUint32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -283,7 +283,7 @@ svuint32_t test_svmls_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2, svuint3 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_u64_mu10__SVBool_tu12__SVUint64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -299,7 +299,7 @@ svuint64_t test_svmls_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2, svuint6 // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmls_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svmls_s8_xu10__SVBool_tu10__SVInt8_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -315,7 +315,7 @@ svint8_t test_svmls_s8_x(svbool_t pg, svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_s16_xu10__SVBool_tu11__SVInt16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -332,7 +332,7 @@ svint16_t test_svmls_s16_x(svbool_t pg, svint16_t op1, svint16_t op2, svint16_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_s32_xu10__SVBool_tu11__SVInt32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -349,7 +349,7 @@ svint32_t test_svmls_s32_x(svbool_t pg, svint32_t op1, svint32_t op2, svint32_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_s64_xu10__SVBool_tu11__SVInt64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -365,7 +365,7 @@ svint64_t test_svmls_s64_x(svbool_t pg, svint64_t op1, svint64_t op2, svint64_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmls_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svmls_u8_xu10__SVBool_tu11__SVUint8_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -381,7 +381,7 @@ svuint8_t test_svmls_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2, svuint8_t o // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_u16_xu10__SVBool_tu12__SVUint16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -398,7 +398,7 @@ svuint16_t test_svmls_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2, svuint1 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_u32_xu10__SVBool_tu12__SVUint32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -415,7 +415,7 @@ svuint32_t test_svmls_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2, svuint3 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_u64_xu10__SVBool_tu12__SVUint64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -434,7 +434,7 @@ svuint64_t test_svmls_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2, svuint6 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmls_n_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_ta( +// CPP-CHECK-LABEL: @_Z17test_svmls_n_s8_zu10__SVBool_tu10__SVInt8_tS0_a( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -456,7 +456,7 @@ svint8_t test_svmls_n_s8_z(svbool_t pg, svint8_t op1, svint8_t op2, int8_t op3) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mls.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_ts( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_s16_zu10__SVBool_tu11__SVInt16_tS0_s( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 @@ -479,7 +479,7 @@ svint16_t test_svmls_n_s16_z(svbool_t pg, svint16_t op1, svint16_t op2, int16_t // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mls.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_ti( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_s32_zu10__SVBool_tu11__SVInt32_tS0_i( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 @@ -502,7 +502,7 @@ svint32_t test_svmls_n_s32_z(svbool_t pg, svint32_t op1, svint32_t op2, int32_t // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mls.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_tl( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_s64_zu10__SVBool_tu11__SVInt64_tS0_l( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 @@ -524,7 +524,7 @@ svint64_t test_svmls_n_s64_z(svbool_t pg, svint64_t op1, svint64_t op2, int64_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmls_n_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_th( +// CPP-CHECK-LABEL: @_Z17test_svmls_n_u8_zu10__SVBool_tu11__SVUint8_tS0_h( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -546,7 +546,7 @@ svuint8_t test_svmls_n_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2, uint8_t o // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mls.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_tt( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_u16_zu10__SVBool_tu12__SVUint16_tS0_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 @@ -569,7 +569,7 @@ svuint16_t test_svmls_n_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2, uint1 // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mls.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_u32_zu10__SVBool_tu12__SVUint32_tS0_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 @@ -592,7 +592,7 @@ svuint32_t test_svmls_n_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2, uint3 // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mls.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_u64_zu10__SVBool_tu12__SVUint64_tS0_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 @@ -613,7 +613,7 @@ svuint64_t test_svmls_n_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2, uint6 // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svmls_n_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_ta( +// CPP-CHECK-LABEL: @_Z17test_svmls_n_s8_mu10__SVBool_tu10__SVInt8_tS0_a( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -633,7 +633,7 @@ svint8_t test_svmls_n_s8_m(svbool_t pg, svint8_t op1, svint8_t op2, int8_t op3) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_ts( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_s16_mu10__SVBool_tu11__SVInt16_tS0_s( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 @@ -654,7 +654,7 @@ svint16_t test_svmls_n_s16_m(svbool_t pg, svint16_t op1, svint16_t op2, int16_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_ti( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_s32_mu10__SVBool_tu11__SVInt32_tS0_i( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 @@ -675,7 +675,7 @@ svint32_t test_svmls_n_s32_m(svbool_t pg, svint32_t op1, svint32_t op2, int32_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_tl( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_s64_mu10__SVBool_tu11__SVInt64_tS0_l( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 @@ -695,7 +695,7 @@ svint64_t test_svmls_n_s64_m(svbool_t pg, svint64_t op1, svint64_t op2, int64_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svmls_n_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_th( +// CPP-CHECK-LABEL: @_Z17test_svmls_n_u8_mu10__SVBool_tu11__SVUint8_tS0_h( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -715,7 +715,7 @@ svuint8_t test_svmls_n_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2, uint8_t o // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_tt( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_u16_mu10__SVBool_tu12__SVUint16_tS0_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 @@ -736,7 +736,7 @@ svuint16_t test_svmls_n_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2, uint1 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_u32_mu10__SVBool_tu12__SVUint32_tS0_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 @@ -757,7 +757,7 @@ svuint32_t test_svmls_n_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2, uint3 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_u64_mu10__SVBool_tu12__SVUint64_tS0_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 @@ -777,7 +777,7 @@ svuint64_t test_svmls_n_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2, uint6 // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svmls_n_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_ta( +// CPP-CHECK-LABEL: @_Z17test_svmls_n_s8_xu10__SVBool_tu10__SVInt8_tS0_a( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -797,7 +797,7 @@ svint8_t test_svmls_n_s8_x(svbool_t pg, svint8_t op1, svint8_t op2, int8_t op3) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_ts( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_s16_xu10__SVBool_tu11__SVInt16_tS0_s( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 @@ -818,7 +818,7 @@ svint16_t test_svmls_n_s16_x(svbool_t pg, svint16_t op1, svint16_t op2, int16_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_ti( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_s32_xu10__SVBool_tu11__SVInt32_tS0_i( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 @@ -839,7 +839,7 @@ svint32_t test_svmls_n_s32_x(svbool_t pg, svint32_t op1, svint32_t op2, int32_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_tl( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_s64_xu10__SVBool_tu11__SVInt64_tS0_l( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 @@ -859,7 +859,7 @@ svint64_t test_svmls_n_s64_x(svbool_t pg, svint64_t op1, svint64_t op2, int64_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svmls_n_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_th( +// CPP-CHECK-LABEL: @_Z17test_svmls_n_u8_xu10__SVBool_tu11__SVUint8_tS0_h( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -879,7 +879,7 @@ svuint8_t test_svmls_n_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2, uint8_t o // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_tt( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_u16_xu10__SVBool_tu12__SVUint16_tS0_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 @@ -900,7 +900,7 @@ svuint16_t test_svmls_n_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2, uint1 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_u32_xu10__SVBool_tu12__SVUint32_tS0_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 @@ -921,7 +921,7 @@ svuint32_t test_svmls_n_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2, uint3 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_u64_xu10__SVBool_tu12__SVUint64_tS0_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 @@ -941,7 +941,7 @@ svuint64_t test_svmls_n_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2, uint6 // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmls.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_f16_zu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -960,7 +960,7 @@ svfloat16_t test_svmls_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfl // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmls.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_f32_zu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -979,7 +979,7 @@ svfloat32_t test_svmls_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfl // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmls.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_f64_zu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -997,7 +997,7 @@ svfloat64_t test_svmls_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_f16_mu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -1014,7 +1014,7 @@ svfloat16_t test_svmls_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_f32_mu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -1031,7 +1031,7 @@ svfloat32_t test_svmls_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_f64_mu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -1048,7 +1048,7 @@ svfloat64_t test_svmls_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_f16_xu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -1065,7 +1065,7 @@ svfloat16_t test_svmls_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_f32_xu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -1082,7 +1082,7 @@ svfloat32_t test_svmls_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmls_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svmls_f64_xu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -1102,7 +1102,7 @@ svfloat64_t test_svmls_f64_x(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfl // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmls.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tDh( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_f16_zu10__SVBool_tu13__SVFloat16_tS0_Dh( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, half [[OP3:%.*]], i64 0 @@ -1125,7 +1125,7 @@ svfloat16_t test_svmls_n_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, fl // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmls.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tf( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_f32_zu10__SVBool_tu13__SVFloat32_tS0_f( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, float [[OP3:%.*]], i64 0 @@ -1148,7 +1148,7 @@ svfloat32_t test_svmls_n_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, fl // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmls.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_td( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_f64_zu10__SVBool_tu13__SVFloat64_tS0_d( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, double [[OP3:%.*]], i64 0 @@ -1170,7 +1170,7 @@ svfloat64_t test_svmls_n_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, fl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tDh( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_f16_mu10__SVBool_tu13__SVFloat16_tS0_Dh( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, half [[OP3:%.*]], i64 0 @@ -1191,7 +1191,7 @@ svfloat16_t test_svmls_n_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, fl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tf( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_f32_mu10__SVBool_tu13__SVFloat32_tS0_f( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, float [[OP3:%.*]], i64 0 @@ -1212,7 +1212,7 @@ svfloat32_t test_svmls_n_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, fl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_td( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_f64_mu10__SVBool_tu13__SVFloat64_tS0_d( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, double [[OP3:%.*]], i64 0 @@ -1233,7 +1233,7 @@ svfloat64_t test_svmls_n_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, fl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tDh( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_f16_xu10__SVBool_tu13__SVFloat16_tS0_Dh( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, half [[OP3:%.*]], i64 0 @@ -1254,7 +1254,7 @@ svfloat16_t test_svmls_n_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, fl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tf( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_f32_xu10__SVBool_tu13__SVFloat32_tS0_f( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, float [[OP3:%.*]], i64 0 @@ -1275,7 +1275,7 @@ svfloat32_t test_svmls_n_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, fl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmls_n_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_td( +// CPP-CHECK-LABEL: @_Z18test_svmls_n_f64_xu10__SVBool_tu13__SVFloat64_tS0_d( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, double [[OP3:%.*]], i64 0 @@ -1293,7 +1293,7 @@ svfloat64_t test_svmls_n_f64_x(svbool_t pg, svfloat64_t op1, svfloat64_t op2, fl // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmls.lane.nxv8f16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmls_lane_f16u13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z19test_svmls_lane_f16u13__SVFloat16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmls.lane.nxv8f16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -1308,7 +1308,7 @@ svfloat16_t test_svmls_lane_f16(svfloat16_t op1, svfloat16_t op2, svfloat16_t op // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmls.lane.nxv8f16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmls_lane_f16_1u13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z21test_svmls_lane_f16_1u13__SVFloat16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmls.lane.nxv8f16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -1323,7 +1323,7 @@ svfloat16_t test_svmls_lane_f16_1(svfloat16_t op1, svfloat16_t op2, svfloat16_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmls.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmls_lane_f32u13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z19test_svmls_lane_f32u13__SVFloat32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmls.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -1338,7 +1338,7 @@ svfloat32_t test_svmls_lane_f32(svfloat32_t op1, svfloat32_t op2, svfloat32_t op // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmls.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmls_lane_f32_1u13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z21test_svmls_lane_f32_1u13__SVFloat32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmls.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -1353,7 +1353,7 @@ svfloat32_t test_svmls_lane_f32_1(svfloat32_t op1, svfloat32_t op2, svfloat32_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmls.lane.nxv2f64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmls_lane_f64u13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z19test_svmls_lane_f64u13__SVFloat64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmls.lane.nxv2f64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -1368,7 +1368,7 @@ svfloat64_t test_svmls_lane_f64(svfloat64_t op1, svfloat64_t op2, svfloat64_t op // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmls.lane.nxv2f64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmls_lane_f64_1u13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z21test_svmls_lane_f64_1u13__SVFloat64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmls.lane.nxv2f64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mmla.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mmla.c index 1044aec4dc46f..88c3df7c93d1d 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mmla.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mmla.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smmla.nxv4i32( [[X:%.*]], [[Y:%.*]], [[Z:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmmla_s32u11__SVInt32_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svmmla_s32u11__SVInt32_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smmla.nxv4i32( [[X:%.*]], [[Y:%.*]], [[Z:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svint32_t test_svmmla_s32(svint32_t x, svint8_t y, svint8_t z) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ummla.nxv4i32( [[X:%.*]], [[Y:%.*]], [[Z:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmmla_u32u12__SVUint32_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svmmla_u32u12__SVUint32_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ummla.nxv4i32( [[X:%.*]], [[Y:%.*]], [[Z:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mov.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mov.c index 35112db22b450..7acd2ca31171f 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mov.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mov.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.z.nxv16i1( [[PG:%.*]], [[OP:%.*]], [[OP]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svmov_b_zu10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z14test_svmov_b_zu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.and.z.nxv16i1( [[PG:%.*]], [[OP:%.*]], [[OP]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_msb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_msb.c index c353c9725b3f7..fadee9ee22db4 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_msb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_msb.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.msb.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svmsb_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svmsb_s8_zu10__SVBool_tu10__SVInt8_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.msb.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]], [[OP3:%.*]]) @@ -38,7 +38,7 @@ svint8_t test_svmsb_s8_z(svbool_t pg, svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.msb.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_s16_zu10__SVBool_tu11__SVInt16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -57,7 +57,7 @@ svint16_t test_svmsb_s16_z(svbool_t pg, svint16_t op1, svint16_t op2, svint16_t // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.msb.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_s32_zu10__SVBool_tu11__SVInt32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -76,7 +76,7 @@ svint32_t test_svmsb_s32_z(svbool_t pg, svint32_t op1, svint32_t op2, svint32_t // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.msb.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_s64_zu10__SVBool_tu11__SVInt64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -94,7 +94,7 @@ svint64_t test_svmsb_s64_z(svbool_t pg, svint64_t op1, svint64_t op2, svint64_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.msb.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svmsb_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svmsb_u8_zu10__SVBool_tu11__SVUint8_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.msb.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]], [[OP3:%.*]]) @@ -112,7 +112,7 @@ svuint8_t test_svmsb_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2, svuint8_t o // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.msb.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_u16_zu10__SVBool_tu12__SVUint16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -131,7 +131,7 @@ svuint16_t test_svmsb_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2, svuint1 // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.msb.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_u32_zu10__SVBool_tu12__SVUint32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -150,7 +150,7 @@ svuint32_t test_svmsb_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2, svuint3 // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.msb.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_u64_zu10__SVBool_tu12__SVUint64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -167,7 +167,7 @@ svuint64_t test_svmsb_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2, svuint6 // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.msb.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmsb_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svmsb_s8_mu10__SVBool_tu10__SVInt8_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.msb.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -183,7 +183,7 @@ svint8_t test_svmsb_s8_m(svbool_t pg, svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.msb.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_s16_mu10__SVBool_tu11__SVInt16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.msb.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -200,7 +200,7 @@ svint16_t test_svmsb_s16_m(svbool_t pg, svint16_t op1, svint16_t op2, svint16_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.msb.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_s32_mu10__SVBool_tu11__SVInt32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.msb.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -217,7 +217,7 @@ svint32_t test_svmsb_s32_m(svbool_t pg, svint32_t op1, svint32_t op2, svint32_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.msb.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_s64_mu10__SVBool_tu11__SVInt64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.msb.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -233,7 +233,7 @@ svint64_t test_svmsb_s64_m(svbool_t pg, svint64_t op1, svint64_t op2, svint64_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.msb.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmsb_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svmsb_u8_mu10__SVBool_tu11__SVUint8_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.msb.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -249,7 +249,7 @@ svuint8_t test_svmsb_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2, svuint8_t o // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.msb.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_u16_mu10__SVBool_tu12__SVUint16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.msb.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -266,7 +266,7 @@ svuint16_t test_svmsb_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2, svuint1 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.msb.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_u32_mu10__SVBool_tu12__SVUint32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.msb.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -283,7 +283,7 @@ svuint32_t test_svmsb_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2, svuint3 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.msb.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_u64_mu10__SVBool_tu12__SVUint64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.msb.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -299,7 +299,7 @@ svuint64_t test_svmsb_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2, svuint6 // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv16i8( [[PG:%.*]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmsb_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svmsb_s8_xu10__SVBool_tu10__SVInt8_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv16i8( [[PG:%.*]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -315,7 +315,7 @@ svint8_t test_svmsb_s8_x(svbool_t pg, svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv8i16( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_s16_xu10__SVBool_tu11__SVInt16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv8i16( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) @@ -332,7 +332,7 @@ svint16_t test_svmsb_s16_x(svbool_t pg, svint16_t op1, svint16_t op2, svint16_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv4i32( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_s32_xu10__SVBool_tu11__SVInt32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv4i32( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) @@ -349,7 +349,7 @@ svint32_t test_svmsb_s32_x(svbool_t pg, svint32_t op1, svint32_t op2, svint32_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv2i64( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_s64_xu10__SVBool_tu11__SVInt64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv2i64( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) @@ -365,7 +365,7 @@ svint64_t test_svmsb_s64_x(svbool_t pg, svint64_t op1, svint64_t op2, svint64_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv16i8( [[PG:%.*]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmsb_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svmsb_u8_xu10__SVBool_tu11__SVUint8_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv16i8( [[PG:%.*]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -381,7 +381,7 @@ svuint8_t test_svmsb_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2, svuint8_t o // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv8i16( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_u16_xu10__SVBool_tu12__SVUint16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv8i16( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) @@ -398,7 +398,7 @@ svuint16_t test_svmsb_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2, svuint1 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv4i32( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_u32_xu10__SVBool_tu12__SVUint32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv4i32( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) @@ -415,7 +415,7 @@ svuint32_t test_svmsb_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2, svuint3 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv2i64( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_u64_xu10__SVBool_tu12__SVUint64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv2i64( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) @@ -434,7 +434,7 @@ svuint64_t test_svmsb_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2, svuint6 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.msb.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmsb_n_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_ta( +// CPP-CHECK-LABEL: @_Z17test_svmsb_n_s8_zu10__SVBool_tu10__SVInt8_tS0_a( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -456,7 +456,7 @@ svint8_t test_svmsb_n_s8_z(svbool_t pg, svint8_t op1, svint8_t op2, int8_t op3) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.msb.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_ts( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_s16_zu10__SVBool_tu11__SVInt16_tS0_s( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 @@ -479,7 +479,7 @@ svint16_t test_svmsb_n_s16_z(svbool_t pg, svint16_t op1, svint16_t op2, int16_t // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.msb.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_ti( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_s32_zu10__SVBool_tu11__SVInt32_tS0_i( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 @@ -502,7 +502,7 @@ svint32_t test_svmsb_n_s32_z(svbool_t pg, svint32_t op1, svint32_t op2, int32_t // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.msb.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_tl( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_s64_zu10__SVBool_tu11__SVInt64_tS0_l( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 @@ -524,7 +524,7 @@ svint64_t test_svmsb_n_s64_z(svbool_t pg, svint64_t op1, svint64_t op2, int64_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.msb.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmsb_n_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_th( +// CPP-CHECK-LABEL: @_Z17test_svmsb_n_u8_zu10__SVBool_tu11__SVUint8_tS0_h( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -546,7 +546,7 @@ svuint8_t test_svmsb_n_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2, uint8_t o // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.msb.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_tt( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_u16_zu10__SVBool_tu12__SVUint16_tS0_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 @@ -569,7 +569,7 @@ svuint16_t test_svmsb_n_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2, uint1 // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.msb.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_u32_zu10__SVBool_tu12__SVUint32_tS0_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 @@ -592,7 +592,7 @@ svuint32_t test_svmsb_n_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2, uint3 // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.msb.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_u64_zu10__SVBool_tu12__SVUint64_tS0_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 @@ -613,7 +613,7 @@ svuint64_t test_svmsb_n_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2, uint6 // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.msb.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svmsb_n_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_ta( +// CPP-CHECK-LABEL: @_Z17test_svmsb_n_s8_mu10__SVBool_tu10__SVInt8_tS0_a( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -633,7 +633,7 @@ svint8_t test_svmsb_n_s8_m(svbool_t pg, svint8_t op1, svint8_t op2, int8_t op3) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.msb.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_ts( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_s16_mu10__SVBool_tu11__SVInt16_tS0_s( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 @@ -654,7 +654,7 @@ svint16_t test_svmsb_n_s16_m(svbool_t pg, svint16_t op1, svint16_t op2, int16_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.msb.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_ti( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_s32_mu10__SVBool_tu11__SVInt32_tS0_i( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 @@ -675,7 +675,7 @@ svint32_t test_svmsb_n_s32_m(svbool_t pg, svint32_t op1, svint32_t op2, int32_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.msb.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_tl( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_s64_mu10__SVBool_tu11__SVInt64_tS0_l( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 @@ -695,7 +695,7 @@ svint64_t test_svmsb_n_s64_m(svbool_t pg, svint64_t op1, svint64_t op2, int64_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.msb.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svmsb_n_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_th( +// CPP-CHECK-LABEL: @_Z17test_svmsb_n_u8_mu10__SVBool_tu11__SVUint8_tS0_h( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -715,7 +715,7 @@ svuint8_t test_svmsb_n_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2, uint8_t o // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.msb.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_tt( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_u16_mu10__SVBool_tu12__SVUint16_tS0_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 @@ -736,7 +736,7 @@ svuint16_t test_svmsb_n_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2, uint1 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.msb.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_u32_mu10__SVBool_tu12__SVUint32_tS0_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 @@ -757,7 +757,7 @@ svuint32_t test_svmsb_n_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2, uint3 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.msb.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_u64_mu10__SVBool_tu12__SVUint64_tS0_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 @@ -777,7 +777,7 @@ svuint64_t test_svmsb_n_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2, uint6 // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv16i8( [[PG:%.*]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svmsb_n_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_ta( +// CPP-CHECK-LABEL: @_Z17test_svmsb_n_s8_xu10__SVBool_tu10__SVInt8_tS0_a( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -797,7 +797,7 @@ svint8_t test_svmsb_n_s8_x(svbool_t pg, svint8_t op1, svint8_t op2, int8_t op3) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv8i16( [[TMP0]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_ts( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_s16_xu10__SVBool_tu11__SVInt16_tS0_s( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 @@ -818,7 +818,7 @@ svint16_t test_svmsb_n_s16_x(svbool_t pg, svint16_t op1, svint16_t op2, int16_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv4i32( [[TMP0]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_ti( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_s32_xu10__SVBool_tu11__SVInt32_tS0_i( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 @@ -839,7 +839,7 @@ svint32_t test_svmsb_n_s32_x(svbool_t pg, svint32_t op1, svint32_t op2, int32_t // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv2i64( [[TMP0]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_tl( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_s64_xu10__SVBool_tu11__SVInt64_tS0_l( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 @@ -859,7 +859,7 @@ svint64_t test_svmsb_n_s64_x(svbool_t pg, svint64_t op1, svint64_t op2, int64_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv16i8( [[PG:%.*]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svmsb_n_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_th( +// CPP-CHECK-LABEL: @_Z17test_svmsb_n_u8_xu10__SVBool_tu11__SVUint8_tS0_h( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -879,7 +879,7 @@ svuint8_t test_svmsb_n_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2, uint8_t o // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv8i16( [[TMP0]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_tt( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_u16_xu10__SVBool_tu12__SVUint16_tS0_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 @@ -900,7 +900,7 @@ svuint16_t test_svmsb_n_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2, uint1 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv4i32( [[TMP0]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_u32_xu10__SVBool_tu12__SVUint32_tS0_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 @@ -921,7 +921,7 @@ svuint32_t test_svmsb_n_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2, uint3 // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mls.u.nxv2i64( [[TMP0]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_u64_xu10__SVBool_tu12__SVUint64_tS0_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 @@ -941,7 +941,7 @@ svuint64_t test_svmsb_n_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2, uint6 // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmsb.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_f16_zu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -960,7 +960,7 @@ svfloat16_t test_svmsb_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfl // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmsb.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_f32_zu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -979,7 +979,7 @@ svfloat32_t test_svmsb_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfl // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmsb.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_f64_zu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -997,7 +997,7 @@ svfloat64_t test_svmsb_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmsb.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_f16_mu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmsb.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -1014,7 +1014,7 @@ svfloat16_t test_svmsb_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmsb.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_f32_mu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmsb.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -1031,7 +1031,7 @@ svfloat32_t test_svmsb_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmsb.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_f64_mu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmsb.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -1048,7 +1048,7 @@ svfloat64_t test_svmsb_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.u.nxv8f16( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_f16_xu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.u.nxv8f16( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) @@ -1065,7 +1065,7 @@ svfloat16_t test_svmsb_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.u.nxv4f32( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_f32_xu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.u.nxv4f32( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) @@ -1082,7 +1082,7 @@ svfloat32_t test_svmsb_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.u.nxv2f64( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmsb_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svmsb_f64_xu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.u.nxv2f64( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) @@ -1102,7 +1102,7 @@ svfloat64_t test_svmsb_f64_x(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfl // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmsb.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tDh( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_f16_zu10__SVBool_tu13__SVFloat16_tS0_Dh( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, half [[OP3:%.*]], i64 0 @@ -1125,7 +1125,7 @@ svfloat16_t test_svmsb_n_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, fl // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmsb.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tf( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_f32_zu10__SVBool_tu13__SVFloat32_tS0_f( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, float [[OP3:%.*]], i64 0 @@ -1148,7 +1148,7 @@ svfloat32_t test_svmsb_n_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, fl // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmsb.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_td( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_f64_zu10__SVBool_tu13__SVFloat64_tS0_d( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, double [[OP3:%.*]], i64 0 @@ -1170,7 +1170,7 @@ svfloat64_t test_svmsb_n_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, fl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmsb.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tDh( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_f16_mu10__SVBool_tu13__SVFloat16_tS0_Dh( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, half [[OP3:%.*]], i64 0 @@ -1191,7 +1191,7 @@ svfloat16_t test_svmsb_n_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, fl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmsb.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tf( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_f32_mu10__SVBool_tu13__SVFloat32_tS0_f( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, float [[OP3:%.*]], i64 0 @@ -1212,7 +1212,7 @@ svfloat32_t test_svmsb_n_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, fl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmsb.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_td( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_f64_mu10__SVBool_tu13__SVFloat64_tS0_d( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, double [[OP3:%.*]], i64 0 @@ -1233,7 +1233,7 @@ svfloat64_t test_svmsb_n_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, fl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.u.nxv8f16( [[TMP0]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tDh( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_f16_xu10__SVBool_tu13__SVFloat16_tS0_Dh( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, half [[OP3:%.*]], i64 0 @@ -1254,7 +1254,7 @@ svfloat16_t test_svmsb_n_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, fl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.u.nxv4f32( [[TMP0]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tf( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_f32_xu10__SVBool_tu13__SVFloat32_tS0_f( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, float [[OP3:%.*]], i64 0 @@ -1275,7 +1275,7 @@ svfloat32_t test_svmsb_n_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, fl // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmls.u.nxv2f64( [[TMP0]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svmsb_n_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_td( +// CPP-CHECK-LABEL: @_Z18test_svmsb_n_f64_xu10__SVBool_tu13__SVFloat64_tS0_d( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, double [[OP3:%.*]], i64 0 diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mul.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mul.c index d95a3b7fb1a19..699d919f886a6 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mul.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mul.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svmul_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svmul_s8_zu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -38,7 +38,7 @@ svint8_t test_svmul_s8_z(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mul.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_s16_zu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -57,7 +57,7 @@ svint16_t test_svmul_s16_z(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mul.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -76,7 +76,7 @@ svint32_t test_svmul_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mul.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -94,7 +94,7 @@ svint64_t test_svmul_s64_z(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svmul_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svmul_u8_zu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -112,7 +112,7 @@ svuint8_t test_svmul_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mul.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_u16_zu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -131,7 +131,7 @@ svuint16_t test_svmul_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mul.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_u32_zu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -150,7 +150,7 @@ svuint32_t test_svmul_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.mul.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_u64_zu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -167,7 +167,7 @@ svuint64_t test_svmul_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmul_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svmul_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -183,7 +183,7 @@ svint8_t test_svmul_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -200,7 +200,7 @@ svint16_t test_svmul_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -217,7 +217,7 @@ svint32_t test_svmul_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -233,7 +233,7 @@ svint64_t test_svmul_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmul_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svmul_u8_mu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -249,7 +249,7 @@ svuint8_t test_svmul_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_u16_mu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -266,7 +266,7 @@ svuint16_t test_svmul_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -283,7 +283,7 @@ svuint32_t test_svmul_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -299,7 +299,7 @@ svuint64_t test_svmul_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmul_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svmul_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -315,7 +315,7 @@ svint8_t test_svmul_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -332,7 +332,7 @@ svint16_t test_svmul_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -349,7 +349,7 @@ svint32_t test_svmul_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -365,7 +365,7 @@ svint64_t test_svmul_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmul_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svmul_u8_xu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -381,7 +381,7 @@ svuint8_t test_svmul_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_u16_xu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -398,7 +398,7 @@ svuint16_t test_svmul_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -415,7 +415,7 @@ svuint32_t test_svmul_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.mul.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -941,7 +941,7 @@ svuint64_t test_svmul_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmul.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_f16_zu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -960,7 +960,7 @@ svfloat16_t test_svmul_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmul.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_f32_zu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -979,7 +979,7 @@ svfloat32_t test_svmul_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmul.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_f64_zu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -997,7 +997,7 @@ svfloat64_t test_svmul_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmul.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_f16_mu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmul.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1014,7 +1014,7 @@ svfloat16_t test_svmul_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmul.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_f32_mu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmul.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1031,7 +1031,7 @@ svfloat32_t test_svmul_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmul.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_f64_mu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmul.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1048,7 +1048,7 @@ svfloat64_t test_svmul_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmul.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_f16_xu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmul.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1065,7 +1065,7 @@ svfloat16_t test_svmul_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmul.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_f32_xu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmul.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1082,7 +1082,7 @@ svfloat32_t test_svmul_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmul.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmul_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svmul_f64_xu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmul.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1293,7 +1293,7 @@ svfloat64_t test_svmul_n_f64_x(svbool_t pg, svfloat64_t op1, float64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmul.lane.nxv8f16( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmul_lane_f16u13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z19test_svmul_lane_f16u13__SVFloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmul.lane.nxv8f16( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -1308,7 +1308,7 @@ svfloat16_t test_svmul_lane_f16(svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmul.lane.nxv8f16( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmul_lane_f16_1u13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z21test_svmul_lane_f16_1u13__SVFloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmul.lane.nxv8f16( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -1323,7 +1323,7 @@ svfloat16_t test_svmul_lane_f16_1(svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmul.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmul_lane_f32u13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z19test_svmul_lane_f32u13__SVFloat32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmul.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -1338,7 +1338,7 @@ svfloat32_t test_svmul_lane_f32(svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmul.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmul_lane_f32_1u13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z21test_svmul_lane_f32_1u13__SVFloat32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmul.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -1353,7 +1353,7 @@ svfloat32_t test_svmul_lane_f32_1(svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmul.lane.nxv2f64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmul_lane_f64u13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z19test_svmul_lane_f64u13__SVFloat64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmul.lane.nxv2f64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -1368,7 +1368,7 @@ svfloat64_t test_svmul_lane_f64(svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmul.lane.nxv2f64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmul_lane_f64_1u13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z21test_svmul_lane_f64_1u13__SVFloat64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmul.lane.nxv2f64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mulh.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mulh.c index b2e98f300470a..208507cba42c7 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mulh.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mulh.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smulh.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmulh_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svmulh_s8_zu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smulh.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -38,7 +38,7 @@ svint8_t test_svmulh_s8_z(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.smulh.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svmulh_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svmulh_s16_zu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -57,7 +57,7 @@ svint16_t test_svmulh_s16_z(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.smulh.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svmulh_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svmulh_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -76,7 +76,7 @@ svint32_t test_svmulh_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.smulh.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svmulh_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svmulh_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -94,7 +94,7 @@ svint64_t test_svmulh_s64_z(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umulh.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svmulh_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svmulh_u8_zu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umulh.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -112,7 +112,7 @@ svuint8_t test_svmulh_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.umulh.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svmulh_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svmulh_u16_zu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -131,7 +131,7 @@ svuint16_t test_svmulh_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.umulh.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svmulh_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svmulh_u32_zu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -150,7 +150,7 @@ svuint32_t test_svmulh_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.umulh.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svmulh_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svmulh_u64_zu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -167,7 +167,7 @@ svuint64_t test_svmulh_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smulh.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmulh_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svmulh_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smulh.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -183,7 +183,7 @@ svint8_t test_svmulh_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smulh.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmulh_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svmulh_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smulh.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -200,7 +200,7 @@ svint16_t test_svmulh_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smulh.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmulh_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svmulh_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smulh.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -217,7 +217,7 @@ svint32_t test_svmulh_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smulh.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmulh_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svmulh_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smulh.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -233,7 +233,7 @@ svint64_t test_svmulh_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umulh.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmulh_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svmulh_u8_mu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umulh.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -249,7 +249,7 @@ svuint8_t test_svmulh_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umulh.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmulh_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svmulh_u16_mu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umulh.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -266,7 +266,7 @@ svuint16_t test_svmulh_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umulh.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmulh_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svmulh_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umulh.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -283,7 +283,7 @@ svuint32_t test_svmulh_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umulh.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmulh_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svmulh_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umulh.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -299,7 +299,7 @@ svuint64_t test_svmulh_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smulh.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmulh_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svmulh_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smulh.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -315,7 +315,7 @@ svint8_t test_svmulh_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smulh.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmulh_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svmulh_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smulh.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -332,7 +332,7 @@ svint16_t test_svmulh_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smulh.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmulh_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svmulh_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smulh.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -349,7 +349,7 @@ svint32_t test_svmulh_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smulh.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmulh_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svmulh_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smulh.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -365,7 +365,7 @@ svint64_t test_svmulh_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umulh.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmulh_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svmulh_u8_xu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umulh.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -381,7 +381,7 @@ svuint8_t test_svmulh_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umulh.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmulh_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svmulh_u16_xu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umulh.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -398,7 +398,7 @@ svuint16_t test_svmulh_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umulh.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmulh_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svmulh_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umulh.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -415,7 +415,7 @@ svuint32_t test_svmulh_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umulh.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmulh_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svmulh_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umulh.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mulx.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mulx.c index fdee3b0b3ad3b..c56c03c30074b 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mulx.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mulx.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmulx.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svmulx_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svmulx_f16_zu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -40,7 +40,7 @@ svfloat16_t test_svmulx_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmulx.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svmulx_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svmulx_f32_zu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -59,7 +59,7 @@ svfloat32_t test_svmulx_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fmulx.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svmulx_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svmulx_f64_zu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -77,7 +77,7 @@ svfloat64_t test_svmulx_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmulx.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmulx_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svmulx_f16_mu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmulx.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -94,7 +94,7 @@ svfloat16_t test_svmulx_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmulx.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmulx_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svmulx_f32_mu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmulx.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -111,7 +111,7 @@ svfloat32_t test_svmulx_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmulx.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmulx_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svmulx_f64_mu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmulx.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -128,7 +128,7 @@ svfloat64_t test_svmulx_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmulx.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmulx_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svmulx_f16_xu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmulx.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -145,7 +145,7 @@ svfloat16_t test_svmulx_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmulx.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmulx_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svmulx_f32_xu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmulx.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -162,7 +162,7 @@ svfloat32_t test_svmulx_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmulx.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmulx_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svmulx_f64_xu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmulx.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nand.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nand.c index a76e126081f67..1344c712cd263 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nand.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nand.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nand.z.nxv16i1( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svnand_b_zu10__SVBool_tu10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svnand_b_zu10__SVBool_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nand.z.nxv16i1( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_neg.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_neg.c index 40b1e07ddcb5c..fdd8900763dfd 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_neg.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_neg.c @@ -85,7 +85,7 @@ svint64_t test_svneg_s64_z(svbool_t pg, svint64_t op) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.neg.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svneg_s8_mu10__SVInt8_tu10__SVBool_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svneg_s8_mu10__SVInt8_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.neg.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -101,7 +101,7 @@ svint8_t test_svneg_s8_m(svint8_t inactive, svbool_t pg, svint8_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.neg.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svneg_s16_mu11__SVInt16_tu10__SVBool_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svneg_s16_mu11__SVInt16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.neg.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -118,7 +118,7 @@ svint16_t test_svneg_s16_m(svint16_t inactive, svbool_t pg, svint16_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.neg.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svneg_s32_mu11__SVInt32_tu10__SVBool_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svneg_s32_mu11__SVInt32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.neg.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -135,7 +135,7 @@ svint32_t test_svneg_s32_m(svint32_t inactive, svbool_t pg, svint32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.neg.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svneg_s64_mu11__SVInt64_tu10__SVBool_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svneg_s64_mu11__SVInt64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.neg.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -269,7 +269,7 @@ svfloat64_t test_svneg_f64_z(svbool_t pg, svfloat64_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fneg.nxv8f16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svneg_f16_mu13__SVFloat16_tu10__SVBool_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svneg_f16_mu13__SVFloat16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fneg.nxv8f16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -286,7 +286,7 @@ svfloat16_t test_svneg_f16_m(svfloat16_t inactive, svbool_t pg, svfloat16_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fneg.nxv4f32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svneg_f32_mu13__SVFloat32_tu10__SVBool_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svneg_f32_mu13__SVFloat32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fneg.nxv4f32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -303,7 +303,7 @@ svfloat32_t test_svneg_f32_m(svfloat32_t inactive, svbool_t pg, svfloat32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fneg.nxv2f64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svneg_f64_mu13__SVFloat64_tu10__SVBool_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svneg_f64_mu13__SVFloat64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fneg.nxv2f64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmad.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmad.c index e0a18e1967494..3a05263e85a16 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmad.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmad.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fnmad.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svnmad_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svnmad_f16_zu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -40,7 +40,7 @@ svfloat16_t test_svnmad_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svf // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fnmad.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svnmad_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svnmad_f32_zu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -59,7 +59,7 @@ svfloat32_t test_svnmad_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svf // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fnmad.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svnmad_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svnmad_f64_zu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -77,7 +77,7 @@ svfloat64_t test_svnmad_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmad.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svnmad_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svnmad_f16_mu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmad.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -94,7 +94,7 @@ svfloat16_t test_svnmad_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmad.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svnmad_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svnmad_f32_mu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmad.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -111,7 +111,7 @@ svfloat32_t test_svnmad_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmad.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svnmad_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svnmad_f64_mu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmad.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -128,7 +128,7 @@ svfloat64_t test_svnmad_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.u.nxv8f16( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svnmad_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svnmad_f16_xu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.u.nxv8f16( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) @@ -145,7 +145,7 @@ svfloat16_t test_svnmad_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.u.nxv4f32( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svnmad_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svnmad_f32_xu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.u.nxv4f32( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) @@ -162,7 +162,7 @@ svfloat32_t test_svnmad_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.u.nxv2f64( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svnmad_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svnmad_f64_xu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.u.nxv2f64( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) @@ -182,7 +182,7 @@ svfloat64_t test_svnmad_f64_x(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svf // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fnmad.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z19test_svnmad_n_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tDh( +// CPP-CHECK-LABEL: @_Z19test_svnmad_n_f16_zu10__SVBool_tu13__SVFloat16_tS0_Dh( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, half [[OP3:%.*]], i64 0 @@ -205,7 +205,7 @@ svfloat16_t test_svnmad_n_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, f // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fnmad.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z19test_svnmad_n_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tf( +// CPP-CHECK-LABEL: @_Z19test_svnmad_n_f32_zu10__SVBool_tu13__SVFloat32_tS0_f( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, float [[OP3:%.*]], i64 0 @@ -228,7 +228,7 @@ svfloat32_t test_svnmad_n_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, f // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fnmad.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z19test_svnmad_n_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_td( +// CPP-CHECK-LABEL: @_Z19test_svnmad_n_f64_zu10__SVBool_tu13__SVFloat64_tS0_d( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, double [[OP3:%.*]], i64 0 @@ -250,7 +250,7 @@ svfloat64_t test_svnmad_n_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, f // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmad.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svnmad_n_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tDh( +// CPP-CHECK-LABEL: @_Z19test_svnmad_n_f16_mu10__SVBool_tu13__SVFloat16_tS0_Dh( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, half [[OP3:%.*]], i64 0 @@ -271,7 +271,7 @@ svfloat16_t test_svnmad_n_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, f // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmad.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svnmad_n_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tf( +// CPP-CHECK-LABEL: @_Z19test_svnmad_n_f32_mu10__SVBool_tu13__SVFloat32_tS0_f( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, float [[OP3:%.*]], i64 0 @@ -292,7 +292,7 @@ svfloat32_t test_svnmad_n_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, f // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmad.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svnmad_n_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_td( +// CPP-CHECK-LABEL: @_Z19test_svnmad_n_f64_mu10__SVBool_tu13__SVFloat64_tS0_d( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, double [[OP3:%.*]], i64 0 @@ -313,7 +313,7 @@ svfloat64_t test_svnmad_n_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, f // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.u.nxv8f16( [[TMP0]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svnmad_n_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tDh( +// CPP-CHECK-LABEL: @_Z19test_svnmad_n_f16_xu10__SVBool_tu13__SVFloat16_tS0_Dh( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, half [[OP3:%.*]], i64 0 @@ -334,7 +334,7 @@ svfloat16_t test_svnmad_n_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, f // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.u.nxv4f32( [[TMP0]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svnmad_n_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tf( +// CPP-CHECK-LABEL: @_Z19test_svnmad_n_f32_xu10__SVBool_tu13__SVFloat32_tS0_f( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, float [[OP3:%.*]], i64 0 @@ -355,7 +355,7 @@ svfloat32_t test_svnmad_n_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, f // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.u.nxv2f64( [[TMP0]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svnmad_n_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_td( +// CPP-CHECK-LABEL: @_Z19test_svnmad_n_f64_xu10__SVBool_tu13__SVFloat64_tS0_d( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, double [[OP3:%.*]], i64 0 diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmla.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmla.c index c9577a9aa7577..61df59c16da3c 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmla.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmla.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fnmla.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svnmla_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svnmla_f16_zu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -40,7 +40,7 @@ svfloat16_t test_svnmla_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svf // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fnmla.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svnmla_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svnmla_f32_zu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -59,7 +59,7 @@ svfloat32_t test_svnmla_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svf // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fnmla.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svnmla_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svnmla_f64_zu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -77,7 +77,7 @@ svfloat64_t test_svnmla_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svnmla_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svnmla_f16_mu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -94,7 +94,7 @@ svfloat16_t test_svnmla_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svnmla_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svnmla_f32_mu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -111,7 +111,7 @@ svfloat32_t test_svnmla_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svnmla_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svnmla_f64_mu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -128,7 +128,7 @@ svfloat64_t test_svnmla_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svnmla_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svnmla_f16_xu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -145,7 +145,7 @@ svfloat16_t test_svnmla_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svnmla_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svnmla_f32_xu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -162,7 +162,7 @@ svfloat32_t test_svnmla_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svnmla_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svnmla_f64_xu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -182,7 +182,7 @@ svfloat64_t test_svnmla_f64_x(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svf // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fnmla.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z19test_svnmla_n_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tDh( +// CPP-CHECK-LABEL: @_Z19test_svnmla_n_f16_zu10__SVBool_tu13__SVFloat16_tS0_Dh( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, half [[OP3:%.*]], i64 0 @@ -205,7 +205,7 @@ svfloat16_t test_svnmla_n_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, f // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fnmla.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z19test_svnmla_n_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tf( +// CPP-CHECK-LABEL: @_Z19test_svnmla_n_f32_zu10__SVBool_tu13__SVFloat32_tS0_f( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, float [[OP3:%.*]], i64 0 @@ -228,7 +228,7 @@ svfloat32_t test_svnmla_n_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, f // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fnmla.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z19test_svnmla_n_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_td( +// CPP-CHECK-LABEL: @_Z19test_svnmla_n_f64_zu10__SVBool_tu13__SVFloat64_tS0_d( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, double [[OP3:%.*]], i64 0 @@ -250,7 +250,7 @@ svfloat64_t test_svnmla_n_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, f // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svnmla_n_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tDh( +// CPP-CHECK-LABEL: @_Z19test_svnmla_n_f16_mu10__SVBool_tu13__SVFloat16_tS0_Dh( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, half [[OP3:%.*]], i64 0 @@ -271,7 +271,7 @@ svfloat16_t test_svnmla_n_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, f // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svnmla_n_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tf( +// CPP-CHECK-LABEL: @_Z19test_svnmla_n_f32_mu10__SVBool_tu13__SVFloat32_tS0_f( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, float [[OP3:%.*]], i64 0 @@ -292,7 +292,7 @@ svfloat32_t test_svnmla_n_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, f // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svnmla_n_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_td( +// CPP-CHECK-LABEL: @_Z19test_svnmla_n_f64_mu10__SVBool_tu13__SVFloat64_tS0_d( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, double [[OP3:%.*]], i64 0 @@ -313,7 +313,7 @@ svfloat64_t test_svnmla_n_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, f // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svnmla_n_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tDh( +// CPP-CHECK-LABEL: @_Z19test_svnmla_n_f16_xu10__SVBool_tu13__SVFloat16_tS0_Dh( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, half [[OP3:%.*]], i64 0 @@ -334,7 +334,7 @@ svfloat16_t test_svnmla_n_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, f // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svnmla_n_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tf( +// CPP-CHECK-LABEL: @_Z19test_svnmla_n_f32_xu10__SVBool_tu13__SVFloat32_tS0_f( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, float [[OP3:%.*]], i64 0 @@ -355,7 +355,7 @@ svfloat32_t test_svnmla_n_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, f // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmla.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svnmla_n_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_td( +// CPP-CHECK-LABEL: @_Z19test_svnmla_n_f64_xu10__SVBool_tu13__SVFloat64_tS0_d( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, double [[OP3:%.*]], i64 0 diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmls.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmls.c index dd8281e1672a7..8d5e936bfae6c 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmls.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmls.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fnmls.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svnmls_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svnmls_f16_zu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -40,7 +40,7 @@ svfloat16_t test_svnmls_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svf // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fnmls.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svnmls_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svnmls_f32_zu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -59,7 +59,7 @@ svfloat32_t test_svnmls_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svf // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fnmls.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svnmls_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svnmls_f64_zu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -77,7 +77,7 @@ svfloat64_t test_svnmls_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svnmls_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svnmls_f16_mu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -94,7 +94,7 @@ svfloat16_t test_svnmls_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svnmls_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svnmls_f32_mu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -111,7 +111,7 @@ svfloat32_t test_svnmls_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svnmls_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svnmls_f64_mu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -128,7 +128,7 @@ svfloat64_t test_svnmls_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svnmls_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svnmls_f16_xu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -145,7 +145,7 @@ svfloat16_t test_svnmls_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svnmls_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svnmls_f32_xu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -162,7 +162,7 @@ svfloat32_t test_svnmls_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svnmls_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svnmls_f64_xu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -182,7 +182,7 @@ svfloat64_t test_svnmls_f64_x(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svf // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fnmls.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z19test_svnmls_n_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tDh( +// CPP-CHECK-LABEL: @_Z19test_svnmls_n_f16_zu10__SVBool_tu13__SVFloat16_tS0_Dh( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, half [[OP3:%.*]], i64 0 @@ -205,7 +205,7 @@ svfloat16_t test_svnmls_n_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, f // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fnmls.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z19test_svnmls_n_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tf( +// CPP-CHECK-LABEL: @_Z19test_svnmls_n_f32_zu10__SVBool_tu13__SVFloat32_tS0_f( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, float [[OP3:%.*]], i64 0 @@ -228,7 +228,7 @@ svfloat32_t test_svnmls_n_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, f // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fnmls.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z19test_svnmls_n_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_td( +// CPP-CHECK-LABEL: @_Z19test_svnmls_n_f64_zu10__SVBool_tu13__SVFloat64_tS0_d( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, double [[OP3:%.*]], i64 0 @@ -250,7 +250,7 @@ svfloat64_t test_svnmls_n_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, f // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svnmls_n_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tDh( +// CPP-CHECK-LABEL: @_Z19test_svnmls_n_f16_mu10__SVBool_tu13__SVFloat16_tS0_Dh( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, half [[OP3:%.*]], i64 0 @@ -271,7 +271,7 @@ svfloat16_t test_svnmls_n_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, f // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svnmls_n_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tf( +// CPP-CHECK-LABEL: @_Z19test_svnmls_n_f32_mu10__SVBool_tu13__SVFloat32_tS0_f( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, float [[OP3:%.*]], i64 0 @@ -292,7 +292,7 @@ svfloat32_t test_svnmls_n_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, f // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svnmls_n_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_td( +// CPP-CHECK-LABEL: @_Z19test_svnmls_n_f64_mu10__SVBool_tu13__SVFloat64_tS0_d( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, double [[OP3:%.*]], i64 0 @@ -313,7 +313,7 @@ svfloat64_t test_svnmls_n_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, f // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svnmls_n_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tDh( +// CPP-CHECK-LABEL: @_Z19test_svnmls_n_f16_xu10__SVBool_tu13__SVFloat16_tS0_Dh( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, half [[OP3:%.*]], i64 0 @@ -334,7 +334,7 @@ svfloat16_t test_svnmls_n_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, f // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svnmls_n_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tf( +// CPP-CHECK-LABEL: @_Z19test_svnmls_n_f32_xu10__SVBool_tu13__SVFloat32_tS0_f( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, float [[OP3:%.*]], i64 0 @@ -355,7 +355,7 @@ svfloat32_t test_svnmls_n_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, f // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svnmls_n_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_td( +// CPP-CHECK-LABEL: @_Z19test_svnmls_n_f64_xu10__SVBool_tu13__SVFloat64_tS0_d( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, double [[OP3:%.*]], i64 0 diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmsb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmsb.c index 7fa52d52d2b65..dda7c11131086 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmsb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmsb.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fnmsb.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svnmsb_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svnmsb_f16_zu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -40,7 +40,7 @@ svfloat16_t test_svnmsb_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svf // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fnmsb.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svnmsb_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svnmsb_f32_zu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -59,7 +59,7 @@ svfloat32_t test_svnmsb_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svf // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fnmsb.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svnmsb_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svnmsb_f64_zu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -77,7 +77,7 @@ svfloat64_t test_svnmsb_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmsb.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svnmsb_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svnmsb_f16_mu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmsb.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -94,7 +94,7 @@ svfloat16_t test_svnmsb_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmsb.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svnmsb_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svnmsb_f32_mu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmsb.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -111,7 +111,7 @@ svfloat32_t test_svnmsb_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmsb.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svnmsb_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svnmsb_f64_mu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmsb.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) @@ -128,7 +128,7 @@ svfloat64_t test_svnmsb_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.u.nxv8f16( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svnmsb_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svnmsb_f16_xu10__SVBool_tu13__SVFloat16_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.u.nxv8f16( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) @@ -145,7 +145,7 @@ svfloat16_t test_svnmsb_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.u.nxv4f32( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svnmsb_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svnmsb_f32_xu10__SVBool_tu13__SVFloat32_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.u.nxv4f32( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) @@ -162,7 +162,7 @@ svfloat32_t test_svnmsb_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svf // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.u.nxv2f64( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svnmsb_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svnmsb_f64_xu10__SVBool_tu13__SVFloat64_tS0_S0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.u.nxv2f64( [[TMP0]], [[OP3:%.*]], [[OP2:%.*]], [[OP1:%.*]]) @@ -182,7 +182,7 @@ svfloat64_t test_svnmsb_f64_x(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svf // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fnmsb.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z19test_svnmsb_n_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tDh( +// CPP-CHECK-LABEL: @_Z19test_svnmsb_n_f16_zu10__SVBool_tu13__SVFloat16_tS0_Dh( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, half [[OP3:%.*]], i64 0 @@ -205,7 +205,7 @@ svfloat16_t test_svnmsb_n_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, f // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fnmsb.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z19test_svnmsb_n_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tf( +// CPP-CHECK-LABEL: @_Z19test_svnmsb_n_f32_zu10__SVBool_tu13__SVFloat32_tS0_f( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, float [[OP3:%.*]], i64 0 @@ -228,7 +228,7 @@ svfloat32_t test_svnmsb_n_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, f // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fnmsb.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z19test_svnmsb_n_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_td( +// CPP-CHECK-LABEL: @_Z19test_svnmsb_n_f64_zu10__SVBool_tu13__SVFloat64_tS0_d( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, double [[OP3:%.*]], i64 0 @@ -250,7 +250,7 @@ svfloat64_t test_svnmsb_n_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, f // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmsb.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svnmsb_n_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tDh( +// CPP-CHECK-LABEL: @_Z19test_svnmsb_n_f16_mu10__SVBool_tu13__SVFloat16_tS0_Dh( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, half [[OP3:%.*]], i64 0 @@ -271,7 +271,7 @@ svfloat16_t test_svnmsb_n_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, f // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmsb.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svnmsb_n_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tf( +// CPP-CHECK-LABEL: @_Z19test_svnmsb_n_f32_mu10__SVBool_tu13__SVFloat32_tS0_f( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, float [[OP3:%.*]], i64 0 @@ -292,7 +292,7 @@ svfloat32_t test_svnmsb_n_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, f // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmsb.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svnmsb_n_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_td( +// CPP-CHECK-LABEL: @_Z19test_svnmsb_n_f64_mu10__SVBool_tu13__SVFloat64_tS0_d( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, double [[OP3:%.*]], i64 0 @@ -313,7 +313,7 @@ svfloat64_t test_svnmsb_n_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, f // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.u.nxv8f16( [[TMP0]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svnmsb_n_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_tDh( +// CPP-CHECK-LABEL: @_Z19test_svnmsb_n_f16_xu10__SVBool_tu13__SVFloat16_tS0_Dh( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, half [[OP3:%.*]], i64 0 @@ -334,7 +334,7 @@ svfloat16_t test_svnmsb_n_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, f // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.u.nxv4f32( [[TMP0]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svnmsb_n_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_tf( +// CPP-CHECK-LABEL: @_Z19test_svnmsb_n_f32_xu10__SVBool_tu13__SVFloat32_tS0_f( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, float [[OP3:%.*]], i64 0 @@ -355,7 +355,7 @@ svfloat32_t test_svnmsb_n_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, f // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fnmls.u.nxv2f64( [[TMP0]], [[DOTSPLAT]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svnmsb_n_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_td( +// CPP-CHECK-LABEL: @_Z19test_svnmsb_n_f64_xu10__SVBool_tu13__SVFloat64_tS0_d( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, double [[OP3:%.*]], i64 0 diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nor.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nor.c index 951e1b9c25ec8..a34cfef495565 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nor.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nor.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nor.z.nxv16i1( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svnor_b_zu10__SVBool_tu10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z14test_svnor_b_zu10__SVBool_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nor.z.nxv16i1( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_not.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_not.c index 02a498edc2112..9ce1fa679be83 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_not.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_not.c @@ -151,7 +151,7 @@ svuint64_t test_svnot_u64_z(svbool_t pg, svuint64_t op) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.not.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svnot_s8_mu10__SVInt8_tu10__SVBool_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svnot_s8_mu10__SVInt8_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.not.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -167,7 +167,7 @@ svint8_t test_svnot_s8_m(svint8_t inactive, svbool_t pg, svint8_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.not.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svnot_s16_mu11__SVInt16_tu10__SVBool_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svnot_s16_mu11__SVInt16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.not.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -184,7 +184,7 @@ svint16_t test_svnot_s16_m(svint16_t inactive, svbool_t pg, svint16_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.not.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svnot_s32_mu11__SVInt32_tu10__SVBool_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svnot_s32_mu11__SVInt32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.not.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -201,7 +201,7 @@ svint32_t test_svnot_s32_m(svint32_t inactive, svbool_t pg, svint32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.not.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svnot_s64_mu11__SVInt64_tu10__SVBool_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svnot_s64_mu11__SVInt64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.not.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -217,7 +217,7 @@ svint64_t test_svnot_s64_m(svint64_t inactive, svbool_t pg, svint64_t op) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.not.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svnot_u8_mu11__SVUint8_tu10__SVBool_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svnot_u8_mu11__SVUint8_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.not.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -233,7 +233,7 @@ svuint8_t test_svnot_u8_m(svuint8_t inactive, svbool_t pg, svuint8_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.not.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svnot_u16_mu12__SVUint16_tu10__SVBool_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svnot_u16_mu12__SVUint16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.not.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -250,7 +250,7 @@ svuint16_t test_svnot_u16_m(svuint16_t inactive, svbool_t pg, svuint16_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.not.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svnot_u32_mu12__SVUint32_tu10__SVBool_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svnot_u32_mu12__SVUint32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.not.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -267,7 +267,7 @@ svuint32_t test_svnot_u32_m(svuint32_t inactive, svbool_t pg, svuint32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.not.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svnot_u64_mu12__SVUint64_tu10__SVBool_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svnot_u64_mu12__SVUint64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.not.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -415,7 +415,7 @@ svuint64_t test_svnot_u64_x(svbool_t pg, svuint64_t op) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.z.nxv16i1( [[PG:%.*]], [[OP:%.*]], [[PG]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svnot_b_zu10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z14test_svnot_b_zu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor.z.nxv16i1( [[PG:%.*]], [[OP:%.*]], [[PG]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orn.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orn.c index c79c6d713552c..66faa65b0d3b9 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orn.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orn.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orn.z.nxv16i1( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svorn_b_zu10__SVBool_tu10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z14test_svorn_b_zu10__SVBool_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orn.z.nxv16i1( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orr.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orr.c index 2aec267c43695..6bbab408efcd3 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orr.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orr.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svorr_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svorr_s8_zu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -38,7 +38,7 @@ svint8_t test_svorr_s8_z(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.orr.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svorr_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svorr_s16_zu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -57,7 +57,7 @@ svint16_t test_svorr_s16_z(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.orr.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svorr_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svorr_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -76,7 +76,7 @@ svint32_t test_svorr_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.orr.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svorr_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svorr_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -94,7 +94,7 @@ svint64_t test_svorr_s64_z(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svorr_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svorr_u8_zu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -112,7 +112,7 @@ svuint8_t test_svorr_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.orr.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svorr_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svorr_u16_zu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -131,7 +131,7 @@ svuint16_t test_svorr_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.orr.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svorr_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svorr_u32_zu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -150,7 +150,7 @@ svuint32_t test_svorr_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.orr.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svorr_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svorr_u64_zu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -167,7 +167,7 @@ svuint64_t test_svorr_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svorr_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svorr_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -183,7 +183,7 @@ svint8_t test_svorr_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svorr_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svorr_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -200,7 +200,7 @@ svint16_t test_svorr_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svorr_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svorr_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -217,7 +217,7 @@ svint32_t test_svorr_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svorr_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svorr_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -233,7 +233,7 @@ svint64_t test_svorr_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svorr_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svorr_u8_mu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -249,7 +249,7 @@ svuint8_t test_svorr_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svorr_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svorr_u16_mu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -266,7 +266,7 @@ svuint16_t test_svorr_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svorr_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svorr_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -283,7 +283,7 @@ svuint32_t test_svorr_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svorr_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svorr_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -299,7 +299,7 @@ svuint64_t test_svorr_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svorr_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svorr_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -315,7 +315,7 @@ svint8_t test_svorr_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svorr_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svorr_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -332,7 +332,7 @@ svint16_t test_svorr_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svorr_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svorr_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -349,7 +349,7 @@ svint32_t test_svorr_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svorr_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svorr_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -365,7 +365,7 @@ svint64_t test_svorr_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svorr_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svorr_u8_xu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -381,7 +381,7 @@ svuint8_t test_svorr_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svorr_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svorr_u16_xu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -398,7 +398,7 @@ svuint16_t test_svorr_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svorr_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svorr_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -415,7 +415,7 @@ svuint32_t test_svorr_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svorr_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svorr_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.orr.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -939,7 +939,7 @@ svuint64_t test_svorr_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.z.nxv16i1( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svorr_b_zu10__SVBool_tu10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z14test_svorr_b_zu10__SVBool_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.orr.z.nxv16i1( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pfirst.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pfirst.c index e1e20f63bb0d1..e39858c93c508 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pfirst.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pfirst.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.pfirst.nxv16i1( [[PG:%.*]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svpfirst_bu10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svpfirst_bu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.pfirst.nxv16i1( [[PG:%.*]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pnext.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pnext.c index e5c030e98aa8d..1a08ea38c6fc8 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pnext.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pnext.c @@ -10,7 +10,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.pnext.nxv16i1( [[PG:%.*]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svpnext_b8u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svpnext_b8u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.pnext.nxv16i1( [[PG:%.*]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -28,7 +28,7 @@ svbool_t test_svpnext_b8(svbool_t pg, svbool_t op) // CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP2]]) // CHECK-NEXT: ret [[TMP3]] // -// CPP-CHECK-LABEL: @_Z16test_svpnext_b16u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z16test_svpnext_b16u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[OP:%.*]]) @@ -49,7 +49,7 @@ svbool_t test_svpnext_b16(svbool_t pg, svbool_t op) // CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( [[TMP2]]) // CHECK-NEXT: ret [[TMP3]] // -// CPP-CHECK-LABEL: @_Z16test_svpnext_b32u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z16test_svpnext_b32u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[OP:%.*]]) @@ -70,7 +70,7 @@ svbool_t test_svpnext_b32(svbool_t pg, svbool_t op) // CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( [[TMP2]]) // CHECK-NEXT: ret [[TMP3]] // -// CPP-CHECK-LABEL: @_Z16test_svpnext_b64u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z16test_svpnext_b64u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ptest.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ptest.c index 94e2e19f0bcb5..7045bd0fd34b6 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ptest.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ptest.c @@ -10,7 +10,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1( [[PG:%.*]], [[OP:%.*]]) // CHECK-NEXT: ret i1 [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svptest_anyu10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z16test_svptest_anyu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1( [[PG:%.*]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret i1 [[TMP0]] @@ -25,7 +25,7 @@ bool test_svptest_any(svbool_t pg, svbool_t op) // CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.aarch64.sve.ptest.first.nxv16i1( [[PG:%.*]], [[OP:%.*]]) // CHECK-NEXT: ret i1 [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svptest_firstu10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z18test_svptest_firstu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.aarch64.sve.ptest.first.nxv16i1( [[PG:%.*]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret i1 [[TMP0]] @@ -40,7 +40,7 @@ bool test_svptest_first(svbool_t pg, svbool_t op) // CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.aarch64.sve.ptest.last.nxv16i1( [[PG:%.*]], [[OP:%.*]]) // CHECK-NEXT: ret i1 [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svptest_lastu10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z17test_svptest_lastu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.aarch64.sve.ptest.last.nxv16i1( [[PG:%.*]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret i1 [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qadd.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qadd.c index 80e6038e22c25..fc5f445b0e9a6 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qadd.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qadd.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqadd.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svqadd_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z14test_svqadd_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqadd.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svint8_t test_svqadd_s8(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqadd.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svqadd_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z15test_svqadd_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqadd.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -49,7 +49,7 @@ svint16_t test_svqadd_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqadd.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svqadd_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z15test_svqadd_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqadd.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -64,7 +64,7 @@ svint32_t test_svqadd_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqadd.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svqadd_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z15test_svqadd_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqadd.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -79,7 +79,7 @@ svint64_t test_svqadd_s64(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqadd.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svqadd_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svqadd_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqadd.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -94,7 +94,7 @@ svuint8_t test_svqadd_u8(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqadd.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svqadd_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z15test_svqadd_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqadd.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -109,7 +109,7 @@ svuint16_t test_svqadd_u16(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqadd.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svqadd_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z15test_svqadd_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqadd.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -124,7 +124,7 @@ svuint32_t test_svqadd_u32(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqadd.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svqadd_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z15test_svqadd_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqadd.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qsub.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qsub.c index 8174e70bfee2a..21802fe5997e8 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qsub.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qsub.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqsub.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svqsub_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z14test_svqsub_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqsub.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svint8_t test_svqsub_s8(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqsub.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svqsub_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z15test_svqsub_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqsub.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -49,7 +49,7 @@ svint16_t test_svqsub_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqsub.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svqsub_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z15test_svqsub_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqsub.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -64,7 +64,7 @@ svint32_t test_svqsub_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqsub.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svqsub_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z15test_svqsub_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqsub.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -79,7 +79,7 @@ svint64_t test_svqsub_s64(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqsub.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svqsub_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svqsub_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqsub.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -94,7 +94,7 @@ svuint8_t test_svqsub_u8(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqsub.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svqsub_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z15test_svqsub_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqsub.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -109,7 +109,7 @@ svuint16_t test_svqsub_u16(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqsub.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svqsub_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z15test_svqsub_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqsub.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -124,7 +124,7 @@ svuint32_t test_svqsub_u32(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqsub.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svqsub_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z15test_svqsub_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqsub.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rbit.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rbit.c index bf830fac8b067..0c7bfc71bd511 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rbit.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rbit.c @@ -151,7 +151,7 @@ svuint64_t test_svrbit_u64_z(svbool_t pg, svuint64_t op) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rbit.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svrbit_s8_mu10__SVInt8_tu10__SVBool_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svrbit_s8_mu10__SVInt8_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rbit.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -167,7 +167,7 @@ svint8_t test_svrbit_s8_m(svint8_t inactive, svbool_t pg, svint8_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.rbit.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrbit_s16_mu11__SVInt16_tu10__SVBool_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svrbit_s16_mu11__SVInt16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.rbit.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -184,7 +184,7 @@ svint16_t test_svrbit_s16_m(svint16_t inactive, svbool_t pg, svint16_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.rbit.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrbit_s32_mu11__SVInt32_tu10__SVBool_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svrbit_s32_mu11__SVInt32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.rbit.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -201,7 +201,7 @@ svint32_t test_svrbit_s32_m(svint32_t inactive, svbool_t pg, svint32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.rbit.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrbit_s64_mu11__SVInt64_tu10__SVBool_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svrbit_s64_mu11__SVInt64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.rbit.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -217,7 +217,7 @@ svint64_t test_svrbit_s64_m(svint64_t inactive, svbool_t pg, svint64_t op) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rbit.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svrbit_u8_mu11__SVUint8_tu10__SVBool_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svrbit_u8_mu11__SVUint8_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rbit.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -233,7 +233,7 @@ svuint8_t test_svrbit_u8_m(svuint8_t inactive, svbool_t pg, svuint8_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.rbit.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrbit_u16_mu12__SVUint16_tu10__SVBool_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svrbit_u16_mu12__SVUint16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.rbit.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -250,7 +250,7 @@ svuint16_t test_svrbit_u16_m(svuint16_t inactive, svbool_t pg, svuint16_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.rbit.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrbit_u32_mu12__SVUint32_tu10__SVBool_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svrbit_u32_mu12__SVUint32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.rbit.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -267,7 +267,7 @@ svuint32_t test_svrbit_u32_m(svuint32_t inactive, svbool_t pg, svuint32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.rbit.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrbit_u64_mu12__SVUint64_tu10__SVBool_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svrbit_u64_mu12__SVUint64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.rbit.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_recps.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_recps.c index a61ad8b221729..674a2ecf672b4 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_recps.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_recps.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.frecps.x.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svrecps_f16u13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svrecps_f16u13__SVFloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.frecps.x.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svfloat16_t test_svrecps_f16(svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.frecps.x.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svrecps_f32u13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svrecps_f32u13__SVFloat32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.frecps.x.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -49,7 +49,7 @@ svfloat32_t test_svrecps_f32(svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.frecps.x.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svrecps_f64u13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svrecps_f64u13__SVFloat64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.frecps.x.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_recpx.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_recpx.c index 18fcbf4a19f6a..0df7d7ae410d2 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_recpx.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_recpx.c @@ -71,7 +71,7 @@ svfloat64_t test_svrecpx_f64_z(svbool_t pg, svfloat64_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frecpx.nxv8f16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrecpx_f16_mu13__SVFloat16_tu10__SVBool_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svrecpx_f16_mu13__SVFloat16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frecpx.nxv8f16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -88,7 +88,7 @@ svfloat16_t test_svrecpx_f16_m(svfloat16_t inactive, svbool_t pg, svfloat16_t op // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frecpx.nxv4f32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrecpx_f32_mu13__SVFloat32_tu10__SVBool_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z18test_svrecpx_f32_mu13__SVFloat32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frecpx.nxv4f32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -105,7 +105,7 @@ svfloat32_t test_svrecpx_f32_m(svfloat32_t inactive, svbool_t pg, svfloat32_t op // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frecpx.nxv2f64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrecpx_f64_mu13__SVFloat64_tu10__SVBool_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z18test_svrecpx_f64_mu13__SVFloat64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frecpx.nxv2f64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret-bfloat.c index 489434bea2691..c99948eb706ba 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret-bfloat.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = bitcast [[OP:%.*]] to // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z26test_svreinterpret_s8_bf16u14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z26test_svreinterpret_s8_bf16u14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = bitcast [[OP:%.*]] to // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svreinterpret_s8_bf16(svbfloat16_t op) { // CHECK-NEXT: [[TMP0:%.*]] = bitcast [[OP:%.*]] to // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z27test_svreinterpret_s16_bf16u14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z27test_svreinterpret_s16_bf16u14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = bitcast [[OP:%.*]] to // CPP-CHECK-NEXT: ret [[TMP0]] @@ -49,7 +49,7 @@ svint16_t test_svreinterpret_s16_bf16(svbfloat16_t op) { // CHECK-NEXT: [[TMP0:%.*]] = bitcast [[OP:%.*]] to // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z27test_svreinterpret_s32_bf16u14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z27test_svreinterpret_s32_bf16u14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = bitcast [[OP:%.*]] to // CPP-CHECK-NEXT: ret [[TMP0]] @@ -62,7 +62,7 @@ svint32_t test_svreinterpret_s32_bf16(svbfloat16_t op) { // CHECK-NEXT: [[TMP0:%.*]] = bitcast [[OP:%.*]] to // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z27test_svreinterpret_s64_bf16u14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z27test_svreinterpret_s64_bf16u14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = bitcast [[OP:%.*]] to // CPP-CHECK-NEXT: ret [[TMP0]] @@ -76,7 +76,7 @@ svint64_t test_svreinterpret_s64_bf16(svbfloat16_t op) { // CHECK-NEXT: [[TMP0:%.*]] = bitcast [[OP:%.*]] to // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z26test_svreinterpret_u8_bf16u14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z26test_svreinterpret_u8_bf16u14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = bitcast [[OP:%.*]] to // CPP-CHECK-NEXT: ret [[TMP0]] @@ -90,7 +90,7 @@ svuint8_t test_svreinterpret_u8_bf16(svbfloat16_t op) { // CHECK-NEXT: [[TMP0:%.*]] = bitcast [[OP:%.*]] to // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z27test_svreinterpret_u16_bf16u14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z27test_svreinterpret_u16_bf16u14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = bitcast [[OP:%.*]] to // CPP-CHECK-NEXT: ret [[TMP0]] @@ -104,7 +104,7 @@ svuint16_t test_svreinterpret_u16_bf16(svbfloat16_t op) { // CHECK-NEXT: [[TMP0:%.*]] = bitcast [[OP:%.*]] to // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z27test_svreinterpret_u32_bf16u14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z27test_svreinterpret_u32_bf16u14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = bitcast [[OP:%.*]] to // CPP-CHECK-NEXT: ret [[TMP0]] @@ -118,7 +118,7 @@ svuint32_t test_svreinterpret_u32_bf16(svbfloat16_t op) { // CHECK-NEXT: [[TMP0:%.*]] = bitcast [[OP:%.*]] to // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z27test_svreinterpret_u64_bf16u14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z27test_svreinterpret_u64_bf16u14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = bitcast [[OP:%.*]] to // CPP-CHECK-NEXT: ret [[TMP0]] @@ -243,7 +243,7 @@ svbfloat16_t test_svreinterpret_bf16_u64(svuint64_t op) { // CHECK-NEXT: entry: // CHECK-NEXT: ret [[OP:%.*]] // -// CPP-CHECK-LABEL: @_Z28test_svreinterpret_bf16_bf16u14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z28test_svreinterpret_bf16_bf16u14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: ret [[OP:%.*]] // @@ -298,7 +298,7 @@ svbfloat16_t test_svreinterpret_bf16_f64(svfloat64_t op) { // CHECK-NEXT: [[TMP0:%.*]] = bitcast [[OP:%.*]] to // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z27test_svreinterpret_f32_bf16u14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z27test_svreinterpret_f32_bf16u14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = bitcast [[OP:%.*]] to // CPP-CHECK-NEXT: ret [[TMP0]] @@ -312,7 +312,7 @@ svfloat32_t test_svreinterpret_f32_bf16(svbfloat16_t op) { // CHECK-NEXT: [[TMP0:%.*]] = bitcast [[OP:%.*]] to // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z27test_svreinterpret_f16_bf16u14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z27test_svreinterpret_f16_bf16u14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = bitcast [[OP:%.*]] to // CPP-CHECK-NEXT: ret [[TMP0]] @@ -326,7 +326,7 @@ svfloat16_t test_svreinterpret_f16_bf16(svbfloat16_t op) { // CHECK-NEXT: [[TMP0:%.*]] = bitcast [[OP:%.*]] to // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z27test_svreinterpret_f64_bf16u14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z27test_svreinterpret_f64_bf16u14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = bitcast [[OP:%.*]] to // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rev-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rev-bfloat.c index 39487de62fd53..f00b7b0bddbb9 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rev-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rev-bfloat.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rev.nxv8bf16( [[OP:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svrev_bf16u14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z15test_svrev_bf16u14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rev.nxv8bf16( [[OP:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revb.c index b9cfb91620612..f580581548e0b 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revb.c @@ -122,7 +122,7 @@ svuint64_t test_svrevb_u64_z(svbool_t pg, svuint64_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revb.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrevb_s16_mu11__SVInt16_tu10__SVBool_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svrevb_s16_mu11__SVInt16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revb.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -139,7 +139,7 @@ svint16_t test_svrevb_s16_m(svint16_t inactive, svbool_t pg, svint16_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revb.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrevb_s32_mu11__SVInt32_tu10__SVBool_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svrevb_s32_mu11__SVInt32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revb.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -156,7 +156,7 @@ svint32_t test_svrevb_s32_m(svint32_t inactive, svbool_t pg, svint32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revb.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrevb_s64_mu11__SVInt64_tu10__SVBool_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svrevb_s64_mu11__SVInt64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revb.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -173,7 +173,7 @@ svint64_t test_svrevb_s64_m(svint64_t inactive, svbool_t pg, svint64_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revb.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrevb_u16_mu12__SVUint16_tu10__SVBool_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svrevb_u16_mu12__SVUint16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revb.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -190,7 +190,7 @@ svuint16_t test_svrevb_u16_m(svuint16_t inactive, svbool_t pg, svuint16_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revb.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrevb_u32_mu12__SVUint32_tu10__SVBool_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svrevb_u32_mu12__SVUint32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revb.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -207,7 +207,7 @@ svuint32_t test_svrevb_u32_m(svuint32_t inactive, svbool_t pg, svuint32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revb.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrevb_u64_mu12__SVUint64_tu10__SVBool_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svrevb_u64_mu12__SVUint64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revb.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revh.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revh.c index ef8ab40fcd2f0..5b987f4372191 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revh.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revh.c @@ -88,7 +88,7 @@ svuint64_t test_svrevh_u64_z(svbool_t pg, svuint64_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revh.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrevh_s32_mu11__SVInt32_tu10__SVBool_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svrevh_s32_mu11__SVInt32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revh.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -105,7 +105,7 @@ svint32_t test_svrevh_s32_m(svint32_t inactive, svbool_t pg, svint32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revh.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrevh_s64_mu11__SVInt64_tu10__SVBool_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svrevh_s64_mu11__SVInt64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revh.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -122,7 +122,7 @@ svint64_t test_svrevh_s64_m(svint64_t inactive, svbool_t pg, svint64_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revh.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrevh_u32_mu12__SVUint32_tu10__SVBool_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svrevh_u32_mu12__SVUint32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revh.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -139,7 +139,7 @@ svuint32_t test_svrevh_u32_m(svuint32_t inactive, svbool_t pg, svuint32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revh.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrevh_u64_mu12__SVUint64_tu10__SVBool_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svrevh_u64_mu12__SVUint64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revh.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revw.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revw.c index 0099c3a96dbde..1052d461f5695 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revw.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revw.c @@ -54,7 +54,7 @@ svuint64_t test_svrevw_u64_z(svbool_t pg, svuint64_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revw.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrevw_s64_mu11__SVInt64_tu10__SVBool_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svrevw_s64_mu11__SVInt64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revw.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -71,7 +71,7 @@ svint64_t test_svrevw_s64_m(svint64_t inactive, svbool_t pg, svint64_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revw.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrevw_u64_mu12__SVUint64_tu10__SVBool_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svrevw_u64_mu12__SVUint64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revw.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rinta.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rinta.c index 48ea8f57be92f..3e13fdbe80464 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rinta.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rinta.c @@ -71,7 +71,7 @@ svfloat64_t test_svrinta_f64_z(svbool_t pg, svfloat64_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frinta.nxv8f16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrinta_f16_mu13__SVFloat16_tu10__SVBool_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svrinta_f16_mu13__SVFloat16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frinta.nxv8f16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -88,7 +88,7 @@ svfloat16_t test_svrinta_f16_m(svfloat16_t inactive, svbool_t pg, svfloat16_t op // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frinta.nxv4f32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrinta_f32_mu13__SVFloat32_tu10__SVBool_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z18test_svrinta_f32_mu13__SVFloat32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frinta.nxv4f32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -105,7 +105,7 @@ svfloat32_t test_svrinta_f32_m(svfloat32_t inactive, svbool_t pg, svfloat32_t op // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frinta.nxv2f64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrinta_f64_mu13__SVFloat64_tu10__SVBool_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z18test_svrinta_f64_mu13__SVFloat64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frinta.nxv2f64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rinti.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rinti.c index b618bfa1feac0..650c6290e9fc6 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rinti.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rinti.c @@ -71,7 +71,7 @@ svfloat64_t test_svrinti_f64_z(svbool_t pg, svfloat64_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frinti.nxv8f16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrinti_f16_mu13__SVFloat16_tu10__SVBool_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svrinti_f16_mu13__SVFloat16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frinti.nxv8f16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -88,7 +88,7 @@ svfloat16_t test_svrinti_f16_m(svfloat16_t inactive, svbool_t pg, svfloat16_t op // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frinti.nxv4f32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrinti_f32_mu13__SVFloat32_tu10__SVBool_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z18test_svrinti_f32_mu13__SVFloat32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frinti.nxv4f32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -105,7 +105,7 @@ svfloat32_t test_svrinti_f32_m(svfloat32_t inactive, svbool_t pg, svfloat32_t op // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frinti.nxv2f64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrinti_f64_mu13__SVFloat64_tu10__SVBool_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z18test_svrinti_f64_mu13__SVFloat64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frinti.nxv2f64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintm.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintm.c index 6c97ecd2a5428..9d3ac355f0609 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintm.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintm.c @@ -71,7 +71,7 @@ svfloat64_t test_svrintm_f64_z(svbool_t pg, svfloat64_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintm.nxv8f16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrintm_f16_mu13__SVFloat16_tu10__SVBool_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svrintm_f16_mu13__SVFloat16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintm.nxv8f16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -88,7 +88,7 @@ svfloat16_t test_svrintm_f16_m(svfloat16_t inactive, svbool_t pg, svfloat16_t op // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintm.nxv4f32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrintm_f32_mu13__SVFloat32_tu10__SVBool_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z18test_svrintm_f32_mu13__SVFloat32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintm.nxv4f32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -105,7 +105,7 @@ svfloat32_t test_svrintm_f32_m(svfloat32_t inactive, svbool_t pg, svfloat32_t op // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintm.nxv2f64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrintm_f64_mu13__SVFloat64_tu10__SVBool_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z18test_svrintm_f64_mu13__SVFloat64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintm.nxv2f64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintn.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintn.c index 4ab099c155601..7ea47d69cd3ca 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintn.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintn.c @@ -71,7 +71,7 @@ svfloat64_t test_svrintn_f64_z(svbool_t pg, svfloat64_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintn.nxv8f16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrintn_f16_mu13__SVFloat16_tu10__SVBool_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svrintn_f16_mu13__SVFloat16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintn.nxv8f16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -88,7 +88,7 @@ svfloat16_t test_svrintn_f16_m(svfloat16_t inactive, svbool_t pg, svfloat16_t op // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintn.nxv4f32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrintn_f32_mu13__SVFloat32_tu10__SVBool_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z18test_svrintn_f32_mu13__SVFloat32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintn.nxv4f32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -105,7 +105,7 @@ svfloat32_t test_svrintn_f32_m(svfloat32_t inactive, svbool_t pg, svfloat32_t op // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintn.nxv2f64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrintn_f64_mu13__SVFloat64_tu10__SVBool_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z18test_svrintn_f64_mu13__SVFloat64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintn.nxv2f64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintp.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintp.c index 390ebbbfe7b28..03780f67e36d7 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintp.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintp.c @@ -71,7 +71,7 @@ svfloat64_t test_svrintp_f64_z(svbool_t pg, svfloat64_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintp.nxv8f16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrintp_f16_mu13__SVFloat16_tu10__SVBool_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svrintp_f16_mu13__SVFloat16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintp.nxv8f16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -88,7 +88,7 @@ svfloat16_t test_svrintp_f16_m(svfloat16_t inactive, svbool_t pg, svfloat16_t op // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintp.nxv4f32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrintp_f32_mu13__SVFloat32_tu10__SVBool_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z18test_svrintp_f32_mu13__SVFloat32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintp.nxv4f32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -105,7 +105,7 @@ svfloat32_t test_svrintp_f32_m(svfloat32_t inactive, svbool_t pg, svfloat32_t op // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintp.nxv2f64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrintp_f64_mu13__SVFloat64_tu10__SVBool_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z18test_svrintp_f64_mu13__SVFloat64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintp.nxv2f64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintx.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintx.c index 02086b824f53e..60e11dd0ba57f 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintx.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintx.c @@ -71,7 +71,7 @@ svfloat64_t test_svrintx_f64_z(svbool_t pg, svfloat64_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintx.nxv8f16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrintx_f16_mu13__SVFloat16_tu10__SVBool_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svrintx_f16_mu13__SVFloat16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintx.nxv8f16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -88,7 +88,7 @@ svfloat16_t test_svrintx_f16_m(svfloat16_t inactive, svbool_t pg, svfloat16_t op // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintx.nxv4f32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrintx_f32_mu13__SVFloat32_tu10__SVBool_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z18test_svrintx_f32_mu13__SVFloat32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintx.nxv4f32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -105,7 +105,7 @@ svfloat32_t test_svrintx_f32_m(svfloat32_t inactive, svbool_t pg, svfloat32_t op // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintx.nxv2f64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrintx_f64_mu13__SVFloat64_tu10__SVBool_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z18test_svrintx_f64_mu13__SVFloat64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintx.nxv2f64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintz.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintz.c index 07667ab682ac7..104254d807023 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintz.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintz.c @@ -71,7 +71,7 @@ svfloat64_t test_svrintz_f64_z(svbool_t pg, svfloat64_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintz.nxv8f16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrintz_f16_mu13__SVFloat16_tu10__SVBool_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svrintz_f16_mu13__SVFloat16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintz.nxv8f16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -88,7 +88,7 @@ svfloat16_t test_svrintz_f16_m(svfloat16_t inactive, svbool_t pg, svfloat16_t op // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintz.nxv4f32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrintz_f32_mu13__SVFloat32_tu10__SVBool_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z18test_svrintz_f32_mu13__SVFloat32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintz.nxv4f32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -105,7 +105,7 @@ svfloat32_t test_svrintz_f32_m(svfloat32_t inactive, svbool_t pg, svfloat32_t op // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintz.nxv2f64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrintz_f64_mu13__SVFloat64_tu10__SVBool_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z18test_svrintz_f64_mu13__SVFloat64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.frintz.nxv2f64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rsqrts.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rsqrts.c index 149d686dd1cc2..465159038f778 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rsqrts.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rsqrts.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.frsqrts.x.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svrsqrts_f16u13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svrsqrts_f16u13__SVFloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.frsqrts.x.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svfloat16_t test_svrsqrts_f16(svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.frsqrts.x.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svrsqrts_f32u13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svrsqrts_f32u13__SVFloat32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.frsqrts.x.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -49,7 +49,7 @@ svfloat32_t test_svrsqrts_f32(svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.frsqrts.x.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svrsqrts_f64u13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svrsqrts_f64u13__SVFloat64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.frsqrts.x.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel-bfloat.c index ea5d6c97a3916..409b39d238317 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel-bfloat.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], [[OP2:%.*]] // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svsel_bf16u10__SVBool_tu14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z15test_svsel_bf16u10__SVBool_tu14__SVBfloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], [[OP2:%.*]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c index ee29fe8a026d2..5ce8c76d8525a 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]] // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z13test_svsel_s8u10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z13test_svsel_s8u10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]] // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svsel_s8(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], [[OP2:%.*]] // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z14test_svsel_s16u10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z14test_svsel_s16u10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], [[OP2:%.*]] @@ -52,7 +52,7 @@ svint16_t test_svsel_s16(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], [[OP2:%.*]] // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z14test_svsel_s32u10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z14test_svsel_s32u10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], [[OP2:%.*]] @@ -69,7 +69,7 @@ svint32_t test_svsel_s32(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], [[OP2:%.*]] // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z14test_svsel_s64u10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z14test_svsel_s64u10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], [[OP2:%.*]] @@ -85,7 +85,7 @@ svint64_t test_svsel_s64(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]] // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z13test_svsel_u8u10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z13test_svsel_u8u10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]] // CPP-CHECK-NEXT: ret [[TMP0]] @@ -101,7 +101,7 @@ svuint8_t test_svsel_u8(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], [[OP2:%.*]] // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z14test_svsel_u16u10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z14test_svsel_u16u10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], [[OP2:%.*]] @@ -118,7 +118,7 @@ svuint16_t test_svsel_u16(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], [[OP2:%.*]] // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z14test_svsel_u32u10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z14test_svsel_u32u10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], [[OP2:%.*]] @@ -135,7 +135,7 @@ svuint32_t test_svsel_u32(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], [[OP2:%.*]] // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z14test_svsel_u64u10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z14test_svsel_u64u10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], [[OP2:%.*]] @@ -152,7 +152,7 @@ svuint64_t test_svsel_u64(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], [[OP2:%.*]] // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z14test_svsel_f16u10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z14test_svsel_f16u10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], [[OP2:%.*]] @@ -169,7 +169,7 @@ svfloat16_t test_svsel_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], [[OP2:%.*]] // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z14test_svsel_f32u10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z14test_svsel_f32u10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], [[OP2:%.*]] @@ -186,7 +186,7 @@ svfloat32_t test_svsel_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], [[OP2:%.*]] // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z14test_svsel_f64u10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z14test_svsel_f64u10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], [[OP2:%.*]] @@ -202,7 +202,7 @@ svfloat64_t test_svsel_f64(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]] // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z12test_svsel_bu10__SVBool_tu10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z12test_svsel_bu10__SVBool_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]] // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set2-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set2-bfloat.c index f6217977d26ab..0307dae2f69e6 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set2-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set2-bfloat.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv16bf16.nxv8bf16( [[TUPLE:%.*]], [[X:%.*]], i64 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svset2_bf16_014svbfloat16x2_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svset2_bf16_014svbfloat16x2_tu14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv16bf16.nxv8bf16( [[TUPLE:%.*]], [[X:%.*]], i64 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svbfloat16x2_t test_svset2_bf16_0(svbfloat16x2_t tuple, svbfloat16_t x) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv16bf16.nxv8bf16( [[TUPLE:%.*]], [[X:%.*]], i64 8) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svset2_bf16_114svbfloat16x2_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svset2_bf16_114svbfloat16x2_tu14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv16bf16.nxv8bf16( [[TUPLE:%.*]], [[X:%.*]], i64 8) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set3-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set3-bfloat.c index aeef3ab59ee0d..5859f579b1892 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set3-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set3-bfloat.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv24bf16.nxv8bf16( [[TUPLE:%.*]], [[X:%.*]], i64 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svset3_bf16_014svbfloat16x3_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svset3_bf16_014svbfloat16x3_tu14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv24bf16.nxv8bf16( [[TUPLE:%.*]], [[X:%.*]], i64 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -36,7 +36,7 @@ svbfloat16x3_t test_svset3_bf16_0(svbfloat16x3_t tuple, svbfloat16_t x) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv24bf16.nxv8bf16( [[TUPLE:%.*]], [[X:%.*]], i64 8) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svset3_bf16_114svbfloat16x3_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svset3_bf16_114svbfloat16x3_tu14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv24bf16.nxv8bf16( [[TUPLE:%.*]], [[X:%.*]], i64 8) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -51,7 +51,7 @@ svbfloat16x3_t test_svset3_bf16_1(svbfloat16x3_t tuple, svbfloat16_t x) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv24bf16.nxv8bf16( [[TUPLE:%.*]], [[X:%.*]], i64 16) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svset3_bf16_214svbfloat16x3_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svset3_bf16_214svbfloat16x3_tu14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv24bf16.nxv8bf16( [[TUPLE:%.*]], [[X:%.*]], i64 16) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set4-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set4-bfloat.c index 013f591e8d72f..3cfe5c7f914f6 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set4-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set4-bfloat.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TUPLE:%.*]], [[X:%.*]], i64 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svset4_bf16_014svbfloat16x4_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svset4_bf16_014svbfloat16x4_tu14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TUPLE:%.*]], [[X:%.*]], i64 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -36,7 +36,7 @@ svbfloat16x4_t test_svset4_bf16_0(svbfloat16x4_t tuple, svbfloat16_t x) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TUPLE:%.*]], [[X:%.*]], i64 8) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svset4_bf16_114svbfloat16x4_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svset4_bf16_114svbfloat16x4_tu14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TUPLE:%.*]], [[X:%.*]], i64 8) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -51,7 +51,7 @@ svbfloat16x4_t test_svset4_bf16_1(svbfloat16x4_t tuple, svbfloat16_t x) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TUPLE:%.*]], [[X:%.*]], i64 16) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svset4_bf16_214svbfloat16x4_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svset4_bf16_214svbfloat16x4_tu14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TUPLE:%.*]], [[X:%.*]], i64 16) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -66,7 +66,7 @@ svbfloat16x4_t test_svset4_bf16_2(svbfloat16x4_t tuple, svbfloat16_t x) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TUPLE:%.*]], [[X:%.*]], i64 24) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svset4_bf16_314svbfloat16x4_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svset4_bf16_314svbfloat16x4_tu14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TUPLE:%.*]], [[X:%.*]], i64 24) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_splice-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_splice-bfloat.c index 782f32524e89b..523a5fdccb5b6 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_splice-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_splice-bfloat.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.splice.nxv8bf16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svsplice_bf16u10__SVBool_tu14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z18test_svsplice_bf16u10__SVBool_tu14__SVBfloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.splice.nxv8bf16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_splice.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_splice.c index dd6143c7e76ff..287646ed9c5a8 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_splice.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_splice.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.splice.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsplice_s8u10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svsplice_s8u10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.splice.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svsplice_s8(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.splice.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsplice_s16u10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svsplice_s16u10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.splice.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -52,7 +52,7 @@ svint16_t test_svsplice_s16(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.splice.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsplice_s32u10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svsplice_s32u10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.splice.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -69,7 +69,7 @@ svint32_t test_svsplice_s32(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.splice.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsplice_s64u10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svsplice_s64u10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.splice.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -85,7 +85,7 @@ svint64_t test_svsplice_s64(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.splice.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsplice_u8u10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svsplice_u8u10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.splice.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -101,7 +101,7 @@ svuint8_t test_svsplice_u8(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.splice.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsplice_u16u10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svsplice_u16u10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.splice.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -118,7 +118,7 @@ svuint16_t test_svsplice_u16(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.splice.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsplice_u32u10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svsplice_u32u10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.splice.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -135,7 +135,7 @@ svuint32_t test_svsplice_u32(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.splice.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsplice_u64u10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svsplice_u64u10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.splice.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -152,7 +152,7 @@ svuint64_t test_svsplice_u64(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.splice.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsplice_f16u10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svsplice_f16u10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.splice.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -169,7 +169,7 @@ svfloat16_t test_svsplice_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.splice.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsplice_f32u10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svsplice_f32u10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.splice.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -186,7 +186,7 @@ svfloat32_t test_svsplice_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.splice.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsplice_f64u10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svsplice_f64u10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.splice.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sqrt.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sqrt.c index 4e39eb964638e..cf8f5496038bf 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sqrt.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sqrt.c @@ -71,7 +71,7 @@ svfloat64_t test_svsqrt_f64_z(svbool_t pg, svfloat64_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsqrt.nxv8f16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsqrt_f16_mu13__SVFloat16_tu10__SVBool_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svsqrt_f16_mu13__SVFloat16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsqrt.nxv8f16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -88,7 +88,7 @@ svfloat16_t test_svsqrt_f16_m(svfloat16_t inactive, svbool_t pg, svfloat16_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsqrt.nxv4f32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsqrt_f32_mu13__SVFloat32_tu10__SVBool_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svsqrt_f32_mu13__SVFloat32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsqrt.nxv4f32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -105,7 +105,7 @@ svfloat32_t test_svsqrt_f32_m(svfloat32_t inactive, svbool_t pg, svfloat32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsqrt.nxv2f64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsqrt_f64_mu13__SVFloat64_tu10__SVBool_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svsqrt_f64_mu13__SVFloat64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsqrt.nxv2f64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1-bfloat.c index f64deb9553f0c..ad6252c6c26e5 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1-bfloat.c @@ -21,7 +21,7 @@ // CHECK-NEXT: tail call void @llvm.masked.store.nxv8bf16.p0( [[DATA:%.*]], ptr [[BASE:%.*]], i32 1, [[TMP0]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z15test_svst1_bf16u10__SVBool_tPu6__bf16u14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z15test_svst1_bf16u10__SVBool_tPu6__bf16u14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: tail call void @llvm.masked.store.nxv8bf16.p0( [[DATA:%.*]], ptr [[BASE:%.*]], i32 1, [[TMP0]]) @@ -39,7 +39,7 @@ void test_svst1_bf16(svbool_t pg, bfloat16_t *base, svbfloat16_t data) // CHECK-NEXT: tail call void @llvm.masked.store.nxv8bf16.p0( [[DATA:%.*]], ptr [[TMP1]], i32 1, [[TMP0]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z20test_svst1_vnum_bf16u10__SVBool_tPu6__bf16lu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z20test_svst1_vnum_bf16u10__SVBool_tPu6__bf16lu14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = getelementptr , ptr [[BASE:%.*]], i64 [[VNUM:%.*]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1.c index 508e8c132b030..4037fc70b3b86 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1.c @@ -442,7 +442,7 @@ void test_svst1_scatter_u64base_s64(svbool_t pg, svuint64_t bases, svint64_t dat // CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i32.nxv4i32( [[DATA:%.*]], [[TMP0]], [[BASES:%.*]], i64 0) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z30test_svst1_scatter_u32base_u32u10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z30test_svst1_scatter_u32base_u32u10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i32.nxv4i32( [[DATA:%.*]], [[TMP0]], [[BASES:%.*]], i64 0) @@ -459,7 +459,7 @@ void test_svst1_scatter_u32base_u32(svbool_t pg, svuint32_t bases, svuint32_t da // CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i64.nxv2i64( [[DATA:%.*]], [[TMP0]], [[BASES:%.*]], i64 0) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z30test_svst1_scatter_u64base_u64u10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z30test_svst1_scatter_u64base_u64u10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i64.nxv2i64( [[DATA:%.*]], [[TMP0]], [[BASES:%.*]], i64 0) @@ -510,7 +510,7 @@ void test_svst1_scatter_u64base_f64(svbool_t pg, svuint64_t bases, svfloat64_t d // CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.sxtw.nxv4i32( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[OFFSETS:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z32test_svst1_scatter_s32offset_s32u10__SVBool_tPiu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z32test_svst1_scatter_s32offset_s32u10__SVBool_tPiu11__SVInt32_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.sxtw.nxv4i32( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[OFFSETS:%.*]]) @@ -527,7 +527,7 @@ void test_svst1_scatter_s32offset_s32(svbool_t pg, int32_t *base, svint32_t offs // CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.nxv2i64( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[OFFSETS:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z32test_svst1_scatter_s64offset_s64u10__SVBool_tPlu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z32test_svst1_scatter_s64offset_s64u10__SVBool_tPlu11__SVInt64_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.nxv2i64( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[OFFSETS:%.*]]) @@ -646,7 +646,7 @@ void test_svst1_scatter_u64offset_s64(svbool_t pg, int64_t *base, svuint64_t off // CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.uxtw.nxv4i32( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[OFFSETS:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z32test_svst1_scatter_u32offset_u32u10__SVBool_tPju12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z32test_svst1_scatter_u32offset_u32u10__SVBool_tPju12__SVUint32_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.uxtw.nxv4i32( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[OFFSETS:%.*]]) @@ -663,7 +663,7 @@ void test_svst1_scatter_u32offset_u32(svbool_t pg, uint32_t *base, svuint32_t of // CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.nxv2i64( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[OFFSETS:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z32test_svst1_scatter_u64offset_u64u10__SVBool_tPmu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z32test_svst1_scatter_u64offset_u64u10__SVBool_tPmu12__SVUint64_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.nxv2i64( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[OFFSETS:%.*]]) @@ -748,7 +748,7 @@ void test_svst1_scatter_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_ // CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i32.nxv4i32( [[DATA:%.*]], [[TMP0]], [[BASES:%.*]], i64 [[OFFSET:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z37test_svst1_scatter_u32base_offset_u32u10__SVBool_tu12__SVUint32_tlu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z37test_svst1_scatter_u32base_offset_u32u10__SVBool_tu12__SVUint32_tlS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i32.nxv4i32( [[DATA:%.*]], [[TMP0]], [[BASES:%.*]], i64 [[OFFSET:%.*]]) @@ -765,7 +765,7 @@ void test_svst1_scatter_u32base_offset_u32(svbool_t pg, svuint32_t bases, int64_ // CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i64.nxv2i64( [[DATA:%.*]], [[TMP0]], [[BASES:%.*]], i64 [[OFFSET:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z37test_svst1_scatter_u64base_offset_u64u10__SVBool_tu12__SVUint64_tlu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z37test_svst1_scatter_u64base_offset_u64u10__SVBool_tu12__SVUint64_tlS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i64.nxv2i64( [[DATA:%.*]], [[TMP0]], [[BASES:%.*]], i64 [[OFFSET:%.*]]) @@ -816,7 +816,7 @@ void test_svst1_scatter_u64base_offset_f64(svbool_t pg, svuint64_t bases, int64_ // CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i32( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z31test_svst1_scatter_s32index_s32u10__SVBool_tPiu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z31test_svst1_scatter_s32index_s32u10__SVBool_tPiu11__SVInt32_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i32( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[INDICES:%.*]]) @@ -833,7 +833,7 @@ void test_svst1_scatter_s32index_s32(svbool_t pg, int32_t *base, svint32_t indic // CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.index.nxv2i64( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z31test_svst1_scatter_s64index_s64u10__SVBool_tPlu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z31test_svst1_scatter_s64index_s64u10__SVBool_tPlu11__SVInt64_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.index.nxv2i64( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[INDICES:%.*]]) @@ -952,7 +952,7 @@ void test_svst1_scatter_u64index_s64(svbool_t pg, int64_t *base, svuint64_t indi // CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4i32( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z31test_svst1_scatter_u32index_u32u10__SVBool_tPju12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z31test_svst1_scatter_u32index_u32u10__SVBool_tPju12__SVUint32_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4i32( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[INDICES:%.*]]) @@ -969,7 +969,7 @@ void test_svst1_scatter_u32index_u32(svbool_t pg, uint32_t *base, svuint32_t ind // CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.index.nxv2i64( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z31test_svst1_scatter_u64index_u64u10__SVBool_tPmu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z31test_svst1_scatter_u64index_u64u10__SVBool_tPmu12__SVUint64_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.index.nxv2i64( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[INDICES:%.*]]) @@ -1059,7 +1059,7 @@ void test_svst1_scatter_u64base_index_s64(svbool_t pg, svuint64_t bases, int64_t // CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i32.nxv4i32( [[DATA:%.*]], [[TMP0]], [[BASES:%.*]], i64 [[TMP1]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z36test_svst1_scatter_u32base_index_u32u10__SVBool_tu12__SVUint32_tlu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z36test_svst1_scatter_u32base_index_u32u10__SVBool_tu12__SVUint32_tlS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[INDEX:%.*]], 2 @@ -1078,7 +1078,7 @@ void test_svst1_scatter_u32base_index_u32(svbool_t pg, svuint32_t bases, int64_t // CHECK-NEXT: tail call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i64.nxv2i64( [[DATA:%.*]], [[TMP0]], [[BASES:%.*]], i64 [[TMP1]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z36test_svst1_scatter_u64base_index_u64u10__SVBool_tu12__SVUint64_tlu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z36test_svst1_scatter_u64base_index_u64u10__SVBool_tu12__SVUint64_tlS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[INDEX:%.*]], 3 diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_stnt1-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_stnt1-bfloat.c index b19c12038f571..1c70293586bbe 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_stnt1-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_stnt1-bfloat.c @@ -21,7 +21,7 @@ // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.nxv8bf16( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z17test_svstnt1_bf16u10__SVBool_tPu6__bf16u14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svstnt1_bf16u10__SVBool_tPu6__bf16u14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.nxv8bf16( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]]) @@ -39,7 +39,7 @@ void test_svstnt1_bf16(svbool_t pg, bfloat16_t *base, svbfloat16_t data) // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.nxv8bf16( [[DATA:%.*]], [[TMP0]], ptr [[TMP1]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z22test_svstnt1_vnum_bf16u10__SVBool_tPu6__bf16lu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z22test_svstnt1_vnum_bf16u10__SVBool_tPu6__bf16lu14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = getelementptr , ptr [[BASE:%.*]], i64 [[VNUM:%.*]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sub.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sub.c index ec189029caecb..a2a8830ba279f 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sub.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sub.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svsub_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svsub_s8_zu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -38,7 +38,7 @@ svint8_t test_svsub_s8_z(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sub.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_s16_zu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -57,7 +57,7 @@ svint16_t test_svsub_s16_z(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sub.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -76,7 +76,7 @@ svint32_t test_svsub_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sub.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -94,7 +94,7 @@ svint64_t test_svsub_s64_z(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z15test_svsub_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svsub_u8_zu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -112,7 +112,7 @@ svuint8_t test_svsub_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sub.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_u16_zu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -131,7 +131,7 @@ svuint16_t test_svsub_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sub.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_u32_zu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -150,7 +150,7 @@ svuint32_t test_svsub_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sub.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_u64_zu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -167,7 +167,7 @@ svuint64_t test_svsub_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sub.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svsub_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svsub_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sub.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -183,7 +183,7 @@ svint8_t test_svsub_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -200,7 +200,7 @@ svint16_t test_svsub_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -217,7 +217,7 @@ svint32_t test_svsub_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -233,7 +233,7 @@ svint64_t test_svsub_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sub.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svsub_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svsub_u8_mu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sub.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -249,7 +249,7 @@ svuint8_t test_svsub_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_u16_mu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -266,7 +266,7 @@ svuint16_t test_svsub_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -283,7 +283,7 @@ svuint32_t test_svsub_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -299,7 +299,7 @@ svuint64_t test_svsub_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svsub_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svsub_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -315,7 +315,7 @@ svint8_t test_svsub_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -332,7 +332,7 @@ svint16_t test_svsub_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -349,7 +349,7 @@ svint32_t test_svsub_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -365,7 +365,7 @@ svint64_t test_svsub_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svsub_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svsub_u8_xu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -381,7 +381,7 @@ svuint8_t test_svsub_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_u16_xu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -398,7 +398,7 @@ svuint16_t test_svsub_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -415,7 +415,7 @@ svuint32_t test_svsub_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -941,7 +941,7 @@ svuint64_t test_svsub_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fsub.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_f16_zu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -960,7 +960,7 @@ svfloat16_t test_svsub_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fsub.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_f32_zu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -979,7 +979,7 @@ svfloat32_t test_svsub_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fsub.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_f64_zu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -997,7 +997,7 @@ svfloat64_t test_svsub_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsub.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_f16_mu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsub.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1014,7 +1014,7 @@ svfloat16_t test_svsub_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsub.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_f32_mu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsub.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1031,7 +1031,7 @@ svfloat32_t test_svsub_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsub.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_f64_mu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsub.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1048,7 +1048,7 @@ svfloat64_t test_svsub_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsub.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_f16_xu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsub.u.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1065,7 +1065,7 @@ svfloat16_t test_svsub_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsub.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_f32_xu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsub.u.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1082,7 +1082,7 @@ svfloat32_t test_svsub_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsub.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svsub_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svsub_f64_xu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsub.u.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_subr.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_subr.c index e8bffc5f97e5a..5d0368ac73b0a 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_subr.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_subr.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.subr.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svsubr_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svsubr_s8_zu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.subr.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -38,7 +38,7 @@ svint8_t test_svsubr_s8_z(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.subr.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_s16_zu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -57,7 +57,7 @@ svint16_t test_svsubr_s16_z(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.subr.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -76,7 +76,7 @@ svint32_t test_svsubr_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.subr.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -94,7 +94,7 @@ svint64_t test_svsubr_s64_z(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.subr.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svsubr_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svsubr_u8_zu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.subr.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -112,7 +112,7 @@ svuint8_t test_svsubr_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.subr.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_u16_zu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -131,7 +131,7 @@ svuint16_t test_svsubr_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.subr.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_u32_zu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -150,7 +150,7 @@ svuint32_t test_svsubr_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.subr.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_u64_zu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -167,7 +167,7 @@ svuint64_t test_svsubr_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsubr_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svsubr_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -183,7 +183,7 @@ svint8_t test_svsubr_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.subr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.subr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -200,7 +200,7 @@ svint16_t test_svsubr_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.subr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.subr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -217,7 +217,7 @@ svint32_t test_svsubr_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.subr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.subr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -233,7 +233,7 @@ svint64_t test_svsubr_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsubr_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svsubr_u8_mu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -249,7 +249,7 @@ svuint8_t test_svsubr_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.subr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_u16_mu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.subr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -266,7 +266,7 @@ svuint16_t test_svsubr_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.subr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.subr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -283,7 +283,7 @@ svuint32_t test_svsubr_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.subr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.subr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -299,7 +299,7 @@ svuint64_t test_svsubr_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv16i8( [[PG:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsubr_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svsubr_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv16i8( [[PG:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -315,7 +315,7 @@ svint8_t test_svsubr_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv8i16( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv8i16( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -332,7 +332,7 @@ svint16_t test_svsubr_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv4i32( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv4i32( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -349,7 +349,7 @@ svint32_t test_svsubr_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv2i64( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv2i64( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -365,7 +365,7 @@ svint64_t test_svsubr_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv16i8( [[PG:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsubr_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svsubr_u8_xu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv16i8( [[PG:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -381,7 +381,7 @@ svuint8_t test_svsubr_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv8i16( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_u16_xu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv8i16( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -398,7 +398,7 @@ svuint16_t test_svsubr_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv4i32( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv4i32( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -415,7 +415,7 @@ svuint32_t test_svsubr_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv2i64( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sub.u.nxv2i64( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -941,7 +941,7 @@ svuint64_t test_svsubr_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fsubr.nxv8f16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_f16_zu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_f16_zu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -960,7 +960,7 @@ svfloat16_t test_svsubr_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fsubr.nxv4f32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_f32_zu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_f32_zu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -979,7 +979,7 @@ svfloat32_t test_svsubr_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fsubr.nxv2f64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_f64_zu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_f64_zu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -997,7 +997,7 @@ svfloat64_t test_svsubr_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsubr.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_f16_mu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsubr.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1014,7 +1014,7 @@ svfloat16_t test_svsubr_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsubr.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_f32_mu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsubr.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1031,7 +1031,7 @@ svfloat32_t test_svsubr_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsubr.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_f64_mu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsubr.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -1048,7 +1048,7 @@ svfloat64_t test_svsubr_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsub.u.nxv8f16( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_f16_xu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsub.u.nxv8f16( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -1065,7 +1065,7 @@ svfloat16_t test_svsubr_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsub.u.nxv4f32( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_f32_xu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsub.u.nxv4f32( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -1082,7 +1082,7 @@ svfloat32_t test_svsubr_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsub.u.nxv2f64( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svsubr_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svsubr_f64_xu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fsub.u.nxv2f64( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tbl-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tbl-bfloat.c index a6090e06ae39b..d8f3be1343407 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tbl-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tbl-bfloat.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbl.nxv8bf16( [[DATA:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtbl_bf16u14__SVBFloat16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z15test_svtbl_bf16u14__SVBfloat16_tu12__SVUint16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbl.nxv8bf16( [[DATA:%.*]], [[INDICES:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tbl.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tbl.c index 18bf5162b6867..8a7fb4b836242 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tbl.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tbl.c @@ -79,7 +79,7 @@ svint64_t test_svtbl_s64(svint64_t data, svuint64_t indices) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbl.nxv16i8( [[DATA:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z13test_svtbl_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z13test_svtbl_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbl.nxv16i8( [[DATA:%.*]], [[INDICES:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -94,7 +94,7 @@ svuint8_t test_svtbl_u8(svuint8_t data, svuint8_t indices) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbl.nxv8i16( [[DATA:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svtbl_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z14test_svtbl_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbl.nxv8i16( [[DATA:%.*]], [[INDICES:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -109,7 +109,7 @@ svuint16_t test_svtbl_u16(svuint16_t data, svuint16_t indices) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbl.nxv4i32( [[DATA:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svtbl_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z14test_svtbl_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbl.nxv4i32( [[DATA:%.*]], [[INDICES:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -124,7 +124,7 @@ svuint32_t test_svtbl_u32(svuint32_t data, svuint32_t indices) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbl.nxv2i64( [[DATA:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svtbl_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z14test_svtbl_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbl.nxv2i64( [[DATA:%.*]], [[INDICES:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tmad.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tmad.c index f38d6d06a405d..cc58279c23999 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tmad.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tmad.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ftmad.x.nxv8f16( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtmad_f16u13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z15test_svtmad_f16u13__SVFloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ftmad.x.nxv8f16( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svfloat16_t test_svtmad_f16(svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ftmad.x.nxv8f16( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svtmad_f16_1u13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svtmad_f16_1u13__SVFloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ftmad.x.nxv8f16( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -49,7 +49,7 @@ svfloat16_t test_svtmad_f16_1(svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ftmad.x.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtmad_f32u13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z15test_svtmad_f32u13__SVFloat32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ftmad.x.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -64,7 +64,7 @@ svfloat32_t test_svtmad_f32(svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ftmad.x.nxv2f64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtmad_f64u13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z15test_svtmad_f64u13__SVFloat64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ftmad.x.nxv2f64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-bfloat.c index ea2feaaf5e39e..0a003ddd6a85f 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-bfloat.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svtrn1_bf16u14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svtrn1_bf16u14__SVBfloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-fp64-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-fp64-bfloat.c index 2e4bd2c889dc1..8734a730b4621 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-fp64-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-fp64-bfloat.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1q.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svtrn1_bf16u14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svtrn1_bf16u14__SVBfloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1q.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-fp64.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-fp64.c index f3283c5236398..4099e492acff6 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-fp64.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-fp64.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1q.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svtrn1_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z14test_svtrn1_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1q.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svint8_t test_svtrn1_s8(svint8_t op1, svint8_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1q.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn1_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn1_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1q.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -48,7 +48,7 @@ svint16_t test_svtrn1_s16(svint16_t op1, svint16_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1q.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn1_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn1_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1q.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -62,7 +62,7 @@ svint32_t test_svtrn1_s32(svint32_t op1, svint32_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1q.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn1_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn1_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1q.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -76,7 +76,7 @@ svint64_t test_svtrn1_s64(svint64_t op1, svint64_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1q.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svtrn1_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svtrn1_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1q.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -90,7 +90,7 @@ svuint8_t test_svtrn1_u8(svuint8_t op1, svuint8_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1q.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn1_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn1_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1q.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -104,7 +104,7 @@ svuint16_t test_svtrn1_u16(svuint16_t op1, svuint16_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1q.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn1_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn1_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1q.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -118,7 +118,7 @@ svuint32_t test_svtrn1_u32(svuint32_t op1, svuint32_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1q.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn1_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn1_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1q.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -132,7 +132,7 @@ svuint64_t test_svtrn1_u64(svuint64_t op1, svuint64_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1q.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn1_f16u13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn1_f16u13__SVFloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1q.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -146,7 +146,7 @@ svfloat16_t test_svtrn1_f16(svfloat16_t op1, svfloat16_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1q.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn1_f32u13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn1_f32u13__SVFloat32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1q.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -160,7 +160,7 @@ svfloat32_t test_svtrn1_f32(svfloat32_t op1, svfloat32_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1q.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn1_f64u13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn1_f64u13__SVFloat64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1q.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1.c index 98d37f23a0af7..279f3b75d4353 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svtrn1_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z14test_svtrn1_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svint8_t test_svtrn1_s8(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn1_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn1_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -49,7 +49,7 @@ svint16_t test_svtrn1_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn1_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn1_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -64,7 +64,7 @@ svint32_t test_svtrn1_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn1_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn1_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -79,7 +79,7 @@ svint64_t test_svtrn1_s64(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svtrn1_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svtrn1_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -94,7 +94,7 @@ svuint8_t test_svtrn1_u8(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn1_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn1_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -109,7 +109,7 @@ svuint16_t test_svtrn1_u16(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn1_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn1_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -124,7 +124,7 @@ svuint32_t test_svtrn1_u32(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn1_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn1_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -139,7 +139,7 @@ svuint64_t test_svtrn1_u64(svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn1_f16u13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn1_f16u13__SVFloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -154,7 +154,7 @@ svfloat16_t test_svtrn1_f16(svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn1_f32u13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn1_f32u13__SVFloat32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -169,7 +169,7 @@ svfloat32_t test_svtrn1_f32(svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn1_f64u13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn1_f64u13__SVFloat64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -184,7 +184,7 @@ svfloat64_t test_svtrn1_f64(svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv16i1( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svtrn1_b8u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z14test_svtrn1_b8u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.nxv16i1( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -199,7 +199,7 @@ svbool_t test_svtrn1_b8(svbool_t op1, svbool_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.b16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn1_b16u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn1_b16u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.b16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -214,7 +214,7 @@ svbool_t test_svtrn1_b16(svbool_t op1, svbool_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.b32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn1_b32u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn1_b32u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.b32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -229,7 +229,7 @@ svbool_t test_svtrn1_b32(svbool_t op1, svbool_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.b64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn1_b64u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn1_b64u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn1.b64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-bfloat.c index e2dbe9fddf489..0dc8d5c426b6b 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-bfloat.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svtrn2_bf16u14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svtrn2_bf16u14__SVBfloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-fp64-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-fp64-bfloat.c index d5b85fad9d8e8..9dc42ed4b5d4c 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-fp64-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-fp64-bfloat.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2q.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svtrn2_bf16u14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svtrn2_bf16u14__SVBfloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2q.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-fp64.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-fp64.c index cbc85098dd621..9c984b7ce4391 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-fp64.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-fp64.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2q.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svtrn2_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z14test_svtrn2_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2q.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svint8_t test_svtrn2_s8(svint8_t op1, svint8_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2q.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn2_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn2_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2q.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -48,7 +48,7 @@ svint16_t test_svtrn2_s16(svint16_t op1, svint16_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2q.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn2_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn2_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2q.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -62,7 +62,7 @@ svint32_t test_svtrn2_s32(svint32_t op1, svint32_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2q.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn2_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn2_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2q.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -76,7 +76,7 @@ svint64_t test_svtrn2_s64(svint64_t op1, svint64_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2q.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svtrn2_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svtrn2_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2q.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -90,7 +90,7 @@ svuint8_t test_svtrn2_u8(svuint8_t op1, svuint8_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2q.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn2_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn2_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2q.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -104,7 +104,7 @@ svuint16_t test_svtrn2_u16(svuint16_t op1, svuint16_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2q.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn2_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn2_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2q.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -118,7 +118,7 @@ svuint32_t test_svtrn2_u32(svuint32_t op1, svuint32_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2q.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn2_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn2_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2q.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -132,7 +132,7 @@ svuint64_t test_svtrn2_u64(svuint64_t op1, svuint64_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2q.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn2_f16u13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn2_f16u13__SVFloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2q.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -146,7 +146,7 @@ svfloat16_t test_svtrn2_f16(svfloat16_t op1, svfloat16_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2q.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn2_f32u13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn2_f32u13__SVFloat32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2q.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -160,7 +160,7 @@ svfloat32_t test_svtrn2_f32(svfloat32_t op1, svfloat32_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2q.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn2_f64u13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn2_f64u13__SVFloat64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2q.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2.c index b228a138bb08a..74a7e73eab77e 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svtrn2_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z14test_svtrn2_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svint8_t test_svtrn2_s8(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn2_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn2_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -49,7 +49,7 @@ svint16_t test_svtrn2_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn2_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn2_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -64,7 +64,7 @@ svint32_t test_svtrn2_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn2_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn2_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -79,7 +79,7 @@ svint64_t test_svtrn2_s64(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svtrn2_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svtrn2_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -94,7 +94,7 @@ svuint8_t test_svtrn2_u8(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn2_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn2_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -109,7 +109,7 @@ svuint16_t test_svtrn2_u16(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn2_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn2_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -124,7 +124,7 @@ svuint32_t test_svtrn2_u32(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn2_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn2_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -139,7 +139,7 @@ svuint64_t test_svtrn2_u64(svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn2_f16u13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn2_f16u13__SVFloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -154,7 +154,7 @@ svfloat16_t test_svtrn2_f16(svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn2_f32u13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn2_f32u13__SVFloat32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -169,7 +169,7 @@ svfloat32_t test_svtrn2_f32(svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn2_f64u13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn2_f64u13__SVFloat64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -184,7 +184,7 @@ svfloat64_t test_svtrn2_f64(svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv16i1( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svtrn2_b8u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z14test_svtrn2_b8u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.nxv16i1( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -199,7 +199,7 @@ svbool_t test_svtrn2_b8(svbool_t op1, svbool_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.b16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn2_b16u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn2_b16u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.b16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -214,7 +214,7 @@ svbool_t test_svtrn2_b16(svbool_t op1, svbool_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.b32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn2_b32u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn2_b32u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.b32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -229,7 +229,7 @@ svbool_t test_svtrn2_b32(svbool_t op1, svbool_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.b64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtrn2_b64u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svtrn2_b64u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.trn2.b64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-bfloat.c index c27cc91815398..0892c10a29caa 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-bfloat.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svuzp1_bf16u14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svuzp1_bf16u14__SVBfloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-fp64-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-fp64-bfloat.c index 2fa26a47d1e98..35565bed3fed3 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-fp64-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-fp64-bfloat.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1q.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svuzp1_bf16u14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svuzp1_bf16u14__SVBfloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1q.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-fp64.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-fp64.c index 7ac4130f63ad9..462f5aa0a7e42 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-fp64.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-fp64.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1q.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svuzp1_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z14test_svuzp1_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1q.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svint8_t test_svuzp1_s8(svint8_t op1, svint8_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1q.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp1_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp1_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1q.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -48,7 +48,7 @@ svint16_t test_svuzp1_s16(svint16_t op1, svint16_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1q.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp1_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp1_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1q.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -62,7 +62,7 @@ svint32_t test_svuzp1_s32(svint32_t op1, svint32_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1q.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp1_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp1_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1q.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -76,7 +76,7 @@ svint64_t test_svuzp1_s64(svint64_t op1, svint64_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1q.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svuzp1_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svuzp1_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1q.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -90,7 +90,7 @@ svuint8_t test_svuzp1_u8(svuint8_t op1, svuint8_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1q.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp1_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp1_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1q.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -104,7 +104,7 @@ svuint16_t test_svuzp1_u16(svuint16_t op1, svuint16_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1q.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp1_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp1_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1q.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -118,7 +118,7 @@ svuint32_t test_svuzp1_u32(svuint32_t op1, svuint32_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1q.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp1_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp1_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1q.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -132,7 +132,7 @@ svuint64_t test_svuzp1_u64(svuint64_t op1, svuint64_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1q.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp1_f16u13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp1_f16u13__SVFloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1q.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -146,7 +146,7 @@ svfloat16_t test_svuzp1_f16(svfloat16_t op1, svfloat16_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1q.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp1_f32u13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp1_f32u13__SVFloat32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1q.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -160,7 +160,7 @@ svfloat32_t test_svuzp1_f32(svfloat32_t op1, svfloat32_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1q.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp1_f64u13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp1_f64u13__SVFloat64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1q.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1.c index 3672e566cb185..abdfaa27162ba 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svuzp1_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z14test_svuzp1_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svint8_t test_svuzp1_s8(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp1_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp1_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -49,7 +49,7 @@ svint16_t test_svuzp1_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp1_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp1_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -64,7 +64,7 @@ svint32_t test_svuzp1_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp1_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp1_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -79,7 +79,7 @@ svint64_t test_svuzp1_s64(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svuzp1_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svuzp1_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -94,7 +94,7 @@ svuint8_t test_svuzp1_u8(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp1_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp1_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -109,7 +109,7 @@ svuint16_t test_svuzp1_u16(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp1_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp1_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -124,7 +124,7 @@ svuint32_t test_svuzp1_u32(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp1_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp1_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -139,7 +139,7 @@ svuint64_t test_svuzp1_u64(svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp1_f16u13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp1_f16u13__SVFloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -154,7 +154,7 @@ svfloat16_t test_svuzp1_f16(svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp1_f32u13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp1_f32u13__SVFloat32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -169,7 +169,7 @@ svfloat32_t test_svuzp1_f32(svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp1_f64u13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp1_f64u13__SVFloat64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -184,7 +184,7 @@ svfloat64_t test_svuzp1_f64(svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv16i1( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svuzp1_b8u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z14test_svuzp1_b8u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.nxv16i1( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -199,7 +199,7 @@ svbool_t test_svuzp1_b8(svbool_t op1, svbool_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.b16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp1_b16u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp1_b16u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.b16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -214,7 +214,7 @@ svbool_t test_svuzp1_b16(svbool_t op1, svbool_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.b32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp1_b32u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp1_b32u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.b32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -229,7 +229,7 @@ svbool_t test_svuzp1_b32(svbool_t op1, svbool_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.b64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp1_b64u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp1_b64u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp1.b64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-bfloat.c index 395e7b25094cd..45ad04b6b50c8 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-bfloat.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svuzp2_bf16u14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svuzp2_bf16u14__SVBfloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-fp64-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-fp64-bfloat.c index ff23a20035882..8affbda65c3c0 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-fp64-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-fp64-bfloat.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2q.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svuzp2_bf16u14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svuzp2_bf16u14__SVBfloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2q.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-fp64.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-fp64.c index 936b2f214cb55..de756218cd6fe 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-fp64.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-fp64.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2q.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svuzp2_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z14test_svuzp2_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2q.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svint8_t test_svuzp2_s8(svint8_t op1, svint8_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2q.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp2_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp2_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2q.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -48,7 +48,7 @@ svint16_t test_svuzp2_s16(svint16_t op1, svint16_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2q.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp2_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp2_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2q.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -62,7 +62,7 @@ svint32_t test_svuzp2_s32(svint32_t op1, svint32_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2q.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp2_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp2_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2q.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -76,7 +76,7 @@ svint64_t test_svuzp2_s64(svint64_t op1, svint64_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2q.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svuzp2_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svuzp2_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2q.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -90,7 +90,7 @@ svuint8_t test_svuzp2_u8(svuint8_t op1, svuint8_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2q.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp2_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp2_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2q.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -104,7 +104,7 @@ svuint16_t test_svuzp2_u16(svuint16_t op1, svuint16_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2q.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp2_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp2_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2q.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -118,7 +118,7 @@ svuint32_t test_svuzp2_u32(svuint32_t op1, svuint32_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2q.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp2_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp2_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2q.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -132,7 +132,7 @@ svuint64_t test_svuzp2_u64(svuint64_t op1, svuint64_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2q.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp2_f16u13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp2_f16u13__SVFloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2q.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -146,7 +146,7 @@ svfloat16_t test_svuzp2_f16(svfloat16_t op1, svfloat16_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2q.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp2_f32u13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp2_f32u13__SVFloat32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2q.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -160,7 +160,7 @@ svfloat32_t test_svuzp2_f32(svfloat32_t op1, svfloat32_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2q.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp2_f64u13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp2_f64u13__SVFloat64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2q.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2.c index d160f88898051..36a3aa6ce6798 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svuzp2_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z14test_svuzp2_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svint8_t test_svuzp2_s8(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp2_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp2_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -49,7 +49,7 @@ svint16_t test_svuzp2_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp2_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp2_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -64,7 +64,7 @@ svint32_t test_svuzp2_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp2_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp2_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -79,7 +79,7 @@ svint64_t test_svuzp2_s64(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svuzp2_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svuzp2_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -94,7 +94,7 @@ svuint8_t test_svuzp2_u8(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp2_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp2_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -109,7 +109,7 @@ svuint16_t test_svuzp2_u16(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp2_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp2_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -124,7 +124,7 @@ svuint32_t test_svuzp2_u32(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp2_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp2_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -139,7 +139,7 @@ svuint64_t test_svuzp2_u64(svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp2_f16u13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp2_f16u13__SVFloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -154,7 +154,7 @@ svfloat16_t test_svuzp2_f16(svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp2_f32u13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp2_f32u13__SVFloat32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -169,7 +169,7 @@ svfloat32_t test_svuzp2_f32(svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp2_f64u13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp2_f64u13__SVFloat64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -184,7 +184,7 @@ svfloat64_t test_svuzp2_f64(svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv16i1( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svuzp2_b8u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z14test_svuzp2_b8u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.nxv16i1( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -199,7 +199,7 @@ svbool_t test_svuzp2_b8(svbool_t op1, svbool_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.b16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp2_b16u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp2_b16u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.b16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -214,7 +214,7 @@ svbool_t test_svuzp2_b16(svbool_t op1, svbool_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.b32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp2_b32u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp2_b32u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.b32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -229,7 +229,7 @@ svbool_t test_svuzp2_b32(svbool_t op1, svbool_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.b64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svuzp2_b64u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svuzp2_b64u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uzp2.b64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-bfloat.c index 451dac959b5bb..9c665a07b5b60 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-bfloat.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svzip1_bf16u14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svzip1_bf16u14__SVBfloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-fp64-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-fp64-bfloat.c index 761e92e7982cf..d00b1204ccd52 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-fp64-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-fp64-bfloat.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1q.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svzip1_bf16u14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svzip1_bf16u14__SVBfloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1q.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-fp64.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-fp64.c index 07315cb61736f..e35218a30bdac 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-fp64.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-fp64.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1q.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svzip1_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z14test_svzip1_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1q.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svint8_t test_svzip1_s8(svint8_t op1, svint8_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1q.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip1_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z15test_svzip1_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1q.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -48,7 +48,7 @@ svint16_t test_svzip1_s16(svint16_t op1, svint16_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1q.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip1_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z15test_svzip1_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1q.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -62,7 +62,7 @@ svint32_t test_svzip1_s32(svint32_t op1, svint32_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1q.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip1_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z15test_svzip1_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1q.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -76,7 +76,7 @@ svint64_t test_svzip1_s64(svint64_t op1, svint64_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1q.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svzip1_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svzip1_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1q.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -90,7 +90,7 @@ svuint8_t test_svzip1_u8(svuint8_t op1, svuint8_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1q.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip1_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z15test_svzip1_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1q.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -104,7 +104,7 @@ svuint16_t test_svzip1_u16(svuint16_t op1, svuint16_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1q.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip1_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z15test_svzip1_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1q.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -118,7 +118,7 @@ svuint32_t test_svzip1_u32(svuint32_t op1, svuint32_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1q.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip1_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z15test_svzip1_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1q.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -132,7 +132,7 @@ svuint64_t test_svzip1_u64(svuint64_t op1, svuint64_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1q.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip1_f16u13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z15test_svzip1_f16u13__SVFloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1q.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -146,7 +146,7 @@ svfloat16_t test_svzip1_f16(svfloat16_t op1, svfloat16_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1q.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip1_f32u13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z15test_svzip1_f32u13__SVFloat32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1q.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -160,7 +160,7 @@ svfloat32_t test_svzip1_f32(svfloat32_t op1, svfloat32_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1q.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip1_f64u13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z15test_svzip1_f64u13__SVFloat64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1q.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1.c index 5a66aee828d8a..1106e2a65c02b 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svzip1_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z14test_svzip1_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svint8_t test_svzip1_s8(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip1_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z15test_svzip1_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -49,7 +49,7 @@ svint16_t test_svzip1_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip1_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z15test_svzip1_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -64,7 +64,7 @@ svint32_t test_svzip1_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip1_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z15test_svzip1_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -79,7 +79,7 @@ svint64_t test_svzip1_s64(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svzip1_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svzip1_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -94,7 +94,7 @@ svuint8_t test_svzip1_u8(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip1_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z15test_svzip1_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -109,7 +109,7 @@ svuint16_t test_svzip1_u16(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip1_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z15test_svzip1_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -124,7 +124,7 @@ svuint32_t test_svzip1_u32(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip1_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z15test_svzip1_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -139,7 +139,7 @@ svuint64_t test_svzip1_u64(svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip1_f16u13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z15test_svzip1_f16u13__SVFloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -154,7 +154,7 @@ svfloat16_t test_svzip1_f16(svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip1_f32u13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z15test_svzip1_f32u13__SVFloat32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -169,7 +169,7 @@ svfloat32_t test_svzip1_f32(svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip1_f64u13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z15test_svzip1_f64u13__SVFloat64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -184,7 +184,7 @@ svfloat64_t test_svzip1_f64(svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv16i1( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svzip1_b8u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z14test_svzip1_b8u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.nxv16i1( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -199,7 +199,7 @@ svbool_t test_svzip1_b8(svbool_t op1, svbool_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.b16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip1_b16u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svzip1_b16u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.b16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -214,7 +214,7 @@ svbool_t test_svzip1_b16(svbool_t op1, svbool_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.b32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip1_b32u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svzip1_b32u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.b32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -229,7 +229,7 @@ svbool_t test_svzip1_b32(svbool_t op1, svbool_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.b64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip1_b64u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svzip1_b64u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip1.b64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-bfloat.c index 6888e2c49d3bd..fefd6bb716ce1 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-bfloat.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svzip2_bf16u14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svzip2_bf16u14__SVBfloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-fp64-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-fp64-bfloat.c index 19af180181c57..fbc563add979f 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-fp64-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-fp64-bfloat.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2q.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svzip2_bf16u14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svzip2_bf16u14__SVBfloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2q.nxv8bf16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-fp64.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-fp64.c index 5bd56b71c919c..fd2c8b333a66b 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-fp64.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-fp64.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2q.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svzip2_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z14test_svzip2_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2q.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svint8_t test_svzip2_s8(svint8_t op1, svint8_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2q.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip2_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z15test_svzip2_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2q.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -48,7 +48,7 @@ svint16_t test_svzip2_s16(svint16_t op1, svint16_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2q.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip2_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z15test_svzip2_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2q.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -62,7 +62,7 @@ svint32_t test_svzip2_s32(svint32_t op1, svint32_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2q.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip2_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z15test_svzip2_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2q.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -76,7 +76,7 @@ svint64_t test_svzip2_s64(svint64_t op1, svint64_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2q.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svzip2_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svzip2_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2q.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -90,7 +90,7 @@ svuint8_t test_svzip2_u8(svuint8_t op1, svuint8_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2q.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip2_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z15test_svzip2_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2q.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -104,7 +104,7 @@ svuint16_t test_svzip2_u16(svuint16_t op1, svuint16_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2q.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip2_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z15test_svzip2_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2q.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -118,7 +118,7 @@ svuint32_t test_svzip2_u32(svuint32_t op1, svuint32_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2q.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip2_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z15test_svzip2_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2q.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -132,7 +132,7 @@ svuint64_t test_svzip2_u64(svuint64_t op1, svuint64_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2q.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip2_f16u13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z15test_svzip2_f16u13__SVFloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2q.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -146,7 +146,7 @@ svfloat16_t test_svzip2_f16(svfloat16_t op1, svfloat16_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2q.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip2_f32u13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z15test_svzip2_f32u13__SVFloat32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2q.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -160,7 +160,7 @@ svfloat32_t test_svzip2_f32(svfloat32_t op1, svfloat32_t op2) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2q.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip2_f64u13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z15test_svzip2_f64u13__SVFloat64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2q.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2.c index bdd89e7a2e8d0..b86142f2b556e 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svzip2_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z14test_svzip2_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svint8_t test_svzip2_s8(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip2_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z15test_svzip2_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -49,7 +49,7 @@ svint16_t test_svzip2_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip2_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z15test_svzip2_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -64,7 +64,7 @@ svint32_t test_svzip2_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip2_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z15test_svzip2_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -79,7 +79,7 @@ svint64_t test_svzip2_s64(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svzip2_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svzip2_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -94,7 +94,7 @@ svuint8_t test_svzip2_u8(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip2_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z15test_svzip2_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -109,7 +109,7 @@ svuint16_t test_svzip2_u16(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip2_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z15test_svzip2_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -124,7 +124,7 @@ svuint32_t test_svzip2_u32(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip2_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z15test_svzip2_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -139,7 +139,7 @@ svuint64_t test_svzip2_u64(svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip2_f16u13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z15test_svzip2_f16u13__SVFloat16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv8f16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -154,7 +154,7 @@ svfloat16_t test_svzip2_f16(svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip2_f32u13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z15test_svzip2_f32u13__SVFloat32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv4f32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -169,7 +169,7 @@ svfloat32_t test_svzip2_f32(svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip2_f64u13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z15test_svzip2_f64u13__SVFloat64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv2f64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -184,7 +184,7 @@ svfloat64_t test_svzip2_f64(svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv16i1( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svzip2_b8u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z14test_svzip2_b8u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.nxv16i1( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -199,7 +199,7 @@ svbool_t test_svzip2_b8(svbool_t op1, svbool_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.b16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip2_b16u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svzip2_b16u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.b16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -214,7 +214,7 @@ svbool_t test_svzip2_b16(svbool_t op1, svbool_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.b32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip2_b32u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svzip2_b32u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.b32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -229,7 +229,7 @@ svbool_t test_svzip2_b32(svbool_t op1, svbool_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.b64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svzip2_b64u10__SVBool_tu10__SVBool_t( +// CPP-CHECK-LABEL: @_Z15test_svzip2_b64u10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.zip2.b64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve.c b/clang/test/CodeGen/aarch64-sve.c index 1e0c4592a2010..5f6a0178aa442 100644 --- a/clang/test/CodeGen/aarch64-sve.c +++ b/clang/test/CodeGen/aarch64-sve.c @@ -33,7 +33,7 @@ void test_locals(void) { __SVFloat32_t f32; __SVFloat64_t f64; - __SVBFloat16_t bf16; + __SVBfloat16_t bf16; __SVBool_t b8; } diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aba.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aba.c index c0b22200f630c..dfa151672c99f 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aba.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aba.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saba.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z13test_svaba_s8u10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z13test_svaba_s8u10__SVInt8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saba.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svaba_s8(svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saba.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svaba_s16u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z14test_svaba_s16u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saba.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_svaba_s16(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saba.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svaba_s32u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z14test_svaba_s32u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saba.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_svaba_s32(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saba.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svaba_s64u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z14test_svaba_s64u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saba.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svint64_t test_svaba_s64(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uaba.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z13test_svaba_u8u11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z13test_svaba_u8u11__SVUint8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uaba.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint8_t test_svaba_u8(svuint8_t op1, svuint8_t op2, svuint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uaba.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svaba_u16u12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z14test_svaba_u16u12__SVUint16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uaba.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -110,7 +110,7 @@ svuint16_t test_svaba_u16(svuint16_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uaba.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svaba_u32u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z14test_svaba_u32u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uaba.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -125,7 +125,7 @@ svuint32_t test_svaba_u32(svuint32_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uaba.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svaba_u64u12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z14test_svaba_u64u12__SVUint64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uaba.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -142,7 +142,7 @@ svuint64_t test_svaba_u64(svuint64_t op1, svuint64_t op2, svuint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saba.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svaba_n_s8u10__SVInt8_tu10__SVInt8_ta( +// CPP-CHECK-LABEL: @_Z15test_svaba_n_s8u10__SVInt8_tS_a( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -161,7 +161,7 @@ svint8_t test_svaba_n_s8(svint8_t op1, svint8_t op2, int8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saba.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svaba_n_s16u11__SVInt16_tu11__SVInt16_ts( +// CPP-CHECK-LABEL: @_Z16test_svaba_n_s16u11__SVInt16_tS_s( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -180,7 +180,7 @@ svint16_t test_svaba_n_s16(svint16_t op1, svint16_t op2, int16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saba.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svaba_n_s32u11__SVInt32_tu11__SVInt32_ti( +// CPP-CHECK-LABEL: @_Z16test_svaba_n_s32u11__SVInt32_tS_i( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -199,7 +199,7 @@ svint32_t test_svaba_n_s32(svint32_t op1, svint32_t op2, int32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saba.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svaba_n_s64u11__SVInt64_tu11__SVInt64_tl( +// CPP-CHECK-LABEL: @_Z16test_svaba_n_s64u11__SVInt64_tS_l( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -218,7 +218,7 @@ svint64_t test_svaba_n_s64(svint64_t op1, svint64_t op2, int64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uaba.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svaba_n_u8u11__SVUint8_tu11__SVUint8_th( +// CPP-CHECK-LABEL: @_Z15test_svaba_n_u8u11__SVUint8_tS_h( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -237,7 +237,7 @@ svuint8_t test_svaba_n_u8(svuint8_t op1, svuint8_t op2, uint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uaba.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svaba_n_u16u12__SVUint16_tu12__SVUint16_tt( +// CPP-CHECK-LABEL: @_Z16test_svaba_n_u16u12__SVUint16_tS_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -256,7 +256,7 @@ svuint16_t test_svaba_n_u16(svuint16_t op1, svuint16_t op2, uint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uaba.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svaba_n_u32u12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z16test_svaba_n_u32u12__SVUint32_tS_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -275,7 +275,7 @@ svuint32_t test_svaba_n_u32(svuint32_t op1, svuint32_t op2, uint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uaba.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svaba_n_u64u12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z16test_svaba_n_u64u12__SVUint64_tS_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_abalb.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_abalb.c index ca538c5644eeb..d60e3668874d5 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_abalb.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_abalb.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabalb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svabalb_s16u11__SVInt16_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svabalb_s16u11__SVInt16_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabalb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svabalb_s16(svint16_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabalb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svabalb_s32u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svabalb_s32u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabalb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svabalb_s32(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabalb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svabalb_s64u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svabalb_s64u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabalb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint64_t test_svabalb_s64(svint64_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabalb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svabalb_u16u12__SVUint16_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svabalb_u16u12__SVUint16_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabalb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svuint16_t test_svabalb_u16(svuint16_t op1, svuint8_t op2, svuint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabalb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svabalb_u32u12__SVUint32_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svabalb_u32u12__SVUint32_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabalb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint32_t test_svabalb_u32(svuint32_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabalb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svabalb_u64u12__SVUint64_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svabalb_u64u12__SVUint64_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabalb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_abalt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_abalt.c index 615dc6c4eae55..e47456a4ddf64 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_abalt.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_abalt.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabalt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svabalt_s16u11__SVInt16_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svabalt_s16u11__SVInt16_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabalt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svabalt_s16(svint16_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabalt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svabalt_s32u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svabalt_s32u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabalt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svabalt_s32(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabalt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svabalt_s64u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svabalt_s64u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabalt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint64_t test_svabalt_s64(svint64_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabalt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svabalt_u16u12__SVUint16_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svabalt_u16u12__SVUint16_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabalt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svuint16_t test_svabalt_u16(svuint16_t op1, svuint8_t op2, svuint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabalt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svabalt_u32u12__SVUint32_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svabalt_u32u12__SVUint32_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabalt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint32_t test_svabalt_u32(svuint32_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabalt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svabalt_u64u12__SVUint64_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svabalt_u64u12__SVUint64_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabalt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_abdlb.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_abdlb.c index 900c635e6a610..03c916c93c51c 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_abdlb.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_abdlb.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabdlb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svabdlb_s16u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svabdlb_s16u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabdlb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svabdlb_s16(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabdlb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svabdlb_s32u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svabdlb_s32u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabdlb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svabdlb_s32(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabdlb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svabdlb_s64u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svabdlb_s64u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabdlb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint64_t test_svabdlb_s64(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabdlb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svabdlb_u16u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svabdlb_u16u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabdlb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svuint16_t test_svabdlb_u16(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabdlb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svabdlb_u32u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svabdlb_u32u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabdlb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint32_t test_svabdlb_u32(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabdlb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svabdlb_u64u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svabdlb_u64u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabdlb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_abdlt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_abdlt.c index 5c8d8991ec37c..753705bf708f8 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_abdlt.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_abdlt.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabdlt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svabdlt_s16u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svabdlt_s16u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabdlt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svabdlt_s16(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabdlt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svabdlt_s32u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svabdlt_s32u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabdlt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svabdlt_s32(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabdlt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svabdlt_s64u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svabdlt_s64u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sabdlt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint64_t test_svabdlt_s64(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabdlt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svabdlt_u16u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svabdlt_u16u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabdlt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svuint16_t test_svabdlt_u16(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabdlt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svabdlt_u32u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svabdlt_u32u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabdlt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint32_t test_svabdlt_u32(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabdlt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svabdlt_u64u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svabdlt_u64u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uabdlt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_adclb.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_adclb.c index 3018525f36820..828fd1159de53 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_adclb.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_adclb.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adclb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svadclb_u32u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svadclb_u32u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adclb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svuint32_t test_svadclb_u32(svuint32_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adclb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svadclb_u64u12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svadclb_u64u12__SVUint64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adclb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -52,7 +52,7 @@ svuint64_t test_svadclb_u64(svuint64_t op1, svuint64_t op2, svuint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adclb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svadclb_n_u32u12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z18test_svadclb_n_u32u12__SVUint32_tS_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -71,7 +71,7 @@ svuint32_t test_svadclb_n_u32(svuint32_t op1, svuint32_t op2, uint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adclb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svadclb_n_u64u12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z18test_svadclb_n_u64u12__SVUint64_tS_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_adclt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_adclt.c index 299e59e855226..3c79d656cef99 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_adclt.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_adclt.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adclt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svadclt_u32u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svadclt_u32u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adclt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svuint32_t test_svadclt_u32(svuint32_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adclt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svadclt_u64u12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svadclt_u64u12__SVUint64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adclt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -52,7 +52,7 @@ svuint64_t test_svadclt_u64(svuint64_t op1, svuint64_t op2, svuint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adclt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svadclt_n_u32u12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z18test_svadclt_n_u32u12__SVUint32_tS_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -71,7 +71,7 @@ svuint32_t test_svadclt_n_u32(svuint32_t op1, svuint32_t op2, uint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.adclt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svadclt_n_u64u12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z18test_svadclt_n_u64u12__SVUint64_tS_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_addhnb.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_addhnb.c index 940ed594b4246..e3dd2559c0f54 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_addhnb.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_addhnb.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addhnb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svaddhnb_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svaddhnb_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addhnb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svaddhnb_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addhnb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svaddhnb_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svaddhnb_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addhnb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_svaddhnb_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addhnb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svaddhnb_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svaddhnb_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addhnb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_svaddhnb_s64(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addhnb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svaddhnb_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svaddhnb_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addhnb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svuint8_t test_svaddhnb_u16(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addhnb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svaddhnb_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svaddhnb_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addhnb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint16_t test_svaddhnb_u32(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addhnb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svaddhnb_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svaddhnb_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addhnb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_addhnt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_addhnt.c index 00a754c3bef06..942155949cb99 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_addhnt.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_addhnt.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addhnt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svaddhnt_s16u10__SVInt8_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svaddhnt_s16u10__SVInt8_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addhnt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svaddhnt_s16(svint8_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addhnt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svaddhnt_s32u11__SVInt16_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svaddhnt_s32u11__SVInt16_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addhnt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_svaddhnt_s32(svint16_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addhnt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svaddhnt_s64u11__SVInt32_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svaddhnt_s64u11__SVInt32_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addhnt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_svaddhnt_s64(svint32_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addhnt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svaddhnt_u16u11__SVUint8_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svaddhnt_u16u11__SVUint8_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addhnt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svuint8_t test_svaddhnt_u16(svuint8_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addhnt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svaddhnt_u32u12__SVUint16_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svaddhnt_u32u12__SVUint16_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addhnt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint16_t test_svaddhnt_u32(svuint16_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addhnt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svaddhnt_u64u12__SVUint32_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svaddhnt_u64u12__SVUint32_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addhnt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_addlb.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_addlb.c index 0bfe9f84ab532..5ac61479b07d3 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_addlb.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_addlb.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saddlb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svaddlb_s16u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svaddlb_s16u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saddlb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svaddlb_s16(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saddlb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svaddlb_s32u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svaddlb_s32u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saddlb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svaddlb_s32(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saddlb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svaddlb_s64u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svaddlb_s64u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saddlb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint64_t test_svaddlb_s64(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uaddlb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svaddlb_u16u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svaddlb_u16u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uaddlb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svuint16_t test_svaddlb_u16(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uaddlb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svaddlb_u32u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svaddlb_u32u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uaddlb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint32_t test_svaddlb_u32(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uaddlb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svaddlb_u64u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svaddlb_u64u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uaddlb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_addlbt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_addlbt.c index 5a9a4b0c198ff..a1358429db364 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_addlbt.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_addlbt.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saddlbt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svaddlbt_s16u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svaddlbt_s16u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saddlbt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svaddlbt_s16(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saddlbt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svaddlbt_s32u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svaddlbt_s32u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saddlbt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svaddlbt_s32(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saddlbt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svaddlbt_s64u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svaddlbt_s64u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saddlbt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_addlt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_addlt.c index 0024efa7b47b4..99f67036ddee8 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_addlt.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_addlt.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saddlt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svaddlt_s16u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svaddlt_s16u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saddlt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svaddlt_s16(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saddlt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svaddlt_s32u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svaddlt_s32u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saddlt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svaddlt_s32(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saddlt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svaddlt_s64u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svaddlt_s64u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.saddlt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint64_t test_svaddlt_s64(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uaddlt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svaddlt_u16u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svaddlt_u16u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uaddlt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svuint16_t test_svaddlt_u16(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uaddlt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svaddlt_u32u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svaddlt_u32u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uaddlt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint32_t test_svaddlt_u32(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uaddlt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svaddlt_u64u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svaddlt_u64u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uaddlt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_addp.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_addp.c index d733e366cf80a..cf6c47eaaeab9 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_addp.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_addp.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addp.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svaddp_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svaddp_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addp.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -36,7 +36,7 @@ svint8_t test_svaddp_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.addp.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svaddp_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svaddp_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.addp.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -53,7 +53,7 @@ svint16_t test_svaddp_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.addp.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svaddp_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svaddp_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.addp.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -70,7 +70,7 @@ svint32_t test_svaddp_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.addp.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svaddp_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svaddp_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.addp.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -86,7 +86,7 @@ svint64_t test_svaddp_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addp.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svaddp_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svaddp_u8_mu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addp.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -102,7 +102,7 @@ svuint8_t test_svaddp_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.addp.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svaddp_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svaddp_u16_mu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.addp.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -119,7 +119,7 @@ svuint16_t test_svaddp_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.addp.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svaddp_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svaddp_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.addp.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -136,7 +136,7 @@ svuint32_t test_svaddp_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.addp.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svaddp_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svaddp_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.addp.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -152,7 +152,7 @@ svuint64_t test_svaddp_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addp.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svaddp_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svaddp_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addp.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -168,7 +168,7 @@ svint8_t test_svaddp_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.addp.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svaddp_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svaddp_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.addp.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -185,7 +185,7 @@ svint16_t test_svaddp_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.addp.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svaddp_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svaddp_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.addp.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -202,7 +202,7 @@ svint32_t test_svaddp_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.addp.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svaddp_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svaddp_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.addp.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -218,7 +218,7 @@ svint64_t test_svaddp_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addp.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svaddp_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svaddp_u8_xu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.addp.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -234,7 +234,7 @@ svuint8_t test_svaddp_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.addp.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svaddp_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svaddp_u16_xu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.addp.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -251,7 +251,7 @@ svuint16_t test_svaddp_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.addp.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svaddp_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svaddp_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.addp.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -268,7 +268,7 @@ svuint32_t test_svaddp_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.addp.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svaddp_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svaddp_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.addp.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -285,7 +285,7 @@ svuint64_t test_svaddp_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.faddp.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svaddp_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svaddp_f16_mu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.faddp.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -302,7 +302,7 @@ svfloat16_t test_svaddp_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.faddp.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svaddp_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svaddp_f32_mu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.faddp.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -319,7 +319,7 @@ svfloat32_t test_svaddp_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.faddp.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svaddp_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svaddp_f64_mu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.faddp.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -336,7 +336,7 @@ svfloat64_t test_svaddp_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.faddp.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svaddp_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svaddp_f16_xu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.faddp.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -353,7 +353,7 @@ svfloat16_t test_svaddp_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.faddp.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svaddp_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svaddp_f32_xu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.faddp.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -370,7 +370,7 @@ svfloat32_t test_svaddp_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.faddp.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svaddp_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svaddp_f64_xu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.faddp.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesd.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesd.c index 4376cd854eb6a..70947df259446 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesd.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesd.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.aesd( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svaesd_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svaesd_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.aesd( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aese.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aese.c index cfd5855b2f41f..718bb82e430da 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aese.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aese.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.aese( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svaese_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svaese_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.aese( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bcax.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bcax.c index 8a53ce6fa26d9..14b7060c6c2a2 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bcax.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bcax.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bcax.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svbcax_s8u10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z14test_svbcax_s8u10__SVInt8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bcax.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svbcax_s8(svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bcax.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbcax_s16u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z15test_svbcax_s16u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bcax.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_svbcax_s16(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bcax.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbcax_s32u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z15test_svbcax_s32u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bcax.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_svbcax_s32(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bcax.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbcax_s64u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z15test_svbcax_s64u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bcax.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svint64_t test_svbcax_s64(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bcax.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svbcax_u8u11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svbcax_u8u11__SVUint8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bcax.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint8_t test_svbcax_u8(svuint8_t op1, svuint8_t op2, svuint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bcax.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbcax_u16u12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z15test_svbcax_u16u12__SVUint16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bcax.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -110,7 +110,7 @@ svuint16_t test_svbcax_u16(svuint16_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bcax.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbcax_u32u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z15test_svbcax_u32u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bcax.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -125,7 +125,7 @@ svuint32_t test_svbcax_u32(svuint32_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bcax.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbcax_u64u12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z15test_svbcax_u64u12__SVUint64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bcax.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -142,7 +142,7 @@ svuint64_t test_svbcax_u64(svuint64_t op1, svuint64_t op2, svuint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bcax.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svbcax_n_s8u10__SVInt8_tu10__SVInt8_ta( +// CPP-CHECK-LABEL: @_Z16test_svbcax_n_s8u10__SVInt8_tS_a( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -161,7 +161,7 @@ svint8_t test_svbcax_n_s8(svint8_t op1, svint8_t op2, int8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bcax.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svbcax_n_s16u11__SVInt16_tu11__SVInt16_ts( +// CPP-CHECK-LABEL: @_Z17test_svbcax_n_s16u11__SVInt16_tS_s( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -180,7 +180,7 @@ svint16_t test_svbcax_n_s16(svint16_t op1, svint16_t op2, int16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bcax.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svbcax_n_s32u11__SVInt32_tu11__SVInt32_ti( +// CPP-CHECK-LABEL: @_Z17test_svbcax_n_s32u11__SVInt32_tS_i( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -199,7 +199,7 @@ svint32_t test_svbcax_n_s32(svint32_t op1, svint32_t op2, int32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bcax.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svbcax_n_s64u11__SVInt64_tu11__SVInt64_tl( +// CPP-CHECK-LABEL: @_Z17test_svbcax_n_s64u11__SVInt64_tS_l( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -218,7 +218,7 @@ svint64_t test_svbcax_n_s64(svint64_t op1, svint64_t op2, int64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bcax.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svbcax_n_u8u11__SVUint8_tu11__SVUint8_th( +// CPP-CHECK-LABEL: @_Z16test_svbcax_n_u8u11__SVUint8_tS_h( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -237,7 +237,7 @@ svuint8_t test_svbcax_n_u8(svuint8_t op1, svuint8_t op2, uint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bcax.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svbcax_n_u16u12__SVUint16_tu12__SVUint16_tt( +// CPP-CHECK-LABEL: @_Z17test_svbcax_n_u16u12__SVUint16_tS_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -256,7 +256,7 @@ svuint16_t test_svbcax_n_u16(svuint16_t op1, svuint16_t op2, uint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bcax.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svbcax_n_u32u12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z17test_svbcax_n_u32u12__SVUint32_tS_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -275,7 +275,7 @@ svuint32_t test_svbcax_n_u32(svuint32_t op1, svuint32_t op2, uint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bcax.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svbcax_n_u64u12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z17test_svbcax_n_u64u12__SVUint64_tS_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bdep.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bdep.c index b98857705a2e2..ee769ec20e733 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bdep.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bdep.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bdep.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svbdep_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svbdep_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bdep.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svuint8_t test_svbdep_u8(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bdep.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbdep_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z15test_svbdep_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bdep.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svuint16_t test_svbdep_u16(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bdep.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbdep_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z15test_svbdep_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bdep.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svuint32_t test_svbdep_u32(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bdep.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbdep_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z15test_svbdep_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bdep.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bext.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bext.c index a49c097ee43c7..c8bd76c452cc6 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bext.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bext.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bext.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svbext_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svbext_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bext.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svuint8_t test_svbext_u8(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bext.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbext_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z15test_svbext_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bext.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svuint16_t test_svbext_u16(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bext.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbext_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z15test_svbext_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bext.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svuint32_t test_svbext_u32(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bext.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbext_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z15test_svbext_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bext.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bgrp.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bgrp.c index 984c5b6c51d3a..f202e8f1ad675 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bgrp.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bgrp.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bgrp.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svbgrp_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svbgrp_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bgrp.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svuint8_t test_svbgrp_u8(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bgrp.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbgrp_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z15test_svbgrp_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bgrp.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svuint16_t test_svbgrp_u16(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bgrp.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbgrp_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z15test_svbgrp_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bgrp.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svuint32_t test_svbgrp_u32(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bgrp.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbgrp_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z15test_svbgrp_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bgrp.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bsl.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bsl.c index 7b345c6a00d97..d84b258856b51 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bsl.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bsl.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z13test_svbsl_s8u10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z13test_svbsl_s8u10__SVInt8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svbsl_s8(svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svbsl_s16u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z14test_svbsl_s16u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_svbsl_s16(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svbsl_s32u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z14test_svbsl_s32u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_svbsl_s32(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svbsl_s64u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z14test_svbsl_s64u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svint64_t test_svbsl_s64(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z13test_svbsl_u8u11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z13test_svbsl_u8u11__SVUint8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint8_t test_svbsl_u8(svuint8_t op1, svuint8_t op2, svuint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svbsl_u16u12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z14test_svbsl_u16u12__SVUint16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -110,7 +110,7 @@ svuint16_t test_svbsl_u16(svuint16_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svbsl_u32u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z14test_svbsl_u32u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -125,7 +125,7 @@ svuint32_t test_svbsl_u32(svuint32_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svbsl_u64u12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z14test_svbsl_u64u12__SVUint64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -142,7 +142,7 @@ svuint64_t test_svbsl_u64(svuint64_t op1, svuint64_t op2, svuint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbsl_n_s8u10__SVInt8_tu10__SVInt8_ta( +// CPP-CHECK-LABEL: @_Z15test_svbsl_n_s8u10__SVInt8_tS_a( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -161,7 +161,7 @@ svint8_t test_svbsl_n_s8(svint8_t op1, svint8_t op2, int8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svbsl_n_s16u11__SVInt16_tu11__SVInt16_ts( +// CPP-CHECK-LABEL: @_Z16test_svbsl_n_s16u11__SVInt16_tS_s( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -180,7 +180,7 @@ svint16_t test_svbsl_n_s16(svint16_t op1, svint16_t op2, int16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svbsl_n_s32u11__SVInt32_tu11__SVInt32_ti( +// CPP-CHECK-LABEL: @_Z16test_svbsl_n_s32u11__SVInt32_tS_i( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -199,7 +199,7 @@ svint32_t test_svbsl_n_s32(svint32_t op1, svint32_t op2, int32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svbsl_n_s64u11__SVInt64_tu11__SVInt64_tl( +// CPP-CHECK-LABEL: @_Z16test_svbsl_n_s64u11__SVInt64_tS_l( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -218,7 +218,7 @@ svint64_t test_svbsl_n_s64(svint64_t op1, svint64_t op2, int64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbsl_n_u8u11__SVUint8_tu11__SVUint8_th( +// CPP-CHECK-LABEL: @_Z15test_svbsl_n_u8u11__SVUint8_tS_h( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -237,7 +237,7 @@ svuint8_t test_svbsl_n_u8(svuint8_t op1, svuint8_t op2, uint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svbsl_n_u16u12__SVUint16_tu12__SVUint16_tt( +// CPP-CHECK-LABEL: @_Z16test_svbsl_n_u16u12__SVUint16_tS_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -256,7 +256,7 @@ svuint16_t test_svbsl_n_u16(svuint16_t op1, svuint16_t op2, uint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svbsl_n_u32u12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z16test_svbsl_n_u32u12__SVUint32_tS_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -275,7 +275,7 @@ svuint32_t test_svbsl_n_u32(svuint32_t op1, svuint32_t op2, uint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svbsl_n_u64u12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z16test_svbsl_n_u64u12__SVUint64_tS_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bsl1n.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bsl1n.c index 11f30554adbf9..6d38563a8b772 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bsl1n.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bsl1n.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl1n.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbsl1n_s8u10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svbsl1n_s8u10__SVInt8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl1n.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svbsl1n_s8(svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl1n.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svbsl1n_s16u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svbsl1n_s16u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl1n.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_svbsl1n_s16(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl1n.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svbsl1n_s32u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svbsl1n_s32u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl1n.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_svbsl1n_s32(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl1n.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svbsl1n_s64u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svbsl1n_s64u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl1n.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svint64_t test_svbsl1n_s64(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl1n.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbsl1n_u8u11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svbsl1n_u8u11__SVUint8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl1n.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint8_t test_svbsl1n_u8(svuint8_t op1, svuint8_t op2, svuint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl1n.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svbsl1n_u16u12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svbsl1n_u16u12__SVUint16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl1n.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -110,7 +110,7 @@ svuint16_t test_svbsl1n_u16(svuint16_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl1n.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svbsl1n_u32u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svbsl1n_u32u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl1n.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -125,7 +125,7 @@ svuint32_t test_svbsl1n_u32(svuint32_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl1n.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svbsl1n_u64u12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svbsl1n_u64u12__SVUint64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl1n.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -142,7 +142,7 @@ svuint64_t test_svbsl1n_u64(svuint64_t op1, svuint64_t op2, svuint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl1n.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svbsl1n_n_s8u10__SVInt8_tu10__SVInt8_ta( +// CPP-CHECK-LABEL: @_Z17test_svbsl1n_n_s8u10__SVInt8_tS_a( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -161,7 +161,7 @@ svint8_t test_svbsl1n_n_s8(svint8_t op1, svint8_t op2, int8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl1n.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svbsl1n_n_s16u11__SVInt16_tu11__SVInt16_ts( +// CPP-CHECK-LABEL: @_Z18test_svbsl1n_n_s16u11__SVInt16_tS_s( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -180,7 +180,7 @@ svint16_t test_svbsl1n_n_s16(svint16_t op1, svint16_t op2, int16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl1n.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svbsl1n_n_s32u11__SVInt32_tu11__SVInt32_ti( +// CPP-CHECK-LABEL: @_Z18test_svbsl1n_n_s32u11__SVInt32_tS_i( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -199,7 +199,7 @@ svint32_t test_svbsl1n_n_s32(svint32_t op1, svint32_t op2, int32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl1n.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svbsl1n_n_s64u11__SVInt64_tu11__SVInt64_tl( +// CPP-CHECK-LABEL: @_Z18test_svbsl1n_n_s64u11__SVInt64_tS_l( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -218,7 +218,7 @@ svint64_t test_svbsl1n_n_s64(svint64_t op1, svint64_t op2, int64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl1n.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svbsl1n_n_u8u11__SVUint8_tu11__SVUint8_th( +// CPP-CHECK-LABEL: @_Z17test_svbsl1n_n_u8u11__SVUint8_tS_h( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -237,7 +237,7 @@ svuint8_t test_svbsl1n_n_u8(svuint8_t op1, svuint8_t op2, uint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl1n.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svbsl1n_n_u16u12__SVUint16_tu12__SVUint16_tt( +// CPP-CHECK-LABEL: @_Z18test_svbsl1n_n_u16u12__SVUint16_tS_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -256,7 +256,7 @@ svuint16_t test_svbsl1n_n_u16(svuint16_t op1, svuint16_t op2, uint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl1n.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svbsl1n_n_u32u12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z18test_svbsl1n_n_u32u12__SVUint32_tS_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -275,7 +275,7 @@ svuint32_t test_svbsl1n_n_u32(svuint32_t op1, svuint32_t op2, uint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl1n.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svbsl1n_n_u64u12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z18test_svbsl1n_n_u64u12__SVUint64_tS_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bsl2n.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bsl2n.c index 8dd861c8b6a69..d59616482e150 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bsl2n.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_bsl2n.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl2n.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbsl2n_s8u10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svbsl2n_s8u10__SVInt8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl2n.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svbsl2n_s8(svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl2n.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svbsl2n_s16u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svbsl2n_s16u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl2n.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_svbsl2n_s16(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl2n.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svbsl2n_s32u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svbsl2n_s32u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl2n.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_svbsl2n_s32(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl2n.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svbsl2n_s64u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svbsl2n_s64u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl2n.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svint64_t test_svbsl2n_s64(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl2n.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svbsl2n_u8u11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svbsl2n_u8u11__SVUint8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl2n.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint8_t test_svbsl2n_u8(svuint8_t op1, svuint8_t op2, svuint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl2n.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svbsl2n_u16u12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svbsl2n_u16u12__SVUint16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl2n.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -110,7 +110,7 @@ svuint16_t test_svbsl2n_u16(svuint16_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl2n.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svbsl2n_u32u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svbsl2n_u32u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl2n.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -125,7 +125,7 @@ svuint32_t test_svbsl2n_u32(svuint32_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl2n.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svbsl2n_u64u12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svbsl2n_u64u12__SVUint64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl2n.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -142,7 +142,7 @@ svuint64_t test_svbsl2n_u64(svuint64_t op1, svuint64_t op2, svuint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl2n.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svbsl2n_n_s8u10__SVInt8_tu10__SVInt8_ta( +// CPP-CHECK-LABEL: @_Z17test_svbsl2n_n_s8u10__SVInt8_tS_a( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -161,7 +161,7 @@ svint8_t test_svbsl2n_n_s8(svint8_t op1, svint8_t op2, int8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl2n.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svbsl2n_n_s16u11__SVInt16_tu11__SVInt16_ts( +// CPP-CHECK-LABEL: @_Z18test_svbsl2n_n_s16u11__SVInt16_tS_s( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -180,7 +180,7 @@ svint16_t test_svbsl2n_n_s16(svint16_t op1, svint16_t op2, int16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl2n.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svbsl2n_n_s32u11__SVInt32_tu11__SVInt32_ti( +// CPP-CHECK-LABEL: @_Z18test_svbsl2n_n_s32u11__SVInt32_tS_i( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -199,7 +199,7 @@ svint32_t test_svbsl2n_n_s32(svint32_t op1, svint32_t op2, int32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl2n.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svbsl2n_n_s64u11__SVInt64_tu11__SVInt64_tl( +// CPP-CHECK-LABEL: @_Z18test_svbsl2n_n_s64u11__SVInt64_tS_l( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -218,7 +218,7 @@ svint64_t test_svbsl2n_n_s64(svint64_t op1, svint64_t op2, int64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl2n.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svbsl2n_n_u8u11__SVUint8_tu11__SVUint8_th( +// CPP-CHECK-LABEL: @_Z17test_svbsl2n_n_u8u11__SVUint8_tS_h( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -237,7 +237,7 @@ svuint8_t test_svbsl2n_n_u8(svuint8_t op1, svuint8_t op2, uint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl2n.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svbsl2n_n_u16u12__SVUint16_tu12__SVUint16_tt( +// CPP-CHECK-LABEL: @_Z18test_svbsl2n_n_u16u12__SVUint16_tS_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -256,7 +256,7 @@ svuint16_t test_svbsl2n_n_u16(svuint16_t op1, svuint16_t op2, uint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl2n.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svbsl2n_n_u32u12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z18test_svbsl2n_n_u32u12__SVUint32_tS_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -275,7 +275,7 @@ svuint32_t test_svbsl2n_n_u32(svuint32_t op1, svuint32_t op2, uint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bsl2n.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svbsl2n_n_u64u12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z18test_svbsl2n_n_u64u12__SVUint64_tS_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cadd.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cadd.c index 3f09fa66f842e..067174e67b888 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cadd.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cadd.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svcadd_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z14test_svcadd_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svcadd_s8(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svcadd_s8_1u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svcadd_s8_1u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint8_t test_svcadd_s8_1(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcadd_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z15test_svcadd_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint16_t test_svcadd_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcadd_s16_1u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svcadd_s16_1u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svint16_t test_svcadd_s16_1(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcadd_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z15test_svcadd_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svint32_t test_svcadd_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcadd_s32_1u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svcadd_s32_1u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -110,7 +110,7 @@ svint32_t test_svcadd_s32_1(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcadd_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z15test_svcadd_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -125,7 +125,7 @@ svint64_t test_svcadd_s64(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcadd_s64_1u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svcadd_s64_1u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -140,7 +140,7 @@ svint64_t test_svcadd_s64_1(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svcadd_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svcadd_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -155,7 +155,7 @@ svuint8_t test_svcadd_u8(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svcadd_u8_1u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svcadd_u8_1u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -170,7 +170,7 @@ svuint8_t test_svcadd_u8_1(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcadd_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z15test_svcadd_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -185,7 +185,7 @@ svuint16_t test_svcadd_u16(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcadd_u16_1u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svcadd_u16_1u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -200,7 +200,7 @@ svuint16_t test_svcadd_u16_1(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcadd_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z15test_svcadd_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -215,7 +215,7 @@ svuint32_t test_svcadd_u32(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcadd_u32_1u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svcadd_u32_1u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -230,7 +230,7 @@ svuint32_t test_svcadd_u32_1(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcadd_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z15test_svcadd_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -245,7 +245,7 @@ svuint64_t test_svcadd_u64(svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcadd_u64_1u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svcadd_u64_1u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cadd.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cdot.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cdot.c index 8a0ec28d2db5f..158224040c467 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cdot.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cdot.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cdot.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcdot_s32u11__SVInt32_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svcdot_s32u11__SVInt32_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cdot.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint32_t test_svcdot_s32(svint32_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cdot.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcdot_s32_1u11__SVInt32_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svcdot_s32_1u11__SVInt32_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cdot.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svcdot_s32_1(svint32_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cdot.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcdot_s32_2u11__SVInt32_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svcdot_s32_2u11__SVInt32_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cdot.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_svcdot_s32_2(svint32_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cdot.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcdot_s32_3u11__SVInt32_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svcdot_s32_3u11__SVInt32_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cdot.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svint32_t test_svcdot_s32_3(svint32_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cdot.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcdot_s64u11__SVInt64_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z15test_svcdot_s64u11__SVInt64_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cdot.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svint64_t test_svcdot_s64(svint64_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cdot.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcdot_s64_1u11__SVInt64_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svcdot_s64_1u11__SVInt64_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cdot.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -110,7 +110,7 @@ svint64_t test_svcdot_s64_1(svint64_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cdot.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcdot_s64_2u11__SVInt64_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svcdot_s64_2u11__SVInt64_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cdot.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -125,7 +125,7 @@ svint64_t test_svcdot_s64_2(svint64_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cdot.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcdot_s64_3u11__SVInt64_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svcdot_s64_3u11__SVInt64_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cdot.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -140,7 +140,7 @@ svint64_t test_svcdot_s64_3(svint64_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cdot.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0, i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z20test_svcdot_lane_s32u11__SVInt32_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z20test_svcdot_lane_s32u11__SVInt32_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cdot.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0, i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -155,7 +155,7 @@ svint32_t test_svcdot_lane_s32(svint32_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cdot.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 2, i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z22test_svcdot_lane_s32_1u11__SVInt32_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z22test_svcdot_lane_s32_1u11__SVInt32_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cdot.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 2, i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -170,7 +170,7 @@ svint32_t test_svcdot_lane_s32_1(svint32_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cdot.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0, i32 180) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z20test_svcdot_lane_s64u11__SVInt64_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z20test_svcdot_lane_s64u11__SVInt64_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cdot.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0, i32 180) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cmla.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cmla.c index a262b238c09a8..23803a71e05f3 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cmla.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cmla.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svcmla_s8u10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z14test_svcmla_s8u10__SVInt8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svcmla_s8(svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svcmla_s8_1u10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svcmla_s8_1u10__SVInt8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint8_t test_svcmla_s8_1(svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svcmla_s8_2u10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svcmla_s8_2u10__SVInt8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint8_t test_svcmla_s8_2(svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svcmla_s8_3u10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svcmla_s8_3u10__SVInt8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svint8_t test_svcmla_s8_3(svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcmla_s16u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z15test_svcmla_s16u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svint16_t test_svcmla_s16(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_s16_1u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_s16_1u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -110,7 +110,7 @@ svint16_t test_svcmla_s16_1(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_s16_2u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_s16_2u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -125,7 +125,7 @@ svint16_t test_svcmla_s16_2(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_s16_3u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_s16_3u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -140,7 +140,7 @@ svint16_t test_svcmla_s16_3(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcmla_s32u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z15test_svcmla_s32u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -155,7 +155,7 @@ svint32_t test_svcmla_s32(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_s32_1u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_s32_1u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -170,7 +170,7 @@ svint32_t test_svcmla_s32_1(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_s32_2u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_s32_2u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -185,7 +185,7 @@ svint32_t test_svcmla_s32_2(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_s32_3u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_s32_3u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -200,7 +200,7 @@ svint32_t test_svcmla_s32_3(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcmla_s64u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z15test_svcmla_s64u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -215,7 +215,7 @@ svint64_t test_svcmla_s64(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_s64_1u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_s64_1u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -230,7 +230,7 @@ svint64_t test_svcmla_s64_1(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_s64_2u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_s64_2u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -245,7 +245,7 @@ svint64_t test_svcmla_s64_2(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_s64_3u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_s64_3u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -260,7 +260,7 @@ svint64_t test_svcmla_s64_3(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svcmla_u8u11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svcmla_u8u11__SVUint8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -275,7 +275,7 @@ svuint8_t test_svcmla_u8(svuint8_t op1, svuint8_t op2, svuint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svcmla_u8_1u11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svcmla_u8_1u11__SVUint8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -290,7 +290,7 @@ svuint8_t test_svcmla_u8_1(svuint8_t op1, svuint8_t op2, svuint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svcmla_u8_2u11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svcmla_u8_2u11__SVUint8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -305,7 +305,7 @@ svuint8_t test_svcmla_u8_2(svuint8_t op1, svuint8_t op2, svuint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svcmla_u8_3u11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svcmla_u8_3u11__SVUint8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -320,7 +320,7 @@ svuint8_t test_svcmla_u8_3(svuint8_t op1, svuint8_t op2, svuint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcmla_u16u12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z15test_svcmla_u16u12__SVUint16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -335,7 +335,7 @@ svuint16_t test_svcmla_u16(svuint16_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_u16_1u12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_u16_1u12__SVUint16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -350,7 +350,7 @@ svuint16_t test_svcmla_u16_1(svuint16_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_u16_2u12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_u16_2u12__SVUint16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -365,7 +365,7 @@ svuint16_t test_svcmla_u16_2(svuint16_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_u16_3u12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_u16_3u12__SVUint16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -380,7 +380,7 @@ svuint16_t test_svcmla_u16_3(svuint16_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcmla_u32u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z15test_svcmla_u32u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -395,7 +395,7 @@ svuint32_t test_svcmla_u32(svuint32_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_u32_1u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_u32_1u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -410,7 +410,7 @@ svuint32_t test_svcmla_u32_1(svuint32_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_u32_2u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_u32_2u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -425,7 +425,7 @@ svuint32_t test_svcmla_u32_2(svuint32_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_u32_3u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_u32_3u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -440,7 +440,7 @@ svuint32_t test_svcmla_u32_3(svuint32_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svcmla_u64u12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z15test_svcmla_u64u12__SVUint64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -455,7 +455,7 @@ svuint64_t test_svcmla_u64(svuint64_t op1, svuint64_t op2, svuint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_u64_1u12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_u64_1u12__SVUint64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -470,7 +470,7 @@ svuint64_t test_svcmla_u64_1(svuint64_t op1, svuint64_t op2, svuint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_u64_2u12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_u64_2u12__SVUint64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -485,7 +485,7 @@ svuint64_t test_svcmla_u64_2(svuint64_t op1, svuint64_t op2, svuint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svcmla_u64_3u12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svcmla_u64_3u12__SVUint64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -500,7 +500,7 @@ svuint64_t test_svcmla_u64_3(svuint64_t op1, svuint64_t op2, svuint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.lane.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0, i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z20test_svcmla_lane_s16u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z20test_svcmla_lane_s16u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.lane.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0, i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -515,7 +515,7 @@ svint16_t test_svcmla_lane_s16(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.lane.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3, i32 180) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z22test_svcmla_lane_s16_1u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z22test_svcmla_lane_s16_1u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.lane.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3, i32 180) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -530,7 +530,7 @@ svint16_t test_svcmla_lane_s16_1(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.lane.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0, i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z20test_svcmla_lane_s32u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z20test_svcmla_lane_s32u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.lane.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0, i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -545,7 +545,7 @@ svint32_t test_svcmla_lane_s32(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.lane.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1, i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z22test_svcmla_lane_s32_1u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z22test_svcmla_lane_s32_1u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.lane.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1, i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -560,7 +560,7 @@ svint32_t test_svcmla_lane_s32_1(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.lane.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0, i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z20test_svcmla_lane_u16u12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z20test_svcmla_lane_u16u12__SVUint16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.lane.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0, i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -575,7 +575,7 @@ svuint16_t test_svcmla_lane_u16(svuint16_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.lane.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3, i32 180) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z22test_svcmla_lane_u16_1u12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z22test_svcmla_lane_u16_1u12__SVUint16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.lane.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3, i32 180) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -590,7 +590,7 @@ svuint16_t test_svcmla_lane_u16_1(svuint16_t op1, svuint16_t op2, svuint16_t op3 // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.lane.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0, i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z20test_svcmla_lane_u32u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z20test_svcmla_lane_u32u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.lane.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0, i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -605,7 +605,7 @@ svuint32_t test_svcmla_lane_u32(svuint32_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.lane.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1, i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z22test_svcmla_lane_u32_1u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z22test_svcmla_lane_u32_1u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.cmla.lane.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1, i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_eor3.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_eor3.c index 16177ff27ff9e..645f52b182a67 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_eor3.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_eor3.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor3.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_sveor3_s8u10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z14test_sveor3_s8u10__SVInt8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor3.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_sveor3_s8(svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor3.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_sveor3_s16u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z15test_sveor3_s16u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor3.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_sveor3_s16(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor3.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_sveor3_s32u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z15test_sveor3_s32u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor3.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_sveor3_s32(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor3.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_sveor3_s64u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z15test_sveor3_s64u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor3.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svint64_t test_sveor3_s64(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor3.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_sveor3_u8u11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_sveor3_u8u11__SVUint8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor3.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint8_t test_sveor3_u8(svuint8_t op1, svuint8_t op2, svuint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor3.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_sveor3_u16u12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z15test_sveor3_u16u12__SVUint16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor3.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -110,7 +110,7 @@ svuint16_t test_sveor3_u16(svuint16_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor3.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_sveor3_u32u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z15test_sveor3_u32u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor3.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -125,7 +125,7 @@ svuint32_t test_sveor3_u32(svuint32_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor3.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_sveor3_u64u12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z15test_sveor3_u64u12__SVUint64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor3.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -142,7 +142,7 @@ svuint64_t test_sveor3_u64(svuint64_t op1, svuint64_t op2, svuint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor3.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_sveor3_n_s8u10__SVInt8_tu10__SVInt8_ta( +// CPP-CHECK-LABEL: @_Z16test_sveor3_n_s8u10__SVInt8_tS_a( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -161,7 +161,7 @@ svint8_t test_sveor3_n_s8(svint8_t op1, svint8_t op2, int8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor3.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_sveor3_n_s16u11__SVInt16_tu11__SVInt16_ts( +// CPP-CHECK-LABEL: @_Z17test_sveor3_n_s16u11__SVInt16_tS_s( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -180,7 +180,7 @@ svint16_t test_sveor3_n_s16(svint16_t op1, svint16_t op2, int16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor3.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_sveor3_n_s32u11__SVInt32_tu11__SVInt32_ti( +// CPP-CHECK-LABEL: @_Z17test_sveor3_n_s32u11__SVInt32_tS_i( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -199,7 +199,7 @@ svint32_t test_sveor3_n_s32(svint32_t op1, svint32_t op2, int32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor3.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_sveor3_n_s64u11__SVInt64_tu11__SVInt64_tl( +// CPP-CHECK-LABEL: @_Z17test_sveor3_n_s64u11__SVInt64_tS_l( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -218,7 +218,7 @@ svint64_t test_sveor3_n_s64(svint64_t op1, svint64_t op2, int64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor3.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_sveor3_n_u8u11__SVUint8_tu11__SVUint8_th( +// CPP-CHECK-LABEL: @_Z16test_sveor3_n_u8u11__SVUint8_tS_h( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -237,7 +237,7 @@ svuint8_t test_sveor3_n_u8(svuint8_t op1, svuint8_t op2, uint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor3.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_sveor3_n_u16u12__SVUint16_tu12__SVUint16_tt( +// CPP-CHECK-LABEL: @_Z17test_sveor3_n_u16u12__SVUint16_tS_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -256,7 +256,7 @@ svuint16_t test_sveor3_n_u16(svuint16_t op1, svuint16_t op2, uint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor3.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_sveor3_n_u32u12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z17test_sveor3_n_u32u12__SVUint32_tS_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -275,7 +275,7 @@ svuint32_t test_sveor3_n_u32(svuint32_t op1, svuint32_t op2, uint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eor3.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_sveor3_n_u64u12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z17test_sveor3_n_u64u12__SVUint64_tS_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_eorbt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_eorbt.c index efb15d6d2eed8..57ee9b4324b34 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_eorbt.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_eorbt.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eorbt.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_sveorbt_s8u10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_sveorbt_s8u10__SVInt8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eorbt.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_sveorbt_s8(svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eorbt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_sveorbt_s16u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_sveorbt_s16u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eorbt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_sveorbt_s16(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eorbt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_sveorbt_s32u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_sveorbt_s32u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eorbt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_sveorbt_s32(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eorbt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_sveorbt_s64u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_sveorbt_s64u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eorbt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svint64_t test_sveorbt_s64(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eorbt.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_sveorbt_u8u11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_sveorbt_u8u11__SVUint8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eorbt.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint8_t test_sveorbt_u8(svuint8_t op1, svuint8_t op2, svuint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eorbt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_sveorbt_u16u12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_sveorbt_u16u12__SVUint16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eorbt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -110,7 +110,7 @@ svuint16_t test_sveorbt_u16(svuint16_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eorbt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_sveorbt_u32u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_sveorbt_u32u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eorbt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -125,7 +125,7 @@ svuint32_t test_sveorbt_u32(svuint32_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eorbt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_sveorbt_u64u12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_sveorbt_u64u12__SVUint64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eorbt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -142,7 +142,7 @@ svuint64_t test_sveorbt_u64(svuint64_t op1, svuint64_t op2, svuint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eorbt.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_sveorbt_n_s8u10__SVInt8_tu10__SVInt8_ta( +// CPP-CHECK-LABEL: @_Z17test_sveorbt_n_s8u10__SVInt8_tS_a( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -161,7 +161,7 @@ svint8_t test_sveorbt_n_s8(svint8_t op1, svint8_t op2, int8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eorbt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_sveorbt_n_s16u11__SVInt16_tu11__SVInt16_ts( +// CPP-CHECK-LABEL: @_Z18test_sveorbt_n_s16u11__SVInt16_tS_s( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -180,7 +180,7 @@ svint16_t test_sveorbt_n_s16(svint16_t op1, svint16_t op2, int16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eorbt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_sveorbt_n_s32u11__SVInt32_tu11__SVInt32_ti( +// CPP-CHECK-LABEL: @_Z18test_sveorbt_n_s32u11__SVInt32_tS_i( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -199,7 +199,7 @@ svint32_t test_sveorbt_n_s32(svint32_t op1, svint32_t op2, int32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eorbt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_sveorbt_n_s64u11__SVInt64_tu11__SVInt64_tl( +// CPP-CHECK-LABEL: @_Z18test_sveorbt_n_s64u11__SVInt64_tS_l( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -218,7 +218,7 @@ svint64_t test_sveorbt_n_s64(svint64_t op1, svint64_t op2, int64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eorbt.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_sveorbt_n_u8u11__SVUint8_tu11__SVUint8_th( +// CPP-CHECK-LABEL: @_Z17test_sveorbt_n_u8u11__SVUint8_tS_h( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -237,7 +237,7 @@ svuint8_t test_sveorbt_n_u8(svuint8_t op1, svuint8_t op2, uint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eorbt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_sveorbt_n_u16u12__SVUint16_tu12__SVUint16_tt( +// CPP-CHECK-LABEL: @_Z18test_sveorbt_n_u16u12__SVUint16_tS_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -256,7 +256,7 @@ svuint16_t test_sveorbt_n_u16(svuint16_t op1, svuint16_t op2, uint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eorbt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_sveorbt_n_u32u12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z18test_sveorbt_n_u32u12__SVUint32_tS_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -275,7 +275,7 @@ svuint32_t test_sveorbt_n_u32(svuint32_t op1, svuint32_t op2, uint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eorbt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_sveorbt_n_u64u12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z18test_sveorbt_n_u64u12__SVUint64_tS_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_eortb.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_eortb.c index 551462e14b488..0da28c0040b60 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_eortb.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_eortb.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eortb.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_sveortb_s8u10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_sveortb_s8u10__SVInt8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eortb.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_sveortb_s8(svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eortb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_sveortb_s16u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_sveortb_s16u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eortb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_sveortb_s16(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eortb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_sveortb_s32u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_sveortb_s32u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eortb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_sveortb_s32(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eortb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_sveortb_s64u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_sveortb_s64u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eortb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svint64_t test_sveortb_s64(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eortb.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_sveortb_u8u11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_sveortb_u8u11__SVUint8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eortb.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint8_t test_sveortb_u8(svuint8_t op1, svuint8_t op2, svuint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eortb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_sveortb_u16u12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_sveortb_u16u12__SVUint16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eortb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -110,7 +110,7 @@ svuint16_t test_sveortb_u16(svuint16_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eortb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_sveortb_u32u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_sveortb_u32u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eortb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -125,7 +125,7 @@ svuint32_t test_sveortb_u32(svuint32_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eortb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_sveortb_u64u12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_sveortb_u64u12__SVUint64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eortb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -142,7 +142,7 @@ svuint64_t test_sveortb_u64(svuint64_t op1, svuint64_t op2, svuint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eortb.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_sveortb_n_s8u10__SVInt8_tu10__SVInt8_ta( +// CPP-CHECK-LABEL: @_Z17test_sveortb_n_s8u10__SVInt8_tS_a( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -161,7 +161,7 @@ svint8_t test_sveortb_n_s8(svint8_t op1, svint8_t op2, int8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eortb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_sveortb_n_s16u11__SVInt16_tu11__SVInt16_ts( +// CPP-CHECK-LABEL: @_Z18test_sveortb_n_s16u11__SVInt16_tS_s( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -180,7 +180,7 @@ svint16_t test_sveortb_n_s16(svint16_t op1, svint16_t op2, int16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eortb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_sveortb_n_s32u11__SVInt32_tu11__SVInt32_ti( +// CPP-CHECK-LABEL: @_Z18test_sveortb_n_s32u11__SVInt32_tS_i( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -199,7 +199,7 @@ svint32_t test_sveortb_n_s32(svint32_t op1, svint32_t op2, int32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eortb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_sveortb_n_s64u11__SVInt64_tu11__SVInt64_tl( +// CPP-CHECK-LABEL: @_Z18test_sveortb_n_s64u11__SVInt64_tS_l( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -218,7 +218,7 @@ svint64_t test_sveortb_n_s64(svint64_t op1, svint64_t op2, int64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eortb.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_sveortb_n_u8u11__SVUint8_tu11__SVUint8_th( +// CPP-CHECK-LABEL: @_Z17test_sveortb_n_u8u11__SVUint8_tS_h( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -237,7 +237,7 @@ svuint8_t test_sveortb_n_u8(svuint8_t op1, svuint8_t op2, uint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eortb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_sveortb_n_u16u12__SVUint16_tu12__SVUint16_tt( +// CPP-CHECK-LABEL: @_Z18test_sveortb_n_u16u12__SVUint16_tS_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -256,7 +256,7 @@ svuint16_t test_sveortb_n_u16(svuint16_t op1, svuint16_t op2, uint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eortb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_sveortb_n_u32u12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z18test_sveortb_n_u32u12__SVUint32_tS_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -275,7 +275,7 @@ svuint32_t test_sveortb_n_u32(svuint32_t op1, svuint32_t op2, uint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.eortb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_sveortb_n_u64u12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z18test_sveortb_n_u64u12__SVUint64_tS_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hadd.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hadd.c index 203671e76487a..57743e6e577f5 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hadd.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hadd.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.shadd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svhadd_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svhadd_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.shadd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -36,7 +36,7 @@ svint8_t test_svhadd_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shadd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhadd_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svhadd_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shadd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -53,7 +53,7 @@ svint16_t test_svhadd_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shadd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhadd_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svhadd_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shadd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -70,7 +70,7 @@ svint32_t test_svhadd_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shadd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhadd_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svhadd_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shadd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -86,7 +86,7 @@ svint64_t test_svhadd_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uhadd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svhadd_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svhadd_u8_mu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uhadd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -102,7 +102,7 @@ svuint8_t test_svhadd_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhadd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhadd_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svhadd_u16_mu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhadd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -119,7 +119,7 @@ svuint16_t test_svhadd_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhadd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhadd_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svhadd_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhadd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -137,7 +137,7 @@ svuint32_t test_svhadd_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhadd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhadd_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svhadd_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhadd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -318,7 +318,7 @@ svuint64_t test_svhadd_n_u64_m(svbool_t pg, svuint64_t op1, uint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shadd.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svhadd_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svhadd_s8_zu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shadd.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -336,7 +336,7 @@ svint8_t test_svhadd_s8_z(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.shadd.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svhadd_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svhadd_s16_zu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -355,7 +355,7 @@ svint16_t test_svhadd_s16_z(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.shadd.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svhadd_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svhadd_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -374,7 +374,7 @@ svint32_t test_svhadd_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.shadd.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svhadd_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svhadd_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -392,7 +392,7 @@ svint64_t test_svhadd_s64_z(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhadd.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svhadd_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svhadd_u8_zu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhadd.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -410,7 +410,7 @@ svuint8_t test_svhadd_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uhadd.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svhadd_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svhadd_u16_zu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -429,7 +429,7 @@ svuint16_t test_svhadd_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uhadd.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svhadd_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svhadd_u32_zu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -449,7 +449,7 @@ svuint32_t test_svhadd_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uhadd.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svhadd_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svhadd_u64_zu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -646,7 +646,7 @@ svuint64_t test_svhadd_n_u64_z(svbool_t pg, svuint64_t op1, uint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.shadd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svhadd_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svhadd_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.shadd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -662,7 +662,7 @@ svint8_t test_svhadd_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shadd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhadd_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svhadd_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shadd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -679,7 +679,7 @@ svint16_t test_svhadd_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shadd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhadd_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svhadd_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shadd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -696,7 +696,7 @@ svint32_t test_svhadd_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shadd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhadd_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svhadd_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shadd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -712,7 +712,7 @@ svint64_t test_svhadd_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uhadd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svhadd_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svhadd_u8_xu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uhadd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -728,7 +728,7 @@ svuint8_t test_svhadd_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhadd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhadd_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svhadd_u16_xu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhadd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -745,7 +745,7 @@ svuint16_t test_svhadd_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhadd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhadd_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svhadd_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhadd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -763,7 +763,7 @@ svuint32_t test_svhadd_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhadd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhadd_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svhadd_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhadd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_histcnt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_histcnt.c index d7503436804c3..15c6f0f1aa7c1 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_histcnt.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_histcnt.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.histcnt.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z20test_svhistcnt_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z20test_svhistcnt_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.histcnt.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -38,7 +38,7 @@ svuint32_t test_svhistcnt_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.histcnt.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z20test_svhistcnt_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z20test_svhistcnt_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.histcnt.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -55,7 +55,7 @@ svuint64_t test_svhistcnt_s64_z(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.histcnt.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z20test_svhistcnt_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z20test_svhistcnt_u32_zu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.histcnt.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -72,7 +72,7 @@ svuint32_t test_svhistcnt_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.histcnt.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z20test_svhistcnt_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z20test_svhistcnt_u64_zu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.histcnt.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_histseg.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_histseg.c index c90706bcf8c4b..4a8aa46fbc3e7 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_histseg.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_histseg.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.histseg.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svhistseg_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svhistseg_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.histseg.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svuint8_t test_svhistseg_s8(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.histseg.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svhistseg_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z17test_svhistseg_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.histseg.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hsub.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hsub.c index 09293a666ffb7..3ae2150a993fe 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hsub.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hsub.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsub.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svhsub_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svhsub_s8_zu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsub.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -39,7 +39,7 @@ svint8_t test_svhsub_s8_z(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.shsub.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svhsub_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svhsub_s16_zu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -58,7 +58,7 @@ svint16_t test_svhsub_s16_z(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.shsub.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svhsub_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svhsub_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -77,7 +77,7 @@ svint32_t test_svhsub_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.shsub.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svhsub_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svhsub_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -95,7 +95,7 @@ svint64_t test_svhsub_s64_z(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsub.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svhsub_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svhsub_u8_zu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsub.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -113,7 +113,7 @@ svuint8_t test_svhsub_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uhsub.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svhsub_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svhsub_u16_zu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -132,7 +132,7 @@ svuint16_t test_svhsub_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uhsub.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svhsub_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svhsub_u32_zu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -151,7 +151,7 @@ svuint32_t test_svhsub_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uhsub.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svhsub_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svhsub_u64_zu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -168,7 +168,7 @@ svuint64_t test_svhsub_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.shsub.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svhsub_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svhsub_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.shsub.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -184,7 +184,7 @@ svint8_t test_svhsub_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsub.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhsub_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svhsub_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsub.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -201,7 +201,7 @@ svint16_t test_svhsub_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsub.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhsub_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svhsub_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsub.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -218,7 +218,7 @@ svint32_t test_svhsub_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsub.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhsub_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svhsub_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsub.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -234,7 +234,7 @@ svint64_t test_svhsub_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uhsub.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svhsub_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svhsub_u8_mu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uhsub.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -250,7 +250,7 @@ svuint8_t test_svhsub_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsub.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhsub_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svhsub_u16_mu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsub.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -267,7 +267,7 @@ svuint16_t test_svhsub_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsub.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhsub_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svhsub_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsub.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -284,7 +284,7 @@ svuint32_t test_svhsub_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsub.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhsub_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svhsub_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsub.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -300,7 +300,7 @@ svuint64_t test_svhsub_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.shsub.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svhsub_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svhsub_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.shsub.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -316,7 +316,7 @@ svint8_t test_svhsub_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsub.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhsub_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svhsub_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsub.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -333,7 +333,7 @@ svint16_t test_svhsub_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsub.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhsub_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svhsub_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsub.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -350,7 +350,7 @@ svint32_t test_svhsub_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsub.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhsub_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svhsub_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsub.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -366,7 +366,7 @@ svint64_t test_svhsub_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uhsub.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svhsub_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svhsub_u8_xu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uhsub.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -382,7 +382,7 @@ svuint8_t test_svhsub_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsub.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhsub_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svhsub_u16_xu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsub.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -399,7 +399,7 @@ svuint16_t test_svhsub_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsub.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhsub_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svhsub_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsub.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -416,7 +416,7 @@ svuint32_t test_svhsub_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsub.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhsub_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svhsub_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsub.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hsubr.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hsubr.c index 425943a314f28..910342da55105 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hsubr.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hsubr.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsubr.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhsubr_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svhsubr_s8_zu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsubr.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -39,7 +39,7 @@ svint8_t test_svhsubr_s8_z(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.shsubr.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svhsubr_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svhsubr_s16_zu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -58,7 +58,7 @@ svint16_t test_svhsubr_s16_z(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.shsubr.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svhsubr_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svhsubr_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -77,7 +77,7 @@ svint32_t test_svhsubr_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.shsubr.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svhsubr_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svhsubr_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -95,7 +95,7 @@ svint64_t test_svhsubr_s64_z(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsubr.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svhsubr_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z17test_svhsubr_u8_zu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsubr.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -113,7 +113,7 @@ svuint8_t test_svhsubr_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uhsubr.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svhsubr_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z18test_svhsubr_u16_zu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -132,7 +132,7 @@ svuint16_t test_svhsubr_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uhsubr.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svhsubr_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z18test_svhsubr_u32_zu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -151,7 +151,7 @@ svuint32_t test_svhsubr_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uhsubr.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svhsubr_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z18test_svhsubr_u64_zu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -168,7 +168,7 @@ svuint64_t test_svhsubr_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.shsubr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svhsubr_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svhsubr_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.shsubr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -184,7 +184,7 @@ svint8_t test_svhsubr_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsubr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svhsubr_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svhsubr_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsubr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -201,7 +201,7 @@ svint16_t test_svhsubr_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsubr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svhsubr_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svhsubr_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsubr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -218,7 +218,7 @@ svint32_t test_svhsubr_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsubr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svhsubr_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svhsubr_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsubr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -234,7 +234,7 @@ svint64_t test_svhsubr_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uhsubr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svhsubr_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z17test_svhsubr_u8_mu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uhsubr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -250,7 +250,7 @@ svuint8_t test_svhsubr_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsubr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svhsubr_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z18test_svhsubr_u16_mu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsubr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -267,7 +267,7 @@ svuint16_t test_svhsubr_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsubr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svhsubr_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z18test_svhsubr_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsubr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -284,7 +284,7 @@ svuint32_t test_svhsubr_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsubr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svhsubr_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z18test_svhsubr_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsubr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -300,7 +300,7 @@ svuint64_t test_svhsubr_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.shsubr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svhsubr_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svhsubr_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.shsubr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -316,7 +316,7 @@ svint8_t test_svhsubr_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsubr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svhsubr_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svhsubr_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsubr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -333,7 +333,7 @@ svint16_t test_svhsubr_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsubr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svhsubr_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svhsubr_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsubr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -350,7 +350,7 @@ svint32_t test_svhsubr_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsubr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svhsubr_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svhsubr_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.shsubr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -366,7 +366,7 @@ svint64_t test_svhsubr_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uhsubr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svhsubr_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z17test_svhsubr_u8_xu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uhsubr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -382,7 +382,7 @@ svuint8_t test_svhsubr_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsubr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svhsubr_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z18test_svhsubr_u16_xu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsubr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -399,7 +399,7 @@ svuint16_t test_svhsubr_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsubr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svhsubr_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z18test_svhsubr_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsubr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -416,7 +416,7 @@ svuint32_t test_svhsubr_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsubr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svhsubr_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z18test_svhsubr_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uhsubr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_match.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_match.c index e1d2f247ac754..c80063af36f15 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_match.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_match.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.match.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmatch_s8u10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svmatch_s8u10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.match.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -37,7 +37,7 @@ svbool_t test_svmatch_s8(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmatch_s16u10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmatch_s16u10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.match.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -54,7 +54,7 @@ svbool_t test_svmatch_s16(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.match.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svmatch_u8u10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svmatch_u8u10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.match.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -71,7 +71,7 @@ svbool_t test_svmatch_u8(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z16test_svmatch_u16u10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmatch_u16u10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.match.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_maxnmp.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_maxnmp.c index a20f591c14e1a..8695d23a4a15a 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_maxnmp.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_maxnmp.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxnmp.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svmaxnmp_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z19test_svmaxnmp_f16_mu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxnmp.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -38,7 +38,7 @@ svfloat16_t test_svmaxnmp_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxnmp.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svmaxnmp_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z19test_svmaxnmp_f32_mu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxnmp.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -55,7 +55,7 @@ svfloat32_t test_svmaxnmp_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxnmp.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svmaxnmp_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z19test_svmaxnmp_f64_mu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxnmp.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -72,7 +72,7 @@ svfloat64_t test_svmaxnmp_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxnmp.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svmaxnmp_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z19test_svmaxnmp_f16_xu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxnmp.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -89,7 +89,7 @@ svfloat16_t test_svmaxnmp_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxnmp.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svmaxnmp_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z19test_svmaxnmp_f32_xu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxnmp.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -106,7 +106,7 @@ svfloat32_t test_svmaxnmp_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxnmp.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svmaxnmp_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z19test_svmaxnmp_f64_xu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxnmp.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_maxp.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_maxp.c index d7a2782ed796c..ba4f77458780d 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_maxp.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_maxp.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smaxp.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmaxp_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svmaxp_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smaxp.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -36,7 +36,7 @@ svint8_t test_svmaxp_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smaxp.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmaxp_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svmaxp_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smaxp.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -53,7 +53,7 @@ svint16_t test_svmaxp_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smaxp.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmaxp_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svmaxp_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smaxp.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -70,7 +70,7 @@ svint32_t test_svmaxp_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smaxp.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmaxp_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svmaxp_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smaxp.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -86,7 +86,7 @@ svint64_t test_svmaxp_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umaxp.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmaxp_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svmaxp_u8_mu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umaxp.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -102,7 +102,7 @@ svuint8_t test_svmaxp_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umaxp.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmaxp_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svmaxp_u16_mu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umaxp.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -119,7 +119,7 @@ svuint16_t test_svmaxp_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umaxp.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmaxp_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svmaxp_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umaxp.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -136,7 +136,7 @@ svuint32_t test_svmaxp_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umaxp.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmaxp_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svmaxp_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umaxp.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -152,7 +152,7 @@ svuint64_t test_svmaxp_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smaxp.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmaxp_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svmaxp_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smaxp.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -168,7 +168,7 @@ svint8_t test_svmaxp_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smaxp.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmaxp_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svmaxp_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smaxp.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -185,7 +185,7 @@ svint16_t test_svmaxp_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smaxp.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmaxp_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svmaxp_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smaxp.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -202,7 +202,7 @@ svint32_t test_svmaxp_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smaxp.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmaxp_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svmaxp_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.smaxp.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -218,7 +218,7 @@ svint64_t test_svmaxp_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umaxp.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmaxp_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svmaxp_u8_xu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umaxp.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -234,7 +234,7 @@ svuint8_t test_svmaxp_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umaxp.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmaxp_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svmaxp_u16_xu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umaxp.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -251,7 +251,7 @@ svuint16_t test_svmaxp_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umaxp.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmaxp_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svmaxp_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umaxp.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -268,7 +268,7 @@ svuint32_t test_svmaxp_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umaxp.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmaxp_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svmaxp_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.umaxp.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -285,7 +285,7 @@ svuint64_t test_svmaxp_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxp.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmaxp_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svmaxp_f16_mu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxp.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -302,7 +302,7 @@ svfloat16_t test_svmaxp_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxp.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmaxp_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svmaxp_f32_mu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxp.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -319,7 +319,7 @@ svfloat32_t test_svmaxp_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxp.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmaxp_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svmaxp_f64_mu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxp.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -336,7 +336,7 @@ svfloat64_t test_svmaxp_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxp.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmaxp_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svmaxp_f16_xu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxp.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -353,7 +353,7 @@ svfloat16_t test_svmaxp_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxp.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmaxp_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svmaxp_f32_xu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxp.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -370,7 +370,7 @@ svfloat32_t test_svmaxp_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxp.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svmaxp_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svmaxp_f64_xu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fmaxp.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_minnmp.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_minnmp.c index c5c46e7999615..21dd51f43c6f7 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_minnmp.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_minnmp.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminnmp.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svminnmp_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z19test_svminnmp_f16_mu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminnmp.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -38,7 +38,7 @@ svfloat16_t test_svminnmp_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminnmp.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svminnmp_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z19test_svminnmp_f32_mu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminnmp.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -55,7 +55,7 @@ svfloat32_t test_svminnmp_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminnmp.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svminnmp_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z19test_svminnmp_f64_mu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminnmp.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -72,7 +72,7 @@ svfloat64_t test_svminnmp_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminnmp.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svminnmp_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z19test_svminnmp_f16_xu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminnmp.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -89,7 +89,7 @@ svfloat16_t test_svminnmp_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminnmp.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svminnmp_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z19test_svminnmp_f32_xu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminnmp.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -106,7 +106,7 @@ svfloat32_t test_svminnmp_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminnmp.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svminnmp_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z19test_svminnmp_f64_xu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminnmp.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_minp.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_minp.c index ad82791fffd79..1eb13493554d4 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_minp.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_minp.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sminp.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svminp_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svminp_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sminp.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -36,7 +36,7 @@ svint8_t test_svminp_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sminp.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svminp_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svminp_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sminp.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -53,7 +53,7 @@ svint16_t test_svminp_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sminp.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svminp_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svminp_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sminp.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -70,7 +70,7 @@ svint32_t test_svminp_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sminp.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svminp_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svminp_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sminp.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -86,7 +86,7 @@ svint64_t test_svminp_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uminp.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svminp_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svminp_u8_mu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uminp.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -102,7 +102,7 @@ svuint8_t test_svminp_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uminp.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svminp_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svminp_u16_mu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uminp.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -119,7 +119,7 @@ svuint16_t test_svminp_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uminp.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svminp_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svminp_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uminp.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -136,7 +136,7 @@ svuint32_t test_svminp_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uminp.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svminp_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svminp_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uminp.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -152,7 +152,7 @@ svuint64_t test_svminp_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sminp.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svminp_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svminp_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sminp.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -168,7 +168,7 @@ svint8_t test_svminp_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sminp.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svminp_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svminp_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sminp.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -185,7 +185,7 @@ svint16_t test_svminp_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sminp.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svminp_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svminp_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sminp.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -202,7 +202,7 @@ svint32_t test_svminp_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sminp.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svminp_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svminp_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sminp.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -218,7 +218,7 @@ svint64_t test_svminp_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uminp.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svminp_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svminp_u8_xu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uminp.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -234,7 +234,7 @@ svuint8_t test_svminp_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uminp.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svminp_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svminp_u16_xu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uminp.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -251,7 +251,7 @@ svuint16_t test_svminp_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uminp.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svminp_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svminp_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uminp.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -268,7 +268,7 @@ svuint32_t test_svminp_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uminp.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svminp_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svminp_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uminp.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -285,7 +285,7 @@ svuint64_t test_svminp_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminp.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svminp_f16_mu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svminp_f16_mu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminp.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -302,7 +302,7 @@ svfloat16_t test_svminp_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminp.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svminp_f32_mu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svminp_f32_mu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminp.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -319,7 +319,7 @@ svfloat32_t test_svminp_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminp.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svminp_f64_mu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svminp_f64_mu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminp.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -336,7 +336,7 @@ svfloat64_t test_svminp_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminp.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svminp_f16_xu10__SVBool_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svminp_f16_xu10__SVBool_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminp.nxv8f16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -353,7 +353,7 @@ svfloat16_t test_svminp_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminp.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svminp_f32_xu10__SVBool_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z17test_svminp_f32_xu10__SVBool_tu13__SVFloat32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminp.nxv4f32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -370,7 +370,7 @@ svfloat32_t test_svminp_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminp.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svminp_f64_xu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z17test_svminp_f64_xu10__SVBool_tu13__SVFloat64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.fminp.nxv2f64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mla.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mla.c index 9f5891c3f4dd5..1d920f2a8fd89 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mla.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mla.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmla_lane_s16u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z19test_svmla_lane_s16u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svmla_lane_s16(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmla_lane_s16_1u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z21test_svmla_lane_s16_1u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_svmla_lane_s16_1(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmla_lane_s32u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z19test_svmla_lane_s32u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_svmla_lane_s32(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmla_lane_s32_1u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z21test_svmla_lane_s32_1u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svint32_t test_svmla_lane_s32_1(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmla_lane_s64u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z19test_svmla_lane_s64u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svint64_t test_svmla_lane_s64(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmla_lane_s64_1u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z21test_svmla_lane_s64_1u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -110,7 +110,7 @@ svint64_t test_svmla_lane_s64_1(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmla_lane_u16u12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z19test_svmla_lane_u16u12__SVUint16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -125,7 +125,7 @@ svuint16_t test_svmla_lane_u16(svuint16_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmla_lane_u16_1u12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z21test_svmla_lane_u16_1u12__SVUint16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -140,7 +140,7 @@ svuint16_t test_svmla_lane_u16_1(svuint16_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmla_lane_u32_1u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z21test_svmla_lane_u32_1u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -155,7 +155,7 @@ svuint32_t test_svmla_lane_u32_1(svuint32_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmla_lane_u64u12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z19test_svmla_lane_u64u12__SVUint64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -170,7 +170,7 @@ svuint64_t test_svmla_lane_u64(svuint64_t op1, svuint64_t op2, svuint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmla_lane_u64_1u12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z21test_svmla_lane_u64_1u12__SVUint64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mla.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mlalb.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mlalb.c index 1820d26a0332c..82e784c1d6f21 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mlalb.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mlalb.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlalb_s16u11__SVInt16_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svmlalb_s16u11__SVInt16_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svmlalb_s16(svint16_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlalb_s32u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmlalb_s32u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svmlalb_s32(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlalb_s64u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmlalb_s64u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint64_t test_svmlalb_s64(svint64_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlalb_u16u12__SVUint16_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svmlalb_u16u12__SVUint16_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svuint16_t test_svmlalb_u16(svuint16_t op1, svuint8_t op2, svuint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlalb_u32u12__SVUint32_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmlalb_u32u12__SVUint32_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint32_t test_svmlalb_u32(svuint32_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlalb_u64u12__SVUint64_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmlalb_u64u12__SVUint64_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -224,7 +224,7 @@ svuint64_t test_svmlalb_n_u64(svuint64_t op1, svuint32_t op2, uint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmlalb_lane_s32u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z21test_svmlalb_lane_s32u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -239,7 +239,7 @@ svint32_t test_svmlalb_lane_s32(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmlalb_lane_s32_1u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z23test_svmlalb_lane_s32_1u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -254,7 +254,7 @@ svint32_t test_svmlalb_lane_s32_1(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmlalb_lane_s64u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z21test_svmlalb_lane_s64u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -269,7 +269,7 @@ svint64_t test_svmlalb_lane_s64(svint64_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmlalb_lane_s64_1u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z23test_svmlalb_lane_s64_1u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -284,7 +284,7 @@ svint64_t test_svmlalb_lane_s64_1(svint64_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmlalb_lane_u32u12__SVUint32_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z21test_svmlalb_lane_u32u12__SVUint32_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -299,7 +299,7 @@ svuint32_t test_svmlalb_lane_u32(svuint32_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmlalb_lane_u32_1u12__SVUint32_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z23test_svmlalb_lane_u32_1u12__SVUint32_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -314,7 +314,7 @@ svuint32_t test_svmlalb_lane_u32_1(svuint32_t op1, svuint16_t op2, svuint16_t op // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmlalb_lane_u64u12__SVUint64_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z21test_svmlalb_lane_u64u12__SVUint64_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -329,7 +329,7 @@ svuint64_t test_svmlalb_lane_u64(svuint64_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmlalb_lane_u64_1u12__SVUint64_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z23test_svmlalb_lane_u64_1u12__SVUint64_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -344,7 +344,7 @@ svuint64_t test_svmlalb_lane_u64_1(svuint64_t op1, svuint32_t op2, svuint32_t op // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmlalb.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlalb_f32u13__SVFloat32_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmlalb_f32u13__SVFloat32_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmlalb.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -378,7 +378,7 @@ svfloat32_t test_svmlalb_n_f32(svfloat32_t op1, svfloat16_t op2, float16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmlalb.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmlalb_lane_f32u13__SVFloat32_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z21test_svmlalb_lane_f32u13__SVFloat32_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmlalb.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -393,7 +393,7 @@ svfloat32_t test_svmlalb_lane_f32(svfloat32_t op1, svfloat16_t op2, svfloat16_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmlalb.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmlalb_lane_f32_1u13__SVFloat32_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z23test_svmlalb_lane_f32_1u13__SVFloat32_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmlalb.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mlalt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mlalt.c index 828eb29f716a2..b4b1fa1be5328 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mlalt.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mlalt.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlalt_s16u11__SVInt16_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svmlalt_s16u11__SVInt16_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svmlalt_s16(svint16_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlalt_s32u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmlalt_s32u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svmlalt_s32(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlalt_s64u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmlalt_s64u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint64_t test_svmlalt_s64(svint64_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlalt_u16u12__SVUint16_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svmlalt_u16u12__SVUint16_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svuint16_t test_svmlalt_u16(svuint16_t op1, svuint8_t op2, svuint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlalt_u32u12__SVUint32_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmlalt_u32u12__SVUint32_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint32_t test_svmlalt_u32(svuint32_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlalt_u64u12__SVUint64_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmlalt_u64u12__SVUint64_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -224,7 +224,7 @@ svuint64_t test_svmlalt_n_u64(svuint64_t op1, svuint32_t op2, uint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmlalt_lane_s32u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z21test_svmlalt_lane_s32u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -239,7 +239,7 @@ svint32_t test_svmlalt_lane_s32(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmlalt_lane_s32_1u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z23test_svmlalt_lane_s32_1u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -254,7 +254,7 @@ svint32_t test_svmlalt_lane_s32_1(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmlalt_lane_s64u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z21test_svmlalt_lane_s64u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -269,7 +269,7 @@ svint64_t test_svmlalt_lane_s64(svint64_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmlalt_lane_s64_1u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z23test_svmlalt_lane_s64_1u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlalt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -284,7 +284,7 @@ svint64_t test_svmlalt_lane_s64_1(svint64_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmlalt_lane_u32u12__SVUint32_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z21test_svmlalt_lane_u32u12__SVUint32_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -299,7 +299,7 @@ svuint32_t test_svmlalt_lane_u32(svuint32_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmlalt_lane_u32_1u12__SVUint32_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z23test_svmlalt_lane_u32_1u12__SVUint32_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -314,7 +314,7 @@ svuint32_t test_svmlalt_lane_u32_1(svuint32_t op1, svuint16_t op2, svuint16_t op // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmlalt_lane_u64u12__SVUint64_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z21test_svmlalt_lane_u64u12__SVUint64_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -329,7 +329,7 @@ svuint64_t test_svmlalt_lane_u64(svuint64_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmlalt_lane_u64_1u12__SVUint64_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z23test_svmlalt_lane_u64_1u12__SVUint64_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlalt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -344,7 +344,7 @@ svuint64_t test_svmlalt_lane_u64_1(svuint64_t op1, svuint32_t op2, svuint32_t op // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmlalt.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlalt_f32u13__SVFloat32_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmlalt_f32u13__SVFloat32_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmlalt.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -378,7 +378,7 @@ svfloat32_t test_svmlalt_n_f32(svfloat32_t op1, svfloat16_t op2, float16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmlalt.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmlalt_lane_f32u13__SVFloat32_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z21test_svmlalt_lane_f32u13__SVFloat32_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmlalt.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -393,7 +393,7 @@ svfloat32_t test_svmlalt_lane_f32(svfloat32_t op1, svfloat16_t op2, svfloat16_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmlalt.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmlalt_lane_f32_1u13__SVFloat32_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z23test_svmlalt_lane_f32_1u13__SVFloat32_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmlalt.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mls.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mls.c index 53d66beb199a6..008de6978fa68 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mls.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mls.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmls_lane_s16u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z19test_svmls_lane_s16u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svmls_lane_s16(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmls_lane_s16_1u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z21test_svmls_lane_s16_1u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_svmls_lane_s16_1(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmls_lane_s32u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z19test_svmls_lane_s32u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_svmls_lane_s32(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmls_lane_s32_1u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z21test_svmls_lane_s32_1u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svint32_t test_svmls_lane_s32_1(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmls_lane_s64u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z19test_svmls_lane_s64u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svint64_t test_svmls_lane_s64(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmls_lane_s64_1u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z21test_svmls_lane_s64_1u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -110,7 +110,7 @@ svint64_t test_svmls_lane_s64_1(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmls_lane_u16u12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z19test_svmls_lane_u16u12__SVUint16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -125,7 +125,7 @@ svuint16_t test_svmls_lane_u16(svuint16_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmls_lane_u16_1u12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z21test_svmls_lane_u16_1u12__SVUint16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -140,7 +140,7 @@ svuint16_t test_svmls_lane_u16_1(svuint16_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmls_lane_u32u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z19test_svmls_lane_u32u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -155,7 +155,7 @@ svuint32_t test_svmls_lane_u32(svuint32_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmls_lane_u32_1u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z21test_svmls_lane_u32_1u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -170,7 +170,7 @@ svuint32_t test_svmls_lane_u32_1(svuint32_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmls_lane_u64u12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z19test_svmls_lane_u64u12__SVUint64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -185,7 +185,7 @@ svuint64_t test_svmls_lane_u64(svuint64_t op1, svuint64_t op2, svuint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmls_lane_u64_1u12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z21test_svmls_lane_u64_1u12__SVUint64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mls.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mlslb.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mlslb.c index a0e511fd4130d..46a8689a20904 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mlslb.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mlslb.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlslb_s16u11__SVInt16_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svmlslb_s16u11__SVInt16_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svmlslb_s16(svint16_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlslb_s32u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmlslb_s32u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svmlslb_s32(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlslb_s64u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmlslb_s64u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint64_t test_svmlslb_s64(svint64_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlslb_u16u12__SVUint16_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svmlslb_u16u12__SVUint16_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svuint16_t test_svmlslb_u16(svuint16_t op1, svuint8_t op2, svuint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlslb_u32u12__SVUint32_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmlslb_u32u12__SVUint32_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint32_t test_svmlslb_u32(svuint32_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlslb_u64u12__SVUint64_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmlslb_u64u12__SVUint64_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -224,7 +224,7 @@ svuint64_t test_svmlslb_n_u64(svuint64_t op1, svuint32_t op2, uint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmlslb_lane_s32u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z21test_svmlslb_lane_s32u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -239,7 +239,7 @@ svint32_t test_svmlslb_lane_s32(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmlslb_lane_s32_1u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z23test_svmlslb_lane_s32_1u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -254,7 +254,7 @@ svint32_t test_svmlslb_lane_s32_1(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmlslb_lane_s64u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z21test_svmlslb_lane_s64u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -269,7 +269,7 @@ svint64_t test_svmlslb_lane_s64(svint64_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmlslb_lane_s64_1u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z23test_svmlslb_lane_s64_1u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -284,7 +284,7 @@ svint64_t test_svmlslb_lane_s64_1(svint64_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmlslb_lane_u32u12__SVUint32_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z21test_svmlslb_lane_u32u12__SVUint32_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -299,7 +299,7 @@ svuint32_t test_svmlslb_lane_u32(svuint32_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmlslb_lane_u32_1u12__SVUint32_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z23test_svmlslb_lane_u32_1u12__SVUint32_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -314,7 +314,7 @@ svuint32_t test_svmlslb_lane_u32_1(svuint32_t op1, svuint16_t op2, svuint16_t op // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmlslb_lane_u64u12__SVUint64_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z21test_svmlslb_lane_u64u12__SVUint64_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -329,7 +329,7 @@ svuint64_t test_svmlslb_lane_u64(svuint64_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmlslb_lane_u64_1u12__SVUint64_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z23test_svmlslb_lane_u64_1u12__SVUint64_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -344,7 +344,7 @@ svuint64_t test_svmlslb_lane_u64_1(svuint64_t op1, svuint32_t op2, svuint32_t op // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmlslb.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlslb_f32u13__SVFloat32_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmlslb_f32u13__SVFloat32_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmlslb.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -378,7 +378,7 @@ svfloat32_t test_svmlslb_n_f32(svfloat32_t op1, svfloat16_t op2, float16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmlslb.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmlslb_lane_f32u13__SVFloat32_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z21test_svmlslb_lane_f32u13__SVFloat32_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmlslb.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -393,7 +393,7 @@ svfloat32_t test_svmlslb_lane_f32(svfloat32_t op1, svfloat16_t op2, svfloat16_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmlslb.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmlslb_lane_f32_1u13__SVFloat32_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z23test_svmlslb_lane_f32_1u13__SVFloat32_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmlslb.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mlslt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mlslt.c index b2d70952a2d3e..07d19a900cbaa 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mlslt.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mlslt.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlslt_s16u11__SVInt16_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svmlslt_s16u11__SVInt16_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svmlslt_s16(svint16_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlslt_s32u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmlslt_s32u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svmlslt_s32(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlslt_s64u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmlslt_s64u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint64_t test_svmlslt_s64(svint64_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlslt_u16u12__SVUint16_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svmlslt_u16u12__SVUint16_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svuint16_t test_svmlslt_u16(svuint16_t op1, svuint8_t op2, svuint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlslt_u32u12__SVUint32_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmlslt_u32u12__SVUint32_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint32_t test_svmlslt_u32(svuint32_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlslt_u64u12__SVUint64_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmlslt_u64u12__SVUint64_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -224,7 +224,7 @@ svuint64_t test_svmlslt_n_u64(svuint64_t op1, svuint32_t op2, uint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmlslt_lane_s32u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z21test_svmlslt_lane_s32u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -239,7 +239,7 @@ svint32_t test_svmlslt_lane_s32(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmlslt_lane_s32_1u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z23test_svmlslt_lane_s32_1u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -254,7 +254,7 @@ svint32_t test_svmlslt_lane_s32_1(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmlslt_lane_s64u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z21test_svmlslt_lane_s64u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -269,7 +269,7 @@ svint64_t test_svmlslt_lane_s64(svint64_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmlslt_lane_s64_1u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z23test_svmlslt_lane_s64_1u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smlslt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -284,7 +284,7 @@ svint64_t test_svmlslt_lane_s64_1(svint64_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmlslt_lane_u32u12__SVUint32_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z21test_svmlslt_lane_u32u12__SVUint32_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -299,7 +299,7 @@ svuint32_t test_svmlslt_lane_u32(svuint32_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmlslt_lane_u32_1u12__SVUint32_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z23test_svmlslt_lane_u32_1u12__SVUint32_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -314,7 +314,7 @@ svuint32_t test_svmlslt_lane_u32_1(svuint32_t op1, svuint16_t op2, svuint16_t op // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmlslt_lane_u64u12__SVUint64_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z21test_svmlslt_lane_u64u12__SVUint64_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -329,7 +329,7 @@ svuint64_t test_svmlslt_lane_u64(svuint64_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmlslt_lane_u64_1u12__SVUint64_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z23test_svmlslt_lane_u64_1u12__SVUint64_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umlslt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -344,7 +344,7 @@ svuint64_t test_svmlslt_lane_u64_1(svuint64_t op1, svuint32_t op2, svuint32_t op // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmlslt.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmlslt_f32u13__SVFloat32_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svmlslt_f32u13__SVFloat32_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmlslt.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -378,7 +378,7 @@ svfloat32_t test_svmlslt_n_f32(svfloat32_t op1, svfloat16_t op2, float16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmlslt.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmlslt_lane_f32u13__SVFloat32_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z21test_svmlslt_lane_f32u13__SVFloat32_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmlslt.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -393,7 +393,7 @@ svfloat32_t test_svmlslt_lane_f32(svfloat32_t op1, svfloat16_t op2, svfloat16_t // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmlslt.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmlslt_lane_f32_1u13__SVFloat32_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z23test_svmlslt_lane_f32_1u13__SVFloat32_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fmlslt.lane.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mul.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mul.c index af2d2b785ea6c..1c2aa9a495e94 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mul.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mul.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmul_lane_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z19test_svmul_lane_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svmul_lane_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmul_lane_s16_1u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z21test_svmul_lane_s16_1u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_svmul_lane_s16_1(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmul_lane_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z19test_svmul_lane_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_svmul_lane_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmul_lane_s32_1u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z21test_svmul_lane_s32_1u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svint32_t test_svmul_lane_s32_1(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmul_lane_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z19test_svmul_lane_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svint64_t test_svmul_lane_s64(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmul_lane_s64_1u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z21test_svmul_lane_s64_1u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -110,7 +110,7 @@ svint64_t test_svmul_lane_s64_1(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmul_lane_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z19test_svmul_lane_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -125,7 +125,7 @@ svuint16_t test_svmul_lane_u16(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmul_lane_u16_1u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z21test_svmul_lane_u16_1u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -140,7 +140,7 @@ svuint16_t test_svmul_lane_u16_1(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmul_lane_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z19test_svmul_lane_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -155,7 +155,7 @@ svuint32_t test_svmul_lane_u32(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmul_lane_u32_1u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z21test_svmul_lane_u32_1u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -170,7 +170,7 @@ svuint32_t test_svmul_lane_u32_1(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svmul_lane_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z19test_svmul_lane_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -185,7 +185,7 @@ svuint64_t test_svmul_lane_u64(svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmul_lane_u64_1u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z21test_svmul_lane_u64_1u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.mul.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mullb.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mullb.c index 80345bce0f1d9..e7f152cedb60e 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mullb.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mullb.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmullb_s16u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svmullb_s16u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svmullb_s16(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmullb_s32u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmullb_s32u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svmullb_s32(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmullb_s64u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmullb_s64u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint64_t test_svmullb_s64(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmullb_u16u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svmullb_u16u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svuint16_t test_svmullb_u16(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmullb_u32u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmullb_u32u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint32_t test_svmullb_u32(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmullb_u64u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmullb_u64u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -224,7 +224,7 @@ svuint64_t test_svmullb_n_u64(svuint32_t op1, uint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmullb_lane_s32u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z21test_svmullb_lane_s32u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -239,7 +239,7 @@ svint32_t test_svmullb_lane_s32(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmullb_lane_s32_1u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z23test_svmullb_lane_s32_1u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -254,7 +254,7 @@ svint32_t test_svmullb_lane_s32_1(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmullb_lane_s64u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z21test_svmullb_lane_s64u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -269,7 +269,7 @@ svint64_t test_svmullb_lane_s64(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmullb_lane_s64_1u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z23test_svmullb_lane_s64_1u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -284,7 +284,7 @@ svint64_t test_svmullb_lane_s64_1(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmullb_lane_u32u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z21test_svmullb_lane_u32u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -299,7 +299,7 @@ svuint32_t test_svmullb_lane_u32(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmullb_lane_u32_1u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z23test_svmullb_lane_u32_1u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -314,7 +314,7 @@ svuint32_t test_svmullb_lane_u32_1(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmullb_lane_u64u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z21test_svmullb_lane_u64u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -329,7 +329,7 @@ svuint64_t test_svmullb_lane_u64(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmullb_lane_u64_1u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z23test_svmullb_lane_u64_1u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mullt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mullt.c index fc4afb38b5e43..1577da58f579c 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mullt.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_mullt.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmullt_s16u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svmullt_s16u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svmullt_s16(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmullt_s32u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svmullt_s32u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svmullt_s32(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmullt_s64u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svmullt_s64u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint64_t test_svmullt_s64(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmullt_u16u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svmullt_u16u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svuint16_t test_svmullt_u16(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmullt_u32u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svmullt_u32u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint32_t test_svmullt_u32(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svmullt_u64u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svmullt_u64u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -224,7 +224,7 @@ svuint64_t test_svmullt_n_u64(svuint32_t op1, uint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmullt_lane_s32u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z21test_svmullt_lane_s32u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -239,7 +239,7 @@ svint32_t test_svmullt_lane_s32(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmullt_lane_s32_1u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z23test_svmullt_lane_s32_1u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -254,7 +254,7 @@ svint32_t test_svmullt_lane_s32_1(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmullt_lane_s64u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z21test_svmullt_lane_s64u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -269,7 +269,7 @@ svint64_t test_svmullt_lane_s64(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmullt_lane_s64_1u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z23test_svmullt_lane_s64_1u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.smullt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -284,7 +284,7 @@ svint64_t test_svmullt_lane_s64_1(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmullt_lane_u32u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z21test_svmullt_lane_u32u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -299,7 +299,7 @@ svuint32_t test_svmullt_lane_u32(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmullt_lane_u32_1u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z23test_svmullt_lane_u32_1u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -314,7 +314,7 @@ svuint32_t test_svmullt_lane_u32_1(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svmullt_lane_u64u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z21test_svmullt_lane_u64u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -329,7 +329,7 @@ svuint64_t test_svmullt_lane_u64(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svmullt_lane_u64_1u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z23test_svmullt_lane_u64_1u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.umullt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_nbsl.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_nbsl.c index ef8367b94693b..b32788d7ce164 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_nbsl.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_nbsl.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nbsl.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svnbsl_s8u10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z14test_svnbsl_s8u10__SVInt8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nbsl.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svnbsl_s8(svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nbsl.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svnbsl_s16u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z15test_svnbsl_s16u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nbsl.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_svnbsl_s16(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nbsl.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svnbsl_s32u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z15test_svnbsl_s32u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nbsl.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_svnbsl_s32(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nbsl.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svnbsl_s64u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z15test_svnbsl_s64u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nbsl.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svint64_t test_svnbsl_s64(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nbsl.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svnbsl_u8u11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svnbsl_u8u11__SVUint8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nbsl.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint8_t test_svnbsl_u8(svuint8_t op1, svuint8_t op2, svuint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nbsl.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svnbsl_u16u12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z15test_svnbsl_u16u12__SVUint16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nbsl.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -110,7 +110,7 @@ svuint16_t test_svnbsl_u16(svuint16_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nbsl.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svnbsl_u32u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z15test_svnbsl_u32u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nbsl.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -125,7 +125,7 @@ svuint32_t test_svnbsl_u32(svuint32_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nbsl.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svnbsl_u64u12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z15test_svnbsl_u64u12__SVUint64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nbsl.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -142,7 +142,7 @@ svuint64_t test_svnbsl_u64(svuint64_t op1, svuint64_t op2, svuint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nbsl.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svnbsl_n_s8u10__SVInt8_tu10__SVInt8_ta( +// CPP-CHECK-LABEL: @_Z16test_svnbsl_n_s8u10__SVInt8_tS_a( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -161,7 +161,7 @@ svint8_t test_svnbsl_n_s8(svint8_t op1, svint8_t op2, int8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nbsl.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svnbsl_n_s16u11__SVInt16_tu11__SVInt16_ts( +// CPP-CHECK-LABEL: @_Z17test_svnbsl_n_s16u11__SVInt16_tS_s( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -180,7 +180,7 @@ svint16_t test_svnbsl_n_s16(svint16_t op1, svint16_t op2, int16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nbsl.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svnbsl_n_s32u11__SVInt32_tu11__SVInt32_ti( +// CPP-CHECK-LABEL: @_Z17test_svnbsl_n_s32u11__SVInt32_tS_i( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -199,7 +199,7 @@ svint32_t test_svnbsl_n_s32(svint32_t op1, svint32_t op2, int32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nbsl.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svnbsl_n_s64u11__SVInt64_tu11__SVInt64_tl( +// CPP-CHECK-LABEL: @_Z17test_svnbsl_n_s64u11__SVInt64_tS_l( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -218,7 +218,7 @@ svint64_t test_svnbsl_n_s64(svint64_t op1, svint64_t op2, int64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nbsl.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svnbsl_n_u8u11__SVUint8_tu11__SVUint8_th( +// CPP-CHECK-LABEL: @_Z16test_svnbsl_n_u8u11__SVUint8_tS_h( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -237,7 +237,7 @@ svuint8_t test_svnbsl_n_u8(svuint8_t op1, svuint8_t op2, uint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nbsl.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svnbsl_n_u16u12__SVUint16_tu12__SVUint16_tt( +// CPP-CHECK-LABEL: @_Z17test_svnbsl_n_u16u12__SVUint16_tS_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -256,7 +256,7 @@ svuint16_t test_svnbsl_n_u16(svuint16_t op1, svuint16_t op2, uint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nbsl.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svnbsl_n_u32u12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z17test_svnbsl_n_u32u12__SVUint32_tS_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -275,7 +275,7 @@ svuint32_t test_svnbsl_n_u32(svuint32_t op1, svuint32_t op2, uint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nbsl.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svnbsl_n_u64u12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z17test_svnbsl_n_u64u12__SVUint64_tS_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_nmatch.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_nmatch.c index a47bc17b9d4ea..1c85b5d68a860 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_nmatch.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_nmatch.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nmatch.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svnmatch_s8u10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svnmatch_s8u10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nmatch.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -37,7 +37,7 @@ svbool_t test_svnmatch_s8(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svnmatch_s16u10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svnmatch_s16u10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.nmatch.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -54,7 +54,7 @@ svbool_t test_svnmatch_s16(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nmatch.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svnmatch_u8u10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svnmatch_u8u10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.nmatch.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -71,7 +71,7 @@ svbool_t test_svnmatch_u8(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( [[TMP1]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svnmatch_u16u10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svnmatch_u16u10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.nmatch.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmul.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmul.c index 66ab20c116274..0015aa2cec30f 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmul.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmul.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.pmul.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svpmul_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z14test_svpmul_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.pmul.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullb.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullb.c index 3664cb78d2e13..43cb99dfd444e 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullb.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullb.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.pmullb.pair.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svpmullb_pair_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z21test_svpmullb_pair_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.pmullb.pair.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svuint8_t test_svpmullb_pair_u8(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.pmullb.pair.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z22test_svpmullb_pair_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z22test_svpmullb_pair_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.pmullb.pair.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -89,7 +89,7 @@ svuint32_t test_svpmullb_pair_n_u32(svuint32_t op1, uint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = bitcast [[TMP0]] to // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svpmullb_u16u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z17test_svpmullb_u16u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.pmullb.pair.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = bitcast [[TMP0]] to @@ -106,7 +106,7 @@ svuint16_t test_svpmullb_u16(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = bitcast [[TMP0]] to // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svpmullb_u64u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svpmullb_u64u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.pmullb.pair.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = bitcast [[TMP0]] to diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullb_128.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullb_128.c index 68d8441ddd264..c2b47688781d5 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullb_128.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullb_128.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.pmullb.pair.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z22test_svpmullb_pair_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z22test_svpmullb_pair_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.pmullb.pair.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullt.c index 0b63d708e66f0..5e6b526e5f099 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullt.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullt.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.pmullt.pair.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svpmullt_pair_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z21test_svpmullt_pair_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.pmullt.pair.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svuint8_t test_svpmullt_pair_u8(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.pmullt.pair.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z22test_svpmullt_pair_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z22test_svpmullt_pair_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.pmullt.pair.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -89,7 +89,7 @@ svuint32_t test_svpmullt_pair_n_u32(svuint32_t op1, uint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = bitcast [[TMP0]] to // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svpmullt_u16u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z17test_svpmullt_u16u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.pmullt.pair.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = bitcast [[TMP0]] to @@ -106,7 +106,7 @@ svuint16_t test_svpmullt_u16(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = bitcast [[TMP0]] to // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svpmullt_u64u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svpmullt_u64u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.pmullt.pair.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = bitcast [[TMP0]] to diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullt_128.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullt_128.c index 322e1994f563b..37e0def202e32 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullt_128.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullt_128.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.pmullt.pair.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z22test_svpmullt_pair_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z22test_svpmullt_pair_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.pmullt.pair.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qabs.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qabs.c index 353f2d7bd9614..8a8c92c4cbba8 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qabs.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qabs.c @@ -86,7 +86,7 @@ svint64_t test_svqabs_s64_z(svbool_t pg, svint64_t op) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqabs.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svqabs_s8_mu10__SVInt8_tu10__SVBool_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svqabs_s8_mu10__SVInt8_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqabs.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -102,7 +102,7 @@ svint8_t test_svqabs_s8_m(svint8_t inactive, svbool_t pg, svint8_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqabs.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqabs_s16_mu11__SVInt16_tu10__SVBool_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svqabs_s16_mu11__SVInt16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqabs.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -119,7 +119,7 @@ svint16_t test_svqabs_s16_m(svint16_t inactive, svbool_t pg, svint16_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqabs.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqabs_s32_mu11__SVInt32_tu10__SVBool_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svqabs_s32_mu11__SVInt32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqabs.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -136,7 +136,7 @@ svint32_t test_svqabs_s32_m(svint32_t inactive, svbool_t pg, svint32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqabs.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqabs_s64_mu11__SVInt64_tu10__SVBool_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svqabs_s64_mu11__SVInt64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqabs.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qadd.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qadd.c index 1cf41a3d21872..964309c8da977 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qadd.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qadd.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqadd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svqadd_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svqadd_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqadd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -36,7 +36,7 @@ svint8_t test_svqadd_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqadd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqadd_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svqadd_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqadd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -53,7 +53,7 @@ svint16_t test_svqadd_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqadd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqadd_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svqadd_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqadd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -70,7 +70,7 @@ svint32_t test_svqadd_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqadd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqadd_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svqadd_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqadd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -86,7 +86,7 @@ svint64_t test_svqadd_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqadd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svqadd_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svqadd_u8_mu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqadd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -102,7 +102,7 @@ svuint8_t test_svqadd_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqadd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqadd_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svqadd_u16_mu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqadd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -119,7 +119,7 @@ svuint16_t test_svqadd_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqadd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqadd_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svqadd_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqadd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -137,7 +137,7 @@ svuint32_t test_svqadd_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqadd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqadd_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svqadd_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqadd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -318,7 +318,7 @@ svuint64_t test_svqadd_n_u64_m(svbool_t pg, svuint64_t op1, uint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqadd.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svqadd_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svqadd_s8_zu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqadd.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -336,7 +336,7 @@ svint8_t test_svqadd_s8_z(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sqadd.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svqadd_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svqadd_s16_zu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -355,7 +355,7 @@ svint16_t test_svqadd_s16_z(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sqadd.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svqadd_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svqadd_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -374,7 +374,7 @@ svint32_t test_svqadd_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sqadd.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svqadd_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svqadd_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -392,7 +392,7 @@ svint64_t test_svqadd_s64_z(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqadd.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svqadd_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svqadd_u8_zu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqadd.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -410,7 +410,7 @@ svuint8_t test_svqadd_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uqadd.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svqadd_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svqadd_u16_zu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -429,7 +429,7 @@ svuint16_t test_svqadd_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uqadd.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svqadd_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svqadd_u32_zu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -449,7 +449,7 @@ svuint32_t test_svqadd_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uqadd.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svqadd_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svqadd_u64_zu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -646,7 +646,7 @@ svuint64_t test_svqadd_n_u64_z(svbool_t pg, svuint64_t op1, uint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqadd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svqadd_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svqadd_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqadd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -662,7 +662,7 @@ svint8_t test_svqadd_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqadd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqadd_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svqadd_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqadd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -679,7 +679,7 @@ svint16_t test_svqadd_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqadd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqadd_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svqadd_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqadd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -696,7 +696,7 @@ svint32_t test_svqadd_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqadd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqadd_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svqadd_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqadd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -712,7 +712,7 @@ svint64_t test_svqadd_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqadd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svqadd_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svqadd_u8_xu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqadd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -728,7 +728,7 @@ svuint8_t test_svqadd_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqadd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqadd_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svqadd_u16_xu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqadd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -745,7 +745,7 @@ svuint16_t test_svqadd_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqadd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqadd_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svqadd_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqadd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -763,7 +763,7 @@ svuint32_t test_svqadd_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqadd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqadd_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svqadd_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqadd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qcadd.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qcadd.c index 3519937a6654c..362c8ccf86b60 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qcadd.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qcadd.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqcadd.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svqcadd_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svqcadd_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqcadd.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svqcadd_s8(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqcadd.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svqcadd_s8_1u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svqcadd_s8_1u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqcadd.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint8_t test_svqcadd_s8_1(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqcadd.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svqcadd_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svqcadd_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqcadd.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint16_t test_svqcadd_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqcadd.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqcadd_s16_1u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svqcadd_s16_1u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqcadd.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svint16_t test_svqcadd_s16_1(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqcadd.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svqcadd_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svqcadd_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqcadd.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svint32_t test_svqcadd_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqcadd.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqcadd_s32_1u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svqcadd_s32_1u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqcadd.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -110,7 +110,7 @@ svint32_t test_svqcadd_s32_1(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqcadd.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svqcadd_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svqcadd_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqcadd.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -125,7 +125,7 @@ svint64_t test_svqcadd_s64(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqcadd.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqcadd_s64_1u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svqcadd_s64_1u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqcadd.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmlalb.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmlalb.c index ceea65d17b69b..f8ccdce183285 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmlalb.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmlalb.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqdmlalb_s16u11__SVInt16_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z18test_svqdmlalb_s16u11__SVInt16_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svqdmlalb_s16(svint16_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqdmlalb_s32u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svqdmlalb_s32u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svqdmlalb_s32(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqdmlalb_s64u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svqdmlalb_s64u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -122,7 +122,7 @@ svint64_t test_svqdmlalb_n_s64(svint64_t op1, svint32_t op2, int32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svqdmlalb_lane_s32u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z23test_svqdmlalb_lane_s32u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -137,7 +137,7 @@ svint32_t test_svqdmlalb_lane_s32(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z25test_svqdmlalb_lane_s32_1u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z25test_svqdmlalb_lane_s32_1u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -152,7 +152,7 @@ svint32_t test_svqdmlalb_lane_s32_1(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svqdmlalb_lane_s64u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z23test_svqdmlalb_lane_s64u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -167,7 +167,7 @@ svint64_t test_svqdmlalb_lane_s64(svint64_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z25test_svqdmlalb_lane_s64_1u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z25test_svqdmlalb_lane_s64_1u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmlalbt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmlalbt.c index 72cceca3c06c7..c22f165f96778 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmlalbt.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmlalbt.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalbt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svqdmlalbt_s16u11__SVInt16_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z19test_svqdmlalbt_s16u11__SVInt16_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalbt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svqdmlalbt_s16(svint16_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalbt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svqdmlalbt_s32u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z19test_svqdmlalbt_s32u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalbt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svqdmlalbt_s32(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalbt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svqdmlalbt_s64u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z19test_svqdmlalbt_s64u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalbt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmlalt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmlalt.c index d3ead2de36bee..19f8d65b46ed1 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmlalt.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmlalt.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqdmlalt_s16u11__SVInt16_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z18test_svqdmlalt_s16u11__SVInt16_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svqdmlalt_s16(svint16_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqdmlalt_s32u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svqdmlalt_s32u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svqdmlalt_s32(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqdmlalt_s64u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svqdmlalt_s64u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -122,7 +122,7 @@ svint64_t test_svqdmlalt_n_s64(svint64_t op1, svint32_t op2, int32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svqdmlalt_lane_s32u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z23test_svqdmlalt_lane_s32u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -137,7 +137,7 @@ svint32_t test_svqdmlalt_lane_s32(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z25test_svqdmlalt_lane_s32_1u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z25test_svqdmlalt_lane_s32_1u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -152,7 +152,7 @@ svint32_t test_svqdmlalt_lane_s32_1(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svqdmlalt_lane_s64u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z23test_svqdmlalt_lane_s64u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -167,7 +167,7 @@ svint64_t test_svqdmlalt_lane_s64(svint64_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z25test_svqdmlalt_lane_s64_1u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z25test_svqdmlalt_lane_s64_1u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlalt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmlslb.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmlslb.c index df6342b9d71da..b56f3d051ff1d 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmlslb.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmlslb.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqdmlslb_s16u11__SVInt16_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z18test_svqdmlslb_s16u11__SVInt16_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svqdmlslb_s16(svint16_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqdmlslb_s32u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svqdmlslb_s32u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svqdmlslb_s32(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqdmlslb_s64u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svqdmlslb_s64u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -122,7 +122,7 @@ svint64_t test_svqdmlslb_n_s64(svint64_t op1, svint32_t op2, int32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svqdmlslb_lane_s32u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z23test_svqdmlslb_lane_s32u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -137,7 +137,7 @@ svint32_t test_svqdmlslb_lane_s32(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z25test_svqdmlslb_lane_s32_1u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z25test_svqdmlslb_lane_s32_1u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -152,7 +152,7 @@ svint32_t test_svqdmlslb_lane_s32_1(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svqdmlslb_lane_s64u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z23test_svqdmlslb_lane_s64u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -167,7 +167,7 @@ svint64_t test_svqdmlslb_lane_s64(svint64_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z25test_svqdmlslb_lane_s64_1u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z25test_svqdmlslb_lane_s64_1u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmlslbt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmlslbt.c index 05f1e6a308908..a1f568d8a01b7 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmlslbt.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmlslbt.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslbt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svqdmlslbt_s16u11__SVInt16_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z19test_svqdmlslbt_s16u11__SVInt16_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslbt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svqdmlslbt_s16(svint16_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslbt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svqdmlslbt_s32u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z19test_svqdmlslbt_s32u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslbt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svqdmlslbt_s32(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslbt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svqdmlslbt_s64u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z19test_svqdmlslbt_s64u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslbt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmlslt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmlslt.c index f27187aba04e9..c53444e417aeb 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmlslt.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmlslt.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqdmlslt_s16u11__SVInt16_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z18test_svqdmlslt_s16u11__SVInt16_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svqdmlslt_s16(svint16_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqdmlslt_s32u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svqdmlslt_s32u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svqdmlslt_s32(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqdmlslt_s64u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svqdmlslt_s64u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -122,7 +122,7 @@ svint64_t test_svqdmlslt_n_s64(svint64_t op1, svint32_t op2, int32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svqdmlslt_lane_s32u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z23test_svqdmlslt_lane_s32u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -137,7 +137,7 @@ svint32_t test_svqdmlslt_lane_s32(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z25test_svqdmlslt_lane_s32_1u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z25test_svqdmlslt_lane_s32_1u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -152,7 +152,7 @@ svint32_t test_svqdmlslt_lane_s32_1(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svqdmlslt_lane_s64u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z23test_svqdmlslt_lane_s64u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -167,7 +167,7 @@ svint64_t test_svqdmlslt_lane_s64(svint64_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z25test_svqdmlslt_lane_s64_1u11__SVInt64_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z25test_svqdmlslt_lane_s64_1u11__SVInt64_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmlslt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmulh.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmulh.c index 70e9877001e14..884e218e250e0 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmulh.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmulh.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmulh.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svqdmulh_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svqdmulh_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmulh.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svqdmulh_s8(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmulh.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svqdmulh_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svqdmulh_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmulh.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_svqdmulh_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmulh.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svqdmulh_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svqdmulh_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmulh.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_svqdmulh_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmulh.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svqdmulh_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svqdmulh_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmulh.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -156,7 +156,7 @@ svint64_t test_svqdmulh_n_s64(svint64_t op1, int64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmulh.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z22test_svqdmulh_lane_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z22test_svqdmulh_lane_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmulh.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -171,7 +171,7 @@ svint16_t test_svqdmulh_lane_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmulh.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z24test_svqdmulh_lane_s16_1u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z24test_svqdmulh_lane_s16_1u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmulh.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -186,7 +186,7 @@ svint16_t test_svqdmulh_lane_s16_1(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmulh.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z22test_svqdmulh_lane_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z22test_svqdmulh_lane_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmulh.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -201,7 +201,7 @@ svint32_t test_svqdmulh_lane_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmulh.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z24test_svqdmulh_lane_s32_1u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z24test_svqdmulh_lane_s32_1u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmulh.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -216,7 +216,7 @@ svint32_t test_svqdmulh_lane_s32_1(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmulh.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z22test_svqdmulh_lane_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z22test_svqdmulh_lane_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmulh.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -231,7 +231,7 @@ svint64_t test_svqdmulh_lane_s64(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmulh.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z24test_svqdmulh_lane_s64_1u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z24test_svqdmulh_lane_s64_1u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmulh.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmullb.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmullb.c index 8eddcc317accb..2e891e97914bd 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmullb.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmullb.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqdmullb_s16u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z18test_svqdmullb_s16u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svqdmullb_s16(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqdmullb_s32u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svqdmullb_s32u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svqdmullb_s32(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqdmullb_s64u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svqdmullb_s64u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -122,7 +122,7 @@ svint64_t test_svqdmullb_n_s64(svint32_t op1, int32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svqdmullb_lane_s32u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z23test_svqdmullb_lane_s32u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -137,7 +137,7 @@ svint32_t test_svqdmullb_lane_s32(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z25test_svqdmullb_lane_s32_1u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z25test_svqdmullb_lane_s32_1u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullb.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -152,7 +152,7 @@ svint32_t test_svqdmullb_lane_s32_1(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svqdmullb_lane_s64u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z23test_svqdmullb_lane_s64u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -167,7 +167,7 @@ svint64_t test_svqdmullb_lane_s64(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z25test_svqdmullb_lane_s64_1u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z25test_svqdmullb_lane_s64_1u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullb.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmullt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmullt.c index 3253e60c0c066..7cb8f5d2988cb 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmullt.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qdmullt.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqdmullt_s16u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z18test_svqdmullt_s16u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svqdmullt_s16(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqdmullt_s32u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svqdmullt_s32u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svqdmullt_s32(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqdmullt_s64u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svqdmullt_s64u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -122,7 +122,7 @@ svint64_t test_svqdmullt_n_s64(svint32_t op1, int32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svqdmullt_lane_s32u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z23test_svqdmullt_lane_s32u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -137,7 +137,7 @@ svint32_t test_svqdmullt_lane_s32(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z25test_svqdmullt_lane_s32_1u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z25test_svqdmullt_lane_s32_1u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullt.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -152,7 +152,7 @@ svint32_t test_svqdmullt_lane_s32_1(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svqdmullt_lane_s64u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z23test_svqdmullt_lane_s64u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -167,7 +167,7 @@ svint64_t test_svqdmullt_lane_s64(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z25test_svqdmullt_lane_s64_1u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z25test_svqdmullt_lane_s64_1u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqdmullt.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qneg.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qneg.c index ed8d1c08c64ae..be21a410e4270 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qneg.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qneg.c @@ -86,7 +86,7 @@ svint64_t test_svqneg_s64_z(svbool_t pg, svint64_t op) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqneg.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svqneg_s8_mu10__SVInt8_tu10__SVBool_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svqneg_s8_mu10__SVInt8_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqneg.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -102,7 +102,7 @@ svint8_t test_svqneg_s8_m(svint8_t inactive, svbool_t pg, svint8_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqneg.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqneg_s16_mu11__SVInt16_tu10__SVBool_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svqneg_s16_mu11__SVInt16_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqneg.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -119,7 +119,7 @@ svint16_t test_svqneg_s16_m(svint16_t inactive, svbool_t pg, svint16_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqneg.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqneg_s32_mu11__SVInt32_tu10__SVBool_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svqneg_s32_mu11__SVInt32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqneg.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) @@ -136,7 +136,7 @@ svint32_t test_svqneg_s32_m(svint32_t inactive, svbool_t pg, svint32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqneg.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqneg_s64_mu11__SVInt64_tu10__SVBool_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svqneg_s64_mu11__SVInt64_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqneg.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qrdcmlah.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qrdcmlah.c index a372dfe7e3b67..fd5aa40ea842a 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qrdcmlah.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qrdcmlah.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqrdcmlah_s8u10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z18test_svqrdcmlah_s8u10__SVInt8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svqrdcmlah_s8(svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z20test_svqrdcmlah_s8_1u10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z20test_svqrdcmlah_s8_1u10__SVInt8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint8_t test_svqrdcmlah_s8_1(svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z20test_svqrdcmlah_s8_2u10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z20test_svqrdcmlah_s8_2u10__SVInt8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint8_t test_svqrdcmlah_s8_2(svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z20test_svqrdcmlah_s8_3u10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z20test_svqrdcmlah_s8_3u10__SVInt8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svint8_t test_svqrdcmlah_s8_3(svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svqrdcmlah_s16u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z19test_svqrdcmlah_s16u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svint16_t test_svqrdcmlah_s16(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s16_1u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s16_1u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -110,7 +110,7 @@ svint16_t test_svqrdcmlah_s16_1(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s16_2u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s16_2u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -125,7 +125,7 @@ svint16_t test_svqrdcmlah_s16_2(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s16_3u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s16_3u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -140,7 +140,7 @@ svint16_t test_svqrdcmlah_s16_3(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svqrdcmlah_s32u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z19test_svqrdcmlah_s32u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -155,7 +155,7 @@ svint32_t test_svqrdcmlah_s32(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s32_1u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s32_1u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -170,7 +170,7 @@ svint32_t test_svqrdcmlah_s32_1(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s32_2u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s32_2u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -185,7 +185,7 @@ svint32_t test_svqrdcmlah_s32_2(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s32_3u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s32_3u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -200,7 +200,7 @@ svint32_t test_svqrdcmlah_s32_3(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svqrdcmlah_s64u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z19test_svqrdcmlah_s64u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -215,7 +215,7 @@ svint64_t test_svqrdcmlah_s64(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s64_1u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s64_1u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -230,7 +230,7 @@ svint64_t test_svqrdcmlah_s64_1(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s64_2u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s64_2u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 180) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -245,7 +245,7 @@ svint64_t test_svqrdcmlah_s64_2(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s64_3u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z21test_svqrdcmlah_s64_3u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.x.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -260,7 +260,7 @@ svint64_t test_svqrdcmlah_s64_3(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.lane.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0, i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z24test_svqrdcmlah_lane_s16u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z24test_svqrdcmlah_lane_s16u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.lane.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0, i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -275,7 +275,7 @@ svint16_t test_svqrdcmlah_lane_s16(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.lane.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3, i32 90) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z26test_svqrdcmlah_lane_s16_1u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z26test_svqrdcmlah_lane_s16_1u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.lane.x.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3, i32 90) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -290,7 +290,7 @@ svint16_t test_svqrdcmlah_lane_s16_1(svint16_t op1, svint16_t op2, svint16_t op3 // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.lane.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0, i32 180) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z24test_svqrdcmlah_lane_s32u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z24test_svqrdcmlah_lane_s32u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.lane.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0, i32 180) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -305,7 +305,7 @@ svint32_t test_svqrdcmlah_lane_s32(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.lane.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1, i32 270) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z26test_svqrdcmlah_lane_s32_1u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z26test_svqrdcmlah_lane_s32_1u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdcmlah.lane.x.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1, i32 270) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qrdmlah.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qrdmlah.c index c0fd289cd07ec..fb271b2329cd1 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qrdmlah.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qrdmlah.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlah.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svqrdmlah_s8u10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svqrdmlah_s8u10__SVInt8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlah.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svqrdmlah_s8(svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlah.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqrdmlah_s16u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svqrdmlah_s16u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlah.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_svqrdmlah_s16(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlah.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqrdmlah_s32u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svqrdmlah_s32u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlah.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_svqrdmlah_s32(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlah.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqrdmlah_s64u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svqrdmlah_s64u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlah.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -82,7 +82,7 @@ svint64_t test_svqrdmlah_s64(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlah.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svqrdmlah_n_s8u10__SVInt8_tu10__SVInt8_ta( +// CPP-CHECK-LABEL: @_Z19test_svqrdmlah_n_s8u10__SVInt8_tS_a( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -101,7 +101,7 @@ svint8_t test_svqrdmlah_n_s8(svint8_t op1, svint8_t op2, int8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlah.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z20test_svqrdmlah_n_s16u11__SVInt16_tu11__SVInt16_ts( +// CPP-CHECK-LABEL: @_Z20test_svqrdmlah_n_s16u11__SVInt16_tS_s( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -120,7 +120,7 @@ svint16_t test_svqrdmlah_n_s16(svint16_t op1, svint16_t op2, int16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlah.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z20test_svqrdmlah_n_s32u11__SVInt32_tu11__SVInt32_ti( +// CPP-CHECK-LABEL: @_Z20test_svqrdmlah_n_s32u11__SVInt32_tS_i( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -139,7 +139,7 @@ svint32_t test_svqrdmlah_n_s32(svint32_t op1, svint32_t op2, int32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlah.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z20test_svqrdmlah_n_s64u11__SVInt64_tu11__SVInt64_tl( +// CPP-CHECK-LABEL: @_Z20test_svqrdmlah_n_s64u11__SVInt64_tS_l( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -156,7 +156,7 @@ svint64_t test_svqrdmlah_n_s64(svint64_t op1, svint64_t op2, int64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlah.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svqrdmlah_lane_s16u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z23test_svqrdmlah_lane_s16u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlah.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -171,7 +171,7 @@ svint16_t test_svqrdmlah_lane_s16(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlah.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z25test_svqrdmlah_lane_s16_1u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z25test_svqrdmlah_lane_s16_1u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlah.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -186,7 +186,7 @@ svint16_t test_svqrdmlah_lane_s16_1(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlah.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svqrdmlah_lane_s32u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z23test_svqrdmlah_lane_s32u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlah.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -201,7 +201,7 @@ svint32_t test_svqrdmlah_lane_s32(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlah.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z25test_svqrdmlah_lane_s32_1u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z25test_svqrdmlah_lane_s32_1u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlah.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -216,7 +216,7 @@ svint32_t test_svqrdmlah_lane_s32_1(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlah.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svqrdmlah_lane_s64u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z23test_svqrdmlah_lane_s64u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlah.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -231,7 +231,7 @@ svint64_t test_svqrdmlah_lane_s64(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlah.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z25test_svqrdmlah_lane_s64_1u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z25test_svqrdmlah_lane_s64_1u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlah.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qrdmlsh.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qrdmlsh.c index 88a55ffdaf6f4..874d51588c6b6 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qrdmlsh.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qrdmlsh.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlsh.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svqrdmlsh_s8u10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svqrdmlsh_s8u10__SVInt8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlsh.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svqrdmlsh_s8(svint8_t op1, svint8_t op2, svint8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlsh.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqrdmlsh_s16u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svqrdmlsh_s16u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlsh.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_svqrdmlsh_s16(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlsh.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqrdmlsh_s32u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svqrdmlsh_s32u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlsh.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_svqrdmlsh_s32(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlsh.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqrdmlsh_s64u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svqrdmlsh_s64u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlsh.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -82,7 +82,7 @@ svint64_t test_svqrdmlsh_s64(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlsh.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svqrdmlsh_n_s8u10__SVInt8_tu10__SVInt8_ta( +// CPP-CHECK-LABEL: @_Z19test_svqrdmlsh_n_s8u10__SVInt8_tS_a( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -101,7 +101,7 @@ svint8_t test_svqrdmlsh_n_s8(svint8_t op1, svint8_t op2, int8_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlsh.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z20test_svqrdmlsh_n_s16u11__SVInt16_tu11__SVInt16_ts( +// CPP-CHECK-LABEL: @_Z20test_svqrdmlsh_n_s16u11__SVInt16_tS_s( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -120,7 +120,7 @@ svint16_t test_svqrdmlsh_n_s16(svint16_t op1, svint16_t op2, int16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlsh.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z20test_svqrdmlsh_n_s32u11__SVInt32_tu11__SVInt32_ti( +// CPP-CHECK-LABEL: @_Z20test_svqrdmlsh_n_s32u11__SVInt32_tS_i( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -139,7 +139,7 @@ svint32_t test_svqrdmlsh_n_s32(svint32_t op1, svint32_t op2, int32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlsh.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z20test_svqrdmlsh_n_s64u11__SVInt64_tu11__SVInt64_tl( +// CPP-CHECK-LABEL: @_Z20test_svqrdmlsh_n_s64u11__SVInt64_tS_l( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -156,7 +156,7 @@ svint64_t test_svqrdmlsh_n_s64(svint64_t op1, svint64_t op2, int64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlsh.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svqrdmlsh_lane_s16u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z23test_svqrdmlsh_lane_s16u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlsh.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -171,7 +171,7 @@ svint16_t test_svqrdmlsh_lane_s16(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlsh.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z25test_svqrdmlsh_lane_s16_1u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z25test_svqrdmlsh_lane_s16_1u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlsh.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -186,7 +186,7 @@ svint16_t test_svqrdmlsh_lane_s16_1(svint16_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlsh.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svqrdmlsh_lane_s32u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z23test_svqrdmlsh_lane_s32u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlsh.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -201,7 +201,7 @@ svint32_t test_svqrdmlsh_lane_s32(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlsh.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z25test_svqrdmlsh_lane_s32_1u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z25test_svqrdmlsh_lane_s32_1u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlsh.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -216,7 +216,7 @@ svint32_t test_svqrdmlsh_lane_s32_1(svint32_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlsh.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svqrdmlsh_lane_s64u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z23test_svqrdmlsh_lane_s64u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlsh.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -231,7 +231,7 @@ svint64_t test_svqrdmlsh_lane_s64(svint64_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlsh.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z25test_svqrdmlsh_lane_s64_1u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z25test_svqrdmlsh_lane_s64_1u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmlsh.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qrdmulh.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qrdmulh.c index 6fcdf45d2cc94..59f6ce9cf391f 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qrdmulh.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qrdmulh.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmulh.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svqrdmulh_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svqrdmulh_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmulh.nxv16i8( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svqrdmulh_s8(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmulh.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqrdmulh_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svqrdmulh_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmulh.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_svqrdmulh_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmulh.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqrdmulh_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svqrdmulh_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmulh.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_svqrdmulh_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmulh.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svqrdmulh_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svqrdmulh_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmulh.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -156,7 +156,7 @@ svint64_t test_svqrdmulh_n_s64(svint64_t op1, int64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmulh.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svqrdmulh_lane_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z23test_svqrdmulh_lane_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmulh.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -171,7 +171,7 @@ svint16_t test_svqrdmulh_lane_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmulh.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z25test_svqrdmulh_lane_s16_1u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z25test_svqrdmulh_lane_s16_1u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmulh.lane.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -186,7 +186,7 @@ svint16_t test_svqrdmulh_lane_s16_1(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmulh.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svqrdmulh_lane_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z23test_svqrdmulh_lane_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmulh.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -201,7 +201,7 @@ svint32_t test_svqrdmulh_lane_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmulh.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z25test_svqrdmulh_lane_s32_1u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z25test_svqrdmulh_lane_s32_1u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmulh.lane.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -216,7 +216,7 @@ svint32_t test_svqrdmulh_lane_s32_1(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmulh.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z23test_svqrdmulh_lane_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z23test_svqrdmulh_lane_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmulh.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -231,7 +231,7 @@ svint64_t test_svqrdmulh_lane_s64(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmulh.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z25test_svqrdmulh_lane_s64_1u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z25test_svqrdmulh_lane_s64_1u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrdmulh.lane.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qrshl.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qrshl.c index 9ff170a65ddb9..355d06e3aab89 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qrshl.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qrshl.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqrshl_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svqrshl_s8_zu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -39,7 +39,7 @@ svint8_t test_svqrshl_s8_z(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svqrshl_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svqrshl_s16_zu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -58,7 +58,7 @@ svint16_t test_svqrshl_s16_z(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svqrshl_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svqrshl_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -77,7 +77,7 @@ svint32_t test_svqrshl_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svqrshl_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svqrshl_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -168,7 +168,7 @@ svuint64_t test_svqrshl_u64_z(svbool_t pg, svuint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svqrshl_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svqrshl_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -184,7 +184,7 @@ svint8_t test_svqrshl_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svqrshl_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svqrshl_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -201,7 +201,7 @@ svint16_t test_svqrshl_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svqrshl_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svqrshl_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -218,7 +218,7 @@ svint32_t test_svqrshl_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svqrshl_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svqrshl_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -300,7 +300,7 @@ svuint64_t test_svqrshl_u64_m(svbool_t pg, svuint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svqrshl_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svqrshl_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -316,7 +316,7 @@ svint8_t test_svqrshl_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svqrshl_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svqrshl_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -333,7 +333,7 @@ svint16_t test_svqrshl_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svqrshl_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svqrshl_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -350,7 +350,7 @@ svint32_t test_svqrshl_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svqrshl_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svqrshl_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qshl.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qshl.c index 55e26ed4ce666..d2aa140ec1718 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qshl.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qshl.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svqshl_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svqshl_s8_zu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -39,7 +39,7 @@ svint8_t test_svqshl_s8_z(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svqshl_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svqshl_s16_zu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -58,7 +58,7 @@ svint16_t test_svqshl_s16_z(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svqshl_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svqshl_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -77,7 +77,7 @@ svint32_t test_svqshl_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svqshl_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svqshl_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -168,7 +168,7 @@ svuint64_t test_svqshl_u64_z(svbool_t pg, svuint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svqshl_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svqshl_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -184,7 +184,7 @@ svint8_t test_svqshl_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqshl_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svqshl_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -201,7 +201,7 @@ svint16_t test_svqshl_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqshl_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svqshl_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -218,7 +218,7 @@ svint32_t test_svqshl_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqshl_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svqshl_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -300,7 +300,7 @@ svuint64_t test_svqshl_u64_m(svbool_t pg, svuint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svqshl_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svqshl_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -316,7 +316,7 @@ svint8_t test_svqshl_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqshl_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svqshl_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -333,7 +333,7 @@ svint16_t test_svqshl_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqshl_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svqshl_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -350,7 +350,7 @@ svint32_t test_svqshl_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqshl_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svqshl_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qsub.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qsub.c index aad06b79a5f5f..195b917868285 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qsub.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qsub.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsub.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svqsub_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svqsub_s8_zu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsub.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -39,7 +39,7 @@ svint8_t test_svqsub_s8_z(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sqsub.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svqsub_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svqsub_s16_zu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -58,7 +58,7 @@ svint16_t test_svqsub_s16_z(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sqsub.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svqsub_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svqsub_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -77,7 +77,7 @@ svint32_t test_svqsub_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sqsub.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svqsub_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svqsub_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -95,7 +95,7 @@ svint64_t test_svqsub_s64_z(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsub.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svqsub_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svqsub_u8_zu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsub.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -113,7 +113,7 @@ svuint8_t test_svqsub_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uqsub.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svqsub_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svqsub_u16_zu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -132,7 +132,7 @@ svuint16_t test_svqsub_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uqsub.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svqsub_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svqsub_u32_zu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -151,7 +151,7 @@ svuint32_t test_svqsub_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uqsub.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svqsub_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svqsub_u64_zu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -168,7 +168,7 @@ svuint64_t test_svqsub_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqsub.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svqsub_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svqsub_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqsub.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -184,7 +184,7 @@ svint8_t test_svqsub_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsub.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqsub_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svqsub_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsub.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -201,7 +201,7 @@ svint16_t test_svqsub_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsub.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqsub_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svqsub_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsub.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -218,7 +218,7 @@ svint32_t test_svqsub_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsub.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqsub_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svqsub_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsub.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -234,7 +234,7 @@ svint64_t test_svqsub_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqsub.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svqsub_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svqsub_u8_mu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqsub.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -250,7 +250,7 @@ svuint8_t test_svqsub_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsub.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqsub_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svqsub_u16_mu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsub.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -267,7 +267,7 @@ svuint16_t test_svqsub_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsub.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqsub_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svqsub_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsub.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -284,7 +284,7 @@ svuint32_t test_svqsub_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsub.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqsub_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svqsub_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsub.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -300,7 +300,7 @@ svuint64_t test_svqsub_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqsub.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svqsub_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svqsub_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqsub.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -316,7 +316,7 @@ svint8_t test_svqsub_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsub.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqsub_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svqsub_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsub.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -333,7 +333,7 @@ svint16_t test_svqsub_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsub.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqsub_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svqsub_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsub.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -350,7 +350,7 @@ svint32_t test_svqsub_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsub.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqsub_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svqsub_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsub.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -366,7 +366,7 @@ svint64_t test_svqsub_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqsub.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svqsub_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svqsub_u8_xu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqsub.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -382,7 +382,7 @@ svuint8_t test_svqsub_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsub.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqsub_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svqsub_u16_xu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsub.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -399,7 +399,7 @@ svuint16_t test_svqsub_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsub.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqsub_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svqsub_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsub.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -416,7 +416,7 @@ svuint32_t test_svqsub_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsub.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqsub_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svqsub_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsub.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qsubr.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qsubr.c index af9f30f44d66e..5dbfbd040af7b 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qsubr.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qsubr.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsubr.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqsubr_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svqsubr_s8_zu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsubr.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -39,7 +39,7 @@ svint8_t test_svqsubr_s8_z(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sqsubr.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svqsubr_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svqsubr_s16_zu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -58,7 +58,7 @@ svint16_t test_svqsubr_s16_z(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sqsubr.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svqsubr_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svqsubr_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -77,7 +77,7 @@ svint32_t test_svqsubr_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sqsubr.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svqsubr_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svqsubr_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -95,7 +95,7 @@ svint64_t test_svqsubr_s64_z(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsubr.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svqsubr_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z17test_svqsubr_u8_zu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsubr.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -113,7 +113,7 @@ svuint8_t test_svqsubr_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uqsubr.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svqsubr_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z18test_svqsubr_u16_zu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -132,7 +132,7 @@ svuint16_t test_svqsubr_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uqsubr.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svqsubr_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z18test_svqsubr_u32_zu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -151,7 +151,7 @@ svuint32_t test_svqsubr_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uqsubr.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svqsubr_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z18test_svqsubr_u64_zu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -168,7 +168,7 @@ svuint64_t test_svqsubr_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqsubr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svqsubr_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svqsubr_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqsubr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -184,7 +184,7 @@ svint8_t test_svqsubr_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsubr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svqsubr_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svqsubr_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsubr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -201,7 +201,7 @@ svint16_t test_svqsubr_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsubr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svqsubr_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svqsubr_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsubr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -218,7 +218,7 @@ svint32_t test_svqsubr_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsubr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svqsubr_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svqsubr_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsubr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -234,7 +234,7 @@ svint64_t test_svqsubr_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqsubr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svqsubr_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z17test_svqsubr_u8_mu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqsubr.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -250,7 +250,7 @@ svuint8_t test_svqsubr_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsubr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svqsubr_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z18test_svqsubr_u16_mu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsubr.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -267,7 +267,7 @@ svuint16_t test_svqsubr_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsubr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svqsubr_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z18test_svqsubr_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsubr.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -284,7 +284,7 @@ svuint32_t test_svqsubr_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsubr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svqsubr_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z18test_svqsubr_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsubr.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -300,7 +300,7 @@ svuint64_t test_svqsubr_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqsub.u.nxv16i8( [[PG:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svqsubr_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svqsubr_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqsub.u.nxv16i8( [[PG:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -316,7 +316,7 @@ svint8_t test_svqsubr_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsub.u.nxv8i16( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svqsubr_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svqsubr_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsub.u.nxv8i16( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -333,7 +333,7 @@ svint16_t test_svqsubr_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsub.u.nxv4i32( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svqsubr_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svqsubr_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsub.u.nxv4i32( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -350,7 +350,7 @@ svint32_t test_svqsubr_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsub.u.nxv2i64( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svqsubr_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svqsubr_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqsub.u.nxv2i64( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -366,7 +366,7 @@ svint64_t test_svqsubr_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqsub.u.nxv16i8( [[PG:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svqsubr_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z17test_svqsubr_u8_xu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqsub.u.nxv16i8( [[PG:%.*]], [[OP2:%.*]], [[OP1:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -382,7 +382,7 @@ svuint8_t test_svqsubr_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsub.u.nxv8i16( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svqsubr_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z18test_svqsubr_u16_xu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsub.u.nxv8i16( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -399,7 +399,7 @@ svuint16_t test_svqsubr_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsub.u.nxv4i32( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svqsubr_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z18test_svqsubr_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsub.u.nxv4i32( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) @@ -416,7 +416,7 @@ svuint32_t test_svqsubr_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsub.u.nxv2i64( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svqsubr_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z18test_svqsubr_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqsub.u.nxv2i64( [[TMP0]], [[OP2:%.*]], [[OP1:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_raddhnb.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_raddhnb.c index 4363d54b52424..9a1bd47b15d6e 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_raddhnb.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_raddhnb.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.raddhnb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svraddhnb_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svraddhnb_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.raddhnb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svraddhnb_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.raddhnb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svraddhnb_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svraddhnb_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.raddhnb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_svraddhnb_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.raddhnb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svraddhnb_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svraddhnb_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.raddhnb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_svraddhnb_s64(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.raddhnb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svraddhnb_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z18test_svraddhnb_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.raddhnb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svuint8_t test_svraddhnb_u16(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.raddhnb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svraddhnb_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z18test_svraddhnb_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.raddhnb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint16_t test_svraddhnb_u32(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.raddhnb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svraddhnb_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z18test_svraddhnb_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.raddhnb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_raddhnt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_raddhnt.c index 9234511ca5188..1c3935c13fa79 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_raddhnt.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_raddhnt.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.raddhnt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svraddhnt_s16u10__SVInt8_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svraddhnt_s16u10__SVInt8_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.raddhnt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svraddhnt_s16(svint8_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.raddhnt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svraddhnt_s32u11__SVInt16_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svraddhnt_s32u11__SVInt16_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.raddhnt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_svraddhnt_s32(svint16_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.raddhnt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svraddhnt_s64u11__SVInt32_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svraddhnt_s64u11__SVInt32_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.raddhnt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_svraddhnt_s64(svint32_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.raddhnt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svraddhnt_u16u11__SVUint8_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z18test_svraddhnt_u16u11__SVUint8_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.raddhnt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svuint8_t test_svraddhnt_u16(svuint8_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.raddhnt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svraddhnt_u32u12__SVUint16_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z18test_svraddhnt_u32u12__SVUint16_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.raddhnt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint16_t test_svraddhnt_u32(svuint16_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.raddhnt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svraddhnt_u64u12__SVUint32_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z18test_svraddhnt_u64u12__SVUint32_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.raddhnt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rax1.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rax1.c index 78b84c776fbd2..d0875525b9532 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rax1.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rax1.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rax1( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svrax1_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z15test_svrax1_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rax1( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint64_t test_svrax1_s64(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rax1( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svrax1_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z15test_svrax1_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rax1( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_recpe.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_recpe.c index 30eae0870bfe4..71ccf1b9154eb 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_recpe.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_recpe.c @@ -38,7 +38,7 @@ svuint32_t test_svrecpe_u32_z(svbool_t pg, svuint32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urecpe.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrecpe_u32_mu12__SVUint32_tu10__SVBool_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z18test_svrecpe_u32_mu12__SVUint32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urecpe.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_revd.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_revd.c new file mode 100644 index 0000000000000..826d4da0cbb3d --- /dev/null +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_revd.c @@ -0,0 +1,390 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// REQUIRES: aarch64-registered-target +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu \ +// RUN: -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu \ +// RUN: -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu \ +// RUN: -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu \ +// RUN: -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK + +#include + +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 +#endif + +// CHECK-LABEL: @test_svrevd_s8_z( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.revd.nxv16i8( zeroinitializer, [[PG:%.*]], [[OP:%.*]]) +// CHECK-NEXT: ret [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z16test_svrevd_s8_zu10__SVBool_tu10__SVInt8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.revd.nxv16i8( zeroinitializer, [[PG:%.*]], [[OP:%.*]]) +// CPP-CHECK-NEXT: ret [[TMP0]] +// +svint8_t test_svrevd_s8_z(svbool_t pg, svint8_t op) { + return SVE_ACLE_FUNC(svrevd, _s8, _z, )(pg, op); +} + +// CHECK-LABEL: @test_svrevd_s16_z( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv8i16( zeroinitializer, [[TMP0]], [[OP:%.*]]) +// CHECK-NEXT: ret [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z17test_svrevd_s16_zu10__SVBool_tu11__SVInt16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv8i16( zeroinitializer, [[TMP0]], [[OP:%.*]]) +// CPP-CHECK-NEXT: ret [[TMP1]] +// +svint16_t test_svrevd_s16_z(svbool_t pg, svint16_t op) { + return SVE_ACLE_FUNC(svrevd, _s16, _z, )(pg, op); +} + +// CHECK-LABEL: @test_svrevd_s32_z( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv4i32( zeroinitializer, [[TMP0]], [[OP:%.*]]) +// CHECK-NEXT: ret [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z17test_svrevd_s32_zu10__SVBool_tu11__SVInt32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv4i32( zeroinitializer, [[TMP0]], [[OP:%.*]]) +// CPP-CHECK-NEXT: ret [[TMP1]] +// +svint32_t test_svrevd_s32_z(svbool_t pg, svint32_t op) { + return SVE_ACLE_FUNC(svrevd, _s32, _z, )(pg, op); +} + +// CHECK-LABEL: @test_svrevd_s64_z( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv2i64( zeroinitializer, [[TMP0]], [[OP:%.*]]) +// CHECK-NEXT: ret [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z17test_svrevd_s64_zu10__SVBool_tu11__SVInt64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv2i64( zeroinitializer, [[TMP0]], [[OP:%.*]]) +// CPP-CHECK-NEXT: ret [[TMP1]] +// +svint64_t test_svrevd_s64_z(svbool_t pg, svint64_t op) { + return SVE_ACLE_FUNC(svrevd, _s64, _z, )(pg, op); +} + +// CHECK-LABEL: @test_svrevd_u8_z( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.revd.nxv16i8( zeroinitializer, [[PG:%.*]], [[OP:%.*]]) +// CHECK-NEXT: ret [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z16test_svrevd_u8_zu10__SVBool_tu11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.revd.nxv16i8( zeroinitializer, [[PG:%.*]], [[OP:%.*]]) +// CPP-CHECK-NEXT: ret [[TMP0]] +// +svuint8_t test_svrevd_u8_z(svbool_t pg, svuint8_t op) { + return SVE_ACLE_FUNC(svrevd, _u8, _z, )(pg, op); +} +// CHECK-LABEL: @test_svrevd_u16_z( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv8i16( zeroinitializer, [[TMP0]], [[OP:%.*]]) +// CHECK-NEXT: ret [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z17test_svrevd_u16_zu10__SVBool_tu12__SVUint16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv8i16( zeroinitializer, [[TMP0]], [[OP:%.*]]) +// CPP-CHECK-NEXT: ret [[TMP1]] +// +svuint16_t test_svrevd_u16_z(svbool_t pg, svuint16_t op) { + return SVE_ACLE_FUNC(svrevd, _u16, _z, )(pg, op); +} + +// CHECK-LABEL: @test_svrevd_u32_z( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv4i32( zeroinitializer, [[TMP0]], [[OP:%.*]]) +// CHECK-NEXT: ret [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z17test_svrevd_u32_zu10__SVBool_tu12__SVUint32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv4i32( zeroinitializer, [[TMP0]], [[OP:%.*]]) +// CPP-CHECK-NEXT: ret [[TMP1]] +// +svuint32_t test_svrevd_u32_z(svbool_t pg, svuint32_t op) { + return SVE_ACLE_FUNC(svrevd, _u32, _z, )(pg, op); +} + +// CHECK-LABEL: @test_svrevd_u64_z( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv2i64( zeroinitializer, [[TMP0]], [[OP:%.*]]) +// CHECK-NEXT: ret [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z17test_svrevd_u64_zu10__SVBool_tu12__SVUint64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv2i64( zeroinitializer, [[TMP0]], [[OP:%.*]]) +// CPP-CHECK-NEXT: ret [[TMP1]] +// +svuint64_t test_svrevd_u64_z(svbool_t pg, svuint64_t op) { + return SVE_ACLE_FUNC(svrevd, _u64, _z, )(pg, op); +} + +// CHECK-LABEL: @test_svrevd_s8_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.revd.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) +// CHECK-NEXT: ret [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z16test_svrevd_s8_mu10__SVInt8_tu10__SVBool_tS_( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.revd.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) +// CPP-CHECK-NEXT: ret [[TMP0]] +// +svint8_t test_svrevd_s8_m(svint8_t inactive, svbool_t pg, svint8_t op) { + return SVE_ACLE_FUNC(svrevd, _s8, _m, )(inactive, pg, op); +} + +// CHECK-LABEL: @test_svrevd_s16_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) +// CHECK-NEXT: ret [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z17test_svrevd_s16_mu11__SVInt16_tu10__SVBool_tS_( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) +// CPP-CHECK-NEXT: ret [[TMP1]] +// +svint16_t test_svrevd_s16_m(svint16_t inactive, svbool_t pg, svint16_t op) { + return SVE_ACLE_FUNC(svrevd, _s16, _m, )(inactive, pg, op); +} + +// CHECK-LABEL: @test_svrevd_s32_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) +// CHECK-NEXT: ret [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z17test_svrevd_s32_mu11__SVInt32_tu10__SVBool_tS_( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) +// CPP-CHECK-NEXT: ret [[TMP1]] +// +svint32_t test_svrevd_s32_m(svint32_t inactive, svbool_t pg, svint32_t op) { + return SVE_ACLE_FUNC(svrevd, _s32, _m, )(inactive, pg, op); +} + +// CHECK-LABEL: @test_svrevd_s64_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) +// CHECK-NEXT: ret [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z17test_svrevd_s64_mu11__SVInt64_tu10__SVBool_tS_( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) +// CPP-CHECK-NEXT: ret [[TMP1]] +// +svint64_t test_svrevd_s64_m(svint64_t inactive, svbool_t pg, svint64_t op) { + return SVE_ACLE_FUNC(svrevd, _s64, _m, )(inactive, pg, op); +} + +// CHECK-LABEL: @test_svrevd_u8_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.revd.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) +// CHECK-NEXT: ret [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z16test_svrevd_u8_mu11__SVUint8_tu10__SVBool_tS_( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.revd.nxv16i8( [[INACTIVE:%.*]], [[PG:%.*]], [[OP:%.*]]) +// CPP-CHECK-NEXT: ret [[TMP0]] +// +svuint8_t test_svrevd_u8_m(svuint8_t inactive, svbool_t pg, svuint8_t op) { + return SVE_ACLE_FUNC(svrevd, _u8, _m, )(inactive, pg, op); +} + +// CHECK-LABEL: @test_svrevd_u16_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) +// CHECK-NEXT: ret [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z17test_svrevd_u16_mu12__SVUint16_tu10__SVBool_tS_( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv8i16( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) +// CPP-CHECK-NEXT: ret [[TMP1]] +// +svuint16_t test_svrevd_u16_m(svuint16_t inactive, svbool_t pg, svuint16_t op) { + return SVE_ACLE_FUNC(svrevd, _u16, _m, )(inactive, pg, op); +} + +// CHECK-LABEL: @test_svrevd_u32_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) +// CHECK-NEXT: ret [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z17test_svrevd_u32_mu12__SVUint32_tu10__SVBool_tS_( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) +// CPP-CHECK-NEXT: ret [[TMP1]] +// +svuint32_t test_svrevd_u32_m(svuint32_t inactive, svbool_t pg, svuint32_t op) { + return SVE_ACLE_FUNC(svrevd, _u32, _m, )(inactive, pg, op); +} + +// CHECK-LABEL: @test_svrevd_u64_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) +// CHECK-NEXT: ret [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z17test_svrevd_u64_mu12__SVUint64_tu10__SVBool_tS_( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv2i64( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) +// CPP-CHECK-NEXT: ret [[TMP1]] +// +svuint64_t test_svrevd_u64_m(svuint64_t inactive, svbool_t pg, svuint64_t op) { + return SVE_ACLE_FUNC(svrevd, _u64, _m, )(inactive, pg, op); +} + +// CHECK-LABEL: @test_svrevd_s8_x( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.revd.nxv16i8( undef, [[PG:%.*]], [[OP:%.*]]) +// CHECK-NEXT: ret [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z16test_svrevd_s8_xu10__SVBool_tu10__SVInt8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.revd.nxv16i8( undef, [[PG:%.*]], [[OP:%.*]]) +// CPP-CHECK-NEXT: ret [[TMP0]] +// +svint8_t test_svrevd_s8_x(svbool_t pg, svint8_t op) { + return SVE_ACLE_FUNC(svrevd, _s8, _x, )(pg, op); +} + +// CHECK-LABEL: @test_svrevd_s16_x( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv8i16( undef, [[TMP0]], [[OP:%.*]]) +// CHECK-NEXT: ret [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z17test_svrevd_s16_xu10__SVBool_tu11__SVInt16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv8i16( undef, [[TMP0]], [[OP:%.*]]) +// CPP-CHECK-NEXT: ret [[TMP1]] +// +svint16_t test_svrevd_s16_x(svbool_t pg, svint16_t op) { + return SVE_ACLE_FUNC(svrevd, _s16, _x, )(pg, op); +} + +// CHECK-LABEL: @test_svrevd_s32_x( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv4i32( undef, [[TMP0]], [[OP:%.*]]) +// CHECK-NEXT: ret [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z17test_svrevd_s32_xu10__SVBool_tu11__SVInt32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv4i32( undef, [[TMP0]], [[OP:%.*]]) +// CPP-CHECK-NEXT: ret [[TMP1]] +// +svint32_t test_svrevd_s32_x(svbool_t pg, svint32_t op) { + return SVE_ACLE_FUNC(svrevd, _s32, _x, )(pg, op); +} + +// CHECK-LABEL: @test_svrevd_s64_x( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv2i64( undef, [[TMP0]], [[OP:%.*]]) +// CHECK-NEXT: ret [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z17test_svrevd_s64_xu10__SVBool_tu11__SVInt64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv2i64( undef, [[TMP0]], [[OP:%.*]]) +// CPP-CHECK-NEXT: ret [[TMP1]] +// +svint64_t test_svrevd_s64_x(svbool_t pg, svint64_t op) { + return SVE_ACLE_FUNC(svrevd, _s64, _x, )(pg, op); +} + +// CHECK-LABEL: @test_svrevd_u8_x( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.revd.nxv16i8( undef, [[PG:%.*]], [[OP:%.*]]) +// CHECK-NEXT: ret [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z16test_svrevd_u8_xu10__SVBool_tu11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.revd.nxv16i8( undef, [[PG:%.*]], [[OP:%.*]]) +// CPP-CHECK-NEXT: ret [[TMP0]] +// +svuint8_t test_svrevd_u8_x(svbool_t pg, svuint8_t op) { + return SVE_ACLE_FUNC(svrevd, _u8, _x, )(pg, op); +} + +// CHECK-LABEL: @test_svrevd_u16_x( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv8i16( undef, [[TMP0]], [[OP:%.*]]) +// CHECK-NEXT: ret [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z17test_svrevd_u16_xu10__SVBool_tu12__SVUint16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv8i16( undef, [[TMP0]], [[OP:%.*]]) +// CPP-CHECK-NEXT: ret [[TMP1]] +// +svuint16_t test_svrevd_u16_x(svbool_t pg, svuint16_t op) { + return SVE_ACLE_FUNC(svrevd, _u16, _x, )(pg, op); +} + +// CHECK-LABEL: @test_svrevd_u32_x( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv4i32( undef, [[TMP0]], [[OP:%.*]]) +// CHECK-NEXT: ret [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z17test_svrevd_u32_xu10__SVBool_tu12__SVUint32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv4i32( undef, [[TMP0]], [[OP:%.*]]) +// CPP-CHECK-NEXT: ret [[TMP1]] +// +svuint32_t test_svrevd_u32_x(svbool_t pg, svuint32_t op) { + return SVE_ACLE_FUNC(svrevd, _u32, _x, )(pg, op); +} + +// CHECK-LABEL: @test_svrevd_u64_x( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv2i64( undef, [[TMP0]], [[OP:%.*]]) +// CHECK-NEXT: ret [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z17test_svrevd_u64_xu10__SVBool_tu12__SVUint64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.revd.nxv2i64( undef, [[TMP0]], [[OP:%.*]]) +// CPP-CHECK-NEXT: ret [[TMP1]] +// +svuint64_t test_svrevd_u64_x(svbool_t pg, svuint64_t op) { + return SVE_ACLE_FUNC(svrevd, _u64, _x, )(pg, op); +} diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rhadd.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rhadd.c index 0c1c7547a251d..24884520ce227 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rhadd.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rhadd.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srhadd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svrhadd_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svrhadd_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srhadd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svrhadd_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srhadd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrhadd_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svrhadd_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srhadd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -52,7 +52,7 @@ svint16_t test_svrhadd_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srhadd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrhadd_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svrhadd_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srhadd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -69,7 +69,7 @@ svint32_t test_svrhadd_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srhadd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrhadd_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svrhadd_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srhadd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -85,7 +85,7 @@ svint64_t test_svrhadd_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.urhadd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svrhadd_u8_mu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z17test_svrhadd_u8_mu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.urhadd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -101,7 +101,7 @@ svuint8_t test_svrhadd_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urhadd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrhadd_u16_mu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z18test_svrhadd_u16_mu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urhadd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -118,7 +118,7 @@ svuint16_t test_svrhadd_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urhadd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrhadd_u32_mu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z18test_svrhadd_u32_mu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urhadd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -136,7 +136,7 @@ svuint32_t test_svrhadd_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urhadd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrhadd_u64_mu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z18test_svrhadd_u64_mu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urhadd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -317,7 +317,7 @@ svuint64_t test_svrhadd_n_u64_m(svbool_t pg, svuint64_t op1, uint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srhadd.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrhadd_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svrhadd_s8_zu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srhadd.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -335,7 +335,7 @@ svint8_t test_svrhadd_s8_z(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.srhadd.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svrhadd_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svrhadd_s16_zu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -354,7 +354,7 @@ svint16_t test_svrhadd_s16_z(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.srhadd.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svrhadd_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svrhadd_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -373,7 +373,7 @@ svint32_t test_svrhadd_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.srhadd.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svrhadd_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svrhadd_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -391,7 +391,7 @@ svint64_t test_svrhadd_s64_z(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urhadd.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrhadd_u8_zu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z17test_svrhadd_u8_zu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urhadd.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -409,7 +409,7 @@ svuint8_t test_svrhadd_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.urhadd.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svrhadd_u16_zu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z18test_svrhadd_u16_zu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -428,7 +428,7 @@ svuint16_t test_svrhadd_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.urhadd.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svrhadd_u32_zu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z18test_svrhadd_u32_zu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -448,7 +448,7 @@ svuint32_t test_svrhadd_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.urhadd.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z18test_svrhadd_u64_zu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z18test_svrhadd_u64_zu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -645,7 +645,7 @@ svuint64_t test_svrhadd_n_u64_z(svbool_t pg, svuint64_t op1, uint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srhadd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svrhadd_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svrhadd_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srhadd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -661,7 +661,7 @@ svint8_t test_svrhadd_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srhadd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrhadd_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svrhadd_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srhadd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -678,7 +678,7 @@ svint16_t test_svrhadd_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srhadd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrhadd_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svrhadd_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srhadd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -695,7 +695,7 @@ svint32_t test_svrhadd_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srhadd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrhadd_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svrhadd_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srhadd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -711,7 +711,7 @@ svint64_t test_svrhadd_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.urhadd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svrhadd_u8_xu10__SVBool_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z17test_svrhadd_u8_xu10__SVBool_tu11__SVUint8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.urhadd.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -727,7 +727,7 @@ svuint8_t test_svrhadd_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urhadd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrhadd_u16_xu10__SVBool_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z18test_svrhadd_u16_xu10__SVBool_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urhadd.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -744,7 +744,7 @@ svuint16_t test_svrhadd_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urhadd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrhadd_u32_xu10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z18test_svrhadd_u32_xu10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urhadd.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -762,7 +762,7 @@ svuint32_t test_svrhadd_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urhadd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z18test_svrhadd_u64_xu10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z18test_svrhadd_u64_xu10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urhadd.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rshl.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rshl.c index 9de10afd65e08..5f9acc5bc5e8a 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rshl.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rshl.c @@ -21,7 +21,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z16test_svrshl_s8_zu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svrshl_s8_zu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = select [[PG:%.*]], [[OP1:%.*]], zeroinitializer // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv16i8( [[PG]], [[TMP0]], [[OP2:%.*]]) @@ -39,7 +39,7 @@ svint8_t test_svrshl_s8_z(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv8i16( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svrshl_s16_zu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svrshl_s16_zu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -58,7 +58,7 @@ svint16_t test_svrshl_s16_z(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv4i32( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svrshl_s32_zu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svrshl_s32_zu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -77,7 +77,7 @@ svint32_t test_svrshl_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv2i64( [[TMP0]], [[TMP1]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP2]] // -// CPP-CHECK-LABEL: @_Z17test_svrshl_s64_zu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svrshl_s64_zu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = select [[TMP0]], [[OP1:%.*]], zeroinitializer @@ -168,7 +168,7 @@ svuint64_t test_svrshl_u64_z(svbool_t pg, svuint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svrshl_s8_mu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svrshl_s8_mu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -184,7 +184,7 @@ svint8_t test_svrshl_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrshl_s16_mu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svrshl_s16_mu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -201,7 +201,7 @@ svint16_t test_svrshl_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrshl_s32_mu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svrshl_s32_mu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -218,7 +218,7 @@ svint32_t test_svrshl_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrshl_s64_mu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svrshl_s64_mu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -300,7 +300,7 @@ svuint64_t test_svrshl_u64_m(svbool_t pg, svuint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svrshl_s8_xu10__SVBool_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svrshl_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -316,7 +316,7 @@ svint8_t test_svrshl_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrshl_s16_xu10__SVBool_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svrshl_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -333,7 +333,7 @@ svint16_t test_svrshl_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrshl_s32_xu10__SVBool_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svrshl_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) @@ -350,7 +350,7 @@ svint32_t test_svrshl_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z17test_svrshl_s64_xu10__SVBool_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svrshl_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rsqrte.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rsqrte.c index 78664ade446a2..591a83cb3f348 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rsqrte.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rsqrte.c @@ -38,7 +38,7 @@ svuint32_t test_svrsqrte_u32_z(svbool_t pg, svuint32_t op) // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.ursqrte.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z19test_svrsqrte_u32_mu12__SVUint32_tu10__SVBool_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z19test_svrsqrte_u32_mu12__SVUint32_tu10__SVBool_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.ursqrte.nxv4i32( [[INACTIVE:%.*]], [[TMP0]], [[OP:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rsra.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rsra.c index d03c43cbf5e2b..c8bfc6a50350c 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rsra.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rsra.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srsra.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svrsra_n_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svrsra_n_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srsra.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svrsra_n_s8(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srsra.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 8) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svrsra_n_s8_1u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z18test_svrsra_n_s8_1u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srsra.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 8) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint8_t test_svrsra_n_s8_1(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srsra.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svrsra_n_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svrsra_n_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srsra.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint16_t test_svrsra_n_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srsra.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 16) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svrsra_n_s16_1u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z19test_svrsra_n_s16_1u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srsra.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 16) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svint16_t test_svrsra_n_s16_1(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srsra.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svrsra_n_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svrsra_n_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srsra.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svint32_t test_svrsra_n_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srsra.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 32) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svrsra_n_s32_1u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z19test_svrsra_n_s32_1u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srsra.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 32) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -110,7 +110,7 @@ svint32_t test_svrsra_n_s32_1(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srsra.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svrsra_n_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svrsra_n_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srsra.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -125,7 +125,7 @@ svint64_t test_svrsra_n_s64(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srsra.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 64) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svrsra_n_s64_1u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z19test_svrsra_n_s64_1u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srsra.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 64) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -140,7 +140,7 @@ svint64_t test_svrsra_n_s64_1(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ursra.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svrsra_n_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svrsra_n_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ursra.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -155,7 +155,7 @@ svuint8_t test_svrsra_n_u8(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ursra.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 8) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svrsra_n_u8_1u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z18test_svrsra_n_u8_1u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ursra.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 8) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -170,7 +170,7 @@ svuint8_t test_svrsra_n_u8_1(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ursra.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svrsra_n_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svrsra_n_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ursra.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -185,7 +185,7 @@ svuint16_t test_svrsra_n_u16(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ursra.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 16) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svrsra_n_u16_1u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z19test_svrsra_n_u16_1u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ursra.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 16) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -200,7 +200,7 @@ svuint16_t test_svrsra_n_u16_1(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ursra.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svrsra_n_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svrsra_n_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ursra.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -215,7 +215,7 @@ svuint32_t test_svrsra_n_u32(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ursra.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 32) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svrsra_n_u32_1u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z19test_svrsra_n_u32_1u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ursra.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 32) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -230,7 +230,7 @@ svuint32_t test_svrsra_n_u32_1(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ursra.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svrsra_n_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svrsra_n_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ursra.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -245,7 +245,7 @@ svuint64_t test_svrsra_n_u64(svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ursra.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 64) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svrsra_n_u64_1u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z19test_svrsra_n_u64_1u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ursra.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 64) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rsubhnb.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rsubhnb.c index d3e8f0028212e..5fe13078119af 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rsubhnb.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rsubhnb.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rsubhnb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svrsubhnb_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svrsubhnb_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rsubhnb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svrsubhnb_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rsubhnb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svrsubhnb_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svrsubhnb_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rsubhnb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_svrsubhnb_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rsubhnb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svrsubhnb_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svrsubhnb_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rsubhnb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_svrsubhnb_s64(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rsubhnb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svrsubhnb_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z18test_svrsubhnb_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rsubhnb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svuint8_t test_svrsubhnb_u16(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rsubhnb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svrsubhnb_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z18test_svrsubhnb_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rsubhnb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint16_t test_svrsubhnb_u32(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rsubhnb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svrsubhnb_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z18test_svrsubhnb_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rsubhnb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rsubhnt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rsubhnt.c index 3d479e513bf61..115b16c53e091 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rsubhnt.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rsubhnt.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rsubhnt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svrsubhnt_s16u10__SVInt8_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svrsubhnt_s16u10__SVInt8_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rsubhnt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svrsubhnt_s16(svint8_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rsubhnt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svrsubhnt_s32u11__SVInt16_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svrsubhnt_s32u11__SVInt16_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rsubhnt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_svrsubhnt_s32(svint16_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rsubhnt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svrsubhnt_s64u11__SVInt32_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svrsubhnt_s64u11__SVInt32_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rsubhnt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_svrsubhnt_s64(svint32_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rsubhnt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svrsubhnt_u16u11__SVUint8_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z18test_svrsubhnt_u16u11__SVUint8_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rsubhnt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svuint8_t test_svrsubhnt_u16(svuint8_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rsubhnt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svrsubhnt_u32u12__SVUint16_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z18test_svrsubhnt_u32u12__SVUint16_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rsubhnt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint16_t test_svrsubhnt_u32(svuint16_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rsubhnt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svrsubhnt_u64u12__SVUint32_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z18test_svrsubhnt_u64u12__SVUint32_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.rsubhnt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sbclb.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sbclb.c index 26c1ffc1f9be9..105e6e9ceef87 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sbclb.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sbclb.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sbclb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsbclb_u32u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svsbclb_u32u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sbclb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svuint32_t test_svsbclb_u32(svuint32_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sbclb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsbclb_u64u12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svsbclb_u64u12__SVUint64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sbclb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -52,7 +52,7 @@ svuint64_t test_svsbclb_u64(svuint64_t op1, svuint64_t op2, svuint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sbclb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svsbclb_n_u32u12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z18test_svsbclb_n_u32u12__SVUint32_tS_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -71,7 +71,7 @@ svuint32_t test_svsbclb_n_u32(svuint32_t op1, svuint32_t op2, uint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sbclb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svsbclb_n_u64u12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z18test_svsbclb_n_u64u12__SVUint64_tS_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sbclt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sbclt.c index cef23098f0b58..dae99532fa075 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sbclt.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sbclt.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sbclt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsbclt_u32u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svsbclt_u32u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sbclt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svuint32_t test_svsbclt_u32(svuint32_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sbclt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsbclt_u64u12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svsbclt_u64u12__SVUint64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sbclt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -52,7 +52,7 @@ svuint64_t test_svsbclt_u64(svuint64_t op1, svuint64_t op2, svuint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sbclt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svsbclt_n_u32u12__SVUint32_tu12__SVUint32_tj( +// CPP-CHECK-LABEL: @_Z18test_svsbclt_n_u32u12__SVUint32_tS_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer @@ -71,7 +71,7 @@ svuint32_t test_svsbclt_n_u32(svuint32_t op1, svuint32_t op2, uint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sbclt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svsbclt_n_u64u12__SVUint64_tu12__SVUint64_tm( +// CPP-CHECK-LABEL: @_Z18test_svsbclt_n_u64u12__SVUint64_tS_m( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP3:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sli.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sli.c index 2f79f36bca2f0..8074c32f87158 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sli.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sli.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svsli_n_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svsli_n_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svsli_n_s8(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svsli_n_s8_1u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svsli_n_s8_1u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint8_t test_svsli_n_s8_1(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsli_n_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svsli_n_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint16_t test_svsli_n_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 15) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svsli_n_s16_1u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svsli_n_s16_1u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 15) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svint16_t test_svsli_n_s16_1(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsli_n_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svsli_n_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svint32_t test_svsli_n_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 31) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svsli_n_s32_1u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svsli_n_s32_1u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 31) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -110,7 +110,7 @@ svint32_t test_svsli_n_s32_1(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsli_n_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svsli_n_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -125,7 +125,7 @@ svint64_t test_svsli_n_s64(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 63) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svsli_n_s64_1u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svsli_n_s64_1u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 63) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -140,7 +140,7 @@ svint64_t test_svsli_n_s64_1(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svsli_n_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svsli_n_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -155,7 +155,7 @@ svuint8_t test_svsli_n_u8(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svsli_n_u8_1u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z17test_svsli_n_u8_1u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -170,7 +170,7 @@ svuint8_t test_svsli_n_u8_1(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsli_n_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svsli_n_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -185,7 +185,7 @@ svuint16_t test_svsli_n_u16(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 15) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svsli_n_u16_1u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z18test_svsli_n_u16_1u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 15) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -200,7 +200,7 @@ svuint16_t test_svsli_n_u16_1(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsli_n_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svsli_n_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -215,7 +215,7 @@ svuint32_t test_svsli_n_u32(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 31) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svsli_n_u32_1u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z18test_svsli_n_u32_1u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 31) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -230,7 +230,7 @@ svuint32_t test_svsli_n_u32_1(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsli_n_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svsli_n_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 0) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -245,7 +245,7 @@ svuint64_t test_svsli_n_u64(svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 63) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svsli_n_u64_1u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z18test_svsli_n_u64_1u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sli.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 63) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sm4e.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sm4e.c index ef725b1bd76dc..bb256a26dd372 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sm4e.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sm4e.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sm4e( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svsm4e_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z15test_svsm4e_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sm4e( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sm4ekey.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sm4ekey.c index 389e70b21c1b1..9676c694b3652 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sm4ekey.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sm4ekey.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sm4ekey( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svsm4ekey_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z18test_svsm4ekey_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sm4ekey( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sra.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sra.c index 4b22be8b0fad1..9659a3ac98c7f 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sra.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sra.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssra.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svsra_n_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svsra_n_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssra.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svsra_n_s8(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssra.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 8) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svsra_n_s8_1u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svsra_n_s8_1u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssra.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 8) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint8_t test_svsra_n_s8_1(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssra.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsra_n_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svsra_n_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssra.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint16_t test_svsra_n_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssra.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 16) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svsra_n_s16_1u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svsra_n_s16_1u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssra.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 16) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svint16_t test_svsra_n_s16_1(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssra.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsra_n_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svsra_n_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssra.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svint32_t test_svsra_n_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssra.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 32) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svsra_n_s32_1u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svsra_n_s32_1u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssra.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 32) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -110,7 +110,7 @@ svint32_t test_svsra_n_s32_1(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssra.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsra_n_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svsra_n_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssra.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -125,7 +125,7 @@ svint64_t test_svsra_n_s64(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssra.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 64) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svsra_n_s64_1u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svsra_n_s64_1u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssra.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 64) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -140,7 +140,7 @@ svint64_t test_svsra_n_s64_1(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usra.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svsra_n_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svsra_n_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usra.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -155,7 +155,7 @@ svuint8_t test_svsra_n_u8(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usra.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 8) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svsra_n_u8_1u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z17test_svsra_n_u8_1u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usra.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 8) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -170,7 +170,7 @@ svuint8_t test_svsra_n_u8_1(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usra.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsra_n_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svsra_n_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usra.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -185,7 +185,7 @@ svuint16_t test_svsra_n_u16(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usra.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 16) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svsra_n_u16_1u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z18test_svsra_n_u16_1u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usra.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 16) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -200,7 +200,7 @@ svuint16_t test_svsra_n_u16_1(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usra.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsra_n_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svsra_n_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usra.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -215,7 +215,7 @@ svuint32_t test_svsra_n_u32(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usra.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 32) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svsra_n_u32_1u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z18test_svsra_n_u32_1u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usra.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 32) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -230,7 +230,7 @@ svuint32_t test_svsra_n_u32_1(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usra.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsra_n_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svsra_n_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usra.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -245,7 +245,7 @@ svuint64_t test_svsra_n_u64(svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usra.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 64) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svsra_n_u64_1u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z18test_svsra_n_u64_1u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usra.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 64) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sri.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sri.c index 6de811d2e0d15..7d35ae814b2e6 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sri.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sri.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svsri_n_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svsri_n_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svsri_n_s8(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 8) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svsri_n_s8_1u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svsri_n_s8_1u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 8) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint8_t test_svsri_n_s8_1(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsri_n_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svsri_n_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint16_t test_svsri_n_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 16) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svsri_n_s16_1u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svsri_n_s16_1u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 16) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svint16_t test_svsri_n_s16_1(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsri_n_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svsri_n_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svint32_t test_svsri_n_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 32) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svsri_n_s32_1u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svsri_n_s32_1u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 32) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -110,7 +110,7 @@ svint32_t test_svsri_n_s32_1(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsri_n_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svsri_n_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -125,7 +125,7 @@ svint64_t test_svsri_n_s64(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 64) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svsri_n_s64_1u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svsri_n_s64_1u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 64) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -140,7 +140,7 @@ svint64_t test_svsri_n_s64_1(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svsri_n_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svsri_n_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -155,7 +155,7 @@ svuint8_t test_svsri_n_u8(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 8) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svsri_n_u8_1u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z17test_svsri_n_u8_1u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 8) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -170,7 +170,7 @@ svuint8_t test_svsri_n_u8_1(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsri_n_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svsri_n_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -185,7 +185,7 @@ svuint16_t test_svsri_n_u16(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 16) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svsri_n_u16_1u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z18test_svsri_n_u16_1u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 16) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -200,7 +200,7 @@ svuint16_t test_svsri_n_u16_1(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsri_n_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svsri_n_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -215,7 +215,7 @@ svuint32_t test_svsri_n_u32(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 32) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svsri_n_u32_1u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z18test_svsri_n_u32_1u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 32) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -230,7 +230,7 @@ svuint32_t test_svsri_n_u32_1(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsri_n_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svsri_n_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -245,7 +245,7 @@ svuint64_t test_svsri_n_u64(svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 64) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svsri_n_u64_1u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z18test_svsri_n_u64_1u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sri.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 64) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1.c index d866c8ac0e4f5..326bbae8d0820 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1.c @@ -53,7 +53,7 @@ void test_svstnt1_scatter_u64base_s64(svbool_t pg, svuint64_t bases, svint64_t d // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i32.nxv4i32( [[DATA:%.*]], [[TMP0]], [[BASES:%.*]], i64 0) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z32test_svstnt1_scatter_u32base_u32u10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z32test_svstnt1_scatter_u32base_u32u10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i32.nxv4i32( [[DATA:%.*]], [[TMP0]], [[BASES:%.*]], i64 0) @@ -69,7 +69,7 @@ void test_svstnt1_scatter_u32base_u32(svbool_t pg, svuint32_t bases, svuint32_t // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i64.nxv2i64( [[DATA:%.*]], [[TMP0]], [[BASES:%.*]], i64 0) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z32test_svstnt1_scatter_u64base_u64u10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z32test_svstnt1_scatter_u64base_u64u10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i64.nxv2i64( [[DATA:%.*]], [[TMP0]], [[BASES:%.*]], i64 0) @@ -117,7 +117,7 @@ void test_svstnt1_scatter_u64base_f64(svbool_t pg, svuint64_t bases, svfloat64_t // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.nxv2i64( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[OFFSETS:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z34test_svstnt1_scatter_s64offset_s64u10__SVBool_tPlu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z34test_svstnt1_scatter_s64offset_s64u10__SVBool_tPlu11__SVInt64_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.nxv2i64( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[OFFSETS:%.*]]) @@ -197,7 +197,7 @@ void test_svstnt1_scatter_u64offset_s64(svbool_t pg, int64_t *base, svuint64_t o // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4i32( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[OFFSETS:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z34test_svstnt1_scatter_u32offset_u32u10__SVBool_tPju12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z34test_svstnt1_scatter_u32offset_u32u10__SVBool_tPju12__SVUint32_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4i32( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[OFFSETS:%.*]]) @@ -213,7 +213,7 @@ void test_svstnt1_scatter_u32offset_u32(svbool_t pg, uint32_t *base, svuint32_t // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.nxv2i64( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[OFFSETS:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z34test_svstnt1_scatter_u64offset_u64u10__SVBool_tPmu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z34test_svstnt1_scatter_u64offset_u64u10__SVBool_tPmu12__SVUint64_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.nxv2i64( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[OFFSETS:%.*]]) @@ -293,7 +293,7 @@ void test_svstnt1_scatter_u64base_offset_s64(svbool_t pg, svuint64_t bases, int6 // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i32.nxv4i32( [[DATA:%.*]], [[TMP0]], [[BASES:%.*]], i64 [[OFFSET:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z39test_svstnt1_scatter_u32base_offset_u32u10__SVBool_tu12__SVUint32_tlu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z39test_svstnt1_scatter_u32base_offset_u32u10__SVBool_tu12__SVUint32_tlS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i32.nxv4i32( [[DATA:%.*]], [[TMP0]], [[BASES:%.*]], i64 [[OFFSET:%.*]]) @@ -309,7 +309,7 @@ void test_svstnt1_scatter_u32base_offset_u32(svbool_t pg, svuint32_t bases, int6 // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i64.nxv2i64( [[DATA:%.*]], [[TMP0]], [[BASES:%.*]], i64 [[OFFSET:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z39test_svstnt1_scatter_u64base_offset_u64u10__SVBool_tu12__SVUint64_tlu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z39test_svstnt1_scatter_u64base_offset_u64u10__SVBool_tu12__SVUint64_tlS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i64.nxv2i64( [[DATA:%.*]], [[TMP0]], [[BASES:%.*]], i64 [[OFFSET:%.*]]) @@ -357,7 +357,7 @@ void test_svstnt1_scatter_u64base_offset_f64(svbool_t pg, svuint64_t bases, int6 // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i64( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z33test_svstnt1_scatter_s64index_s64u10__SVBool_tPlu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z33test_svstnt1_scatter_s64index_s64u10__SVBool_tPlu11__SVInt64_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i64( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[INDICES:%.*]]) @@ -421,7 +421,7 @@ void test_svstnt1_scatter_u64index_s64(svbool_t pg, int64_t *base, svuint64_t in // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i64( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z33test_svstnt1_scatter_u64index_u64u10__SVBool_tPmu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z33test_svstnt1_scatter_u64index_u64u10__SVBool_tPmu12__SVUint64_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i64( [[DATA:%.*]], [[TMP0]], ptr [[BASE:%.*]], [[INDICES:%.*]]) @@ -490,7 +490,7 @@ void test_svstnt1_scatter_u64base_index_s64(svbool_t pg, svuint64_t bases, int64 // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i32.nxv4i32( [[DATA:%.*]], [[TMP0]], [[BASES:%.*]], i64 [[TMP1]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z38test_svstnt1_scatter_u32base_index_u32u10__SVBool_tu12__SVUint32_tlu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z38test_svstnt1_scatter_u32base_index_u32u10__SVBool_tu12__SVUint32_tlS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[INDEX:%.*]], 2 @@ -508,7 +508,7 @@ void test_svstnt1_scatter_u32base_index_u32(svbool_t pg, svuint32_t bases, int64 // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i64.nxv2i64( [[DATA:%.*]], [[TMP0]], [[BASES:%.*]], i64 [[TMP1]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z38test_svstnt1_scatter_u64base_index_u64u10__SVBool_tu12__SVUint64_tlu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z38test_svstnt1_scatter_u64base_index_u64u10__SVBool_tu12__SVUint64_tlS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[INDEX:%.*]], 3 diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1b.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1b.c index d9e0d79b23c04..3694b85bd6c89 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1b.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1b.c @@ -58,7 +58,7 @@ void test_svstnt1b_scatter_u64base_s64(svbool_t pg, svuint64_t bases, svint64_t // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i8.nxv4i32( [[TMP0]], [[TMP1]], [[BASES:%.*]], i64 0) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z33test_svstnt1b_scatter_u32base_u32u10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z33test_svstnt1b_scatter_u32base_u32u10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) @@ -76,7 +76,7 @@ void test_svstnt1b_scatter_u32base_u32(svbool_t pg, svuint32_t bases, svuint32_t // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i8.nxv2i64( [[TMP0]], [[TMP1]], [[BASES:%.*]], i64 0) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z33test_svstnt1b_scatter_u64base_u64u10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z33test_svstnt1b_scatter_u64base_u64u10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) @@ -94,7 +94,7 @@ void test_svstnt1b_scatter_u64base_u64(svbool_t pg, svuint64_t bases, svuint64_t // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.nxv2i8( [[TMP0]], [[TMP1]], ptr [[BASE:%.*]], [[OFFSETS:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z35test_svstnt1b_scatter_s64offset_s64u10__SVBool_tPau11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z35test_svstnt1b_scatter_s64offset_s64u10__SVBool_tPau11__SVInt64_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) @@ -166,7 +166,7 @@ void test_svstnt1b_scatter_u64offset_s64(svbool_t pg, int8_t *base, svuint64_t o // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4i8( [[TMP0]], [[TMP1]], ptr [[BASE:%.*]], [[OFFSETS:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z35test_svstnt1b_scatter_u32offset_u32u10__SVBool_tPhu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z35test_svstnt1b_scatter_u32offset_u32u10__SVBool_tPhu12__SVUint32_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) @@ -184,7 +184,7 @@ void test_svstnt1b_scatter_u32offset_u32(svbool_t pg, uint8_t *base, svuint32_t // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.nxv2i8( [[TMP0]], [[TMP1]], ptr [[BASE:%.*]], [[OFFSETS:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z35test_svstnt1b_scatter_u64offset_u64u10__SVBool_tPhu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z35test_svstnt1b_scatter_u64offset_u64u10__SVBool_tPhu12__SVUint64_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) @@ -238,7 +238,7 @@ void test_svstnt1b_scatter_u64base_offset_s64(svbool_t pg, svuint64_t bases, int // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i8.nxv4i32( [[TMP0]], [[TMP1]], [[BASES:%.*]], i64 [[OFFSET:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z40test_svstnt1b_scatter_u32base_offset_u32u10__SVBool_tu12__SVUint32_tlu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z40test_svstnt1b_scatter_u32base_offset_u32u10__SVBool_tu12__SVUint32_tlS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) @@ -256,7 +256,7 @@ void test_svstnt1b_scatter_u32base_offset_u32(svbool_t pg, svuint32_t bases, int // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i8.nxv2i64( [[TMP0]], [[TMP1]], [[BASES:%.*]], i64 [[OFFSET:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z40test_svstnt1b_scatter_u64base_offset_u64u10__SVBool_tu12__SVUint64_tlu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z40test_svstnt1b_scatter_u64base_offset_u64u10__SVBool_tu12__SVUint64_tlS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1h.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1h.c index 825b699bd722f..aee960d6dd743 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1h.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1h.c @@ -58,7 +58,7 @@ void test_svstnt1h_scatter_u64base_s64(svbool_t pg, svuint64_t bases, svint64_t // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i16.nxv4i32( [[TMP0]], [[TMP1]], [[BASES:%.*]], i64 0) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z33test_svstnt1h_scatter_u32base_u32u10__SVBool_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z33test_svstnt1h_scatter_u32base_u32u10__SVBool_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) @@ -76,7 +76,7 @@ void test_svstnt1h_scatter_u32base_u32(svbool_t pg, svuint32_t bases, svuint32_t // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i16.nxv2i64( [[TMP0]], [[TMP1]], [[BASES:%.*]], i64 0) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z33test_svstnt1h_scatter_u64base_u64u10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z33test_svstnt1h_scatter_u64base_u64u10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) @@ -94,7 +94,7 @@ void test_svstnt1h_scatter_u64base_u64(svbool_t pg, svuint64_t bases, svuint64_t // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.nxv2i16( [[TMP0]], [[TMP1]], ptr [[BASE:%.*]], [[OFFSETS:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z35test_svstnt1h_scatter_s64offset_s64u10__SVBool_tPsu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z35test_svstnt1h_scatter_s64offset_s64u10__SVBool_tPsu11__SVInt64_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) @@ -166,7 +166,7 @@ void test_svstnt1h_scatter_u64offset_s64(svbool_t pg, int16_t *base, svuint64_t // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4i16( [[TMP0]], [[TMP1]], ptr [[BASE:%.*]], [[OFFSETS:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z35test_svstnt1h_scatter_u32offset_u32u10__SVBool_tPtu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z35test_svstnt1h_scatter_u32offset_u32u10__SVBool_tPtu12__SVUint32_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) @@ -184,7 +184,7 @@ void test_svstnt1h_scatter_u32offset_u32(svbool_t pg, uint16_t *base, svuint32_t // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.nxv2i16( [[TMP0]], [[TMP1]], ptr [[BASE:%.*]], [[OFFSETS:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z35test_svstnt1h_scatter_u64offset_u64u10__SVBool_tPtu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z35test_svstnt1h_scatter_u64offset_u64u10__SVBool_tPtu12__SVUint64_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) @@ -238,7 +238,7 @@ void test_svstnt1h_scatter_u64base_offset_s64(svbool_t pg, svuint64_t bases, int // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i16.nxv4i32( [[TMP0]], [[TMP1]], [[BASES:%.*]], i64 [[OFFSET:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z40test_svstnt1h_scatter_u32base_offset_u32u10__SVBool_tu12__SVUint32_tlu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z40test_svstnt1h_scatter_u32base_offset_u32u10__SVBool_tu12__SVUint32_tlS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) @@ -256,7 +256,7 @@ void test_svstnt1h_scatter_u32base_offset_u32(svbool_t pg, svuint32_t bases, int // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i16.nxv2i64( [[TMP0]], [[TMP1]], [[BASES:%.*]], i64 [[OFFSET:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z40test_svstnt1h_scatter_u64base_offset_u64u10__SVBool_tu12__SVUint64_tlu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z40test_svstnt1h_scatter_u64base_offset_u64u10__SVBool_tu12__SVUint64_tlS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) @@ -274,7 +274,7 @@ void test_svstnt1h_scatter_u64base_offset_u64(svbool_t pg, svuint64_t bases, int // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i16( [[TMP0]], [[TMP1]], ptr [[BASE:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z34test_svstnt1h_scatter_s64index_s64u10__SVBool_tPsu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z34test_svstnt1h_scatter_s64index_s64u10__SVBool_tPsu11__SVInt64_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) @@ -328,7 +328,7 @@ void test_svstnt1h_scatter_u64index_s64(svbool_t pg, int16_t *base, svuint64_t i // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i16( [[TMP0]], [[TMP1]], ptr [[BASE:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z34test_svstnt1h_scatter_u64index_u64u10__SVBool_tPtu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z34test_svstnt1h_scatter_u64index_u64u10__SVBool_tPtu12__SVUint64_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) @@ -387,7 +387,7 @@ void test_svstnt1h_scatter_u64base_index_s64(svbool_t pg, svuint64_t bases, int6 // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i16.nxv4i32( [[TMP0]], [[TMP1]], [[BASES:%.*]], i64 [[TMP2]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z39test_svstnt1h_scatter_u32base_index_u32u10__SVBool_tu12__SVUint32_tlu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z39test_svstnt1h_scatter_u32base_index_u32u10__SVBool_tu12__SVUint32_tlS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) @@ -407,7 +407,7 @@ void test_svstnt1h_scatter_u32base_index_u32(svbool_t pg, svuint32_t bases, int6 // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i16.nxv2i64( [[TMP0]], [[TMP1]], [[BASES:%.*]], i64 [[TMP2]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z39test_svstnt1h_scatter_u64base_index_u64u10__SVBool_tu12__SVUint64_tlu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z39test_svstnt1h_scatter_u64base_index_u64u10__SVBool_tu12__SVUint64_tlS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1w.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1w.c index 48c434f91b164..c382bead27963 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1w.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1w.c @@ -40,7 +40,7 @@ void test_svstnt1w_scatter_u64base_s64(svbool_t pg, svuint64_t bases, svint64_t // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i32.nxv2i64( [[TMP0]], [[TMP1]], [[BASES:%.*]], i64 0) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z33test_svstnt1w_scatter_u64base_u64u10__SVBool_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z33test_svstnt1w_scatter_u64base_u64u10__SVBool_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) @@ -58,7 +58,7 @@ void test_svstnt1w_scatter_u64base_u64(svbool_t pg, svuint64_t bases, svuint64_t // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.nxv2i32( [[TMP0]], [[TMP1]], ptr [[BASE:%.*]], [[OFFSETS:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z35test_svstnt1w_scatter_s64offset_s64u10__SVBool_tPiu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z35test_svstnt1w_scatter_s64offset_s64u10__SVBool_tPiu11__SVInt64_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) @@ -112,7 +112,7 @@ void test_svstnt1w_scatter_u64offset_s64(svbool_t pg, int32_t *base, svuint64_t // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.nxv2i32( [[TMP0]], [[TMP1]], ptr [[BASE:%.*]], [[OFFSETS:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z35test_svstnt1w_scatter_u64offset_u64u10__SVBool_tPju12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z35test_svstnt1w_scatter_u64offset_u64u10__SVBool_tPju12__SVUint64_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) @@ -148,7 +148,7 @@ void test_svstnt1w_scatter_u64base_offset_s64(svbool_t pg, svuint64_t bases, int // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i32.nxv2i64( [[TMP0]], [[TMP1]], [[BASES:%.*]], i64 [[OFFSET:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z40test_svstnt1w_scatter_u64base_offset_u64u10__SVBool_tu12__SVUint64_tlu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z40test_svstnt1w_scatter_u64base_offset_u64u10__SVBool_tu12__SVUint64_tlS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) @@ -166,7 +166,7 @@ void test_svstnt1w_scatter_u64base_offset_u64(svbool_t pg, svuint64_t bases, int // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i32( [[TMP0]], [[TMP1]], ptr [[BASE:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z34test_svstnt1w_scatter_s64index_s64u10__SVBool_tPiu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z34test_svstnt1w_scatter_s64index_s64u10__SVBool_tPiu11__SVInt64_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) @@ -220,7 +220,7 @@ void test_svstnt1w_scatter_u64index_s64(svbool_t pg, int32_t *base, svuint64_t i // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i32( [[TMP0]], [[TMP1]], ptr [[BASE:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z34test_svstnt1w_scatter_u64index_u64u10__SVBool_tPju12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z34test_svstnt1w_scatter_u64index_u64u10__SVBool_tPju12__SVUint64_tS1_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) @@ -259,7 +259,7 @@ void test_svstnt1w_scatter_u64base_index_s64(svbool_t pg, svuint64_t bases, int6 // CHECK-NEXT: tail call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i32.nxv2i64( [[TMP0]], [[TMP1]], [[BASES:%.*]], i64 [[TMP2]]) // CHECK-NEXT: ret void // -// CPP-CHECK-LABEL: @_Z39test_svstnt1w_scatter_u64base_index_u64u10__SVBool_tu12__SVUint64_tlu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z39test_svstnt1w_scatter_u64base_index_u64u10__SVBool_tu12__SVUint64_tlS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = trunc [[DATA:%.*]] to // CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_subhnb.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_subhnb.c index df51c2de90817..b73468ddd264e 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_subhnb.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_subhnb.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subhnb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svsubhnb_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svsubhnb_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subhnb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svsubhnb_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subhnb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svsubhnb_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svsubhnb_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subhnb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_svsubhnb_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subhnb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svsubhnb_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svsubhnb_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subhnb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_svsubhnb_s64(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subhnb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svsubhnb_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svsubhnb_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subhnb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svuint8_t test_svsubhnb_u16(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subhnb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svsubhnb_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svsubhnb_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subhnb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint16_t test_svsubhnb_u32(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subhnb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svsubhnb_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svsubhnb_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subhnb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_subhnt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_subhnt.c index 35e2634795763..674607350c9ff 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_subhnt.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_subhnt.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subhnt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svsubhnt_s16u10__SVInt8_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svsubhnt_s16u10__SVInt8_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subhnt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svsubhnt_s16(svint8_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subhnt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svsubhnt_s32u11__SVInt16_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svsubhnt_s32u11__SVInt16_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subhnt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_svsubhnt_s32(svint16_t op1, svint32_t op2, svint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subhnt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svsubhnt_s64u11__SVInt32_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z17test_svsubhnt_s64u11__SVInt32_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subhnt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_svsubhnt_s64(svint32_t op1, svint64_t op2, svint64_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subhnt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svsubhnt_u16u11__SVUint8_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svsubhnt_u16u11__SVUint8_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subhnt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svuint8_t test_svsubhnt_u16(svuint8_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subhnt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svsubhnt_u32u12__SVUint16_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z17test_svsubhnt_u32u12__SVUint16_tu12__SVUint32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subhnt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint16_t test_svsubhnt_u32(svuint16_t op1, svuint32_t op2, svuint32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subhnt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svsubhnt_u64u12__SVUint32_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z17test_svsubhnt_u64u12__SVUint32_tu12__SVUint64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.subhnt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sublb.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sublb.c index 2e881891c27d0..ce365e4949f15 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sublb.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sublb.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssublb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsublb_s16u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svsublb_s16u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssublb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svsublb_s16(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssublb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsublb_s32u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svsublb_s32u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssublb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svsublb_s32(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssublb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsublb_s64u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svsublb_s64u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssublb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint64_t test_svsublb_s64(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usublb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsublb_u16u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svsublb_u16u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usublb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svuint16_t test_svsublb_u16(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usublb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsublb_u32u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svsublb_u32u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usublb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint32_t test_svsublb_u32(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usublb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsublb_u64u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svsublb_u64u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usublb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sublbt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sublbt.c index 541fc7aa4e469..c2a01a028eba5 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sublbt.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sublbt.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssublbt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svsublbt_s16u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svsublbt_s16u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssublbt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svsublbt_s16(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssublbt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svsublbt_s32u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svsublbt_s32u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssublbt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svsublbt_s32(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssublbt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svsublbt_s64u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svsublbt_s64u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssublbt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sublt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sublt.c index 6deb20e82e7bb..deaad5ea88383 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sublt.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sublt.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssublt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsublt_s16u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z16test_svsublt_s16u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssublt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svsublt_s16(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssublt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsublt_s32u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svsublt_s32u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssublt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svsublt_s32(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssublt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsublt_s64u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svsublt_s64u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssublt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint64_t test_svsublt_s64(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usublt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsublt_u16u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z16test_svsublt_u16u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usublt.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svuint16_t test_svsublt_u16(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usublt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsublt_u32u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svsublt_u32u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usublt.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint32_t test_svsublt_u32(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usublt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svsublt_u64u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svsublt_u64u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.usublt.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_subltb.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_subltb.c index 36235aeb65618..811a27deb4649 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_subltb.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_subltb.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssubltb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svsubltb_s16u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svsubltb_s16u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssubltb.nxv8i16( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint16_t test_svsubltb_s16(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssubltb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svsubltb_s32u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svsubltb_s32u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssubltb.nxv4i32( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint32_t test_svsubltb_s32(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssubltb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svsubltb_s64u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z17test_svsubltb_s64u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ssubltb.nxv2i64( [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_tbx-bfloat.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_tbx-bfloat.c index 35e5142f80e21..0cd0c76c55085 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_tbx-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_tbx-bfloat.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbx.nxv8bf16( [[FALLBACK:%.*]], [[DATA:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svtbx_bf16u14__SVBFloat16_tu14__SVBFloat16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z15test_svtbx_bf16u14__SVBfloat16_tS_u12__SVUint16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbx.nxv8bf16( [[FALLBACK:%.*]], [[DATA:%.*]], [[INDICES:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_tbx.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_tbx.c index bce9e133e1c21..e2ae7bac0a3e2 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_tbx.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_tbx.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbx.nxv16i8( [[FALLBACK:%.*]], [[DATA:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z13test_svtbx_s8u10__SVInt8_tu10__SVInt8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z13test_svtbx_s8u10__SVInt8_tS_u11__SVUint8_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbx.nxv16i8( [[FALLBACK:%.*]], [[DATA:%.*]], [[INDICES:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svtbx_s8(svint8_t fallback, svint8_t data, svuint8_t indices) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbx.nxv8i16( [[FALLBACK:%.*]], [[DATA:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svtbx_s16u11__SVInt16_tu11__SVInt16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z14test_svtbx_s16u11__SVInt16_tS_u12__SVUint16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbx.nxv8i16( [[FALLBACK:%.*]], [[DATA:%.*]], [[INDICES:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint16_t test_svtbx_s16(svint16_t fallback, svint16_t data, svuint16_t indices) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbx.nxv4i32( [[FALLBACK:%.*]], [[DATA:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svtbx_s32u11__SVInt32_tu11__SVInt32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z14test_svtbx_s32u11__SVInt32_tS_u12__SVUint32_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbx.nxv4i32( [[FALLBACK:%.*]], [[DATA:%.*]], [[INDICES:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint32_t test_svtbx_s32(svint32_t fallback, svint32_t data, svuint32_t indices) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbx.nxv2i64( [[FALLBACK:%.*]], [[DATA:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svtbx_s64u11__SVInt64_tu11__SVInt64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z14test_svtbx_s64u11__SVInt64_tS_u12__SVUint64_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbx.nxv2i64( [[FALLBACK:%.*]], [[DATA:%.*]], [[INDICES:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svint64_t test_svtbx_s64(svint64_t fallback, svint64_t data, svuint64_t indices) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbx.nxv16i8( [[FALLBACK:%.*]], [[DATA:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z13test_svtbx_u8u11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z13test_svtbx_u8u11__SVUint8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbx.nxv16i8( [[FALLBACK:%.*]], [[DATA:%.*]], [[INDICES:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svuint8_t test_svtbx_u8(svuint8_t fallback, svuint8_t data, svuint8_t indices) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbx.nxv8i16( [[FALLBACK:%.*]], [[DATA:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svtbx_u16u12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z14test_svtbx_u16u12__SVUint16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbx.nxv8i16( [[FALLBACK:%.*]], [[DATA:%.*]], [[INDICES:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -110,7 +110,7 @@ svuint16_t test_svtbx_u16(svuint16_t fallback, svuint16_t data, svuint16_t indic // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbx.nxv4i32( [[FALLBACK:%.*]], [[DATA:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svtbx_u32u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z14test_svtbx_u32u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbx.nxv4i32( [[FALLBACK:%.*]], [[DATA:%.*]], [[INDICES:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -125,7 +125,7 @@ svuint32_t test_svtbx_u32(svuint32_t fallback, svuint32_t data, svuint32_t indic // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbx.nxv2i64( [[FALLBACK:%.*]], [[DATA:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svtbx_u64u12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z14test_svtbx_u64u12__SVUint64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbx.nxv2i64( [[FALLBACK:%.*]], [[DATA:%.*]], [[INDICES:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -140,7 +140,7 @@ svuint64_t test_svtbx_u64(svuint64_t fallback, svuint64_t data, svuint64_t indic // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbx.nxv8f16( [[FALLBACK:%.*]], [[DATA:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svtbx_f16u13__SVFloat16_tu13__SVFloat16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z14test_svtbx_f16u13__SVFloat16_tS_u12__SVUint16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbx.nxv8f16( [[FALLBACK:%.*]], [[DATA:%.*]], [[INDICES:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -155,7 +155,7 @@ svfloat16_t test_svtbx_f16(svfloat16_t fallback, svfloat16_t data, svuint16_t in // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbx.nxv4f32( [[FALLBACK:%.*]], [[DATA:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svtbx_f32u13__SVFloat32_tu13__SVFloat32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z14test_svtbx_f32u13__SVFloat32_tS_u12__SVUint32_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbx.nxv4f32( [[FALLBACK:%.*]], [[DATA:%.*]], [[INDICES:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -170,7 +170,7 @@ svfloat32_t test_svtbx_f32(svfloat32_t fallback, svfloat32_t data, svuint32_t in // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbx.nxv2f64( [[FALLBACK:%.*]], [[DATA:%.*]], [[INDICES:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z14test_svtbx_f64u13__SVFloat64_tu13__SVFloat64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z14test_svtbx_f64u13__SVFloat64_tS_u12__SVUint64_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.tbx.nxv2f64( [[FALLBACK:%.*]], [[DATA:%.*]], [[INDICES:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_xar.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_xar.c index b8d5414cc39bf..0f4cf88f6f135 100644 --- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_xar.c +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_xar.c @@ -20,7 +20,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svxar_n_s8u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svxar_n_s8u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -35,7 +35,7 @@ svint8_t test_svxar_n_s8(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 8) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svxar_n_s8_1u10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z17test_svxar_n_s8_1u10__SVInt8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 8) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -50,7 +50,7 @@ svint8_t test_svxar_n_s8_1(svint8_t op1, svint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svxar_n_s16u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svxar_n_s16u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -65,7 +65,7 @@ svint16_t test_svxar_n_s16(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 16) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svxar_n_s16_1u11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z18test_svxar_n_s16_1u11__SVInt16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 16) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -80,7 +80,7 @@ svint16_t test_svxar_n_s16_1(svint16_t op1, svint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svxar_n_s32u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svxar_n_s32u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -95,7 +95,7 @@ svint32_t test_svxar_n_s32(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 32) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svxar_n_s32_1u11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z18test_svxar_n_s32_1u11__SVInt32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 32) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -110,7 +110,7 @@ svint32_t test_svxar_n_s32_1(svint32_t op1, svint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svxar_n_s64u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svxar_n_s64u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -125,7 +125,7 @@ svint64_t test_svxar_n_s64(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 64) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svxar_n_s64_1u11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z18test_svxar_n_s64_1u11__SVInt64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 64) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -140,7 +140,7 @@ svint64_t test_svxar_n_s64_1(svint64_t op1, svint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svxar_n_u8u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svxar_n_u8u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -155,7 +155,7 @@ svuint8_t test_svxar_n_u8(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 8) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svxar_n_u8_1u11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z17test_svxar_n_u8_1u11__SVUint8_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], i32 8) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -170,7 +170,7 @@ svuint8_t test_svxar_n_u8_1(svuint8_t op1, svuint8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svxar_n_u16u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svxar_n_u16u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -185,7 +185,7 @@ svuint16_t test_svxar_n_u16(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 16) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svxar_n_u16_1u12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z18test_svxar_n_u16_1u12__SVUint16_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], i32 16) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -200,7 +200,7 @@ svuint16_t test_svxar_n_u16_1(svuint16_t op1, svuint16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svxar_n_u32u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svxar_n_u32u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -215,7 +215,7 @@ svuint32_t test_svxar_n_u32(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 32) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svxar_n_u32_1u12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z18test_svxar_n_u32_1u12__SVUint32_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], i32 32) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -230,7 +230,7 @@ svuint32_t test_svxar_n_u32_1(svuint32_t op1, svuint32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svxar_n_u64u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svxar_n_u64u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 1) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -245,7 +245,7 @@ svuint64_t test_svxar_n_u64(svuint64_t op1, svuint64_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 64) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z18test_svxar_n_u64_1u12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z18test_svxar_n_u64_1u12__SVUint64_tS_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.xar.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], i32 64) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmlsl.c b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmlsl.c index 2955d4554da00..f3e4c3334cfa8 100644 --- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmlsl.c +++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmlsl.c @@ -24,7 +24,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfmlslb( [[ZDA:%.*]], [[ZN:%.*]], [[ZM:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z12test_bfmlslbu13__SVFloat32_tu14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z12test_bfmlslbu13__SVFloat32_tu14__SVBfloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfmlslb( [[ZDA:%.*]], [[ZN:%.*]], [[ZM:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -40,7 +40,7 @@ svfloat32_t test_bfmlslb(svfloat32_t zda, svbfloat16_t zn, svbfloat16_t zm) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfmlslb.lane( [[ZDA:%.*]], [[ZN:%.*]], [[ZM:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_bfmlslb_laneu13__SVFloat32_tu14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_bfmlslb_laneu13__SVFloat32_tu14__SVBfloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfmlslb.lane( [[ZDA:%.*]], [[ZN:%.*]], [[ZM:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -58,7 +58,7 @@ svfloat32_t test_bfmlslb_lane(svfloat32_t zda, svbfloat16_t zn, svbfloat16_t zm) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfmlslt( [[ZDA:%.*]], [[ZN:%.*]], [[ZM:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z12test_bfmlsltu13__SVFloat32_tu14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z12test_bfmlsltu13__SVFloat32_tu14__SVBfloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfmlslt( [[ZDA:%.*]], [[ZN:%.*]], [[ZM:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -74,7 +74,7 @@ svfloat32_t test_bfmlslt(svfloat32_t zda, svbfloat16_t zn, svbfloat16_t zm) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfmlslt.lane( [[ZDA:%.*]], [[ZN:%.*]], [[ZM:%.*]], i32 7) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_bfmlslt_laneu13__SVFloat32_tu14__SVBFloat16_tu14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_bfmlslt_laneu13__SVFloat32_tu14__SVBfloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.bfmlslt.lane( [[ZDA:%.*]], [[ZN:%.*]], [[ZM:%.*]], i32 7) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_dot.c b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_dot.c index d50be9ae177d7..8886a6f03841b 100644 --- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_dot.c +++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_dot.c @@ -19,7 +19,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sdot.x2.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svdot_s32_x2u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z17test_svdot_s32_x2u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sdot.x2.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -34,7 +34,7 @@ svint32_t test_svdot_s32_x2(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.udot.x2.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svdot_u32_x2u12__SVUint32_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z17test_svdot_u32_x2u12__SVUint32_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.udot.x2.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -49,7 +49,7 @@ svuint32_t test_svdot_u32_x2(svuint32_t op1, svuint16_t op2, svuint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fdot.x2.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z17test_svdot_f32_x2u13__SVFloat32_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z17test_svdot_f32_x2u13__SVFloat32_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fdot.x2.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -66,7 +66,7 @@ svfloat32_t test_svdot_f32_x2(svfloat32_t op1, svfloat16_t op2, svfloat16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sdot.lane.x2.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z22test_svdot_lane_s32_x2u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z22test_svdot_lane_s32_x2u11__SVInt32_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sdot.lane.x2.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -81,7 +81,7 @@ svint32_t test_svdot_lane_s32_x2(svint32_t op1, svint16_t op2, svint16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.udot.lane.x2.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z22test_svdot_lane_u32_x2u12__SVUint32_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z22test_svdot_lane_u32_x2u12__SVUint32_tu12__SVUint16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.udot.lane.x2.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -96,7 +96,7 @@ svuint32_t test_svdot_lane_u32_x2(svuint32_t op1, svuint16_t op2, svuint16_t op3 // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fdot.lane.x2.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z22test_svdot_lane_f32_x2u13__SVFloat32_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z22test_svdot_lane_f32_x2u13__SVFloat32_tu13__SVFloat16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fdot.lane.x2.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]], i32 3) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_fclamp.c b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_fclamp.c index e7085c94b255c..d9f0e2af6026b 100644 --- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_fclamp.c +++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_fclamp.c @@ -25,7 +25,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fclamp.nxv8f16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svclamp_f16u13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t( +// CPP-CHECK-LABEL: @_Z16test_svclamp_f16u13__SVFloat16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fclamp.nxv8f16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -39,7 +39,7 @@ svfloat16_t test_svclamp_f16(svfloat16_t op1, svfloat16_t op2, svfloat16_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fclamp.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svclamp_f32u13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t( +// CPP-CHECK-LABEL: @_Z16test_svclamp_f32u13__SVFloat32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fclamp.nxv4f32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -53,7 +53,7 @@ svfloat32_t test_svclamp_f32(svfloat32_t op1, svfloat32_t op2, svfloat32_t op3) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fclamp.nxv2f64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svclamp_f64u13__SVFloat64_tu13__SVFloat64_tu13__SVFloat64_t( +// CPP-CHECK-LABEL: @_Z16test_svclamp_f64u13__SVFloat64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.fclamp.nxv2f64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_psel.c b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_psel.c index 97354d75d7b87..6ada27c6d8da4 100644 --- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_psel.c +++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_psel.c @@ -14,7 +14,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.psel.nxv16i1( [[P1:%.*]], [[P2:%.*]], i32 [[ADD]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z19test_svpsel_lane_b8u10__SVBool_tu10__SVBool_tj( +// CPP-CHECK-LABEL: @_Z19test_svpsel_lane_b8u10__SVBool_tS_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[ADD:%.*]] = add i32 [[IDX:%.*]], 15 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.psel.nxv16i1( [[P1:%.*]], [[P2:%.*]], i32 [[ADD]]) @@ -31,7 +31,7 @@ svbool_t test_svpsel_lane_b8(svbool_t p1, svbool_t p2, uint32_t idx) { // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.psel.nxv8i1( [[P1:%.*]], [[TMP0]], i32 [[ADD]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z20test_svpsel_lane_b16u10__SVBool_tu10__SVBool_tj( +// CPP-CHECK-LABEL: @_Z20test_svpsel_lane_b16u10__SVBool_tS_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[ADD:%.*]] = add i32 [[IDX:%.*]], 7 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[P2:%.*]]) @@ -49,7 +49,7 @@ svbool_t test_svpsel_lane_b16(svbool_t p1, svbool_t p2, uint32_t idx) { // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.psel.nxv4i1( [[P1:%.*]], [[TMP0]], i32 [[ADD]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z20test_svpsel_lane_b32u10__SVBool_tu10__SVBool_tj( +// CPP-CHECK-LABEL: @_Z20test_svpsel_lane_b32u10__SVBool_tS_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[ADD:%.*]] = add i32 [[IDX:%.*]], 3 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[P2:%.*]]) @@ -67,7 +67,7 @@ svbool_t test_svpsel_lane_b32(svbool_t p1, svbool_t p2, uint32_t idx) { // CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.psel.nxv2i1( [[P1:%.*]], [[TMP0]], i32 [[ADD]]) // CHECK-NEXT: ret [[TMP1]] // -// CPP-CHECK-LABEL: @_Z20test_svpsel_lane_b64u10__SVBool_tu10__SVBool_tj( +// CPP-CHECK-LABEL: @_Z20test_svpsel_lane_b64u10__SVBool_tS_j( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[ADD:%.*]] = add i32 [[IDX:%.*]], 1 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[P2:%.*]]) diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_sclamp.c b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_sclamp.c index 31615ca542186..bbbbda9e6edfd 100644 --- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_sclamp.c +++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_sclamp.c @@ -25,7 +25,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sclamp.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svclamp_s8u10__SVInt8_tu10__SVInt8_tu10__SVInt8_t( +// CPP-CHECK-LABEL: @_Z15test_svclamp_s8u10__SVInt8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sclamp.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -39,7 +39,7 @@ svint8_t test_svclamp_s8(svint8_t op1, svint8_t op2, svint8_t op3) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sclamp.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svclamp_s16u11__SVInt16_tu11__SVInt16_tu11__SVInt16_t( +// CPP-CHECK-LABEL: @_Z16test_svclamp_s16u11__SVInt16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sclamp.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -53,7 +53,7 @@ svint16_t test_svclamp_s16(svint16_t op1, svint16_t op2, svint16_t op3) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sclamp.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svclamp_s32u11__SVInt32_tu11__SVInt32_tu11__SVInt32_t( +// CPP-CHECK-LABEL: @_Z16test_svclamp_s32u11__SVInt32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sclamp.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -67,7 +67,7 @@ svint32_t test_svclamp_s32(svint32_t op1, svint32_t op2, svint32_t op3) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sclamp.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svclamp_s64u11__SVInt64_tu11__SVInt64_tu11__SVInt64_t( +// CPP-CHECK-LABEL: @_Z16test_svclamp_s64u11__SVInt64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sclamp.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_uclamp.c b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_uclamp.c index 8d2f68fbd42f4..6af4d8b43afd6 100644 --- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_uclamp.c +++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_uclamp.c @@ -25,7 +25,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uclamp.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z15test_svclamp_u8u11__SVUint8_tu11__SVUint8_tu11__SVUint8_t( +// CPP-CHECK-LABEL: @_Z15test_svclamp_u8u11__SVUint8_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uclamp.nxv16i8( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -39,7 +39,7 @@ svuint8_t test_svclamp_u8(svuint8_t op1, svuint8_t op2, svuint8_t op3) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uclamp.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svclamp_u16u12__SVUint16_tu12__SVUint16_tu12__SVUint16_t( +// CPP-CHECK-LABEL: @_Z16test_svclamp_u16u12__SVUint16_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uclamp.nxv8i16( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -53,7 +53,7 @@ svuint16_t test_svclamp_u16(svuint16_t op1, svuint16_t op2, svuint16_t op3) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uclamp.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svclamp_u32u12__SVUint32_tu12__SVUint32_tu12__SVUint32_t( +// CPP-CHECK-LABEL: @_Z16test_svclamp_u32u12__SVUint32_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uclamp.nxv4i32( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] @@ -67,7 +67,7 @@ svuint32_t test_svclamp_u32(svuint32_t op1, svuint32_t op2, svuint32_t op3) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uclamp.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z16test_svclamp_u64u12__SVUint64_tu12__SVUint64_tu12__SVUint64_t( +// CPP-CHECK-LABEL: @_Z16test_svclamp_u64u12__SVUint64_tS_S_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uclamp.nxv2i64( [[OP1:%.*]], [[OP2:%.*]], [[OP3:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_get_neonq.c b/clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_get_neonq.c index 89460ab6187eb..038b1c14e6141 100644 --- a/clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_get_neonq.c +++ b/clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_get_neonq.c @@ -174,7 +174,7 @@ float64x2_t test_svget_neonq_f64(svfloat64_t n) { // CHECK-NEXT: [[TMP0:%.*]] = tail call <8 x bfloat> @llvm.vector.extract.v8bf16.nxv8bf16( [[N:%.*]], i64 0) // CHECK-NEXT: ret <8 x bfloat> [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svget_neonq_bf16u14__SVBFloat16_t( +// CPP-CHECK-LABEL: @_Z21test_svget_neonq_bf16u14__SVBfloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <8 x bfloat> @llvm.vector.extract.v8bf16.nxv8bf16( [[N:%.*]], i64 0) // CPP-CHECK-NEXT: ret <8 x bfloat> [[TMP0]] diff --git a/clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_set_neonq.c b/clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_set_neonq.c index dff25650a7394..a1585e231c32c 100644 --- a/clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_set_neonq.c +++ b/clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_set_neonq.c @@ -173,7 +173,7 @@ svfloat64_t test_svset_neonq_f64(svfloat64_t s, float64x2_t n) { // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv8bf16.v8bf16( [[S:%.*]], <8 x bfloat> [[N:%.*]], i64 0) // CHECK-NEXT: ret [[TMP0]] // -// CPP-CHECK-LABEL: @_Z21test_svset_neonq_bf16u14__SVBFloat16_t14__Bfloat16x8_t( +// CPP-CHECK-LABEL: @_Z21test_svset_neonq_bf16u14__SVBfloat16_t14__Bfloat16x8_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv8bf16.v8bf16( [[S:%.*]], <8 x bfloat> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: ret [[TMP0]] diff --git a/clang/test/CodeGen/attr-riscv-rvv-vector-bits-cast.c b/clang/test/CodeGen/attr-riscv-rvv-vector-bits-cast.c index b324d0a2b3cbd..93e9a4eee96eb 100644 --- a/clang/test/CodeGen/attr-riscv-rvv-vector-bits-cast.c +++ b/clang/test/CodeGen/attr-riscv-rvv-vector-bits-cast.c @@ -55,23 +55,11 @@ fixed_float64m1_t from_vfloat64m1_t(vfloat64m1_t type) { return type; } -// CHECK-LABEL: @lax_cast( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[SAVED_VALUE:%.*]] = alloca <8 x i32>, align 32 -// CHECK-NEXT: [[TYPE:%.*]] = tail call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( [[TYPE_COERCE:%.*]], i64 0) -// CHECK-NEXT: store <8 x i32> [[TYPE]], ptr [[SAVED_VALUE]], align 32, !tbaa [[TBAA4:![0-9]+]] -// CHECK-NEXT: [[TMP0:%.*]] = load , ptr [[SAVED_VALUE]], align 32, !tbaa [[TBAA4]] -// CHECK-NEXT: ret [[TMP0]] -// -vint64m1_t lax_cast(fixed_int32m1_t type) { - return type; -} - // CHECK-LABEL: @to_vint32m1_t__from_gnu_int32m1_t( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TYPE:%.*]] = load <8 x i32>, ptr [[TMP0:%.*]], align 32, !tbaa [[TBAA4]] -// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = tail call @llvm.vector.insert.nxv2i32.v8i32( undef, <8 x i32> [[TYPE]], i64 0) -// CHECK-NEXT: ret [[CASTSCALABLESVE]] +// CHECK-NEXT: [[TYPE:%.*]] = load <8 x i32>, ptr [[TMP0:%.*]], align 32, !tbaa [[TBAA4:![0-9]+]] +// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = tail call @llvm.vector.insert.nxv2i32.v8i32( undef, <8 x i32> [[TYPE]], i64 0) +// CHECK-NEXT: ret [[CAST_SCALABLE]] // vint32m1_t to_vint32m1_t__from_gnu_int32m1_t(gnu_int32m1_t type) { return type; @@ -79,8 +67,8 @@ vint32m1_t to_vint32m1_t__from_gnu_int32m1_t(gnu_int32m1_t type) { // CHECK-LABEL: @from_vint32m1_t__to_gnu_int32m1_t( // CHECK-NEXT: entry: -// CHECK-NEXT: [[CASTFIXEDSVE:%.*]] = tail call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( [[TYPE:%.*]], i64 0) -// CHECK-NEXT: store <8 x i32> [[CASTFIXEDSVE]], ptr [[AGG_RESULT:%.*]], align 32, !tbaa [[TBAA4]] +// CHECK-NEXT: [[CAST_FIXED:%.*]] = tail call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( [[TYPE:%.*]], i64 0) +// CHECK-NEXT: store <8 x i32> [[CAST_FIXED]], ptr [[AGG_RESULT:%.*]], align 32, !tbaa [[TBAA4]] // CHECK-NEXT: ret void // gnu_int32m1_t from_vint32m1_t__to_gnu_int32m1_t(vint32m1_t type) { @@ -90,8 +78,8 @@ gnu_int32m1_t from_vint32m1_t__to_gnu_int32m1_t(vint32m1_t type) { // CHECK-LABEL: @to_fixed_int32m1_t__from_gnu_int32m1_t( // CHECK-NEXT: entry: // CHECK-NEXT: [[TYPE:%.*]] = load <8 x i32>, ptr [[TMP0:%.*]], align 32, !tbaa [[TBAA4]] -// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = tail call @llvm.vector.insert.nxv2i32.v8i32( undef, <8 x i32> [[TYPE]], i64 0) -// CHECK-NEXT: ret [[CASTSCALABLESVE]] +// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = tail call @llvm.vector.insert.nxv2i32.v8i32( undef, <8 x i32> [[TYPE]], i64 0) +// CHECK-NEXT: ret [[CAST_SCALABLE]] // fixed_int32m1_t to_fixed_int32m1_t__from_gnu_int32m1_t(gnu_int32m1_t type) { return type; diff --git a/clang/test/CodeGen/const-init.c b/clang/test/CodeGen/const-init.c index 7062393c45022..0e4fc4ad48af8 100644 --- a/clang/test/CodeGen/const-init.c +++ b/clang/test/CodeGen/const-init.c @@ -140,11 +140,12 @@ void g28(void) { typedef short v12i16 __attribute((vector_size(24))); typedef long double v2f80 __attribute((vector_size(24))); // CHECK: @g28.a = internal global <1 x i64> - // CHECK: @g28.b = internal global <12 x i16> - // CHECK: @g28.c = internal global <2 x x86_fp80> , align 32 + // @g28.b = internal global <12 x i16> + // @g28.c = internal global <2 x x86_fp80> , align 32 static v1i64 a = (v1i64)10LL; - static v12i16 b = (v12i16)(v2f80){1,2}; - static v2f80 c = (v2f80)(v12i16){0,0,0,-32768,16383,0,0,0,0,-32768,16384,0}; + //FIXME: support constant bitcast between vectors of x86_fp80 + //static v12i16 b = (v12i16)(v2f80){1,2}; + //static v2f80 c = (v2f80)(v12i16){0,0,0,-32768,16383,0,0,0,0,-32768,16384,0}; } // PR13643 diff --git a/clang/test/CodeGen/debug-info-preferred-type.cpp b/clang/test/CodeGen/debug-info-preferred-type.cpp new file mode 100644 index 0000000000000..6406657a18e92 --- /dev/null +++ b/clang/test/CodeGen/debug-info-preferred-type.cpp @@ -0,0 +1,9 @@ +// RUN: %clang -target x86_64-linux -g -S -emit-llvm -o - %s | FileCheck %s + +struct A { + enum E : unsigned {}; + [[clang::preferred_type(E)]] unsigned b : 2; +} a; + +// CHECK-DAG: [[ENUM:![0-9]+]] = !DICompositeType(tag: DW_TAG_enumeration_type, name: "E"{{.*}} +// CHECK-DAG: !DIDerivedType(tag: DW_TAG_member, name: "b",{{.*}} baseType: [[ENUM]] diff --git a/clang/test/CodeGen/stack-usage.c b/clang/test/CodeGen/stack-usage.c index f7dc486c50058..c9f495605fefd 100644 --- a/clang/test/CodeGen/stack-usage.c +++ b/clang/test/CodeGen/stack-usage.c @@ -1,17 +1,20 @@ // REQUIRES: aarch64-registered-target -// RUN: rm -rf %t && mkdir %t && cd %t -// RUN: %clang_cc1 -triple aarch64-unknown -stack-usage-file b.su -emit-obj %s -o b.o -// RUN: FileCheck %s < b.su +// RUN: rm -rf %t && split-file %s %t && cd %t +// RUN: %clang_cc1 -triple aarch64-unknown -I . -stack-usage-file a.su -emit-obj a.c -o a.o +// RUN: FileCheck %s < a.su -// CHECK: stack-usage.c:[[#@LINE+1]]:foo {{[0-9]+}} static +// CHECK: {{.*}}x.inc:1:bar [[#]] dynamic +// CHECK: a.c:2:foo [[#]] static +//--- a.c +#include "x.inc" int foo() { char a[8]; return 0; } -// CHECK: stack-usage.c:[[#@LINE+1]]:bar {{[0-9]+}} dynamic +//--- x.inc int bar(int len) { char a[len]; diff --git a/clang/test/CodeGen/thread_local.c b/clang/test/CodeGen/thread_local.c new file mode 100644 index 0000000000000..b97f31c2fff2f --- /dev/null +++ b/clang/test/CodeGen/thread_local.c @@ -0,0 +1,27 @@ +// RUN: %clang_cc1 -triple i686-pc-linux-gnu -std=c23 -emit-llvm -o - %s | FileCheck %s + +// Ensure that thread_local and _Thread_local emit the same codegen. See +// https://github.com/llvm/llvm-project/issues/70068 for details. + +void func(void) { + static thread_local int i = 12; + static _Thread_local int j = 13; + + extern thread_local int k; + extern thread_local int l; + + (void)k; + (void)l; +} + +// CHECK: @func.i = internal thread_local global i32 12, align 4 +// CHECK-NEXT: @func.j = internal thread_local global i32 13, align 4 +// CHECK-NEXT: @k = external thread_local global i32, align 4 +// CHECK-NEXT: @l = external thread_local global i32, align 4 + +// CHECK: define dso_local void @func() +// CHECK-NEXT: entry: +// CHECK-NEXT: %[[K:.+]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @k) +// CHECK-NEXT: load i32, ptr %[[K]], align 4 +// CHECK-NEXT: %[[L:.+]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @l) +// CHECK-NEXT: load i32, ptr %[[L]], align 4 diff --git a/clang/test/CodeGenCXX/aarch64-mangle-sve-fixed-vectors.cpp b/clang/test/CodeGenCXX/aarch64-mangle-sve-fixed-vectors.cpp index 1a47eb9b1e345..d0bde80a34057 100644 --- a/clang/test/CodeGenCXX/aarch64-mangle-sve-fixed-vectors.cpp +++ b/clang/test/CodeGenCXX/aarch64-mangle-sve-fixed-vectors.cpp @@ -30,7 +30,7 @@ typedef __SVFloat16_t fixed_float16_t __attribute__((arm_sve_vector_bits(N))); typedef __SVFloat32_t fixed_float32_t __attribute__((arm_sve_vector_bits(N))); typedef __SVFloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N))); -typedef __SVBFloat16_t fixed_bfloat16_t __attribute__((arm_sve_vector_bits(N))); +typedef __SVBfloat16_t fixed_bfloat16_t __attribute__((arm_sve_vector_bits(N))); typedef __SVBool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N))); diff --git a/clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp b/clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp index f387824b56661..75e24c1c90251 100644 --- a/clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp +++ b/clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp @@ -1,114 +1,233 @@ -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu %s -emit-llvm -o - \ -// RUN: | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu %s -emit-llvm -o - \ // RUN: -target-feature +sve,+bf16 | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu %s -emit-llvm -o - \ +// RUN: -target-feature +sve,+bf16 -fclang-abi-compat=17 | FileCheck %s --check-prefix=COMPAT_17 -template struct S {}; +void f(__SVInt8_t, __SVInt8_t); +void f(__SVInt16_t, __SVInt16_t); +void f(__SVInt16_t, __SVInt16_t); +void f(__SVInt32_t, __SVInt32_t); +void f(__SVInt64_t, __SVInt64_t); +void f(__SVUint8_t, __SVUint8_t); +void f(__SVUint16_t, __SVUint16_t); +void f(__SVUint32_t, __SVUint32_t); +void f(__SVUint64_t, __SVUint64_t); +void f(__SVFloat16_t, __SVFloat16_t); +void f(__SVFloat32_t, __SVFloat32_t); +void f(__SVFloat64_t, __SVFloat64_t); +void f(__SVBfloat16_t, __SVBfloat16_t); +void f(__SVBool_t, __SVBool_t); +void f(__SVCount_t, __SVCount_t); -// CHECK: _Z2f11SIu10__SVInt8_tE -void f1(S<__SVInt8_t>) {} -// CHECK: _Z2f21SIu11__SVInt16_tE -void f2(S<__SVInt16_t>) {} -// CHECK: _Z2f31SIu11__SVInt32_tE -void f3(S<__SVInt32_t>) {} -// CHECK: _Z2f41SIu11__SVInt64_tE -void f4(S<__SVInt64_t>) {} -// CHECK: _Z2f51SIu11__SVUint8_tE -void f5(S<__SVUint8_t>) {} -// CHECK: _Z2f61SIu12__SVUint16_tE -void f6(S<__SVUint16_t>) {} -// CHECK: _Z2f71SIu12__SVUint32_tE -void f7(S<__SVUint32_t>) {} -// CHECK: _Z2f81SIu12__SVUint64_tE -void f8(S<__SVUint64_t>) {} -// CHECK: _Z2f91SIu13__SVFloat16_tE -void f9(S<__SVFloat16_t>) {} -// CHECK: _Z3f101SIu13__SVFloat32_tE -void f10(S<__SVFloat32_t>) {} -// CHECK: _Z3f111SIu13__SVFloat64_tE -void f11(S<__SVFloat64_t>) {} -// CHECK: _Z3f121SIu14__SVBFloat16_tE -void f12(S<__SVBFloat16_t>) {} -// CHECK: _Z3f131SIu10__SVBool_tE -void f13(S<__SVBool_t>) {} -// CHECK: _Z3f141SIu11__SVCount_tE -void f14(S<__SVCount_t>) {} +void f(__clang_svint8x2_t, __clang_svint8x2_t); +void f(__clang_svint8x3_t, __clang_svint8x3_t); +void f(__clang_svint8x4_t, __clang_svint8x4_t); +void f(__clang_svint16x2_t, __clang_svint16x2_t); +void f(__clang_svint16x3_t, __clang_svint16x3_t); +void f(__clang_svint16x4_t, __clang_svint16x4_t); +void f(__clang_svint32x2_t, __clang_svint32x2_t); +void f(__clang_svint32x3_t, __clang_svint32x3_t); +void f(__clang_svint32x4_t, __clang_svint32x4_t); +void f(__clang_svint64x2_t, __clang_svint64x2_t); +void f(__clang_svint64x3_t, __clang_svint64x3_t); +void f(__clang_svint64x4_t, __clang_svint64x4_t); +void f(__clang_svuint8x2_t, __clang_svuint8x2_t); +void f(__clang_svuint8x3_t, __clang_svuint8x3_t); +void f(__clang_svuint8x4_t, __clang_svuint8x4_t); +void f(__clang_svuint16x2_t, __clang_svuint16x2_t); +void f(__clang_svuint16x3_t, __clang_svuint16x3_t); +void f(__clang_svuint16x4_t, __clang_svuint16x4_t); +void f(__clang_svuint32x2_t, __clang_svuint32x2_t); +void f(__clang_svuint32x3_t, __clang_svuint32x3_t); +void f(__clang_svuint32x4_t, __clang_svuint32x4_t); +void f(__clang_svuint64x2_t, __clang_svuint64x2_t); +void f(__clang_svuint64x3_t, __clang_svuint64x3_t); +void f(__clang_svuint64x4_t, __clang_svuint64x4_t); +void f(__clang_svfloat16x2_t, __clang_svfloat16x2_t); +void f(__clang_svfloat16x3_t, __clang_svfloat16x3_t); +void f(__clang_svfloat16x4_t, __clang_svfloat16x4_t); +void f(__clang_svfloat32x2_t, __clang_svfloat32x2_t); +void f(__clang_svfloat32x3_t, __clang_svfloat32x3_t); +void f(__clang_svfloat32x4_t, __clang_svfloat32x4_t); +void f(__clang_svfloat64x2_t, __clang_svfloat64x2_t); +void f(__clang_svfloat64x3_t, __clang_svfloat64x3_t); +void f(__clang_svfloat64x4_t, __clang_svfloat64x4_t); +void f(__clang_svbfloat16x2_t, __clang_svbfloat16x2_t); +void f(__clang_svbfloat16x3_t, __clang_svbfloat16x3_t); +void f(__clang_svbfloat16x4_t, __clang_svbfloat16x4_t); +void f(__clang_svboolx2_t, __clang_svboolx2_t); +void f(__clang_svboolx4_t, __clang_svboolx4_t); -// The tuple types don't use the internal name for mangling. +// CHECK-LABEL: define dso_local void @_Z3foov( +// CHECK-SAME: ) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: call void @_Z1fu10__SVInt8_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1fu11__SVInt16_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1fu11__SVInt16_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1fu11__SVInt32_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1fu11__SVInt64_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1fu11__SVUint8_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1fu12__SVUint16_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1fu12__SVUint32_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1fu12__SVUint64_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1fu13__SVFloat16_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1fu13__SVFloat32_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1fu13__SVFloat64_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1fu14__SVBfloat16_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1fu10__SVBool_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1fu11__SVCount_tS_(target("aarch64.svcount") zeroinitializer, target("aarch64.svcount") zeroinitializer) +// CHECK-NEXT: call void @_Z1f10svint8x2_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f10svint8x3_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f10svint8x4_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f11svint16x2_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f11svint16x3_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f11svint16x4_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f11svint32x2_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f11svint32x3_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f11svint32x4_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f11svint64x2_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f11svint64x3_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f11svint64x4_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f11svuint8x2_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f11svuint8x3_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f11svuint8x4_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f12svuint16x2_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f12svuint16x3_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f12svuint16x4_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f12svuint32x2_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f12svuint32x3_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f12svuint32x4_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f12svuint64x2_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f12svuint64x3_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f12svuint64x4_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f13svfloat16x2_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f13svfloat16x3_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f13svfloat16x4_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f13svfloat32x2_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f13svfloat32x3_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f13svfloat32x4_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f13svfloat64x2_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f13svfloat64x3_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f13svfloat64x4_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f14svbfloat16x2_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f14svbfloat16x3_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f14svbfloat16x4_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f10svboolx2_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: call void @_Z1f10svboolx4_tS_( zeroinitializer, zeroinitializer) +// CHECK-NEXT: ret void +// +// COMPAT_17-LABEL: define dso_local void @_Z3foov( +// COMPAT_17-SAME: ) #[[ATTR0:[0-9]+]] { +// COMPAT_17-NEXT: entry: +// COMPAT_17-NEXT: call void @_Z1fu10__SVInt8_tu10__SVInt8_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1fu11__SVInt16_tu11__SVInt16_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1fu11__SVInt16_tu11__SVInt16_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1fu11__SVInt32_tu11__SVInt32_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1fu11__SVInt64_tu11__SVInt64_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1fu11__SVUint8_tu11__SVUint8_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1fu12__SVUint16_tu12__SVUint16_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1fu12__SVUint32_tu12__SVUint32_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1fu12__SVUint64_tu12__SVUint64_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1fu13__SVFloat16_tu13__SVFloat16_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1fu13__SVFloat32_tu13__SVFloat32_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1fu13__SVFloat64_tu13__SVFloat64_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1fu14__SVBFloat16_tu14__SVBFloat16_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1fu10__SVBool_tu10__SVBool_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1fu11__SVCount_tu11__SVCount_t(target("aarch64.svcount") zeroinitializer, target("aarch64.svcount") zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f10svint8x2_t10svint8x2_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f10svint8x3_t10svint8x3_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f10svint8x4_t10svint8x4_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f11svint16x2_t11svint16x2_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f11svint16x3_t11svint16x3_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f11svint16x4_t11svint16x4_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f11svint32x2_t11svint32x2_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f11svint32x3_t11svint32x3_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f11svint32x4_t11svint32x4_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f11svint64x2_t11svint64x2_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f11svint64x3_t11svint64x3_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f11svint64x4_t11svint64x4_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f11svuint8x2_t11svuint8x2_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f11svuint8x3_t11svuint8x3_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f11svuint8x4_t11svuint8x4_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f12svuint16x2_t12svuint16x2_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f12svuint16x3_t12svuint16x3_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f12svuint16x4_t12svuint16x4_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f12svuint32x2_t12svuint32x2_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f12svuint32x3_t12svuint32x3_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f12svuint32x4_t12svuint32x4_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f12svuint64x2_t12svuint64x2_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f12svuint64x3_t12svuint64x3_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f12svuint64x4_t12svuint64x4_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f13svfloat16x2_t13svfloat16x2_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f13svfloat16x3_t13svfloat16x3_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f13svfloat16x4_t13svfloat16x4_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f13svfloat32x2_t13svfloat32x2_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f13svfloat32x3_t13svfloat32x3_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f13svfloat32x4_t13svfloat32x4_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f13svfloat64x2_t13svfloat64x2_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f13svfloat64x3_t13svfloat64x3_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f13svfloat64x4_t13svfloat64x4_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f14svbfloat16x2_t14svbfloat16x2_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f14svbfloat16x3_t14svbfloat16x3_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f14svbfloat16x4_t14svbfloat16x4_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f10svboolx2_t10svboolx2_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: call void @_Z1f10svboolx4_t10svboolx4_t( zeroinitializer, zeroinitializer) +// COMPAT_17-NEXT: ret void +// +void foo() { + f(__SVInt8_t(), __SVInt8_t()); + f(__SVInt16_t(), __SVInt16_t()); + f(__SVInt16_t(), __SVInt16_t()); + f(__SVInt32_t(), __SVInt32_t()); + f(__SVInt64_t(), __SVInt64_t()); + f(__SVUint8_t(), __SVUint8_t()); + f(__SVUint16_t(), __SVUint16_t()); + f(__SVUint32_t(), __SVUint32_t()); + f(__SVUint64_t(), __SVUint64_t()); + f(__SVFloat16_t(), __SVFloat16_t()); + f(__SVFloat32_t(), __SVFloat32_t()); + f(__SVFloat64_t(), __SVFloat64_t()); + f(__SVBfloat16_t(), __SVBfloat16_t()); + f(__SVBool_t(), __SVBool_t()); + f(__SVCount_t(), __SVCount_t()); -// CHECK: _Z3f131SI10svint8x2_tE -void f13(S<__clang_svint8x2_t>) {} -// CHECK: _Z3f141SI10svint8x3_tE -void f14(S<__clang_svint8x3_t>) {} -// CHECK: _Z3f151SI10svint8x4_tE -void f15(S<__clang_svint8x4_t>) {} -// CHECK: _Z3f161SI11svint16x2_tE -void f16(S<__clang_svint16x2_t>) {} -// CHECK: _Z3f171SI11svint16x3_tE -void f17(S<__clang_svint16x3_t>) {} -// CHECK: _Z3f181SI11svint16x4_tE -void f18(S<__clang_svint16x4_t>) {} -// CHECK: _Z3f191SI11svint32x2_tE -void f19(S<__clang_svint32x2_t>) {} -// CHECK: _Z3f201SI11svint32x3_tE -void f20(S<__clang_svint32x3_t>) {} -// CHECK: _Z3f211SI11svint32x4_tE -void f21(S<__clang_svint32x4_t>) {} -// CHECK: _Z3f221SI11svint64x2_tE -void f22(S<__clang_svint64x2_t>) {} -// CHECK: _Z3f231SI11svint64x3_tE -void f23(S<__clang_svint64x3_t>) {} -// CHECK: _Z3f241SI11svint64x4_tE -void f24(S<__clang_svint64x4_t>) {} -// CHECK: _Z3f251SI11svuint8x2_tE -void f25(S<__clang_svuint8x2_t>) {} -// CHECK: _Z3f261SI11svuint8x3_tE -void f26(S<__clang_svuint8x3_t>) {} -// CHECK: _Z3f271SI11svuint8x4_tE -void f27(S<__clang_svuint8x4_t>) {} -// CHECK: _Z3f281SI12svuint16x2_tE -void f28(S<__clang_svuint16x2_t>) {} -// CHECK: _Z3f291SI12svuint16x3_tE -void f29(S<__clang_svuint16x3_t>) {} -// CHECK: _Z3f301SI12svuint16x4_tE -void f30(S<__clang_svuint16x4_t>) {} -// CHECK: _Z3f311SI12svuint32x2_tE -void f31(S<__clang_svuint32x2_t>) {} -// CHECK: _Z3f321SI12svuint32x3_tE -void f32(S<__clang_svuint32x3_t>) {} -// CHECK: _Z3f331SI12svuint32x4_tE -void f33(S<__clang_svuint32x4_t>) {} -// CHECK: _Z3f341SI12svuint64x2_tE -void f34(S<__clang_svuint64x2_t>) {} -// CHECK: _Z3f351SI12svuint64x3_tE -void f35(S<__clang_svuint64x3_t>) {} -// CHECK: _Z3f361SI12svuint64x4_tE -void f36(S<__clang_svuint64x4_t>) {} -// CHECK: _Z3f371SI13svfloat16x2_tE -void f37(S<__clang_svfloat16x2_t>) {} -// CHECK: _Z3f381SI13svfloat16x3_tE -void f38(S<__clang_svfloat16x3_t>) {} -// CHECK: _Z3f391SI13svfloat16x4_tE -void f39(S<__clang_svfloat16x4_t>) {} -// CHECK: _Z3f401SI13svfloat32x2_tE -void f40(S<__clang_svfloat32x2_t>) {} -// CHECK: _Z3f411SI13svfloat32x3_tE -void f41(S<__clang_svfloat32x3_t>) {} -// CHECK: _Z3f421SI13svfloat32x4_tE -void f42(S<__clang_svfloat32x4_t>) {} -// CHECK: _Z3f431SI13svfloat64x2_tE -void f43(S<__clang_svfloat64x2_t>) {} -// CHECK: _Z3f441SI13svfloat64x3_tE -void f44(S<__clang_svfloat64x3_t>) {} -// CHECK: _Z3f451SI13svfloat64x4_tE -void f45(S<__clang_svfloat64x4_t>) {} -// CHECK: _Z3f461SI14svbfloat16x2_tE -void f46(S<__clang_svbfloat16x2_t>) {} -// CHECK: _Z3f471SI14svbfloat16x3_tE -void f47(S<__clang_svbfloat16x3_t>) {} -// CHECK: _Z3f481SI14svbfloat16x4_tE -void f48(S<__clang_svbfloat16x4_t>) {} -// CHECK: _Z3f491SI10svboolx2_tE -void f49(S<__clang_svboolx2_t>) {} -// CHECK: _Z3f501SI10svboolx4_tE -void f50(S<__clang_svboolx4_t>) {} + f(__clang_svint8x2_t(), __clang_svint8x2_t()); + f(__clang_svint8x3_t(), __clang_svint8x3_t()); + f(__clang_svint8x4_t(), __clang_svint8x4_t()); + f(__clang_svint16x2_t(), __clang_svint16x2_t()); + f(__clang_svint16x3_t(), __clang_svint16x3_t()); + f(__clang_svint16x4_t(), __clang_svint16x4_t()); + f(__clang_svint32x2_t(), __clang_svint32x2_t()); + f(__clang_svint32x3_t(), __clang_svint32x3_t()); + f(__clang_svint32x4_t(), __clang_svint32x4_t()); + f(__clang_svint64x2_t(), __clang_svint64x2_t()); + f(__clang_svint64x3_t(), __clang_svint64x3_t()); + f(__clang_svint64x4_t(), __clang_svint64x4_t()); + f(__clang_svuint8x2_t(), __clang_svuint8x2_t()); + f(__clang_svuint8x3_t(), __clang_svuint8x3_t()); + f(__clang_svuint8x4_t(), __clang_svuint8x4_t()); + f(__clang_svuint16x2_t(), __clang_svuint16x2_t()); + f(__clang_svuint16x3_t(), __clang_svuint16x3_t()); + f(__clang_svuint16x4_t(), __clang_svuint16x4_t()); + f(__clang_svuint32x2_t(), __clang_svuint32x2_t()); + f(__clang_svuint32x3_t(), __clang_svuint32x3_t()); + f(__clang_svuint32x4_t(), __clang_svuint32x4_t()); + f(__clang_svuint64x2_t(), __clang_svuint64x2_t()); + f(__clang_svuint64x3_t(), __clang_svuint64x3_t()); + f(__clang_svuint64x4_t(), __clang_svuint64x4_t()); + f(__clang_svfloat16x2_t(), __clang_svfloat16x2_t()); + f(__clang_svfloat16x3_t(), __clang_svfloat16x3_t()); + f(__clang_svfloat16x4_t(), __clang_svfloat16x4_t()); + f(__clang_svfloat32x2_t(), __clang_svfloat32x2_t()); + f(__clang_svfloat32x3_t(), __clang_svfloat32x3_t()); + f(__clang_svfloat32x4_t(), __clang_svfloat32x4_t()); + f(__clang_svfloat64x2_t(), __clang_svfloat64x2_t()); + f(__clang_svfloat64x3_t(), __clang_svfloat64x3_t()); + f(__clang_svfloat64x4_t(), __clang_svfloat64x4_t()); + f(__clang_svbfloat16x2_t(), __clang_svbfloat16x2_t()); + f(__clang_svbfloat16x3_t(), __clang_svbfloat16x3_t()); + f(__clang_svbfloat16x4_t(), __clang_svbfloat16x4_t()); + f(__clang_svboolx2_t(), __clang_svboolx2_t()); + f(__clang_svboolx4_t(), __clang_svboolx4_t()); +} diff --git a/clang/test/CodeGenCXX/aarch64-sve-fixedtypeinfo.cpp b/clang/test/CodeGenCXX/aarch64-sve-fixedtypeinfo.cpp index c2c128ae9f7f1..dcc2c2e0af85d 100644 --- a/clang/test/CodeGenCXX/aarch64-sve-fixedtypeinfo.cpp +++ b/clang/test/CodeGenCXX/aarch64-sve-fixedtypeinfo.cpp @@ -34,7 +34,7 @@ typedef __SVFloat16_t fixed_float16_t __attribute__((arm_sve_vector_bits(N))); typedef __SVFloat32_t fixed_float32_t __attribute__((arm_sve_vector_bits(N))); typedef __SVFloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N))); -typedef __SVBFloat16_t fixed_bfloat16_t __attribute__((arm_sve_vector_bits(N))); +typedef __SVBfloat16_t fixed_bfloat16_t __attribute__((arm_sve_vector_bits(N))); typedef __SVBool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N))); diff --git a/clang/test/CodeGenCXX/aarch64-sve-typeinfo.cpp b/clang/test/CodeGenCXX/aarch64-sve-typeinfo.cpp index 4ee2ed9888438..f414ee0862a1e 100644 --- a/clang/test/CodeGenCXX/aarch64-sve-typeinfo.cpp +++ b/clang/test/CodeGenCXX/aarch64-sve-typeinfo.cpp @@ -19,7 +19,7 @@ auto &f16 = typeid(__SVFloat16_t); auto &f32 = typeid(__SVFloat32_t); auto &f64 = typeid(__SVFloat64_t); -auto &bf16 = typeid(__SVBFloat16_t); +auto &bf16 = typeid(__SVBfloat16_t); auto &b8 = typeid(__SVBool_t); auto &c8 = typeid(__SVCount_t); @@ -57,8 +57,8 @@ auto &c8 = typeid(__SVCount_t); // CHECK-DAG: @_ZTSu13__SVFloat64_t = {{.*}} c"u13__SVFloat64_t\00" // CHECK-DAG: @_ZTIu13__SVFloat64_t = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTSu13__SVFloat64_t // -// CHECK-DAG: @_ZTSu14__SVBFloat16_t = {{.*}} c"u14__SVBFloat16_t\00" -// CHECK-DAG: @_ZTIu14__SVBFloat16_t = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTSu14__SVBFloat16_t +// CHECK-DAG: @_ZTSu14__SVBfloat16_t = {{.*}} c"u14__SVBfloat16_t\00" +// CHECK-DAG: @_ZTIu14__SVBfloat16_t = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTSu14__SVBfloat16_t // CHECK-DAG: @_ZTSu10__SVBool_t = {{.*}} c"u10__SVBool_t\00" // CHECK-DAG: @_ZTIu10__SVBool_t = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTSu10__SVBool_t diff --git a/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp b/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp index cdf389c5e7b52..622d572ce8f36 100644 --- a/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp +++ b/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp @@ -7,7 +7,7 @@ #include -// CHECK-LABEL: @_Z9cond_boolu10__SVBool_tu10__SVBool_t( +// CHECK-LABEL: @_Z9cond_boolu10__SVBool_tS_( // CHECK-NEXT: entry: // CHECK-NEXT: [[CMP:%.*]] = icmp ult [[A:%.*]], [[B:%.*]] // CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne [[CMP]], zeroinitializer @@ -18,7 +18,7 @@ svbool_t cond_bool(svbool_t a, svbool_t b) { return a < b ? a : b; } -// CHECK-LABEL: @_Z7cond_i8u10__SVInt8_tu10__SVInt8_t( +// CHECK-LABEL: @_Z7cond_i8u10__SVInt8_tS_( // CHECK-NEXT: entry: // CHECK-NEXT: [[CMP:%.*]] = icmp ult [[A:%.*]], [[B:%.*]] // CHECK-NEXT: [[CONV:%.*]] = zext [[CMP]] to @@ -30,7 +30,7 @@ svint8_t cond_i8(svint8_t a, svint8_t b) { return a < b ? a : b; } -// CHECK-LABEL: @_Z7cond_u8u11__SVUint8_tu11__SVUint8_t( +// CHECK-LABEL: @_Z7cond_u8u11__SVUint8_tS_( // CHECK-NEXT: entry: // CHECK-NEXT: [[CMP:%.*]] = icmp ult [[A:%.*]], [[B:%.*]] // CHECK-NEXT: [[CONV:%.*]] = zext [[CMP]] to @@ -42,7 +42,7 @@ svuint8_t cond_u8(svuint8_t a, svuint8_t b) { return a < b ? a : b; } -// CHECK-LABEL: @_Z8cond_i16u11__SVInt16_tu11__SVInt16_t( +// CHECK-LABEL: @_Z8cond_i16u11__SVInt16_tS_( // CHECK-NEXT: entry: // CHECK-NEXT: [[CMP:%.*]] = icmp ult [[A:%.*]], [[B:%.*]] // CHECK-NEXT: [[CONV:%.*]] = zext [[CMP]] to @@ -54,7 +54,7 @@ svint16_t cond_i16(svint16_t a, svint16_t b) { return a < b ? a : b; } -// CHECK-LABEL: @_Z8cond_u16u12__SVUint16_tu12__SVUint16_t( +// CHECK-LABEL: @_Z8cond_u16u12__SVUint16_tS_( // CHECK-NEXT: entry: // CHECK-NEXT: [[CMP:%.*]] = icmp ult [[A:%.*]], [[B:%.*]] // CHECK-NEXT: [[CONV:%.*]] = zext [[CMP]] to @@ -66,7 +66,7 @@ svuint16_t cond_u16(svuint16_t a, svuint16_t b) { return a < b ? a : b; } -// CHECK-LABEL: @_Z8cond_i32u11__SVInt32_tu11__SVInt32_t( +// CHECK-LABEL: @_Z8cond_i32u11__SVInt32_tS_( // CHECK-NEXT: entry: // CHECK-NEXT: [[CMP:%.*]] = icmp ult [[A:%.*]], [[B:%.*]] // CHECK-NEXT: [[CONV:%.*]] = zext [[CMP]] to @@ -78,7 +78,7 @@ svint32_t cond_i32(svint32_t a, svint32_t b) { return a < b ? a : b; } -// CHECK-LABEL: @_Z8cond_u32u12__SVUint32_tu12__SVUint32_t( +// CHECK-LABEL: @_Z8cond_u32u12__SVUint32_tS_( // CHECK-NEXT: entry: // CHECK-NEXT: [[CMP:%.*]] = icmp ult [[A:%.*]], [[B:%.*]] // CHECK-NEXT: [[CONV:%.*]] = zext [[CMP]] to @@ -90,7 +90,7 @@ svuint32_t cond_u32(svuint32_t a, svuint32_t b) { return a < b ? a : b; } -// CHECK-LABEL: @_Z8cond_i64u11__SVInt64_tu11__SVInt64_t( +// CHECK-LABEL: @_Z8cond_i64u11__SVInt64_tS_( // CHECK-NEXT: entry: // CHECK-NEXT: [[CMP:%.*]] = icmp ult [[A:%.*]], [[B:%.*]] // CHECK-NEXT: [[CONV:%.*]] = zext [[CMP]] to @@ -102,7 +102,7 @@ svint64_t cond_i64(svint64_t a, svint64_t b) { return a < b ? a : b; } -// CHECK-LABEL: @_Z8cond_u64u12__SVUint64_tu12__SVUint64_t( +// CHECK-LABEL: @_Z8cond_u64u12__SVUint64_tS_( // CHECK-NEXT: entry: // CHECK-NEXT: [[CMP:%.*]] = icmp ult [[A:%.*]], [[B:%.*]] // CHECK-NEXT: [[CONV:%.*]] = zext [[CMP]] to @@ -114,7 +114,7 @@ svuint64_t cond_u64(svuint64_t a, svuint64_t b) { return a < b ? a : b; } -// CHECK-LABEL: @_Z8cond_f16u13__SVFloat16_tu13__SVFloat16_t( +// CHECK-LABEL: @_Z8cond_f16u13__SVFloat16_tS_( // CHECK-NEXT: entry: // CHECK-NEXT: [[CMP:%.*]] = fcmp olt [[A:%.*]], [[B:%.*]] // CHECK-NEXT: [[CONV:%.*]] = zext [[CMP]] to @@ -126,7 +126,7 @@ svfloat16_t cond_f16(svfloat16_t a, svfloat16_t b) { return a < b ? a : b; } -// CHECK-LABEL: @_Z8cond_f32u13__SVFloat32_tu13__SVFloat32_t( +// CHECK-LABEL: @_Z8cond_f32u13__SVFloat32_tS_( // CHECK-NEXT: entry: // CHECK-NEXT: [[CMP:%.*]] = fcmp olt [[A:%.*]], [[B:%.*]] // CHECK-NEXT: [[CONV:%.*]] = zext [[CMP]] to @@ -138,7 +138,7 @@ svfloat32_t cond_f32(svfloat32_t a, svfloat32_t b) { return a < b ? a : b; } -// CHECK-LABEL: @_Z8cond_f64u13__SVFloat64_tu13__SVFloat64_t( +// CHECK-LABEL: @_Z8cond_f64u13__SVFloat64_tS_( // CHECK-NEXT: entry: // CHECK-NEXT: [[CMP:%.*]] = fcmp olt [[A:%.*]], [[B:%.*]] // CHECK-NEXT: [[CONV:%.*]] = zext [[CMP]] to diff --git a/clang/test/CodeGenCXX/aarch64-sve-vector-init.cpp b/clang/test/CodeGenCXX/aarch64-sve-vector-init.cpp index 464275f164c2a..3a57f80110d47 100644 --- a/clang/test/CodeGenCXX/aarch64-sve-vector-init.cpp +++ b/clang/test/CodeGenCXX/aarch64-sve-vector-init.cpp @@ -122,7 +122,7 @@ void test_locals(void) { __SVFloat16_t f16{}; __SVFloat32_t f32{}; __SVFloat64_t f64{}; - __SVBFloat16_t bf16{}; + __SVBfloat16_t bf16{}; __clang_svint8x2_t s8x2{}; __clang_svint16x2_t s16x2{}; @@ -324,7 +324,7 @@ void test_copy_f64(__SVFloat64_t a) { __SVFloat64_t b{a}; } -// CHECK-LABEL: define dso_local void @_Z14test_copy_bf16u14__SVBFloat16_t +// CHECK-LABEL: define dso_local void @_Z14test_copy_bf16u14__SVBfloat16_t // CHECK-SAME: ( [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[A_ADDR:%.*]] = alloca , align 16 @@ -334,8 +334,8 @@ void test_copy_f64(__SVFloat64_t a) { // CHECK-NEXT: store [[TMP0]], ptr [[B]], align 16 // CHECK-NEXT: ret void // -void test_copy_bf16(__SVBFloat16_t a) { - __SVBFloat16_t b{a}; +void test_copy_bf16(__SVBfloat16_t a) { + __SVBfloat16_t b{a}; } // CHECK-LABEL: define dso_local void @_Z14test_copy_s8x210svint8x2_t diff --git a/clang/test/CodeGenCXX/const-init-cxx11.cpp b/clang/test/CodeGenCXX/const-init-cxx11.cpp index d22d78d2b94ed..3a12fe444f137 100644 --- a/clang/test/CodeGenCXX/const-init-cxx11.cpp +++ b/clang/test/CodeGenCXX/const-init-cxx11.cpp @@ -424,6 +424,8 @@ namespace DR2126 { // CHECK: @_ZN33ClassTemplateWithStaticDataMember3useE ={{.*}} constant ptr @_ZGRN33ClassTemplateWithStaticDataMember1SIvE1aE_ // CHECK: @_ZGRN39ClassTemplateWithHiddenStaticDataMember1SIvE1aE_ = linkonce_odr hidden constant i32 5, comdat // CHECK: @_ZN39ClassTemplateWithHiddenStaticDataMember3useE ={{.*}} constant ptr @_ZGRN39ClassTemplateWithHiddenStaticDataMember1SIvE1aE_ +// CHECK: @.str.[[STR:[0-9]+]] ={{.*}} constant [9 x i8] c"12345678\00" +// CHECK-NEXT: @e = global %struct.PR69979 { ptr @.str.[[STR]] } // CHECK: @_ZGRZN20InlineStaticConstRef3funEvE1i_ = linkonce_odr constant i32 10, comdat // CHECK20: @_ZZN12LocalVarInit4dtorEvE1a = internal constant {{.*}} i32 103 @@ -632,6 +634,10 @@ struct X { const char *f() { return &X::p; } } +struct PR69979 { + const char (&d)[9]; +} e {"12345678"}; + // VirtualMembers::TemplateClass::templateMethod() must be defined in this TU, // not just declared. // CHECK: define linkonce_odr void @_ZN14VirtualMembers13TemplateClassIiE14templateMethodEv(ptr {{[^,]*}} %this) diff --git a/clang/test/CodeGenCXX/debug-info-structured-binding-bitfield.cpp b/clang/test/CodeGenCXX/debug-info-structured-binding-bitfield.cpp index b5ee96224565d..0234e41009f62 100644 --- a/clang/test/CodeGenCXX/debug-info-structured-binding-bitfield.cpp +++ b/clang/test/CodeGenCXX/debug-info-structured-binding-bitfield.cpp @@ -189,7 +189,6 @@ struct S11 { // CHECK-LABEL: define dso_local void @_Z4fS11v // CHECK: alloca %struct.S11, align 4 // CHECK-NEXT: [[TMP0:%.*]] = alloca %struct.S11, align 4 -// CHECK: call void @llvm.dbg.declare(metadata ptr [[TMP0]] // CHECK-NOT: call void @llvm.dbg.declare(metadata ptr [[TMP0]] // void fS11() { @@ -206,7 +205,6 @@ struct S12 { // CHECK: alloca %struct.S12, align 4 // CHECK-NEXT: [[TMP0:%.*]] = alloca %struct.S12, align 4 // CHECK: call void @llvm.dbg.declare(metadata ptr [[TMP0]], metadata [[S12_A:![0-9]+]], metadata !DIExpression()) -// CHECK: call void @llvm.dbg.declare(metadata ptr [[TMP0]] // CHECK-NOT: call void @llvm.dbg.declare(metadata ptr [[TMP0]] // void fS12() { @@ -222,7 +220,6 @@ struct __attribute__((packed)) S13 { // CHECK-LABEL: define dso_local void @_Z4fS13v // CHECK: alloca %struct.S13, align 1 // CHECK-NEXT: [[TMP0:%.*]] = alloca %struct.S13, align 1 -// CHECK: call void @llvm.dbg.declare(metadata ptr [[TMP0]], metadata {{.*}}, metadata !DIExpression()) // CHECK-NOT: call void @llvm.dbg.declare(metadata ptr [[TMP0]] // void fS13() { diff --git a/clang/test/CodeGenCXX/debug-info-structured-binding.cpp b/clang/test/CodeGenCXX/debug-info-structured-binding.cpp index 8d4ae0aaf3263..7f3c3a08941ab 100644 --- a/clang/test/CodeGenCXX/debug-info-structured-binding.cpp +++ b/clang/test/CodeGenCXX/debug-info-structured-binding.cpp @@ -1,11 +1,16 @@ -// RUN: %clang_cc1 -emit-llvm -debug-info-kind=standalone -triple %itanium_abi_triple %s -o - | FileCheck %s +// RUN: %clang_cc1 -emit-llvm -debug-info-kind=standalone -triple %itanium_abi_triple %s -o - | FileCheck %s --implicit-check-not="call void @llvm.dbg.declare" + +// CHECK: call void @llvm.dbg.declare(metadata ptr %{{[a-z]+}}, metadata ![[VAR_0:[0-9]+]], metadata !DIExpression()) +// CHECK: call void @llvm.dbg.declare(metadata ptr %{{[0-9]+}}, metadata ![[VAR_1:[0-9]+]], metadata !DIExpression()) +// CHECK: call void @llvm.dbg.declare(metadata ptr %{{[0-9]+}}, metadata ![[VAR_2:[0-9]+]], metadata !DIExpression(DW_OP_plus_uconst, 4)) +// CHECK: call void @llvm.dbg.declare(metadata ptr %{{[0-9]+}}, metadata ![[VAR_3:[0-9]+]], metadata !DIExpression(DW_OP_deref)) +// CHECK: call void @llvm.dbg.declare(metadata ptr %{{[0-9]+}}, metadata ![[VAR_4:[0-9]+]], metadata !DIExpression(DW_OP_deref, DW_OP_plus_uconst, 4)) +// CHECK: ![[VAR_0]] = !DILocalVariable(name: "a" +// CHECK: ![[VAR_1]] = !DILocalVariable(name: "x1" +// CHECK: ![[VAR_2]] = !DILocalVariable(name: "y1" +// CHECK: ![[VAR_3]] = !DILocalVariable(name: "x2" +// CHECK: ![[VAR_4]] = !DILocalVariable(name: "y2" -// CHECK: call void @llvm.dbg.declare(metadata ptr %{{[0-9]+}}, metadata !{{[0-9]+}}, metadata !DIExpression()) -// CHECK: call void @llvm.dbg.declare(metadata ptr %{{[0-9]+}}, metadata !{{[0-9]+}}, metadata !DIExpression(DW_OP_plus_uconst, {{[0-9]+}})) -// CHECK: call void @llvm.dbg.declare(metadata ptr %{{[0-9]+}}, metadata !{{[0-9]+}}, metadata !DIExpression()) -// CHECK: call void @llvm.dbg.declare(metadata ptr %{{[0-9]+}}, metadata !{{[0-9]+}}, metadata !DIExpression(DW_OP_deref)) -// CHECK: call void @llvm.dbg.declare(metadata ptr %{{[0-9]+}}, metadata !{{[0-9]+}}, metadata !DIExpression(DW_OP_deref, DW_OP_plus_uconst, {{[0-9]+}})) -// CHECK: call void @llvm.dbg.declare(metadata ptr %{{[0-9]+}}, metadata !{{[0-9]+}}, metadata !DIExpression()) struct A { int x; int y; diff --git a/clang/test/CodeGenCXX/fixed-point-mangle.cpp b/clang/test/CodeGenCXX/fixed-point-mangle.cpp deleted file mode 100644 index 103990a61316a..0000000000000 --- a/clang/test/CodeGenCXX/fixed-point-mangle.cpp +++ /dev/null @@ -1,45 +0,0 @@ -// RUN: %clang_cc1 -ffixed-point -S -emit-llvm %s -o - -triple=x86_64-unknown-linux-gnu | FileCheck %s - -// Primary fixed point types -void func(signed short _Accum){} // CHECK: @_Z4funcDAs -void func(signed _Accum){} // CHECK: @_Z4funcDAi -void func(signed long _Accum){} // CHECK: @_Z4funcDAl -void func(unsigned short _Accum){} // CHECK: @_Z4funcDAt -void func(unsigned _Accum){} // CHECK: @_Z4funcDAj -void func(unsigned long _Accum){} // CHECK: @_Z4funcDAm -void func(signed short _Fract){} // CHECK: @_Z4funcDRs -void func(signed _Fract){} // CHECK: @_Z4funcDRi -void func(signed long _Fract){} // CHECK: @_Z4funcDRl -void func(unsigned short _Fract){} // CHECK: @_Z4funcDRt -void func(unsigned _Fract){} // CHECK: @_Z4funcDRj -void func(unsigned long _Fract){} // CHECK: @_Z4funcDRm - -// Aliased -void func2(short _Accum){} // CHECK: @_Z5func2DAs -void func2(_Accum){} // CHECK: @_Z5func2DAi -void func2(long _Accum){} // CHECK: @_Z5func2DAl -void func2(short _Fract){} // CHECK: @_Z5func2DRs -void func2(_Fract){} // CHECK: @_Z5func2DRi -void func2(long _Fract){} // CHECK: @_Z5func2DRl - -// Primary saturated -void func(_Sat signed short _Accum){} // CHECK: @_Z4funcDSDAs -void func(_Sat signed _Accum){} // CHECK: @_Z4funcDSDAi -void func(_Sat signed long _Accum){} // CHECK: @_Z4funcDSDAl -void func(_Sat unsigned short _Accum){} // CHECK: @_Z4funcDSDAt -void func(_Sat unsigned _Accum){} // CHECK: @_Z4funcDSDAj -void func(_Sat unsigned long _Accum){} // CHECK: @_Z4funcDSDAm -void func(_Sat signed short _Fract){} // CHECK: @_Z4funcDSDRs -void func(_Sat signed _Fract){} // CHECK: @_Z4funcDSDRi -void func(_Sat signed long _Fract){} // CHECK: @_Z4funcDSDRl -void func(_Sat unsigned short _Fract){} // CHECK: @_Z4funcDSDRt -void func(_Sat unsigned _Fract){} // CHECK: @_Z4funcDSDRj -void func(_Sat unsigned long _Fract){} // CHECK: @_Z4funcDSDRm - -// Aliased saturated -void func2(_Sat short _Accum){} // CHECK: @_Z5func2DSDAs -void func2(_Sat _Accum){} // CHECK: @_Z5func2DSDAi -void func2(_Sat long _Accum){} // CHECK: @_Z5func2DSDAl -void func2(_Sat short _Fract){} // CHECK: @_Z5func2DSDRs -void func2(_Sat _Fract){} // CHECK: @_Z5func2DSDRi -void func2(_Sat long _Fract){} // CHECK: @_Z5func2DSDRl diff --git a/clang/test/CodeGenObjC/aarch64-sve-types.m b/clang/test/CodeGenObjC/aarch64-sve-types.m index cc0a95a044068..eae734fa4d593 100644 --- a/clang/test/CodeGenObjC/aarch64-sve-types.m +++ b/clang/test/CodeGenObjC/aarch64-sve-types.m @@ -28,8 +28,8 @@ // CHECK: error: cannot yet @encode type __SVFloat64_t const char f64[] = @encode(__SVFloat64_t); -// CHECK: error: cannot yet @encode type __SVBFloat16_t -const char bf16[] = @encode(__SVBFloat16_t); +// CHECK: error: cannot yet @encode type __SVBfloat16_t +const char bf16[] = @encode(__SVBfloat16_t); // CHECK: error: cannot yet @encode type __SVBool_t const char b8[] = @encode(__SVBool_t); diff --git a/clang/test/CodeGenObjC/arc.m b/clang/test/CodeGenObjC/arc.m index fb4eb3452318d..754c339cb2b31 100644 --- a/clang/test/CodeGenObjC/arc.m +++ b/clang/test/CodeGenObjC/arc.m @@ -7,30 +7,30 @@ // RUN: %clang_cc1 -fobjc-runtime=macosx-10.7.0 -triple x86_64-apple-darwin11 -Wno-objc-root-class -Wno-incompatible-pointer-types -Wno-arc-unsafe-retained-assign -emit-llvm -fblocks -fobjc-arc -fobjc-runtime-has-weak -o - %s | FileCheck -check-prefix=ARC-NATIVE %s // ARC-ALIEN: declare extern_weak void @llvm.objc.storeStrong(ptr, ptr) -// ARC-ALIEN: declare extern_weak ptr @llvm.objc.retain(ptr returned) -// ARC-ALIEN: declare extern_weak ptr @llvm.objc.autoreleaseReturnValue(ptr returned) +// ARC-ALIEN: declare extern_weak ptr @llvm.objc.retain(ptr) +// ARC-ALIEN: declare extern_weak ptr @llvm.objc.autoreleaseReturnValue(ptr) // ARC-ALIEN: declare ptr @objc_msgSend(ptr, ptr, ...) [[NLB:#[0-9]+]] // ARC-ALIEN: declare extern_weak void @llvm.objc.release(ptr) -// ARC-ALIEN: declare extern_weak ptr @llvm.objc.retainAutoreleasedReturnValue(ptr returned) +// ARC-ALIEN: declare extern_weak ptr @llvm.objc.retainAutoreleasedReturnValue(ptr) // ARC-ALIEN: declare extern_weak ptr @llvm.objc.initWeak(ptr, ptr) // ARC-ALIEN: declare extern_weak ptr @llvm.objc.storeWeak(ptr, ptr) // ARC-ALIEN: declare extern_weak ptr @llvm.objc.loadWeakRetained(ptr) // ARC-ALIEN: declare extern_weak void @llvm.objc.destroyWeak(ptr) -// ARC-ALIEN: declare extern_weak ptr @llvm.objc.autorelease(ptr returned) -// ARC-ALIEN: declare extern_weak ptr @llvm.objc.retainAutorelease(ptr returned) +// ARC-ALIEN: declare extern_weak ptr @llvm.objc.autorelease(ptr) +// ARC-ALIEN: declare extern_weak ptr @llvm.objc.retainAutorelease(ptr) // ARC-NATIVE: declare void @llvm.objc.storeStrong(ptr, ptr) -// ARC-NATIVE: declare ptr @llvm.objc.retain(ptr returned) -// ARC-NATIVE: declare ptr @llvm.objc.autoreleaseReturnValue(ptr returned) +// ARC-NATIVE: declare ptr @llvm.objc.retain(ptr) +// ARC-NATIVE: declare ptr @llvm.objc.autoreleaseReturnValue(ptr) // ARC-NATIVE: declare ptr @objc_msgSend(ptr, ptr, ...) [[NLB:#[0-9]+]] // ARC-NATIVE: declare void @llvm.objc.release(ptr) -// ARC-NATIVE: declare ptr @llvm.objc.retainAutoreleasedReturnValue(ptr returned) +// ARC-NATIVE: declare ptr @llvm.objc.retainAutoreleasedReturnValue(ptr) // ARC-NATIVE: declare ptr @llvm.objc.initWeak(ptr, ptr) // ARC-NATIVE: declare ptr @llvm.objc.storeWeak(ptr, ptr) // ARC-NATIVE: declare ptr @llvm.objc.loadWeakRetained(ptr) // ARC-NATIVE: declare void @llvm.objc.destroyWeak(ptr) -// ARC-NATIVE: declare ptr @llvm.objc.autorelease(ptr returned) -// ARC-NATIVE: declare ptr @llvm.objc.retainAutorelease(ptr returned) +// ARC-NATIVE: declare ptr @llvm.objc.autorelease(ptr) +// ARC-NATIVE: declare ptr @llvm.objc.retainAutorelease(ptr) // CHECK-LABEL: define{{.*}} void @test0 void test0(id x) { diff --git a/clang/test/CodeGenObjC/convert-messages-to-runtime-calls.m b/clang/test/CodeGenObjC/convert-messages-to-runtime-calls.m index a60c9b0feb801..9a5ecbc03d8ae 100644 --- a/clang/test/CodeGenObjC/convert-messages-to-runtime-calls.m +++ b/clang/test/CodeGenObjC/convert-messages-to-runtime-calls.m @@ -28,11 +28,6 @@ void test1(id x) { // MSGS: {{call.*@objc_msgSend}} // CALLS: {{call.*@objc_alloc}} // CALLS: {{call.*@objc_allocWithZone}} - - // Note that calls to the intrinsics are not allowed for - // retain/release/autorelease they're marked `thisreturn`, which isn't - // guaranteed to be true for classes that define their own `-retain`, for - // example. Be sure to keep these as normal function calls: // CALLS: {{call.*@objc_retain}} // CALLS: {{call.*@objc_release}} // CALLS: {{tail call.*@objc_autorelease}} diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-wave32.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-wave32.cl index a4d14cf1f6cf0..43553131f63c5 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn-wave32.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-wave32.cl @@ -13,6 +13,8 @@ void test_ballot_wave32(global uint* out, int a, int b) *out = __builtin_amdgcn_ballot_w32(a == b); } +// CHECK: declare i32 @llvm.amdgcn.ballot.i32(i1) #[[$NOUNWIND_READONLY:[0-9]+]] + // CHECK-LABEL: @test_ballot_wave32_target_attr( // CHECK: call i32 @llvm.amdgcn.ballot.i32(i1 %{{.+}}) __attribute__((target("wavefrontsize32"))) @@ -21,6 +23,28 @@ void test_ballot_wave32_target_attr(global uint* out, int a, int b) *out = __builtin_amdgcn_ballot_w32(a == b); } +// CHECK-LABEL: @test_read_exec( +// CHECK: call i64 @llvm.amdgcn.ballot.i64(i1 true) +void test_read_exec(global uint* out) { + *out = __builtin_amdgcn_read_exec(); +} + +// CHECK: declare i64 @llvm.amdgcn.ballot.i64(i1) #[[$NOUNWIND_READONLY:[0-9]+]] + +// CHECK-LABEL: @test_read_exec_lo( +// CHECK: call i32 @llvm.amdgcn.ballot.i32(i1 true) +void test_read_exec_lo(global uint* out) { + *out = __builtin_amdgcn_read_exec_lo(); +} + +// CHECK-LABEL: @test_read_exec_hi( +// CHECK: call i64 @llvm.amdgcn.ballot.i64(i1 true) +// CHECK: lshr i64 [[A:%.*]], 32 +// CHECK: trunc i64 [[B:%.*]] to i32 +void test_read_exec_hi(global uint* out) { + *out = __builtin_amdgcn_read_exec_hi(); +} + #if __AMDGCN_WAVEFRONT_SIZE != 32 #error Wrong wavesize detected #endif diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-wave64.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-wave64.cl index 563c9a2a240c1..53f34c6a44ae7 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn-wave64.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-wave64.cl @@ -13,6 +13,8 @@ void test_ballot_wave64(global ulong* out, int a, int b) *out = __builtin_amdgcn_ballot_w64(a == b); } +// CHECK: declare i64 @llvm.amdgcn.ballot.i64(i1) #[[$NOUNWIND_READONLY:[0-9]+]] + // CHECK-LABEL: @test_ballot_wave64_target_attr( // CHECK: call i64 @llvm.amdgcn.ballot.i64(i1 %{{.+}}) __attribute__((target("wavefrontsize64"))) @@ -21,6 +23,27 @@ void test_ballot_wave64_target_attr(global ulong* out, int a, int b) *out = __builtin_amdgcn_ballot_w64(a == b); } +// CHECK-LABEL: @test_read_exec( +// CHECK: call i64 @llvm.amdgcn.ballot.i64(i1 true) +void test_read_exec(global ulong* out) { + *out = __builtin_amdgcn_read_exec(); +} + +// CHECK-LABEL: @test_read_exec_lo( +// CHECK: call i32 @llvm.amdgcn.ballot.i32(i1 true) +void test_read_exec_lo(global ulong* out) { + *out = __builtin_amdgcn_read_exec_lo(); +} + +// CHECK: declare i32 @llvm.amdgcn.ballot.i32(i1) #[[$NOUNWIND_READONLY:[0-9]+]] + +// CHECK-LABEL: @test_read_exec_hi( +// CHECK: call i64 @llvm.amdgcn.ballot.i64(i1 true) +// CHECK: lshr i64 [[A:%.*]], 32 +void test_read_exec_hi(global ulong* out) { + *out = __builtin_amdgcn_read_exec_hi(); +} + #if __AMDGCN_WAVEFRONT_SIZE != 64 #error Wrong wavesize detected #endif diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn.cl index 8938642e3b19f..0bc9a54682d3e 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn.cl @@ -526,7 +526,9 @@ void test_read_exec_lo(global uint* out) { // CHECK: declare i32 @llvm.amdgcn.ballot.i32(i1) #[[$NOUNWIND_READONLY:[0-9]+]] // CHECK-LABEL: @test_read_exec_hi( -// CHECK: call i32 @llvm.amdgcn.ballot.i32(i1 true) +// CHECK: call i64 @llvm.amdgcn.ballot.i64(i1 true) +// CHECK: lshr i64 [[A:%.*]], 32 +// CHECK: trunc i64 [[B:%.*]] to i32 void test_read_exec_hi(global uint* out) { *out = __builtin_amdgcn_read_exec_hi(); } diff --git a/clang/test/Driver/amdgpu-openmp-toolchain.c b/clang/test/Driver/amdgpu-openmp-toolchain.c index 06b6ed324e74e..f38486ad0cccc 100644 --- a/clang/test/Driver/amdgpu-openmp-toolchain.c +++ b/clang/test/Driver/amdgpu-openmp-toolchain.c @@ -56,7 +56,7 @@ // RUN: %clang -### -target x86_64-pc-linux-gnu -fopenmp --offload-arch=gfx803 \ // RUN: --rocm-device-lib-path=%S/Inputs/rocm/amdgcn/bitcode -fopenmp-new-driver %s 2>&1 | \ // RUN: FileCheck %s --check-prefix=CHECK-LIB-DEVICE -// CHECK-LIB-DEVICE: "-cc1" {{.*}}ocml.bc"{{.*}}ockl.bc"{{.*}}oclc_daz_opt_on.bc"{{.*}}oclc_unsafe_math_off.bc"{{.*}}oclc_finite_only_off.bc"{{.*}}oclc_correctly_rounded_sqrt_on.bc"{{.*}}oclc_wavefrontsize64_on.bc"{{.*}}oclc_isa_version_803.bc" +// CHECK-LIB-DEVICE: "-cc1" {{.*}}ocml.bc"{{.*}}oclc_daz_opt_on.bc"{{.*}}oclc_unsafe_math_off.bc"{{.*}}oclc_finite_only_off.bc"{{.*}}oclc_correctly_rounded_sqrt_on.bc"{{.*}}oclc_wavefrontsize64_on.bc"{{.*}}oclc_isa_version_803.bc" // RUN: %clang -### -target x86_64-pc-linux-gnu -fopenmp --offload-arch=gfx803 -nogpulib \ // RUN: --rocm-device-lib-path=%S/Inputs/rocm/amdgcn/bitcode -fopenmp-new-driver %s 2>&1 | \ diff --git a/clang/test/Driver/cl-delayed-template-parsing-cxx20.cpp b/clang/test/Driver/cl-delayed-template-parsing-cxx20.cpp new file mode 100644 index 0000000000000..7af9b2447bb4b --- /dev/null +++ b/clang/test/Driver/cl-delayed-template-parsing-cxx20.cpp @@ -0,0 +1,10 @@ +// RUN: %clang_cl -### -- %s 2>&1 | FileCheck %s --check-prefix=PRE-CXX20 +// RUN: %clang_cl -std:c++20 -### -- %s 2>&1 | FileCheck %s +// RUN: %clang_cl -std:c++20 -### -fdelayed-template-parsing -- %s 2>&1 | FileCheck %s --check-prefix=CHECK-EXPLICIT + +// PRE-CXX20: -fdelayed-template-parsing + +// CHECK-NOT: -fdelayed-template-parsing + +// CHECK-EXPLICIT: warning: -fdelayed-template-parsing is deprecated after C++20 +// CHECK-EXPLICIT: -fdelayed-template-parsing diff --git a/clang/test/Driver/cl-offload.cu b/clang/test/Driver/cl-offload.cu index c3bc5a2c08275..b05bf3b97b7eb 100644 --- a/clang/test/Driver/cl-offload.cu +++ b/clang/test/Driver/cl-offload.cu @@ -1,10 +1,14 @@ +// REQUIRES: !system-solaris + +// The test cannot be run on Darwin because /Users will be treated as a MSVC option. + // RUN: %clang_cl -### -target x86_64-pc-windows-msvc --offload-arch=sm_35 -fgpu-rdc \ // RUN: --cuda-path=%S/Inputs/CUDA/usr/local/cuda \ -// RUN: /Wall -x cuda %s 2>&1 \ +// RUN: /Wall -x cuda -- %s 2>&1 \ // RUN: | FileCheck %s -check-prefix=CUDA // RUN: %clang_cl -### -target x86_64-pc-windows-msvc --offload-arch=gfx1010 -fgpu-rdc --hip-link \ -// RUN: --rocm-path=%S/Inputs/rocm /Wall -x hip %s 2>&1 \ +// RUN: --rocm-path=%S/Inputs/rocm /Wall -x hip -- %s 2>&1 \ // RUN: | FileCheck %s -check-prefix=HIP // CUDA: "-cc1" "-triple" "nvptx64-nvidia-cuda" "-aux-triple" "x86_64-pc-windows-msvc" diff --git a/clang/test/Driver/darwin-ld.c b/clang/test/Driver/darwin-ld.c index b835b1f876beb..f0ca411430cc7 100644 --- a/clang/test/Driver/darwin-ld.c +++ b/clang/test/Driver/darwin-ld.c @@ -336,7 +336,7 @@ // RUN: FileCheck -check-prefix=PROFILE_SECTALIGN %s < %t.log // RUN: %clang -target arm64-apple-ios12 -fprofile-instr-generate -### %t.o 2> %t.log // RUN: FileCheck -check-prefix=PROFILE_SECTALIGN %s < %t.log -// PROFILE_SECTALIGN: "-sectalign" "__DATA" "__llvm_prf_cnts" "0x4000" "-sectalign" "__DATA" "__llvm_prf_data" "0x4000" +// PROFILE_SECTALIGN: "-sectalign" "__DATA" "__llvm_prf_cnts" "0x4000" "-sectalign" "__DATA" "__llvm_prf_bits" "0x4000" "-sectalign" "__DATA" "__llvm_prf_data" "0x4000" // RUN: %clang -target x86_64-apple-darwin12 -fprofile-instr-generate --coverage -### %t.o 2> %t.log // RUN: FileCheck -check-prefix=NO_PROFILE_EXPORT %s < %t.log diff --git a/clang/test/Driver/freebsd.c b/clang/test/Driver/freebsd.c index afa0a17249851..e1ce8889459f9 100644 --- a/clang/test/Driver/freebsd.c +++ b/clang/test/Driver/freebsd.c @@ -163,9 +163,9 @@ // CHECK-ARM-EABIHF-NOT: as{{.*}}" "-mfpu=softvfp" // CHECK-ARM-EABIHF-NOT: as{{.*}}" "-matpcs" -// RUN: %clang --target=sparc-unknown-freebsd -### %s -fpic -no-integrated-as 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-SPARC-PIE %s -// CHECK-SPARC-PIE: as{{.*}}" "-KPIC +// RUN: %clang --target=sparc64-unknown-freebsd -### %s -fpic -no-integrated-as 2>&1 \ +// RUN: | FileCheck --check-prefix=CHECK-SPARC-PIC %s +// CHECK-SPARC-PIC: as{{.*}}" "-KPIC // RUN: %clang -mcpu=ultrasparc --target=sparc64-unknown-freebsd -### %s -no-integrated-as 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-SPARC-CPU %s @@ -191,11 +191,6 @@ // RUN: | FileCheck -check-prefix=CHECK-MIPS64-CPU %s // CHECK-MIPS64-CPU: "-target-cpu" "mips3" -// Check that the integrated assembler is enabled for SPARC64 -// RUN: %clang --target=sparc64-unknown-freebsd -### -c %s 2>&1 \ -// RUN: | FileCheck -check-prefix=CHECK-IAS %s -// CHECK-IAS-NOT: "-no-integrated-as" - // RUN: %clang --target=ppc64-unknown-freebsd13.0 -### -S %s 2>&1 | \ // RUN: FileCheck -check-prefix=PPC64-MUNWIND %s // PPC64-MUNWIND: "-funwind-tables=2" diff --git a/clang/test/Driver/hlsl-lang-targets-spirv.hlsl b/clang/test/Driver/hlsl-lang-targets-spirv.hlsl index ff29f143ba1dc..e04d71263770b 100644 --- a/clang/test/Driver/hlsl-lang-targets-spirv.hlsl +++ b/clang/test/Driver/hlsl-lang-targets-spirv.hlsl @@ -2,8 +2,8 @@ // Supported targets // -// RUN: %clang -target dxil-unknown-shadermodel6.2-pixel %s -S -o /dev/null 2>&1 | FileCheck --check-prefix=CHECK-VALID %s -// RUN: %clang -target spirv-unknown-shadermodel6.2-library %s -S -o /dev/null 2>&1 | FileCheck --check-prefix=CHECK-VALID %s +// RUN: %clang -target dxil-unknown-shadermodel6.2-compute %s -S -o /dev/null 2>&1 | FileCheck --allow-empty --check-prefix=CHECK-VALID %s +// RUN: %clang -target spirv-unknown-shadermodel6.2-compute %s -S -o /dev/null 2>&1 | FileCheck --allow-empty --check-prefix=CHECK-VALID %s // Empty shader model // @@ -27,5 +27,5 @@ // CHECK-NO-ENV: error: shader stage is required in target '{{.*}}' for HLSL code generation // CHECK-BAD-ENV: error: shader stage '{{.*}}' in target '{{.*}}' is invalid for HLSL code generation -[shader("pixel")] +[shader("compute"), numthreads(1,1,1)] void main() {} diff --git a/clang/test/Driver/lto.c b/clang/test/Driver/lto.c index 62bdbd6f5d3cf..b6c89eb99e274 100644 --- a/clang/test/Driver/lto.c +++ b/clang/test/Driver/lto.c @@ -105,3 +105,12 @@ // FLTO-THIN: -flto=thin // FLTO-THIN-NOT: "-flto" // FLTO-THIN-NOT: -flto=full + +// -flto passes along an explicit GlobalISel flag. +// RUN: %clang --target=riscv64-linux-gnu -### %s -flto -fglobal-isel 2> %t +// RUN: FileCheck --check-prefix=CHECK-GISEL < %t %s +// RUN: %clang --target=aarch64-linux-gnu -### %s -flto -fno-global-isel 2> %t +// RUN: FileCheck --check-prefix=CHECK-DISABLE-GISEL < %t %s +// +// CHECK-GISEL: "-plugin-opt=-global-isel=1" +// CHECK-DISABLE-GISEL: "-plugin-opt=-global-isel=0" diff --git a/clang/test/Driver/mcmodel.c b/clang/test/Driver/mcmodel.c index 63b4320361592..fb3bbccb0c681 100644 --- a/clang/test/Driver/mcmodel.c +++ b/clang/test/Driver/mcmodel.c @@ -1,13 +1,18 @@ +// RUN: not %clang -### -c --target=i686 -mcmodel=medium %s 2>&1 | FileCheck --check-prefix=ERR-MEDIUM %s // RUN: %clang --target=x86_64 -### -c -mcmodel=tiny %s 2>&1 | FileCheck --check-prefix=TINY %s // RUN: %clang --target=x86_64 -### -c -mcmodel=small %s 2>&1 | FileCheck --check-prefix=SMALL %s // RUN: %clang --target=x86_64 -### -S -mcmodel=kernel %s 2>&1 | FileCheck --check-prefix=KERNEL %s // RUN: %clang --target=x86_64 -### -c -mcmodel=medium %s 2>&1 | FileCheck --check-prefix=MEDIUM %s // RUN: %clang --target=x86_64 -### -S -mcmodel=large %s 2>&1 | FileCheck --check-prefix=LARGE %s +// RUN: not %clang -### -c --target=powerpc-linux-gnu -mcmodel=medium %s 2>&1 | FileCheck --check-prefix=ERR-MEDIUM %s // RUN: %clang --target=powerpc-unknown-aix -### -S -mcmodel=medium %s 2> %t.log // RUN: FileCheck --check-prefix=AIX-MCMEDIUM-OVERRIDE %s < %t.log -// RUN: not %clang -c -mcmodel=lager %s 2>&1 | FileCheck --check-prefix=INVALID %s -// RUN: not %clang -c --target=aarch64 -mcmodel=medium %s 2>&1 | FileCheck --check-prefix=AARCH64-MEDIUM %s -// RUN: not %clang -c --target=aarch64 -mcmodel=kernel %s 2>&1 | FileCheck --check-prefix=AARCH64-KERNEL %s +// RUN: not %clang -### -c -mcmodel=lager %s 2>&1 | FileCheck --check-prefix=INVALID %s +// RUN: %clang --target=aarch64 -### -S -mcmodel=large -fno-pic %s 2>&1 | FileCheck --check-prefix=LARGE %s +// RUN: not %clang --target=aarch64 -### -S -mcmodel=large -fpic %s 2>&1 | FileCheck --check-prefix=AARCH64-PIC-LARGE %s +// RUN: not %clang -### -c --target=aarch64 -mcmodel=medium %s 2>&1 | FileCheck --check-prefix=ERR-MEDIUM %s +// RUN: not %clang -### -c --target=aarch64 -mcmodel=kernel %s 2>&1 | FileCheck --check-prefix=ERR-KERNEL %s +// RUN: not %clang --target=aarch64_32-linux -### -S -mcmodel=small %s 2>&1 | FileCheck --check-prefix=ERR-AARCH64_32 %s // TINY: "-mcmodel=tiny" // SMALL: "-mcmodel=small" @@ -16,7 +21,11 @@ // LARGE: "-mcmodel=large" // AIX-MCMEDIUM-OVERRIDE: "-mcmodel=large" -// INVALID: error: invalid argument 'lager' to -mcmodel= +// INVALID: error: unsupported argument 'lager' to option '-mcmodel=' for target '{{.*}}' -// AARCH64-MEDIUM: error: invalid argument 'medium' to -mcmodel= -// AARCH64-KERNEL: error: invalid argument 'kernel' to -mcmodel= +// ERR-MEDIUM: error: unsupported argument 'medium' to option '-mcmodel=' for target '{{.*}}' +// ERR-KERNEL: error: unsupported argument 'kernel' to option '-mcmodel=' for target '{{.*}}' +// ERR-LARGE: error: unsupported argument 'large' to option '-mcmodel=' for target '{{.*}}' + +// AARCH64-PIC-LARGE: error: invalid argument '-mcmodel=large' only allowed with '-fno-pic' +// ERR-AARCH64_32: error: unsupported argument 'small' to option '-mcmodel=' for target 'aarch64_32-unknown-linux' diff --git a/clang/test/Driver/openbsd.c b/clang/test/Driver/openbsd.c index c84b54f24fdc2..f42da97110b50 100644 --- a/clang/test/Driver/openbsd.c +++ b/clang/test/Driver/openbsd.c @@ -2,13 +2,13 @@ // RUN: %clang --target=i686-pc-openbsd -static -### %s 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-LD-STATIC-EH %s // CHECK-LD-STATIC-EH: "-cc1" "-triple" "i686-pc-openbsd" -// CHECK-LD-STATIC-EH: ld{{.*}}" "-e" "__start" "--eh-frame-hdr" "-Bstatic" "-o" "a.out" "{{.*}}rcrt0.o" "{{.*}}crtbegin.o" "{{.*}}.o" "-lcompiler_rt" "-lc" "-lcompiler_rt" "{{.*}}crtend.o" +// CHECK-LD-STATIC-EH: ld{{.*}}" "{{.*}}" "--eh-frame-hdr" "-Bstatic" // Check for profiling variants of libraries when linking and -nopie // RUN: %clang --target=i686-pc-openbsd -pg -pthread -### %s 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-PG %s // CHECK-PG: "-cc1" "-triple" "i686-pc-openbsd" -// CHECK-PG: ld{{.*}}" "-e" "__start" "--eh-frame-hdr" "-Bdynamic" "-dynamic-linker" "{{.*}}ld.so" "-nopie" "-o" "a.out" "{{.*}}gcrt0.o" "{{.*}}crtbegin.o" "{{.*}}.o" "-lcompiler_rt" "-lpthread_p" "-lc_p" "-lcompiler_rt" "{{.*}}crtend.o" +// CHECK-PG: ld{{.*}}" "-e" "__start" "--eh-frame-hdr" "-dynamic-linker" "{{.*}}ld.so" "-nopie" "-o" "a.out" "{{.*}}gcrt0.o" "{{.*}}crtbegin.o" "{{.*}}.o" "-lcompiler_rt" "-lpthread_p" "-lc_p" "-lcompiler_rt" "{{.*}}crtend.o" // Check CPU type for i386 // RUN: %clang --target=i386-unknown-openbsd -### -c %s 2>&1 \ @@ -26,26 +26,23 @@ // Check that the new linker flags are passed to OpenBSD // RUN: %clang --target=i686-pc-openbsd -r -### %s 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-LD-R %s -// RUN: %clang --target=i686-pc-openbsd -s -### %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-LD-S %s -// RUN: %clang --target=i686-pc-openbsd -t -### %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-LD-T %s +// RUN: %clang --target=i686-pc-openbsd -s -t -### %s 2>&1 \ +// RUN: | FileCheck --check-prefix=CHECK-LD-ST %s // RUN: %clang --target=mips64-unknown-openbsd -### %s 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-MIPS64-LD %s // RUN: %clang --target=mips64el-unknown-openbsd -### %s 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-MIPS64EL-LD %s -// CHECK-LD-R: "-r" +// CHECK-LD-R-NOT: "-e" // CHECK-LD-R-NOT: "-dynamic-linker" // CHECK-LD-R-NOT: "-l // CHECK-LD-R-NOT: crt{{[^./\\]+}}.o -// CHECK-LD-S: "-cc1" "-triple" "i686-pc-openbsd" -// CHECK-LD-S: ld{{.*}}" "-e" "__start" "--eh-frame-hdr" "-Bdynamic" "-dynamic-linker" "{{.*}}ld.so" "-o" "a.out" "{{.*}}crt0.o" "{{.*}}crtbegin.o" "-L{{.*}}" "-s" "{{.*}}.o" "-lcompiler_rt" "-lc" "-lcompiler_rt" "{{.*}}crtend.o" -// CHECK-LD-T: "-cc1" "-triple" "i686-pc-openbsd" -// CHECK-LD-T: ld{{.*}}" "-e" "__start" "--eh-frame-hdr" "-Bdynamic" "-dynamic-linker" "{{.*}}ld.so" "-o" "a.out" "{{.*}}crt0.o" "{{.*}}crtbegin.o" "-L{{.*}}" "-t" "{{.*}}.o" "-lcompiler_rt" "-lc" "-lcompiler_rt" "{{.*}}crtend.o" +// CHECK-LD-R: "-r" +// CHECK-LD-ST: "-cc1" "-triple" "i686-pc-openbsd" +// CHECK-LD-ST: ld{{.*}}" "{{.*}}" "-s" "-t" // CHECK-MIPS64-LD: "-cc1" "-triple" "mips64-unknown-openbsd" -// CHECK-MIPS64-LD: ld{{.*}}" "-EB" "-e" "__start" "--eh-frame-hdr" "-Bdynamic" "-dynamic-linker" "{{.*}}ld.so" "-o" "a.out" "{{.*}}crt0.o" "{{.*}}crtbegin.o" "-L{{.*}}" "{{.*}}.o" "-lcompiler_rt" "-lc" "-lcompiler_rt" "{{.*}}crtend.o" +// CHECK-MIPS64-LD: ld{{.*}}" "-EB" // CHECK-MIPS64EL-LD: "-cc1" "-triple" "mips64el-unknown-openbsd" -// CHECK-MIPS64EL-LD: ld{{.*}}" "-EL" "-e" "__start" "--eh-frame-hdr" "-Bdynamic" "-dynamic-linker" "{{.*}}ld.so" "-o" "a.out" "{{.*}}crt0.o" "{{.*}}crtbegin.o" "-L{{.*}}" "{{.*}}.o" "-lcompiler_rt" "-lc" "-lcompiler_rt" "{{.*}}crtend.o" +// CHECK-MIPS64EL-LD: ld{{.*}}" "-EL" // Check that --sysroot is passed to the linker // RUN: %clang --target=i686-pc-openbsd -### %s 2>&1 \ diff --git a/clang/test/Driver/riscv-sdata-warning.c b/clang/test/Driver/riscv-sdata-warning.c index dbb5f5de9cd81..ace9a32ee116f 100644 --- a/clang/test/Driver/riscv-sdata-warning.c +++ b/clang/test/Driver/riscv-sdata-warning.c @@ -2,11 +2,3 @@ // RUN: %clang -S --target=riscv32-unknown-elf -fpic -msmall-data-limit=8 %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-PIC-SDATA %s // CHECK-PIC-SDATA: warning: ignoring '-msmall-data-limit=' with -mcmodel=large for -fpic or RV64 - -// RUN: %clang -S --target=riscv64-unknown-elf -mcmodel=large -msmall-data-limit=8 %s 2>&1 \ -// RUN: | FileCheck -check-prefix=CHECK-RV64-LARGE-SDATA %s -// CHECK-RV64-LARGE-SDATA: warning: ignoring '-msmall-data-limit=' with -mcmodel=large for -fpic or RV64 - -// RUN: %clang -S --target=riscv64-linux-android -msmall-data-limit=8 %s 2>&1 \ -// RUN: | FileCheck -check-prefix=CHECK-RV64-LARGE-SDATA-ANDROID %s -// CHECK-RV64-LARGE-SDATA-ANDROID: warning: ignoring '-msmall-data-limit=' with -mcmodel=large for -fpic or RV64 diff --git a/clang/test/Driver/solaris-ld.c b/clang/test/Driver/solaris-ld.c index 09e6e8b4f07cf..8f7f168c38721 100644 --- a/clang/test/Driver/solaris-ld.c +++ b/clang/test/Driver/solaris-ld.c @@ -177,6 +177,7 @@ // RUN: | FileCheck %s --check-prefix=CHECK-RELOCATABLE // CHECK-RELOCATABLE: "-L // CHECK-RELOCATABLE: "-r" +// CHECK-RELOCATABLE-NOT: "-e" // CHECK-RELOCATABLE-NOT: "-l // CHECK-RELOCATABLE-NOT: /crt{{[^.]+}}.o // CHECK-RELOCATABLE-NOT: /values-{{[^.]+}}.o diff --git a/clang/test/Frontend/fixed_point_errors.cpp b/clang/test/Frontend/fixed_point_errors.cpp index 2264622a2e8c8..cdd90ceb7548f 100644 --- a/clang/test/Frontend/fixed_point_errors.cpp +++ b/clang/test/Frontend/fixed_point_errors.cpp @@ -1,18 +1,14 @@ -// RUN: %clang_cc1 -x c++ %s -verify -DWITHOUT_FIXED_POINT -// RUN: %clang_cc1 -x c++ %s -verify -ffixed-point +// RUN: %clang_cc1 -x c++ %s -verify +// RUN: %clang_cc1 -x c++ -ffixed-point %s -verify -#ifdef WITHOUT_FIXED_POINT -_Accum accum; // expected-error{{compile with '-ffixed-point' to enable fixed point types}} - // expected-error@-1{{a type specifier is required for all declarations}} -_Fract fract; // expected-error{{compile with '-ffixed-point' to enable fixed point types}} - // expected-error@-1{{a type specifier is required for all declarations}} -_Sat _Accum sat_accum; // expected-error 2{{compile with '-ffixed-point' to enable fixed point types}} - // expected-error@-1{{a type specifier is required for all declarations}} -#endif +// Name namgling is not provided for fixed point types in c++ + +_Accum accum; // expected-error{{unknown type name '_Accum'}} +_Fract fract; // expected-error{{unknown type name '_Fract'}} +_Sat _Accum sat_accum; // expected-error{{unknown type name '_Sat'}} + // expected-error@-1{{expected ';' after top level declarator}} int accum_int = 10k; // expected-error{{invalid suffix 'k' on integer constant}} int fract_int = 10r; // expected-error{{invalid suffix 'r' on integer constant}} -#ifdef WITHOUT_FIXED_POINT -float accum_flt = 0.0k; // expected-error{{invalid suffix 'k' on floating constant}} -float fract_flt = 0.0r; // expected-error{{invalid suffix 'r' on floating constant}} -#endif +float accum_flt = 10.0k; // expected-error{{invalid suffix 'k' on floating constant}} +float fract_flt = 10.0r; // expected-error{{invalid suffix 'r' on floating constant}} diff --git a/clang/test/Frontend/optimization-remark-with-hotness-new-pm.c b/clang/test/Frontend/optimization-remark-with-hotness-new-pm.c index cb1992ec4cb85..173b43ba41bfe 100644 --- a/clang/test/Frontend/optimization-remark-with-hotness-new-pm.c +++ b/clang/test/Frontend/optimization-remark-with-hotness-new-pm.c @@ -73,7 +73,7 @@ void bar(int x) { // THRESHOLD-NOT: hotness // NO_PGO: '-fdiagnostics-show-hotness' requires profile-guided optimization information // NO_PGO: '-fdiagnostics-hotness-threshold=' requires profile-guided optimization information - // expected-remark@+1 {{'foo' inlined into 'bar': always inline attribute at callsite bar:8:10; (hotness:}} + // expected-remark@+1 {{'foo' inlined into 'bar' with (cost=always): always inline attribute at callsite bar:8:10; (hotness:}} sum += foo(x, x - 2); } diff --git a/clang/test/Frontend/rewrite-includes-cli-include.c b/clang/test/Frontend/rewrite-includes-cli-include.c index 437bc2ffadf19..d63f966f79ca6 100644 --- a/clang/test/Frontend/rewrite-includes-cli-include.c +++ b/clang/test/Frontend/rewrite-includes-cli-include.c @@ -3,7 +3,6 @@ main_file_line // CHECK: {{^}}# 1 ""{{$}} // CHECK-NEXT: {{^}}# 1 "{{.*[/\\]Inputs(/|\\\\)}}rewrite-includes2.h" 1{{$}} // CHECK-NEXT: {{^}}int included_line2;{{$}} -// CHECK-NEXT: {{^}}#endif /* rewrite-includes2.h expanded by -frewrite-includes */{{$}} // CHECK-NEXT: {{^}}# 1 "" 2{{$}} // CHECK-NEXT: {{^}}# 1 "{{.*}}rewrite-includes-cli-include.c"{{$}} // CHECK-NEXT: FileCheck diff --git a/clang/test/Headers/__clang_hip_math.hip b/clang/test/Headers/__clang_hip_math.hip index fc18e14d82296..b57c38d70b14c 100644 --- a/clang/test/Headers/__clang_hip_math.hip +++ b/clang/test/Headers/__clang_hip_math.hip @@ -138,26 +138,26 @@ extern "C" __device__ uint64_t test___make_mantissa_base16(const char *p) { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[P:%.*]], align 1, !tbaa [[TBAA4]] // CHECK-NEXT: [[CMP_I:%.*]] = icmp eq i8 [[TMP0]], 48 -// CHECK-NEXT: br i1 [[CMP_I]], label [[IF_THEN_I:%.*]], label [[WHILE_COND_I30_I:%.*]] +// CHECK-NEXT: br i1 [[CMP_I]], label [[IF_THEN_I:%.*]], label [[WHILE_COND_I14_I:%.*]] // CHECK: if.then.i: // CHECK-NEXT: [[INCDEC_PTR_I:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 1 // CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[INCDEC_PTR_I]], align 1, !tbaa [[TBAA4]] -// CHECK-NEXT: switch i8 [[TMP1]], label [[WHILE_COND_I14_I:%.*]] [ -// CHECK-NEXT: i8 120, label [[WHILE_COND_I_I_PREHEADER:%.*]] -// CHECK-NEXT: i8 88, label [[WHILE_COND_I_I_PREHEADER]] +// CHECK-NEXT: switch i8 [[TMP1]], label [[WHILE_COND_I_I:%.*]] [ +// CHECK-NEXT: i8 120, label [[WHILE_COND_I30_I_PREHEADER:%.*]] +// CHECK-NEXT: i8 88, label [[WHILE_COND_I30_I_PREHEADER]] // CHECK-NEXT: ] -// CHECK: while.cond.i.i.preheader: -// CHECK-NEXT: br label [[WHILE_COND_I_I:%.*]] -// CHECK: while.cond.i.i: -// CHECK-NEXT: [[__TAGP_ADDR_0_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I_I:%.*]], [[CLEANUP_I_I:%.*]] ], [ [[INCDEC_PTR_I]], [[WHILE_COND_I_I_PREHEADER]] ] -// CHECK-NEXT: [[__R_0_I_I:%.*]] = phi i64 [ [[__R_2_I_I:%.*]], [[CLEANUP_I_I]] ], [ 0, [[WHILE_COND_I_I_PREHEADER]] ] -// CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I_I]], align 1, !tbaa [[TBAA4]] -// CHECK-NEXT: [[CMP_NOT_I_I:%.*]] = icmp eq i8 [[TMP2]], 0 -// CHECK-NEXT: br i1 [[CMP_NOT_I_I]], label [[_ZL15__MAKE_MANTISSAPKC_EXIT:%.*]], label [[WHILE_BODY_I_I:%.*]] -// CHECK: while.body.i.i: +// CHECK: while.cond.i30.i.preheader: +// CHECK-NEXT: br label [[WHILE_COND_I30_I:%.*]] +// CHECK: while.cond.i30.i: +// CHECK-NEXT: [[__TAGP_ADDR_0_I31_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I37_I:%.*]], [[CLEANUP_I36_I:%.*]] ], [ [[INCDEC_PTR_I]], [[WHILE_COND_I30_I_PREHEADER]] ] +// CHECK-NEXT: [[__R_0_I32_I:%.*]] = phi i64 [ [[__R_2_I_I:%.*]], [[CLEANUP_I36_I]] ], [ 0, [[WHILE_COND_I30_I_PREHEADER]] ] +// CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I31_I]], align 1, !tbaa [[TBAA4]] +// CHECK-NEXT: [[CMP_NOT_I33_I:%.*]] = icmp eq i8 [[TMP2]], 0 +// CHECK-NEXT: br i1 [[CMP_NOT_I33_I]], label [[_ZL15__MAKE_MANTISSAPKC_EXIT:%.*]], label [[WHILE_BODY_I34_I:%.*]] +// CHECK: while.body.i34.i: // CHECK-NEXT: [[TMP3:%.*]] = add i8 [[TMP2]], -48 -// CHECK-NEXT: [[OR_COND_I_I:%.*]] = icmp ult i8 [[TMP3]], 10 -// CHECK-NEXT: br i1 [[OR_COND_I_I]], label [[IF_END31_I_I:%.*]], label [[IF_ELSE_I_I:%.*]] +// CHECK-NEXT: [[OR_COND_I35_I:%.*]] = icmp ult i8 [[TMP3]], 10 +// CHECK-NEXT: br i1 [[OR_COND_I35_I]], label [[IF_END31_I_I:%.*]], label [[IF_ELSE_I_I:%.*]] // CHECK: if.else.i.i: // CHECK-NEXT: [[TMP4:%.*]] = add i8 [[TMP2]], -97 // CHECK-NEXT: [[OR_COND33_I_I:%.*]] = icmp ult i8 [[TMP4]], 6 @@ -165,33 +165,54 @@ extern "C" __device__ uint64_t test___make_mantissa_base16(const char *p) { // CHECK: if.else17.i.i: // CHECK-NEXT: [[TMP5:%.*]] = add i8 [[TMP2]], -65 // CHECK-NEXT: [[OR_COND34_I_I:%.*]] = icmp ult i8 [[TMP5]], 6 -// CHECK-NEXT: br i1 [[OR_COND34_I_I]], label [[IF_END31_I_I]], label [[CLEANUP_I_I]] +// CHECK-NEXT: br i1 [[OR_COND34_I_I]], label [[IF_END31_I_I]], label [[CLEANUP_I36_I]] // CHECK: if.end31.i.i: -// CHECK-NEXT: [[DOTSINK:%.*]] = phi i64 [ -48, [[WHILE_BODY_I_I]] ], [ -87, [[IF_ELSE_I_I]] ], [ -55, [[IF_ELSE17_I_I]] ] -// CHECK-NEXT: [[MUL24_I_I:%.*]] = shl i64 [[__R_0_I_I]], 4 +// CHECK-NEXT: [[DOTSINK:%.*]] = phi i64 [ -48, [[WHILE_BODY_I34_I]] ], [ -87, [[IF_ELSE_I_I]] ], [ -55, [[IF_ELSE17_I_I]] ] +// CHECK-NEXT: [[MUL24_I_I:%.*]] = shl i64 [[__R_0_I32_I]], 4 // CHECK-NEXT: [[CONV25_I_I:%.*]] = sext i8 [[TMP2]] to i64 // CHECK-NEXT: [[ADD26_I_I:%.*]] = add i64 [[MUL24_I_I]], [[DOTSINK]] // CHECK-NEXT: [[ADD28_I_I:%.*]] = add i64 [[ADD26_I_I]], [[CONV25_I_I]] +// CHECK-NEXT: [[INCDEC_PTR_I40_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I31_I]], i64 1 +// CHECK-NEXT: br label [[CLEANUP_I36_I]] +// CHECK: cleanup.i36.i: +// CHECK-NEXT: [[__TAGP_ADDR_1_I37_I]] = phi ptr [ [[INCDEC_PTR_I40_I]], [[IF_END31_I_I]] ], [ [[__TAGP_ADDR_0_I31_I]], [[IF_ELSE17_I_I]] ] +// CHECK-NEXT: [[__R_2_I_I]] = phi i64 [ [[ADD28_I_I]], [[IF_END31_I_I]] ], [ [[__R_0_I32_I]], [[IF_ELSE17_I_I]] ] +// CHECK-NEXT: [[COND_I_I:%.*]] = phi i1 [ true, [[IF_END31_I_I]] ], [ false, [[IF_ELSE17_I_I]] ] +// CHECK-NEXT: br i1 [[COND_I_I]], label [[WHILE_COND_I30_I]], label [[_ZL15__MAKE_MANTISSAPKC_EXIT]], !llvm.loop [[LOOP11]] +// CHECK: while.cond.i.i: +// CHECK-NEXT: [[__TAGP_ADDR_0_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I_I:%.*]], [[CLEANUP_I_I:%.*]] ], [ [[INCDEC_PTR_I]], [[IF_THEN_I]] ] +// CHECK-NEXT: [[__R_0_I_I:%.*]] = phi i64 [ [[__R_1_I_I:%.*]], [[CLEANUP_I_I]] ], [ 0, [[IF_THEN_I]] ] +// CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I_I]], align 1, !tbaa [[TBAA4]] +// CHECK-NEXT: [[CMP_NOT_I_I:%.*]] = icmp eq i8 [[TMP6]], 0 +// CHECK-NEXT: br i1 [[CMP_NOT_I_I]], label [[_ZL15__MAKE_MANTISSAPKC_EXIT]], label [[WHILE_BODY_I_I:%.*]] +// CHECK: while.body.i.i: +// CHECK-NEXT: [[TMP7:%.*]] = and i8 [[TMP6]], -8 +// CHECK-NEXT: [[OR_COND_I_I:%.*]] = icmp eq i8 [[TMP7]], 48 +// CHECK-NEXT: br i1 [[OR_COND_I_I]], label [[IF_THEN_I_I:%.*]], label [[CLEANUP_I_I]] +// CHECK: if.then.i.i: +// CHECK-NEXT: [[MUL_I_I:%.*]] = shl i64 [[__R_0_I_I]], 3 +// CHECK-NEXT: [[CONV5_I_I:%.*]] = sext i8 [[TMP6]] to i64 +// CHECK-NEXT: [[ADD_I_I:%.*]] = add i64 [[MUL_I_I]], -48 +// CHECK-NEXT: [[SUB_I_I:%.*]] = add i64 [[ADD_I_I]], [[CONV5_I_I]] // CHECK-NEXT: [[INCDEC_PTR_I_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I_I]], i64 1 // CHECK-NEXT: br label [[CLEANUP_I_I]] // CHECK: cleanup.i.i: -// CHECK-NEXT: [[__TAGP_ADDR_1_I_I]] = phi ptr [ [[INCDEC_PTR_I_I]], [[IF_END31_I_I]] ], [ [[__TAGP_ADDR_0_I_I]], [[IF_ELSE17_I_I]] ] -// CHECK-NEXT: [[__R_2_I_I]] = phi i64 [ [[ADD28_I_I]], [[IF_END31_I_I]] ], [ [[__R_0_I_I]], [[IF_ELSE17_I_I]] ] -// CHECK-NEXT: [[COND_I_I:%.*]] = phi i1 [ true, [[IF_END31_I_I]] ], [ false, [[IF_ELSE17_I_I]] ] -// CHECK-NEXT: br i1 [[COND_I_I]], label [[WHILE_COND_I_I]], label [[_ZL15__MAKE_MANTISSAPKC_EXIT]], !llvm.loop [[LOOP11]] +// CHECK-NEXT: [[__TAGP_ADDR_1_I_I]] = phi ptr [ [[INCDEC_PTR_I_I]], [[IF_THEN_I_I]] ], [ [[__TAGP_ADDR_0_I_I]], [[WHILE_BODY_I_I]] ] +// CHECK-NEXT: [[__R_1_I_I]] = phi i64 [ [[SUB_I_I]], [[IF_THEN_I_I]] ], [ [[__R_0_I_I]], [[WHILE_BODY_I_I]] ] +// CHECK-NEXT: br i1 [[OR_COND_I_I]], label [[WHILE_COND_I_I]], label [[_ZL15__MAKE_MANTISSAPKC_EXIT]], !llvm.loop [[LOOP7]] // CHECK: while.cond.i14.i: -// CHECK-NEXT: [[__TAGP_ADDR_0_I15_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I21_I:%.*]], [[CLEANUP_I20_I:%.*]] ], [ [[INCDEC_PTR_I]], [[IF_THEN_I]] ] -// CHECK-NEXT: [[__R_0_I16_I:%.*]] = phi i64 [ [[__R_1_I22_I:%.*]], [[CLEANUP_I20_I]] ], [ 0, [[IF_THEN_I]] ] -// CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I15_I]], align 1, !tbaa [[TBAA4]] -// CHECK-NEXT: [[CMP_NOT_I17_I:%.*]] = icmp eq i8 [[TMP6]], 0 +// CHECK-NEXT: [[__TAGP_ADDR_0_I15_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I21_I:%.*]], [[CLEANUP_I20_I:%.*]] ], [ [[P]], [[ENTRY:%.*]] ] +// CHECK-NEXT: [[__R_0_I16_I:%.*]] = phi i64 [ [[__R_1_I22_I:%.*]], [[CLEANUP_I20_I]] ], [ 0, [[ENTRY]] ] +// CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I15_I]], align 1, !tbaa [[TBAA4]] +// CHECK-NEXT: [[CMP_NOT_I17_I:%.*]] = icmp eq i8 [[TMP8]], 0 // CHECK-NEXT: br i1 [[CMP_NOT_I17_I]], label [[_ZL15__MAKE_MANTISSAPKC_EXIT]], label [[WHILE_BODY_I18_I:%.*]] // CHECK: while.body.i18.i: -// CHECK-NEXT: [[TMP7:%.*]] = and i8 [[TMP6]], -8 -// CHECK-NEXT: [[OR_COND_I19_I:%.*]] = icmp eq i8 [[TMP7]], 48 +// CHECK-NEXT: [[TMP9:%.*]] = add i8 [[TMP8]], -48 +// CHECK-NEXT: [[OR_COND_I19_I:%.*]] = icmp ult i8 [[TMP9]], 10 // CHECK-NEXT: br i1 [[OR_COND_I19_I]], label [[IF_THEN_I24_I:%.*]], label [[CLEANUP_I20_I]] // CHECK: if.then.i24.i: -// CHECK-NEXT: [[MUL_I25_I:%.*]] = shl i64 [[__R_0_I16_I]], 3 -// CHECK-NEXT: [[CONV5_I26_I:%.*]] = sext i8 [[TMP6]] to i64 +// CHECK-NEXT: [[MUL_I25_I:%.*]] = mul i64 [[__R_0_I16_I]], 10 +// CHECK-NEXT: [[CONV5_I26_I:%.*]] = sext i8 [[TMP8]] to i64 // CHECK-NEXT: [[ADD_I27_I:%.*]] = add i64 [[MUL_I25_I]], -48 // CHECK-NEXT: [[SUB_I28_I:%.*]] = add i64 [[ADD_I27_I]], [[CONV5_I26_I]] // CHECK-NEXT: [[INCDEC_PTR_I29_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I15_I]], i64 1 @@ -199,30 +220,9 @@ extern "C" __device__ uint64_t test___make_mantissa_base16(const char *p) { // CHECK: cleanup.i20.i: // CHECK-NEXT: [[__TAGP_ADDR_1_I21_I]] = phi ptr [ [[INCDEC_PTR_I29_I]], [[IF_THEN_I24_I]] ], [ [[__TAGP_ADDR_0_I15_I]], [[WHILE_BODY_I18_I]] ] // CHECK-NEXT: [[__R_1_I22_I]] = phi i64 [ [[SUB_I28_I]], [[IF_THEN_I24_I]] ], [ [[__R_0_I16_I]], [[WHILE_BODY_I18_I]] ] -// CHECK-NEXT: br i1 [[OR_COND_I19_I]], label [[WHILE_COND_I14_I]], label [[_ZL15__MAKE_MANTISSAPKC_EXIT]], !llvm.loop [[LOOP7]] -// CHECK: while.cond.i30.i: -// CHECK-NEXT: [[__TAGP_ADDR_0_I31_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I37_I:%.*]], [[CLEANUP_I36_I:%.*]] ], [ [[P]], [[ENTRY:%.*]] ] -// CHECK-NEXT: [[__R_0_I32_I:%.*]] = phi i64 [ [[__R_1_I38_I:%.*]], [[CLEANUP_I36_I]] ], [ 0, [[ENTRY]] ] -// CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I31_I]], align 1, !tbaa [[TBAA4]] -// CHECK-NEXT: [[CMP_NOT_I33_I:%.*]] = icmp eq i8 [[TMP8]], 0 -// CHECK-NEXT: br i1 [[CMP_NOT_I33_I]], label [[_ZL15__MAKE_MANTISSAPKC_EXIT]], label [[WHILE_BODY_I34_I:%.*]] -// CHECK: while.body.i34.i: -// CHECK-NEXT: [[TMP9:%.*]] = add i8 [[TMP8]], -48 -// CHECK-NEXT: [[OR_COND_I35_I:%.*]] = icmp ult i8 [[TMP9]], 10 -// CHECK-NEXT: br i1 [[OR_COND_I35_I]], label [[IF_THEN_I40_I:%.*]], label [[CLEANUP_I36_I]] -// CHECK: if.then.i40.i: -// CHECK-NEXT: [[MUL_I41_I:%.*]] = mul i64 [[__R_0_I32_I]], 10 -// CHECK-NEXT: [[CONV5_I42_I:%.*]] = sext i8 [[TMP8]] to i64 -// CHECK-NEXT: [[ADD_I43_I:%.*]] = add i64 [[MUL_I41_I]], -48 -// CHECK-NEXT: [[SUB_I44_I:%.*]] = add i64 [[ADD_I43_I]], [[CONV5_I42_I]] -// CHECK-NEXT: [[INCDEC_PTR_I45_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I31_I]], i64 1 -// CHECK-NEXT: br label [[CLEANUP_I36_I]] -// CHECK: cleanup.i36.i: -// CHECK-NEXT: [[__TAGP_ADDR_1_I37_I]] = phi ptr [ [[INCDEC_PTR_I45_I]], [[IF_THEN_I40_I]] ], [ [[__TAGP_ADDR_0_I31_I]], [[WHILE_BODY_I34_I]] ] -// CHECK-NEXT: [[__R_1_I38_I]] = phi i64 [ [[SUB_I44_I]], [[IF_THEN_I40_I]] ], [ [[__R_0_I32_I]], [[WHILE_BODY_I34_I]] ] -// CHECK-NEXT: br i1 [[OR_COND_I35_I]], label [[WHILE_COND_I30_I]], label [[_ZL15__MAKE_MANTISSAPKC_EXIT]], !llvm.loop [[LOOP10]] +// CHECK-NEXT: br i1 [[OR_COND_I19_I]], label [[WHILE_COND_I14_I]], label [[_ZL15__MAKE_MANTISSAPKC_EXIT]], !llvm.loop [[LOOP10]] // CHECK: _ZL15__make_mantissaPKc.exit: -// CHECK-NEXT: [[RETVAL_0_I:%.*]] = phi i64 [ 0, [[CLEANUP_I20_I]] ], [ [[__R_0_I16_I]], [[WHILE_COND_I14_I]] ], [ 0, [[CLEANUP_I_I]] ], [ [[__R_0_I_I]], [[WHILE_COND_I_I]] ], [ 0, [[CLEANUP_I36_I]] ], [ [[__R_0_I32_I]], [[WHILE_COND_I30_I]] ] +// CHECK-NEXT: [[RETVAL_0_I:%.*]] = phi i64 [ 0, [[CLEANUP_I_I]] ], [ [[__R_0_I_I]], [[WHILE_COND_I_I]] ], [ 0, [[CLEANUP_I36_I]] ], [ [[__R_0_I32_I]], [[WHILE_COND_I30_I]] ], [ 0, [[CLEANUP_I20_I]] ], [ [[__R_0_I16_I]], [[WHILE_COND_I14_I]] ] // CHECK-NEXT: ret i64 [[RETVAL_0_I]] // extern "C" __device__ uint64_t test___make_mantissa(const char *p) { @@ -231,8 +231,8 @@ extern "C" __device__ uint64_t test___make_mantissa(const char *p) { // CHECK-LABEL: @test_abs( // CHECK-NEXT: entry: -// CHECK-NEXT: [[ABS_I:%.*]] = tail call noundef i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true) -// CHECK-NEXT: ret i32 [[ABS_I]] +// CHECK-NEXT: [[TMP0:%.*]] = tail call noundef i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true) +// CHECK-NEXT: ret i32 [[TMP0]] // extern "C" __device__ int test_abs(int x) { return abs(x); @@ -240,8 +240,8 @@ extern "C" __device__ int test_abs(int x) { // CHECK-LABEL: @test_labs( // CHECK-NEXT: entry: -// CHECK-NEXT: [[ABS_I:%.*]] = tail call noundef i64 @llvm.abs.i64(i64 [[X:%.*]], i1 true) -// CHECK-NEXT: ret i64 [[ABS_I]] +// CHECK-NEXT: [[TMP0:%.*]] = tail call noundef i64 @llvm.abs.i64(i64 [[X:%.*]], i1 true) +// CHECK-NEXT: ret i64 [[TMP0]] // extern "C" __device__ long test_labs(long x) { return labs(x); @@ -249,8 +249,8 @@ extern "C" __device__ long test_labs(long x) { // CHECK-LABEL: @test_llabs( // CHECK-NEXT: entry: -// CHECK-NEXT: [[ABS_I:%.*]] = tail call noundef i64 @llvm.abs.i64(i64 [[X:%.*]], i1 true) -// CHECK-NEXT: ret i64 [[ABS_I]] +// CHECK-NEXT: [[TMP0:%.*]] = tail call noundef i64 @llvm.abs.i64(i64 [[X:%.*]], i1 true) +// CHECK-NEXT: ret i64 [[TMP0]] // extern "C" __device__ long long test_llabs(long x) { return llabs(x); @@ -649,8 +649,8 @@ extern "C" __device__ double test_copysign(double x, double y) { // // APPROX-LABEL: @test_cosf( // APPROX-NEXT: entry: -// APPROX-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_native_cos_f32(float noundef [[X:%.*]]) #[[ATTR16:[0-9]+]] -// APPROX-NEXT: ret float [[CALL_I_I]] +// APPROX-NEXT: [[CALL_I1:%.*]] = tail call contract noundef float @__ocml_native_cos_f32(float noundef [[X:%.*]]) #[[ATTR16:[0-9]+]] +// APPROX-NEXT: ret float [[CALL_I1]] // extern "C" __device__ float test_cosf(float x) { return cosf(x); @@ -1670,30 +1670,30 @@ extern "C" __device__ double test_j1(double x) { // DEFAULT-NEXT: i32 1, label [[IF_THEN2_I:%.*]] // DEFAULT-NEXT: ] // DEFAULT: if.then.i: -// DEFAULT-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_j0_f32(float noundef [[Y:%.*]]) #[[ATTR16]] +// DEFAULT-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef float @__ocml_j0_f32(float noundef [[Y:%.*]]) #[[ATTR16]] // DEFAULT-NEXT: br label [[_ZL3JNFIF_EXIT:%.*]] // DEFAULT: if.then2.i: -// DEFAULT-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR16]] +// DEFAULT-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR16]] // DEFAULT-NEXT: br label [[_ZL3JNFIF_EXIT]] // DEFAULT: if.end4.i: -// DEFAULT-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef float @__ocml_j0_f32(float noundef [[Y]]) #[[ATTR16]] -// DEFAULT-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR16]] -// DEFAULT-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 -// DEFAULT-NEXT: br i1 [[CMP723_I]], label [[FOR_BODY_I:%.*]], label [[_ZL3JNFIF_EXIT]] +// DEFAULT-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_j0_f32(float noundef [[Y]]) #[[ATTR16]] +// DEFAULT-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR16]] +// DEFAULT-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 +// DEFAULT-NEXT: br i1 [[CMP7_I1]], label [[FOR_BODY_I:%.*]], label [[_ZL3JNFIF_EXIT]] // DEFAULT: for.body.i: -// DEFAULT-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ] -// DEFAULT-NEXT: [[__X1_025_I:%.*]] = phi float [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I22_I]], [[IF_END4_I]] ] -// DEFAULT-NEXT: [[__X0_024_I:%.*]] = phi float [ [[__X1_025_I]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ] -// DEFAULT-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 +// DEFAULT-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ] +// DEFAULT-NEXT: [[__X1_0_I3:%.*]] = phi float [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ] +// DEFAULT-NEXT: [[__X0_0_I2:%.*]] = phi float [ [[__X1_0_I3]], [[FOR_BODY_I]] ], [ [[CALL_I_I]], [[IF_END4_I]] ] +// DEFAULT-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 // DEFAULT-NEXT: [[CONV_I:%.*]] = sitofp i32 [[MUL_I]] to float // DEFAULT-NEXT: [[DIV_I:%.*]] = fdiv contract float [[CONV_I]], [[Y]] -// DEFAULT-NEXT: [[MUL8_I:%.*]] = fmul contract float [[__X1_025_I]], [[DIV_I]] -// DEFAULT-NEXT: [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_024_I]] -// DEFAULT-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 -// DEFAULT-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// DEFAULT-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZL3JNFIF_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP14:![0-9]+]] +// DEFAULT-NEXT: [[MUL8_I:%.*]] = fmul contract float [[__X1_0_I3]], [[DIV_I]] +// DEFAULT-NEXT: [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_0_I2]] +// DEFAULT-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 +// DEFAULT-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// DEFAULT-NEXT: br i1 [[EXITCOND_NOT]], label [[_ZL3JNFIF_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP14:![0-9]+]] // DEFAULT: _ZL3jnfif.exit: -// DEFAULT-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I_I]], [[IF_THEN_I]] ], [ [[CALL_I20_I]], [[IF_THEN2_I]] ], [ [[CALL_I22_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ] +// DEFAULT-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I20_I]], [[IF_THEN_I]] ], [ [[CALL_I22_I]], [[IF_THEN2_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ] // DEFAULT-NEXT: ret float [[RETVAL_0_I]] // // FINITEONLY-LABEL: @test_jnf( @@ -1703,30 +1703,30 @@ extern "C" __device__ double test_j1(double x) { // FINITEONLY-NEXT: i32 1, label [[IF_THEN2_I:%.*]] // FINITEONLY-NEXT: ] // FINITEONLY: if.then.i: -// FINITEONLY-NEXT: [[CALL_I_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_j0_f32(float noundef nofpclass(nan inf) [[Y:%.*]]) #[[ATTR16]] +// FINITEONLY-NEXT: [[CALL_I20_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_j0_f32(float noundef nofpclass(nan inf) [[Y:%.*]]) #[[ATTR16]] // FINITEONLY-NEXT: br label [[_ZL3JNFIF_EXIT:%.*]] // FINITEONLY: if.then2.i: -// FINITEONLY-NEXT: [[CALL_I20_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_j1_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR16]] +// FINITEONLY-NEXT: [[CALL_I22_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_j1_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR16]] // FINITEONLY-NEXT: br label [[_ZL3JNFIF_EXIT]] // FINITEONLY: if.end4.i: -// FINITEONLY-NEXT: [[CALL_I21_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_j0_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR16]] -// FINITEONLY-NEXT: [[CALL_I22_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_j1_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR16]] -// FINITEONLY-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 -// FINITEONLY-NEXT: br i1 [[CMP723_I]], label [[FOR_BODY_I:%.*]], label [[_ZL3JNFIF_EXIT]] +// FINITEONLY-NEXT: [[CALL_I_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_j0_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR16]] +// FINITEONLY-NEXT: [[CALL_I21_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_j1_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR16]] +// FINITEONLY-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 +// FINITEONLY-NEXT: br i1 [[CMP7_I1]], label [[FOR_BODY_I:%.*]], label [[_ZL3JNFIF_EXIT]] // FINITEONLY: for.body.i: -// FINITEONLY-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ] -// FINITEONLY-NEXT: [[__X1_025_I:%.*]] = phi float [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I22_I]], [[IF_END4_I]] ] -// FINITEONLY-NEXT: [[__X0_024_I:%.*]] = phi float [ [[__X1_025_I]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ] -// FINITEONLY-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 +// FINITEONLY-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ] +// FINITEONLY-NEXT: [[__X1_0_I3:%.*]] = phi float [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ] +// FINITEONLY-NEXT: [[__X0_0_I2:%.*]] = phi float [ [[__X1_0_I3]], [[FOR_BODY_I]] ], [ [[CALL_I_I]], [[IF_END4_I]] ] +// FINITEONLY-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 // FINITEONLY-NEXT: [[CONV_I:%.*]] = sitofp i32 [[MUL_I]] to float // FINITEONLY-NEXT: [[DIV_I:%.*]] = fdiv nnan ninf contract float [[CONV_I]], [[Y]] -// FINITEONLY-NEXT: [[MUL8_I:%.*]] = fmul nnan ninf contract float [[__X1_025_I]], [[DIV_I]] -// FINITEONLY-NEXT: [[SUB_I]] = fsub nnan ninf contract float [[MUL8_I]], [[__X0_024_I]] -// FINITEONLY-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 -// FINITEONLY-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// FINITEONLY-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZL3JNFIF_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP14:![0-9]+]] +// FINITEONLY-NEXT: [[MUL8_I:%.*]] = fmul nnan ninf contract float [[__X1_0_I3]], [[DIV_I]] +// FINITEONLY-NEXT: [[SUB_I]] = fsub nnan ninf contract float [[MUL8_I]], [[__X0_0_I2]] +// FINITEONLY-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 +// FINITEONLY-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// FINITEONLY-NEXT: br i1 [[EXITCOND_NOT]], label [[_ZL3JNFIF_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP14:![0-9]+]] // FINITEONLY: _ZL3jnfif.exit: -// FINITEONLY-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I_I]], [[IF_THEN_I]] ], [ [[CALL_I20_I]], [[IF_THEN2_I]] ], [ [[CALL_I22_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ] +// FINITEONLY-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I20_I]], [[IF_THEN_I]] ], [ [[CALL_I22_I]], [[IF_THEN2_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ] // FINITEONLY-NEXT: ret float [[RETVAL_0_I]] // // APPROX-LABEL: @test_jnf( @@ -1736,30 +1736,30 @@ extern "C" __device__ double test_j1(double x) { // APPROX-NEXT: i32 1, label [[IF_THEN2_I:%.*]] // APPROX-NEXT: ] // APPROX: if.then.i: -// APPROX-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_j0_f32(float noundef [[Y:%.*]]) #[[ATTR16]] +// APPROX-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef float @__ocml_j0_f32(float noundef [[Y:%.*]]) #[[ATTR16]] // APPROX-NEXT: br label [[_ZL3JNFIF_EXIT:%.*]] // APPROX: if.then2.i: -// APPROX-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR16]] +// APPROX-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR16]] // APPROX-NEXT: br label [[_ZL3JNFIF_EXIT]] // APPROX: if.end4.i: -// APPROX-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef float @__ocml_j0_f32(float noundef [[Y]]) #[[ATTR16]] -// APPROX-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR16]] -// APPROX-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 -// APPROX-NEXT: br i1 [[CMP723_I]], label [[FOR_BODY_I:%.*]], label [[_ZL3JNFIF_EXIT]] +// APPROX-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_j0_f32(float noundef [[Y]]) #[[ATTR16]] +// APPROX-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR16]] +// APPROX-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 +// APPROX-NEXT: br i1 [[CMP7_I1]], label [[FOR_BODY_I:%.*]], label [[_ZL3JNFIF_EXIT]] // APPROX: for.body.i: -// APPROX-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ] -// APPROX-NEXT: [[__X1_025_I:%.*]] = phi float [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I22_I]], [[IF_END4_I]] ] -// APPROX-NEXT: [[__X0_024_I:%.*]] = phi float [ [[__X1_025_I]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ] -// APPROX-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 +// APPROX-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ] +// APPROX-NEXT: [[__X1_0_I3:%.*]] = phi float [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ] +// APPROX-NEXT: [[__X0_0_I2:%.*]] = phi float [ [[__X1_0_I3]], [[FOR_BODY_I]] ], [ [[CALL_I_I]], [[IF_END4_I]] ] +// APPROX-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 // APPROX-NEXT: [[CONV_I:%.*]] = sitofp i32 [[MUL_I]] to float // APPROX-NEXT: [[DIV_I:%.*]] = fdiv contract float [[CONV_I]], [[Y]] -// APPROX-NEXT: [[MUL8_I:%.*]] = fmul contract float [[__X1_025_I]], [[DIV_I]] -// APPROX-NEXT: [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_024_I]] -// APPROX-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 -// APPROX-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// APPROX-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZL3JNFIF_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP14:![0-9]+]] +// APPROX-NEXT: [[MUL8_I:%.*]] = fmul contract float [[__X1_0_I3]], [[DIV_I]] +// APPROX-NEXT: [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_0_I2]] +// APPROX-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 +// APPROX-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// APPROX-NEXT: br i1 [[EXITCOND_NOT]], label [[_ZL3JNFIF_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP14:![0-9]+]] // APPROX: _ZL3jnfif.exit: -// APPROX-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I_I]], [[IF_THEN_I]] ], [ [[CALL_I20_I]], [[IF_THEN2_I]] ], [ [[CALL_I22_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ] +// APPROX-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I20_I]], [[IF_THEN_I]] ], [ [[CALL_I22_I]], [[IF_THEN2_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ] // APPROX-NEXT: ret float [[RETVAL_0_I]] // extern "C" __device__ float test_jnf(int x, float y) { @@ -1773,30 +1773,30 @@ extern "C" __device__ float test_jnf(int x, float y) { // DEFAULT-NEXT: i32 1, label [[IF_THEN2_I:%.*]] // DEFAULT-NEXT: ] // DEFAULT: if.then.i: -// DEFAULT-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef double @__ocml_j0_f64(double noundef [[Y:%.*]]) #[[ATTR16]] +// DEFAULT-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef double @__ocml_j0_f64(double noundef [[Y:%.*]]) #[[ATTR16]] // DEFAULT-NEXT: br label [[_ZL2JNID_EXIT:%.*]] // DEFAULT: if.then2.i: -// DEFAULT-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR16]] +// DEFAULT-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR16]] // DEFAULT-NEXT: br label [[_ZL2JNID_EXIT]] // DEFAULT: if.end4.i: -// DEFAULT-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef double @__ocml_j0_f64(double noundef [[Y]]) #[[ATTR16]] -// DEFAULT-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR16]] -// DEFAULT-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 -// DEFAULT-NEXT: br i1 [[CMP723_I]], label [[FOR_BODY_I:%.*]], label [[_ZL2JNID_EXIT]] +// DEFAULT-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef double @__ocml_j0_f64(double noundef [[Y]]) #[[ATTR16]] +// DEFAULT-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR16]] +// DEFAULT-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 +// DEFAULT-NEXT: br i1 [[CMP7_I1]], label [[FOR_BODY_I:%.*]], label [[_ZL2JNID_EXIT]] // DEFAULT: for.body.i: -// DEFAULT-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ] -// DEFAULT-NEXT: [[__X1_025_I:%.*]] = phi double [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I22_I]], [[IF_END4_I]] ] -// DEFAULT-NEXT: [[__X0_024_I:%.*]] = phi double [ [[__X1_025_I]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ] -// DEFAULT-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 +// DEFAULT-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ] +// DEFAULT-NEXT: [[__X1_0_I3:%.*]] = phi double [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ] +// DEFAULT-NEXT: [[__X0_0_I2:%.*]] = phi double [ [[__X1_0_I3]], [[FOR_BODY_I]] ], [ [[CALL_I_I]], [[IF_END4_I]] ] +// DEFAULT-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 // DEFAULT-NEXT: [[CONV_I:%.*]] = sitofp i32 [[MUL_I]] to double // DEFAULT-NEXT: [[DIV_I:%.*]] = fdiv contract double [[CONV_I]], [[Y]] -// DEFAULT-NEXT: [[MUL8_I:%.*]] = fmul contract double [[__X1_025_I]], [[DIV_I]] -// DEFAULT-NEXT: [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_024_I]] -// DEFAULT-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 -// DEFAULT-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// DEFAULT-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZL2JNID_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP15:![0-9]+]] +// DEFAULT-NEXT: [[MUL8_I:%.*]] = fmul contract double [[__X1_0_I3]], [[DIV_I]] +// DEFAULT-NEXT: [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_0_I2]] +// DEFAULT-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 +// DEFAULT-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// DEFAULT-NEXT: br i1 [[EXITCOND_NOT]], label [[_ZL2JNID_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP15:![0-9]+]] // DEFAULT: _ZL2jnid.exit: -// DEFAULT-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I_I]], [[IF_THEN_I]] ], [ [[CALL_I20_I]], [[IF_THEN2_I]] ], [ [[CALL_I22_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ] +// DEFAULT-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I20_I]], [[IF_THEN_I]] ], [ [[CALL_I22_I]], [[IF_THEN2_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ] // DEFAULT-NEXT: ret double [[RETVAL_0_I]] // // FINITEONLY-LABEL: @test_jn( @@ -1806,30 +1806,30 @@ extern "C" __device__ float test_jnf(int x, float y) { // FINITEONLY-NEXT: i32 1, label [[IF_THEN2_I:%.*]] // FINITEONLY-NEXT: ] // FINITEONLY: if.then.i: -// FINITEONLY-NEXT: [[CALL_I_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_j0_f64(double noundef nofpclass(nan inf) [[Y:%.*]]) #[[ATTR16]] +// FINITEONLY-NEXT: [[CALL_I20_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_j0_f64(double noundef nofpclass(nan inf) [[Y:%.*]]) #[[ATTR16]] // FINITEONLY-NEXT: br label [[_ZL2JNID_EXIT:%.*]] // FINITEONLY: if.then2.i: -// FINITEONLY-NEXT: [[CALL_I20_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_j1_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR16]] +// FINITEONLY-NEXT: [[CALL_I22_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_j1_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR16]] // FINITEONLY-NEXT: br label [[_ZL2JNID_EXIT]] // FINITEONLY: if.end4.i: -// FINITEONLY-NEXT: [[CALL_I21_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_j0_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR16]] -// FINITEONLY-NEXT: [[CALL_I22_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_j1_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR16]] -// FINITEONLY-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 -// FINITEONLY-NEXT: br i1 [[CMP723_I]], label [[FOR_BODY_I:%.*]], label [[_ZL2JNID_EXIT]] +// FINITEONLY-NEXT: [[CALL_I_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_j0_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR16]] +// FINITEONLY-NEXT: [[CALL_I21_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_j1_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR16]] +// FINITEONLY-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 +// FINITEONLY-NEXT: br i1 [[CMP7_I1]], label [[FOR_BODY_I:%.*]], label [[_ZL2JNID_EXIT]] // FINITEONLY: for.body.i: -// FINITEONLY-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ] -// FINITEONLY-NEXT: [[__X1_025_I:%.*]] = phi double [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I22_I]], [[IF_END4_I]] ] -// FINITEONLY-NEXT: [[__X0_024_I:%.*]] = phi double [ [[__X1_025_I]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ] -// FINITEONLY-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 +// FINITEONLY-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ] +// FINITEONLY-NEXT: [[__X1_0_I3:%.*]] = phi double [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ] +// FINITEONLY-NEXT: [[__X0_0_I2:%.*]] = phi double [ [[__X1_0_I3]], [[FOR_BODY_I]] ], [ [[CALL_I_I]], [[IF_END4_I]] ] +// FINITEONLY-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 // FINITEONLY-NEXT: [[CONV_I:%.*]] = sitofp i32 [[MUL_I]] to double // FINITEONLY-NEXT: [[DIV_I:%.*]] = fdiv nnan ninf contract double [[CONV_I]], [[Y]] -// FINITEONLY-NEXT: [[MUL8_I:%.*]] = fmul nnan ninf contract double [[__X1_025_I]], [[DIV_I]] -// FINITEONLY-NEXT: [[SUB_I]] = fsub nnan ninf contract double [[MUL8_I]], [[__X0_024_I]] -// FINITEONLY-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 -// FINITEONLY-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// FINITEONLY-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZL2JNID_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP15:![0-9]+]] +// FINITEONLY-NEXT: [[MUL8_I:%.*]] = fmul nnan ninf contract double [[__X1_0_I3]], [[DIV_I]] +// FINITEONLY-NEXT: [[SUB_I]] = fsub nnan ninf contract double [[MUL8_I]], [[__X0_0_I2]] +// FINITEONLY-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 +// FINITEONLY-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// FINITEONLY-NEXT: br i1 [[EXITCOND_NOT]], label [[_ZL2JNID_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP15:![0-9]+]] // FINITEONLY: _ZL2jnid.exit: -// FINITEONLY-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I_I]], [[IF_THEN_I]] ], [ [[CALL_I20_I]], [[IF_THEN2_I]] ], [ [[CALL_I22_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ] +// FINITEONLY-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I20_I]], [[IF_THEN_I]] ], [ [[CALL_I22_I]], [[IF_THEN2_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ] // FINITEONLY-NEXT: ret double [[RETVAL_0_I]] // // APPROX-LABEL: @test_jn( @@ -1839,30 +1839,30 @@ extern "C" __device__ float test_jnf(int x, float y) { // APPROX-NEXT: i32 1, label [[IF_THEN2_I:%.*]] // APPROX-NEXT: ] // APPROX: if.then.i: -// APPROX-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef double @__ocml_j0_f64(double noundef [[Y:%.*]]) #[[ATTR16]] +// APPROX-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef double @__ocml_j0_f64(double noundef [[Y:%.*]]) #[[ATTR16]] // APPROX-NEXT: br label [[_ZL2JNID_EXIT:%.*]] // APPROX: if.then2.i: -// APPROX-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR16]] +// APPROX-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR16]] // APPROX-NEXT: br label [[_ZL2JNID_EXIT]] // APPROX: if.end4.i: -// APPROX-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef double @__ocml_j0_f64(double noundef [[Y]]) #[[ATTR16]] -// APPROX-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR16]] -// APPROX-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 -// APPROX-NEXT: br i1 [[CMP723_I]], label [[FOR_BODY_I:%.*]], label [[_ZL2JNID_EXIT]] +// APPROX-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef double @__ocml_j0_f64(double noundef [[Y]]) #[[ATTR16]] +// APPROX-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR16]] +// APPROX-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 +// APPROX-NEXT: br i1 [[CMP7_I1]], label [[FOR_BODY_I:%.*]], label [[_ZL2JNID_EXIT]] // APPROX: for.body.i: -// APPROX-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ] -// APPROX-NEXT: [[__X1_025_I:%.*]] = phi double [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I22_I]], [[IF_END4_I]] ] -// APPROX-NEXT: [[__X0_024_I:%.*]] = phi double [ [[__X1_025_I]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ] -// APPROX-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 +// APPROX-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ] +// APPROX-NEXT: [[__X1_0_I3:%.*]] = phi double [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ] +// APPROX-NEXT: [[__X0_0_I2:%.*]] = phi double [ [[__X1_0_I3]], [[FOR_BODY_I]] ], [ [[CALL_I_I]], [[IF_END4_I]] ] +// APPROX-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 // APPROX-NEXT: [[CONV_I:%.*]] = sitofp i32 [[MUL_I]] to double // APPROX-NEXT: [[DIV_I:%.*]] = fdiv contract double [[CONV_I]], [[Y]] -// APPROX-NEXT: [[MUL8_I:%.*]] = fmul contract double [[__X1_025_I]], [[DIV_I]] -// APPROX-NEXT: [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_024_I]] -// APPROX-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 -// APPROX-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// APPROX-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZL2JNID_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP15:![0-9]+]] +// APPROX-NEXT: [[MUL8_I:%.*]] = fmul contract double [[__X1_0_I3]], [[DIV_I]] +// APPROX-NEXT: [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_0_I2]] +// APPROX-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 +// APPROX-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// APPROX-NEXT: br i1 [[EXITCOND_NOT]], label [[_ZL2JNID_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP15:![0-9]+]] // APPROX: _ZL2jnid.exit: -// APPROX-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I_I]], [[IF_THEN_I]] ], [ [[CALL_I20_I]], [[IF_THEN2_I]] ], [ [[CALL_I22_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ] +// APPROX-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I20_I]], [[IF_THEN_I]] ], [ [[CALL_I22_I]], [[IF_THEN2_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ] // APPROX-NEXT: ret double [[RETVAL_0_I]] // extern "C" __device__ double test_jn(int x, double y) { @@ -2364,26 +2364,26 @@ extern "C" __device__ double test_modf(double x, double* y) { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[TAG:%.*]], align 1, !tbaa [[TBAA4]] // CHECK-NEXT: [[CMP_I_I:%.*]] = icmp eq i8 [[TMP0]], 48 -// CHECK-NEXT: br i1 [[CMP_I_I]], label [[IF_THEN_I_I:%.*]], label [[WHILE_COND_I30_I_I:%.*]] +// CHECK-NEXT: br i1 [[CMP_I_I]], label [[IF_THEN_I_I:%.*]], label [[WHILE_COND_I14_I_I:%.*]] // CHECK: if.then.i.i: // CHECK-NEXT: [[INCDEC_PTR_I_I:%.*]] = getelementptr inbounds i8, ptr [[TAG]], i64 1 // CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[TBAA4]] -// CHECK-NEXT: switch i8 [[TMP1]], label [[WHILE_COND_I14_I_I:%.*]] [ -// CHECK-NEXT: i8 120, label [[WHILE_COND_I_I_I_PREHEADER:%.*]] -// CHECK-NEXT: i8 88, label [[WHILE_COND_I_I_I_PREHEADER]] +// CHECK-NEXT: switch i8 [[TMP1]], label [[WHILE_COND_I_I_I:%.*]] [ +// CHECK-NEXT: i8 120, label [[WHILE_COND_I30_I_I_PREHEADER:%.*]] +// CHECK-NEXT: i8 88, label [[WHILE_COND_I30_I_I_PREHEADER]] // CHECK-NEXT: ] -// CHECK: while.cond.i.i.i.preheader: -// CHECK-NEXT: br label [[WHILE_COND_I_I_I:%.*]] -// CHECK: while.cond.i.i.i: -// CHECK-NEXT: [[__TAGP_ADDR_0_I_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I_I_I:%.*]], [[CLEANUP_I_I_I:%.*]] ], [ [[INCDEC_PTR_I_I]], [[WHILE_COND_I_I_I_PREHEADER]] ] -// CHECK-NEXT: [[__R_0_I_I_I:%.*]] = phi i64 [ [[__R_2_I_I_I:%.*]], [[CLEANUP_I_I_I]] ], [ 0, [[WHILE_COND_I_I_I_PREHEADER]] ] -// CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I_I_I]], align 1, !tbaa [[TBAA4]] -// CHECK-NEXT: [[CMP_NOT_I_I_I:%.*]] = icmp eq i8 [[TMP2]], 0 -// CHECK-NEXT: br i1 [[CMP_NOT_I_I_I]], label [[_ZL4NANFPKC_EXIT:%.*]], label [[WHILE_BODY_I_I_I:%.*]] -// CHECK: while.body.i.i.i: +// CHECK: while.cond.i30.i.i.preheader: +// CHECK-NEXT: br label [[WHILE_COND_I30_I_I:%.*]] +// CHECK: while.cond.i30.i.i: +// CHECK-NEXT: [[__TAGP_ADDR_0_I31_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I37_I_I:%.*]], [[CLEANUP_I36_I_I:%.*]] ], [ [[INCDEC_PTR_I_I]], [[WHILE_COND_I30_I_I_PREHEADER]] ] +// CHECK-NEXT: [[__R_0_I32_I_I:%.*]] = phi i64 [ [[__R_2_I_I_I:%.*]], [[CLEANUP_I36_I_I]] ], [ 0, [[WHILE_COND_I30_I_I_PREHEADER]] ] +// CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I31_I_I]], align 1, !tbaa [[TBAA4]] +// CHECK-NEXT: [[CMP_NOT_I33_I_I:%.*]] = icmp eq i8 [[TMP2]], 0 +// CHECK-NEXT: br i1 [[CMP_NOT_I33_I_I]], label [[_ZL4NANFPKC_EXIT:%.*]], label [[WHILE_BODY_I34_I_I:%.*]] +// CHECK: while.body.i34.i.i: // CHECK-NEXT: [[TMP3:%.*]] = add i8 [[TMP2]], -48 -// CHECK-NEXT: [[OR_COND_I_I_I:%.*]] = icmp ult i8 [[TMP3]], 10 -// CHECK-NEXT: br i1 [[OR_COND_I_I_I]], label [[IF_END31_I_I_I:%.*]], label [[IF_ELSE_I_I_I:%.*]] +// CHECK-NEXT: [[OR_COND_I35_I_I:%.*]] = icmp ult i8 [[TMP3]], 10 +// CHECK-NEXT: br i1 [[OR_COND_I35_I_I]], label [[IF_END31_I_I_I:%.*]], label [[IF_ELSE_I_I_I:%.*]] // CHECK: if.else.i.i.i: // CHECK-NEXT: [[TMP4:%.*]] = add i8 [[TMP2]], -97 // CHECK-NEXT: [[OR_COND33_I_I_I:%.*]] = icmp ult i8 [[TMP4]], 6 @@ -2391,33 +2391,54 @@ extern "C" __device__ double test_modf(double x, double* y) { // CHECK: if.else17.i.i.i: // CHECK-NEXT: [[TMP5:%.*]] = add i8 [[TMP2]], -65 // CHECK-NEXT: [[OR_COND34_I_I_I:%.*]] = icmp ult i8 [[TMP5]], 6 -// CHECK-NEXT: br i1 [[OR_COND34_I_I_I]], label [[IF_END31_I_I_I]], label [[CLEANUP_I_I_I]] +// CHECK-NEXT: br i1 [[OR_COND34_I_I_I]], label [[IF_END31_I_I_I]], label [[CLEANUP_I36_I_I]] // CHECK: if.end31.i.i.i: -// CHECK-NEXT: [[DOTSINK:%.*]] = phi i64 [ -48, [[WHILE_BODY_I_I_I]] ], [ -87, [[IF_ELSE_I_I_I]] ], [ -55, [[IF_ELSE17_I_I_I]] ] -// CHECK-NEXT: [[MUL24_I_I_I:%.*]] = shl i64 [[__R_0_I_I_I]], 4 +// CHECK-NEXT: [[DOTSINK:%.*]] = phi i64 [ -48, [[WHILE_BODY_I34_I_I]] ], [ -87, [[IF_ELSE_I_I_I]] ], [ -55, [[IF_ELSE17_I_I_I]] ] +// CHECK-NEXT: [[MUL24_I_I_I:%.*]] = shl i64 [[__R_0_I32_I_I]], 4 // CHECK-NEXT: [[CONV25_I_I_I:%.*]] = sext i8 [[TMP2]] to i64 // CHECK-NEXT: [[ADD26_I_I_I:%.*]] = add i64 [[MUL24_I_I_I]], [[DOTSINK]] // CHECK-NEXT: [[ADD28_I_I_I:%.*]] = add i64 [[ADD26_I_I_I]], [[CONV25_I_I_I]] +// CHECK-NEXT: [[INCDEC_PTR_I40_I_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I31_I_I]], i64 1 +// CHECK-NEXT: br label [[CLEANUP_I36_I_I]] +// CHECK: cleanup.i36.i.i: +// CHECK-NEXT: [[__TAGP_ADDR_1_I37_I_I]] = phi ptr [ [[INCDEC_PTR_I40_I_I]], [[IF_END31_I_I_I]] ], [ [[__TAGP_ADDR_0_I31_I_I]], [[IF_ELSE17_I_I_I]] ] +// CHECK-NEXT: [[__R_2_I_I_I]] = phi i64 [ [[ADD28_I_I_I]], [[IF_END31_I_I_I]] ], [ [[__R_0_I32_I_I]], [[IF_ELSE17_I_I_I]] ] +// CHECK-NEXT: [[COND_I_I_I:%.*]] = phi i1 [ true, [[IF_END31_I_I_I]] ], [ false, [[IF_ELSE17_I_I_I]] ] +// CHECK-NEXT: br i1 [[COND_I_I_I]], label [[WHILE_COND_I30_I_I]], label [[_ZL4NANFPKC_EXIT]], !llvm.loop [[LOOP11]] +// CHECK: while.cond.i.i.i: +// CHECK-NEXT: [[__TAGP_ADDR_0_I_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I_I_I:%.*]], [[CLEANUP_I_I_I:%.*]] ], [ [[INCDEC_PTR_I_I]], [[IF_THEN_I_I]] ] +// CHECK-NEXT: [[__R_0_I_I_I:%.*]] = phi i64 [ [[__R_1_I_I_I:%.*]], [[CLEANUP_I_I_I]] ], [ 0, [[IF_THEN_I_I]] ] +// CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I_I_I]], align 1, !tbaa [[TBAA4]] +// CHECK-NEXT: [[CMP_NOT_I_I_I:%.*]] = icmp eq i8 [[TMP6]], 0 +// CHECK-NEXT: br i1 [[CMP_NOT_I_I_I]], label [[_ZL4NANFPKC_EXIT]], label [[WHILE_BODY_I_I_I:%.*]] +// CHECK: while.body.i.i.i: +// CHECK-NEXT: [[TMP7:%.*]] = and i8 [[TMP6]], -8 +// CHECK-NEXT: [[OR_COND_I_I_I:%.*]] = icmp eq i8 [[TMP7]], 48 +// CHECK-NEXT: br i1 [[OR_COND_I_I_I]], label [[IF_THEN_I_I_I:%.*]], label [[CLEANUP_I_I_I]] +// CHECK: if.then.i.i.i: +// CHECK-NEXT: [[MUL_I_I_I:%.*]] = shl i64 [[__R_0_I_I_I]], 3 +// CHECK-NEXT: [[CONV5_I_I_I:%.*]] = sext i8 [[TMP6]] to i64 +// CHECK-NEXT: [[ADD_I_I_I:%.*]] = add i64 [[MUL_I_I_I]], -48 +// CHECK-NEXT: [[SUB_I_I_I:%.*]] = add i64 [[ADD_I_I_I]], [[CONV5_I_I_I]] // CHECK-NEXT: [[INCDEC_PTR_I_I_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I_I_I]], i64 1 // CHECK-NEXT: br label [[CLEANUP_I_I_I]] // CHECK: cleanup.i.i.i: -// CHECK-NEXT: [[__TAGP_ADDR_1_I_I_I]] = phi ptr [ [[INCDEC_PTR_I_I_I]], [[IF_END31_I_I_I]] ], [ [[__TAGP_ADDR_0_I_I_I]], [[IF_ELSE17_I_I_I]] ] -// CHECK-NEXT: [[__R_2_I_I_I]] = phi i64 [ [[ADD28_I_I_I]], [[IF_END31_I_I_I]] ], [ [[__R_0_I_I_I]], [[IF_ELSE17_I_I_I]] ] -// CHECK-NEXT: [[COND_I_I_I:%.*]] = phi i1 [ true, [[IF_END31_I_I_I]] ], [ false, [[IF_ELSE17_I_I_I]] ] -// CHECK-NEXT: br i1 [[COND_I_I_I]], label [[WHILE_COND_I_I_I]], label [[_ZL4NANFPKC_EXIT]], !llvm.loop [[LOOP11]] +// CHECK-NEXT: [[__TAGP_ADDR_1_I_I_I]] = phi ptr [ [[INCDEC_PTR_I_I_I]], [[IF_THEN_I_I_I]] ], [ [[__TAGP_ADDR_0_I_I_I]], [[WHILE_BODY_I_I_I]] ] +// CHECK-NEXT: [[__R_1_I_I_I]] = phi i64 [ [[SUB_I_I_I]], [[IF_THEN_I_I_I]] ], [ [[__R_0_I_I_I]], [[WHILE_BODY_I_I_I]] ] +// CHECK-NEXT: br i1 [[OR_COND_I_I_I]], label [[WHILE_COND_I_I_I]], label [[_ZL4NANFPKC_EXIT]], !llvm.loop [[LOOP7]] // CHECK: while.cond.i14.i.i: -// CHECK-NEXT: [[__TAGP_ADDR_0_I15_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I21_I_I:%.*]], [[CLEANUP_I20_I_I:%.*]] ], [ [[INCDEC_PTR_I_I]], [[IF_THEN_I_I]] ] -// CHECK-NEXT: [[__R_0_I16_I_I:%.*]] = phi i64 [ [[__R_1_I22_I_I:%.*]], [[CLEANUP_I20_I_I]] ], [ 0, [[IF_THEN_I_I]] ] -// CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I15_I_I]], align 1, !tbaa [[TBAA4]] -// CHECK-NEXT: [[CMP_NOT_I17_I_I:%.*]] = icmp eq i8 [[TMP6]], 0 +// CHECK-NEXT: [[__TAGP_ADDR_0_I15_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I21_I_I:%.*]], [[CLEANUP_I20_I_I:%.*]] ], [ [[TAG]], [[ENTRY:%.*]] ] +// CHECK-NEXT: [[__R_0_I16_I_I:%.*]] = phi i64 [ [[__R_1_I22_I_I:%.*]], [[CLEANUP_I20_I_I]] ], [ 0, [[ENTRY]] ] +// CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I15_I_I]], align 1, !tbaa [[TBAA4]] +// CHECK-NEXT: [[CMP_NOT_I17_I_I:%.*]] = icmp eq i8 [[TMP8]], 0 // CHECK-NEXT: br i1 [[CMP_NOT_I17_I_I]], label [[_ZL4NANFPKC_EXIT]], label [[WHILE_BODY_I18_I_I:%.*]] // CHECK: while.body.i18.i.i: -// CHECK-NEXT: [[TMP7:%.*]] = and i8 [[TMP6]], -8 -// CHECK-NEXT: [[OR_COND_I19_I_I:%.*]] = icmp eq i8 [[TMP7]], 48 +// CHECK-NEXT: [[TMP9:%.*]] = add i8 [[TMP8]], -48 +// CHECK-NEXT: [[OR_COND_I19_I_I:%.*]] = icmp ult i8 [[TMP9]], 10 // CHECK-NEXT: br i1 [[OR_COND_I19_I_I]], label [[IF_THEN_I24_I_I:%.*]], label [[CLEANUP_I20_I_I]] // CHECK: if.then.i24.i.i: -// CHECK-NEXT: [[MUL_I25_I_I:%.*]] = shl i64 [[__R_0_I16_I_I]], 3 -// CHECK-NEXT: [[CONV5_I26_I_I:%.*]] = sext i8 [[TMP6]] to i64 +// CHECK-NEXT: [[MUL_I25_I_I:%.*]] = mul i64 [[__R_0_I16_I_I]], 10 +// CHECK-NEXT: [[CONV5_I26_I_I:%.*]] = sext i8 [[TMP8]] to i64 // CHECK-NEXT: [[ADD_I27_I_I:%.*]] = add i64 [[MUL_I25_I_I]], -48 // CHECK-NEXT: [[SUB_I28_I_I:%.*]] = add i64 [[ADD_I27_I_I]], [[CONV5_I26_I_I]] // CHECK-NEXT: [[INCDEC_PTR_I29_I_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I15_I_I]], i64 1 @@ -2425,30 +2446,9 @@ extern "C" __device__ double test_modf(double x, double* y) { // CHECK: cleanup.i20.i.i: // CHECK-NEXT: [[__TAGP_ADDR_1_I21_I_I]] = phi ptr [ [[INCDEC_PTR_I29_I_I]], [[IF_THEN_I24_I_I]] ], [ [[__TAGP_ADDR_0_I15_I_I]], [[WHILE_BODY_I18_I_I]] ] // CHECK-NEXT: [[__R_1_I22_I_I]] = phi i64 [ [[SUB_I28_I_I]], [[IF_THEN_I24_I_I]] ], [ [[__R_0_I16_I_I]], [[WHILE_BODY_I18_I_I]] ] -// CHECK-NEXT: br i1 [[OR_COND_I19_I_I]], label [[WHILE_COND_I14_I_I]], label [[_ZL4NANFPKC_EXIT]], !llvm.loop [[LOOP7]] -// CHECK: while.cond.i30.i.i: -// CHECK-NEXT: [[__TAGP_ADDR_0_I31_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I37_I_I:%.*]], [[CLEANUP_I36_I_I:%.*]] ], [ [[TAG]], [[ENTRY:%.*]] ] -// CHECK-NEXT: [[__R_0_I32_I_I:%.*]] = phi i64 [ [[__R_1_I38_I_I:%.*]], [[CLEANUP_I36_I_I]] ], [ 0, [[ENTRY]] ] -// CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I31_I_I]], align 1, !tbaa [[TBAA4]] -// CHECK-NEXT: [[CMP_NOT_I33_I_I:%.*]] = icmp eq i8 [[TMP8]], 0 -// CHECK-NEXT: br i1 [[CMP_NOT_I33_I_I]], label [[_ZL4NANFPKC_EXIT]], label [[WHILE_BODY_I34_I_I:%.*]] -// CHECK: while.body.i34.i.i: -// CHECK-NEXT: [[TMP9:%.*]] = add i8 [[TMP8]], -48 -// CHECK-NEXT: [[OR_COND_I35_I_I:%.*]] = icmp ult i8 [[TMP9]], 10 -// CHECK-NEXT: br i1 [[OR_COND_I35_I_I]], label [[IF_THEN_I40_I_I:%.*]], label [[CLEANUP_I36_I_I]] -// CHECK: if.then.i40.i.i: -// CHECK-NEXT: [[MUL_I41_I_I:%.*]] = mul i64 [[__R_0_I32_I_I]], 10 -// CHECK-NEXT: [[CONV5_I42_I_I:%.*]] = sext i8 [[TMP8]] to i64 -// CHECK-NEXT: [[ADD_I43_I_I:%.*]] = add i64 [[MUL_I41_I_I]], -48 -// CHECK-NEXT: [[SUB_I44_I_I:%.*]] = add i64 [[ADD_I43_I_I]], [[CONV5_I42_I_I]] -// CHECK-NEXT: [[INCDEC_PTR_I45_I_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I31_I_I]], i64 1 -// CHECK-NEXT: br label [[CLEANUP_I36_I_I]] -// CHECK: cleanup.i36.i.i: -// CHECK-NEXT: [[__TAGP_ADDR_1_I37_I_I]] = phi ptr [ [[INCDEC_PTR_I45_I_I]], [[IF_THEN_I40_I_I]] ], [ [[__TAGP_ADDR_0_I31_I_I]], [[WHILE_BODY_I34_I_I]] ] -// CHECK-NEXT: [[__R_1_I38_I_I]] = phi i64 [ [[SUB_I44_I_I]], [[IF_THEN_I40_I_I]] ], [ [[__R_0_I32_I_I]], [[WHILE_BODY_I34_I_I]] ] -// CHECK-NEXT: br i1 [[OR_COND_I35_I_I]], label [[WHILE_COND_I30_I_I]], label [[_ZL4NANFPKC_EXIT]], !llvm.loop [[LOOP10]] +// CHECK-NEXT: br i1 [[OR_COND_I19_I_I]], label [[WHILE_COND_I14_I_I]], label [[_ZL4NANFPKC_EXIT]], !llvm.loop [[LOOP10]] // CHECK: _ZL4nanfPKc.exit: -// CHECK-NEXT: [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, [[CLEANUP_I20_I_I]] ], [ [[__R_0_I16_I_I]], [[WHILE_COND_I14_I_I]] ], [ 0, [[CLEANUP_I_I_I]] ], [ [[__R_0_I_I_I]], [[WHILE_COND_I_I_I]] ], [ 0, [[CLEANUP_I36_I_I]] ], [ [[__R_0_I32_I_I]], [[WHILE_COND_I30_I_I]] ] +// CHECK-NEXT: [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, [[CLEANUP_I_I_I]] ], [ [[__R_0_I_I_I]], [[WHILE_COND_I_I_I]] ], [ 0, [[CLEANUP_I36_I_I]] ], [ [[__R_0_I32_I_I]], [[WHILE_COND_I30_I_I]] ], [ 0, [[CLEANUP_I20_I_I]] ], [ [[__R_0_I16_I_I]], [[WHILE_COND_I14_I_I]] ] // CHECK-NEXT: [[CONV_I:%.*]] = trunc i64 [[RETVAL_0_I_I]] to i32 // CHECK-NEXT: [[BF_VALUE_I:%.*]] = and i32 [[CONV_I]], 4194303 // CHECK-NEXT: [[BF_SET9_I:%.*]] = or i32 [[BF_VALUE_I]], 2143289344 @@ -2463,26 +2463,26 @@ extern "C" __device__ float test_nanf(const char *tag) { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[TAG:%.*]], align 1, !tbaa [[TBAA4]] // CHECK-NEXT: [[CMP_I_I:%.*]] = icmp eq i8 [[TMP0]], 48 -// CHECK-NEXT: br i1 [[CMP_I_I]], label [[IF_THEN_I_I:%.*]], label [[WHILE_COND_I30_I_I:%.*]] +// CHECK-NEXT: br i1 [[CMP_I_I]], label [[IF_THEN_I_I:%.*]], label [[WHILE_COND_I14_I_I:%.*]] // CHECK: if.then.i.i: // CHECK-NEXT: [[INCDEC_PTR_I_I:%.*]] = getelementptr inbounds i8, ptr [[TAG]], i64 1 // CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[TBAA4]] -// CHECK-NEXT: switch i8 [[TMP1]], label [[WHILE_COND_I14_I_I:%.*]] [ -// CHECK-NEXT: i8 120, label [[WHILE_COND_I_I_I_PREHEADER:%.*]] -// CHECK-NEXT: i8 88, label [[WHILE_COND_I_I_I_PREHEADER]] +// CHECK-NEXT: switch i8 [[TMP1]], label [[WHILE_COND_I_I_I:%.*]] [ +// CHECK-NEXT: i8 120, label [[WHILE_COND_I30_I_I_PREHEADER:%.*]] +// CHECK-NEXT: i8 88, label [[WHILE_COND_I30_I_I_PREHEADER]] // CHECK-NEXT: ] -// CHECK: while.cond.i.i.i.preheader: -// CHECK-NEXT: br label [[WHILE_COND_I_I_I:%.*]] -// CHECK: while.cond.i.i.i: -// CHECK-NEXT: [[__TAGP_ADDR_0_I_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I_I_I:%.*]], [[CLEANUP_I_I_I:%.*]] ], [ [[INCDEC_PTR_I_I]], [[WHILE_COND_I_I_I_PREHEADER]] ] -// CHECK-NEXT: [[__R_0_I_I_I:%.*]] = phi i64 [ [[__R_2_I_I_I:%.*]], [[CLEANUP_I_I_I]] ], [ 0, [[WHILE_COND_I_I_I_PREHEADER]] ] -// CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I_I_I]], align 1, !tbaa [[TBAA4]] -// CHECK-NEXT: [[CMP_NOT_I_I_I:%.*]] = icmp eq i8 [[TMP2]], 0 -// CHECK-NEXT: br i1 [[CMP_NOT_I_I_I]], label [[_ZL3NANPKC_EXIT:%.*]], label [[WHILE_BODY_I_I_I:%.*]] -// CHECK: while.body.i.i.i: +// CHECK: while.cond.i30.i.i.preheader: +// CHECK-NEXT: br label [[WHILE_COND_I30_I_I:%.*]] +// CHECK: while.cond.i30.i.i: +// CHECK-NEXT: [[__TAGP_ADDR_0_I31_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I37_I_I:%.*]], [[CLEANUP_I36_I_I:%.*]] ], [ [[INCDEC_PTR_I_I]], [[WHILE_COND_I30_I_I_PREHEADER]] ] +// CHECK-NEXT: [[__R_0_I32_I_I:%.*]] = phi i64 [ [[__R_2_I_I_I:%.*]], [[CLEANUP_I36_I_I]] ], [ 0, [[WHILE_COND_I30_I_I_PREHEADER]] ] +// CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I31_I_I]], align 1, !tbaa [[TBAA4]] +// CHECK-NEXT: [[CMP_NOT_I33_I_I:%.*]] = icmp eq i8 [[TMP2]], 0 +// CHECK-NEXT: br i1 [[CMP_NOT_I33_I_I]], label [[_ZL3NANPKC_EXIT:%.*]], label [[WHILE_BODY_I34_I_I:%.*]] +// CHECK: while.body.i34.i.i: // CHECK-NEXT: [[TMP3:%.*]] = add i8 [[TMP2]], -48 -// CHECK-NEXT: [[OR_COND_I_I_I:%.*]] = icmp ult i8 [[TMP3]], 10 -// CHECK-NEXT: br i1 [[OR_COND_I_I_I]], label [[IF_END31_I_I_I:%.*]], label [[IF_ELSE_I_I_I:%.*]] +// CHECK-NEXT: [[OR_COND_I35_I_I:%.*]] = icmp ult i8 [[TMP3]], 10 +// CHECK-NEXT: br i1 [[OR_COND_I35_I_I]], label [[IF_END31_I_I_I:%.*]], label [[IF_ELSE_I_I_I:%.*]] // CHECK: if.else.i.i.i: // CHECK-NEXT: [[TMP4:%.*]] = add i8 [[TMP2]], -97 // CHECK-NEXT: [[OR_COND33_I_I_I:%.*]] = icmp ult i8 [[TMP4]], 6 @@ -2490,33 +2490,54 @@ extern "C" __device__ float test_nanf(const char *tag) { // CHECK: if.else17.i.i.i: // CHECK-NEXT: [[TMP5:%.*]] = add i8 [[TMP2]], -65 // CHECK-NEXT: [[OR_COND34_I_I_I:%.*]] = icmp ult i8 [[TMP5]], 6 -// CHECK-NEXT: br i1 [[OR_COND34_I_I_I]], label [[IF_END31_I_I_I]], label [[CLEANUP_I_I_I]] +// CHECK-NEXT: br i1 [[OR_COND34_I_I_I]], label [[IF_END31_I_I_I]], label [[CLEANUP_I36_I_I]] // CHECK: if.end31.i.i.i: -// CHECK-NEXT: [[DOTSINK:%.*]] = phi i64 [ -48, [[WHILE_BODY_I_I_I]] ], [ -87, [[IF_ELSE_I_I_I]] ], [ -55, [[IF_ELSE17_I_I_I]] ] -// CHECK-NEXT: [[MUL24_I_I_I:%.*]] = shl i64 [[__R_0_I_I_I]], 4 +// CHECK-NEXT: [[DOTSINK:%.*]] = phi i64 [ -48, [[WHILE_BODY_I34_I_I]] ], [ -87, [[IF_ELSE_I_I_I]] ], [ -55, [[IF_ELSE17_I_I_I]] ] +// CHECK-NEXT: [[MUL24_I_I_I:%.*]] = shl i64 [[__R_0_I32_I_I]], 4 // CHECK-NEXT: [[CONV25_I_I_I:%.*]] = sext i8 [[TMP2]] to i64 // CHECK-NEXT: [[ADD26_I_I_I:%.*]] = add i64 [[MUL24_I_I_I]], [[DOTSINK]] // CHECK-NEXT: [[ADD28_I_I_I:%.*]] = add i64 [[ADD26_I_I_I]], [[CONV25_I_I_I]] +// CHECK-NEXT: [[INCDEC_PTR_I40_I_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I31_I_I]], i64 1 +// CHECK-NEXT: br label [[CLEANUP_I36_I_I]] +// CHECK: cleanup.i36.i.i: +// CHECK-NEXT: [[__TAGP_ADDR_1_I37_I_I]] = phi ptr [ [[INCDEC_PTR_I40_I_I]], [[IF_END31_I_I_I]] ], [ [[__TAGP_ADDR_0_I31_I_I]], [[IF_ELSE17_I_I_I]] ] +// CHECK-NEXT: [[__R_2_I_I_I]] = phi i64 [ [[ADD28_I_I_I]], [[IF_END31_I_I_I]] ], [ [[__R_0_I32_I_I]], [[IF_ELSE17_I_I_I]] ] +// CHECK-NEXT: [[COND_I_I_I:%.*]] = phi i1 [ true, [[IF_END31_I_I_I]] ], [ false, [[IF_ELSE17_I_I_I]] ] +// CHECK-NEXT: br i1 [[COND_I_I_I]], label [[WHILE_COND_I30_I_I]], label [[_ZL3NANPKC_EXIT]], !llvm.loop [[LOOP11]] +// CHECK: while.cond.i.i.i: +// CHECK-NEXT: [[__TAGP_ADDR_0_I_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I_I_I:%.*]], [[CLEANUP_I_I_I:%.*]] ], [ [[INCDEC_PTR_I_I]], [[IF_THEN_I_I]] ] +// CHECK-NEXT: [[__R_0_I_I_I:%.*]] = phi i64 [ [[__R_1_I_I_I:%.*]], [[CLEANUP_I_I_I]] ], [ 0, [[IF_THEN_I_I]] ] +// CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I_I_I]], align 1, !tbaa [[TBAA4]] +// CHECK-NEXT: [[CMP_NOT_I_I_I:%.*]] = icmp eq i8 [[TMP6]], 0 +// CHECK-NEXT: br i1 [[CMP_NOT_I_I_I]], label [[_ZL3NANPKC_EXIT]], label [[WHILE_BODY_I_I_I:%.*]] +// CHECK: while.body.i.i.i: +// CHECK-NEXT: [[TMP7:%.*]] = and i8 [[TMP6]], -8 +// CHECK-NEXT: [[OR_COND_I_I_I:%.*]] = icmp eq i8 [[TMP7]], 48 +// CHECK-NEXT: br i1 [[OR_COND_I_I_I]], label [[IF_THEN_I_I_I:%.*]], label [[CLEANUP_I_I_I]] +// CHECK: if.then.i.i.i: +// CHECK-NEXT: [[MUL_I_I_I:%.*]] = shl i64 [[__R_0_I_I_I]], 3 +// CHECK-NEXT: [[CONV5_I_I_I:%.*]] = sext i8 [[TMP6]] to i64 +// CHECK-NEXT: [[ADD_I_I_I:%.*]] = add i64 [[MUL_I_I_I]], -48 +// CHECK-NEXT: [[SUB_I_I_I:%.*]] = add i64 [[ADD_I_I_I]], [[CONV5_I_I_I]] // CHECK-NEXT: [[INCDEC_PTR_I_I_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I_I_I]], i64 1 // CHECK-NEXT: br label [[CLEANUP_I_I_I]] // CHECK: cleanup.i.i.i: -// CHECK-NEXT: [[__TAGP_ADDR_1_I_I_I]] = phi ptr [ [[INCDEC_PTR_I_I_I]], [[IF_END31_I_I_I]] ], [ [[__TAGP_ADDR_0_I_I_I]], [[IF_ELSE17_I_I_I]] ] -// CHECK-NEXT: [[__R_2_I_I_I]] = phi i64 [ [[ADD28_I_I_I]], [[IF_END31_I_I_I]] ], [ [[__R_0_I_I_I]], [[IF_ELSE17_I_I_I]] ] -// CHECK-NEXT: [[COND_I_I_I:%.*]] = phi i1 [ true, [[IF_END31_I_I_I]] ], [ false, [[IF_ELSE17_I_I_I]] ] -// CHECK-NEXT: br i1 [[COND_I_I_I]], label [[WHILE_COND_I_I_I]], label [[_ZL3NANPKC_EXIT]], !llvm.loop [[LOOP11]] +// CHECK-NEXT: [[__TAGP_ADDR_1_I_I_I]] = phi ptr [ [[INCDEC_PTR_I_I_I]], [[IF_THEN_I_I_I]] ], [ [[__TAGP_ADDR_0_I_I_I]], [[WHILE_BODY_I_I_I]] ] +// CHECK-NEXT: [[__R_1_I_I_I]] = phi i64 [ [[SUB_I_I_I]], [[IF_THEN_I_I_I]] ], [ [[__R_0_I_I_I]], [[WHILE_BODY_I_I_I]] ] +// CHECK-NEXT: br i1 [[OR_COND_I_I_I]], label [[WHILE_COND_I_I_I]], label [[_ZL3NANPKC_EXIT]], !llvm.loop [[LOOP7]] // CHECK: while.cond.i14.i.i: -// CHECK-NEXT: [[__TAGP_ADDR_0_I15_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I21_I_I:%.*]], [[CLEANUP_I20_I_I:%.*]] ], [ [[INCDEC_PTR_I_I]], [[IF_THEN_I_I]] ] -// CHECK-NEXT: [[__R_0_I16_I_I:%.*]] = phi i64 [ [[__R_1_I22_I_I:%.*]], [[CLEANUP_I20_I_I]] ], [ 0, [[IF_THEN_I_I]] ] -// CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I15_I_I]], align 1, !tbaa [[TBAA4]] -// CHECK-NEXT: [[CMP_NOT_I17_I_I:%.*]] = icmp eq i8 [[TMP6]], 0 +// CHECK-NEXT: [[__TAGP_ADDR_0_I15_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I21_I_I:%.*]], [[CLEANUP_I20_I_I:%.*]] ], [ [[TAG]], [[ENTRY:%.*]] ] +// CHECK-NEXT: [[__R_0_I16_I_I:%.*]] = phi i64 [ [[__R_1_I22_I_I:%.*]], [[CLEANUP_I20_I_I]] ], [ 0, [[ENTRY]] ] +// CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I15_I_I]], align 1, !tbaa [[TBAA4]] +// CHECK-NEXT: [[CMP_NOT_I17_I_I:%.*]] = icmp eq i8 [[TMP8]], 0 // CHECK-NEXT: br i1 [[CMP_NOT_I17_I_I]], label [[_ZL3NANPKC_EXIT]], label [[WHILE_BODY_I18_I_I:%.*]] // CHECK: while.body.i18.i.i: -// CHECK-NEXT: [[TMP7:%.*]] = and i8 [[TMP6]], -8 -// CHECK-NEXT: [[OR_COND_I19_I_I:%.*]] = icmp eq i8 [[TMP7]], 48 +// CHECK-NEXT: [[TMP9:%.*]] = add i8 [[TMP8]], -48 +// CHECK-NEXT: [[OR_COND_I19_I_I:%.*]] = icmp ult i8 [[TMP9]], 10 // CHECK-NEXT: br i1 [[OR_COND_I19_I_I]], label [[IF_THEN_I24_I_I:%.*]], label [[CLEANUP_I20_I_I]] // CHECK: if.then.i24.i.i: -// CHECK-NEXT: [[MUL_I25_I_I:%.*]] = shl i64 [[__R_0_I16_I_I]], 3 -// CHECK-NEXT: [[CONV5_I26_I_I:%.*]] = sext i8 [[TMP6]] to i64 +// CHECK-NEXT: [[MUL_I25_I_I:%.*]] = mul i64 [[__R_0_I16_I_I]], 10 +// CHECK-NEXT: [[CONV5_I26_I_I:%.*]] = sext i8 [[TMP8]] to i64 // CHECK-NEXT: [[ADD_I27_I_I:%.*]] = add i64 [[MUL_I25_I_I]], -48 // CHECK-NEXT: [[SUB_I28_I_I:%.*]] = add i64 [[ADD_I27_I_I]], [[CONV5_I26_I_I]] // CHECK-NEXT: [[INCDEC_PTR_I29_I_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I15_I_I]], i64 1 @@ -2524,30 +2545,9 @@ extern "C" __device__ float test_nanf(const char *tag) { // CHECK: cleanup.i20.i.i: // CHECK-NEXT: [[__TAGP_ADDR_1_I21_I_I]] = phi ptr [ [[INCDEC_PTR_I29_I_I]], [[IF_THEN_I24_I_I]] ], [ [[__TAGP_ADDR_0_I15_I_I]], [[WHILE_BODY_I18_I_I]] ] // CHECK-NEXT: [[__R_1_I22_I_I]] = phi i64 [ [[SUB_I28_I_I]], [[IF_THEN_I24_I_I]] ], [ [[__R_0_I16_I_I]], [[WHILE_BODY_I18_I_I]] ] -// CHECK-NEXT: br i1 [[OR_COND_I19_I_I]], label [[WHILE_COND_I14_I_I]], label [[_ZL3NANPKC_EXIT]], !llvm.loop [[LOOP7]] -// CHECK: while.cond.i30.i.i: -// CHECK-NEXT: [[__TAGP_ADDR_0_I31_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I37_I_I:%.*]], [[CLEANUP_I36_I_I:%.*]] ], [ [[TAG]], [[ENTRY:%.*]] ] -// CHECK-NEXT: [[__R_0_I32_I_I:%.*]] = phi i64 [ [[__R_1_I38_I_I:%.*]], [[CLEANUP_I36_I_I]] ], [ 0, [[ENTRY]] ] -// CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I31_I_I]], align 1, !tbaa [[TBAA4]] -// CHECK-NEXT: [[CMP_NOT_I33_I_I:%.*]] = icmp eq i8 [[TMP8]], 0 -// CHECK-NEXT: br i1 [[CMP_NOT_I33_I_I]], label [[_ZL3NANPKC_EXIT]], label [[WHILE_BODY_I34_I_I:%.*]] -// CHECK: while.body.i34.i.i: -// CHECK-NEXT: [[TMP9:%.*]] = add i8 [[TMP8]], -48 -// CHECK-NEXT: [[OR_COND_I35_I_I:%.*]] = icmp ult i8 [[TMP9]], 10 -// CHECK-NEXT: br i1 [[OR_COND_I35_I_I]], label [[IF_THEN_I40_I_I:%.*]], label [[CLEANUP_I36_I_I]] -// CHECK: if.then.i40.i.i: -// CHECK-NEXT: [[MUL_I41_I_I:%.*]] = mul i64 [[__R_0_I32_I_I]], 10 -// CHECK-NEXT: [[CONV5_I42_I_I:%.*]] = sext i8 [[TMP8]] to i64 -// CHECK-NEXT: [[ADD_I43_I_I:%.*]] = add i64 [[MUL_I41_I_I]], -48 -// CHECK-NEXT: [[SUB_I44_I_I:%.*]] = add i64 [[ADD_I43_I_I]], [[CONV5_I42_I_I]] -// CHECK-NEXT: [[INCDEC_PTR_I45_I_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I31_I_I]], i64 1 -// CHECK-NEXT: br label [[CLEANUP_I36_I_I]] -// CHECK: cleanup.i36.i.i: -// CHECK-NEXT: [[__TAGP_ADDR_1_I37_I_I]] = phi ptr [ [[INCDEC_PTR_I45_I_I]], [[IF_THEN_I40_I_I]] ], [ [[__TAGP_ADDR_0_I31_I_I]], [[WHILE_BODY_I34_I_I]] ] -// CHECK-NEXT: [[__R_1_I38_I_I]] = phi i64 [ [[SUB_I44_I_I]], [[IF_THEN_I40_I_I]] ], [ [[__R_0_I32_I_I]], [[WHILE_BODY_I34_I_I]] ] -// CHECK-NEXT: br i1 [[OR_COND_I35_I_I]], label [[WHILE_COND_I30_I_I]], label [[_ZL3NANPKC_EXIT]], !llvm.loop [[LOOP10]] +// CHECK-NEXT: br i1 [[OR_COND_I19_I_I]], label [[WHILE_COND_I14_I_I]], label [[_ZL3NANPKC_EXIT]], !llvm.loop [[LOOP10]] // CHECK: _ZL3nanPKc.exit: -// CHECK-NEXT: [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, [[CLEANUP_I20_I_I]] ], [ [[__R_0_I16_I_I]], [[WHILE_COND_I14_I_I]] ], [ 0, [[CLEANUP_I_I_I]] ], [ [[__R_0_I_I_I]], [[WHILE_COND_I_I_I]] ], [ 0, [[CLEANUP_I36_I_I]] ], [ [[__R_0_I32_I_I]], [[WHILE_COND_I30_I_I]] ] +// CHECK-NEXT: [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, [[CLEANUP_I_I_I]] ], [ [[__R_0_I_I_I]], [[WHILE_COND_I_I_I]] ], [ 0, [[CLEANUP_I36_I_I]] ], [ [[__R_0_I32_I_I]], [[WHILE_COND_I30_I_I]] ], [ 0, [[CLEANUP_I20_I_I]] ], [ [[__R_0_I16_I_I]], [[WHILE_COND_I14_I_I]] ] // CHECK-NEXT: [[BF_VALUE_I:%.*]] = and i64 [[RETVAL_0_I_I]], 2251799813685247 // CHECK-NEXT: [[BF_SET9_I:%.*]] = or i64 [[BF_VALUE_I]], 9221120237041090560 // CHECK-NEXT: [[TMP10:%.*]] = bitcast i64 [[BF_SET9_I]] to double @@ -2819,62 +2819,62 @@ extern "C" __device__ double test_normcdfinv(double x) { // DEFAULT-LABEL: @test_normf( // DEFAULT-NEXT: entry: -// DEFAULT-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X:%.*]], 0 -// DEFAULT-NEXT: br i1 [[TOBOOL_NOT5_I]], label [[_ZL5NORMFIPKF_EXIT:%.*]], label [[WHILE_BODY_I:%.*]] +// DEFAULT-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X:%.*]], 0 +// DEFAULT-NEXT: br i1 [[TOBOOL_NOT_I1]], label [[_ZL5NORMFIPKF_EXIT:%.*]], label [[WHILE_BODY_I:%.*]] // DEFAULT: while.body.i: -// DEFAULT-NEXT: [[__R_08_I:%.*]] = phi float [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] -// DEFAULT-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ] -// DEFAULT-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ] -// DEFAULT-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 -// DEFAULT-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_07_I]], align 4, !tbaa [[TBAA16]] +// DEFAULT-NEXT: [[__R_0_I4:%.*]] = phi float [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] +// DEFAULT-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ] +// DEFAULT-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ] +// DEFAULT-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 +// DEFAULT-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_0_I3]], align 4, !tbaa [[TBAA16]] // DEFAULT-NEXT: [[MUL_I:%.*]] = fmul contract float [[TMP0]], [[TMP0]] -// DEFAULT-NEXT: [[ADD_I]] = fadd contract float [[__R_08_I]], [[MUL_I]] -// DEFAULT-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds float, ptr [[__A_ADDR_07_I]], i64 1 +// DEFAULT-NEXT: [[ADD_I]] = fadd contract float [[__R_0_I4]], [[MUL_I]] +// DEFAULT-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds float, ptr [[__A_ADDR_0_I3]], i64 1 // DEFAULT-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 // DEFAULT-NEXT: br i1 [[TOBOOL_NOT_I]], label [[_ZL5NORMFIPKF_EXIT]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP20:![0-9]+]] // DEFAULT: _ZL5normfiPKf.exit: -// DEFAULT-NEXT: [[__R_0_LCSSA_I:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ] -// DEFAULT-NEXT: [[TMP1:%.*]] = tail call contract noundef float @llvm.sqrt.f32(float [[__R_0_LCSSA_I]]) +// DEFAULT-NEXT: [[__R_0_I_LCSSA:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ] +// DEFAULT-NEXT: [[TMP1:%.*]] = tail call contract noundef float @llvm.sqrt.f32(float [[__R_0_I_LCSSA]]) // DEFAULT-NEXT: ret float [[TMP1]] // // FINITEONLY-LABEL: @test_normf( // FINITEONLY-NEXT: entry: -// FINITEONLY-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X:%.*]], 0 -// FINITEONLY-NEXT: br i1 [[TOBOOL_NOT5_I]], label [[_ZL5NORMFIPKF_EXIT:%.*]], label [[WHILE_BODY_I:%.*]] +// FINITEONLY-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X:%.*]], 0 +// FINITEONLY-NEXT: br i1 [[TOBOOL_NOT_I1]], label [[_ZL5NORMFIPKF_EXIT:%.*]], label [[WHILE_BODY_I:%.*]] // FINITEONLY: while.body.i: -// FINITEONLY-NEXT: [[__R_08_I:%.*]] = phi float [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] -// FINITEONLY-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ] -// FINITEONLY-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ] -// FINITEONLY-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 -// FINITEONLY-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_07_I]], align 4, !tbaa [[TBAA16]] +// FINITEONLY-NEXT: [[__R_0_I4:%.*]] = phi float [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] +// FINITEONLY-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ] +// FINITEONLY-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ] +// FINITEONLY-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 +// FINITEONLY-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_0_I3]], align 4, !tbaa [[TBAA16]] // FINITEONLY-NEXT: [[MUL_I:%.*]] = fmul nnan ninf contract float [[TMP0]], [[TMP0]] -// FINITEONLY-NEXT: [[ADD_I]] = fadd nnan ninf contract float [[__R_08_I]], [[MUL_I]] -// FINITEONLY-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds float, ptr [[__A_ADDR_07_I]], i64 1 +// FINITEONLY-NEXT: [[ADD_I]] = fadd nnan ninf contract float [[__R_0_I4]], [[MUL_I]] +// FINITEONLY-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds float, ptr [[__A_ADDR_0_I3]], i64 1 // FINITEONLY-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 // FINITEONLY-NEXT: br i1 [[TOBOOL_NOT_I]], label [[_ZL5NORMFIPKF_EXIT]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP20:![0-9]+]] // FINITEONLY: _ZL5normfiPKf.exit: -// FINITEONLY-NEXT: [[__R_0_LCSSA_I:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ] -// FINITEONLY-NEXT: [[TMP1:%.*]] = tail call nnan ninf contract noundef float @llvm.sqrt.f32(float [[__R_0_LCSSA_I]]) +// FINITEONLY-NEXT: [[__R_0_I_LCSSA:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ] +// FINITEONLY-NEXT: [[TMP1:%.*]] = tail call nnan ninf contract noundef float @llvm.sqrt.f32(float [[__R_0_I_LCSSA]]) // FINITEONLY-NEXT: ret float [[TMP1]] // // APPROX-LABEL: @test_normf( // APPROX-NEXT: entry: -// APPROX-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X:%.*]], 0 -// APPROX-NEXT: br i1 [[TOBOOL_NOT5_I]], label [[_ZL5NORMFIPKF_EXIT:%.*]], label [[WHILE_BODY_I:%.*]] +// APPROX-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X:%.*]], 0 +// APPROX-NEXT: br i1 [[TOBOOL_NOT_I1]], label [[_ZL5NORMFIPKF_EXIT:%.*]], label [[WHILE_BODY_I:%.*]] // APPROX: while.body.i: -// APPROX-NEXT: [[__R_08_I:%.*]] = phi float [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] -// APPROX-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ] -// APPROX-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ] -// APPROX-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 -// APPROX-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_07_I]], align 4, !tbaa [[TBAA16]] +// APPROX-NEXT: [[__R_0_I4:%.*]] = phi float [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] +// APPROX-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ] +// APPROX-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ] +// APPROX-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 +// APPROX-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_0_I3]], align 4, !tbaa [[TBAA16]] // APPROX-NEXT: [[MUL_I:%.*]] = fmul contract float [[TMP0]], [[TMP0]] -// APPROX-NEXT: [[ADD_I]] = fadd contract float [[__R_08_I]], [[MUL_I]] -// APPROX-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds float, ptr [[__A_ADDR_07_I]], i64 1 +// APPROX-NEXT: [[ADD_I]] = fadd contract float [[__R_0_I4]], [[MUL_I]] +// APPROX-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds float, ptr [[__A_ADDR_0_I3]], i64 1 // APPROX-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 // APPROX-NEXT: br i1 [[TOBOOL_NOT_I]], label [[_ZL5NORMFIPKF_EXIT]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP20:![0-9]+]] // APPROX: _ZL5normfiPKf.exit: -// APPROX-NEXT: [[__R_0_LCSSA_I:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ] -// APPROX-NEXT: [[TMP1:%.*]] = tail call contract noundef float @llvm.sqrt.f32(float [[__R_0_LCSSA_I]]) +// APPROX-NEXT: [[__R_0_I_LCSSA:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ] +// APPROX-NEXT: [[TMP1:%.*]] = tail call contract noundef float @llvm.sqrt.f32(float [[__R_0_I_LCSSA]]) // APPROX-NEXT: ret float [[TMP1]] // extern "C" __device__ float test_normf(int x, const float *y) { @@ -2883,62 +2883,62 @@ extern "C" __device__ float test_normf(int x, const float *y) { // DEFAULT-LABEL: @test_norm( // DEFAULT-NEXT: entry: -// DEFAULT-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X:%.*]], 0 -// DEFAULT-NEXT: br i1 [[TOBOOL_NOT5_I]], label [[_ZL4NORMIPKD_EXIT:%.*]], label [[WHILE_BODY_I:%.*]] +// DEFAULT-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X:%.*]], 0 +// DEFAULT-NEXT: br i1 [[TOBOOL_NOT_I1]], label [[_ZL4NORMIPKD_EXIT:%.*]], label [[WHILE_BODY_I:%.*]] // DEFAULT: while.body.i: -// DEFAULT-NEXT: [[__R_08_I:%.*]] = phi double [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] -// DEFAULT-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ] -// DEFAULT-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ] -// DEFAULT-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 -// DEFAULT-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_07_I]], align 8, !tbaa [[TBAA18]] +// DEFAULT-NEXT: [[__R_0_I4:%.*]] = phi double [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] +// DEFAULT-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ] +// DEFAULT-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ] +// DEFAULT-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 +// DEFAULT-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_0_I3]], align 8, !tbaa [[TBAA18]] // DEFAULT-NEXT: [[MUL_I:%.*]] = fmul contract double [[TMP0]], [[TMP0]] -// DEFAULT-NEXT: [[ADD_I]] = fadd contract double [[__R_08_I]], [[MUL_I]] -// DEFAULT-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds double, ptr [[__A_ADDR_07_I]], i64 1 +// DEFAULT-NEXT: [[ADD_I]] = fadd contract double [[__R_0_I4]], [[MUL_I]] +// DEFAULT-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds double, ptr [[__A_ADDR_0_I3]], i64 1 // DEFAULT-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 // DEFAULT-NEXT: br i1 [[TOBOOL_NOT_I]], label [[_ZL4NORMIPKD_EXIT]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP21:![0-9]+]] // DEFAULT: _ZL4normiPKd.exit: -// DEFAULT-NEXT: [[__R_0_LCSSA_I:%.*]] = phi double [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ] -// DEFAULT-NEXT: [[TMP1:%.*]] = tail call contract noundef double @llvm.sqrt.f64(double [[__R_0_LCSSA_I]]) +// DEFAULT-NEXT: [[__R_0_I_LCSSA:%.*]] = phi double [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ] +// DEFAULT-NEXT: [[TMP1:%.*]] = tail call contract noundef double @llvm.sqrt.f64(double [[__R_0_I_LCSSA]]) // DEFAULT-NEXT: ret double [[TMP1]] // // FINITEONLY-LABEL: @test_norm( // FINITEONLY-NEXT: entry: -// FINITEONLY-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X:%.*]], 0 -// FINITEONLY-NEXT: br i1 [[TOBOOL_NOT5_I]], label [[_ZL4NORMIPKD_EXIT:%.*]], label [[WHILE_BODY_I:%.*]] +// FINITEONLY-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X:%.*]], 0 +// FINITEONLY-NEXT: br i1 [[TOBOOL_NOT_I1]], label [[_ZL4NORMIPKD_EXIT:%.*]], label [[WHILE_BODY_I:%.*]] // FINITEONLY: while.body.i: -// FINITEONLY-NEXT: [[__R_08_I:%.*]] = phi double [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] -// FINITEONLY-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ] -// FINITEONLY-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ] -// FINITEONLY-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 -// FINITEONLY-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_07_I]], align 8, !tbaa [[TBAA18]] +// FINITEONLY-NEXT: [[__R_0_I4:%.*]] = phi double [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] +// FINITEONLY-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ] +// FINITEONLY-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ] +// FINITEONLY-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 +// FINITEONLY-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_0_I3]], align 8, !tbaa [[TBAA18]] // FINITEONLY-NEXT: [[MUL_I:%.*]] = fmul nnan ninf contract double [[TMP0]], [[TMP0]] -// FINITEONLY-NEXT: [[ADD_I]] = fadd nnan ninf contract double [[__R_08_I]], [[MUL_I]] -// FINITEONLY-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds double, ptr [[__A_ADDR_07_I]], i64 1 +// FINITEONLY-NEXT: [[ADD_I]] = fadd nnan ninf contract double [[__R_0_I4]], [[MUL_I]] +// FINITEONLY-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds double, ptr [[__A_ADDR_0_I3]], i64 1 // FINITEONLY-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 // FINITEONLY-NEXT: br i1 [[TOBOOL_NOT_I]], label [[_ZL4NORMIPKD_EXIT]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP21:![0-9]+]] // FINITEONLY: _ZL4normiPKd.exit: -// FINITEONLY-NEXT: [[__R_0_LCSSA_I:%.*]] = phi double [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ] -// FINITEONLY-NEXT: [[TMP1:%.*]] = tail call nnan ninf contract noundef double @llvm.sqrt.f64(double [[__R_0_LCSSA_I]]) +// FINITEONLY-NEXT: [[__R_0_I_LCSSA:%.*]] = phi double [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ] +// FINITEONLY-NEXT: [[TMP1:%.*]] = tail call nnan ninf contract noundef double @llvm.sqrt.f64(double [[__R_0_I_LCSSA]]) // FINITEONLY-NEXT: ret double [[TMP1]] // // APPROX-LABEL: @test_norm( // APPROX-NEXT: entry: -// APPROX-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X:%.*]], 0 -// APPROX-NEXT: br i1 [[TOBOOL_NOT5_I]], label [[_ZL4NORMIPKD_EXIT:%.*]], label [[WHILE_BODY_I:%.*]] +// APPROX-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X:%.*]], 0 +// APPROX-NEXT: br i1 [[TOBOOL_NOT_I1]], label [[_ZL4NORMIPKD_EXIT:%.*]], label [[WHILE_BODY_I:%.*]] // APPROX: while.body.i: -// APPROX-NEXT: [[__R_08_I:%.*]] = phi double [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] -// APPROX-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ] -// APPROX-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ] -// APPROX-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 -// APPROX-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_07_I]], align 8, !tbaa [[TBAA18]] +// APPROX-NEXT: [[__R_0_I4:%.*]] = phi double [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] +// APPROX-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ] +// APPROX-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ] +// APPROX-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 +// APPROX-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_0_I3]], align 8, !tbaa [[TBAA18]] // APPROX-NEXT: [[MUL_I:%.*]] = fmul contract double [[TMP0]], [[TMP0]] -// APPROX-NEXT: [[ADD_I]] = fadd contract double [[__R_08_I]], [[MUL_I]] -// APPROX-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds double, ptr [[__A_ADDR_07_I]], i64 1 +// APPROX-NEXT: [[ADD_I]] = fadd contract double [[__R_0_I4]], [[MUL_I]] +// APPROX-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds double, ptr [[__A_ADDR_0_I3]], i64 1 // APPROX-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 // APPROX-NEXT: br i1 [[TOBOOL_NOT_I]], label [[_ZL4NORMIPKD_EXIT]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP21:![0-9]+]] // APPROX: _ZL4normiPKd.exit: -// APPROX-NEXT: [[__R_0_LCSSA_I:%.*]] = phi double [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ] -// APPROX-NEXT: [[TMP1:%.*]] = tail call contract noundef double @llvm.sqrt.f64(double [[__R_0_LCSSA_I]]) +// APPROX-NEXT: [[__R_0_I_LCSSA:%.*]] = phi double [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ] +// APPROX-NEXT: [[TMP1:%.*]] = tail call contract noundef double @llvm.sqrt.f64(double [[__R_0_I_LCSSA]]) // APPROX-NEXT: ret double [[TMP1]] // extern "C" __device__ double test_norm(int x, const double *y) { @@ -3243,62 +3243,62 @@ extern "C" __device__ double test_rint(double x) { // DEFAULT-LABEL: @test_rnormf( // DEFAULT-NEXT: entry: -// DEFAULT-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X:%.*]], 0 -// DEFAULT-NEXT: br i1 [[TOBOOL_NOT5_I]], label [[_ZL6RNORMFIPKF_EXIT:%.*]], label [[WHILE_BODY_I:%.*]] +// DEFAULT-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X:%.*]], 0 +// DEFAULT-NEXT: br i1 [[TOBOOL_NOT_I1]], label [[_ZL6RNORMFIPKF_EXIT:%.*]], label [[WHILE_BODY_I:%.*]] // DEFAULT: while.body.i: -// DEFAULT-NEXT: [[__R_08_I:%.*]] = phi float [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] -// DEFAULT-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ] -// DEFAULT-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ] -// DEFAULT-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 -// DEFAULT-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_07_I]], align 4, !tbaa [[TBAA16]] +// DEFAULT-NEXT: [[__R_0_I4:%.*]] = phi float [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] +// DEFAULT-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ] +// DEFAULT-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ] +// DEFAULT-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 +// DEFAULT-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_0_I3]], align 4, !tbaa [[TBAA16]] // DEFAULT-NEXT: [[MUL_I:%.*]] = fmul contract float [[TMP0]], [[TMP0]] -// DEFAULT-NEXT: [[ADD_I]] = fadd contract float [[__R_08_I]], [[MUL_I]] -// DEFAULT-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds float, ptr [[__A_ADDR_07_I]], i64 1 +// DEFAULT-NEXT: [[ADD_I]] = fadd contract float [[__R_0_I4]], [[MUL_I]] +// DEFAULT-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds float, ptr [[__A_ADDR_0_I3]], i64 1 // DEFAULT-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 // DEFAULT-NEXT: br i1 [[TOBOOL_NOT_I]], label [[_ZL6RNORMFIPKF_EXIT]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP22:![0-9]+]] // DEFAULT: _ZL6rnormfiPKf.exit: -// DEFAULT-NEXT: [[__R_0_LCSSA_I:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ] -// DEFAULT-NEXT: [[CALL_I:%.*]] = tail call contract noundef float @__ocml_rsqrt_f32(float noundef [[__R_0_LCSSA_I]]) #[[ATTR15]] +// DEFAULT-NEXT: [[__R_0_I_LCSSA:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ] +// DEFAULT-NEXT: [[CALL_I:%.*]] = tail call contract noundef float @__ocml_rsqrt_f32(float noundef [[__R_0_I_LCSSA]]) #[[ATTR15]] // DEFAULT-NEXT: ret float [[CALL_I]] // // FINITEONLY-LABEL: @test_rnormf( // FINITEONLY-NEXT: entry: -// FINITEONLY-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X:%.*]], 0 -// FINITEONLY-NEXT: br i1 [[TOBOOL_NOT5_I]], label [[_ZL6RNORMFIPKF_EXIT:%.*]], label [[WHILE_BODY_I:%.*]] +// FINITEONLY-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X:%.*]], 0 +// FINITEONLY-NEXT: br i1 [[TOBOOL_NOT_I1]], label [[_ZL6RNORMFIPKF_EXIT:%.*]], label [[WHILE_BODY_I:%.*]] // FINITEONLY: while.body.i: -// FINITEONLY-NEXT: [[__R_08_I:%.*]] = phi float [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] -// FINITEONLY-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ] -// FINITEONLY-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ] -// FINITEONLY-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 -// FINITEONLY-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_07_I]], align 4, !tbaa [[TBAA16]] +// FINITEONLY-NEXT: [[__R_0_I4:%.*]] = phi float [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] +// FINITEONLY-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ] +// FINITEONLY-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ] +// FINITEONLY-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 +// FINITEONLY-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_0_I3]], align 4, !tbaa [[TBAA16]] // FINITEONLY-NEXT: [[MUL_I:%.*]] = fmul nnan ninf contract float [[TMP0]], [[TMP0]] -// FINITEONLY-NEXT: [[ADD_I]] = fadd nnan ninf contract float [[__R_08_I]], [[MUL_I]] -// FINITEONLY-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds float, ptr [[__A_ADDR_07_I]], i64 1 +// FINITEONLY-NEXT: [[ADD_I]] = fadd nnan ninf contract float [[__R_0_I4]], [[MUL_I]] +// FINITEONLY-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds float, ptr [[__A_ADDR_0_I3]], i64 1 // FINITEONLY-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 // FINITEONLY-NEXT: br i1 [[TOBOOL_NOT_I]], label [[_ZL6RNORMFIPKF_EXIT]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP22:![0-9]+]] // FINITEONLY: _ZL6rnormfiPKf.exit: -// FINITEONLY-NEXT: [[__R_0_LCSSA_I:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ] -// FINITEONLY-NEXT: [[CALL_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_rsqrt_f32(float noundef nofpclass(nan inf) [[__R_0_LCSSA_I]]) #[[ATTR15]] +// FINITEONLY-NEXT: [[__R_0_I_LCSSA:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ] +// FINITEONLY-NEXT: [[CALL_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_rsqrt_f32(float noundef nofpclass(nan inf) [[__R_0_I_LCSSA]]) #[[ATTR15]] // FINITEONLY-NEXT: ret float [[CALL_I]] // // APPROX-LABEL: @test_rnormf( // APPROX-NEXT: entry: -// APPROX-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X:%.*]], 0 -// APPROX-NEXT: br i1 [[TOBOOL_NOT5_I]], label [[_ZL6RNORMFIPKF_EXIT:%.*]], label [[WHILE_BODY_I:%.*]] +// APPROX-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X:%.*]], 0 +// APPROX-NEXT: br i1 [[TOBOOL_NOT_I1]], label [[_ZL6RNORMFIPKF_EXIT:%.*]], label [[WHILE_BODY_I:%.*]] // APPROX: while.body.i: -// APPROX-NEXT: [[__R_08_I:%.*]] = phi float [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] -// APPROX-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ] -// APPROX-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ] -// APPROX-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 -// APPROX-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_07_I]], align 4, !tbaa [[TBAA16]] +// APPROX-NEXT: [[__R_0_I4:%.*]] = phi float [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] +// APPROX-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ] +// APPROX-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ] +// APPROX-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 +// APPROX-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_0_I3]], align 4, !tbaa [[TBAA16]] // APPROX-NEXT: [[MUL_I:%.*]] = fmul contract float [[TMP0]], [[TMP0]] -// APPROX-NEXT: [[ADD_I]] = fadd contract float [[__R_08_I]], [[MUL_I]] -// APPROX-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds float, ptr [[__A_ADDR_07_I]], i64 1 +// APPROX-NEXT: [[ADD_I]] = fadd contract float [[__R_0_I4]], [[MUL_I]] +// APPROX-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds float, ptr [[__A_ADDR_0_I3]], i64 1 // APPROX-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 // APPROX-NEXT: br i1 [[TOBOOL_NOT_I]], label [[_ZL6RNORMFIPKF_EXIT]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP22:![0-9]+]] // APPROX: _ZL6rnormfiPKf.exit: -// APPROX-NEXT: [[__R_0_LCSSA_I:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ] -// APPROX-NEXT: [[CALL_I:%.*]] = tail call contract noundef float @__ocml_rsqrt_f32(float noundef [[__R_0_LCSSA_I]]) #[[ATTR15]] +// APPROX-NEXT: [[__R_0_I_LCSSA:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ] +// APPROX-NEXT: [[CALL_I:%.*]] = tail call contract noundef float @__ocml_rsqrt_f32(float noundef [[__R_0_I_LCSSA]]) #[[ATTR15]] // APPROX-NEXT: ret float [[CALL_I]] // extern "C" __device__ float test_rnormf(int x, const float* y) { @@ -3307,62 +3307,62 @@ extern "C" __device__ float test_rnormf(int x, const float* y) { // DEFAULT-LABEL: @test_rnorm( // DEFAULT-NEXT: entry: -// DEFAULT-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X:%.*]], 0 -// DEFAULT-NEXT: br i1 [[TOBOOL_NOT5_I]], label [[_ZL5RNORMIPKD_EXIT:%.*]], label [[WHILE_BODY_I:%.*]] +// DEFAULT-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X:%.*]], 0 +// DEFAULT-NEXT: br i1 [[TOBOOL_NOT_I1]], label [[_ZL5RNORMIPKD_EXIT:%.*]], label [[WHILE_BODY_I:%.*]] // DEFAULT: while.body.i: -// DEFAULT-NEXT: [[__R_08_I:%.*]] = phi double [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] -// DEFAULT-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ] -// DEFAULT-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ] -// DEFAULT-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 -// DEFAULT-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_07_I]], align 8, !tbaa [[TBAA18]] +// DEFAULT-NEXT: [[__R_0_I4:%.*]] = phi double [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] +// DEFAULT-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ] +// DEFAULT-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ] +// DEFAULT-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 +// DEFAULT-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_0_I3]], align 8, !tbaa [[TBAA18]] // DEFAULT-NEXT: [[MUL_I:%.*]] = fmul contract double [[TMP0]], [[TMP0]] -// DEFAULT-NEXT: [[ADD_I]] = fadd contract double [[__R_08_I]], [[MUL_I]] -// DEFAULT-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds double, ptr [[__A_ADDR_07_I]], i64 1 +// DEFAULT-NEXT: [[ADD_I]] = fadd contract double [[__R_0_I4]], [[MUL_I]] +// DEFAULT-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds double, ptr [[__A_ADDR_0_I3]], i64 1 // DEFAULT-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 // DEFAULT-NEXT: br i1 [[TOBOOL_NOT_I]], label [[_ZL5RNORMIPKD_EXIT]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP23:![0-9]+]] // DEFAULT: _ZL5rnormiPKd.exit: -// DEFAULT-NEXT: [[__R_0_LCSSA_I:%.*]] = phi double [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ] -// DEFAULT-NEXT: [[CALL_I:%.*]] = tail call contract noundef double @__ocml_rsqrt_f64(double noundef [[__R_0_LCSSA_I]]) #[[ATTR15]] +// DEFAULT-NEXT: [[__R_0_I_LCSSA:%.*]] = phi double [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ] +// DEFAULT-NEXT: [[CALL_I:%.*]] = tail call contract noundef double @__ocml_rsqrt_f64(double noundef [[__R_0_I_LCSSA]]) #[[ATTR15]] // DEFAULT-NEXT: ret double [[CALL_I]] // // FINITEONLY-LABEL: @test_rnorm( // FINITEONLY-NEXT: entry: -// FINITEONLY-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X:%.*]], 0 -// FINITEONLY-NEXT: br i1 [[TOBOOL_NOT5_I]], label [[_ZL5RNORMIPKD_EXIT:%.*]], label [[WHILE_BODY_I:%.*]] +// FINITEONLY-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X:%.*]], 0 +// FINITEONLY-NEXT: br i1 [[TOBOOL_NOT_I1]], label [[_ZL5RNORMIPKD_EXIT:%.*]], label [[WHILE_BODY_I:%.*]] // FINITEONLY: while.body.i: -// FINITEONLY-NEXT: [[__R_08_I:%.*]] = phi double [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] -// FINITEONLY-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ] -// FINITEONLY-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ] -// FINITEONLY-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 -// FINITEONLY-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_07_I]], align 8, !tbaa [[TBAA18]] +// FINITEONLY-NEXT: [[__R_0_I4:%.*]] = phi double [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] +// FINITEONLY-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ] +// FINITEONLY-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ] +// FINITEONLY-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 +// FINITEONLY-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_0_I3]], align 8, !tbaa [[TBAA18]] // FINITEONLY-NEXT: [[MUL_I:%.*]] = fmul nnan ninf contract double [[TMP0]], [[TMP0]] -// FINITEONLY-NEXT: [[ADD_I]] = fadd nnan ninf contract double [[__R_08_I]], [[MUL_I]] -// FINITEONLY-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds double, ptr [[__A_ADDR_07_I]], i64 1 +// FINITEONLY-NEXT: [[ADD_I]] = fadd nnan ninf contract double [[__R_0_I4]], [[MUL_I]] +// FINITEONLY-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds double, ptr [[__A_ADDR_0_I3]], i64 1 // FINITEONLY-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 // FINITEONLY-NEXT: br i1 [[TOBOOL_NOT_I]], label [[_ZL5RNORMIPKD_EXIT]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP23:![0-9]+]] // FINITEONLY: _ZL5rnormiPKd.exit: -// FINITEONLY-NEXT: [[__R_0_LCSSA_I:%.*]] = phi double [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ] -// FINITEONLY-NEXT: [[CALL_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_rsqrt_f64(double noundef nofpclass(nan inf) [[__R_0_LCSSA_I]]) #[[ATTR15]] +// FINITEONLY-NEXT: [[__R_0_I_LCSSA:%.*]] = phi double [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ] +// FINITEONLY-NEXT: [[CALL_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_rsqrt_f64(double noundef nofpclass(nan inf) [[__R_0_I_LCSSA]]) #[[ATTR15]] // FINITEONLY-NEXT: ret double [[CALL_I]] // // APPROX-LABEL: @test_rnorm( // APPROX-NEXT: entry: -// APPROX-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X:%.*]], 0 -// APPROX-NEXT: br i1 [[TOBOOL_NOT5_I]], label [[_ZL5RNORMIPKD_EXIT:%.*]], label [[WHILE_BODY_I:%.*]] +// APPROX-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X:%.*]], 0 +// APPROX-NEXT: br i1 [[TOBOOL_NOT_I1]], label [[_ZL5RNORMIPKD_EXIT:%.*]], label [[WHILE_BODY_I:%.*]] // APPROX: while.body.i: -// APPROX-NEXT: [[__R_08_I:%.*]] = phi double [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] -// APPROX-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ] -// APPROX-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ] -// APPROX-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 -// APPROX-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_07_I]], align 8, !tbaa [[TBAA18]] +// APPROX-NEXT: [[__R_0_I4:%.*]] = phi double [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] +// APPROX-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ] +// APPROX-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ] +// APPROX-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 +// APPROX-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_0_I3]], align 8, !tbaa [[TBAA18]] // APPROX-NEXT: [[MUL_I:%.*]] = fmul contract double [[TMP0]], [[TMP0]] -// APPROX-NEXT: [[ADD_I]] = fadd contract double [[__R_08_I]], [[MUL_I]] -// APPROX-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds double, ptr [[__A_ADDR_07_I]], i64 1 +// APPROX-NEXT: [[ADD_I]] = fadd contract double [[__R_0_I4]], [[MUL_I]] +// APPROX-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds double, ptr [[__A_ADDR_0_I3]], i64 1 // APPROX-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 // APPROX-NEXT: br i1 [[TOBOOL_NOT_I]], label [[_ZL5RNORMIPKD_EXIT]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP23:![0-9]+]] // APPROX: _ZL5rnormiPKd.exit: -// APPROX-NEXT: [[__R_0_LCSSA_I:%.*]] = phi double [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ] -// APPROX-NEXT: [[CALL_I:%.*]] = tail call contract noundef double @__ocml_rsqrt_f64(double noundef [[__R_0_LCSSA_I]]) #[[ATTR15]] +// APPROX-NEXT: [[__R_0_I_LCSSA:%.*]] = phi double [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ] +// APPROX-NEXT: [[CALL_I:%.*]] = tail call contract noundef double @__ocml_rsqrt_f64(double noundef [[__R_0_I_LCSSA]]) #[[ATTR15]] // APPROX-NEXT: ret double [[CALL_I]] // extern "C" __device__ double test_rnorm(int x, const double* y) { @@ -3838,8 +3838,8 @@ extern "C" __device__ void test_sincospi(double x, double *y, double *z) { // // APPROX-LABEL: @test_sinf( // APPROX-NEXT: entry: -// APPROX-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_native_sin_f32(float noundef [[X:%.*]]) #[[ATTR16]] -// APPROX-NEXT: ret float [[CALL_I_I]] +// APPROX-NEXT: [[CALL_I1:%.*]] = tail call contract noundef float @__ocml_native_sin_f32(float noundef [[X:%.*]]) #[[ATTR16]] +// APPROX-NEXT: ret float [[CALL_I1]] // extern "C" __device__ float test_sinf(float x) { return sinf(x); @@ -4175,30 +4175,30 @@ extern "C" __device__ double test_y1(double x) { // DEFAULT-NEXT: i32 1, label [[IF_THEN2_I:%.*]] // DEFAULT-NEXT: ] // DEFAULT: if.then.i: -// DEFAULT-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_y0_f32(float noundef [[Y:%.*]]) #[[ATTR16]] +// DEFAULT-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef float @__ocml_y0_f32(float noundef [[Y:%.*]]) #[[ATTR16]] // DEFAULT-NEXT: br label [[_ZL3YNFIF_EXIT:%.*]] // DEFAULT: if.then2.i: -// DEFAULT-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR16]] +// DEFAULT-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR16]] // DEFAULT-NEXT: br label [[_ZL3YNFIF_EXIT]] // DEFAULT: if.end4.i: -// DEFAULT-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef float @__ocml_y0_f32(float noundef [[Y]]) #[[ATTR16]] -// DEFAULT-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR16]] -// DEFAULT-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 -// DEFAULT-NEXT: br i1 [[CMP723_I]], label [[FOR_BODY_I:%.*]], label [[_ZL3YNFIF_EXIT]] +// DEFAULT-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_y0_f32(float noundef [[Y]]) #[[ATTR16]] +// DEFAULT-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR16]] +// DEFAULT-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 +// DEFAULT-NEXT: br i1 [[CMP7_I1]], label [[FOR_BODY_I:%.*]], label [[_ZL3YNFIF_EXIT]] // DEFAULT: for.body.i: -// DEFAULT-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ] -// DEFAULT-NEXT: [[__X1_025_I:%.*]] = phi float [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I22_I]], [[IF_END4_I]] ] -// DEFAULT-NEXT: [[__X0_024_I:%.*]] = phi float [ [[__X1_025_I]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ] -// DEFAULT-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 +// DEFAULT-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ] +// DEFAULT-NEXT: [[__X1_0_I3:%.*]] = phi float [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ] +// DEFAULT-NEXT: [[__X0_0_I2:%.*]] = phi float [ [[__X1_0_I3]], [[FOR_BODY_I]] ], [ [[CALL_I_I]], [[IF_END4_I]] ] +// DEFAULT-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 // DEFAULT-NEXT: [[CONV_I:%.*]] = sitofp i32 [[MUL_I]] to float // DEFAULT-NEXT: [[DIV_I:%.*]] = fdiv contract float [[CONV_I]], [[Y]] -// DEFAULT-NEXT: [[MUL8_I:%.*]] = fmul contract float [[__X1_025_I]], [[DIV_I]] -// DEFAULT-NEXT: [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_024_I]] -// DEFAULT-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 -// DEFAULT-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// DEFAULT-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZL3YNFIF_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP24:![0-9]+]] +// DEFAULT-NEXT: [[MUL8_I:%.*]] = fmul contract float [[__X1_0_I3]], [[DIV_I]] +// DEFAULT-NEXT: [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_0_I2]] +// DEFAULT-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 +// DEFAULT-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// DEFAULT-NEXT: br i1 [[EXITCOND_NOT]], label [[_ZL3YNFIF_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP24:![0-9]+]] // DEFAULT: _ZL3ynfif.exit: -// DEFAULT-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I_I]], [[IF_THEN_I]] ], [ [[CALL_I20_I]], [[IF_THEN2_I]] ], [ [[CALL_I22_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ] +// DEFAULT-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I20_I]], [[IF_THEN_I]] ], [ [[CALL_I22_I]], [[IF_THEN2_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ] // DEFAULT-NEXT: ret float [[RETVAL_0_I]] // // FINITEONLY-LABEL: @test_ynf( @@ -4208,30 +4208,30 @@ extern "C" __device__ double test_y1(double x) { // FINITEONLY-NEXT: i32 1, label [[IF_THEN2_I:%.*]] // FINITEONLY-NEXT: ] // FINITEONLY: if.then.i: -// FINITEONLY-NEXT: [[CALL_I_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_y0_f32(float noundef nofpclass(nan inf) [[Y:%.*]]) #[[ATTR16]] +// FINITEONLY-NEXT: [[CALL_I20_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_y0_f32(float noundef nofpclass(nan inf) [[Y:%.*]]) #[[ATTR16]] // FINITEONLY-NEXT: br label [[_ZL3YNFIF_EXIT:%.*]] // FINITEONLY: if.then2.i: -// FINITEONLY-NEXT: [[CALL_I20_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_y1_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR16]] +// FINITEONLY-NEXT: [[CALL_I22_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_y1_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR16]] // FINITEONLY-NEXT: br label [[_ZL3YNFIF_EXIT]] // FINITEONLY: if.end4.i: -// FINITEONLY-NEXT: [[CALL_I21_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_y0_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR16]] -// FINITEONLY-NEXT: [[CALL_I22_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_y1_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR16]] -// FINITEONLY-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 -// FINITEONLY-NEXT: br i1 [[CMP723_I]], label [[FOR_BODY_I:%.*]], label [[_ZL3YNFIF_EXIT]] +// FINITEONLY-NEXT: [[CALL_I_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_y0_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR16]] +// FINITEONLY-NEXT: [[CALL_I21_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_y1_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR16]] +// FINITEONLY-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 +// FINITEONLY-NEXT: br i1 [[CMP7_I1]], label [[FOR_BODY_I:%.*]], label [[_ZL3YNFIF_EXIT]] // FINITEONLY: for.body.i: -// FINITEONLY-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ] -// FINITEONLY-NEXT: [[__X1_025_I:%.*]] = phi float [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I22_I]], [[IF_END4_I]] ] -// FINITEONLY-NEXT: [[__X0_024_I:%.*]] = phi float [ [[__X1_025_I]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ] -// FINITEONLY-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 +// FINITEONLY-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ] +// FINITEONLY-NEXT: [[__X1_0_I3:%.*]] = phi float [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ] +// FINITEONLY-NEXT: [[__X0_0_I2:%.*]] = phi float [ [[__X1_0_I3]], [[FOR_BODY_I]] ], [ [[CALL_I_I]], [[IF_END4_I]] ] +// FINITEONLY-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 // FINITEONLY-NEXT: [[CONV_I:%.*]] = sitofp i32 [[MUL_I]] to float // FINITEONLY-NEXT: [[DIV_I:%.*]] = fdiv nnan ninf contract float [[CONV_I]], [[Y]] -// FINITEONLY-NEXT: [[MUL8_I:%.*]] = fmul nnan ninf contract float [[__X1_025_I]], [[DIV_I]] -// FINITEONLY-NEXT: [[SUB_I]] = fsub nnan ninf contract float [[MUL8_I]], [[__X0_024_I]] -// FINITEONLY-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 -// FINITEONLY-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// FINITEONLY-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZL3YNFIF_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP24:![0-9]+]] +// FINITEONLY-NEXT: [[MUL8_I:%.*]] = fmul nnan ninf contract float [[__X1_0_I3]], [[DIV_I]] +// FINITEONLY-NEXT: [[SUB_I]] = fsub nnan ninf contract float [[MUL8_I]], [[__X0_0_I2]] +// FINITEONLY-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 +// FINITEONLY-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// FINITEONLY-NEXT: br i1 [[EXITCOND_NOT]], label [[_ZL3YNFIF_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP24:![0-9]+]] // FINITEONLY: _ZL3ynfif.exit: -// FINITEONLY-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I_I]], [[IF_THEN_I]] ], [ [[CALL_I20_I]], [[IF_THEN2_I]] ], [ [[CALL_I22_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ] +// FINITEONLY-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I20_I]], [[IF_THEN_I]] ], [ [[CALL_I22_I]], [[IF_THEN2_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ] // FINITEONLY-NEXT: ret float [[RETVAL_0_I]] // // APPROX-LABEL: @test_ynf( @@ -4241,30 +4241,30 @@ extern "C" __device__ double test_y1(double x) { // APPROX-NEXT: i32 1, label [[IF_THEN2_I:%.*]] // APPROX-NEXT: ] // APPROX: if.then.i: -// APPROX-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_y0_f32(float noundef [[Y:%.*]]) #[[ATTR16]] +// APPROX-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef float @__ocml_y0_f32(float noundef [[Y:%.*]]) #[[ATTR16]] // APPROX-NEXT: br label [[_ZL3YNFIF_EXIT:%.*]] // APPROX: if.then2.i: -// APPROX-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR16]] +// APPROX-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR16]] // APPROX-NEXT: br label [[_ZL3YNFIF_EXIT]] // APPROX: if.end4.i: -// APPROX-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef float @__ocml_y0_f32(float noundef [[Y]]) #[[ATTR16]] -// APPROX-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR16]] -// APPROX-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 -// APPROX-NEXT: br i1 [[CMP723_I]], label [[FOR_BODY_I:%.*]], label [[_ZL3YNFIF_EXIT]] +// APPROX-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_y0_f32(float noundef [[Y]]) #[[ATTR16]] +// APPROX-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR16]] +// APPROX-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 +// APPROX-NEXT: br i1 [[CMP7_I1]], label [[FOR_BODY_I:%.*]], label [[_ZL3YNFIF_EXIT]] // APPROX: for.body.i: -// APPROX-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ] -// APPROX-NEXT: [[__X1_025_I:%.*]] = phi float [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I22_I]], [[IF_END4_I]] ] -// APPROX-NEXT: [[__X0_024_I:%.*]] = phi float [ [[__X1_025_I]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ] -// APPROX-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 +// APPROX-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ] +// APPROX-NEXT: [[__X1_0_I3:%.*]] = phi float [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ] +// APPROX-NEXT: [[__X0_0_I2:%.*]] = phi float [ [[__X1_0_I3]], [[FOR_BODY_I]] ], [ [[CALL_I_I]], [[IF_END4_I]] ] +// APPROX-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 // APPROX-NEXT: [[CONV_I:%.*]] = sitofp i32 [[MUL_I]] to float // APPROX-NEXT: [[DIV_I:%.*]] = fdiv contract float [[CONV_I]], [[Y]] -// APPROX-NEXT: [[MUL8_I:%.*]] = fmul contract float [[__X1_025_I]], [[DIV_I]] -// APPROX-NEXT: [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_024_I]] -// APPROX-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 -// APPROX-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// APPROX-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZL3YNFIF_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP24:![0-9]+]] +// APPROX-NEXT: [[MUL8_I:%.*]] = fmul contract float [[__X1_0_I3]], [[DIV_I]] +// APPROX-NEXT: [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_0_I2]] +// APPROX-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 +// APPROX-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// APPROX-NEXT: br i1 [[EXITCOND_NOT]], label [[_ZL3YNFIF_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP24:![0-9]+]] // APPROX: _ZL3ynfif.exit: -// APPROX-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I_I]], [[IF_THEN_I]] ], [ [[CALL_I20_I]], [[IF_THEN2_I]] ], [ [[CALL_I22_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ] +// APPROX-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I20_I]], [[IF_THEN_I]] ], [ [[CALL_I22_I]], [[IF_THEN2_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ] // APPROX-NEXT: ret float [[RETVAL_0_I]] // extern "C" __device__ float test_ynf(int x, float y) { @@ -4278,30 +4278,30 @@ extern "C" __device__ float test_ynf(int x, float y) { // DEFAULT-NEXT: i32 1, label [[IF_THEN2_I:%.*]] // DEFAULT-NEXT: ] // DEFAULT: if.then.i: -// DEFAULT-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef double @__ocml_y0_f64(double noundef [[Y:%.*]]) #[[ATTR16]] +// DEFAULT-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef double @__ocml_y0_f64(double noundef [[Y:%.*]]) #[[ATTR16]] // DEFAULT-NEXT: br label [[_ZL2YNID_EXIT:%.*]] // DEFAULT: if.then2.i: -// DEFAULT-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR16]] +// DEFAULT-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR16]] // DEFAULT-NEXT: br label [[_ZL2YNID_EXIT]] // DEFAULT: if.end4.i: -// DEFAULT-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef double @__ocml_y0_f64(double noundef [[Y]]) #[[ATTR16]] -// DEFAULT-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR16]] -// DEFAULT-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 -// DEFAULT-NEXT: br i1 [[CMP723_I]], label [[FOR_BODY_I:%.*]], label [[_ZL2YNID_EXIT]] +// DEFAULT-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef double @__ocml_y0_f64(double noundef [[Y]]) #[[ATTR16]] +// DEFAULT-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR16]] +// DEFAULT-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 +// DEFAULT-NEXT: br i1 [[CMP7_I1]], label [[FOR_BODY_I:%.*]], label [[_ZL2YNID_EXIT]] // DEFAULT: for.body.i: -// DEFAULT-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ] -// DEFAULT-NEXT: [[__X1_025_I:%.*]] = phi double [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I22_I]], [[IF_END4_I]] ] -// DEFAULT-NEXT: [[__X0_024_I:%.*]] = phi double [ [[__X1_025_I]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ] -// DEFAULT-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 +// DEFAULT-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ] +// DEFAULT-NEXT: [[__X1_0_I3:%.*]] = phi double [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ] +// DEFAULT-NEXT: [[__X0_0_I2:%.*]] = phi double [ [[__X1_0_I3]], [[FOR_BODY_I]] ], [ [[CALL_I_I]], [[IF_END4_I]] ] +// DEFAULT-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 // DEFAULT-NEXT: [[CONV_I:%.*]] = sitofp i32 [[MUL_I]] to double // DEFAULT-NEXT: [[DIV_I:%.*]] = fdiv contract double [[CONV_I]], [[Y]] -// DEFAULT-NEXT: [[MUL8_I:%.*]] = fmul contract double [[__X1_025_I]], [[DIV_I]] -// DEFAULT-NEXT: [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_024_I]] -// DEFAULT-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 -// DEFAULT-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// DEFAULT-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZL2YNID_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP25:![0-9]+]] +// DEFAULT-NEXT: [[MUL8_I:%.*]] = fmul contract double [[__X1_0_I3]], [[DIV_I]] +// DEFAULT-NEXT: [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_0_I2]] +// DEFAULT-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 +// DEFAULT-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// DEFAULT-NEXT: br i1 [[EXITCOND_NOT]], label [[_ZL2YNID_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP25:![0-9]+]] // DEFAULT: _ZL2ynid.exit: -// DEFAULT-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I_I]], [[IF_THEN_I]] ], [ [[CALL_I20_I]], [[IF_THEN2_I]] ], [ [[CALL_I22_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ] +// DEFAULT-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I20_I]], [[IF_THEN_I]] ], [ [[CALL_I22_I]], [[IF_THEN2_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ] // DEFAULT-NEXT: ret double [[RETVAL_0_I]] // // FINITEONLY-LABEL: @test_yn( @@ -4311,30 +4311,30 @@ extern "C" __device__ float test_ynf(int x, float y) { // FINITEONLY-NEXT: i32 1, label [[IF_THEN2_I:%.*]] // FINITEONLY-NEXT: ] // FINITEONLY: if.then.i: -// FINITEONLY-NEXT: [[CALL_I_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_y0_f64(double noundef nofpclass(nan inf) [[Y:%.*]]) #[[ATTR16]] +// FINITEONLY-NEXT: [[CALL_I20_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_y0_f64(double noundef nofpclass(nan inf) [[Y:%.*]]) #[[ATTR16]] // FINITEONLY-NEXT: br label [[_ZL2YNID_EXIT:%.*]] // FINITEONLY: if.then2.i: -// FINITEONLY-NEXT: [[CALL_I20_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_y1_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR16]] +// FINITEONLY-NEXT: [[CALL_I22_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_y1_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR16]] // FINITEONLY-NEXT: br label [[_ZL2YNID_EXIT]] // FINITEONLY: if.end4.i: -// FINITEONLY-NEXT: [[CALL_I21_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_y0_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR16]] -// FINITEONLY-NEXT: [[CALL_I22_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_y1_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR16]] -// FINITEONLY-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 -// FINITEONLY-NEXT: br i1 [[CMP723_I]], label [[FOR_BODY_I:%.*]], label [[_ZL2YNID_EXIT]] +// FINITEONLY-NEXT: [[CALL_I_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_y0_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR16]] +// FINITEONLY-NEXT: [[CALL_I21_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_y1_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR16]] +// FINITEONLY-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 +// FINITEONLY-NEXT: br i1 [[CMP7_I1]], label [[FOR_BODY_I:%.*]], label [[_ZL2YNID_EXIT]] // FINITEONLY: for.body.i: -// FINITEONLY-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ] -// FINITEONLY-NEXT: [[__X1_025_I:%.*]] = phi double [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I22_I]], [[IF_END4_I]] ] -// FINITEONLY-NEXT: [[__X0_024_I:%.*]] = phi double [ [[__X1_025_I]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ] -// FINITEONLY-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 +// FINITEONLY-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ] +// FINITEONLY-NEXT: [[__X1_0_I3:%.*]] = phi double [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ] +// FINITEONLY-NEXT: [[__X0_0_I2:%.*]] = phi double [ [[__X1_0_I3]], [[FOR_BODY_I]] ], [ [[CALL_I_I]], [[IF_END4_I]] ] +// FINITEONLY-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 // FINITEONLY-NEXT: [[CONV_I:%.*]] = sitofp i32 [[MUL_I]] to double // FINITEONLY-NEXT: [[DIV_I:%.*]] = fdiv nnan ninf contract double [[CONV_I]], [[Y]] -// FINITEONLY-NEXT: [[MUL8_I:%.*]] = fmul nnan ninf contract double [[__X1_025_I]], [[DIV_I]] -// FINITEONLY-NEXT: [[SUB_I]] = fsub nnan ninf contract double [[MUL8_I]], [[__X0_024_I]] -// FINITEONLY-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 -// FINITEONLY-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// FINITEONLY-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZL2YNID_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP25:![0-9]+]] +// FINITEONLY-NEXT: [[MUL8_I:%.*]] = fmul nnan ninf contract double [[__X1_0_I3]], [[DIV_I]] +// FINITEONLY-NEXT: [[SUB_I]] = fsub nnan ninf contract double [[MUL8_I]], [[__X0_0_I2]] +// FINITEONLY-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 +// FINITEONLY-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// FINITEONLY-NEXT: br i1 [[EXITCOND_NOT]], label [[_ZL2YNID_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP25:![0-9]+]] // FINITEONLY: _ZL2ynid.exit: -// FINITEONLY-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I_I]], [[IF_THEN_I]] ], [ [[CALL_I20_I]], [[IF_THEN2_I]] ], [ [[CALL_I22_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ] +// FINITEONLY-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I20_I]], [[IF_THEN_I]] ], [ [[CALL_I22_I]], [[IF_THEN2_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ] // FINITEONLY-NEXT: ret double [[RETVAL_0_I]] // // APPROX-LABEL: @test_yn( @@ -4344,30 +4344,30 @@ extern "C" __device__ float test_ynf(int x, float y) { // APPROX-NEXT: i32 1, label [[IF_THEN2_I:%.*]] // APPROX-NEXT: ] // APPROX: if.then.i: -// APPROX-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef double @__ocml_y0_f64(double noundef [[Y:%.*]]) #[[ATTR16]] +// APPROX-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef double @__ocml_y0_f64(double noundef [[Y:%.*]]) #[[ATTR16]] // APPROX-NEXT: br label [[_ZL2YNID_EXIT:%.*]] // APPROX: if.then2.i: -// APPROX-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR16]] +// APPROX-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR16]] // APPROX-NEXT: br label [[_ZL2YNID_EXIT]] // APPROX: if.end4.i: -// APPROX-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef double @__ocml_y0_f64(double noundef [[Y]]) #[[ATTR16]] -// APPROX-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR16]] -// APPROX-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 -// APPROX-NEXT: br i1 [[CMP723_I]], label [[FOR_BODY_I:%.*]], label [[_ZL2YNID_EXIT]] +// APPROX-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef double @__ocml_y0_f64(double noundef [[Y]]) #[[ATTR16]] +// APPROX-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR16]] +// APPROX-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 +// APPROX-NEXT: br i1 [[CMP7_I1]], label [[FOR_BODY_I:%.*]], label [[_ZL2YNID_EXIT]] // APPROX: for.body.i: -// APPROX-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ] -// APPROX-NEXT: [[__X1_025_I:%.*]] = phi double [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I22_I]], [[IF_END4_I]] ] -// APPROX-NEXT: [[__X0_024_I:%.*]] = phi double [ [[__X1_025_I]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ] -// APPROX-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 +// APPROX-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ] +// APPROX-NEXT: [[__X1_0_I3:%.*]] = phi double [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ] +// APPROX-NEXT: [[__X0_0_I2:%.*]] = phi double [ [[__X1_0_I3]], [[FOR_BODY_I]] ], [ [[CALL_I_I]], [[IF_END4_I]] ] +// APPROX-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 // APPROX-NEXT: [[CONV_I:%.*]] = sitofp i32 [[MUL_I]] to double // APPROX-NEXT: [[DIV_I:%.*]] = fdiv contract double [[CONV_I]], [[Y]] -// APPROX-NEXT: [[MUL8_I:%.*]] = fmul contract double [[__X1_025_I]], [[DIV_I]] -// APPROX-NEXT: [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_024_I]] -// APPROX-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 -// APPROX-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// APPROX-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZL2YNID_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP25:![0-9]+]] +// APPROX-NEXT: [[MUL8_I:%.*]] = fmul contract double [[__X1_0_I3]], [[DIV_I]] +// APPROX-NEXT: [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_0_I2]] +// APPROX-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 +// APPROX-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// APPROX-NEXT: br i1 [[EXITCOND_NOT]], label [[_ZL2YNID_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP25:![0-9]+]] // APPROX: _ZL2ynid.exit: -// APPROX-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I_I]], [[IF_THEN_I]] ], [ [[CALL_I20_I]], [[IF_THEN2_I]] ], [ [[CALL_I22_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ] +// APPROX-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I20_I]], [[IF_THEN_I]] ], [ [[CALL_I22_I]], [[IF_THEN2_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ] // APPROX-NEXT: ret double [[RETVAL_0_I]] // extern "C" __device__ double test_yn(int x, double y) { @@ -4742,26 +4742,26 @@ extern "C" __device__ float test___sinf(float x) { // DEFAULT-LABEL: @test___tanf( // DEFAULT-NEXT: entry: -// DEFAULT-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_native_sin_f32(float noundef [[X:%.*]]) #[[ATTR16]] -// DEFAULT-NEXT: [[CALL_I3_I:%.*]] = tail call contract noundef float @__ocml_native_cos_f32(float noundef [[X]]) #[[ATTR16]] -// DEFAULT-NEXT: [[TMP0:%.*]] = tail call contract float @llvm.amdgcn.rcp.f32(float [[CALL_I3_I]]) -// DEFAULT-NEXT: [[MUL_I:%.*]] = fmul contract float [[CALL_I_I]], [[TMP0]] +// DEFAULT-NEXT: [[CALL_I3_I:%.*]] = tail call contract noundef float @__ocml_native_sin_f32(float noundef [[X:%.*]]) #[[ATTR16]] +// DEFAULT-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_native_cos_f32(float noundef [[X]]) #[[ATTR16]] +// DEFAULT-NEXT: [[TMP0:%.*]] = tail call contract float @llvm.amdgcn.rcp.f32(float [[CALL_I_I]]) +// DEFAULT-NEXT: [[MUL_I:%.*]] = fmul contract float [[CALL_I3_I]], [[TMP0]] // DEFAULT-NEXT: ret float [[MUL_I]] // // FINITEONLY-LABEL: @test___tanf( // FINITEONLY-NEXT: entry: -// FINITEONLY-NEXT: [[CALL_I_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_native_sin_f32(float noundef nofpclass(nan inf) [[X:%.*]]) #[[ATTR16]] -// FINITEONLY-NEXT: [[CALL_I3_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_native_cos_f32(float noundef nofpclass(nan inf) [[X]]) #[[ATTR16]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract float @llvm.amdgcn.rcp.f32(float [[CALL_I3_I]]) -// FINITEONLY-NEXT: [[MUL_I:%.*]] = fmul nnan ninf contract float [[CALL_I_I]], [[TMP0]] +// FINITEONLY-NEXT: [[CALL_I3_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_native_sin_f32(float noundef nofpclass(nan inf) [[X:%.*]]) #[[ATTR16]] +// FINITEONLY-NEXT: [[CALL_I_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_native_cos_f32(float noundef nofpclass(nan inf) [[X]]) #[[ATTR16]] +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract float @llvm.amdgcn.rcp.f32(float [[CALL_I_I]]) +// FINITEONLY-NEXT: [[MUL_I:%.*]] = fmul nnan ninf contract float [[CALL_I3_I]], [[TMP0]] // FINITEONLY-NEXT: ret float [[MUL_I]] // // APPROX-LABEL: @test___tanf( // APPROX-NEXT: entry: -// APPROX-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_native_sin_f32(float noundef [[X:%.*]]) #[[ATTR16]] -// APPROX-NEXT: [[CALL_I3_I:%.*]] = tail call contract noundef float @__ocml_native_cos_f32(float noundef [[X]]) #[[ATTR16]] -// APPROX-NEXT: [[TMP0:%.*]] = tail call contract float @llvm.amdgcn.rcp.f32(float [[CALL_I3_I]]) -// APPROX-NEXT: [[MUL_I:%.*]] = fmul contract float [[CALL_I_I]], [[TMP0]] +// APPROX-NEXT: [[CALL_I3_I:%.*]] = tail call contract noundef float @__ocml_native_sin_f32(float noundef [[X:%.*]]) #[[ATTR16]] +// APPROX-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_native_cos_f32(float noundef [[X]]) #[[ATTR16]] +// APPROX-NEXT: [[TMP0:%.*]] = tail call contract float @llvm.amdgcn.rcp.f32(float [[CALL_I_I]]) +// APPROX-NEXT: [[MUL_I:%.*]] = fmul contract float [[CALL_I3_I]], [[TMP0]] // APPROX-NEXT: ret float [[MUL_I]] // extern "C" __device__ float test___tanf(float x) { diff --git a/clang/test/Headers/stdckdint.c b/clang/test/Headers/stdckdint.c index 896c740360065..6b6d74a89d4c1 100644 --- a/clang/test/Headers/stdckdint.c +++ b/clang/test/Headers/stdckdint.c @@ -1,12 +1,14 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 +// RUN: %clang_cc1 -triple=x86_64 -emit-llvm -verify -std=c99 %s -o - | FileCheck %s +// RUN: %clang_cc1 -triple=x86_64 -emit-llvm -verify -std=c11 %s -o - | FileCheck %s +// RUN: %clang_cc1 -triple=x86_64 -emit-llvm -verify -std=c17 %s -o - | FileCheck %s // RUN: %clang_cc1 -triple=x86_64 -emit-llvm -verify -std=c23 %s -o - | FileCheck %s // expected-no-diagnostics +#include #include -_Static_assert(__STDC_VERSION_STDCKDINT_H__ == 202311L, ""); - // CHECK-LABEL: define dso_local zeroext i1 @test_ckd_add( // CHECK-SAME: ) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: entry: diff --git a/clang/test/Import/objc-param-decl/test.m b/clang/test/Import/objc-param-decl/test.m index dc98c31200193..f2b6aa0927295 100644 --- a/clang/test/Import/objc-param-decl/test.m +++ b/clang/test/Import/objc-param-decl/test.m @@ -5,7 +5,7 @@ // CHECK-SAME: FirstParam // CHECK-SAME: 'id' // CHECK-NEXT: ObjCTypeParamDecl -// CHECK-SAME: 'id':'id' +// CHECK-SAME: 'id' void expr() { Dictionary *d; diff --git a/clang/test/Index/annotate-comments-objc.m b/clang/test/Index/annotate-comments-objc.m index 6a48d9ae8f2cb..f013684c1a638 100644 --- a/clang/test/Index/annotate-comments-objc.m +++ b/clang/test/Index/annotate-comments-objc.m @@ -46,18 +46,23 @@ - (void)method1_isdoxy4; /*!< method1_isdoxy4 IS_DOXYGEN_SINGLE */ // attach unrelated comments in the following cases where tag decls are // embedded in declarators. -#define DECLARE_FUNCTIONS(suffix) \ - /** functionFromMacro IS_DOXYGEN_SINGLE */ \ - void functionFromMacro(void) { \ - typedef struct Struct_notdoxy Struct_notdoxy; \ - } \ - /** functionFromMacroWithSuffix IS_DOXYGEN_SINGLE */ \ - void functionFromMacro##suffix(void) { \ - typedef struct Struct_notdoxy Struct_notdoxy; \ - } - -/// IS_DOXYGEN_NOT_ATTACHED -DECLARE_FUNCTIONS(WithSuffix) +#define DECLARE_FUNCTIONS_COMMENTS_IN_MACRO(suffix) \ + /** functionFromMacro IS_DOXYGEN_SINGLE */ \ + void functionFromMacro(void) { \ + typedef struct Struct_notdoxy Struct_notdoxy; \ + } \ + /** functionFromMacroWithSuffix IS_DOXYGEN_SINGLE */ \ + void functionFromMacro##suffix(void) { \ + typedef struct Struct_notdoxy Struct_notdoxy; \ + } + +DECLARE_FUNCTIONS_COMMENTS_IN_MACRO(WithSuffix) + +#define DECLARE_FUNCTIONS \ + void functionFromMacroWithCommentFromExpansionSite(void) { typedef struct Struct_notdoxy Struct_notdoxy; } + +/// functionFromMacroWithCommentFromExpansionSite IS_DOXYGEN_SINGLE +DECLARE_FUNCTIONS /// typedef_isdoxy1 IS_DOXYGEN_SINGLE typedef struct Struct_notdoxy *typedef_isdoxy1; @@ -68,9 +73,14 @@ void functionFromMacro(void) { \ /** namedEnumFromMacro IS_DOXYGEN_SINGLE */ \ enum name { B }; -/// IS_DOXYGEN_NOT_ATTACHED DECLARE_ENUMS(namedEnumFromMacro) +#define MYENUM(name) enum name +struct Foo { + /// Vehicles IS_DOXYGEN_SINGLE + MYENUM(Vehicles) { Car, Motorbike, Boat} a; +}; + #endif // RUN: rm -rf %t @@ -133,8 +143,10 @@ void functionFromMacro(void) { \ // CHECK: annotate-comments-objc.m:41:22: EnumDecl=An_NS_ENUM_isdoxy1:{{.*}} An_NS_ENUM_isdoxy1 IS_DOXYGEN_SINGLE // CHECK: annotate-comments-objc.m:41:22: TypedefDecl=An_NS_ENUM_isdoxy1:{{.*}} An_NS_ENUM_isdoxy1 IS_DOXYGEN_SINGLE // CHECK: annotate-comments-objc.m:41:22: EnumDecl=An_NS_ENUM_isdoxy1:{{.*}} An_NS_ENUM_isdoxy1 IS_DOXYGEN_SINGLE -// CHECK: annotate-comments-objc.m:60:1: FunctionDecl=functionFromMacro:{{.*}} BriefComment=[functionFromMacro IS_DOXYGEN_SINGLE] -// CHECK: annotate-comments-objc.m:60:1: FunctionDecl=functionFromMacroWithSuffix:{{.*}} BriefComment=[functionFromMacroWithSuffix IS_DOXYGEN_SINGLE] -// CHECK: annotate-comments-objc.m:63:32: TypedefDecl=typedef_isdoxy1:{{.*}} typedef_isdoxy1 IS_DOXYGEN_SINGLE -// CHECK: annotate-comments-objc.m:72:1: EnumDecl=enumFromMacro:{{.*}} BriefComment=[enumFromMacro IS_DOXYGEN_SINGLE] -// CHECK: annotate-comments-objc.m:72:15: EnumDecl=namedEnumFromMacro:{{.*}} BriefComment=[namedEnumFromMacro IS_DOXYGEN_SINGLE] +// CHECK: annotate-comments-objc.m:59:1: FunctionDecl=functionFromMacro:{{.*}} BriefComment=[functionFromMacro IS_DOXYGEN_SINGLE] +// CHECK: annotate-comments-objc.m:59:1: FunctionDecl=functionFromMacroWithSuffix:{{.*}} BriefComment=[functionFromMacroWithSuffix IS_DOXYGEN_SINGLE] +// CHECK: annotate-comments-objc.m:65:1: FunctionDecl=functionFromMacroWithCommentFromExpansionSite:{{.*}} BriefComment=[functionFromMacroWithCommentFromExpansionSite IS_DOXYGEN_SINGLE] +// CHECK: annotate-comments-objc.m:68:32: TypedefDecl=typedef_isdoxy1:{{.*}} typedef_isdoxy1 IS_DOXYGEN_SINGLE +// CHECK: annotate-comments-objc.m:76:1: EnumDecl=enumFromMacro:{{.*}} BriefComment=[enumFromMacro IS_DOXYGEN_SINGLE] +// CHECK: annotate-comments-objc.m:76:15: EnumDecl=namedEnumFromMacro:{{.*}} BriefComment=[namedEnumFromMacro IS_DOXYGEN_SINGLE] +// CHECK: annotate-comments-objc.m:81:10: EnumDecl=Vehicles:{{.*}} Vehicles IS_DOXYGEN_SINGLE diff --git a/clang/test/Interpreter/simple-exception.cpp b/clang/test/Interpreter/simple-exception.cpp index 8741886a0a621..6749acd6e6bd2 100644 --- a/clang/test/Interpreter/simple-exception.cpp +++ b/clang/test/Interpreter/simple-exception.cpp @@ -1,7 +1,7 @@ // clang-format off // UNSUPPORTED: system-aix -// XFAIL for arm, arm64, riscv, or running on Windows. -// XFAIL: target={{(arm|riscv).*}}, system-windows +// XFAIL for arm and arm64, or running on Windows. +// XFAIL: target=arm{{.*}}, system-windows // RUN: cat %s | clang-repl | FileCheck %s // Incompatible with msan. It passes with -O3 but fail -Oz. Interpreter diff --git a/clang/test/Lexer/SourceLocationsOverflow.c b/clang/test/Lexer/SourceLocationsOverflow.c index 2b838ca4e861d..c42f648fedf50 100644 --- a/clang/test/Lexer/SourceLocationsOverflow.c +++ b/clang/test/Lexer/SourceLocationsOverflow.c @@ -1,6 +1,6 @@ // RUN: not %clang %s -S -o - 2>&1 | FileCheck %s // CHECK: In file included from {{.*}}SourceLocationsOverflow.c -// CHECK-NEXT: inc1.h{{.*}}: fatal error: sorry, this include generates a translation unit too large for Clang to process. +// CHECK-NEXT: inc1.h{{.*}}: fatal error: sorry, the translation unit is too large for Clang to process: ran out of source locations // CHECK-NEXT: #include "inc2.h" // CHECK-NEXT: ^ // CHECK-NEXT: note: 214{{.......}}B in local locations, 0B in locations loaded from AST files, for a total of 214{{.......}}B (99% of available space) diff --git a/clang/test/Misc/constexpr-source-ranges.cpp b/clang/test/Misc/constexpr-source-ranges.cpp index 7f5c522ae305b..fde05b5c75aa4 100644 --- a/clang/test/Misc/constexpr-source-ranges.cpp +++ b/clang/test/Misc/constexpr-source-ranges.cpp @@ -49,3 +49,7 @@ constexpr int uninit() { return aaa; } static_assert(uninit() == 0, ""); + + +constexpr void neverValid() { throw; } +// CHECK: :{[[@LINE-1]]:16-[[@LINE-1]]:26}: diff --git a/clang/test/Misc/misc-source-ranges.cpp b/clang/test/Misc/misc-source-ranges.cpp index 7a9d9d057dac4..1835952fd7559 100644 --- a/clang/test/Misc/misc-source-ranges.cpp +++ b/clang/test/Misc/misc-source-ranges.cpp @@ -1,7 +1,13 @@ -// RUN: not %clang_cc1 -fsyntax-only -fdiagnostics-print-source-range-info %s 2>&1 | FileCheck %s +// RUN: not %clang_cc1 -fsyntax-only -fdiagnostics-print-source-range-info -Wcast-function-type-strict %s 2>&1 | FileCheck %s struct S { char a : 12 - 12; }; // CHECK: misc-source-ranges.cpp:[[@LINE-2]]:8:{[[@LINE-2]]:12-[[@LINE-2]]:19} +using fun = long(*)(int &); +fun foo(){ + long (*f_ptr)(const int &); + return fun(f_ptr); +} +// CHECK: misc-source-ranges.cpp:[[@LINE-2]]:10:{[[@LINE-2]]:10-[[@LINE-2]]:20} diff --git a/clang/test/Misc/warning-wall.c b/clang/test/Misc/warning-wall.c index 57866713fc570..05a82770e26de 100644 --- a/clang/test/Misc/warning-wall.c +++ b/clang/test/Misc/warning-wall.c @@ -105,6 +105,7 @@ CHECK-NEXT: -Wswitch CHECK-NEXT: -Wswitch-bool CHECK-NEXT: -Wmisleading-indentation CHECK-NEXT: -Wpacked-non-pod - +CHECK-NEXT: -Wvla-cxx-extension +CHECK-NEXT: -Wvla-extension-static-assert CHECK-NOT:-W diff --git a/clang/test/Modules/Inputs/all-product-headers.yaml b/clang/test/Modules/Inputs/all-product-headers.yaml new file mode 100644 index 0000000000000..53d683f2ad2ec --- /dev/null +++ b/clang/test/Modules/Inputs/all-product-headers.yaml @@ -0,0 +1,33 @@ +{ + 'version': 0, + 'case-sensitive': 'false', + 'roots': [ + { + 'type': 'directory', + 'name': "DUMMY_DIR/build/A.framework/PrivateHeaders" + 'contents': [ + { + 'type': 'file', + 'name': "A.h", + 'external-contents': "DUMMY_DIR/sources/A.h" + } + ] + }, + { + 'type': 'directory', + 'name': "DUMMY_DIR/build/A.framework/Modules" + 'contents': [ + { + 'type': 'file', + 'name': "module.modulemap", + 'external-contents': "DUMMY_DIR/build/module.modulemap" + }, + { + 'type': 'file', + 'name': "module.private.modulemap", + 'external-contents': "DUMMY_DIR/build/module.private.modulemap" + } + ] + } + ] +} diff --git a/clang/test/Modules/Inputs/builtin-headers/module.modulemap b/clang/test/Modules/Inputs/builtin-headers/module.modulemap new file mode 100644 index 0000000000000..78a5b730dc6a9 --- /dev/null +++ b/clang/test/Modules/Inputs/builtin-headers/module.modulemap @@ -0,0 +1,3 @@ +module ModuleWithBuiltinHeader [system] { + header "float.h" +} \ No newline at end of file diff --git a/clang/test/Modules/duplicated-module-file-eq-module-name.cppm b/clang/test/Modules/duplicated-module-file-eq-module-name.cppm new file mode 100644 index 0000000000000..e86dbe2b941ef --- /dev/null +++ b/clang/test/Modules/duplicated-module-file-eq-module-name.cppm @@ -0,0 +1,21 @@ +// Tests that we will pick the last `-fmodule-file==` flag +// for . + +// RUN: rm -rf %t +// RUN: split-file %s %t +// RUN: cd %t +// +// RUN: %clang_cc1 -std=c++20 %t/a.cppm -emit-module-interface -o %t/a.pcm +// RUN: %clang_cc1 -std=c++20 %t/u.cpp -fmodule-file=a=%t/unexist.pcm \ +// RUN: -fmodule-file=a=%t/a.pcm -verify -fsyntax-only + +//--- a.cppm +export module a; +export int a(); + +//--- u.cpp +// expected-no-diagnostics +import a; +int u() { + return a(); +} diff --git a/clang/test/Modules/modulemap-collision.m b/clang/test/Modules/modulemap-collision.m new file mode 100644 index 0000000000000..5ada45da3dae1 --- /dev/null +++ b/clang/test/Modules/modulemap-collision.m @@ -0,0 +1,15 @@ +// REQUIRES: shell + +// RUN: rm -rf %t +// RUN: mkdir -p %t/sources %t/build +// RUN: echo "// A.h" > %t/sources/A.h +// RUN: echo "framework module A {}" > %t/sources/module.modulemap +// RUN: echo "framework module A.Private { umbrella header \"A.h\" }" > %t/sources/module.private.modulemap +// RUN: cp %t/sources/module.modulemap %t/build/module.modulemap +// RUN: cp %t/sources/module.private.modulemap %t/build/module.private.modulemap + +// RUN: sed -e "s:DUMMY_DIR:%t:g" %S/Inputs/all-product-headers.yaml > %t/build/all-product-headers.yaml +// RUN: %clang_cc1 -fsyntax-only -ivfsoverlay %t/build/all-product-headers.yaml -F%t/build -fmodules -fimplicit-module-maps -Wno-private-module -fmodules-cache-path=%t/cache -x objective-c %s -verify + +// expected-no-diagnostics +#import diff --git a/clang/test/Modules/no-undeclared-includes.c b/clang/test/Modules/no-undeclared-includes.c new file mode 100644 index 0000000000000..83a654f6ed775 --- /dev/null +++ b/clang/test/Modules/no-undeclared-includes.c @@ -0,0 +1,31 @@ +// RUN: rm -rf %t +// RUN: split-file %s %t +// RUN: %clang_cc1 -fmodules-cache-path=%t -fmodules -fimplicit-module-maps -I %t %t/no-undeclared-includes.c -verify + +//--- no-undeclared-includes.c +// expected-no-diagnostics +#include + +//--- assert.h +#include + +//--- base.h +#ifndef base_h +#define base_h + + + +#endif /* base_h */ + +//--- module.modulemap +module cstd [system] [no_undeclared_includes] { + use base + module assert { + textual header "assert.h" + } +} + +module base [system] { + header "base.h" + export * +} diff --git a/clang/test/Modules/relative-resource-dir.m b/clang/test/Modules/relative-resource-dir.m new file mode 100644 index 0000000000000..e0d1b6d221d10 --- /dev/null +++ b/clang/test/Modules/relative-resource-dir.m @@ -0,0 +1,12 @@ +// UNSUPPORTED: -zos, -aix +// REQUIRES: shell + +// RUN: EXPECTED_RESOURCE_DIR=`%clang -print-resource-dir` && \ +// RUN: mkdir -p %t && rm -rf %t/resource-dir && \ +// RUN: cp -R $EXPECTED_RESOURCE_DIR %t/resource-dir +// RUN: cd %t && %clang -cc1 -x objective-c -fmodules -fmodule-format=obj \ +// RUN: -fimplicit-module-maps -fmodules-cache-path=%t.mcp \ +// RUN: -fbuiltin-headers-in-system-modules \ +// RUN: -resource-dir resource-dir \ +// RUN: -emit-module %S/Inputs/builtin-headers/module.modulemap \ +// RUN: -fmodule-name=ModuleWithBuiltinHeader -o %t.pcm diff --git a/clang/test/OpenMP/align_clause_ast_print.cpp b/clang/test/OpenMP/align_clause_ast_print.cpp index 3ed602d533bc8..87000f9c41bae 100644 --- a/clang/test/OpenMP/align_clause_ast_print.cpp +++ b/clang/test/OpenMP/align_clause_ast_print.cpp @@ -122,7 +122,7 @@ int template_test() { // DUMP: NonTypeTemplateParmDecl {{.*}}'unsigned int' depth 0 index 1 size // DUMP: IntegerLiteral {{.*}}'unsigned int' 1 // DUMP: OMPAllocateDecl {{.*}} -// DUMP: DeclRefExpr {{.*}}'double':'double' lvalue Var {{.*}} 'foo' 'double':'double' +// DUMP: DeclRefExpr {{.*}}'double' lvalue Var {{.*}} 'foo' 'double' // DUMP: OMPAlignClause {{.*}} // DUMP: ConstantExpr {{.*}}'unsigned int' // DUMP: value: Int 1 diff --git a/clang/test/OpenMP/bug57757.cpp b/clang/test/OpenMP/bug57757.cpp index 7894796ac4628..7acfe134ddd0b 100644 --- a/clang/test/OpenMP/bug57757.cpp +++ b/clang/test/OpenMP/bug57757.cpp @@ -32,24 +32,23 @@ void foo() { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP1]], i64 0, i32 2 // CHECK-NEXT: tail call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) -// CHECK-NEXT: tail call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) -// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !tbaa [[TBAA18:![0-9]+]], !alias.scope !13, !noalias !16 +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !tbaa [[TBAA16:![0-9]+]], !alias.scope !13, !noalias !17 // CHECK-NEXT: switch i32 [[TMP3]], label [[DOTOMP_OUTLINED__EXIT:%.*]] [ // CHECK-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK-NEXT: i32 1, label [[DOTUNTIED_NEXT__I:%.*]] // CHECK-NEXT: ] // CHECK: .untied.jmp..i: -// CHECK-NEXT: store i32 1, ptr [[TMP2]], align 4, !tbaa [[TBAA18]], !alias.scope !13, !noalias !16 -// CHECK-NEXT: [[TMP4:%.*]] = tail call i32 @__kmpc_omp_task(ptr nonnull @[[GLOB1]], i32 [[TMP0]], ptr [[TMP1]]), !noalias !19 +// CHECK-NEXT: store i32 1, ptr [[TMP2]], align 4, !tbaa [[TBAA16]], !alias.scope !13, !noalias !17 +// CHECK-NEXT: [[TMP4:%.*]] = tail call i32 @__kmpc_omp_task(ptr nonnull @[[GLOB1]], i32 [[TMP0]], ptr [[TMP1]]), !noalias !13 // CHECK-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] // CHECK: .untied.next..i: // CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP1]], i64 0, i32 1 // CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP1]], i64 0, i32 1, i32 2 // CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP1]], i64 0, i32 1, i32 1 -// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP5]], align 8, !tbaa [[TBAA20:![0-9]+]], !alias.scope !16, !noalias !13 -// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4, !tbaa [[TBAA18]], !alias.scope !16, !noalias !13 -// CHECK-NEXT: [[TMP10:%.*]] = load float, ptr [[TMP6]], align 4, !tbaa [[TBAA21:![0-9]+]], !alias.scope !16, !noalias !13 -// CHECK-NEXT: tail call void [[TMP8]](i32 noundef [[TMP9]], float noundef [[TMP10]]) #[[ATTR2:[0-9]+]], !noalias !19 +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP5]], align 8, !tbaa [[TBAA19:![0-9]+]], !noalias !13 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4, !tbaa [[TBAA16]], !noalias !13 +// CHECK-NEXT: [[TMP10:%.*]] = load float, ptr [[TMP6]], align 4, !tbaa [[TBAA20:![0-9]+]], !noalias !13 +// CHECK-NEXT: tail call void [[TMP8]](i32 noundef [[TMP9]], float noundef [[TMP10]]) #[[ATTR2:[0-9]+]], !noalias !13 // CHECK-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] // CHECK: .omp_outlined..exit: // CHECK-NEXT: ret i32 0 diff --git a/clang/test/OpenMP/debug-info-openmp-array.cpp b/clang/test/OpenMP/debug-info-openmp-array.cpp index 3c9ce386568af..6c5c3bbffee34 100644 --- a/clang/test/OpenMP/debug-info-openmp-array.cpp +++ b/clang/test/OpenMP/debug-info-openmp-array.cpp @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -triple x86_64-unknown-linux -fopenmp -x c++ %s -verify -debug-info-kind=limited -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -Wno-vla -fopenmp -x c++ %s -verify -debug-info-kind=limited -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -fopenmp-simd -x c++ %s -verify -debug-info-kind=limited -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -triple x86_64-unknown-linux -Wno-vla -fopenmp-simd -x c++ %s -verify -debug-info-kind=limited -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics void f(int m) { diff --git a/clang/test/OpenMP/declare_mapper_ast_print.c b/clang/test/OpenMP/declare_mapper_ast_print.c index 7c30b21c48b95..e6a0546fe5c98 100644 --- a/clang/test/OpenMP/declare_mapper_ast_print.c +++ b/clang/test/OpenMP/declare_mapper_ast_print.c @@ -58,7 +58,7 @@ int main(void) { // CHECK: #pragma omp declare mapper (id : struct vec v) map(tofrom: v.len) struct vec vv; struct dat dd[10]; -#pragma omp target map(mapper(id) alloc: vv) +#pragma omp target map(mapper(id), alloc: vv) // CHECK: #pragma omp target map(mapper(id),alloc: vv) { vv.len++; } #pragma omp target map(mapper(default), from: dd[0:10]) diff --git a/clang/test/OpenMP/declare_mapper_messages.c b/clang/test/OpenMP/declare_mapper_messages.c index 17315738155b1..288caca097648 100644 --- a/clang/test/OpenMP/declare_mapper_messages.c +++ b/clang/test/OpenMP/declare_mapper_messages.c @@ -1,10 +1,10 @@ // RUN: %clang_cc1 -verify=omp50,expected -fopenmp -fopenmp-version=50 -ferror-limit 100 -DOMP50 %s // RUN: %clang_cc1 -verify=omp51,expected -fopenmp -ferror-limit 100 %s -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=52 -ferror-limit 100 -DOMP52 %s +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp -fopenmp-version=52 -ferror-limit 100 -DOMP52 %s // RUN: %clang_cc1 -verify=omp50,expected -fopenmp-simd -fopenmp-version=50 -ferror-limit 100 -DOMP50 %s // RUN: %clang_cc1 -verify=omp51-simd,expected -fopenmp-simd -ferror-limit 100 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=52 -ferror-limit 100 -DOMP52 %s +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp-simd -fopenmp-version=52 -ferror-limit 100 -DOMP52 %s int temp; // expected-note {{'temp' declared here}} @@ -74,9 +74,9 @@ int fun(int arg) { {} #pragma omp target map(mapper(aa) :vv) // expected-error {{missing map type}} {} -#pragma omp target map(mapper(aa) to:d) // expected-error {{mapper type must be of struct, union or class type}} +#pragma omp target map(mapper(aa) to:d) // expected-error {{mapper type must be of struct, union or class type}} omp52-error{{missing ',' after map type modifier}} {} -#pragma omp target map(mapper(aa) to:vv) map(close mapper(aa) from:v1) map(mapper(aa) to:arr[0]) +#pragma omp target map(mapper(aa) to:vv) map(close mapper(aa) from:v1) map(mapper(aa) to:arr[0]) // omp52-error 4 {{missing ',' after map type modifier}} {} #pragma omp target update to(mapper) // expected-error {{expected '(' after 'mapper'}} expected-error {{expected expression}} expected-error {{expected at least one 'to' clause or 'from' clause specified to '#pragma omp target update'}} diff --git a/clang/test/OpenMP/declare_simd_messages.cpp b/clang/test/OpenMP/declare_simd_messages.cpp index 60515965ce3d0..dd24322694b69 100644 --- a/clang/test/OpenMP/declare_simd_messages.cpp +++ b/clang/test/OpenMP/declare_simd_messages.cpp @@ -122,11 +122,12 @@ void test() { #pragma omp declare simd aligned( // expected-error@+1 {{expected expression}} #pragma omp declare simd aligned() +// expected-error@+4 {{argument of aligned clause should be array, pointer, reference to array or reference to pointer, not 'int'}} // expected-note@+3 {{to match this '('}} // expected-error@+2 {{expected ')'}} // expected-error@+1 {{expected expression}} #pragma omp declare simd aligned(a: -// expected-error@+1 {{expected expression}} +// expected-error@+1 {{expected expression}} expected-error@+1 {{argument of aligned clause should be array, pointer, reference to array or reference to pointer, not 'int'}} #pragma omp declare simd aligned(a:) // expected-warning@+2 {{extra tokens at the end of '#pragma omp declare simd' are ignored}} // expected-error@+1 {{expected '(' after 'aligned'}} @@ -205,6 +206,8 @@ void test() { // expected-error@+1 {{expected one of 'ref', val' or 'uval' modifiers}} expected-warning@+1 {{extra tokens at the end of '#pragma omp declare simd' are ignored}} #pragma omp declare simd linear(uref(b)) allocate(b) #pragma omp declare simd linear(ref(c)) +// expected-note@+2 {{'a' declared here}} +// expected-note@+1 {{'a' declared here}} void bar(int a, int *b, float &c); template diff --git a/clang/test/OpenMP/declare_variant_device_kind_codegen.cpp b/clang/test/OpenMP/declare_variant_device_kind_codegen.cpp index daa14f1e3a931..4f9a86f1e0080 100644 --- a/clang/test/OpenMP/declare_variant_device_kind_codegen.cpp +++ b/clang/test/OpenMP/declare_variant_device_kind_codegen.cpp @@ -80,7 +80,8 @@ // expected-no-diagnostics -// CHECK-NOT: alias +// Verify no unexpected global symbol aliasing +// CHECK-NOT: @{{[^ ]+}} = {{.*}}alias // CHECK-NOT: ret i32 {{1|4|81|84}} // CHECK-DAG: declare {{.*}}i32 @_Z5bazzzv() diff --git a/clang/test/OpenMP/distribute_parallel_for_simd_ast_print.cpp b/clang/test/OpenMP/distribute_parallel_for_simd_ast_print.cpp index 48809c07ffc39..94ba8494d7126 100644 --- a/clang/test/OpenMP/distribute_parallel_for_simd_ast_print.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_simd_ast_print.cpp @@ -165,9 +165,9 @@ int main(int argc, char **argv) { for (i = 0; i < 100; i++) for (int j = 0; j < 200; j++) a += h + x[j]; - // OMP45: #pragma omp distribute parallel for simd aligned(x: 8) linear(i: 2) safelen(8) simdlen(8) - // OMP50: #pragma omp distribute parallel for simd aligned(x: 8) linear(i: 2) safelen(8) simdlen(8) if(simd: argc) nontemporal(argc,c,d) order(concurrent) - // OMP51: #pragma omp distribute parallel for simd aligned(x: 8) linear(i: 2) safelen(8) simdlen(8) if(simd: argc) nontemporal(argc,c,d) order(unconstrained: concurrent) + // OMP45: #pragma omp distribute parallel for simd aligned(x: 8) linear(i: step(2)) safelen(8) simdlen(8) + // OMP50: #pragma omp distribute parallel for simd aligned(x: 8) linear(i: step(2)) safelen(8) simdlen(8) if(simd: argc) nontemporal(argc,c,d) order(concurrent) + // OMP51: #pragma omp distribute parallel for simd aligned(x: 8) linear(i: step(2)) safelen(8) simdlen(8) if(simd: argc) nontemporal(argc,c,d) order(unconstrained: concurrent) // CHECK-NEXT: for (i = 0; i < 100; i++) // CHECK-NEXT: for (int j = 0; j < 200; j++) // CHECK-NEXT: a += h + x[j]; diff --git a/clang/test/OpenMP/distribute_parallel_for_simd_linear_messages.cpp b/clang/test/OpenMP/distribute_parallel_for_simd_linear_messages.cpp index cdfb9bc605eec..be05533d43f9b 100644 --- a/clang/test/OpenMP/distribute_parallel_for_simd_linear_messages.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_simd_linear_messages.cpp @@ -1,6 +1,8 @@ // RUN: %clang_cc1 -verify -fopenmp %s -Wno-openmp-mapping -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp -fopenmp-version=52 -DOMP52 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify -fopenmp-simd %s -Wno-openmp-mapping -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp-simd -fopenmp-version=52 -DOMP52 %s -Wno-openmp-mapping -Wuninitialized extern int omp_default_mem_alloc; @@ -333,6 +335,33 @@ int main(int argc, char **argv) { #pragma omp teams #pragma omp distribute parallel for simd linear(i : 4) for (i = 0; i < argc; ++i) { ++i; i += 4; } + +#ifdef OMP52 + #pragma omp target + #pragma omp teams + #pragma omp distribute parallel for simd linear(i: step() //omp52-error 2 {{expected expression}} omp52-error{{expected ')'}} omp52-note{{to match this '('}} + for (i = 0; i < argc; ++i) ++i; + #pragma omp target + #pragma omp teams + #pragma omp distribute parallel for simd linear(i: step(1), step(2)) // omp52-error {{multiple 'step size' found in linear clause}} + for (i = 0; i < argc; ++i) ++i; + #pragma omp target + #pragma omp teams + #pragma omp distribute parallel for simd linear(i: val, val) // omp52-error {{multiple 'linear modifier' found in linear clause}} + for (i = 0; i < argc; ++i) ++i; + #pragma omp target + #pragma omp teams + #pragma omp distribute parallel for simd linear(i: step()) // omp52-error 2 {{expected expression}} + for (i = 0; i < argc; ++i) ++i; + #pragma omp target + #pragma omp teams + #pragma omp distribute parallel for simd linear(i: pval) // omp52-error {{use of undeclared identifier 'pval'}} + for (i = 0; i < argc; ++i) ++i; + #pragma omp target + #pragma omp teams + #pragma omp distribute parallel for simd linear(i: val, step(2 // omp52-error {{expected ')' or ',' after 'step expression'}} omp52-error 2 {{expected ')'}} omp52-note 2 {{to match this '('}} + for (i = 0; i < argc; ++i) ++i; +#endif } foomain(argc,argv); // expected-note {{in instantiation of function template specialization 'foomain' requested here}} diff --git a/clang/test/OpenMP/distribute_simd_ast_print.cpp b/clang/test/OpenMP/distribute_simd_ast_print.cpp index a39a1af9267f2..aed9d6376ef58 100644 --- a/clang/test/OpenMP/distribute_simd_ast_print.cpp +++ b/clang/test/OpenMP/distribute_simd_ast_print.cpp @@ -7,6 +7,9 @@ // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=51 -ast-print %s -Wno-openmp-mapping -DOMP51 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP51 // RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -x c++ -std=c++11 -emit-pch -o %t %s -DOMP51 // RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -Wno-openmp-mapping -DOMP51 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP51 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=52 -ast-print %s -Wno-openmp-mapping -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=52 -x c++ -std=c++11 -emit-pch -o %t %s -DOMP52 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=52 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -Wno-openmp-mapping -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -ast-print %s -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK --check-prefix=OMP45 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -emit-pch -o %t %s @@ -18,6 +21,10 @@ // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=51 -x c++ -std=c++11 -emit-pch -o %t %s -DOMP51 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=51 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -Wno-openmp-mapping -DOMP51 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP51 // expected-no-diagnostics +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=52 -ast-print %s -Wno-openmp-mapping -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=52 -x c++ -std=c++11 -emit-pch -o %t %s -DOMP52 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=52 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -Wno-openmp-mapping -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 +// expected-no-diagnostics #ifndef HEADER #define HEADER @@ -147,6 +154,7 @@ int main(int argc, char **argv) { // OMP45: #pragma omp distribute simd private(argc,b) firstprivate(argv,c) lastprivate(d,f) collapse(2) reduction(+: h) dist_schedule(static, b) // OMP50: #pragma omp distribute simd private(argc,b) firstprivate(argv,c) lastprivate(d,f) collapse(2) reduction(+: h) dist_schedule(static, b) if(simd: argc) // OMP51: #pragma omp distribute simd private(argc,b) firstprivate(argv,c) lastprivate(d,f) collapse(2) reduction(+: h) dist_schedule(static, b) +// OMP52: #pragma omp distribute simd private(argc,b) firstprivate(argv,c) lastprivate(d,f) collapse(2) reduction(+: h) dist_schedule(static, b) // CHECK-NEXT: for (int i = 0; i < 10; ++i) // CHECK-NEXT: for (int j = 0; j < 10; ++j) // CHECK-NEXT: a++; @@ -154,7 +162,9 @@ int main(int argc, char **argv) { int i; #pragma omp target #pragma omp teams -#ifdef OMP51 +#ifdef OMP52 +#pragma omp distribute simd aligned(x:8) linear(i: step(2)) safelen(8) simdlen(8) if(argc) nontemporal(argc, c, d) order(reproducible:concurrent) +#elif OMP51 #pragma omp distribute simd aligned(x:8) linear(i:2) safelen(8) simdlen(8) if(argc) nontemporal(argc, c, d) order(reproducible:concurrent) #elif OMP5 #pragma omp distribute simd aligned(x:8) linear(i:2) safelen(8) simdlen(8) if(argc) nontemporal(argc, c, d) order(concurrent) @@ -164,9 +174,10 @@ int main(int argc, char **argv) { for (i = 0; i < 100; i++) for (int j = 0; j < 200; j++) a += h + x[j]; -// OMP45: #pragma omp distribute simd aligned(x: 8) linear(i: 2) safelen(8) simdlen(8) -// OMP50: #pragma omp distribute simd aligned(x: 8) linear(i: 2) safelen(8) simdlen(8) if(argc) nontemporal(argc,c,d) order(concurrent) -// OMP51: #pragma omp distribute simd aligned(x: 8) linear(i: 2) safelen(8) simdlen(8) if(argc) nontemporal(argc,c,d) order(reproducible: concurrent) +// OMP45: #pragma omp distribute simd aligned(x: 8) linear(i: step(2)) safelen(8) simdlen(8) +// OMP50: #pragma omp distribute simd aligned(x: 8) linear(i: step(2)) safelen(8) simdlen(8) if(argc) nontemporal(argc,c,d) order(concurrent) +// OMP51: #pragma omp distribute simd aligned(x: 8) linear(i: step(2)) safelen(8) simdlen(8) if(argc) nontemporal(argc,c,d) order(reproducible: concurrent) +// OMP52: #pragma omp distribute simd aligned(x: 8) linear(i: step(2)) safelen(8) simdlen(8) if(argc) nontemporal(argc,c,d) order(reproducible: concurrent) // CHECK-NEXT: for (i = 0; i < 100; i++) // CHECK-NEXT: for (int j = 0; j < 200; j++) // CHECK-NEXT: a += h + x[j]; diff --git a/clang/test/OpenMP/distribute_simd_codegen.cpp b/clang/test/OpenMP/distribute_simd_codegen.cpp index 297f508575d99..f74abbe32e454 100644 --- a/clang/test/OpenMP/distribute_simd_codegen.cpp +++ b/clang/test/OpenMP/distribute_simd_codegen.cpp @@ -220,7 +220,7 @@ int fint(void) { return ftemplate(); } // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3:[0-9]+]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: ret void @@ -242,7 +242,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -291,45 +291,45 @@ int fint(void) { return ftemplate(); } // CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP13]] -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP8]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[IDXPROM]] -// CHECK1-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP13]] -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP8]] +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM2]] -// CHECK1-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]] -// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP13]] -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP8]] +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i64 [[IDXPROM5]] -// CHECK1-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]] -// CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP13]] -// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP8]] +// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i64 [[IDXPROM8]] -// CHECK1-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK1-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -420,7 +420,7 @@ int fint(void) { return ftemplate(); } // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: ret void @@ -442,7 +442,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -527,7 +527,7 @@ int fint(void) { return ftemplate(); } // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -618,7 +618,7 @@ int fint(void) { return ftemplate(); } // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: ret void @@ -640,7 +640,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -694,45 +694,45 @@ int fint(void) { return ftemplate(); } // CHECK1: omp.dispatch.body: // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]] -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 // CHECK1-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP22]] -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP17]] +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM]] -// CHECK1-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP22]] -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK1-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP17]] +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM3]] -// CHECK1-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK1-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] -// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP22]] -// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP17]] +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM6]] -// CHECK1-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK1-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] -// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP22]] -// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP17]] +// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM9]] -// CHECK1-NEXT: store float [[MUL8]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK1-NEXT: store float [[MUL8]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 -// CHECK1-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK1: omp.dispatch.inc: @@ -835,7 +835,7 @@ int fint(void) { return ftemplate(); } // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i64 [[TMP1]], i64 [[TMP3]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i64 [[TMP1]], i64 [[TMP3]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: ret void @@ -853,7 +853,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -917,26 +917,26 @@ int fint(void) { return ftemplate(); } // CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]] -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]] +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP16:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP25]] +// CHECK1-NEXT: [[TMP16:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP20]] // CHECK1-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] // CHECK1-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 -// CHECK1-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !llvm.access.group [[ACC_GRP25]] +// CHECK1-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !llvm.access.group [[ACC_GRP20]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK1-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1025,7 +1025,7 @@ int fint(void) { return ftemplate(); } // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 // CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i64 [[TMP1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i64 [[TMP1]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: ret i32 0 @@ -1041,7 +1041,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1088,23 +1088,23 @@ int fint(void) { return ftemplate(); } // CHECK1: omp.dispatch.body: // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]] -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK1: omp.dispatch.inc: @@ -1130,7 +1130,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK1-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK1-SAME: () #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) // CHECK1-NEXT: ret void @@ -1212,7 +1212,7 @@ int fint(void) { return ftemplate(); } // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR4:[0-9]+]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3:[0-9]+]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: ret void @@ -1234,7 +1234,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -1283,41 +1283,41 @@ int fint(void) { return ftemplate(); } // CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]] -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i32 [[TMP14]] -// CHECK3-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK3-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i32 [[TMP17]] -// CHECK3-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK3-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]] -// CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i32 [[TMP20]] -// CHECK3-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK3-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]] -// CHECK3-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK3-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i32 [[TMP23]] -// CHECK3-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK3-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK3-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1408,7 +1408,7 @@ int fint(void) { return ftemplate(); } // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: ret void @@ -1430,7 +1430,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -1511,7 +1511,7 @@ int fint(void) { return ftemplate(); } // CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1602,7 +1602,7 @@ int fint(void) { return ftemplate(); } // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: ret void @@ -1624,7 +1624,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -1678,41 +1678,41 @@ int fint(void) { return ftemplate(); } // CHECK3: omp.dispatch.body: // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]] -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 // CHECK3-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] -// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP23]] -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i32 [[TMP15]] -// CHECK3-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] -// CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP23]] -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK3-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i32 [[TMP18]] -// CHECK3-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK3-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] -// CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP23]] -// CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i32 [[TMP21]] -// CHECK3-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK3-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] -// CHECK3-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP23]] -// CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK3-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i32 [[TMP24]] -// CHECK3-NEXT: store float [[MUL6]], ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK3-NEXT: store float [[MUL6]], ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK3-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 -// CHECK3-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK3: omp.dispatch.inc: @@ -1815,7 +1815,7 @@ int fint(void) { return ftemplate(); } // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i32 [[TMP1]], i32 [[TMP3]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i32 [[TMP1]], i32 [[TMP3]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: ret void @@ -1833,7 +1833,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -1897,26 +1897,26 @@ int fint(void) { return ftemplate(); } // CHECK3-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]] -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP16:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP26]] +// CHECK3-NEXT: [[TMP16:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP21]] // CHECK3-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] // CHECK3-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 -// CHECK3-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !llvm.access.group [[ACC_GRP26]] +// CHECK3-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !llvm.access.group [[ACC_GRP21]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK3-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK3-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -2005,7 +2005,7 @@ int fint(void) { return ftemplate(); } // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 // CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i32 [[TMP1]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i32 [[TMP1]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: ret i32 0 @@ -2021,7 +2021,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -2068,23 +2068,23 @@ int fint(void) { return ftemplate(); } // CHECK3: omp.dispatch.body: // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29:![0-9]+]] -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK3-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]] -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK3: omp.dispatch.inc: @@ -2110,7 +2110,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK3-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK3-SAME: () #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) // CHECK3-NEXT: ret void @@ -2192,7 +2192,7 @@ int fint(void) { return ftemplate(); } // CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 // CHECK5-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK5: omp_offload.failed: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR4:[0-9]+]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3:[0-9]+]] // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK5: omp_offload.cont: // CHECK5-NEXT: ret void @@ -2214,7 +2214,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -2263,45 +2263,45 @@ int fint(void) { return ftemplate(); } // CHECK5-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]] +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP13]] -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP8]] +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[IDXPROM]] -// CHECK5-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP13]] -// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK5-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP8]] +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64 // CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM2]] -// CHECK5-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK5-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]] -// CHECK5-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP13]] -// CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK5-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP8]] +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i64 [[IDXPROM5]] -// CHECK5-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK5-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]] -// CHECK5-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP13]] -// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK5-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP8]] +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64 // CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i64 [[IDXPROM8]] -// CHECK5-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK5-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK5-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2392,7 +2392,7 @@ int fint(void) { return ftemplate(); } // CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 // CHECK5-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK5: omp_offload.failed: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK5: omp_offload.cont: // CHECK5-NEXT: ret void @@ -2414,7 +2414,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -2470,7 +2470,7 @@ int fint(void) { return ftemplate(); } // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] // CHECK5-NEXT: store i32 [[SUB]], ptr [[I]], align 4 -// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8, !nontemporal !20 +// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8, !nontemporal !15 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]] @@ -2487,7 +2487,7 @@ int fint(void) { return ftemplate(); } // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]] // CHECK5-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4 // CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] -// CHECK5-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8, !nontemporal !20 +// CHECK5-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8, !nontemporal !15 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 // CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 // CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]] @@ -2499,7 +2499,7 @@ int fint(void) { return ftemplate(); } // CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2590,7 +2590,7 @@ int fint(void) { return ftemplate(); } // CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 // CHECK5-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK5: omp_offload.failed: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK5: omp_offload.cont: // CHECK5-NEXT: ret void @@ -2612,7 +2612,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -2666,45 +2666,45 @@ int fint(void) { return ftemplate(); } // CHECK5: omp.dispatch.body: // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]] -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 // CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] -// CHECK5-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP23]] -// CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK5-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP18]] +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM]] -// CHECK5-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] -// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP23]] -// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK5-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP18]] +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK5-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM3]] -// CHECK5-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK5-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] -// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP23]] -// CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP18]] +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 // CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM6]] -// CHECK5-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK5-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] -// CHECK5-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP23]] -// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK5-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP18]] +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM9]] -// CHECK5-NEXT: store float [[MUL8]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK5-NEXT: store float [[MUL8]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 -// CHECK5-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK5: omp.dispatch.inc: @@ -2807,7 +2807,7 @@ int fint(void) { return ftemplate(); } // CHECK5-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 // CHECK5-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK5: omp_offload.failed: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i64 [[TMP1]], i64 [[TMP3]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i64 [[TMP1]], i64 [[TMP3]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK5: omp_offload.cont: // CHECK5-NEXT: ret void @@ -2825,7 +2825,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -2893,26 +2893,26 @@ int fint(void) { return ftemplate(); } // CHECK5: omp_if.then: // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]] -// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP17:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP26]] +// CHECK5-NEXT: [[TMP17:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP21]] // CHECK5-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] // CHECK5-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 -// CHECK5-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !nontemporal !20, !llvm.access.group [[ACC_GRP26]] +// CHECK5-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !nontemporal !15, !llvm.access.group [[ACC_GRP21]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK5-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] // CHECK5: omp_if.else: @@ -2937,7 +2937,7 @@ int fint(void) { return ftemplate(); } // CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK5-NEXT: store i32 [[ADD22]], ptr [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP24:![0-9]+]] // CHECK5: omp.inner.for.end23: // CHECK5-NEXT: br label [[OMP_IF_END]] // CHECK5: omp_if.end: @@ -3028,7 +3028,7 @@ int fint(void) { return ftemplate(); } // CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 // CHECK5-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK5: omp_offload.failed: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i64 [[TMP1]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i64 [[TMP1]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK5: omp_offload.cont: // CHECK5-NEXT: ret i32 0 @@ -3044,7 +3044,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -3091,23 +3091,23 @@ int fint(void) { return ftemplate(); } // CHECK5: omp.dispatch.body: // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31:![0-9]+]] -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]] +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK5: omp.dispatch.inc: @@ -3133,7 +3133,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK5-SAME: () #[[ATTR4:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: call void @__tgt_register_requires(i64 1) // CHECK5-NEXT: ret void @@ -3215,7 +3215,7 @@ int fint(void) { return ftemplate(); } // CHECK7-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 // CHECK7-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK7: omp_offload.failed: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR4:[0-9]+]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3:[0-9]+]] // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK7: omp_offload.cont: // CHECK7-NEXT: ret void @@ -3237,7 +3237,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined -// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -3286,41 +3286,41 @@ int fint(void) { return ftemplate(); } // CHECK7-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]] -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] -// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK7-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK7-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i32 [[TMP14]] -// CHECK7-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK7-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK7-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK7-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i32 [[TMP17]] -// CHECK7-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK7-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK7-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]] -// CHECK7-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK7-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK7-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i32 [[TMP20]] -// CHECK7-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK7-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]] -// CHECK7-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK7-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i32 [[TMP23]] -// CHECK7-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK7-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK7-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK7-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK7: omp.loop.exit: @@ -3411,7 +3411,7 @@ int fint(void) { return ftemplate(); } // CHECK7-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 // CHECK7-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK7: omp_offload.failed: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK7: omp_offload.cont: // CHECK7-NEXT: ret void @@ -3433,7 +3433,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined -// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR2]] { +// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -3489,7 +3489,7 @@ int fint(void) { return ftemplate(); } // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] // CHECK7-NEXT: store i32 [[SUB]], ptr [[I]], align 4 -// CHECK7-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 4, !nontemporal !21 +// CHECK7-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 4, !nontemporal !16 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i32 [[TMP13]] // CHECK7-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4 @@ -3503,7 +3503,7 @@ int fint(void) { return ftemplate(); } // CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i32 [[TMP19]] // CHECK7-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX4]], align 4 // CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] -// CHECK7-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 4, !nontemporal !21 +// CHECK7-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 4, !nontemporal !16 // CHECK7-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 // CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i32 [[TMP22]] // CHECK7-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4 @@ -3514,7 +3514,7 @@ int fint(void) { return ftemplate(); } // CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK7-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK7: omp.loop.exit: @@ -3605,7 +3605,7 @@ int fint(void) { return ftemplate(); } // CHECK7-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 // CHECK7-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK7: omp_offload.failed: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK7: omp_offload.cont: // CHECK7-NEXT: ret void @@ -3627,7 +3627,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined -// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR2]] { +// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -3681,41 +3681,41 @@ int fint(void) { return ftemplate(); } // CHECK7: omp.dispatch.body: // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK7-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] // CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK7-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 // CHECK7-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] -// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK7-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK7-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i32 [[TMP15]] -// CHECK7-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK7-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK7-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK7-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i32 [[TMP18]] -// CHECK7-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK7-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK7-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] -// CHECK7-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK7-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK7-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK7-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i32 [[TMP21]] -// CHECK7-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK7-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK7-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] -// CHECK7-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK7-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i32 [[TMP24]] -// CHECK7-NEXT: store float [[MUL6]], ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK7-NEXT: store float [[MUL6]], ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK7-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK7-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 -// CHECK7-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK7-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK7: omp.dispatch.inc: @@ -3818,7 +3818,7 @@ int fint(void) { return ftemplate(); } // CHECK7-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 // CHECK7-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK7: omp_offload.failed: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i32 [[TMP1]], i32 [[TMP3]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i32 [[TMP1]], i32 [[TMP3]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK7: omp_offload.cont: // CHECK7-NEXT: ret void @@ -3836,7 +3836,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined -// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR2]] { +// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -3904,26 +3904,26 @@ int fint(void) { return ftemplate(); } // CHECK7: omp_if.then: // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] -// CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]] +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP17:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP27]] +// CHECK7-NEXT: [[TMP17:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP22]] // CHECK7-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK7-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] // CHECK7-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 -// CHECK7-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !nontemporal !21, !llvm.access.group [[ACC_GRP27]] +// CHECK7-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !nontemporal !16, !llvm.access.group [[ACC_GRP22]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK7-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK7-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK7-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] // CHECK7: omp_if.else: @@ -3948,7 +3948,7 @@ int fint(void) { return ftemplate(); } // CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK7-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK7-NEXT: store i32 [[ADD22]], ptr [[DOTOMP_IV]], align 4 -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP30:![0-9]+]] +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK7: omp.inner.for.end23: // CHECK7-NEXT: br label [[OMP_IF_END]] // CHECK7: omp_if.end: @@ -4039,7 +4039,7 @@ int fint(void) { return ftemplate(); } // CHECK7-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 // CHECK7-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK7: omp_offload.failed: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i32 [[TMP1]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i32 [[TMP1]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK7: omp_offload.cont: // CHECK7-NEXT: ret i32 0 @@ -4055,7 +4055,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined -// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR2]] { +// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -4102,23 +4102,23 @@ int fint(void) { return ftemplate(); } // CHECK7: omp.dispatch.body: // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]] -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK7-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] +// CHECK7-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK7: omp.dispatch.inc: @@ -4144,7 +4144,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK7-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK7-SAME: () #[[ATTR4:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: call void @__tgt_register_requires(i64 1) // CHECK7-NEXT: ret void @@ -5504,7 +5504,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -5553,45 +5553,45 @@ int fint(void) { return ftemplate(); } // CHECK17-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]] -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] +// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP14]] -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP9]] +// CHECK17-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[IDXPROM]] -// CHECK17-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK17-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP14]] -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK17-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK17-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP9]] +// CHECK17-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK17-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64 // CHECK17-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM2]] -// CHECK17-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK17-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK17-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]] -// CHECK17-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP14]] -// CHECK17-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK17-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP9]] +// CHECK17-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK17-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64 // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i64 [[IDXPROM5]] -// CHECK17-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK17-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK17-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]] -// CHECK17-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP14]] -// CHECK17-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK17-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP9]] +// CHECK17-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK17-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64 // CHECK17-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i64 [[IDXPROM8]] -// CHECK17-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK17-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK17-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK17-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK17-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK17: omp.inner.for.end: // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK17: omp.loop.exit: @@ -5622,7 +5622,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -5707,7 +5707,7 @@ int fint(void) { return ftemplate(); } // CHECK17-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK17-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK17: omp.inner.for.end: // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK17: omp.loop.exit: @@ -5738,7 +5738,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -5792,45 +5792,45 @@ int fint(void) { return ftemplate(); } // CHECK17: omp.dispatch.body: // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]] -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] +// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK17-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 // CHECK17-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] -// CHECK17-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP23]] -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK17-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP18]] +// CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK17-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM]] -// CHECK17-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] -// CHECK17-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP23]] -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK17-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK17-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP18]] +// CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK17-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 // CHECK17-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM3]] -// CHECK17-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK17-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK17-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] -// CHECK17-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP23]] -// CHECK17-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK17-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP18]] +// CHECK17-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK17-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 // CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM6]] -// CHECK17-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK17-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK17-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] -// CHECK17-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP23]] -// CHECK17-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK17-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP18]] +// CHECK17-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK17-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 // CHECK17-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM9]] -// CHECK17-NEXT: store float [[MUL8]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK17-NEXT: store float [[MUL8]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK17-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK17-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 -// CHECK17-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] +// CHECK17-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK17: omp.inner.for.end: // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK17: omp.dispatch.inc: @@ -5867,7 +5867,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -5931,26 +5931,26 @@ int fint(void) { return ftemplate(); } // CHECK17-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]] -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK17-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] +// CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK17-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK17-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP16:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP26]] +// CHECK17-NEXT: [[TMP16:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP21]] // CHECK17-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK17-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] // CHECK17-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 -// CHECK17-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !llvm.access.group [[ACC_GRP26]] +// CHECK17-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !llvm.access.group [[ACC_GRP21]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK17-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK17-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] +// CHECK17-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK17: omp.inner.for.end: // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK17: omp.loop.exit: @@ -5990,7 +5990,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -6037,23 +6037,23 @@ int fint(void) { return ftemplate(); } // CHECK17: omp.dispatch.body: // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29:![0-9]+]] -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] +// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK17-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]] -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] +// CHECK17-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK17: omp.inner.for.end: // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK17: omp.dispatch.inc: @@ -6094,7 +6094,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -6143,41 +6143,41 @@ int fint(void) { return ftemplate(); } // CHECK19-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] +// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK19-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK19-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i32 [[TMP14]] -// CHECK19-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK19-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK19-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK19-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK19-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i32 [[TMP17]] -// CHECK19-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK19-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK19-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]] -// CHECK19-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK19-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK19-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK19-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK19-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i32 [[TMP20]] -// CHECK19-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK19-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK19-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]] -// CHECK19-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK19-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK19-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK19-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i32 [[TMP23]] -// CHECK19-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK19-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK19-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK19-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK19-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK19: omp.inner.for.end: // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK19: omp.loop.exit: @@ -6208,7 +6208,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -6289,7 +6289,7 @@ int fint(void) { return ftemplate(); } // CHECK19-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK19-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK19: omp.inner.for.end: // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK19: omp.loop.exit: @@ -6320,7 +6320,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -6374,41 +6374,41 @@ int fint(void) { return ftemplate(); } // CHECK19: omp.dispatch.body: // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] +// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK19-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] // CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK19-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 // CHECK19-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK19-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK19-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i32 [[TMP15]] -// CHECK19-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK19-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK19-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK19-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK19-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i32 [[TMP18]] -// CHECK19-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK19-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK19-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] -// CHECK19-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK19-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK19-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK19-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK19-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i32 [[TMP21]] -// CHECK19-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK19-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK19-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] -// CHECK19-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK19-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK19-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK19-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK19-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i32 [[TMP24]] -// CHECK19-NEXT: store float [[MUL6]], ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK19-NEXT: store float [[MUL6]], ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK19-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK19-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 -// CHECK19-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK19-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK19: omp.inner.for.end: // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK19: omp.dispatch.inc: @@ -6445,7 +6445,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -6509,26 +6509,26 @@ int fint(void) { return ftemplate(); } // CHECK19-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]] +// CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK19-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK19-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP16:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP27]] +// CHECK19-NEXT: [[TMP16:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP22]] // CHECK19-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK19-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK19-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] // CHECK19-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 -// CHECK19-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !llvm.access.group [[ACC_GRP27]] +// CHECK19-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !llvm.access.group [[ACC_GRP22]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK19-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK19-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK19-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK19: omp.inner.for.end: // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK19: omp.loop.exit: @@ -6568,7 +6568,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -6615,23 +6615,23 @@ int fint(void) { return ftemplate(); } // CHECK19: omp.dispatch.body: // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30:![0-9]+]] -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]] +// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK19-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK19-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] // CHECK19: omp.inner.for.end: // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK19: omp.dispatch.inc: @@ -6672,7 +6672,7 @@ int fint(void) { return ftemplate(); } // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined -// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -6721,45 +6721,45 @@ int fint(void) { return ftemplate(); } // CHECK21-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK21: omp.inner.for.cond: -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]] -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] +// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK21: omp.inner.for.body: -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] -// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK21-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP14]] -// CHECK21-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK21-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP9]] +// CHECK21-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[IDXPROM]] -// CHECK21-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK21-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP14]] -// CHECK21-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK21-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK21-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP9]] +// CHECK21-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK21-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64 // CHECK21-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM2]] -// CHECK21-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK21-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK21-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]] -// CHECK21-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP14]] -// CHECK21-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK21-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP9]] +// CHECK21-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK21-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64 // CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i64 [[IDXPROM5]] -// CHECK21-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK21-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK21-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]] -// CHECK21-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP14]] -// CHECK21-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK21-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP9]] +// CHECK21-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK21-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64 // CHECK21-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i64 [[IDXPROM8]] -// CHECK21-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK21-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK21: omp.body.continue: // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK21: omp.inner.for.inc: -// CHECK21-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK21-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK21-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK21-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK21-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK21: omp.inner.for.end: // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK21: omp.loop.exit: @@ -6790,7 +6790,7 @@ int fint(void) { return ftemplate(); } // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined -// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -6846,7 +6846,7 @@ int fint(void) { return ftemplate(); } // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 // CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] // CHECK21-NEXT: store i32 [[SUB]], ptr [[I]], align 4 -// CHECK21-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8, !nontemporal !21 +// CHECK21-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8, !nontemporal !16 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]] @@ -6863,7 +6863,7 @@ int fint(void) { return ftemplate(); } // CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]] // CHECK21-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4 // CHECK21-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] -// CHECK21-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8, !nontemporal !21 +// CHECK21-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8, !nontemporal !16 // CHECK21-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 // CHECK21-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 // CHECK21-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]] @@ -6875,7 +6875,7 @@ int fint(void) { return ftemplate(); } // CHECK21-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK21-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK21: omp.inner.for.end: // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK21: omp.loop.exit: @@ -6906,7 +6906,7 @@ int fint(void) { return ftemplate(); } // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined -// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -6960,45 +6960,45 @@ int fint(void) { return ftemplate(); } // CHECK21: omp.dispatch.body: // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK21: omp.inner.for.cond: -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] +// CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK21-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] // CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK21: omp.inner.for.body: -// CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK21-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 // CHECK21-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] -// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK21-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP24]] -// CHECK21-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK21-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP19]] +// CHECK21-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK21-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM]] -// CHECK21-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK21-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP24]] -// CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK21-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK21-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP19]] +// CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK21-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 // CHECK21-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM3]] -// CHECK21-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK21-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK21-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] -// CHECK21-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP24]] -// CHECK21-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK21-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP19]] +// CHECK21-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK21-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 // CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM6]] -// CHECK21-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK21-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK21-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] -// CHECK21-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP24]] -// CHECK21-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK21-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP19]] +// CHECK21-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK21-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 // CHECK21-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM9]] -// CHECK21-NEXT: store float [[MUL8]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK21-NEXT: store float [[MUL8]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK21: omp.body.continue: // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK21: omp.inner.for.inc: -// CHECK21-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK21-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK21-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 -// CHECK21-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK21-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK21: omp.inner.for.end: // CHECK21-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK21: omp.dispatch.inc: @@ -7035,7 +7035,7 @@ int fint(void) { return ftemplate(); } // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined -// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -7103,26 +7103,26 @@ int fint(void) { return ftemplate(); } // CHECK21: omp_if.then: // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK21: omp.inner.for.cond: -// CHECK21-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] -// CHECK21-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK21-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]] +// CHECK21-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK21-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK21-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK21: omp.inner.for.body: -// CHECK21-NEXT: [[TMP17:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP27]] +// CHECK21-NEXT: [[TMP17:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP22]] // CHECK21-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK21-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] // CHECK21-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 -// CHECK21-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !nontemporal !21, !llvm.access.group [[ACC_GRP27]] +// CHECK21-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !nontemporal !16, !llvm.access.group [[ACC_GRP22]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK21: omp.body.continue: // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK21: omp.inner.for.inc: -// CHECK21-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK21-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK21-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK21-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] -// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK21-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK21: omp.inner.for.end: // CHECK21-NEXT: br label [[OMP_IF_END:%.*]] // CHECK21: omp_if.else: @@ -7147,7 +7147,7 @@ int fint(void) { return ftemplate(); } // CHECK21-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK21-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK21-NEXT: store i32 [[ADD22]], ptr [[DOTOMP_IV]], align 4 -// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP30:![0-9]+]] +// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK21: omp.inner.for.end23: // CHECK21-NEXT: br label [[OMP_IF_END]] // CHECK21: omp_if.end: @@ -7189,7 +7189,7 @@ int fint(void) { return ftemplate(); } // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined -// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -7236,23 +7236,23 @@ int fint(void) { return ftemplate(); } // CHECK21: omp.dispatch.body: // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK21: omp.inner.for.cond: -// CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]] -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] +// CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK21-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK21: omp.inner.for.body: -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK21: omp.body.continue: // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK21: omp.inner.for.inc: -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK21-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] -// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] +// CHECK21-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] // CHECK21: omp.inner.for.end: // CHECK21-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK21: omp.dispatch.inc: @@ -7293,7 +7293,7 @@ int fint(void) { return ftemplate(); } // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined -// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -7342,41 +7342,41 @@ int fint(void) { return ftemplate(); } // CHECK23-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK23: omp.inner.for.cond: -// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] +// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK23: omp.inner.for.body: -// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] -// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK23-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK23-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK23-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK23-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i32 [[TMP14]] -// CHECK23-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK23-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK23-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK23-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK23-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK23-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK23-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i32 [[TMP17]] -// CHECK23-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK23-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK23-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]] -// CHECK23-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK23-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK23-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK23-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK23-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i32 [[TMP20]] -// CHECK23-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK23-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK23-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]] -// CHECK23-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK23-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK23-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK23-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK23-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i32 [[TMP23]] -// CHECK23-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK23-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK23: omp.body.continue: // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK23: omp.inner.for.inc: -// CHECK23-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK23-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK23-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK23-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK23-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK23: omp.inner.for.end: // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK23: omp.loop.exit: @@ -7407,7 +7407,7 @@ int fint(void) { return ftemplate(); } // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined -// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -7463,7 +7463,7 @@ int fint(void) { return ftemplate(); } // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 // CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] // CHECK23-NEXT: store i32 [[SUB]], ptr [[I]], align 4 -// CHECK23-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 4, !nontemporal !22 +// CHECK23-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 4, !nontemporal !17 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i32 [[TMP13]] // CHECK23-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4 @@ -7477,7 +7477,7 @@ int fint(void) { return ftemplate(); } // CHECK23-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i32 [[TMP19]] // CHECK23-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX4]], align 4 // CHECK23-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] -// CHECK23-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 4, !nontemporal !22 +// CHECK23-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 4, !nontemporal !17 // CHECK23-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 // CHECK23-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i32 [[TMP22]] // CHECK23-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4 @@ -7488,7 +7488,7 @@ int fint(void) { return ftemplate(); } // CHECK23-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK23-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK23: omp.inner.for.end: // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK23: omp.loop.exit: @@ -7519,7 +7519,7 @@ int fint(void) { return ftemplate(); } // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined -// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -7573,41 +7573,41 @@ int fint(void) { return ftemplate(); } // CHECK23: omp.dispatch.body: // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK23: omp.inner.for.cond: -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]] -// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]] +// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK23-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] // CHECK23-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK23: omp.inner.for.body: -// CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK23-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 // CHECK23-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] -// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK23-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK23-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK23-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK23-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i32 [[TMP15]] -// CHECK23-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK23-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK23-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK23-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK23-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i32 [[TMP18]] -// CHECK23-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK23-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK23-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] -// CHECK23-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK23-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK23-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK23-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK23-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i32 [[TMP21]] -// CHECK23-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK23-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK23-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] -// CHECK23-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK23-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK23-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK23-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK23-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i32 [[TMP24]] -// CHECK23-NEXT: store float [[MUL6]], ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK23-NEXT: store float [[MUL6]], ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK23: omp.body.continue: // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK23: omp.inner.for.inc: -// CHECK23-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK23-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK23-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 -// CHECK23-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK23-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK23: omp.inner.for.end: // CHECK23-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK23: omp.dispatch.inc: @@ -7644,7 +7644,7 @@ int fint(void) { return ftemplate(); } // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined -// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[I:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -7712,26 +7712,26 @@ int fint(void) { return ftemplate(); } // CHECK23: omp_if.then: // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK23: omp.inner.for.cond: -// CHECK23-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]] -// CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK23-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]] +// CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK23-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK23-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK23: omp.inner.for.body: -// CHECK23-NEXT: [[TMP17:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP28]] +// CHECK23-NEXT: [[TMP17:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP23]] // CHECK23-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK23-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]] // CHECK23-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8 -// CHECK23-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !nontemporal !22, !llvm.access.group [[ACC_GRP28]] +// CHECK23-NEXT: store i8 [[CONV11]], ptr [[I6]], align 1, !nontemporal !17, !llvm.access.group [[ACC_GRP23]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK23: omp.body.continue: // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK23: omp.inner.for.inc: -// CHECK23-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK23-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK23-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK23-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] -// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK23-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] // CHECK23: omp.inner.for.end: // CHECK23-NEXT: br label [[OMP_IF_END:%.*]] // CHECK23: omp_if.else: @@ -7756,7 +7756,7 @@ int fint(void) { return ftemplate(); } // CHECK23-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK23-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK23-NEXT: store i32 [[ADD22]], ptr [[DOTOMP_IV]], align 4 -// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP26:![0-9]+]] // CHECK23: omp.inner.for.end23: // CHECK23-NEXT: br label [[OMP_IF_END]] // CHECK23: omp_if.end: @@ -7798,7 +7798,7 @@ int fint(void) { return ftemplate(); } // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined -// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -7845,23 +7845,23 @@ int fint(void) { return ftemplate(); } // CHECK23: omp.dispatch.body: // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK23: omp.inner.for.cond: -// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]] -// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]] +// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK23-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK23-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK23: omp.inner.for.body: -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK23: omp.body.continue: // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK23: omp.inner.for.inc: -// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK23-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] -// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK23-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] // CHECK23: omp.inner.for.end: // CHECK23-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK23: omp.dispatch.inc: diff --git a/clang/test/OpenMP/distribute_simd_linear_messages.cpp b/clang/test/OpenMP/distribute_simd_linear_messages.cpp index 1ba4c5ceeb734..a56fd636b6f1a 100644 --- a/clang/test/OpenMP/distribute_simd_linear_messages.cpp +++ b/clang/test/OpenMP/distribute_simd_linear_messages.cpp @@ -1,6 +1,8 @@ // RUN: %clang_cc1 -verify -fopenmp %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp -fopenmp-version=52 -DOMP52 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify -fopenmp-simd %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp-simd -fopenmp-version=52 -DOMP52 %s -Wno-openmp-mapping -Wuninitialized extern int omp_default_mem_alloc; @@ -322,6 +324,33 @@ int main(int argc, char **argv) { #pragma omp teams #pragma omp distribute simd linear(k : 4) for (k = 0; k < argc; k+=4) { } + +#ifdef OMP52 + #pragma omp target + #pragma omp teams + #pragma omp distribute simd linear(k: step() //omp52-error 2 {{expected expression}} omp52-error{{expected ')'}} omp52-note{{to match this '('}} + for (k = 0; k < argc; ++k) ++k; + #pragma omp target + #pragma omp teams + #pragma omp distribute simd linear(k: step(1), step(2)) // omp52-error {{multiple 'step size' found in linear clause}} + for (k = 0; k < argc; ++k) ++k; + #pragma omp target + #pragma omp teams + #pragma omp distribute simd linear(k: val, val) // omp52-error {{multiple 'linear modifier' found in linear clause}} + for (k = 0; k < argc; ++k) ++k; + #pragma omp target + #pragma omp teams + #pragma omp distribute simd linear(k: step()) // omp52-error 2 {{expected expression}} + for (k = 0; k < argc; ++k) ++k; + #pragma omp target + #pragma omp teams + #pragma omp distribute simd linear(k: pval) // omp52-error {{use of undeclared identifier 'pval'}} + for (k = 0; k < argc; ++k) ++k; + #pragma omp target + #pragma omp teams + #pragma omp distribute simd linear(i: val, step(2 // omp52-error {{expected ')' or ',' after 'step expression'}} omp52-error 2 {{expected ')'}} omp52-note 2 {{to match this '('}} + for (i = 0; i < argc; ++i) ++i; +#endif } foomain(argc,argv); // expected-note {{in instantiation of function template specialization 'foomain' requested here}} diff --git a/clang/test/OpenMP/for_ast_print.cpp b/clang/test/OpenMP/for_ast_print.cpp index 6ac945758aaa6..abc27caa9ae8d 100644 --- a/clang/test/OpenMP/for_ast_print.cpp +++ b/clang/test/OpenMP/for_ast_print.cpp @@ -4,6 +4,9 @@ // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=51 -ast-print %s -Wsign-conversion -DOMP51 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP51 // RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -x c++ -std=c++11 -emit-pch -o %t %s -DOMP51 // RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -DOMP51 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP51 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=52 -ast-print %s -Wsign-conversion -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=52 -x c++ -std=c++11 -emit-pch -o %t %s -DOMP52 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=52 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 // RUN: %clang_cc1 -verify -fopenmp-simd -ast-print %s -Wsign-conversion | FileCheck %s --check-prefix=CHECK --check-prefix=OMP50 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -emit-pch -o %t %s @@ -11,6 +14,9 @@ // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=51 -ast-print %s -Wsign-conversion -DOMP51 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP51 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=51 -x c++ -std=c++11 -emit-pch -o %t %s -DOMP51 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=51 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -DOMP51 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP51 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=52 -ast-print %s -Wsign-conversion -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=52 -x c++ -std=c++11 -emit-pch -o %t %s -DOMP52 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=52 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 // expected-no-diagnostics #ifndef HEADER @@ -42,7 +48,11 @@ class S7 : public T { #pragma omp for lastprivate(a) lastprivate(this->a) lastprivate(T::a) for (int k = 0; k < a.a; ++k) ++this->a.a; +#if defined(OMP52) +#pragma omp for linear(c: val) +#else #pragma omp for linear(val(c)) +#endif for (int k = 0; k < a.a; ++k) ++this->a.a; } @@ -53,7 +63,11 @@ class S7 : public T { #pragma omp for lastprivate(a) lastprivate(this->a) for (int k = 0; k < s.a.a; ++k) ++s.a.a; +#if defined(OMP52) +#pragma omp for linear(this->b: uval) +#else #pragma omp for linear(uval(this->b)) +#endif for (int k = 0; k < s.a.a; ++k) ++s.a.a; return *this; @@ -62,13 +76,13 @@ class S7 : public T { // CHECK: #pragma omp for private(this->a) private(this->a) private(T::a) // CHECK: #pragma omp for lastprivate(this->a) lastprivate(this->a) lastprivate(T::a) -// CHECK: #pragma omp for linear(val(this->c)) +// CHECK: #pragma omp for linear(this->c: val) // CHECK: #pragma omp for private(this->a) private(this->a) // CHECK: #pragma omp for lastprivate(this->a) lastprivate(this->a) -// CHECK: #pragma omp for linear(uval(this->b)) +// CHECK: #pragma omp for linear(this->b: uval) // CHECK: #pragma omp for private(this->a) private(this->a) private(this->S::a) // CHECK: #pragma omp for lastprivate(this->a) lastprivate(this->a) lastprivate(this->S::a) -// CHECK: #pragma omp for linear(val(this->c)) +// CHECK: #pragma omp for linear(this->c: val) class S8 : public S7 { S8() {} @@ -81,7 +95,11 @@ class S8 : public S7 { #pragma omp for lastprivate(a) lastprivate(this->a) lastprivate(S7::a) for (int k = 0; k < a.a; ++k) ++this->a.a; +#if defined(OMP52) +#pragma omp for linear(S7::d: ref) +#else #pragma omp for linear(ref(S7::d)) +#endif for (int k = 0; k < a.a; ++k) ++this->a.a; } @@ -101,7 +119,7 @@ class S8 : public S7 { // CHECK: #pragma omp for private(this->a) private(this->a) private(this->S7::a) // CHECK: #pragma omp for lastprivate(this->a) lastprivate(this->a) lastprivate(this->S7::a) -// CHECK: #pragma omp for linear(ref(this->S7::d)) +// CHECK: #pragma omp for linear(this->S7::d: ref) // CHECK: #pragma omp for private(this->a) private(this->a) // CHECK: #pragma omp for lastprivate(this->a) lastprivate(this->a) // CHECK: #pragma omp for linear(this->c) @@ -227,25 +245,32 @@ int main(int argc, char **argv) { float arr[20]; static int a; // CHECK: static int a; -#ifdef OMP51 +#ifdef OMP52 +#pragma omp for schedule(guided, argc) reduction(+:argv[0][:1]) order(unconstrained:concurrent) +#elif OMP51 #pragma omp for schedule(guided, argc) reduction(+:argv[0][:1]) order(unconstrained:concurrent) #else #pragma omp for schedule(guided, argc) reduction(+:argv[0][:1]) order(concurrent) #endif // OMP51 // OMP50: #pragma omp for schedule(guided, argc) reduction(+: argv[0][:1]) order(concurrent) // OMP51: #pragma omp for schedule(guided, argc) reduction(+: argv[0][:1]) order(unconstrained: concurrent) + // OMP52: #pragma omp for schedule(guided, argc) reduction(+: argv[0][:1]) order(unconstrained: concurrent) for (int i = argc; i < c; ++i) a = 2; // CHECK-NEXT: for (int i = argc; i < c; ++i) // CHECK-NEXT: a = 2; #pragma omp parallel +#ifdef OMP52 +#pragma omp for private(argc, b), firstprivate(argv, c), lastprivate(d, f) collapse(3) schedule(auto) ordered nowait linear(g: step(-1)) reduction(task, +:e) +#else #pragma omp for private(argc, b), firstprivate(argv, c), lastprivate(d, f) collapse(3) schedule(auto) ordered nowait linear(g:-1) reduction(task, +:e) +#endif for (int i = 0; i < 10; ++i) for (int j = 0; j < 10; ++j) for (auto x : arr) foo(), (void)x; // CHECK-NEXT: #pragma omp parallel - // CHECK-NEXT: #pragma omp for private(argc,b) firstprivate(argv,c) lastprivate(d,f) collapse(3) schedule(auto) ordered nowait linear(g: -1) reduction(task, +: e) + // CHECK-NEXT: #pragma omp for private(argc,b) firstprivate(argv,c) lastprivate(d,f) collapse(3) schedule(auto) ordered nowait linear(g: step(-1)) reduction(task, +: e) // CHECK-NEXT: for (int i = 0; i < 10; ++i) // CHECK-NEXT: for (int j = 0; j < 10; ++j) // CHECK-NEXT: for (auto x : arr) diff --git a/clang/test/OpenMP/for_linear_messages.cpp b/clang/test/OpenMP/for_linear_messages.cpp index 363bbdbbe9dc3..d8d3391c0c271 100644 --- a/clang/test/OpenMP/for_linear_messages.cpp +++ b/clang/test/OpenMP/for_linear_messages.cpp @@ -1,12 +1,14 @@ // RUN: %clang_cc1 -verify -fopenmp %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp -fopenmp-version=52 -DOMP52 %s -Wuninitialized // RUN: %clang_cc1 -verify -fopenmp-simd %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp-simd -fopenmp-version=52 -DOMP52 %s -Wuninitialized extern int omp_default_mem_alloc; void xxx(int argc) { - int i, lin, step; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step' to silence this warning}} -#pragma omp for linear(lin : step) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step' is uninitialized when used here}} + int i, lin, step_sz; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step_sz' to silence this warning}} +#pragma omp for linear(lin : step_sz) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step_sz' is uninitialized when used here}} for (i = 0; i < 10; ++i) ; } @@ -213,15 +215,41 @@ int main(int argc, char **argv) { int i; #pragma omp for linear(i) for (int k = 0; k < argc; ++k) ++k; + #pragma omp for linear(val(i)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} + for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp for linear(i : step(4)) +#else #pragma omp for linear(i : 4) +#endif for (int k = 0; k < argc; ++k) { ++k; i += 4; } } +#ifdef OMP52 + #pragma omp for linear(j: step() //omp52-error 2 {{expected expression}} omp52-error{{expected ')'}} omp52-note{{to match this '('}} +#else #pragma omp for linear(j) +#endif for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp for linear(i: step(1), val) +#else #pragma omp for linear(i) +#endif for (int k = 0; k < argc; ++k) ++k; #pragma omp for linear(i) ordered(1) // expected-error {{'linear' clause cannot be specified along with 'ordered' clause with a parameter}} for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp for linear(j: step()) // omp52-error 2 {{expected expression}} + for (int k = 0; k < argc; ++k) ++k; + #pragma omp for linear(j: step(1), step(2)) // omp52-error {{multiple 'step size' found in linear clause}} + for (int k = 0; k < argc; ++k) ++k; + #pragma omp for linear(j: val, val) // omp52-error {{multiple 'linear modifier' found in linear clause}} + for (int k = 0; k < argc; ++k) ++k; + #pragma omp for linear(j: pval) // omp52-error{{use of undeclared identifier 'pval'}} + for (int k = 0; k < argc; ++k) ++k; + #pragma omp for linear(i: val, step(2 // omp52-error 3 {{expected ')'}} omp52-note 2 {{to match this '('}} + for (int k = 0; k < argc; ++k) ++k; +#endif foomain(argc,argv); // expected-note {{n instantiation of function template specialization 'foomain' requested here}} return 0; diff --git a/clang/test/OpenMP/for_reduction_codegen.cpp b/clang/test/OpenMP/for_reduction_codegen.cpp index 7dc8b81d60521..893c606f8d7b9 100644 --- a/clang/test/OpenMP/for_reduction_codegen.cpp +++ b/clang/test/OpenMP/for_reduction_codegen.cpp @@ -1,15 +1,15 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --check-globals --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ --global-value-regex ".gomp_critical_user[a-zA-Z_.]+" -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER diff --git a/clang/test/OpenMP/for_reduction_codegen_UDR.cpp b/clang/test/OpenMP/for_reduction_codegen_UDR.cpp index d9b7aba066755..14d903fd7ad71 100644 --- a/clang/test/OpenMP/for_reduction_codegen_UDR.cpp +++ b/clang/test/OpenMP/for_reduction_codegen_UDR.cpp @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 // expected-no-diagnostics #ifndef HEADER #define HEADER diff --git a/clang/test/OpenMP/for_simd_ast_print.cpp b/clang/test/OpenMP/for_simd_ast_print.cpp index 137a34a287703..0e8c13f7cc8fe 100644 --- a/clang/test/OpenMP/for_simd_ast_print.cpp +++ b/clang/test/OpenMP/for_simd_ast_print.cpp @@ -6,7 +6,10 @@ // RUN: %clang_cc1 -fopenmp -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -DOMP5 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP50 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=51 -ast-print %s -DOMP51 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP51 // RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -x c++ -std=c++11 -emit-pch -o %t %s -DOMP51 -// RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -DOMP51 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP51 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -DOMP51 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=52 -ast-print %s -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=52 -x c++ -std=c++11 -emit-pch -o %t %s -DOMP52 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=52 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -ast-print %s | FileCheck %s --check-prefix=CHECK --check-prefix=OMP45 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -emit-pch -o %t %s @@ -18,6 +21,10 @@ // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=51 -x c++ -std=c++11 -emit-pch -o %t %s -DOMP51 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=51 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -DOMP51 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP51 // expected-no-diagnostics +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=52 -ast-print %s -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=52 -x c++ -std=c++11 -emit-pch -o %t %s -DOMP52 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=52 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 +// expected-no-diagnostics #ifndef HEADER #define HEADER @@ -102,16 +109,19 @@ template struct S { // CHECK: T res; // CHECK: T val; // CHECK: T lin = 0; -#ifdef OMP51 +#ifdef OMP52 + #pragma omp for simd private(val) safelen(7) linear(lin : step(-5)) lastprivate(res) simdlen(5) allocate(res) if(res) nontemporal(res, val, lin) order(reproducible:concurrent) +#elif OMP51 #pragma omp for simd private(val) safelen(7) linear(lin : -5) lastprivate(res) simdlen(5) allocate(res) if(res) nontemporal(res, val, lin) order(reproducible:concurrent) #elif OMP5 #pragma omp for simd private(val) safelen(7) linear(lin : -5) lastprivate(res) simdlen(5) allocate(res) if(res) nontemporal(res, val, lin) order(concurrent) #else #pragma omp for simd private(val) safelen(7) linear(lin : -5) lastprivate(res) simdlen(5) allocate(res) #endif // OMP51 -// OMP51-NEXT: #pragma omp for simd private(val) safelen(7) linear(lin: -5) lastprivate(res) simdlen(5) allocate(res) if(res) nontemporal(res,val,lin) order(reproducible: concurrent) -// OMP50-NEXT: #pragma omp for simd private(val) safelen(7) linear(lin: -5) lastprivate(res) simdlen(5) allocate(res) if(res) nontemporal(res,val,lin) order(concurrent) -// OMP45-NEXT: #pragma omp for simd private(val) safelen(7) linear(lin: -5) lastprivate(res) simdlen(5) allocate(res) +// OMP52-NEXT: #pragma omp for simd private(val) safelen(7) linear(lin: step(-5)) lastprivate(res) simdlen(5) allocate(res) if(res) nontemporal(res,val,lin) order(reproducible: concurrent) +// OMP51-NEXT: #pragma omp for simd private(val) safelen(7) linear(lin: step(-5)) lastprivate(res) simdlen(5) allocate(res) if(res) nontemporal(res,val,lin) order(reproducible: concurrent) +// OMP50-NEXT: #pragma omp for simd private(val) safelen(7) linear(lin: step(-5)) lastprivate(res) simdlen(5) allocate(res) if(res) nontemporal(res,val,lin) order(concurrent) +// OMP45-NEXT: #pragma omp for simd private(val) safelen(7) linear(lin: step(-5)) lastprivate(res) simdlen(5) allocate(res) for (T i = 7; i < m_a; ++i) { val = v[i-7] + m_a; res = val; @@ -152,7 +162,7 @@ template struct S2 { // CHECK: template<> struct S2<4> { // CHECK-NEXT: static void func(int n, float *a, float *b, float *c) { // CHECK-NEXT: int k1 = 0, k2 = 0; -// CHECK-NEXT: #pragma omp for simd allocate(k1) safelen(4) linear(k1,k2: 4) aligned(a: 4) simdlen(4) +// CHECK-NEXT: #pragma omp for simd allocate(k1) safelen(4) linear(k1,k2: step(4)) aligned(a: 4) simdlen(4) // CHECK-NEXT: for (int i = 0; i < n; i++) { // CHECK-NEXT: c[i] = a[i] + b[i]; // CHECK-NEXT: c[k1] = a[k1] + b[k1]; @@ -194,9 +204,10 @@ int main (int argc, char **argv) { #else #pragma omp for simd aligned(a:CLEN) linear(a:CLEN) safelen(CLEN) collapse( 1 ) simdlen(CLEN) #endif -// OMP51-NEXT: #pragma omp for simd aligned(a: CLEN) linear(a: CLEN) safelen(CLEN) collapse(1) simdlen(CLEN) -// OMP50-NEXT: #pragma omp for simd aligned(a: CLEN) linear(a: CLEN) safelen(CLEN) collapse(1) simdlen(CLEN) if(simd: a) -// OMP45-NEXT: #pragma omp for simd aligned(a: CLEN) linear(a: CLEN) safelen(CLEN) collapse(1) simdlen(CLEN) +// OMP52-NEXT: #pragma omp for simd aligned(a: CLEN) linear(a: step(CLEN)) safelen(CLEN) collapse(1) simdlen(CLEN) +// OMP51-NEXT: #pragma omp for simd aligned(a: CLEN) linear(a: step(CLEN)) safelen(CLEN) collapse(1) simdlen(CLEN) +// OMP50-NEXT: #pragma omp for simd aligned(a: CLEN) linear(a: step(CLEN)) safelen(CLEN) collapse(1) simdlen(CLEN) if(simd: a) +// OMP45-NEXT: #pragma omp for simd aligned(a: CLEN) linear(a: step(CLEN)) safelen(CLEN) collapse(1) simdlen(CLEN) for (int i = 0; i < 10; ++i)foo(); // CHECK-NEXT: for (int i = 0; i < 10; ++i) // CHECK-NEXT: foo(); diff --git a/clang/test/OpenMP/for_simd_linear_messages.cpp b/clang/test/OpenMP/for_simd_linear_messages.cpp index 27b908739b1f2..a760675dcf34c 100644 --- a/clang/test/OpenMP/for_simd_linear_messages.cpp +++ b/clang/test/OpenMP/for_simd_linear_messages.cpp @@ -1,12 +1,14 @@ // RUN: %clang_cc1 -verify -fopenmp %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp -fopenmp-version=52 -DOMP52 %s -Wuninitialized // RUN: %clang_cc1 -verify -fopenmp-simd %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp-simd -fopenmp-version=52 -DOMP52 %s -Wuninitialized extern int omp_default_mem_alloc; void xxx(int argc) { - int i, lin, step; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step' to silence this warning}} -#pragma omp for simd linear(i, lin : step) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step' is uninitialized when used here}} + int i, lin, step_sz; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step_sz' to silence this warning}} +#pragma omp for simd linear(i, lin : step_sz) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step_sz' is uninitialized when used here}} for (i = 0; i < 10; ++i) ; } @@ -210,15 +212,35 @@ int main(int argc, char **argv) { #pragma omp parallel { int i; - #pragma omp for simd linear(i : i) + #pragma omp for simd linear(i) for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp for simd linear(i : step(4)) +#else #pragma omp for simd linear(i : 4) +#endif for (int k = 0; k < argc; ++k) { ++k; i += 4; } } +#ifdef OMP52 + #pragma omp for simd linear(j: step() //omp52-error 2 {{expected expression}} omp52-error{{expected ')'}} omp52-note{{to match this '('}} +#else #pragma omp for simd linear(j) +#endif for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp for simd linear(i: step(1), step(2)) // omp52-error {{multiple 'step size' found in linear clause}} +#else #pragma omp for simd linear(i) +#endif for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp for simd linear(j: step()) // omp52-error 2 {{expected expression}} + for (int k = 0; k < argc; ++k) ++k; + #pragma omp for simd linear(j: pval) // omp52-error {{use of undeclared identifier 'pval'}} + for (int k = 0; k < argc; ++k) ++k; + #pragma omp for simd linear(i: val, step(2 // omp52-error 3 {{expected ')'}} omp52-note 2 {{to match this '('}} + for (int k = 0; k < argc; ++k) ++k; +#endif foomain(argc,argv); // expected-note {{in instantiation of function template specialization 'foomain' requested here}} return 0; diff --git a/clang/test/OpenMP/generic_loop_ast_print.cpp b/clang/test/OpenMP/generic_loop_ast_print.cpp index 29c48ffde8092..df806405571cf 100644 --- a/clang/test/OpenMP/generic_loop_ast_print.cpp +++ b/clang/test/OpenMP/generic_loop_ast_print.cpp @@ -51,15 +51,15 @@ //DUMP: FunctionDecl{{.*}}templ_foo 'void (int)' //DUMP: TemplateArgument type 'int' //DUMP: TemplateArgument integral 2 -//DUMP: ParmVarDecl{{.*}}'int':'int' +//DUMP: ParmVarDecl{{.*}}'int' //DUMP: OMPSimdDirective //DUMP: OMPCollapseClause //DUMP: ConstantExpr{{.*}}'int' //DUMP: value: Int 2 //DUMP: OMPReductionClause -//DUMP: DeclRefExpr{{.*}}'z' 'int':'int' +//DUMP: DeclRefExpr{{.*}}'z' 'int' //DUMP: OMPLastprivateClause -//DUMP: DeclRefExpr{{.*}}'j' 'int':'int' +//DUMP: DeclRefExpr{{.*}}'j' 'int' //DUMP: ForStmt template void templ_foo(T t) { diff --git a/clang/test/OpenMP/masked_taskloop_simd_linear_messages.cpp b/clang/test/OpenMP/masked_taskloop_simd_linear_messages.cpp index 111b74f7d427c..50d2da7e8fd4d 100644 --- a/clang/test/OpenMP/masked_taskloop_simd_linear_messages.cpp +++ b/clang/test/OpenMP/masked_taskloop_simd_linear_messages.cpp @@ -1,6 +1,8 @@ // RUN: %clang_cc1 -verify -fopenmp %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp -fopenmp-version=52 -DOMP52 %s -Wuninitialized // RUN: %clang_cc1 -verify -fopenmp-simd %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp-simd -fopenmp-version=52 -DOMP52 %s -Wuninitialized typedef void **omp_allocator_handle_t; extern const omp_allocator_handle_t omp_null_allocator; @@ -14,8 +16,8 @@ extern const omp_allocator_handle_t omp_pteam_mem_alloc; extern const omp_allocator_handle_t omp_thread_mem_alloc; void xxx(int argc) { - int i, lin, step; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step' to silence this warning}} -#pragma omp master taskloop simd linear(i, lin : step) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step' is uninitialized when used here}} + int i, lin, step_sz; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step_sz' to silence this warning}} +#pragma omp masked taskloop simd linear(i, lin : step_sz) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step_sz' is uninitialized when used here}} for (i = 0; i < 10; ++i) ; } @@ -37,29 +39,29 @@ const int C2 = 2; void test_linear_colons() { int B = 0; - #pragma omp master taskloop simd linear(B:bfoo()) + #pragma omp masked taskloop simd linear(B:bfoo()) for (int i = 0; i < 10; ++i) ; // expected-error@+1 {{unexpected ':' in nested name specifier; did you mean '::'}} - #pragma omp master taskloop simd linear(B::ib:B:bfoo()) + #pragma omp masked taskloop simd linear(B::ib:B:bfoo()) for (int i = 0; i < 10; ++i) ; // expected-error@+1 {{use of undeclared identifier 'ib'; did you mean 'B::ib'}} - #pragma omp master taskloop simd linear(B:ib) + #pragma omp masked taskloop simd linear(B:ib) for (int i = 0; i < 10; ++i) ; // expected-error@+1 {{unexpected ':' in nested name specifier; did you mean '::'?}} - #pragma omp master taskloop simd linear(z:B:ib) + #pragma omp masked taskloop simd linear(z:B:ib) for (int i = 0; i < 10; ++i) ; - #pragma omp master taskloop simd linear(B:B::bfoo()) + #pragma omp masked taskloop simd linear(B:B::bfoo()) for (int i = 0; i < 10; ++i) ; - #pragma omp master taskloop simd linear(X::x : ::z) + #pragma omp masked taskloop simd linear(X::x : ::z) for (int i = 0; i < 10; ++i) ; - #pragma omp master taskloop simd linear(B,::z, X::x) + #pragma omp masked taskloop simd linear(B,::z, X::x) for (int i = 0; i < 10; ++i) ; - #pragma omp master taskloop simd linear(::z) + #pragma omp masked taskloop simd linear(::z) for (int i = 0; i < 10; ++i) ; // expected-error@+1 {{expected variable name}} - #pragma omp master taskloop simd linear(B::bfoo()) + #pragma omp masked taskloop simd linear(B::bfoo()) for (int i = 0; i < 10; ++i) ; - #pragma omp master taskloop simd linear(B::ib,B:C1+C2) + #pragma omp masked taskloop simd linear(B::ib,B:C1+C2) for (int i = 0; i < 10; ++i) ; } @@ -68,7 +70,7 @@ template T test_template(T* arr, N num) { T sum = (T)0; T ind2 = - num * L; // expected-note {{'ind2' defined here}} // expected-error@+1 {{argument of a linear clause should be of integral or pointer type}} -#pragma omp master taskloop simd linear(ind2:L) +#pragma omp masked taskloop simd linear(ind2:L) for (i = 0; i < num; ++i) { T cur = arr[(int)ind2]; ind2 += L; @@ -80,7 +82,7 @@ template T test_template(T* arr, N num) { template int test_warn() { int ind2 = 0; // expected-warning@+1 {{zero linear step (ind2 should probably be const)}} - #pragma omp master taskloop simd linear(ind2:LEN) + #pragma omp masked taskloop simd linear(ind2:LEN) for (int i = 0; i < 100; i++) { ind2 += LEN; } @@ -123,59 +125,66 @@ template int foomain(I argc, C **argv) { I g(5); int i, z; int &j = i; - #pragma omp master taskloop simd linear // expected-error {{expected '(' after 'linear'}} + #pragma omp masked taskloop simd linear // expected-error {{expected '(' after 'linear'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear ( // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} + #pragma omp masked taskloop simd linear ( // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (val // expected-error {{use of undeclared identifier 'val'}} expected-error {{expected ')'}} expected-note {{to match this '('}} + #pragma omp masked taskloop simd linear (val // expected-error {{use of undeclared identifier 'val'}} expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (uval( // expected-error {{expected expression}} expected-error 2 {{expected ')'}} expected-note 2 {{to match this '('}} + #pragma omp masked taskloop simd linear (uval( // expected-error {{expected expression}} expected-error 2 {{expected ')'}} expected-note 2 {{to match this '('}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (ref() // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} + #pragma omp masked taskloop simd linear (ref() // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (foo() // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} + #pragma omp masked taskloop simd linear (foo() // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear () // expected-error {{expected expression}} + #pragma omp masked taskloop simd linear () // expected-error {{expected expression}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (argc // expected-error {{expected ')'}} expected-note {{to match this '('}} + #pragma omp masked taskloop simd linear (argc // expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (val argc // expected-error {{use of undeclared identifier 'val'}} expected-error {{expected ')'}} expected-note {{to match this '('}} + #pragma omp masked taskloop simd linear (val argc // expected-error {{use of undeclared identifier 'val'}} expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (val(argc, // expected-error {{expected expression}} expected-error 2 {{expected ')'}} expected-note 2 {{to match this '('}} + #pragma omp masked taskloop simd linear (val(argc, // expected-error {{expected expression}} expected-error 2 {{expected ')'}} expected-note 2 {{to match this '('}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (argc > 0 ? argv[1] : argv[2]) // expected-error {{expected variable name}} + #pragma omp masked taskloop simd linear (argc > 0 ? argv[1] : argv[2]) // expected-error {{expected variable name}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (argc : 5) allocate , allocate(, allocate(omp_default , allocate(omp_default_mem_alloc, allocate(omp_default_mem_alloc:, allocate(omp_default_mem_alloc: argc, allocate(omp_default_mem_alloc: argv), allocate(argv) // expected-error {{expected '(' after 'allocate'}} expected-error 2 {{expected expression}} expected-error 2 {{expected ')'}} expected-error {{use of undeclared identifier 'omp_default'}} expected-note 2 {{to match this '('}} + #pragma omp masked taskloop simd linear (argc : 5) allocate , allocate(, allocate(omp_default , allocate(omp_default_mem_alloc, allocate(omp_default_mem_alloc:, allocate(omp_default_mem_alloc: argc, allocate(omp_default_mem_alloc: argv), allocate(argv) // expected-error {{expected '(' after 'allocate'}} expected-error 2 {{expected expression}} expected-error 2 {{expected ')'}} expected-error {{use of undeclared identifier 'omp_default'}} expected-note 2 {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (S1) // expected-error {{'S1' does not refer to a value}} + #pragma omp masked taskloop simd linear (S1) // expected-error {{'S1' does not refer to a value}} for (int k = 0; k < argc; ++k) ++k; +#if defined(OMP52) + // omp52-error@+3{{step simple modifier is exclusive and can't be use with 'val', 'uval' or 'ref' modifier}} // expected-error@+2 {{linear variable with incomplete type 'S1'}} // expected-error@+1 {{argument of a linear clause should be of integral or pointer type, not 'S2'}} - #pragma omp master taskloop simd linear (val(a, b):B::ib) + #pragma omp masked taskloop simd linear (a, b: val, B::ib) +#else + // expected-error@+2 {{linear variable with incomplete type 'S1'}} + // expected-error@+1 {{argument of a linear clause should be of integral or pointer type, not 'S2'}} + #pragma omp masked taskloop simd linear (val(a, b):B::ib) +#endif for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (argv[1]) // expected-error {{expected variable name}} + #pragma omp masked taskloop simd linear (argv[1]) // expected-error {{expected variable name}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear(ref(e, g)) // expected-error 2 {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'ref'}} + #pragma omp masked taskloop simd linear(ref(e, g)) // expected-error 2 {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'ref'}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear(h, z) // expected-error {{threadprivate or thread local variable cannot be linear}} + #pragma omp masked taskloop simd linear(h, z) // expected-error {{threadprivate or thread local variable cannot be linear}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear(uval(i)) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} + #pragma omp masked taskloop simd linear(uval(i)) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} omp52 {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel { int v = 0; int i; - #pragma omp master taskloop simd allocate(omp_thread_mem_alloc: v) linear(v:i) // expected-warning {{allocator with the 'thread' trait access has unspecified behavior on 'master taskloop simd' directive}} + #pragma omp masked taskloop simd allocate(omp_thread_mem_alloc: v) linear(v:i) // expected-warning {{allocator with the 'thread' trait access has unspecified behavior on 'masked taskloop simd' directive}} for (int k = 0; k < argc; ++k) { i = k; v += i; } } - #pragma omp master taskloop simd linear(ref(j)) + #pragma omp masked taskloop simd linear(ref(j)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear(uval(j)) + #pragma omp masked taskloop simd linear(uval(j)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; int v = 0; - #pragma omp master taskloop simd linear(v:j) + #pragma omp masked taskloop simd linear(v:j) for (int k = 0; k < argc; ++k) { ++k; v += j; } - #pragma omp master taskloop simd linear(i) + #pragma omp masked taskloop simd linear(i) for (int k = 0; k < argc; ++k) ++k; return 0; } @@ -190,15 +199,15 @@ using A::x; void linear_modifiers(int argc) { int &f = argc; - #pragma omp master taskloop simd linear(f) + #pragma omp masked taskloop simd linear(f) for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear(val(f)) + #pragma omp masked taskloop simd linear(val(f)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear(uval(f)) + #pragma omp masked taskloop simd linear(uval(f)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear(ref(f)) + #pragma omp masked taskloop simd linear(ref(f)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear(foo(f)) // expected-error {{expected one of 'ref', val' or 'uval' modifiers}} + #pragma omp masked taskloop simd linear(foo(f)) // expected-error {{expected one of 'ref', val' or 'uval' modifiers}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; } @@ -214,54 +223,77 @@ int main(int argc, char **argv) { S5 g(5); // expected-note {{'g' defined here}} int i, z; int &j = i; - #pragma omp master taskloop simd linear(f) linear(f) // expected-error {{linear variable cannot be linear}} expected-note {{defined as linear}} + #pragma omp masked taskloop simd linear(f) linear(f) // expected-error {{linear variable cannot be linear}} expected-note {{defined as linear}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear // expected-error {{expected '(' after 'linear'}} + #pragma omp masked taskloop simd linear // expected-error {{expected '(' after 'linear'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear ( // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} + #pragma omp masked taskloop simd linear ( // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear () // expected-error {{expected expression}} + #pragma omp masked taskloop simd linear () // expected-error {{expected expression}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (val // expected-error {{use of undeclared identifier 'val'}} expected-error {{expected ')'}} expected-note {{to match this '('}} + #pragma omp masked taskloop simd linear (val // expected-error {{use of undeclared identifier 'val'}} expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (ref()) // expected-error {{expected expression}} + #pragma omp masked taskloop simd linear (ref()) // expected-error {{expected expression}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (foo()) // expected-error {{expected expression}} + #pragma omp masked taskloop simd linear (foo()) // expected-error {{expected expression}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (argc // expected-error {{expected ')'}} expected-note {{to match this '('}} + #pragma omp masked taskloop simd linear (argc // expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (argc, // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} + #pragma omp masked taskloop simd linear (argc, // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (argc > 0 ? argv[1] : argv[2]) // expected-error {{expected variable name}} + #pragma omp masked taskloop simd linear (argc > 0 ? argv[1] : argv[2]) // expected-error {{expected variable name}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (argc, z) + #pragma omp masked taskloop simd linear (argc, z) for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (S1) // expected-error {{'S1' does not refer to a value}} + #pragma omp masked taskloop simd linear (S1) // expected-error {{'S1' does not refer to a value}} for (int k = 0; k < argc; ++k) ++k; // expected-error@+2 {{linear variable with incomplete type 'S1'}} // expected-error@+1 {{argument of a linear clause should be of integral or pointer type, not 'S2'}} - #pragma omp master taskloop simd linear(a, b) + #pragma omp masked taskloop simd linear(a, b) for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (argv[1]) // expected-error {{expected variable name}} + #pragma omp masked taskloop simd linear (argv[1]) // expected-error {{expected variable name}} for (int k = 0; k < argc; ++k) ++k; + // omp52-error@+3 {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} // expected-error@+2 {{argument of a linear clause should be of integral or pointer type, not 'S4'}} // expected-error@+1 {{argument of a linear clause should be of integral or pointer type, not 'S5'}} - #pragma omp master taskloop simd linear(val(e, g)) + #pragma omp masked taskloop simd linear(val(e, g)) for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear(h, C::x) // expected-error 2 {{threadprivate or thread local variable cannot be linear}} + #pragma omp masked taskloop simd linear(h, C::x) // expected-error 2 {{threadprivate or thread local variable cannot be linear}} for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel { int i; - #pragma omp master taskloop simd linear(val(i)) + #pragma omp masked taskloop simd linear(val(i)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear(uval(i) : 4) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} +#ifdef OMP52 + #pragma omp masked taskloop simd linear(i : uval, step(4)) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} +#else + #pragma omp masked taskloop simd linear(uval(i) : 4) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} +#endif for (int k = 0; k < argc; ++k) { ++k; i += 4; } } - #pragma omp master taskloop simd linear(ref(j)) +#ifdef OMP52 + #pragma omp masked taskloop simd linear(j: ref) +#else + #pragma omp masked taskloop simd linear(ref(j)) +#endif + for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp masked taskloop simd linear(i: step(1), step(2)) // omp52-error {{multiple 'step size' found in linear clause}} +#else + #pragma omp masked taskloop simd linear(i) +#endif + for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp masked taskloop simd linear(i: val, val) // omp52-error {{multiple 'linear modifier' found in linear clause}} + for (int k = 0; k < argc; ++k) ++k; + #pragma omp masked taskloop simd linear(j: step()) // omp52-error 2 {{expected expression}} + for (int k = 0; k < argc; ++k) ++k; + #pragma omp masked taskloop simd linear(j: pval) // omp52-error {{use of undeclared identifier 'pval'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear(i) + #pragma omp masked taskloop simd linear(i: val, step(2 // omp52-error {{expected ')' or ',' after 'step expression'}} omp52-error 2 {{expected ')'}} omp52-note 2 {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; +#endif foomain(argc,argv); // expected-note {{in instantiation of function template specialization 'foomain' requested here}} return 0; diff --git a/clang/test/OpenMP/master_taskloop_firstprivate_codegen.cpp b/clang/test/OpenMP/master_taskloop_firstprivate_codegen.cpp index 4dfce7fd3ead7..a238422755561 100644 --- a/clang/test/OpenMP/master_taskloop_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_firstprivate_codegen.cpp @@ -1,16 +1,16 @@ -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp b/clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp index d22d884d3269b..9886b71dc135f 100644 --- a/clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER diff --git a/clang/test/OpenMP/master_taskloop_lastprivate_codegen.cpp b/clang/test/OpenMP/master_taskloop_lastprivate_codegen.cpp index d86ecd1b6ef1b..63900ffeb3bfe 100644 --- a/clang/test/OpenMP/master_taskloop_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_lastprivate_codegen.cpp @@ -1,18 +1,18 @@ -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLOOP -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LOOP %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLOOP -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LOOP %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLOOP -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLOOP -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/master_taskloop_private_codegen.cpp b/clang/test/OpenMP/master_taskloop_private_codegen.cpp index 1a63c0a664e7e..518808f5ca30d 100644 --- a/clang/test/OpenMP/master_taskloop_private_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_private_codegen.cpp @@ -1,16 +1,16 @@ -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/master_taskloop_reduction_codegen.cpp b/clang/test/OpenMP/master_taskloop_reduction_codegen.cpp index e2178f6457bae..05450785c0d63 100644 --- a/clang/test/OpenMP/master_taskloop_reduction_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_reduction_codegen.cpp @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 -fopenmp -x c++ %s -verify -debug-info-kind=limited -emit-llvm -o - -triple powerpc64le-unknown-linux-gnu -fnoopenmp-use-tls -std=c++98 | FileCheck %s +// RUN: %clang_cc1 -fopenmp -x c++ %s -verify -Wno-vla -debug-info-kind=limited -emit-llvm -o - -triple powerpc64le-unknown-linux-gnu -fnoopenmp-use-tls -std=c++98 | FileCheck %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ %s -verify -debug-info-kind=limited -emit-llvm -o - -triple powerpc64le-unknown-linux-gnu -fnoopenmp-use-tls -std=c++98 | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ %s -verify -Wno-vla -debug-info-kind=limited -emit-llvm -o - -triple powerpc64le-unknown-linux-gnu -fnoopenmp-use-tls -std=c++98 | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/master_taskloop_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/master_taskloop_simd_firstprivate_codegen.cpp index a8da845245943..785efe3ec1f1c 100644 --- a/clang/test/OpenMP/master_taskloop_simd_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_simd_firstprivate_codegen.cpp @@ -1,16 +1,16 @@ -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp b/clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp index aeecfdcd337e6..76e5794b6fa5d 100644 --- a/clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 // expected-no-diagnostics #ifndef HEADER #define HEADER diff --git a/clang/test/OpenMP/master_taskloop_simd_lastprivate_codegen.cpp b/clang/test/OpenMP/master_taskloop_simd_lastprivate_codegen.cpp index 8d7de7ba58535..8a2af21fba9e8 100644 --- a/clang/test/OpenMP/master_taskloop_simd_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_simd_lastprivate_codegen.cpp @@ -1,16 +1,16 @@ -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/master_taskloop_simd_linear_messages.cpp b/clang/test/OpenMP/master_taskloop_simd_linear_messages.cpp index 111b74f7d427c..ee29f63e110c0 100644 --- a/clang/test/OpenMP/master_taskloop_simd_linear_messages.cpp +++ b/clang/test/OpenMP/master_taskloop_simd_linear_messages.cpp @@ -1,6 +1,8 @@ // RUN: %clang_cc1 -verify -fopenmp %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp -fopenmp-version=52 -DOMP52 %s -Wuninitialized // RUN: %clang_cc1 -verify -fopenmp-simd %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp-simd -fopenmp-version=52 -DOMP52 %s -Wuninitialized typedef void **omp_allocator_handle_t; extern const omp_allocator_handle_t omp_null_allocator; @@ -14,8 +16,8 @@ extern const omp_allocator_handle_t omp_pteam_mem_alloc; extern const omp_allocator_handle_t omp_thread_mem_alloc; void xxx(int argc) { - int i, lin, step; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step' to silence this warning}} -#pragma omp master taskloop simd linear(i, lin : step) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step' is uninitialized when used here}} + int i, lin, step_sz; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step_sz' to silence this warning}} +#pragma omp master taskloop simd linear(i, lin : step_sz) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step_sz' is uninitialized when used here}} for (i = 0; i < 10; ++i) ; } @@ -129,11 +131,11 @@ template int foomain(I argc, C **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp master taskloop simd linear (val // expected-error {{use of undeclared identifier 'val'}} expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (uval( // expected-error {{expected expression}} expected-error 2 {{expected ')'}} expected-note 2 {{to match this '('}} + #pragma omp master taskloop simd linear (uval( // expected-error {{expected expression}} expected-error 2 {{expected ')'}} expected-note 2 {{to match this '('}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (ref() // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} + #pragma omp master taskloop simd linear (ref() // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (foo() // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} + #pragma omp master taskloop simd linear (foo() // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp master taskloop simd linear () // expected-error {{expected expression}} for (int k = 0; k < argc; ++k) ++k; @@ -141,7 +143,7 @@ template int foomain(I argc, C **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp master taskloop simd linear (val argc // expected-error {{use of undeclared identifier 'val'}} expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (val(argc, // expected-error {{expected expression}} expected-error 2 {{expected ')'}} expected-note 2 {{to match this '('}} + #pragma omp master taskloop simd linear (val(argc, // expected-error {{expected expression}} expected-error 2 {{expected ')'}} expected-note 2 {{to match this '('}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp master taskloop simd linear (argc > 0 ? argv[1] : argv[2]) // expected-error {{expected variable name}} for (int k = 0; k < argc; ++k) ++k; @@ -149,17 +151,25 @@ template int foomain(I argc, C **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp master taskloop simd linear (S1) // expected-error {{'S1' does not refer to a value}} for (int k = 0; k < argc; ++k) ++k; +#if defined(OMP52) + // omp52-error@+3{{step simple modifier is exclusive and can't be use with 'val', 'uval' or 'ref' modifier}} + // expected-error@+2 {{linear variable with incomplete type 'S1'}} + // expected-error@+1 {{argument of a linear clause should be of integral or pointer type, not 'S2'}} + #pragma omp master taskloop simd linear (a, b: val, B::ib) +#else + // omp52-error@+3 {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} // expected-error@+2 {{linear variable with incomplete type 'S1'}} // expected-error@+1 {{argument of a linear clause should be of integral or pointer type, not 'S2'}} #pragma omp master taskloop simd linear (val(a, b):B::ib) +#endif for (int k = 0; k < argc; ++k) ++k; #pragma omp master taskloop simd linear (argv[1]) // expected-error {{expected variable name}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear(ref(e, g)) // expected-error 2 {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'ref'}} + #pragma omp master taskloop simd linear(ref(e, g)) // expected-error 2 {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'ref'}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp master taskloop simd linear(h, z) // expected-error {{threadprivate or thread local variable cannot be linear}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear(uval(i)) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} + #pragma omp master taskloop simd linear(uval(i)) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel { @@ -168,9 +178,9 @@ template int foomain(I argc, C **argv) { #pragma omp master taskloop simd allocate(omp_thread_mem_alloc: v) linear(v:i) // expected-warning {{allocator with the 'thread' trait access has unspecified behavior on 'master taskloop simd' directive}} for (int k = 0; k < argc; ++k) { i = k; v += i; } } - #pragma omp master taskloop simd linear(ref(j)) + #pragma omp master taskloop simd linear(ref(j)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear(uval(j)) + #pragma omp master taskloop simd linear(uval(j)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; int v = 0; #pragma omp master taskloop simd linear(v:j) @@ -192,13 +202,13 @@ void linear_modifiers(int argc) { int &f = argc; #pragma omp master taskloop simd linear(f) for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear(val(f)) + #pragma omp master taskloop simd linear(val(f)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear(uval(f)) + #pragma omp master taskloop simd linear(uval(f)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear(ref(f)) + #pragma omp master taskloop simd linear(ref(f)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear(foo(f)) // expected-error {{expected one of 'ref', val' or 'uval' modifiers}} + #pragma omp master taskloop simd linear(foo(f)) // expected-error {{expected one of 'ref', val' or 'uval' modifiers}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; } @@ -224,9 +234,9 @@ int main(int argc, char **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp master taskloop simd linear (val // expected-error {{use of undeclared identifier 'val'}} expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (ref()) // expected-error {{expected expression}} + #pragma omp master taskloop simd linear (ref()) // expected-error {{expected expression}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear (foo()) // expected-error {{expected expression}} + #pragma omp master taskloop simd linear (foo()) // expected-error {{expected expression}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp master taskloop simd linear (argc // expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; @@ -244,6 +254,7 @@ int main(int argc, char **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp master taskloop simd linear (argv[1]) // expected-error {{expected variable name}} for (int k = 0; k < argc; ++k) ++k; + // omp52-error@+3 {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} // expected-error@+2 {{argument of a linear clause should be of integral or pointer type, not 'S4'}} // expected-error@+1 {{argument of a linear clause should be of integral or pointer type, not 'S5'}} #pragma omp master taskloop simd linear(val(e, g)) @@ -253,15 +264,37 @@ int main(int argc, char **argv) { #pragma omp parallel { int i; - #pragma omp master taskloop simd linear(val(i)) + #pragma omp master taskloop simd linear(val(i)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp master taskloop simd linear(uval(i) : 4) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} +#ifdef OMP52 + #pragma omp master taskloop simd linear(i : uval, step(4)) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} +#else + #pragma omp master taskloop simd linear(uval(i) : 4) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} +#endif for (int k = 0; k < argc; ++k) { ++k; i += 4; } } - #pragma omp master taskloop simd linear(ref(j)) - for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp master taskloop simd linear(j: ref) +#else + #pragma omp master taskloop simd linear(ref(j)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} +#endif + for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp master taskloop simd linear(i: step(1), step(2)) // omp52-error {{multiple 'step size' found in linear clause}} +#else #pragma omp master taskloop simd linear(i) +#endif + for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp master taskloop simd linear(i: val, val) // omp52-error {{multiple 'linear modifier' found in linear clause}} + for (int k = 0; k < argc; ++k) ++k; + #pragma omp master taskloop simd linear(j: step()) // omp52-error 2 {{expected expression}} + for (int k = 0; k < argc; ++k) ++k; + #pragma omp master taskloop simd linear(j: pval) // omp52-error {{use of undeclared identifier 'pval'}} + for (int k = 0; k < argc; ++k) ++k; + #pragma omp master taskloop simd linear(i: val, step(2 // omp52-error {{expected ')' or ',' after 'step expression'}} omp52-error 2 {{expected ')'}} omp52-note 2 {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; +#endif foomain(argc,argv); // expected-note {{in instantiation of function template specialization 'foomain' requested here}} return 0; diff --git a/clang/test/OpenMP/master_taskloop_simd_private_codegen.cpp b/clang/test/OpenMP/master_taskloop_simd_private_codegen.cpp index 4aae9ea42503a..b70a45f55c6e6 100644 --- a/clang/test/OpenMP/master_taskloop_simd_private_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_simd_private_codegen.cpp @@ -1,16 +1,16 @@ -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/master_taskloop_simd_reduction_codegen.cpp b/clang/test/OpenMP/master_taskloop_simd_reduction_codegen.cpp index 0782d4710dcda..2e07b136f56f0 100644 --- a/clang/test/OpenMP/master_taskloop_simd_reduction_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_simd_reduction_codegen.cpp @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 -fopenmp -x c++ %s -verify -debug-info-kind=limited -emit-llvm -o - -triple powerpc64le-unknown-linux-gnu -std=c++98 -fnoopenmp-use-tls | FileCheck %s +// RUN: %clang_cc1 -fopenmp -x c++ %s -verify -Wno-vla -debug-info-kind=limited -emit-llvm -o - -triple powerpc64le-unknown-linux-gnu -std=c++98 -fnoopenmp-use-tls | FileCheck %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ %s -verify -debug-info-kind=limited -emit-llvm -o - -triple powerpc64le-unknown-linux-gnu -std=c++98 -fnoopenmp-use-tls | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ %s -verify -Wno-vla -debug-info-kind=limited -emit-llvm -o - -triple powerpc64le-unknown-linux-gnu -std=c++98 -fnoopenmp-use-tls | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/nvptx_target_codegen.cpp b/clang/test/OpenMP/nvptx_target_codegen.cpp index 58e487e866e43..cea2fd4e75125 100644 --- a/clang/test/OpenMP/nvptx_target_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_codegen.cpp @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2 // expected-no-diagnostics #ifndef HEADER diff --git a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp index ce8b2d6b4622e..df43851378bcb 100644 --- a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp @@ -98,7 +98,7 @@ int bar(int n){ // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[L_CASTED]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], i64 [[TMP6]]) #[[ATTR3:[0-9]+]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: call void @__kmpc_target_deinit() // CHECK1-NEXT: ret void // CHECK1: worker.exit: @@ -116,13 +116,13 @@ int bar(int n){ // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[I3:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[L_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x ptr], align 8 @@ -132,21 +132,20 @@ int bar(int n){ // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[L]], ptr [[L_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: [[L1:%.*]] = call align 8 ptr @__kmpc_alloc_shared(i64 4) // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK1-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK1-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: store i32 0, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK1: omp.precond.then: // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 @@ -154,11 +153,11 @@ int bar(int n){ // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 // CHECK1-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 128) // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK1-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] -// CHECK1-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK1-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK1-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK1: cond.true: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: br label [[COND_END:%.*]] // CHECK1: cond.false: // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 @@ -171,10 +170,10 @@ int bar(int n){ // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK1-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] -// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK1-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] +// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 @@ -207,29 +206,29 @@ int bar(int n){ // CHECK1: omp.inner.for.inc: // CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] -// CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] +// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP35]], [[TMP36]] -// CHECK1-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP35]], [[TMP36]] +// CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP37]], [[TMP38]] -// CHECK1-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP37]], [[TMP38]] +// CHECK1-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK1-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP39]], [[TMP40]] -// CHECK1-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] -// CHECK1: cond.true11: -// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK1-NEXT: br label [[COND_END13:%.*]] -// CHECK1: cond.false12: +// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK1-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP39]], [[TMP40]] +// CHECK1-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] +// CHECK1: cond.true10: +// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK1-NEXT: br label [[COND_END12:%.*]] +// CHECK1: cond.false11: // CHECK1-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: br label [[COND_END13]] -// CHECK1: cond.end13: -// CHECK1-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP41]], [[COND_TRUE11]] ], [ [[TMP42]], [[COND_FALSE12]] ] -// CHECK1-NEXT: store i32 [[COND14]], ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: br label [[COND_END12]] +// CHECK1: cond.end12: +// CHECK1-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP41]], [[COND_TRUE10]] ], [ [[TMP42]], [[COND_FALSE11]] ] +// CHECK1-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: store i32 [[TMP43]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] @@ -249,7 +248,6 @@ int bar(int n){ // CHECK1: .omp.lastprivate.done: // CHECK1-NEXT: br label [[OMP_PRECOND_END]] // CHECK1: omp.precond.end: -// CHECK1-NEXT: call void @__kmpc_free_shared(ptr [[L1]], i64 4) // CHECK1-NEXT: ret void // // @@ -386,7 +384,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34 -// CHECK1-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8 @@ -406,7 +404,7 @@ int bar(int n){ // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]] // CHECK1-NEXT: call void @__kmpc_target_deinit() // CHECK1-NEXT: ret void // CHECK1: worker.exit: @@ -652,7 +650,7 @@ int bar(int n){ // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK1-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]] // CHECK1-NEXT: call void @__kmpc_target_deinit() // CHECK1-NEXT: ret void // CHECK1: worker.exit: @@ -843,7 +841,7 @@ int bar(int n){ // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[F_CASTED]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR3]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR2]] // CHECK1-NEXT: call void @__kmpc_target_deinit() // CHECK1-NEXT: ret void // CHECK1: worker.exit: @@ -1069,7 +1067,7 @@ int bar(int n){ // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]] // CHECK1-NEXT: call void @__kmpc_target_deinit() // CHECK1-NEXT: ret void // CHECK1: worker.exit: @@ -1382,7 +1380,7 @@ int bar(int n){ // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[V_ADDR]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], ptr [[TMP5]]) #[[ATTR3]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], ptr [[TMP5]]) #[[ATTR2]] // CHECK1-NEXT: call void @__kmpc_target_deinit() // CHECK1-NEXT: ret void // CHECK1: worker.exit: @@ -1648,7 +1646,7 @@ int bar(int n){ // CHECK2-NEXT: [[TMP6:%.*]] = load i64, ptr [[L_CASTED]], align 8 // CHECK2-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], i64 [[TMP6]]) #[[ATTR3:[0-9]+]] +// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: call void @__kmpc_target_deinit() // CHECK2-NEXT: ret void // CHECK2: worker.exit: @@ -1666,13 +1664,13 @@ int bar(int n){ // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[I3:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[L_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x ptr], align 8 @@ -1682,21 +1680,20 @@ int bar(int n){ // CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[L]], ptr [[L_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK2-NEXT: [[L1:%.*]] = call align 8 ptr @__kmpc_alloc_shared(i64 4) // CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK2-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK2-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK2-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK2-NEXT: store i32 0, ptr [[I]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK2: omp.precond.then: // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK2-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 @@ -1704,11 +1701,11 @@ int bar(int n){ // CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 // CHECK2-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 128) // CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK2-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] -// CHECK2-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK2-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK2-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK2: cond.true: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK2-NEXT: br label [[COND_END:%.*]] // CHECK2: cond.false: // CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 @@ -1721,10 +1718,10 @@ int bar(int n){ // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: // CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK2-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] -// CHECK2-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK2-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] +// CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: // CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 @@ -1757,29 +1754,29 @@ int bar(int n){ // CHECK2: omp.inner.for.inc: // CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] -// CHECK2-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] +// CHECK2-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP35]], [[TMP36]] -// CHECK2-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP35]], [[TMP36]] +// CHECK2-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP37]], [[TMP38]] -// CHECK2-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP37]], [[TMP38]] +// CHECK2-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK2-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK2-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP39]], [[TMP40]] -// CHECK2-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] -// CHECK2: cond.true11: -// CHECK2-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK2-NEXT: br label [[COND_END13:%.*]] -// CHECK2: cond.false12: +// CHECK2-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK2-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP39]], [[TMP40]] +// CHECK2-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] +// CHECK2: cond.true10: +// CHECK2-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK2-NEXT: br label [[COND_END12:%.*]] +// CHECK2: cond.false11: // CHECK2-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK2-NEXT: br label [[COND_END13]] -// CHECK2: cond.end13: -// CHECK2-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP41]], [[COND_TRUE11]] ], [ [[TMP42]], [[COND_FALSE12]] ] -// CHECK2-NEXT: store i32 [[COND14]], ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK2-NEXT: br label [[COND_END12]] +// CHECK2: cond.end12: +// CHECK2-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP41]], [[COND_TRUE10]] ], [ [[TMP42]], [[COND_FALSE11]] ] +// CHECK2-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: store i32 [[TMP43]], ptr [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] @@ -1799,7 +1796,6 @@ int bar(int n){ // CHECK2: .omp.lastprivate.done: // CHECK2-NEXT: br label [[OMP_PRECOND_END]] // CHECK2: omp.precond.end: -// CHECK2-NEXT: call void @__kmpc_free_shared(ptr [[L1]], i64 4) // CHECK2-NEXT: ret void // // @@ -1936,7 +1932,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34 -// CHECK2-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK2-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8 @@ -1956,7 +1952,7 @@ int bar(int n){ // CHECK2-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK2-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]] // CHECK2-NEXT: call void @__kmpc_target_deinit() // CHECK2-NEXT: ret void // CHECK2: worker.exit: @@ -2202,7 +2198,7 @@ int bar(int n){ // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK2-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]] // CHECK2-NEXT: call void @__kmpc_target_deinit() // CHECK2-NEXT: ret void // CHECK2: worker.exit: @@ -2393,7 +2389,7 @@ int bar(int n){ // CHECK2-NEXT: [[TMP4:%.*]] = load i64, ptr [[F_CASTED]], align 8 // CHECK2-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR3]] +// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR2]] // CHECK2-NEXT: call void @__kmpc_target_deinit() // CHECK2-NEXT: ret void // CHECK2: worker.exit: @@ -2619,7 +2615,7 @@ int bar(int n){ // CHECK2-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK2-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]] // CHECK2-NEXT: call void @__kmpc_target_deinit() // CHECK2-NEXT: ret void // CHECK2: worker.exit: @@ -2927,7 +2923,7 @@ int bar(int n){ // CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[V_ADDR]], align 8 // CHECK2-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], ptr [[TMP5]]) #[[ATTR3]] +// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], ptr [[TMP5]]) #[[ATTR2]] // CHECK2-NEXT: call void @__kmpc_target_deinit() // CHECK2-NEXT: ret void // CHECK2: worker.exit: @@ -3193,7 +3189,7 @@ int bar(int n){ // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[L_CASTED]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]], i32 [[TMP6]]) #[[ATTR3:[0-9]+]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: call void @__kmpc_target_deinit() // CHECK3-NEXT: ret void // CHECK3: worker.exit: @@ -3211,13 +3207,13 @@ int bar(int n){ // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I3:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[L_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x ptr], align 4 @@ -3227,21 +3223,20 @@ int bar(int n){ // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[L]], ptr [[L_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK3-NEXT: [[L1:%.*]] = call align 8 ptr @__kmpc_alloc_shared(i32 4) // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK3-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK3-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK3-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK3-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK3-NEXT: store i32 0, ptr [[I]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK3: omp.precond.then: // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 @@ -3249,11 +3244,11 @@ int bar(int n){ // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 // CHECK3-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 128) // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK3-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] -// CHECK3-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK3-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK3: cond.true: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK3-NEXT: br label [[COND_END:%.*]] // CHECK3: cond.false: // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 @@ -3266,10 +3261,10 @@ int bar(int n){ // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK3-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] -// CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] +// CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 @@ -3300,29 +3295,29 @@ int bar(int n){ // CHECK3: omp.inner.for.inc: // CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP31]], [[TMP32]] -// CHECK3-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP31]], [[TMP32]] +// CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] -// CHECK3-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] +// CHECK3-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP35]], [[TMP36]] -// CHECK3-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP35]], [[TMP36]] +// CHECK3-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK3-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP37]], [[TMP38]] -// CHECK3-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] -// CHECK3: cond.true11: -// CHECK3-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK3-NEXT: br label [[COND_END13:%.*]] -// CHECK3: cond.false12: +// CHECK3-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK3-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP37]], [[TMP38]] +// CHECK3-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] +// CHECK3: cond.true10: +// CHECK3-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK3-NEXT: br label [[COND_END12:%.*]] +// CHECK3: cond.false11: // CHECK3-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: br label [[COND_END13]] -// CHECK3: cond.end13: -// CHECK3-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP39]], [[COND_TRUE11]] ], [ [[TMP40]], [[COND_FALSE12]] ] -// CHECK3-NEXT: store i32 [[COND14]], ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END12]] +// CHECK3: cond.end12: +// CHECK3-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP39]], [[COND_TRUE10]] ], [ [[TMP40]], [[COND_FALSE11]] ] +// CHECK3-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: store i32 [[TMP41]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] @@ -3342,7 +3337,6 @@ int bar(int n){ // CHECK3: .omp.lastprivate.done: // CHECK3-NEXT: br label [[OMP_PRECOND_END]] // CHECK3: omp.precond.end: -// CHECK3-NEXT: call void @__kmpc_free_shared(ptr [[L1]], i32 4) // CHECK3-NEXT: ret void // // @@ -3474,7 +3468,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34 -// CHECK3-SAME: (i32 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK3-SAME: (i32 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4 @@ -3494,7 +3488,7 @@ int bar(int n){ // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]] // CHECK3-NEXT: call void @__kmpc_target_deinit() // CHECK3-NEXT: ret void // CHECK3: worker.exit: @@ -3734,7 +3728,7 @@ int bar(int n){ // CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK3-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]] // CHECK3-NEXT: call void @__kmpc_target_deinit() // CHECK3-NEXT: ret void // CHECK3: worker.exit: @@ -3919,7 +3913,7 @@ int bar(int n){ // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[F_CASTED]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i32 [[TMP4]]) #[[ATTR3]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i32 [[TMP4]]) #[[ATTR2]] // CHECK3-NEXT: call void @__kmpc_target_deinit() // CHECK3-NEXT: ret void // CHECK3: worker.exit: @@ -4138,7 +4132,7 @@ int bar(int n){ // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]] // CHECK3-NEXT: call void @__kmpc_target_deinit() // CHECK3-NEXT: ret void // CHECK3: worker.exit: @@ -4454,7 +4448,7 @@ int bar(int n){ // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[V_ADDR]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]], ptr [[TMP5]]) #[[ATTR3]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]], ptr [[TMP5]]) #[[ATTR2]] // CHECK3-NEXT: call void @__kmpc_target_deinit() // CHECK3-NEXT: ret void // CHECK3: worker.exit: diff --git a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp index 6a3f968e74b10..fdd4457739510 100644 --- a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp @@ -86,7 +86,7 @@ int bar(int n){ // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[L_CASTED]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], i64 [[TMP6]]) #[[ATTR3:[0-9]+]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: call void @__kmpc_target_deinit() // CHECK1-NEXT: ret void // CHECK1: worker.exit: @@ -104,13 +104,13 @@ int bar(int n){ // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[I3:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[L_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x ptr], align 8 @@ -120,21 +120,20 @@ int bar(int n){ // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[L]], ptr [[L_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: [[L1:%.*]] = call align 8 ptr @__kmpc_alloc_shared(i64 4) // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK1-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK1-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: store i32 0, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK1: omp.precond.then: // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 @@ -142,11 +141,11 @@ int bar(int n){ // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 // CHECK1-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 128) // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK1-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] -// CHECK1-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK1-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK1-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK1: cond.true: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: br label [[COND_END:%.*]] // CHECK1: cond.false: // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 @@ -158,69 +157,69 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK1-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] -// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK1-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] +// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[N_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK1-NEXT: store i32 [[TMP18]], ptr [[N_CASTED]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8, !llvm.access.group [[ACC_GRP12]] -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK1-NEXT: store i32 [[TMP20]], ptr [[L_CASTED]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[L_CASTED]], align 8, !llvm.access.group [[ACC_GRP12]] +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[N_ADDR]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: store i32 [[TMP18]], ptr [[N_CASTED]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: store i32 [[TMP20]], ptr [[L_CASTED]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[L_CASTED]], align 8, !llvm.access.group [[ACC_GRP16]] // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK1-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP15]] to ptr -// CHECK1-NEXT: store ptr [[TMP23]], ptr [[TMP22]], align 8, !llvm.access.group [[ACC_GRP12]] +// CHECK1-NEXT: store ptr [[TMP23]], ptr [[TMP22]], align 8, !llvm.access.group [[ACC_GRP16]] // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 // CHECK1-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP17]] to ptr -// CHECK1-NEXT: store ptr [[TMP25]], ptr [[TMP24]], align 8, !llvm.access.group [[ACC_GRP12]] +// CHECK1-NEXT: store ptr [[TMP25]], ptr [[TMP24]], align 8, !llvm.access.group [[ACC_GRP16]] // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2 // CHECK1-NEXT: [[TMP27:%.*]] = inttoptr i64 [[TMP19]] to ptr -// CHECK1-NEXT: store ptr [[TMP27]], ptr [[TMP26]], align 8, !llvm.access.group [[ACC_GRP12]] +// CHECK1-NEXT: store ptr [[TMP27]], ptr [[TMP26]], align 8, !llvm.access.group [[ACC_GRP16]] // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3 -// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP28]], align 8, !llvm.access.group [[ACC_GRP12]] +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP28]], align 8, !llvm.access.group [[ACC_GRP16]] // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 4 // CHECK1-NEXT: [[TMP30:%.*]] = inttoptr i64 [[TMP21]] to ptr -// CHECK1-NEXT: store ptr [[TMP30]], ptr [[TMP29]], align 8, !llvm.access.group [[ACC_GRP12]] -// CHECK1-NEXT: [[TMP31:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group [[ACC_GRP12]] -// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[TMP31]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP32]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 5), !llvm.access.group [[ACC_GRP12]] +// CHECK1-NEXT: store ptr [[TMP30]], ptr [[TMP29]], align 8, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: [[TMP31:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[TMP31]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP32]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 5), !llvm.access.group [[ACC_GRP16]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] -// CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP35]], [[TMP36]] -// CHECK1-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP37]], [[TMP38]] -// CHECK1-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK1-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP39]], [[TMP40]] -// CHECK1-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] -// CHECK1: cond.true11: -// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK1-NEXT: br label [[COND_END13:%.*]] -// CHECK1: cond.false12: -// CHECK1-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK1-NEXT: br label [[COND_END13]] -// CHECK1: cond.end13: -// CHECK1-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP41]], [[COND_TRUE11]] ], [ [[TMP42]], [[COND_FALSE12]] ] -// CHECK1-NEXT: store i32 [[COND14]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK1-NEXT: store i32 [[TMP43]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] +// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP35]], [[TMP36]] +// CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP37]], [[TMP38]] +// CHECK1-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP39]], [[TMP40]] +// CHECK1-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] +// CHECK1: cond.true10: +// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: br label [[COND_END12:%.*]] +// CHECK1: cond.false11: +// CHECK1-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: br label [[COND_END12]] +// CHECK1: cond.end12: +// CHECK1-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP41]], [[COND_TRUE10]] ], [ [[TMP42]], [[COND_FALSE11]] ] +// CHECK1-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: store i32 [[TMP43]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -232,11 +231,11 @@ int bar(int n){ // CHECK1-NEXT: br i1 [[TMP47]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK1: .omp.final.then: // CHECK1-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP48]], 0 -// CHECK1-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV16]], 1 -// CHECK1-NEXT: [[ADD17:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD17]], ptr [[I4]], align 4 +// CHECK1-NEXT: [[SUB14:%.*]] = sub nsw i32 [[TMP48]], 0 +// CHECK1-NEXT: [[DIV15:%.*]] = sdiv i32 [[SUB14]], 1 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV15]], 1 +// CHECK1-NEXT: [[ADD16:%.*]] = add nsw i32 0, [[MUL]] +// CHECK1-NEXT: store i32 [[ADD16]], ptr [[I3]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: // CHECK1-NEXT: [[TMP49:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 @@ -249,7 +248,6 @@ int bar(int n){ // CHECK1: .omp.lastprivate.done: // CHECK1-NEXT: br label [[OMP_PRECOND_END]] // CHECK1: omp.precond.end: -// CHECK1-NEXT: call void @__kmpc_free_shared(ptr [[L1]], i64 4) // CHECK1-NEXT: ret void // // @@ -333,29 +331,29 @@ int bar(int n){ // CHECK1: omp.dispatch.body: // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]] +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK1-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK1-NEXT: store i32 [[TMP20]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK1-NEXT: store i32 [[TMP20]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK1-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK1: omp.dispatch.inc: @@ -398,7 +396,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32 -// CHECK1-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8 @@ -418,7 +416,7 @@ int bar(int n){ // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]] // CHECK1-NEXT: call void @__kmpc_target_deinit() // CHECK1-NEXT: ret void // CHECK1: worker.exit: @@ -487,63 +485,63 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]] +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 // CHECK1-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] // CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[N_ADDR]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK1-NEXT: store i32 [[TMP18]], ptr [[N_CASTED]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8, !llvm.access.group [[ACC_GRP19]] +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[N_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK1-NEXT: store i32 [[TMP18]], ptr [[N_CASTED]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8, !llvm.access.group [[ACC_GRP23]] // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK1-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP15]] to ptr -// CHECK1-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 8, !llvm.access.group [[ACC_GRP19]] +// CHECK1-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 8, !llvm.access.group [[ACC_GRP23]] // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 // CHECK1-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP17]] to ptr -// CHECK1-NEXT: store ptr [[TMP23]], ptr [[TMP22]], align 8, !llvm.access.group [[ACC_GRP19]] +// CHECK1-NEXT: store ptr [[TMP23]], ptr [[TMP22]], align 8, !llvm.access.group [[ACC_GRP23]] // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2 // CHECK1-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP19]] to ptr -// CHECK1-NEXT: store ptr [[TMP25]], ptr [[TMP24]], align 8, !llvm.access.group [[ACC_GRP19]] +// CHECK1-NEXT: store ptr [[TMP25]], ptr [[TMP24]], align 8, !llvm.access.group [[ACC_GRP23]] // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3 -// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP26]], align 8, !llvm.access.group [[ACC_GRP19]] -// CHECK1-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group [[ACC_GRP19]] -// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP28]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4), !llvm.access.group [[ACC_GRP19]] +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP26]], align 8, !llvm.access.group [[ACC_GRP23]] +// CHECK1-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group [[ACC_GRP23]] +// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP28]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4), !llvm.access.group [[ACC_GRP23]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP29]], [[TMP30]] -// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP31]], [[TMP32]] -// CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] -// CHECK1-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK1-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK1-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP35]], [[TMP36]] // CHECK1-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] // CHECK1: cond.true10: -// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK1-NEXT: br label [[COND_END12:%.*]] // CHECK1: cond.false11: -// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK1-NEXT: br label [[COND_END12]] // CHECK1: cond.end12: // CHECK1-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP37]], [[COND_TRUE10]] ], [ [[TMP38]], [[COND_FALSE11]] ] -// CHECK1-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK1-NEXT: store i32 [[TMP39]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK1-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK1-NEXT: store i32 [[TMP39]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -623,33 +621,33 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]] // CHECK1-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8, !llvm.access.group [[ACC_GRP22]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8, !llvm.access.group [[ACC_GRP26]] // CHECK1-NEXT: [[CMP6:%.*]] = icmp ule i64 [[CONV5]], [[TMP11]] // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP22]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP26]] // CHECK1-NEXT: [[CONV7:%.*]] = sext i16 [[TMP14]] to i32 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[CONV7]], 1 // CHECK1-NEXT: [[CONV9:%.*]] = trunc i32 [[ADD8]] to i16 -// CHECK1-NEXT: store i16 [[CONV9]], ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP22]] +// CHECK1-NEXT: store i16 [[CONV9]], ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP26]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK1-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -688,7 +686,7 @@ int bar(int n){ // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK1-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]] // CHECK1-NEXT: call void @__kmpc_target_deinit() // CHECK1-NEXT: ret void // CHECK1: worker.exit: @@ -736,51 +734,51 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29:![0-9]+]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 10 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP29]] // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP29]] // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK1-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP8]] to ptr -// CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8, !llvm.access.group [[ACC_GRP25]] +// CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8, !llvm.access.group [[ACC_GRP29]] // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 // CHECK1-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP10]] to ptr -// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8, !llvm.access.group [[ACC_GRP25]] +// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8, !llvm.access.group [[ACC_GRP29]] // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2 -// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP15]], align 8, !llvm.access.group [[ACC_GRP25]] -// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3), !llvm.access.group [[ACC_GRP25]] +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP15]], align 8, !llvm.access.group [[ACC_GRP29]] +// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3), !llvm.access.group [[ACC_GRP29]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP29]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP29]] // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK1-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK1-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP29]] // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP29]] // CHECK1-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP22]], 9 // CHECK1-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]] // CHECK1: cond.true5: // CHECK1-NEXT: br label [[COND_END7:%.*]] // CHECK1: cond.false6: -// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP29]] // CHECK1-NEXT: br label [[COND_END7]] // CHECK1: cond.end7: // CHECK1-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP23]], [[COND_FALSE6]] ] -// CHECK1-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK1-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK1-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK1-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -833,31 +831,31 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]] // CHECK1-NEXT: [[CONV2:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8, !llvm.access.group [[ACC_GRP28]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8, !llvm.access.group [[ACC_GRP32]] // CHECK1-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV2]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]] -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]] // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK1-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP32]] // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -893,7 +891,7 @@ int bar(int n){ // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[F_CASTED]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l42_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR3]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l42_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR2]] // CHECK1-NEXT: call void @__kmpc_target_deinit() // CHECK1-NEXT: ret void // CHECK1: worker.exit: @@ -947,57 +945,57 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31:![0-9]+]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35:![0-9]+]] // CHECK1-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], 100 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK1-NEXT: store i32 [[TMP11]], ptr [[F_CASTED]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[F_CASTED]], align 8, !llvm.access.group [[ACC_GRP31]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK1-NEXT: store i32 [[TMP11]], ptr [[F_CASTED]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[F_CASTED]], align 8, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK1-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP8]] to ptr -// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8, !llvm.access.group [[ACC_GRP31]] +// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 // CHECK1-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP10]] to ptr -// CHECK1-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 8, !llvm.access.group [[ACC_GRP31]] +// CHECK1-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 8, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2 -// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP17]], align 8, !llvm.access.group [[ACC_GRP31]] +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP17]], align 8, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3 // CHECK1-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP12]] to ptr -// CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP18]], align 8, !llvm.access.group [[ACC_GRP31]] -// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l42_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4), !llvm.access.group [[ACC_GRP31]] +// CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP18]], align 8, !llvm.access.group [[ACC_GRP35]] +// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l42_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4), !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] -// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP26]], 99 // CHECK1-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]] // CHECK1: cond.true6: // CHECK1-NEXT: br label [[COND_END8:%.*]] // CHECK1: cond.false7: -// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: br label [[COND_END8]] // CHECK1: cond.end8: // CHECK1-NEXT: [[COND9:%.*]] = phi i32 [ 99, [[COND_TRUE6]] ], [ [[TMP27]], [[COND_FALSE7]] ] -// CHECK1-NEXT: store i32 [[COND9]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK1-NEXT: store i32 [[TMP28]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] +// CHECK1-NEXT: store i32 [[COND9]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK1-NEXT: store i32 [[TMP28]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1056,49 +1054,49 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34:![0-9]+]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38:![0-9]+]] // CHECK1-NEXT: [[CONV3:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8, !llvm.access.group [[ACC_GRP34]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8, !llvm.access.group [[ACC_GRP38]] // CHECK1-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV3]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 10 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK1-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP10]], 10 // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 10 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL5]] // CHECK1-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] -// CHECK1-NEXT: store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK1-NEXT: store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK1-NEXT: store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK1-NEXT: store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK1-NEXT: [[MUL8:%.*]] = mul nsw i32 [[TMP12]], [[TMP13]] // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP11]], [[MUL8]] -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP14]] -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP16]] to i64 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM11]] -// CHECK1-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK1-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] -// CHECK1-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1141,7 +1139,7 @@ int bar(int n){ // CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[L_CASTED]], align 4 // CHECK2-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]], i32 [[TMP6]]) #[[ATTR3:[0-9]+]] +// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: call void @__kmpc_target_deinit() // CHECK2-NEXT: ret void // CHECK2: worker.exit: @@ -1159,13 +1157,13 @@ int bar(int n){ // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[I3:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[L_CASTED:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x ptr], align 4 @@ -1175,21 +1173,20 @@ int bar(int n){ // CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 // CHECK2-NEXT: store i32 [[L]], ptr [[L_ADDR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK2-NEXT: [[L1:%.*]] = call align 8 ptr @__kmpc_alloc_shared(i32 4) // CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK2-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK2-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK2-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK2-NEXT: store i32 0, ptr [[I]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK2: omp.precond.then: // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK2-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 @@ -1197,11 +1194,11 @@ int bar(int n){ // CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 // CHECK2-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 128) // CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK2-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] -// CHECK2-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK2-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK2-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK2: cond.true: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK2-NEXT: br label [[COND_END:%.*]] // CHECK2: cond.false: // CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 @@ -1213,67 +1210,67 @@ int bar(int n){ // CHECK2-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK2-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] -// CHECK2-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK2-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] +// CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[N_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: store i32 [[TMP16]], ptr [[N_CASTED]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[N_CASTED]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: store i32 [[TMP18]], ptr [[L_CASTED]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[L_CASTED]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[N_ADDR]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: store i32 [[TMP16]], ptr [[N_CASTED]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[N_CASTED]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: store i32 [[TMP18]], ptr [[L_CASTED]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[L_CASTED]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 // CHECK2-NEXT: [[TMP21:%.*]] = inttoptr i32 [[TMP14]] to ptr -// CHECK2-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK2-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 // CHECK2-NEXT: [[TMP23:%.*]] = inttoptr i32 [[TMP15]] to ptr -// CHECK2-NEXT: store ptr [[TMP23]], ptr [[TMP22]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK2-NEXT: store ptr [[TMP23]], ptr [[TMP22]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 // CHECK2-NEXT: [[TMP25:%.*]] = inttoptr i32 [[TMP17]] to ptr -// CHECK2-NEXT: store ptr [[TMP25]], ptr [[TMP24]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK2-NEXT: store ptr [[TMP25]], ptr [[TMP24]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3 -// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP26]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP26]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 4 // CHECK2-NEXT: [[TMP28:%.*]] = inttoptr i32 [[TMP19]] to ptr -// CHECK2-NEXT: store ptr [[TMP28]], ptr [[TMP27]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP30]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 5), !llvm.access.group [[ACC_GRP12]] +// CHECK2-NEXT: store ptr [[TMP28]], ptr [[TMP27]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP30]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 5), !llvm.access.group [[ACC_GRP16]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP31]], [[TMP32]] -// CHECK2-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] -// CHECK2-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP35]], [[TMP36]] -// CHECK2-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP37]], [[TMP38]] -// CHECK2-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] -// CHECK2: cond.true11: -// CHECK2-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: br label [[COND_END13:%.*]] -// CHECK2: cond.false12: -// CHECK2-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: br label [[COND_END13]] -// CHECK2: cond.end13: -// CHECK2-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP39]], [[COND_TRUE11]] ], [ [[TMP40]], [[COND_FALSE12]] ] -// CHECK2-NEXT: store i32 [[COND14]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: store i32 [[TMP41]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP31]], [[TMP32]] +// CHECK2-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] +// CHECK2-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP35]], [[TMP36]] +// CHECK2-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP37]], [[TMP38]] +// CHECK2-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] +// CHECK2: cond.true10: +// CHECK2-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: br label [[COND_END12:%.*]] +// CHECK2: cond.false11: +// CHECK2-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: br label [[COND_END12]] +// CHECK2: cond.end12: +// CHECK2-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP39]], [[COND_TRUE10]] ], [ [[TMP40]], [[COND_FALSE11]] ] +// CHECK2-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: store i32 [[TMP41]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1285,11 +1282,11 @@ int bar(int n){ // CHECK2-NEXT: br i1 [[TMP45]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK2: .omp.final.then: // CHECK2-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP46]], 0 -// CHECK2-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 -// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV16]], 1 -// CHECK2-NEXT: [[ADD17:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD17]], ptr [[I4]], align 4 +// CHECK2-NEXT: [[SUB14:%.*]] = sub nsw i32 [[TMP46]], 0 +// CHECK2-NEXT: [[DIV15:%.*]] = sdiv i32 [[SUB14]], 1 +// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV15]], 1 +// CHECK2-NEXT: [[ADD16:%.*]] = add nsw i32 0, [[MUL]] +// CHECK2-NEXT: store i32 [[ADD16]], ptr [[I3]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: // CHECK2-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 @@ -1302,7 +1299,6 @@ int bar(int n){ // CHECK2: .omp.lastprivate.done: // CHECK2-NEXT: br label [[OMP_PRECOND_END]] // CHECK2: omp.precond.end: -// CHECK2-NEXT: call void @__kmpc_free_shared(ptr [[L1]], i32 4) // CHECK2-NEXT: ret void // // @@ -1382,28 +1378,28 @@ int bar(int n){ // CHECK2: omp.dispatch.body: // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]] +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK2-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK2-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP19]] -// CHECK2-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK2-NEXT: store i32 [[TMP20]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK2-NEXT: store i32 [[TMP20]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK2-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK2: omp.dispatch.inc: @@ -1446,7 +1442,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32 -// CHECK2-SAME: (i32 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK2-SAME: (i32 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4 @@ -1466,7 +1462,7 @@ int bar(int n){ // CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK2-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]] // CHECK2-NEXT: call void @__kmpc_target_deinit() // CHECK2-NEXT: ret void // CHECK2: worker.exit: @@ -1535,61 +1531,61 @@ int bar(int n){ // CHECK2-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]] +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 // CHECK2-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] // CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[N_ADDR]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK2-NEXT: store i32 [[TMP16]], ptr [[N_CASTED]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[N_CASTED]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[N_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK2-NEXT: store i32 [[TMP16]], ptr [[N_CASTED]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[N_CASTED]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 // CHECK2-NEXT: [[TMP19:%.*]] = inttoptr i32 [[TMP14]] to ptr -// CHECK2-NEXT: store ptr [[TMP19]], ptr [[TMP18]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK2-NEXT: store ptr [[TMP19]], ptr [[TMP18]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 // CHECK2-NEXT: [[TMP21:%.*]] = inttoptr i32 [[TMP15]] to ptr -// CHECK2-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK2-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 // CHECK2-NEXT: [[TMP23:%.*]] = inttoptr i32 [[TMP17]] to ptr -// CHECK2-NEXT: store ptr [[TMP23]], ptr [[TMP22]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK2-NEXT: store ptr [[TMP23]], ptr [[TMP22]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3 -// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP24]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK2-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP26]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 4), !llvm.access.group [[ACC_GRP19]] +// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP24]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK2-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP26]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 4), !llvm.access.group [[ACC_GRP23]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] -// CHECK2-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK2-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP29]], [[TMP30]] -// CHECK2-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK2-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP31]], [[TMP32]] -// CHECK2-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK2-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK2-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP33]], [[TMP34]] // CHECK2-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] // CHECK2: cond.true10: -// CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK2-NEXT: br label [[COND_END12:%.*]] // CHECK2: cond.false11: -// CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK2-NEXT: br label [[COND_END12]] // CHECK2: cond.end12: // CHECK2-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP35]], [[COND_TRUE10]] ], [ [[TMP36]], [[COND_FALSE11]] ] -// CHECK2-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK2-NEXT: store i32 [[TMP37]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK2-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK2-NEXT: store i32 [[TMP37]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1667,31 +1663,31 @@ int bar(int n){ // CHECK2-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]] -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]] +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK2-NEXT: [[CMP4:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]] // CHECK2-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK2-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i32 0, i32 [[TMP13]] -// CHECK2-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP22]] +// CHECK2-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP26]] // CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV]], 1 // CHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 -// CHECK2-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP22]] +// CHECK2-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP26]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK2-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1730,7 +1726,7 @@ int bar(int n){ // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK2-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]] // CHECK2-NEXT: call void @__kmpc_target_deinit() // CHECK2-NEXT: ret void // CHECK2: worker.exit: @@ -1778,49 +1774,49 @@ int bar(int n){ // CHECK2-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]] +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29:![0-9]+]] // CHECK2-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 10 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP29]] // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 // CHECK2-NEXT: [[TMP10:%.*]] = inttoptr i32 [[TMP7]] to ptr -// CHECK2-NEXT: store ptr [[TMP10]], ptr [[TMP9]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK2-NEXT: store ptr [[TMP10]], ptr [[TMP9]], align 4, !llvm.access.group [[ACC_GRP29]] // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 // CHECK2-NEXT: [[TMP12:%.*]] = inttoptr i32 [[TMP8]] to ptr -// CHECK2-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK2-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 4, !llvm.access.group [[ACC_GRP29]] // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 -// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP13]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3), !llvm.access.group [[ACC_GRP25]] +// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP13]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3), !llvm.access.group [[ACC_GRP29]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP29]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK2-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK2-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP29]] // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK2-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK2-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP29]] // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK2-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK2-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP29]] // CHECK2-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9 // CHECK2-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]] // CHECK2: cond.true5: // CHECK2-NEXT: br label [[COND_END7:%.*]] // CHECK2: cond.false6: -// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP29]] // CHECK2-NEXT: br label [[COND_END7]] // CHECK2: cond.end7: // CHECK2-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ] -// CHECK2-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK2-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK2-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK2-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1871,29 +1867,29 @@ int bar(int n){ // CHECK2-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]] -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]] +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] // CHECK2-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP6]], [[TMP7]] // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]] -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP9]] -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]] // CHECK2-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK2-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP32]] // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1929,7 +1925,7 @@ int bar(int n){ // CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[F_CASTED]], align 4 // CHECK2-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l42_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i32 [[TMP4]]) #[[ATTR3]] +// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l42_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i32 [[TMP4]]) #[[ATTR2]] // CHECK2-NEXT: call void @__kmpc_target_deinit() // CHECK2-NEXT: ret void // CHECK2: worker.exit: @@ -1983,55 +1979,55 @@ int bar(int n){ // CHECK2-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31:![0-9]+]] +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35:![0-9]+]] // CHECK2-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], 100 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK2-NEXT: store i32 [[TMP9]], ptr [[F_CASTED]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[F_CASTED]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK2-NEXT: store i32 [[TMP9]], ptr [[F_CASTED]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[F_CASTED]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 // CHECK2-NEXT: [[TMP12:%.*]] = inttoptr i32 [[TMP7]] to ptr -// CHECK2-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK2-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 // CHECK2-NEXT: [[TMP14:%.*]] = inttoptr i32 [[TMP8]] to ptr -// CHECK2-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK2-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 -// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP15]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP15]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3 // CHECK2-NEXT: [[TMP17:%.*]] = inttoptr i32 [[TMP10]] to ptr -// CHECK2-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l42_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 4), !llvm.access.group [[ACC_GRP31]] +// CHECK2-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l42_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 4), !llvm.access.group [[ACC_GRP35]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK2-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK2-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK2-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK2-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK2-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK2-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK2-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP24]], 99 // CHECK2-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]] // CHECK2: cond.true6: // CHECK2-NEXT: br label [[COND_END8:%.*]] // CHECK2: cond.false7: -// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK2-NEXT: br label [[COND_END8]] // CHECK2: cond.end8: // CHECK2-NEXT: [[COND9:%.*]] = phi i32 [ 99, [[COND_TRUE6]] ], [ [[TMP25]], [[COND_FALSE7]] ] -// CHECK2-NEXT: store i32 [[COND9]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK2-NEXT: store i32 [[TMP26]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] +// CHECK2-NEXT: store i32 [[COND9]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK2-NEXT: store i32 [[TMP26]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -2088,46 +2084,46 @@ int bar(int n){ // CHECK2-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34:![0-9]+]] -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38:![0-9]+]] +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK2-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP6]], [[TMP7]] // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 10 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK2-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP10]], 10 // CHECK2-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 10 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL3]] // CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]] -// CHECK2-NEXT: store i32 [[ADD5]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK2-NEXT: store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK2-NEXT: store i32 [[ADD5]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK2-NEXT: store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK2-NEXT: [[MUL6:%.*]] = mul nsw i32 [[TMP12]], [[TMP13]] // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], [[MUL6]] -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[ADD7]], [[TMP14]] -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP15]] -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP16]] -// CHECK2-NEXT: store i32 [[ADD8]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK2-NEXT: store i32 [[ADD8]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] -// CHECK2-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: diff --git a/clang/test/OpenMP/nvptx_target_teams_distribute_simd_codegen.cpp b/clang/test/OpenMP/nvptx_target_teams_distribute_simd_codegen.cpp index 20fe58ce10082..be814ed13349c 100644 --- a/clang/test/OpenMP/nvptx_target_teams_distribute_simd_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_teams_distribute_simd_codegen.cpp @@ -94,7 +94,7 @@ int bar(int n){ // CHECK45-64-NEXT: [[TMP6:%.*]] = load i64, ptr [[L_CASTED]], align 8 // CHECK45-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK45-64-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK45-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], i64 [[TMP6]]) #[[ATTR3:[0-9]+]] +// CHECK45-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]] // CHECK45-64-NEXT: call void @__kmpc_target_deinit() // CHECK45-64-NEXT: ret void // CHECK45-64: worker.exit: @@ -112,34 +112,33 @@ int bar(int n){ // CHECK45-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK45-64-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK45-64-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK45-64-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK45-64-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK45-64-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK45-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK45-64-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK45-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK45-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK45-64-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK45-64-NEXT: [[I3:%.*]] = alloca i32, align 4 // CHECK45-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK45-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK45-64-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 // CHECK45-64-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK45-64-NEXT: store i64 [[L]], ptr [[L_ADDR]], align 8 // CHECK45-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK45-64-NEXT: [[L1:%.*]] = call align 8 ptr @__kmpc_alloc_shared(i64 4) // CHECK45-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK45-64-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK45-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK45-64-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK45-64-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK45-64-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK45-64-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK45-64-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK45-64-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK45-64-NEXT: store i32 0, ptr [[I]], align 4 // CHECK45-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK45-64-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] // CHECK45-64-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK45-64: omp.precond.then: // CHECK45-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK45-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK45-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK45-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 // CHECK45-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK45-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 @@ -149,11 +148,11 @@ int bar(int n){ // CHECK45-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK45-64: omp.dispatch.cond: // CHECK45-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK45-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK45-64-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] -// CHECK45-64-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK45-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK45-64-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK45-64-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK45-64: cond.true: -// CHECK45-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK45-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK45-64-NEXT: br label [[COND_END:%.*]] // CHECK45-64: cond.false: // CHECK45-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 @@ -165,45 +164,45 @@ int bar(int n){ // CHECK45-64-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4 // CHECK45-64-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK45-64-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK45-64-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK45-64-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK45-64-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK45-64-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] // CHECK45-64: omp.dispatch.body: // CHECK45-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK45-64: omp.inner.for.cond: -// CHECK45-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] -// CHECK45-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK45-64-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK45-64-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK45-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] +// CHECK45-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-64-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK45-64-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK45-64: omp.inner.for.body: -// CHECK45-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK45-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK45-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK45-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK45-64-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK45-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK45-64-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK45-64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK45-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK45-64-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK45-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK45-64-NEXT: store i32 [[TMP18]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK45-64-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-64-NEXT: store i32 [[TMP18]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK45-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK45-64: omp.body.continue: // CHECK45-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK45-64: omp.inner.for.inc: -// CHECK45-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK45-64-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK45-64-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK45-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK45-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-64-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK45-64-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK45-64: omp.inner.for.end: // CHECK45-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK45-64: omp.dispatch.inc: // CHECK45-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK45-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK45-64-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK45-64-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_LB]], align 4 +// CHECK45-64-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK45-64-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_LB]], align 4 // CHECK45-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK45-64-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK45-64-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK45-64-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_UB]], align 4 +// CHECK45-64-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK45-64-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_UB]], align 4 // CHECK45-64-NEXT: br label [[OMP_DISPATCH_COND]] // CHECK45-64: omp.dispatch.end: // CHECK45-64-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -214,11 +213,11 @@ int bar(int n){ // CHECK45-64-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK45-64: .omp.final.then: // CHECK45-64-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK45-64-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK45-64-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 -// CHECK45-64-NEXT: [[MUL13:%.*]] = mul nsw i32 [[DIV12]], 1 -// CHECK45-64-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] -// CHECK45-64-NEXT: store i32 [[ADD14]], ptr [[I4]], align 4 +// CHECK45-64-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK45-64-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1 +// CHECK45-64-NEXT: [[MUL12:%.*]] = mul nsw i32 [[DIV11]], 1 +// CHECK45-64-NEXT: [[ADD13:%.*]] = add nsw i32 0, [[MUL12]] +// CHECK45-64-NEXT: store i32 [[ADD13]], ptr [[I3]], align 4 // CHECK45-64-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK45-64: .omp.final.done: // CHECK45-64-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 @@ -231,12 +230,11 @@ int bar(int n){ // CHECK45-64: .omp.lastprivate.done: // CHECK45-64-NEXT: br label [[OMP_PRECOND_END]] // CHECK45-64: omp.precond.end: -// CHECK45-64-NEXT: call void @__kmpc_free_shared(ptr [[L1]], i64 4) // CHECK45-64-NEXT: ret void // // // CHECK45-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40 -// CHECK45-64-SAME: (i64 [[N:%.*]], ptr nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK45-64-SAME: (i64 [[N:%.*]], ptr nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK45-64-NEXT: entry: // CHECK45-64-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK45-64-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8 @@ -256,7 +254,7 @@ int bar(int n){ // CHECK45-64-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK45-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK45-64-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK45-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK45-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]] // CHECK45-64-NEXT: call void @__kmpc_target_deinit() // CHECK45-64-NEXT: ret void // CHECK45-64: worker.exit: @@ -330,31 +328,31 @@ int bar(int n){ // CHECK45-64: omp.dispatch.body: // CHECK45-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK45-64: omp.inner.for.cond: -// CHECK45-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] -// CHECK45-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]] +// CHECK45-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK45-64-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK45-64-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK45-64: omp.inner.for.body: -// CHECK45-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK45-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK45-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK45-64-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK45-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-64-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK45-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK45-64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK45-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK45-64-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP16]] +// CHECK45-64-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP20]] // CHECK45-64-NEXT: [[CONV:%.*]] = sext i16 [[TMP18]] to i32 // CHECK45-64-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV]], 1 // CHECK45-64-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK45-64-NEXT: store i16 [[CONV8]], ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP16]] +// CHECK45-64-NEXT: store i16 [[CONV8]], ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP20]] // CHECK45-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK45-64: omp.body.continue: // CHECK45-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK45-64: omp.inner.for.inc: -// CHECK45-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK45-64-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK45-64-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK45-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK45-64-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK45-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK45-64: omp.inner.for.end: // CHECK45-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK45-64: omp.dispatch.inc: @@ -403,7 +401,7 @@ int bar(int n){ // CHECK45-64-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK45-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK45-64-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK45-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK45-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]] // CHECK45-64-NEXT: call void @__kmpc_target_deinit() // CHECK45-64-NEXT: ret void // CHECK45-64: worker.exit: @@ -457,29 +455,29 @@ int bar(int n){ // CHECK45-64: omp.dispatch.body: // CHECK45-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK45-64: omp.inner.for.cond: -// CHECK45-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] -// CHECK45-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK45-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]] +// CHECK45-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK45-64-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK45-64-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK45-64: omp.inner.for.body: -// CHECK45-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK45-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK45-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK45-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK45-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK45-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK45-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK45-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK45-64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK45-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK45-64-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK45-64-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK45-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK45-64-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK45-64-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK45-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK45-64: omp.body.continue: // CHECK45-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK45-64: omp.inner.for.inc: -// CHECK45-64-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK45-64-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK45-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK45-64-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK45-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK45-64-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK45-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] // CHECK45-64: omp.inner.for.end: // CHECK45-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK45-64: omp.dispatch.inc: @@ -525,7 +523,7 @@ int bar(int n){ // CHECK45-64-NEXT: [[TMP4:%.*]] = load i64, ptr [[F_CASTED]], align 8 // CHECK45-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK45-64-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK45-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR3]] +// CHECK45-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR2]] // CHECK45-64-NEXT: call void @__kmpc_target_deinit() // CHECK45-64-NEXT: ret void // CHECK45-64: worker.exit: @@ -584,47 +582,47 @@ int bar(int n){ // CHECK45-64: omp.dispatch.body: // CHECK45-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK45-64: omp.inner.for.cond: -// CHECK45-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]] -// CHECK45-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]] +// CHECK45-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-64-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK45-64-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK45-64: omp.inner.for.body: -// CHECK45-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-64-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 10 // CHECK45-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK45-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK45-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-64-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK45-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK45-64-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-64-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 10 // CHECK45-64-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 10 // CHECK45-64-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] // CHECK45-64-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK45-64-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] -// CHECK45-64-NEXT: store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-64-NEXT: store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-64-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-64-NEXT: store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK45-64-NEXT: store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK45-64-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK45-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK45-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-64-NEXT: [[MUL8:%.*]] = mul nsw i32 [[TMP14]], [[TMP15]] // CHECK45-64-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], [[MUL8]] -// CHECK45-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-64-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP16]] -// CHECK45-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK45-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK45-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-64-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP18]] to i64 // CHECK45-64-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM11]] -// CHECK45-64-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-64-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK45-64: omp.body.continue: // CHECK45-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK45-64: omp.inner.for.inc: -// CHECK45-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-64-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK45-64-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK45-64-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK45-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK45-64: omp.inner.for.end: // CHECK45-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK45-64: omp.dispatch.inc: @@ -677,7 +675,7 @@ int bar(int n){ // CHECK45-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[L_CASTED]], align 4 // CHECK45-32-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK45-32-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK45-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]], i32 [[TMP6]]) #[[ATTR3:[0-9]+]] +// CHECK45-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]] // CHECK45-32-NEXT: call void @__kmpc_target_deinit() // CHECK45-32-NEXT: ret void // CHECK45-32: worker.exit: @@ -695,34 +693,33 @@ int bar(int n){ // CHECK45-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK45-32-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK45-32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK45-32-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK45-32-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK45-32-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK45-32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK45-32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK45-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK45-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK45-32-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK45-32-NEXT: [[I3:%.*]] = alloca i32, align 4 // CHECK45-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK45-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 // CHECK45-32-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK45-32-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 // CHECK45-32-NEXT: store i32 [[L]], ptr [[L_ADDR]], align 4 // CHECK45-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK45-32-NEXT: [[L1:%.*]] = call align 8 ptr @__kmpc_alloc_shared(i32 4) // CHECK45-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK45-32-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK45-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK45-32-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK45-32-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK45-32-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK45-32-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK45-32-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK45-32-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK45-32-NEXT: store i32 0, ptr [[I]], align 4 // CHECK45-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK45-32-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] // CHECK45-32-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK45-32: omp.precond.then: // CHECK45-32-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK45-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK45-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK45-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 // CHECK45-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK45-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 @@ -732,11 +729,11 @@ int bar(int n){ // CHECK45-32-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK45-32: omp.dispatch.cond: // CHECK45-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK45-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK45-32-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] -// CHECK45-32-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK45-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK45-32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK45-32-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK45-32: cond.true: -// CHECK45-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK45-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK45-32-NEXT: br label [[COND_END:%.*]] // CHECK45-32: cond.false: // CHECK45-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 @@ -748,44 +745,44 @@ int bar(int n){ // CHECK45-32-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4 // CHECK45-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK45-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK45-32-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK45-32-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK45-32-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK45-32-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] // CHECK45-32: omp.dispatch.body: // CHECK45-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK45-32: omp.inner.for.cond: -// CHECK45-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] -// CHECK45-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK45-32-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK45-32-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK45-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] +// CHECK45-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-32-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK45-32-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK45-32: omp.inner.for.body: -// CHECK45-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK45-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK45-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK45-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK45-32-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK45-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK45-32-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK45-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP17]] -// CHECK45-32-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK45-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK45-32-NEXT: store i32 [[TMP18]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK45-32-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-32-NEXT: store i32 [[TMP18]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK45-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK45-32: omp.body.continue: // CHECK45-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK45-32: omp.inner.for.inc: -// CHECK45-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK45-32-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK45-32-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK45-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK45-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-32-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK45-32-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK45-32: omp.inner.for.end: // CHECK45-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK45-32: omp.dispatch.inc: // CHECK45-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK45-32-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK45-32-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK45-32-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_LB]], align 4 +// CHECK45-32-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK45-32-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_LB]], align 4 // CHECK45-32-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK45-32-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK45-32-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK45-32-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_UB]], align 4 +// CHECK45-32-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK45-32-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_UB]], align 4 // CHECK45-32-NEXT: br label [[OMP_DISPATCH_COND]] // CHECK45-32: omp.dispatch.end: // CHECK45-32-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -796,11 +793,11 @@ int bar(int n){ // CHECK45-32-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK45-32: .omp.final.then: // CHECK45-32-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK45-32-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK45-32-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 -// CHECK45-32-NEXT: [[MUL13:%.*]] = mul nsw i32 [[DIV12]], 1 -// CHECK45-32-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] -// CHECK45-32-NEXT: store i32 [[ADD14]], ptr [[I4]], align 4 +// CHECK45-32-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK45-32-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1 +// CHECK45-32-NEXT: [[MUL12:%.*]] = mul nsw i32 [[DIV11]], 1 +// CHECK45-32-NEXT: [[ADD13:%.*]] = add nsw i32 0, [[MUL12]] +// CHECK45-32-NEXT: store i32 [[ADD13]], ptr [[I3]], align 4 // CHECK45-32-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK45-32: .omp.final.done: // CHECK45-32-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 @@ -813,12 +810,11 @@ int bar(int n){ // CHECK45-32: .omp.lastprivate.done: // CHECK45-32-NEXT: br label [[OMP_PRECOND_END]] // CHECK45-32: omp.precond.end: -// CHECK45-32-NEXT: call void @__kmpc_free_shared(ptr [[L1]], i32 4) // CHECK45-32-NEXT: ret void // // // CHECK45-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40 -// CHECK45-32-SAME: (i32 [[N:%.*]], ptr nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK45-32-SAME: (i32 [[N:%.*]], ptr nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK45-32-NEXT: entry: // CHECK45-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK45-32-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4 @@ -838,7 +834,7 @@ int bar(int n){ // CHECK45-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK45-32-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK45-32-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK45-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK45-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]] // CHECK45-32-NEXT: call void @__kmpc_target_deinit() // CHECK45-32-NEXT: ret void // CHECK45-32: worker.exit: @@ -912,30 +908,30 @@ int bar(int n){ // CHECK45-32: omp.dispatch.body: // CHECK45-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK45-32: omp.inner.for.cond: -// CHECK45-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] -// CHECK45-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]] +// CHECK45-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK45-32-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK45-32-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK45-32: omp.inner.for.body: -// CHECK45-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK45-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK45-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK45-32-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK45-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-32-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK45-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK45-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i32 0, i32 [[TMP17]] -// CHECK45-32-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP16]] +// CHECK45-32-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP20]] // CHECK45-32-NEXT: [[CONV:%.*]] = sext i16 [[TMP18]] to i32 // CHECK45-32-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV]], 1 // CHECK45-32-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK45-32-NEXT: store i16 [[CONV8]], ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP16]] +// CHECK45-32-NEXT: store i16 [[CONV8]], ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP20]] // CHECK45-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK45-32: omp.body.continue: // CHECK45-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK45-32: omp.inner.for.inc: -// CHECK45-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK45-32-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK45-32-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK45-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK45-32-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK45-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK45-32: omp.inner.for.end: // CHECK45-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK45-32: omp.dispatch.inc: @@ -984,7 +980,7 @@ int bar(int n){ // CHECK45-32-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK45-32-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK45-32-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK45-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK45-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]] // CHECK45-32-NEXT: call void @__kmpc_target_deinit() // CHECK45-32-NEXT: ret void // CHECK45-32: worker.exit: @@ -1038,28 +1034,28 @@ int bar(int n){ // CHECK45-32: omp.dispatch.body: // CHECK45-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK45-32: omp.inner.for.cond: -// CHECK45-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] -// CHECK45-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK45-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]] +// CHECK45-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK45-32-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK45-32-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK45-32: omp.inner.for.body: -// CHECK45-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK45-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK45-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK45-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK45-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK45-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK45-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK45-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK45-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK45-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK45-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK45-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK45-32-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK45-32-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK45-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK45-32: omp.body.continue: // CHECK45-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK45-32: omp.inner.for.inc: -// CHECK45-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK45-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK45-32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK45-32-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK45-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK45-32-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK45-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] // CHECK45-32: omp.inner.for.end: // CHECK45-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK45-32: omp.dispatch.inc: @@ -1105,7 +1101,7 @@ int bar(int n){ // CHECK45-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[F_CASTED]], align 4 // CHECK45-32-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK45-32-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK45-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i32 [[TMP4]]) #[[ATTR3]] +// CHECK45-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i32 [[TMP4]]) #[[ATTR2]] // CHECK45-32-NEXT: call void @__kmpc_target_deinit() // CHECK45-32-NEXT: ret void // CHECK45-32: worker.exit: @@ -1164,45 +1160,45 @@ int bar(int n){ // CHECK45-32: omp.dispatch.body: // CHECK45-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK45-32: omp.inner.for.cond: -// CHECK45-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]] -// CHECK45-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]] +// CHECK45-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-32-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK45-32-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK45-32: omp.inner.for.body: -// CHECK45-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-32-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 10 // CHECK45-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK45-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK45-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK45-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK45-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-32-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 10 // CHECK45-32-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 10 // CHECK45-32-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] // CHECK45-32-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK45-32-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] -// CHECK45-32-NEXT: store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-32-NEXT: store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-32-NEXT: store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK45-32-NEXT: store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK45-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK45-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK45-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-32-NEXT: [[MUL8:%.*]] = mul nsw i32 [[TMP14]], [[TMP15]] // CHECK45-32-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], [[MUL8]] -// CHECK45-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-32-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP16]] -// CHECK45-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP17]] -// CHECK45-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-32-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP18]] -// CHECK45-32-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX11]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-32-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX11]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK45-32: omp.body.continue: // CHECK45-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK45-32: omp.inner.for.inc: -// CHECK45-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-32-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK45-32-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK45-32-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK45-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK45-32: omp.inner.for.end: // CHECK45-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK45-32: omp.dispatch.inc: @@ -1255,7 +1251,7 @@ int bar(int n){ // CHECK45-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[L_CASTED]], align 4 // CHECK45-32-EX-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK45-32-EX-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK45-32-EX-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]], i32 [[TMP6]]) #[[ATTR3:[0-9]+]] +// CHECK45-32-EX-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]] // CHECK45-32-EX-NEXT: call void @__kmpc_target_deinit() // CHECK45-32-EX-NEXT: ret void // CHECK45-32-EX: worker.exit: @@ -1273,34 +1269,33 @@ int bar(int n){ // CHECK45-32-EX-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK45-32-EX-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK45-32-EX-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK45-32-EX-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK45-32-EX-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK45-32-EX-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK45-32-EX-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK45-32-EX-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK45-32-EX-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK45-32-EX-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK45-32-EX-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK45-32-EX-NEXT: [[I3:%.*]] = alloca i32, align 4 // CHECK45-32-EX-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK45-32-EX-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 // CHECK45-32-EX-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK45-32-EX-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 // CHECK45-32-EX-NEXT: store i32 [[L]], ptr [[L_ADDR]], align 4 // CHECK45-32-EX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK45-32-EX-NEXT: [[L1:%.*]] = call align 8 ptr @__kmpc_alloc_shared(i32 4) // CHECK45-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK45-32-EX-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK45-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK45-32-EX-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK45-32-EX-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK45-32-EX-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK45-32-EX-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK45-32-EX-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK45-32-EX-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK45-32-EX-NEXT: store i32 0, ptr [[I]], align 4 // CHECK45-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK45-32-EX-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] // CHECK45-32-EX-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK45-32-EX: omp.precond.then: // CHECK45-32-EX-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK45-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK45-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK45-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 // CHECK45-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK45-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 @@ -1310,11 +1305,11 @@ int bar(int n){ // CHECK45-32-EX-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK45-32-EX: omp.dispatch.cond: // CHECK45-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK45-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK45-32-EX-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] -// CHECK45-32-EX-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK45-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK45-32-EX-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK45-32-EX-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK45-32-EX: cond.true: -// CHECK45-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK45-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK45-32-EX-NEXT: br label [[COND_END:%.*]] // CHECK45-32-EX: cond.false: // CHECK45-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 @@ -1326,44 +1321,44 @@ int bar(int n){ // CHECK45-32-EX-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4 // CHECK45-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK45-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK45-32-EX-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK45-32-EX-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK45-32-EX-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK45-32-EX-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] // CHECK45-32-EX: omp.dispatch.body: // CHECK45-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK45-32-EX: omp.inner.for.cond: -// CHECK45-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] -// CHECK45-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK45-32-EX-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK45-32-EX-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK45-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] +// CHECK45-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-32-EX-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK45-32-EX-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK45-32-EX: omp.inner.for.body: -// CHECK45-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK45-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK45-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK45-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK45-32-EX-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK45-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK45-32-EX-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK45-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP17]] -// CHECK45-32-EX-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK45-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK45-32-EX-NEXT: store i32 [[TMP18]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK45-32-EX-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-32-EX-NEXT: store i32 [[TMP18]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK45-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK45-32-EX: omp.body.continue: // CHECK45-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK45-32-EX: omp.inner.for.inc: -// CHECK45-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK45-32-EX-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK45-32-EX-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK45-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK45-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-32-EX-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK45-32-EX-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK45-32-EX: omp.inner.for.end: // CHECK45-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK45-32-EX: omp.dispatch.inc: // CHECK45-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK45-32-EX-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK45-32-EX-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK45-32-EX-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_LB]], align 4 +// CHECK45-32-EX-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK45-32-EX-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_LB]], align 4 // CHECK45-32-EX-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK45-32-EX-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK45-32-EX-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK45-32-EX-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_UB]], align 4 +// CHECK45-32-EX-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK45-32-EX-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_UB]], align 4 // CHECK45-32-EX-NEXT: br label [[OMP_DISPATCH_COND]] // CHECK45-32-EX: omp.dispatch.end: // CHECK45-32-EX-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1374,11 +1369,11 @@ int bar(int n){ // CHECK45-32-EX-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK45-32-EX: .omp.final.then: // CHECK45-32-EX-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK45-32-EX-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK45-32-EX-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 -// CHECK45-32-EX-NEXT: [[MUL13:%.*]] = mul nsw i32 [[DIV12]], 1 -// CHECK45-32-EX-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] -// CHECK45-32-EX-NEXT: store i32 [[ADD14]], ptr [[I4]], align 4 +// CHECK45-32-EX-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK45-32-EX-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1 +// CHECK45-32-EX-NEXT: [[MUL12:%.*]] = mul nsw i32 [[DIV11]], 1 +// CHECK45-32-EX-NEXT: [[ADD13:%.*]] = add nsw i32 0, [[MUL12]] +// CHECK45-32-EX-NEXT: store i32 [[ADD13]], ptr [[I3]], align 4 // CHECK45-32-EX-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK45-32-EX: .omp.final.done: // CHECK45-32-EX-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 @@ -1391,12 +1386,11 @@ int bar(int n){ // CHECK45-32-EX: .omp.lastprivate.done: // CHECK45-32-EX-NEXT: br label [[OMP_PRECOND_END]] // CHECK45-32-EX: omp.precond.end: -// CHECK45-32-EX-NEXT: call void @__kmpc_free_shared(ptr [[L1]], i32 4) // CHECK45-32-EX-NEXT: ret void // // // CHECK45-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40 -// CHECK45-32-EX-SAME: (i32 [[N:%.*]], ptr nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK45-32-EX-SAME: (i32 [[N:%.*]], ptr nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK45-32-EX-NEXT: entry: // CHECK45-32-EX-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK45-32-EX-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4 @@ -1416,7 +1410,7 @@ int bar(int n){ // CHECK45-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK45-32-EX-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK45-32-EX-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK45-32-EX-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK45-32-EX-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]] // CHECK45-32-EX-NEXT: call void @__kmpc_target_deinit() // CHECK45-32-EX-NEXT: ret void // CHECK45-32-EX: worker.exit: @@ -1490,30 +1484,30 @@ int bar(int n){ // CHECK45-32-EX: omp.dispatch.body: // CHECK45-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK45-32-EX: omp.inner.for.cond: -// CHECK45-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] -// CHECK45-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]] +// CHECK45-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK45-32-EX-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK45-32-EX-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK45-32-EX: omp.inner.for.body: -// CHECK45-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK45-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK45-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK45-32-EX-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK45-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-32-EX-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK45-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK45-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i32 0, i32 [[TMP17]] -// CHECK45-32-EX-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP16]] +// CHECK45-32-EX-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP20]] // CHECK45-32-EX-NEXT: [[CONV:%.*]] = sext i16 [[TMP18]] to i32 // CHECK45-32-EX-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV]], 1 // CHECK45-32-EX-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK45-32-EX-NEXT: store i16 [[CONV8]], ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP16]] +// CHECK45-32-EX-NEXT: store i16 [[CONV8]], ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP20]] // CHECK45-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK45-32-EX: omp.body.continue: // CHECK45-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK45-32-EX: omp.inner.for.inc: -// CHECK45-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK45-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK45-32-EX-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK45-32-EX-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK45-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK45-32-EX-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK45-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK45-32-EX: omp.inner.for.end: // CHECK45-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK45-32-EX: omp.dispatch.inc: @@ -1562,7 +1556,7 @@ int bar(int n){ // CHECK45-32-EX-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK45-32-EX-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK45-32-EX-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK45-32-EX-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK45-32-EX-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]] // CHECK45-32-EX-NEXT: call void @__kmpc_target_deinit() // CHECK45-32-EX-NEXT: ret void // CHECK45-32-EX: worker.exit: @@ -1616,28 +1610,28 @@ int bar(int n){ // CHECK45-32-EX: omp.dispatch.body: // CHECK45-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK45-32-EX: omp.inner.for.cond: -// CHECK45-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] -// CHECK45-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK45-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]] +// CHECK45-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK45-32-EX-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK45-32-EX-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK45-32-EX: omp.inner.for.body: -// CHECK45-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK45-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK45-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK45-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK45-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK45-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK45-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK45-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK45-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK45-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK45-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK45-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK45-32-EX-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK45-32-EX-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK45-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK45-32-EX: omp.body.continue: // CHECK45-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK45-32-EX: omp.inner.for.inc: -// CHECK45-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK45-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK45-32-EX-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK45-32-EX-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK45-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK45-32-EX-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK45-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] // CHECK45-32-EX: omp.inner.for.end: // CHECK45-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK45-32-EX: omp.dispatch.inc: @@ -1683,7 +1677,7 @@ int bar(int n){ // CHECK45-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[F_CASTED]], align 4 // CHECK45-32-EX-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK45-32-EX-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK45-32-EX-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i32 [[TMP4]]) #[[ATTR3]] +// CHECK45-32-EX-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i32 [[TMP4]]) #[[ATTR2]] // CHECK45-32-EX-NEXT: call void @__kmpc_target_deinit() // CHECK45-32-EX-NEXT: ret void // CHECK45-32-EX: worker.exit: @@ -1742,45 +1736,45 @@ int bar(int n){ // CHECK45-32-EX: omp.dispatch.body: // CHECK45-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK45-32-EX: omp.inner.for.cond: -// CHECK45-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]] -// CHECK45-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]] +// CHECK45-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-32-EX-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK45-32-EX-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK45-32-EX: omp.inner.for.body: -// CHECK45-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-32-EX-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 10 // CHECK45-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK45-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK45-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK45-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK45-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-32-EX-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 10 // CHECK45-32-EX-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 10 // CHECK45-32-EX-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] // CHECK45-32-EX-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK45-32-EX-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] -// CHECK45-32-EX-NEXT: store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-32-EX-NEXT: store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-32-EX-NEXT: store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK45-32-EX-NEXT: store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK45-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK45-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK45-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-32-EX-NEXT: [[MUL8:%.*]] = mul nsw i32 [[TMP14]], [[TMP15]] // CHECK45-32-EX-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], [[MUL8]] -// CHECK45-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-32-EX-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP16]] -// CHECK45-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP17]] -// CHECK45-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-32-EX-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP18]] -// CHECK45-32-EX-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX11]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-32-EX-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX11]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK45-32-EX: omp.body.continue: // CHECK45-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK45-32-EX: omp.inner.for.inc: -// CHECK45-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK45-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK45-32-EX-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK45-32-EX-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK45-32-EX-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK45-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK45-32-EX: omp.inner.for.end: // CHECK45-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK45-32-EX: omp.dispatch.inc: @@ -1833,7 +1827,7 @@ int bar(int n){ // CHECK-64-NEXT: [[TMP6:%.*]] = load i64, ptr [[L_CASTED]], align 8 // CHECK-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK-64-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], i64 [[TMP6]]) #[[ATTR3:[0-9]+]] +// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]] // CHECK-64-NEXT: call void @__kmpc_target_deinit() // CHECK-64-NEXT: ret void // CHECK-64: worker.exit: @@ -1851,34 +1845,33 @@ int bar(int n){ // CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK-64-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK-64-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK-64-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK-64-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK-64-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK-64-NEXT: [[I3:%.*]] = alloca i32, align 4 // CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK-64-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 // CHECK-64-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK-64-NEXT: store i64 [[L]], ptr [[L_ADDR]], align 8 // CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK-64-NEXT: [[L1:%.*]] = call align 8 ptr @__kmpc_alloc_shared(i64 4) // CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK-64-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK-64-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK-64-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK-64-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK-64-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK-64-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK-64-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK-64-NEXT: store i32 0, ptr [[I]], align 4 // CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK-64-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] // CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK-64: omp.precond.then: // CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 // CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 @@ -1888,11 +1881,11 @@ int bar(int n){ // CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK-64: omp.dispatch.cond: // CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK-64-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] -// CHECK-64-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-64-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK-64-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK-64: cond.true: -// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK-64-NEXT: br label [[COND_END:%.*]] // CHECK-64: cond.false: // CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 @@ -1904,45 +1897,45 @@ int bar(int n){ // CHECK-64-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4 // CHECK-64-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK-64-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK-64-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK-64-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK-64-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK-64-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] // CHECK-64: omp.dispatch.body: // CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK-64: omp.inner.for.cond: -// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] -// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK-64-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK-64-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] +// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-64-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK-64-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK-64: omp.inner.for.body: -// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK-64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK-64-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK-64-NEXT: store i32 [[TMP18]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK-64-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-64-NEXT: store i32 [[TMP18]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK-64: omp.body.continue: // CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK-64: omp.inner.for.inc: -// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK-64-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK-64-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-64-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK-64-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK-64: omp.inner.for.end: // CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK-64: omp.dispatch.inc: // CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK-64-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK-64-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_LB]], align 4 +// CHECK-64-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK-64-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_LB]], align 4 // CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK-64-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK-64-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK-64-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_UB]], align 4 +// CHECK-64-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK-64-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_UB]], align 4 // CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]] // CHECK-64: omp.dispatch.end: // CHECK-64-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1953,11 +1946,11 @@ int bar(int n){ // CHECK-64-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK-64: .omp.final.then: // CHECK-64-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK-64-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK-64-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 -// CHECK-64-NEXT: [[MUL13:%.*]] = mul nsw i32 [[DIV12]], 1 -// CHECK-64-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] -// CHECK-64-NEXT: store i32 [[ADD14]], ptr [[I4]], align 4 +// CHECK-64-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK-64-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1 +// CHECK-64-NEXT: [[MUL12:%.*]] = mul nsw i32 [[DIV11]], 1 +// CHECK-64-NEXT: [[ADD13:%.*]] = add nsw i32 0, [[MUL12]] +// CHECK-64-NEXT: store i32 [[ADD13]], ptr [[I3]], align 4 // CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK-64: .omp.final.done: // CHECK-64-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 @@ -1970,12 +1963,11 @@ int bar(int n){ // CHECK-64: .omp.lastprivate.done: // CHECK-64-NEXT: br label [[OMP_PRECOND_END]] // CHECK-64: omp.precond.end: -// CHECK-64-NEXT: call void @__kmpc_free_shared(ptr [[L1]], i64 4) // CHECK-64-NEXT: ret void // // // CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40 -// CHECK-64-SAME: (i64 [[N:%.*]], ptr nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK-64-SAME: (i64 [[N:%.*]], ptr nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK-64-NEXT: entry: // CHECK-64-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK-64-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8 @@ -1995,7 +1987,7 @@ int bar(int n){ // CHECK-64-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK-64-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]] // CHECK-64-NEXT: call void @__kmpc_target_deinit() // CHECK-64-NEXT: ret void // CHECK-64: worker.exit: @@ -2069,31 +2061,31 @@ int bar(int n){ // CHECK-64: omp.dispatch.body: // CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK-64: omp.inner.for.cond: -// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] -// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]] +// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK-64-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK-64-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK-64: omp.inner.for.body: -// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK-64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK-64-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP16]] +// CHECK-64-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP20]] // CHECK-64-NEXT: [[CONV:%.*]] = sext i16 [[TMP18]] to i32 // CHECK-64-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV]], 1 // CHECK-64-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK-64-NEXT: store i16 [[CONV8]], ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP16]] +// CHECK-64-NEXT: store i16 [[CONV8]], ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP20]] // CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK-64: omp.body.continue: // CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK-64: omp.inner.for.inc: -// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK-64-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK-64-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK-64-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK-64: omp.inner.for.end: // CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK-64: omp.dispatch.inc: @@ -2142,7 +2134,7 @@ int bar(int n){ // CHECK-64-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK-64-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]] // CHECK-64-NEXT: call void @__kmpc_target_deinit() // CHECK-64-NEXT: ret void // CHECK-64: worker.exit: @@ -2196,29 +2188,29 @@ int bar(int n){ // CHECK-64: omp.dispatch.body: // CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK-64: omp.inner.for.cond: -// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] -// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]] +// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK-64-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK-64-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK-64: omp.inner.for.body: -// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK-64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK-64-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK-64-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK-64: omp.body.continue: // CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK-64: omp.inner.for.inc: -// CHECK-64-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK-64-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK-64-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK-64-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] // CHECK-64: omp.inner.for.end: // CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK-64: omp.dispatch.inc: @@ -2264,7 +2256,7 @@ int bar(int n){ // CHECK-64-NEXT: [[TMP4:%.*]] = load i64, ptr [[F_CASTED]], align 8 // CHECK-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK-64-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR3]] +// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR2]] // CHECK-64-NEXT: call void @__kmpc_target_deinit() // CHECK-64-NEXT: ret void // CHECK-64: worker.exit: @@ -2323,47 +2315,47 @@ int bar(int n){ // CHECK-64: omp.dispatch.body: // CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK-64: omp.inner.for.cond: -// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]] -// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]] +// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-64-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK-64-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK-64: omp.inner.for.body: -// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-64-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 10 // CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-64-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK-64-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-64-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 10 // CHECK-64-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 10 // CHECK-64-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] // CHECK-64-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK-64-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] -// CHECK-64-NEXT: store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-64-NEXT: store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-64-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-64-NEXT: store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK-64-NEXT: store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK-64-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-64-NEXT: [[MUL8:%.*]] = mul nsw i32 [[TMP14]], [[TMP15]] // CHECK-64-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], [[MUL8]] -// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-64-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP16]] -// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-64-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP18]] to i64 // CHECK-64-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM11]] -// CHECK-64-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-64-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK-64: omp.body.continue: // CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK-64: omp.inner.for.inc: -// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-64-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK-64-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK-64-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK-64: omp.inner.for.end: // CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK-64: omp.dispatch.inc: @@ -2416,7 +2408,7 @@ int bar(int n){ // CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[L_CASTED]], align 4 // CHECK-32-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK-32-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]], i32 [[TMP6]]) #[[ATTR3:[0-9]+]] +// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]] // CHECK-32-NEXT: call void @__kmpc_target_deinit() // CHECK-32-NEXT: ret void // CHECK-32: worker.exit: @@ -2434,34 +2426,33 @@ int bar(int n){ // CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK-32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK-32-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK-32-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK-32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK-32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK-32-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK-32-NEXT: [[I3:%.*]] = alloca i32, align 4 // CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 // CHECK-32-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK-32-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 // CHECK-32-NEXT: store i32 [[L]], ptr [[L_ADDR]], align 4 // CHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK-32-NEXT: [[L1:%.*]] = call align 8 ptr @__kmpc_alloc_shared(i32 4) // CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK-32-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK-32-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK-32-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK-32-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK-32-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK-32-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK-32-NEXT: store i32 0, ptr [[I]], align 4 // CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK-32-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] // CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK-32: omp.precond.then: // CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 // CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 @@ -2471,11 +2462,11 @@ int bar(int n){ // CHECK-32-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK-32: omp.dispatch.cond: // CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK-32-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] -// CHECK-32-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK-32-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK-32: cond.true: -// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK-32-NEXT: br label [[COND_END:%.*]] // CHECK-32: cond.false: // CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 @@ -2487,44 +2478,44 @@ int bar(int n){ // CHECK-32-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4 // CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK-32-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK-32-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK-32-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK-32-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] // CHECK-32: omp.dispatch.body: // CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK-32: omp.inner.for.cond: -// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] -// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK-32-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK-32-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] +// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-32-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK-32-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK-32: omp.inner.for.body: -// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP17]] -// CHECK-32-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK-32-NEXT: store i32 [[TMP18]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK-32-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-32-NEXT: store i32 [[TMP18]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK-32: omp.body.continue: // CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK-32: omp.inner.for.inc: -// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK-32-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK-32-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-32-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK-32-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK-32: omp.inner.for.end: // CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK-32: omp.dispatch.inc: // CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK-32-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK-32-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK-32-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_LB]], align 4 +// CHECK-32-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK-32-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_LB]], align 4 // CHECK-32-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK-32-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK-32-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK-32-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_UB]], align 4 +// CHECK-32-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK-32-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_UB]], align 4 // CHECK-32-NEXT: br label [[OMP_DISPATCH_COND]] // CHECK-32: omp.dispatch.end: // CHECK-32-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2535,11 +2526,11 @@ int bar(int n){ // CHECK-32-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK-32: .omp.final.then: // CHECK-32-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK-32-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK-32-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 -// CHECK-32-NEXT: [[MUL13:%.*]] = mul nsw i32 [[DIV12]], 1 -// CHECK-32-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] -// CHECK-32-NEXT: store i32 [[ADD14]], ptr [[I4]], align 4 +// CHECK-32-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK-32-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1 +// CHECK-32-NEXT: [[MUL12:%.*]] = mul nsw i32 [[DIV11]], 1 +// CHECK-32-NEXT: [[ADD13:%.*]] = add nsw i32 0, [[MUL12]] +// CHECK-32-NEXT: store i32 [[ADD13]], ptr [[I3]], align 4 // CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK-32: .omp.final.done: // CHECK-32-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 @@ -2552,12 +2543,11 @@ int bar(int n){ // CHECK-32: .omp.lastprivate.done: // CHECK-32-NEXT: br label [[OMP_PRECOND_END]] // CHECK-32: omp.precond.end: -// CHECK-32-NEXT: call void @__kmpc_free_shared(ptr [[L1]], i32 4) // CHECK-32-NEXT: ret void // // // CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40 -// CHECK-32-SAME: (i32 [[N:%.*]], ptr nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK-32-SAME: (i32 [[N:%.*]], ptr nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK-32-NEXT: entry: // CHECK-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK-32-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4 @@ -2577,7 +2567,7 @@ int bar(int n){ // CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK-32-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK-32-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]] // CHECK-32-NEXT: call void @__kmpc_target_deinit() // CHECK-32-NEXT: ret void // CHECK-32: worker.exit: @@ -2651,30 +2641,30 @@ int bar(int n){ // CHECK-32: omp.dispatch.body: // CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK-32: omp.inner.for.cond: -// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] -// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]] +// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK-32-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK-32-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK-32: omp.inner.for.body: -// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i32 0, i32 [[TMP17]] -// CHECK-32-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP16]] +// CHECK-32-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP20]] // CHECK-32-NEXT: [[CONV:%.*]] = sext i16 [[TMP18]] to i32 // CHECK-32-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV]], 1 // CHECK-32-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK-32-NEXT: store i16 [[CONV8]], ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP16]] +// CHECK-32-NEXT: store i16 [[CONV8]], ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP20]] // CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK-32: omp.body.continue: // CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK-32: omp.inner.for.inc: -// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK-32-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK-32-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK-32-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK-32: omp.inner.for.end: // CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK-32: omp.dispatch.inc: @@ -2723,7 +2713,7 @@ int bar(int n){ // CHECK-32-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK-32-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK-32-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]] // CHECK-32-NEXT: call void @__kmpc_target_deinit() // CHECK-32-NEXT: ret void // CHECK-32: worker.exit: @@ -2777,28 +2767,28 @@ int bar(int n){ // CHECK-32: omp.dispatch.body: // CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK-32: omp.inner.for.cond: -// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] -// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]] +// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK-32-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK-32-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK-32: omp.inner.for.body: -// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK-32: omp.body.continue: // CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK-32: omp.inner.for.inc: -// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK-32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK-32-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK-32-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] // CHECK-32: omp.inner.for.end: // CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK-32: omp.dispatch.inc: @@ -2844,7 +2834,7 @@ int bar(int n){ // CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[F_CASTED]], align 4 // CHECK-32-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK-32-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i32 [[TMP4]]) #[[ATTR3]] +// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i32 [[TMP4]]) #[[ATTR2]] // CHECK-32-NEXT: call void @__kmpc_target_deinit() // CHECK-32-NEXT: ret void // CHECK-32: worker.exit: @@ -2903,45 +2893,45 @@ int bar(int n){ // CHECK-32: omp.dispatch.body: // CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK-32: omp.inner.for.cond: -// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]] -// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]] +// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-32-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK-32-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK-32: omp.inner.for.body: -// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-32-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 10 // CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-32-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 10 // CHECK-32-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 10 // CHECK-32-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] // CHECK-32-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK-32-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] -// CHECK-32-NEXT: store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-32-NEXT: store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-32-NEXT: store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK-32-NEXT: store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-32-NEXT: [[MUL8:%.*]] = mul nsw i32 [[TMP14]], [[TMP15]] // CHECK-32-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], [[MUL8]] -// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-32-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP16]] -// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP17]] -// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-32-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP18]] -// CHECK-32-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX11]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-32-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX11]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK-32: omp.body.continue: // CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK-32: omp.inner.for.inc: -// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-32-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK-32-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK-32-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK-32: omp.inner.for.end: // CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK-32: omp.dispatch.inc: @@ -2994,7 +2984,7 @@ int bar(int n){ // CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[L_CASTED]], align 4 // CHECK-32-EX-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK-32-EX-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK-32-EX-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]], i32 [[TMP6]]) #[[ATTR3:[0-9]+]] +// CHECK-32-EX-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]] // CHECK-32-EX-NEXT: call void @__kmpc_target_deinit() // CHECK-32-EX-NEXT: ret void // CHECK-32-EX: worker.exit: @@ -3012,34 +3002,33 @@ int bar(int n){ // CHECK-32-EX-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK-32-EX-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK-32-EX-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK-32-EX-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// CHECK-32-EX-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK-32-EX-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK-32-EX-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK-32-EX-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK-32-EX-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK-32-EX-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK-32-EX-NEXT: [[I4:%.*]] = alloca i32, align 4 +// CHECK-32-EX-NEXT: [[I3:%.*]] = alloca i32, align 4 // CHECK-32-EX-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK-32-EX-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 // CHECK-32-EX-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK-32-EX-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 // CHECK-32-EX-NEXT: store i32 [[L]], ptr [[L_ADDR]], align 4 // CHECK-32-EX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK-32-EX-NEXT: [[L1:%.*]] = call align 8 ptr @__kmpc_alloc_shared(i32 4) // CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK-32-EX-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK-32-EX-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK-32-EX-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK-32-EX-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK-32-EX-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK-32-EX-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK-32-EX-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK-32-EX-NEXT: store i32 0, ptr [[I]], align 4 // CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] // CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK-32-EX: omp.precond.then: // CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 // CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 @@ -3049,11 +3038,11 @@ int bar(int n){ // CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK-32-EX: omp.dispatch.cond: // CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK-32-EX-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] -// CHECK-32-EX-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-32-EX-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK-32-EX-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK-32-EX: cond.true: -// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK-32-EX-NEXT: br label [[COND_END:%.*]] // CHECK-32-EX: cond.false: // CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 @@ -3065,44 +3054,44 @@ int bar(int n){ // CHECK-32-EX-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4 // CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK-32-EX-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] -// CHECK-32-EX-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] +// CHECK-32-EX-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK-32-EX-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] // CHECK-32-EX: omp.dispatch.body: // CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK-32-EX: omp.inner.for.cond: -// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] -// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK-32-EX-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] -// CHECK-32-EX-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] +// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-32-EX-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK-32-EX-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK-32-EX: omp.inner.for.body: -// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP17]] -// CHECK-32-EX-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK-32-EX-NEXT: store i32 [[TMP18]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK-32-EX-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-32-EX-NEXT: store i32 [[TMP18]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK-32-EX: omp.body.continue: // CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK-32-EX: omp.inner.for.inc: -// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK-32-EX-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK-32-EX-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-32-EX-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK-32-EX-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK-32-EX: omp.inner.for.end: // CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK-32-EX: omp.dispatch.inc: // CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK-32-EX-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK-32-EX-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK-32-EX-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_LB]], align 4 +// CHECK-32-EX-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK-32-EX-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_LB]], align 4 // CHECK-32-EX-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK-32-EX-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK-32-EX-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK-32-EX-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_UB]], align 4 +// CHECK-32-EX-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK-32-EX-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_UB]], align 4 // CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_COND]] // CHECK-32-EX: omp.dispatch.end: // CHECK-32-EX-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -3113,11 +3102,11 @@ int bar(int n){ // CHECK-32-EX-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK-32-EX: .omp.final.then: // CHECK-32-EX-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK-32-EX-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK-32-EX-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1 -// CHECK-32-EX-NEXT: [[MUL13:%.*]] = mul nsw i32 [[DIV12]], 1 -// CHECK-32-EX-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] -// CHECK-32-EX-NEXT: store i32 [[ADD14]], ptr [[I4]], align 4 +// CHECK-32-EX-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK-32-EX-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1 +// CHECK-32-EX-NEXT: [[MUL12:%.*]] = mul nsw i32 [[DIV11]], 1 +// CHECK-32-EX-NEXT: [[ADD13:%.*]] = add nsw i32 0, [[MUL12]] +// CHECK-32-EX-NEXT: store i32 [[ADD13]], ptr [[I3]], align 4 // CHECK-32-EX-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK-32-EX: .omp.final.done: // CHECK-32-EX-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 @@ -3130,12 +3119,11 @@ int bar(int n){ // CHECK-32-EX: .omp.lastprivate.done: // CHECK-32-EX-NEXT: br label [[OMP_PRECOND_END]] // CHECK-32-EX: omp.precond.end: -// CHECK-32-EX-NEXT: call void @__kmpc_free_shared(ptr [[L1]], i32 4) // CHECK-32-EX-NEXT: ret void // // // CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40 -// CHECK-32-EX-SAME: (i32 [[N:%.*]], ptr nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK-32-EX-SAME: (i32 [[N:%.*]], ptr nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK-32-EX-NEXT: entry: // CHECK-32-EX-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK-32-EX-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4 @@ -3155,7 +3143,7 @@ int bar(int n){ // CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK-32-EX-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK-32-EX-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK-32-EX-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK-32-EX-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l40_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]] // CHECK-32-EX-NEXT: call void @__kmpc_target_deinit() // CHECK-32-EX-NEXT: ret void // CHECK-32-EX: worker.exit: @@ -3229,30 +3217,30 @@ int bar(int n){ // CHECK-32-EX: omp.dispatch.body: // CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK-32-EX: omp.inner.for.cond: -// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] -// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]] +// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK-32-EX-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK-32-EX-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK-32-EX: omp.inner.for.body: -// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i32 0, i32 [[TMP17]] -// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP16]] +// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP20]] // CHECK-32-EX-NEXT: [[CONV:%.*]] = sext i16 [[TMP18]] to i32 // CHECK-32-EX-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV]], 1 // CHECK-32-EX-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK-32-EX-NEXT: store i16 [[CONV8]], ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP16]] +// CHECK-32-EX-NEXT: store i16 [[CONV8]], ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP20]] // CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK-32-EX: omp.body.continue: // CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK-32-EX: omp.inner.for.inc: -// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK-32-EX-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK-32-EX-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK-32-EX-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] +// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK-32-EX: omp.inner.for.end: // CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK-32-EX: omp.dispatch.inc: @@ -3301,7 +3289,7 @@ int bar(int n){ // CHECK-32-EX-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK-32-EX-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK-32-EX-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK-32-EX-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR3]] +// CHECK-32-EX-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l45_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]] // CHECK-32-EX-NEXT: call void @__kmpc_target_deinit() // CHECK-32-EX-NEXT: ret void // CHECK-32-EX: worker.exit: @@ -3355,28 +3343,28 @@ int bar(int n){ // CHECK-32-EX: omp.dispatch.body: // CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK-32-EX: omp.inner.for.cond: -// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] -// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]] +// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK-32-EX-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK-32-EX-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK-32-EX: omp.inner.for.body: -// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK-32-EX: omp.body.continue: // CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK-32-EX: omp.inner.for.inc: -// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK-32-EX-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK-32-EX-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK-32-EX-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] +// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] // CHECK-32-EX: omp.inner.for.end: // CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK-32-EX: omp.dispatch.inc: @@ -3422,7 +3410,7 @@ int bar(int n){ // CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[F_CASTED]], align 4 // CHECK-32-EX-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK-32-EX-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK-32-EX-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i32 [[TMP4]]) #[[ATTR3]] +// CHECK-32-EX-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l50_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i32 [[TMP4]]) #[[ATTR2]] // CHECK-32-EX-NEXT: call void @__kmpc_target_deinit() // CHECK-32-EX-NEXT: ret void // CHECK-32-EX: worker.exit: @@ -3481,45 +3469,45 @@ int bar(int n){ // CHECK-32-EX: omp.dispatch.body: // CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK-32-EX: omp.inner.for.cond: -// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]] -// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]] +// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-32-EX-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK-32-EX-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK-32-EX: omp.inner.for.body: -// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-32-EX-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 10 // CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-32-EX-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 10 // CHECK-32-EX-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 10 // CHECK-32-EX-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] // CHECK-32-EX-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK-32-EX-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] -// CHECK-32-EX-NEXT: store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-32-EX-NEXT: store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-32-EX-NEXT: store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK-32-EX-NEXT: store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-32-EX-NEXT: [[MUL8:%.*]] = mul nsw i32 [[TMP14]], [[TMP15]] // CHECK-32-EX-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], [[MUL8]] -// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-32-EX-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP16]] -// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP17]] -// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-32-EX-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP18]] -// CHECK-32-EX-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX11]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-32-EX-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX11]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK-32-EX: omp.body.continue: // CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK-32-EX: omp.inner.for.inc: -// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK-32-EX-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK-32-EX-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK-32-EX-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK-32-EX: omp.inner.for.end: // CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]] // CHECK-32-EX: omp.dispatch.inc: diff --git a/clang/test/OpenMP/ompx_attributes_codegen.cpp b/clang/test/OpenMP/ompx_attributes_codegen.cpp index 21e9805cbe829..bcf524b464aef 100644 --- a/clang/test/OpenMP/ompx_attributes_codegen.cpp +++ b/clang/test/OpenMP/ompx_attributes_codegen.cpp @@ -1,16 +1,17 @@ // REQUIRES: amdgpu-registered-target // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s -// RUN: %clang_cc1 -target-cpu gfx900 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=AMD +// RUN: %clang_cc1 -target-cpu gfx900 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=AMD +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple nvptx64 -fopenmp-targets=nvptx64 -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=NVIDIA // expected-no-diagnostics // Check that the target attributes are set on the generated kernel void func() { - // CHECK: amdgpu_kernel void @__omp_offloading[[HASH:.*]]_l15() #0 - // CHECK: amdgpu_kernel void @__omp_offloading[[HASH:.*]]_l17() - // CHECK: amdgpu_kernel void @__omp_offloading[[HASH:.*]]_l19() #4 + // AMD: amdgpu_kernel void @__omp_offloading[[HASH:.*]]_l16() #0 + // AMD: amdgpu_kernel void @__omp_offloading[[HASH:.*]]_l18() + // AMD: amdgpu_kernel void @__omp_offloading[[HASH:.*]]_l20() #4 #pragma omp target ompx_attribute([[clang::amdgpu_flat_work_group_size(10, 20)]]) {} @@ -21,11 +22,20 @@ void func() { {} } -// CHECK: attributes #0 -// CHECK-SAME: "amdgpu-flat-work-group-size"="10,20" -// CHECK: attributes #4 -// CHECK-SAME: "amdgpu-flat-work-group-size"="3,17" -// CHECK-SAME: "amdgpu-waves-per-eu"="3,7" +// AMD: attributes #0 +// AMD-SAME: "amdgpu-flat-work-group-size"="10,20" +// AMD-SAME: "omp_target_thread_limit"="20" +// AMD: "omp_target_thread_limit"="45" +// AMD: attributes #4 +// AMD-SAME: "amdgpu-flat-work-group-size"="3,17" +// AMD-SAME: "amdgpu-waves-per-eu"="3,7" +// AMD-SAME: "omp_target_thread_limit"="17" -// CHECK: !{ptr @__omp_offloading[[HASH]]_l17, !"maxntidx", i32 45} -// CHECK: !{ptr @__omp_offloading[[HASH]]_l17, !"minctasm", i32 90} +// It is unclear if we should use the AMD annotations for other targets, we do for now. +// NVIDIA: "omp_target_thread_limit"="20" +// NVIDIA: "omp_target_thread_limit"="45" +// NVIDIA: "omp_target_thread_limit"="17" +// NVIDIA: !{ptr @__omp_offloading[[HASH1:.*]]_l16, !"maxntidx", i32 20} +// NVIDIA: !{ptr @__omp_offloading[[HASH2:.*]]_l18, !"minctasm", i32 90} +// NVIDIA: !{ptr @__omp_offloading[[HASH2]]_l18, !"maxntidx", i32 45} +// NVIDIA: !{ptr @__omp_offloading[[HASH3:.*]]_l20, !"maxntidx", i32 17} diff --git a/clang/test/OpenMP/parallel_ast_print.cpp b/clang/test/OpenMP/parallel_ast_print.cpp index 341cd8a47a709..dcfec564ed074 100644 --- a/clang/test/OpenMP/parallel_ast_print.cpp +++ b/clang/test/OpenMP/parallel_ast_print.cpp @@ -1,18 +1,18 @@ -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -ast-print %s | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=50 -ast-print %s | FileCheck %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print | FileCheck %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -std=c++11 -include-pch %t -fsyntax-only -verify -Wno-vla %s -ast-print | FileCheck %s -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -ast-print %s | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=50 -ast-print %s | FileCheck %s // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print | FileCheck %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -std=c++11 -include-pch %t -fsyntax-only -verify -Wno-vla %s -ast-print | FileCheck %s -// RUN: %clang_cc1 -DOMP51 -verify -fopenmp -ast-print %s | FileCheck -check-prefixes=CHECK,OMP51 %s +// RUN: %clang_cc1 -DOMP51 -verify -Wno-vla -fopenmp -ast-print %s | FileCheck -check-prefixes=CHECK,OMP51 %s // RUN: %clang_cc1 -DOMP51 -fopenmp -x c++ -std=c++11 -emit-pch -o %t %s -// RUN: %clang_cc1 -DOMP51 -fopenmp -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print | FileCheck -check-prefixes=CHECK,OMP51 %s +// RUN: %clang_cc1 -DOMP51 -fopenmp -std=c++11 -include-pch %t -fsyntax-only -verify -Wno-vla %s -ast-print | FileCheck -check-prefixes=CHECK,OMP51 %s -// RUN: %clang_cc1 -DOMP51 -verify -fopenmp-simd -ast-print %s | FileCheck -check-prefixes=CHECK,OMP51 %s +// RUN: %clang_cc1 -DOMP51 -verify -Wno-vla -fopenmp-simd -ast-print %s | FileCheck -check-prefixes=CHECK,OMP51 %s // RUN: %clang_cc1 -DOMP51 -fopenmp-simd -x c++ -std=c++11 -emit-pch -o %t %s -// RUN: %clang_cc1 -DOMP51 -fopenmp-simd -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print | FileCheck -check-prefixes=CHECK,OMP51 %s +// RUN: %clang_cc1 -DOMP51 -fopenmp-simd -std=c++11 -include-pch %t -fsyntax-only -verify -Wno-vla %s -ast-print | FileCheck -check-prefixes=CHECK,OMP51 %s // expected-no-diagnostics #ifndef HEADER diff --git a/clang/test/OpenMP/parallel_codegen.cpp b/clang/test/OpenMP/parallel_codegen.cpp index b90729907acb2..5c98761be0808 100644 --- a/clang/test/OpenMP/parallel_codegen.cpp +++ b/clang/test/OpenMP/parallel_codegen.cpp @@ -1,17 +1,17 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -verify -fopenmp -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-enable-irbuilder -DIRBUILDER -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-enable-irbuilder -DIRBUILDER -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -DIRBUILDER -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -DIRBUILDER -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -gno-column-info -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -DIRBUILDER -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -gno-column-info -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER diff --git a/clang/test/OpenMP/parallel_firstprivate_codegen.cpp b/clang/test/OpenMP/parallel_firstprivate_codegen.cpp index 706a9fb4b25dd..eb71100bd4d1b 100644 --- a/clang/test/OpenMP/parallel_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/parallel_firstprivate_codegen.cpp @@ -1,31 +1,31 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -x c++ -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple x86_64-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple x86_64-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef ARRAY #ifndef HEADER diff --git a/clang/test/OpenMP/parallel_for_ast_print.cpp b/clang/test/OpenMP/parallel_for_ast_print.cpp index f9f6a8aa01d28..df5e7596f6a90 100644 --- a/clang/test/OpenMP/parallel_for_ast_print.cpp +++ b/clang/test/OpenMP/parallel_for_ast_print.cpp @@ -4,6 +4,9 @@ // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=51 -ast-print %s -DOMP51 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP51 // RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -x c++ -std=c++11 -emit-pch -o %t %s -DOMP51 // RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -DOMP51 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP51 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=52 -ast-print %s -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=52 -x c++ -std=c++11 -emit-pch -o %t %s -DOMP52 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=52 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 // RUN: %clang_cc1 -verify -fopenmp-simd -ast-print %s | FileCheck %s --check-prefix=CHECK --check-prefix=OMP50 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -emit-pch -o %t %s @@ -12,6 +15,10 @@ // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=51 -x c++ -std=c++11 -emit-pch -o %t %s -DOMP51 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=51 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -DOMP51 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP51 // expected-no-diagnostics +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=52 -ast-print %s -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=52 -x c++ -std=c++11 -emit-pch -o %t %s -DOMP52 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=52 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 +// expected-no-diagnostics #ifndef HEADER #define HEADER @@ -76,13 +83,14 @@ T tmain(T argc) { // CHECK: static T a; static T g; #pragma omp threadprivate(g) -#ifdef OMP51 +#if defined(OMP51) || defined(OMP52) #pragma omp parallel for schedule(dynamic) default(none) copyin(g) linear(a) allocate(a) lastprivate(conditional: d, e,f) order(reproducible:concurrent) #else #pragma omp parallel for schedule(dynamic) default(none) copyin(g) linear(a) allocate(a) lastprivate(conditional: d, e,f) order(concurrent) #endif // OMP51 // OMP50: #pragma omp parallel for schedule(dynamic) default(none) copyin(g) linear(a) allocate(a) lastprivate(conditional: d,e,f) order(concurrent) // OMP51: #pragma omp parallel for schedule(dynamic) default(none) copyin(g) linear(a) allocate(a) lastprivate(conditional: d,e,f) order(reproducible: concurrent) + // OMP52: #pragma omp parallel for schedule(dynamic) default(none) copyin(g) linear(a) allocate(a) lastprivate(conditional: d,e,f) order(reproducible: concurrent) for (int i = 0; i < 2; ++i) a = 2; // CHECK-NEXT: for (int i = 0; i < 2; ++i) @@ -149,11 +157,15 @@ int main(int argc, char **argv) { a = 2; // CHECK-NEXT: for (int i = 0; i < 2; ++i) // CHECK-NEXT: a = 2; +#ifdef OMP52 +#pragma omp parallel for private(argc, b), firstprivate(argv, c), lastprivate(d, f) collapse(2) schedule(auto) ordered if (argc) num_threads(a) default(shared) shared(e) reduction(+ : h) linear(a: step(-5)) +#else #pragma omp parallel for private(argc, b), firstprivate(argv, c), lastprivate(d, f) collapse(2) schedule(auto) ordered if (argc) num_threads(a) default(shared) shared(e) reduction(+ : h) linear(a:-5) +#endif for (int i = 0; i < 10; ++i) for (int j = 0; j < 10; ++j) foo(); - // CHECK-NEXT: #pragma omp parallel for private(argc,b) firstprivate(argv,c) lastprivate(d,f) collapse(2) schedule(auto) ordered if(argc) num_threads(a) default(shared) shared(e) reduction(+: h) linear(a: -5) + // CHECK-NEXT: #pragma omp parallel for private(argc,b) firstprivate(argv,c) lastprivate(d,f) collapse(2) schedule(auto) ordered if(argc) num_threads(a) default(shared) shared(e) reduction(+: h) linear(a: step(-5)) // CHECK-NEXT: for (int i = 0; i < 10; ++i) // CHECK-NEXT: for (int j = 0; j < 10; ++j) // CHECK-NEXT: foo(); diff --git a/clang/test/OpenMP/parallel_for_codegen.cpp b/clang/test/OpenMP/parallel_for_codegen.cpp index 3c21be5f6347e..dcd4ccfa5dcb3 100644 --- a/clang/test/OpenMP/parallel_for_codegen.cpp +++ b/clang/test/OpenMP/parallel_for_codegen.cpp @@ -1,29 +1,29 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK2 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -gno-column-info -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -gno-column-info -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp-simd -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp-simd -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics -// RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifndef HEADER #define HEADER diff --git a/clang/test/OpenMP/parallel_for_linear_messages.cpp b/clang/test/OpenMP/parallel_for_linear_messages.cpp index a6dc1fdde63c2..4e863de79fe0e 100644 --- a/clang/test/OpenMP/parallel_for_linear_messages.cpp +++ b/clang/test/OpenMP/parallel_for_linear_messages.cpp @@ -1,12 +1,14 @@ // RUN: %clang_cc1 -verify -fopenmp %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp -fopenmp-version=52 -DOMP52 %s -Wuninitialized // RUN: %clang_cc1 -verify -fopenmp-simd %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp-simd -fopenmp-version=52 -DOMP52 %s -Wuninitialized extern int omp_default_mem_alloc; void xxx(int argc) { - int i, lin, step; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step' to silence this warning}} -#pragma omp parallel for linear(lin : step) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step' is uninitialized when used here}} + int i, lin, step_sz; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step_sz' to silence this warning}} +#pragma omp parallel for linear(lin : step_sz) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step_sz' is uninitialized when used here}} for (i = 0; i < 10; ++i) ; } @@ -261,16 +263,28 @@ int main(int argc, char **argv) { #pragma omp parallel for linear(i) for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 +#pragma omp parallel for linear(i : step(4)) +#else #pragma omp parallel for linear(i : 4) +#endif for (int k = 0; k < argc; ++k) { ++k; i += 4; } } -#pragma omp parallel for linear(j) +#ifdef OMP52 +#pragma omp for linear(j: step() //omp52-error 2 {{expected expression}} omp52-error{{expected ')'}} omp52-note{{to match this '('}} +#else +#pragma omp for linear(j) +#endif for (int k = 0; k < argc; ++k) ++k; -#pragma omp parallel for linear(i) +#ifdef OMP52 + #pragma omp for linear(i: step(1), step(2)) // omp52-error {{multiple 'step size' found in linear clause}} +#else + #pragma omp for linear(i) +#endif for (int k = 0; k < argc; ++k) ++k; diff --git a/clang/test/OpenMP/parallel_for_simd_ast_print.cpp b/clang/test/OpenMP/parallel_for_simd_ast_print.cpp index 8b2b21e505ce4..69c21f5bdfdf6 100644 --- a/clang/test/OpenMP/parallel_for_simd_ast_print.cpp +++ b/clang/test/OpenMP/parallel_for_simd_ast_print.cpp @@ -104,7 +104,7 @@ template struct S { // CHECK: T val; // CHECK: T lin = 0; #pragma omp parallel for simd private(val) safelen(7) linear(lin : -5) lastprivate(res) simdlen(5) if(7) allocate(lin) -// CHECK-NEXT: #pragma omp parallel for simd private(val) safelen(7) linear(lin: -5) lastprivate(res) simdlen(5) if(7) allocate(lin) +// CHECK-NEXT: #pragma omp parallel for simd private(val) safelen(7) linear(lin: step(-5)) lastprivate(res) simdlen(5) if(7) allocate(lin) for (T i = 7; i < m_a; ++i) { val = v[i-7] + m_a; res = val; @@ -145,7 +145,7 @@ template struct S2 { // CHECK: template<> struct S2<4> { // CHECK-NEXT: static void func(int n, float *a, float *b, float *c) { // CHECK-NEXT: int k1 = 0, k2 = 0; -// CHECK-NEXT: #pragma omp parallel for simd allocate(k1) safelen(4) linear(k1,k2: 4) aligned(a: 4) simdlen(4) +// CHECK-NEXT: #pragma omp parallel for simd allocate(k1) safelen(4) linear(k1,k2: step(4)) aligned(a: 4) simdlen(4) // CHECK-NEXT: for (int i = 0; i < n; i++) { // CHECK-NEXT: c[i] = a[i] + b[i]; // CHECK-NEXT: c[k1] = a[k1] + b[k1]; @@ -191,7 +191,7 @@ int main (int argc, char **argv) { const int CLEN = 4; // CHECK-NEXT: const int CLEN = 4; #pragma omp parallel for simd aligned(a:CLEN) linear(a:CLEN) safelen(CLEN) collapse( 1 ) simdlen(CLEN) -// CHECK-NEXT: #pragma omp parallel for simd aligned(a: CLEN) linear(a: CLEN) safelen(CLEN) collapse(1) simdlen(CLEN) +// CHECK-NEXT: #pragma omp parallel for simd aligned(a: CLEN) linear(a: step(CLEN)) safelen(CLEN) collapse(1) simdlen(CLEN) for (int i = 0; i < 10; ++i)foo(); // CHECK-NEXT: for (int i = 0; i < 10; ++i) // CHECK-NEXT: foo(); diff --git a/clang/test/OpenMP/parallel_for_simd_linear_messages.cpp b/clang/test/OpenMP/parallel_for_simd_linear_messages.cpp index 6ca28adad04fd..ab682e29cd93c 100644 --- a/clang/test/OpenMP/parallel_for_simd_linear_messages.cpp +++ b/clang/test/OpenMP/parallel_for_simd_linear_messages.cpp @@ -1,11 +1,13 @@ // RUN: %clang_cc1 -verify -fopenmp %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp -fopenmp-version=52 -DOMP52 %s -Wuninitialized // RUN: %clang_cc1 -verify -fopenmp-simd %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp-simd -fopenmp-version=52 -DOMP52 %s -Wuninitialized extern int omp_default_mem_alloc; void xxx(int argc) { - int i, lin, step; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step' to silence this warning}} -#pragma omp parallel for simd linear(i, lin : step) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step' is uninitialized when used here}} + int i, lin, step_sz; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step_sz' to silence this warning}} +#pragma omp parallel for simd linear(i, lin : step_sz) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step_sz' is uninitialized when used here}} for (i = 0; i < 10; ++i) ; } @@ -210,12 +212,24 @@ int main(int argc, char **argv) { int i; #pragma omp parallel for simd linear(i) for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp parallel for simd linear(i : step(4)) +#else #pragma omp parallel for simd linear(i : 4) +#endif for (int k = 0; k < argc; ++k) { ++k; i += 4; } } +#ifdef OMP52 + #pragma omp for linear(j: step() //omp52-error 2 {{expected expression}} omp52-error{{expected ')'}} omp52-note{{to match this '('}} +#else #pragma omp parallel for simd linear(j) +#endif for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp for linear(i: step(1), step(2)) // omp52-error {{multiple 'step size' found in linear clause}} +#else #pragma omp parallel for simd linear(i) +#endif for (int k = 0; k < argc; ++k) ++k; foomain(argc,argv); // expected-note {{in instantiation of function template specialization 'foomain' requested here}} diff --git a/clang/test/OpenMP/parallel_masked_ast_print.cpp b/clang/test/OpenMP/parallel_masked_ast_print.cpp index ce1552ff5bcf1..c56c7aa14c936 100644 --- a/clang/test/OpenMP/parallel_masked_ast_print.cpp +++ b/clang/test/OpenMP/parallel_masked_ast_print.cpp @@ -1,10 +1,10 @@ -// RUN: %clang_cc1 -verify -fopenmp -ast-print %s | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -ast-print %s | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print | FileCheck %s +// RUN: %clang_cc1 -fopenmp -std=c++11 -include-pch %t -fsyntax-only -verify -Wno-vla %s -ast-print | FileCheck %s -// RUN: %clang_cc1 -verify -fopenmp-simd -ast-print %s | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -ast-print %s | FileCheck %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print | FileCheck %s +// RUN: %clang_cc1 -fopenmp-simd -std=c++11 -include-pch %t -fsyntax-only -verify -Wno-vla %s -ast-print | FileCheck %s // expected-no-diagnostics #ifndef HEADER diff --git a/clang/test/OpenMP/parallel_masked_taskloop_simd_ast_print.cpp b/clang/test/OpenMP/parallel_masked_taskloop_simd_ast_print.cpp index 888e123d2a512..1d01ac9a668c8 100644 --- a/clang/test/OpenMP/parallel_masked_taskloop_simd_ast_print.cpp +++ b/clang/test/OpenMP/parallel_masked_taskloop_simd_ast_print.cpp @@ -62,7 +62,7 @@ int main(int argc, char **argv) { #pragma omp taskgroup task_reduction(+: d) #pragma omp parallel masked taskloop simd if(parallel: a) default(none) shared(a, b, argc) final(b) priority(5) num_tasks(argc) reduction(*: g) aligned(argv: 8) linear(c:b) filter(tid) // CHECK-NEXT: #pragma omp taskgroup task_reduction(+: d) - // CHECK-NEXT: #pragma omp parallel masked taskloop simd if(parallel: a) default(none) shared(a,b,argc) final(b) priority(5) num_tasks(argc) reduction(*: g) aligned(argv: 8) linear(c: b) filter(tid) + // CHECK-NEXT: #pragma omp parallel masked taskloop simd if(parallel: a) default(none) shared(a,b,argc) final(b) priority(5) num_tasks(argc) reduction(*: g) aligned(argv: 8) linear(c: step(b)) filter(tid) for (int i = 0; i < 2; ++i) a = 2; // CHECK-NEXT: for (int i = 0; i < 2; ++i) diff --git a/clang/test/OpenMP/parallel_masked_taskloop_simd_linear_messages.cpp b/clang/test/OpenMP/parallel_masked_taskloop_simd_linear_messages.cpp index 767d683a80766..a913a4e331964 100644 --- a/clang/test/OpenMP/parallel_masked_taskloop_simd_linear_messages.cpp +++ b/clang/test/OpenMP/parallel_masked_taskloop_simd_linear_messages.cpp @@ -1,6 +1,8 @@ // RUN: %clang_cc1 -verify -fopenmp %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp -fopenmp-version=52 -DOMP52 %s -Wuninitialized // RUN: %clang_cc1 -verify -fopenmp-simd %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp-simd -fopenmp-version=52 -DOMP52 %s -Wuninitialized typedef void **omp_allocator_handle_t; extern const omp_allocator_handle_t omp_null_allocator; @@ -14,8 +16,8 @@ extern const omp_allocator_handle_t omp_pteam_mem_alloc; extern const omp_allocator_handle_t omp_thread_mem_alloc; void xxx(int argc) { - int i, lin, step; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step' to silence this warning}} -#pragma omp parallel masked taskloop simd linear(i, lin : step) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step' is uninitialized when used here}} + int i, lin, step_sz; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step_sz' to silence this warning}} +#pragma omp parallel masked taskloop simd linear(i, lin : step_sz) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step_sz' is uninitialized when used here}} for (i = 0; i < 10; ++i) ; } @@ -129,11 +131,11 @@ template int foomain(I argc, C **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel masked taskloop simd linear (val // expected-error {{use of undeclared identifier 'val'}} expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel masked taskloop simd linear (uval( // expected-error {{expected expression}} expected-error 2 {{expected ')'}} expected-note 2 {{to match this '('}} + #pragma omp parallel masked taskloop simd linear (uval( // expected-error {{expected expression}} expected-error 2 {{expected ')'}} expected-note 2 {{to match this '('}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel masked taskloop simd linear (ref() // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} + #pragma omp parallel masked taskloop simd linear (ref() // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel masked taskloop simd linear (foo() // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} + #pragma omp parallel masked taskloop simd linear (foo() // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel masked taskloop simd linear () // expected-error {{expected expression}} for (int k = 0; k < argc; ++k) ++k; @@ -141,7 +143,7 @@ template int foomain(I argc, C **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel masked taskloop simd linear (val argc // expected-error {{use of undeclared identifier 'val'}} expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel masked taskloop simd linear (val(argc, // expected-error {{expected expression}} expected-error 2 {{expected ')'}} expected-note 2 {{to match this '('}} + #pragma omp parallel masked taskloop simd linear (val(argc, // expected-error {{expected expression}} expected-error 2 {{expected ')'}} expected-note 2 {{to match this '('}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel masked taskloop simd linear (argc > 0 ? argv[1] : argv[2]) // expected-error {{expected variable name}} for (int k = 0; k < argc; ++k) ++k; @@ -149,17 +151,25 @@ template int foomain(I argc, C **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel masked taskloop simd linear (S1) // expected-error {{'S1' does not refer to a value}} for (int k = 0; k < argc; ++k) ++k; +#if defined(OMP52) + // omp52-error@+3{{step simple modifier is exclusive and can't be use with 'val', 'uval' or 'ref' modifier}} + // expected-error@+2 {{linear variable with incomplete type 'S1'}} + // expected-error@+1 {{argument of a linear clause should be of integral or pointer type, not 'S2'}} + #pragma omp parallel masked taskloop simd linear (a, b: val, B::ib) +#else + // omp52-error@+3 {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} // expected-error@+2 {{linear variable with incomplete type 'S1'}} // expected-error@+1 {{argument of a linear clause should be of integral or pointer type, not 'S2'}} #pragma omp parallel masked taskloop simd linear (val(a, b):B::ib) +#endif for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel masked taskloop simd linear (argv[1]) // expected-error {{expected variable name}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel masked taskloop simd linear(ref(e, g)) // expected-error 2 {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'ref'}} + #pragma omp parallel masked taskloop simd linear(ref(e, g)) // expected-error 2 {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'ref'}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel masked taskloop simd linear(h, z) // expected-error {{threadprivate or thread local variable cannot be linear}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel masked taskloop simd linear(uval(i)) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} + #pragma omp parallel masked taskloop simd linear(uval(i)) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel { @@ -168,9 +178,9 @@ template int foomain(I argc, C **argv) { #pragma omp parallel masked taskloop simd allocate(omp_thread_mem_alloc: v) linear(v:i) // expected-warning {{allocator with the 'thread' trait access has unspecified behavior on 'parallel masked taskloop simd' directive}} for (int k = 0; k < argc; ++k) { i = k; v += i; } } - #pragma omp parallel masked taskloop simd linear(ref(j)) + #pragma omp parallel masked taskloop simd linear(ref(j)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel masked taskloop simd linear(uval(j)) + #pragma omp parallel masked taskloop simd linear(uval(j)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; int v = 0; #pragma omp parallel masked taskloop simd linear(v:j) @@ -192,13 +202,13 @@ void linear_modifiers(int argc) { int &f = argc; #pragma omp parallel masked taskloop simd linear(f) for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel masked taskloop simd linear(val(f)) + #pragma omp parallel masked taskloop simd linear(val(f)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel masked taskloop simd linear(uval(f)) + #pragma omp parallel masked taskloop simd linear(uval(f)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel masked taskloop simd linear(ref(f)) + #pragma omp parallel masked taskloop simd linear(ref(f)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel masked taskloop simd linear(foo(f)) // expected-error {{expected one of 'ref', val' or 'uval' modifiers}} + #pragma omp parallel masked taskloop simd linear(foo(f)) // expected-error {{expected one of 'ref', val' or 'uval' modifiers}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; } @@ -224,9 +234,9 @@ int main(int argc, char **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel masked taskloop simd linear (val // expected-error {{use of undeclared identifier 'val'}} expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel masked taskloop simd linear (ref()) // expected-error {{expected expression}} + #pragma omp parallel masked taskloop simd linear (ref()) // expected-error {{expected expression}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel masked taskloop simd linear (foo()) // expected-error {{expected expression}} + #pragma omp parallel masked taskloop simd linear (foo()) // expected-error {{expected expression}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel masked taskloop simd linear (argc // expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; @@ -244,6 +254,7 @@ int main(int argc, char **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel masked taskloop simd linear (argv[1]) // expected-error {{expected variable name}} for (int k = 0; k < argc; ++k) ++k; + // omp52-error@+3 {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} // expected-error@+2 {{argument of a linear clause should be of integral or pointer type, not 'S4'}} // expected-error@+1 {{argument of a linear clause should be of integral or pointer type, not 'S5'}} #pragma omp parallel masked taskloop simd linear(val(e, g)) @@ -253,17 +264,36 @@ int main(int argc, char **argv) { #pragma omp parallel { int i; - #pragma omp parallel masked taskloop simd linear(val(i)) + #pragma omp parallel masked taskloop simd linear(val(i)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel masked taskloop simd linear(uval(i) : 4) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} +#ifdef OMP52 + #pragma omp parallel masked taskloop simd linear(i : uval, step(4)) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} +#else + #pragma omp parallel masked taskloop simd linear(uval(i) : 4) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} +#endif for (int k = 0; k < argc; ++k) { ++k; i += 4; } } - #pragma omp parallel masked taskloop simd linear(ref(j)) - for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp parallel masked taskloop simd linear(j: ref) +#else + #pragma omp parallel masked taskloop simd linear(ref(j)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} +#endif + for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp parallel masked taskloop simd linear(i: step(1), step(2)) // omp52-error {{multiple 'step size' found in linear clause}} +#else #pragma omp parallel masked taskloop simd linear(i) +#endif + for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp parallel masked taskloop simd linear(j: step()) // omp52-error 2 {{expected expression}} for (int k = 0; k < argc; ++k) ++k; + #pragma omp parallel masked taskloop simd linear(j: pval) // omp52-error {{use of undeclared identifier 'pval'}} + for (int k = 0; k < argc; ++k) ++k; + #pragma omp parallel masked taskloop simd linear(i: val, step(2 // omp52-error {{expected ')' or ',' after 'step expression'}} omp52-error 2 {{expected ')'}} omp52-note 2 {{to match this '('}} + for (int k = 0; k < argc; ++k) ++k; +#endif foomain(argc,argv); // expected-note {{in instantiation of function template specialization 'foomain' requested here}} return 0; } - diff --git a/clang/test/OpenMP/parallel_master_ast_print.cpp b/clang/test/OpenMP/parallel_master_ast_print.cpp index c6cba2d2b5e3c..c2d3a6a25b9be 100644 --- a/clang/test/OpenMP/parallel_master_ast_print.cpp +++ b/clang/test/OpenMP/parallel_master_ast_print.cpp @@ -1,10 +1,10 @@ -// RUN: %clang_cc1 -verify -fopenmp -ast-print %s | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -ast-print %s | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print | FileCheck %s +// RUN: %clang_cc1 -fopenmp -std=c++11 -include-pch %t -fsyntax-only -verify -Wno-vla %s -ast-print | FileCheck %s -// RUN: %clang_cc1 -verify -fopenmp-simd -ast-print %s | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -ast-print %s | FileCheck %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print | FileCheck %s +// RUN: %clang_cc1 -fopenmp-simd -std=c++11 -include-pch %t -fsyntax-only -verify -Wno-vla %s -ast-print | FileCheck %s // expected-no-diagnostics #ifndef HEADER diff --git a/clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp index 75b99b1a00318..5e3bcae3acacc 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp @@ -1,17 +1,17 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY3 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY4 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY3 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY4 %s // expected-no-diagnostics #ifndef ARRAY diff --git a/clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp index b6c140a331e43..7dc775b5ac7c8 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp @@ -1,19 +1,19 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLOOP -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLOOP -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLOOP -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLOOP -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #if !defined(ARRAY) && !defined(LOOP) diff --git a/clang/test/OpenMP/parallel_master_taskloop_private_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_private_codegen.cpp index 6d5e7c1219911..9ecc4747df66b 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_private_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_private_codegen.cpp @@ -1,16 +1,16 @@ -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/parallel_master_taskloop_reduction_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_reduction_codegen.cpp index ea2e82c5e6b70..1c9271c3224cb 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_reduction_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_reduction_codegen.cpp @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 -fopenmp -x c++ %s -verify -debug-info-kind=limited -emit-llvm -o - -triple powerpc64le-unknown-linux-gnu -std=c++98 -fnoopenmp-use-tls | FileCheck %s +// RUN: %clang_cc1 -fopenmp -x c++ %s -verify -Wno-vla -debug-info-kind=limited -emit-llvm -o - -triple powerpc64le-unknown-linux-gnu -std=c++98 -fnoopenmp-use-tls | FileCheck %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ %s -verify -debug-info-kind=limited -emit-llvm -o - -triple powerpc64le-unknown-linux-gnu -std=c++98 -fnoopenmp-use-tls | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ %s -verify -Wno-vla -debug-info-kind=limited -emit-llvm -o - -triple powerpc64le-unknown-linux-gnu -std=c++98 -fnoopenmp-use-tls | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/parallel_master_taskloop_simd_ast_print.cpp b/clang/test/OpenMP/parallel_master_taskloop_simd_ast_print.cpp index a85c232265d99..441e16c268b1f 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_simd_ast_print.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_simd_ast_print.cpp @@ -68,7 +68,7 @@ int main(int argc, char **argv) { #pragma omp taskgroup task_reduction(+: d) #pragma omp parallel master taskloop simd if(parallel: a) default(none) shared(a, b, argc) final(b) priority(5) num_tasks(argc) reduction(*: g) aligned(argv: 8) linear(c:b) // CHECK-NEXT: #pragma omp taskgroup task_reduction(+: d) - // CHECK-NEXT: #pragma omp parallel master taskloop simd if(parallel: a) default(none) shared(a,b,argc) final(b) priority(5) num_tasks(argc) reduction(*: g) aligned(argv: 8) linear(c: b) + // CHECK-NEXT: #pragma omp parallel master taskloop simd if(parallel: a) default(none) shared(a,b,argc) final(b) priority(5) num_tasks(argc) reduction(*: g) aligned(argv: 8) linear(c: step(b)) for (int i = 0; i < 2; ++i) a = 2; // CHECK-NEXT: for (int i = 0; i < 2; ++i) diff --git a/clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp index b938758b051a2..e5ce73f6ee045 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp @@ -1,17 +1,17 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY3 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY4 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY3 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY4 %s // expected-no-diagnostics #ifndef ARRAY diff --git a/clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp index 1339272bb315e..cd5ee03eb6352 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp @@ -1,19 +1,19 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLOOP -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLOOP -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLOOP -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLOOP -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK12 // expected-no-diagnostics #if !defined(ARRAY) && !defined(LOOP) diff --git a/clang/test/OpenMP/parallel_master_taskloop_simd_linear_messages.cpp b/clang/test/OpenMP/parallel_master_taskloop_simd_linear_messages.cpp index 45cad614a7317..2be29fdc6b929 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_simd_linear_messages.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_simd_linear_messages.cpp @@ -1,6 +1,8 @@ // RUN: %clang_cc1 -verify -fopenmp %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp -fopenmp-version=52 -DOMP52 %s -Wuninitialized // RUN: %clang_cc1 -verify -fopenmp-simd %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp-simd -fopenmp-version=52 -DOMP52 %s -Wuninitialized typedef void **omp_allocator_handle_t; extern const omp_allocator_handle_t omp_null_allocator; @@ -14,8 +16,8 @@ extern const omp_allocator_handle_t omp_pteam_mem_alloc; extern const omp_allocator_handle_t omp_thread_mem_alloc; void xxx(int argc) { - int i, lin, step; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step' to silence this warning}} -#pragma omp parallel master taskloop simd linear(i, lin : step) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step' is uninitialized when used here}} + int i, lin, step_sz; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step_sz' to silence this warning}} +#pragma omp parallel master taskloop simd linear(i, lin : step_sz) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step_sz' is uninitialized when used here}} for (i = 0; i < 10; ++i) ; } @@ -129,11 +131,11 @@ template int foomain(I argc, C **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel master taskloop simd linear (val // expected-error {{use of undeclared identifier 'val'}} expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel master taskloop simd linear (uval( // expected-error {{expected expression}} expected-error 2 {{expected ')'}} expected-note 2 {{to match this '('}} + #pragma omp parallel master taskloop simd linear (uval( // expected-error {{expected expression}} expected-error 2 {{expected ')'}} expected-note 2 {{to match this '('}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel master taskloop simd linear (ref() // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} + #pragma omp parallel master taskloop simd linear (ref() // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel master taskloop simd linear (foo() // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} + #pragma omp parallel master taskloop simd linear (foo() // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel master taskloop simd linear () // expected-error {{expected expression}} for (int k = 0; k < argc; ++k) ++k; @@ -141,7 +143,7 @@ template int foomain(I argc, C **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel master taskloop simd linear (val argc // expected-error {{use of undeclared identifier 'val'}} expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel master taskloop simd linear (val(argc, // expected-error {{expected expression}} expected-error 2 {{expected ')'}} expected-note 2 {{to match this '('}} + #pragma omp parallel master taskloop simd linear (val(argc, // expected-error {{expected expression}} expected-error 2 {{expected ')'}} expected-note 2 {{to match this '('}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel master taskloop simd linear (argc > 0 ? argv[1] : argv[2]) // expected-error {{expected variable name}} for (int k = 0; k < argc; ++k) ++k; @@ -149,17 +151,25 @@ template int foomain(I argc, C **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel master taskloop simd linear (S1) // expected-error {{'S1' does not refer to a value}} for (int k = 0; k < argc; ++k) ++k; +#if defined(OMP52) + // omp52-error@+3{{step simple modifier is exclusive and can't be use with 'val', 'uval' or 'ref' modifier}} + // expected-error@+2 {{linear variable with incomplete type 'S1'}} + // expected-error@+1 {{argument of a linear clause should be of integral or pointer type, not 'S2'}} + #pragma omp parallel master taskloop simd linear (a, b: val, B::ib) +#else + // omp52-error @+3{{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} // expected-error@+2 {{linear variable with incomplete type 'S1'}} // expected-error@+1 {{argument of a linear clause should be of integral or pointer type, not 'S2'}} #pragma omp parallel master taskloop simd linear (val(a, b):B::ib) +#endif for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel master taskloop simd linear (argv[1]) // expected-error {{expected variable name}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel master taskloop simd linear(ref(e, g)) // expected-error 2 {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'ref'}} + #pragma omp parallel master taskloop simd linear(ref(e, g)) // expected-error 2 {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'ref'}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel master taskloop simd linear(h, z) // expected-error {{threadprivate or thread local variable cannot be linear}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel master taskloop simd linear(uval(i)) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} + #pragma omp parallel master taskloop simd linear(uval(i)) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel { @@ -168,9 +178,9 @@ template int foomain(I argc, C **argv) { #pragma omp parallel master taskloop simd allocate(omp_thread_mem_alloc: v) linear(v:i) // expected-warning {{allocator with the 'thread' trait access has unspecified behavior on 'parallel master taskloop simd' directive}} for (int k = 0; k < argc; ++k) { i = k; v += i; } } - #pragma omp parallel master taskloop simd linear(ref(j)) + #pragma omp parallel master taskloop simd linear(ref(j)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel master taskloop simd linear(uval(j)) + #pragma omp parallel master taskloop simd linear(uval(j)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; int v = 0; #pragma omp parallel master taskloop simd linear(v:j) @@ -192,13 +202,13 @@ void linear_modifiers(int argc) { int &f = argc; #pragma omp parallel master taskloop simd linear(f) for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel master taskloop simd linear(val(f)) + #pragma omp parallel master taskloop simd linear(val(f)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel master taskloop simd linear(uval(f)) + #pragma omp parallel master taskloop simd linear(uval(f)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel master taskloop simd linear(ref(f)) + #pragma omp parallel master taskloop simd linear(ref(f)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel master taskloop simd linear(foo(f)) // expected-error {{expected one of 'ref', val' or 'uval' modifiers}} + #pragma omp parallel master taskloop simd linear(foo(f)) // expected-error {{expected one of 'ref', val' or 'uval' modifiers}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; } @@ -224,9 +234,9 @@ int main(int argc, char **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel master taskloop simd linear (val // expected-error {{use of undeclared identifier 'val'}} expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel master taskloop simd linear (ref()) // expected-error {{expected expression}} + #pragma omp parallel master taskloop simd linear (ref()) // expected-error {{expected expression}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp parallel master taskloop simd linear (foo()) // expected-error {{expected expression}} + #pragma omp parallel master taskloop simd linear (foo()) // expected-error {{expected expression}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel master taskloop simd linear (argc // expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; @@ -244,6 +254,7 @@ int main(int argc, char **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel master taskloop simd linear (argv[1]) // expected-error {{expected variable name}} for (int k = 0; k < argc; ++k) ++k; + // omp52-error@+3 {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} // expected-error@+2 {{argument of a linear clause should be of integral or pointer type, not 'S4'}} // expected-error@+1 {{argument of a linear clause should be of integral or pointer type, not 'S5'}} #pragma omp parallel master taskloop simd linear(val(e, g)) @@ -253,15 +264,35 @@ int main(int argc, char **argv) { #pragma omp parallel { int i; - #pragma omp parallel master taskloop simd linear(val(i)) + #pragma omp parallel master taskloop simd linear(val(i)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp parallel master taskloop simd linear(i : uval, step(4)) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} +#else #pragma omp parallel master taskloop simd linear(uval(i) : 4) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} +#endif for (int k = 0; k < argc; ++k) { ++k; i += 4; } } - #pragma omp parallel master taskloop simd linear(ref(j)) - for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp parallel master taskloop simd linear(j: ref) +#else + #pragma omp parallel master taskloop simd linear(ref(j)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} +#endif + for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp parallel master taskloop simd linear(i: step(1), step(2)) // omp52-error {{multiple 'step size' found in linear clause}} +#else #pragma omp parallel master taskloop simd linear(i) +#endif + for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp parallel master taskloop simd linear(j: step()) // omp52-error 2 {{expected expression}} + for (int k = 0; k < argc; ++k) ++k; + #pragma omp parallel master taskloop simd linear(j: pval) // omp52-error {{use of undeclared identifier 'pval'}} + for (int k = 0; k < argc; ++k) ++k; + #pragma omp parallel master taskloop simd linear(i: val, step(2 // omp52-error {{expected ')' or ',' after 'step expression'}} omp52-error 2 {{expected ')'}} omp52-note 2 {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; +#endif foomain(argc,argv); // expected-note {{in instantiation of function template specialization 'foomain' requested here}} return 0; diff --git a/clang/test/OpenMP/parallel_master_taskloop_simd_private_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_simd_private_codegen.cpp index d58c01d756647..e586b13bf9ba9 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_simd_private_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_simd_private_codegen.cpp @@ -1,16 +1,16 @@ -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/parallel_master_taskloop_simd_reduction_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_simd_reduction_codegen.cpp index 7a0ea6bbbbf15..e193540158421 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_simd_reduction_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_simd_reduction_codegen.cpp @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 -fopenmp -x c++ %s -verify -debug-info-kind=limited -emit-llvm -o - -triple powerpc64le-unknown-linux-gnu -std=c++98 -fnoopenmp-use-tls | FileCheck %s +// RUN: %clang_cc1 -fopenmp -x c++ %s -verify -Wno-vla -debug-info-kind=limited -emit-llvm -o - -triple powerpc64le-unknown-linux-gnu -std=c++98 -fnoopenmp-use-tls | FileCheck %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ %s -verify -debug-info-kind=limited -emit-llvm -o - -triple powerpc64le-unknown-linux-gnu -std=c++98 -fnoopenmp-use-tls | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ %s -verify -Wno-vla -debug-info-kind=limited -emit-llvm -o - -triple powerpc64le-unknown-linux-gnu -std=c++98 -fnoopenmp-use-tls | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/scope_ast_print.cpp b/clang/test/OpenMP/scope_ast_print.cpp index c69908980d229..c5c3a29738a72 100644 --- a/clang/test/OpenMP/scope_ast_print.cpp +++ b/clang/test/OpenMP/scope_ast_print.cpp @@ -81,8 +81,8 @@ int template_test() { //DUMP: BuiltinType {{.*}}'double' //DUMP: OMPScopeDirective //DUMP: OMPPrivateClause -//DUMP: DeclRefExpr {{.*}}'double':'double' lvalue Var {{.*}} 'a' 'double':'double' +//DUMP: DeclRefExpr {{.*}}'double' lvalue Var {{.*}} 'a' 'double' //DUMP: OMPReductionClause -//DUMP: DeclRefExpr {{.*}}'double':'double' lvalue Var {{.*}} 'b' 'double':'double' +//DUMP: DeclRefExpr {{.*}}'double' lvalue Var {{.*}} 'b' 'double' //PRINT: #pragma omp scope private(a) reduction(*: b) #endif // HEADER diff --git a/clang/test/OpenMP/simd_ast_print.cpp b/clang/test/OpenMP/simd_ast_print.cpp index 7f98d351e7edc..057f1e7c03c0e 100644 --- a/clang/test/OpenMP/simd_ast_print.cpp +++ b/clang/test/OpenMP/simd_ast_print.cpp @@ -7,6 +7,9 @@ // RUN: %clang_cc1 -verify -fopenmp -ast-print %s -DOMP51 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP51 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -emit-pch -o %t %s -DOMP51 // RUN: %clang_cc1 -fopenmp -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -DOMP51 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP51 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=52 -ast-print %s -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=52 -x c++ -std=c++11 -emit-pch -o %t %s -DOMP52 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=52 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -ast-print %s | FileCheck %s --check-prefix=CHECK --check-prefix=OMP45 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -emit-pch -o %t %s @@ -18,6 +21,10 @@ // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -emit-pch -o %t %s -DOMP51 // RUN: %clang_cc1 -fopenmp-simd -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -DOMP51 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP51 // expected-no-diagnostics +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=52 -ast-print %s -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=52 -x c++ -std=c++11 -emit-pch -o %t %s -DOMP52 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=52 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 +// expected-no-diagnostics #ifndef HEADER #define HEADER @@ -80,11 +87,15 @@ template T reduct(T* arr, N num) { N i; N ind; N myind; - N &ref = i; + N &r = i; T sum = (T)0; // CHECK: T sum = (T)0; -#pragma omp simd private(myind, g_ind), linear(ind), aligned(arr), linear(uval(ref)) -// CHECK-NEXT: #pragma omp simd private(myind,g_ind) linear(ind) aligned(arr) linear(uval(ref)) +#ifdef OMP52 +#pragma omp simd private(myind, g_ind), linear(ind), aligned(arr), linear(r: uval) +#else +#pragma omp simd private(myind, g_ind), linear(ind), aligned(arr), linear(uval(r)) +#endif +// CHECK-NEXT: #pragma omp simd private(myind,g_ind) linear(ind) aligned(arr) linear(r: uval) for (i = 0; i < num; ++i) { myind = ind; T cur = arr[myind]; @@ -101,13 +112,17 @@ template struct S { T res; T val; T lin = 0; - T &ref = res; + T &r = res; // CHECK: T res; // CHECK: T val; // CHECK: T lin = 0; -// CHECK: T &ref = res; - #pragma omp simd allocate(res) private(val) safelen(7) linear(lin : -5) lastprivate(res) simdlen(5) linear(ref(ref)) -// CHECK-NEXT: #pragma omp simd allocate(res) private(val) safelen(7) linear(lin: -5) lastprivate(res) simdlen(5) linear(ref(ref)) +// CHECK: T &r = res; +#ifdef OMP52 + #pragma omp simd allocate(res) private(val) safelen(7) linear(lin : step(-5)) lastprivate(res) simdlen(5) linear(r: ref) +#else + #pragma omp simd allocate(res) private(val) safelen(7) linear(lin : -5) lastprivate(res) simdlen(5) linear(ref(r)) +#endif +// CHECK-NEXT: #pragma omp simd allocate(res) private(val) safelen(7) linear(lin: step(-5)) lastprivate(res) simdlen(5) linear(r: ref) for (T i = 7; i < m_a; ++i) { val = v[i-7] + m_a; res = val; @@ -148,7 +163,7 @@ template struct S2 { // CHECK: template<> struct S2<4> { // CHECK-NEXT: static void func(int n, float *a, float *b, float *c) { // CHECK-NEXT: int k1 = 0, k2 = 0; -// CHECK-NEXT: #pragma omp simd safelen(4) linear(k1,k2: 4) aligned(a: 4) simdlen(4) allocate(k1) +// CHECK-NEXT: #pragma omp simd safelen(4) linear(k1,k2: step(4)) aligned(a: 4) simdlen(4) allocate(k1) // CHECK-NEXT: for (int i = 0; i < n; i++) { // CHECK-NEXT: c[i] = a[i] + b[i]; // CHECK-NEXT: c[k1] = a[k1] + b[k1]; @@ -161,7 +176,7 @@ template struct S2 { int main (int argc, char **argv) { int b = argc, c, d, e, f, g; int k1=0,k2=0; - int &ref = b; + int &r = b; static int *a; // CHECK: static int *a; #pragma omp simd @@ -169,7 +184,10 @@ int main (int argc, char **argv) { for (int i=0; i < 2; ++i)*a=2; // CHECK-NEXT: for (int i = 0; i < 2; ++i) // CHECK-NEXT: *a = 2; -#ifdef OMP51 +#ifdef OMP52 +#pragma omp simd private(argc, b),lastprivate(d,f) collapse(2) aligned(a : 4) if(simd:a) nontemporal(argc, c, d) lastprivate(conditional: e, f) order(unconstrained:concurrent) +// OMP52-NEXT: #pragma omp simd private(argc,b) lastprivate(d,f) collapse(2) aligned(a: 4) if(simd: a) nontemporal(argc,c,d) lastprivate(conditional: e,f) order(unconstrained: concurrent) +#elif OMP51 #pragma omp simd private(argc, b),lastprivate(d,f) collapse(2) aligned(a : 4) if(simd:a) nontemporal(argc, c, d) lastprivate(conditional: e, f) order(unconstrained:concurrent) // OMP51-NEXT: #pragma omp simd private(argc,b) lastprivate(d,f) collapse(2) aligned(a: 4) if(simd: a) nontemporal(argc,c,d) lastprivate(conditional: e,f) order(unconstrained: concurrent) #elif OMP5 @@ -192,13 +210,16 @@ int main (int argc, char **argv) { // CHECK-NEXT: foo(); const int CLEN = 4; // CHECK-NEXT: const int CLEN = 4; -#ifdef OMP5 - #pragma omp simd aligned(a:CLEN) linear(a:CLEN) safelen(CLEN) collapse( 1 ) simdlen(CLEN) linear(val(ref): CLEN) if(a) -// OMP50-NEXT: #pragma omp simd aligned(a: CLEN) linear(a: CLEN) safelen(CLEN) collapse(1) simdlen(CLEN) linear(val(ref): CLEN) if(a) +#ifdef OMP52 + #pragma omp simd aligned(a:CLEN) linear(a: step(CLEN)) safelen(CLEN) collapse( 1 ) simdlen(CLEN) linear(r: val, step(CLEN)) if(a) +#elif OMP5 + #pragma omp simd aligned(a:CLEN) linear(a:CLEN) safelen(CLEN) collapse( 1 ) simdlen(CLEN) linear(val(r): CLEN) if(a) +// OMP50-NEXT: #pragma omp simd aligned(a: CLEN) linear(a: step(CLEN)) safelen(CLEN) collapse(1) simdlen(CLEN) linear(r: val, step(CLEN)) if(a) #else - #pragma omp simd aligned(a:CLEN) linear(a:CLEN) safelen(CLEN) collapse( 1 ) simdlen(CLEN) linear(val(ref): CLEN) -// OMP45-NEXT: #pragma omp simd aligned(a: CLEN) linear(a: CLEN) safelen(CLEN) collapse(1) simdlen(CLEN) linear(val(ref): CLEN) -// OMP51-NEXT: #pragma omp simd aligned(a: CLEN) linear(a: CLEN) safelen(CLEN) collapse(1) simdlen(CLEN) linear(val(ref): CLEN) + #pragma omp simd aligned(a:CLEN) linear(a:CLEN) safelen(CLEN) collapse( 1 ) simdlen(CLEN) linear(val(r): CLEN) +// OMP45-NEXT: #pragma omp simd aligned(a: CLEN) linear(a: step(CLEN)) safelen(CLEN) collapse(1) simdlen(CLEN) linear(r: val, step(CLEN)) +// OMP51-NEXT: #pragma omp simd aligned(a: CLEN) linear(a: step(CLEN)) safelen(CLEN) collapse(1) simdlen(CLEN) linear(r: val, step(CLEN)) +// OMP52-NEXT: #pragma omp simd aligned(a: CLEN) linear(a: step(CLEN)) safelen(CLEN) collapse(1) simdlen(CLEN) linear(r: val, step(CLEN)) #endif // OMP5 for (int i = 0; i < 10; ++i)foo(); // CHECK-NEXT: for (int i = 0; i < 10; ++i) diff --git a/clang/test/OpenMP/simd_linear_messages.cpp b/clang/test/OpenMP/simd_linear_messages.cpp index 92637fbc880d0..a19fad9d7718a 100644 --- a/clang/test/OpenMP/simd_linear_messages.cpp +++ b/clang/test/OpenMP/simd_linear_messages.cpp @@ -1,11 +1,13 @@ // RUN: %clang_cc1 -verify -fopenmp %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp -fopenmp-version=52 -DOMP52 %s -Wuninitialized // RUN: %clang_cc1 -verify -fopenmp-simd %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp-simd -fopenmp-version=52 -DOMP52 %s -Wuninitialized extern int omp_default_mem_alloc; void xxx(int argc) { - int i, lin, step; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step' to silence this warning}} -#pragma omp simd linear(i, lin : step) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step' is uninitialized when used here}} + int i, lin, step_sz; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step_sz' to silence this warning}} +#pragma omp simd linear(i, lin : step_sz) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step_sz' is uninitialized when used here}} for (i = 0; i < 10; ++i) ; } @@ -119,11 +121,11 @@ template int foomain(I argc, C **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp simd linear (val // expected-error {{use of undeclared identifier 'val'}} expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp simd linear (uval( // expected-error {{expected expression}} expected-error 2 {{expected ')'}} expected-note 2 {{to match this '('}} + #pragma omp simd linear (uval( // expected-error {{expected expression}} expected-error 2 {{expected ')'}} expected-note 2 {{to match this '('}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp simd linear (ref() // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} + #pragma omp simd linear (ref() // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp simd linear (foo() // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} + #pragma omp simd linear (foo() // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp simd linear () // expected-error {{expected expression}} for (int k = 0; k < argc; ++k) ++k; @@ -131,7 +133,7 @@ template int foomain(I argc, C **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp simd linear (val argc // expected-error {{use of undeclared identifier 'val'}} expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp simd linear (val(argc, // expected-error {{expected expression}} expected-error 2 {{expected ')'}} expected-note 2 {{to match this '('}} + #pragma omp simd linear (val(argc, // expected-error {{expected expression}} expected-error 2 {{expected ')'}} expected-note 2 {{to match this '('}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp simd linear (argc > 0 ? argv[1] : argv[2]) // expected-error {{expected variable name}} for (int k = 0; k < argc; ++k) ++k; @@ -139,17 +141,25 @@ template int foomain(I argc, C **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp simd linear (S1) // expected-error {{'S1' does not refer to a value}} for (int k = 0; k < argc; ++k) ++k; +#if defined(OMP52) + // omp52-error@+3{{step simple modifier is exclusive and can't be use with 'val', 'uval' or 'ref' modifier}} + // expected-error@+2 {{linear variable with incomplete type 'S1'}} + // expected-error@+1 {{argument of a linear clause should be of integral or pointer type, not 'S2'}} + #pragma omp simd linear (a, b: val, B::ib) +#else + // omp52-error@+3 {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} // expected-error@+2 {{linear variable with incomplete type 'S1'}} // expected-error@+1 {{argument of a linear clause should be of integral or pointer type, not 'S2'}} #pragma omp simd linear (val(a, b):B::ib) +#endif for (int k = 0; k < argc; ++k) ++k; #pragma omp simd linear (argv[1]) // expected-error {{expected variable name}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp simd linear(ref(e, g)) // expected-error 2 {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'ref'}} + #pragma omp simd linear(ref(e, g)) // expected-error 2 {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'ref'}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp simd linear(h, z) // expected-error {{threadprivate or thread local variable cannot be linear}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp simd linear(uval(i)) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} + #pragma omp simd linear(uval(i)) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel { @@ -158,9 +168,9 @@ template int foomain(I argc, C **argv) { #pragma omp simd linear(v:i) for (int k = 0; k < argc; ++k) { i = k; v += i; } } - #pragma omp simd linear(ref(j)) + #pragma omp simd linear(ref(j)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp simd linear(uval(j)) + #pragma omp simd linear(uval(j)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; int v = 0; #pragma omp simd linear(v:j) @@ -182,13 +192,13 @@ void linear_modifiers(int argc) { int &f = argc; #pragma omp simd linear(f) for (int k = 0; k < argc; ++k) ++k; - #pragma omp simd linear(val(f)) + #pragma omp simd linear(val(f)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp simd linear(uval(f)) + #pragma omp simd linear(uval(f)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp simd linear(ref(f)) + #pragma omp simd linear(ref(f)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp simd linear(foo(f)) // expected-error {{expected one of 'ref', val' or 'uval' modifiers}} + #pragma omp simd linear(foo(f)) // expected-error {{expected one of 'ref', val' or 'uval' modifiers}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; } @@ -214,9 +224,9 @@ int main(int argc, char **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp simd linear (val // expected-error {{use of undeclared identifier 'val'}} expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp simd linear (ref()) // expected-error {{expected expression}} + #pragma omp simd linear (ref()) // expected-error {{expected expression}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp simd linear (foo()) // expected-error {{expected expression}} + #pragma omp simd linear (foo()) // expected-error {{expected expression}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp simd linear (argc // expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; @@ -234,6 +244,7 @@ int main(int argc, char **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp simd linear (argv[1]) // expected-error {{expected variable name}} for (int k = 0; k < argc; ++k) ++k; + // omp52-error@+3 {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} // expected-error@+2 {{argument of a linear clause should be of integral or pointer type, not 'S4'}} // expected-error@+1 {{argument of a linear clause should be of integral or pointer type, not 'S5'}} #pragma omp simd linear(val(e, g)) @@ -243,17 +254,38 @@ int main(int argc, char **argv) { #pragma omp parallel { int i; - #pragma omp simd linear(val(i)) + #pragma omp simd linear(val(i)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp simd linear(uval(i) : 4) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} +#ifdef OMP52 + #pragma omp simd linear(i : uval, step(4)) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} +#else + #pragma omp simd linear(uval(i) : 4) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} +#endif for (int k = 0; k < argc; ++k) { ++k; i += 4; } } - #pragma omp simd linear(ref(j)) - for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp simd linear(j: ref) +#else + #pragma omp simd linear(ref(j)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} +#endif + for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp simd linear(i: step(1), step(2)) // omp52-error {{multiple 'step size' found in linear clause}} +#else #pragma omp simd linear(i) +#endif + for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp simd linear(i: val, val) // omp52-error {{multiple 'linear modifier' found in linear clause}} for (int k = 0; k < argc; ++k) ++k; + #pragma omp simd linear(j: step()) // omp52-error 2 {{expected expression}} + for (int k = 0; k < argc; ++k) ++k; + #pragma omp simd linear(j: pval) // omp52-error {{use of undeclared identifier 'pval'}} + for (int k = 0; k < argc; ++k) ++k; + #pragma omp simd linear(i: val, step(2 // omp52-error {{expected ')' or ',' after 'step expression'}} omp52-error 2 {{expected ')'}} omp52-note 2 {{to match this '('}} + for (int k = 0; k < argc; ++k) ++k; +#endif foomain(argc,argv); // expected-note {{in instantiation of function template specialization 'foomain' requested here}} return 0; } - diff --git a/clang/test/OpenMP/single_codegen.cpp b/clang/test/OpenMP/single_codegen.cpp index f32bc7e31c644..0bc2ba2bcc620 100644 --- a/clang/test/OpenMP/single_codegen.cpp +++ b/clang/test/OpenMP/single_codegen.cpp @@ -1,21 +1,21 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -verify -fopenmp -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK2 // RUN: %clang_cc1 -fopenmp -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -fopenmp -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -std=c++11 -fopenmp -fnoopenmp-use-tls -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -verify -fopenmp -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -std=c++11 -fopenmp -fnoopenmp-use-tls -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -std=c++11 -fopenmp-simd -fnoopenmp-use-tls -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -std=c++11 -fopenmp-simd -fnoopenmp-use-tls -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef ARRAY #ifndef HEADER diff --git a/clang/test/OpenMP/target_ast_print.cpp b/clang/test/OpenMP/target_ast_print.cpp index f580ff3257e39..d3daed053cc2e 100644 --- a/clang/test/OpenMP/target_ast_print.cpp +++ b/clang/test/OpenMP/target_ast_print.cpp @@ -4,13 +4,13 @@ #ifndef HEADER #define HEADER -// RUN: %clang_cc1 -DOMP45 -verify -fopenmp -fopenmp-version=45 -ast-print %s | FileCheck %s --check-prefix=OMP45 +// RUN: %clang_cc1 -DOMP45 -verify -Wno-vla -fopenmp -fopenmp-version=45 -ast-print %s | FileCheck %s --check-prefix=OMP45 // RUN: %clang_cc1 -DOMP45 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -emit-pch -o %t %s -// RUN: %clang_cc1 -DOMP45 -fopenmp -fopenmp-version=45 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print | FileCheck %s --check-prefix=OMP45 +// RUN: %clang_cc1 -DOMP45 -fopenmp -fopenmp-version=45 -std=c++11 -include-pch %t -fsyntax-only -verify -Wno-vla %s -ast-print | FileCheck %s --check-prefix=OMP45 -// RUN: %clang_cc1 -DOMP45 -verify -fopenmp-simd -fopenmp-version=45 -ast-print %s | FileCheck %s --check-prefix=OMP45 +// RUN: %clang_cc1 -DOMP45 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -ast-print %s | FileCheck %s --check-prefix=OMP45 // RUN: %clang_cc1 -DOMP45 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -emit-pch -o %t %s -// RUN: %clang_cc1 -DOMP45 -fopenmp-simd -fopenmp-version=45 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print | FileCheck %s --check-prefix=OMP45 +// RUN: %clang_cc1 -DOMP45 -fopenmp-simd -fopenmp-version=45 -std=c++11 -include-pch %t -fsyntax-only -verify -Wno-vla %s -ast-print | FileCheck %s --check-prefix=OMP45 #ifdef OMP45 void foo() {} @@ -40,7 +40,7 @@ T tmain(T argc, T *argv) { {always++;i++;} #pragma omp target map(close,alloc: i) foo(); -#pragma omp target map(close from: i) +#pragma omp target map(close, from: i) foo(); #pragma omp target map(close) {close++;} @@ -335,21 +335,21 @@ int main (int argc, char **argv) { #ifdef OMP5 ///==========================================================================/// -// RUN: %clang_cc1 -DOMP5 -verify -fopenmp -fopenmp-version=50 -ast-print %s | FileCheck %s --check-prefix OMP5 +// RUN: %clang_cc1 -DOMP5 -verify -Wno-vla -fopenmp -fopenmp-version=50 -ast-print %s | FileCheck %s --check-prefix OMP5 // RUN: %clang_cc1 -DOMP5 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -emit-pch -o %t %s -// RUN: %clang_cc1 -DOMP5 -fopenmp -fopenmp-version=50 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print | FileCheck %s --check-prefix OMP5 +// RUN: %clang_cc1 -DOMP5 -fopenmp -fopenmp-version=50 -std=c++11 -include-pch %t -fsyntax-only -verify -Wno-vla %s -ast-print | FileCheck %s --check-prefix OMP5 -// RUN: %clang_cc1 -DOMP5 -verify -fopenmp-simd -fopenmp-version=50 -ast-print %s | FileCheck %s --check-prefix OMP5 +// RUN: %clang_cc1 -DOMP5 -verify -Wno-vla -fopenmp-simd -fopenmp-version=50 -ast-print %s | FileCheck %s --check-prefix OMP5 // RUN: %clang_cc1 -DOMP5 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -emit-pch -o %t %s -// RUN: %clang_cc1 -DOMP5 -fopenmp-simd -fopenmp-version=50 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print | FileCheck %s --check-prefix OMP5 +// RUN: %clang_cc1 -DOMP5 -fopenmp-simd -fopenmp-version=50 -std=c++11 -include-pch %t -fsyntax-only -verify -Wno-vla %s -ast-print | FileCheck %s --check-prefix OMP5 -// RUN: %clang_cc1 -DOMP5 -verify -fopenmp -fopenmp-version=99 -DOMP99 -ast-print %s | FileCheck %s --check-prefixes=OMP5,REV +// RUN: %clang_cc1 -DOMP5 -verify -Wno-vla -fopenmp -fopenmp-version=99 -DOMP99 -ast-print %s | FileCheck %s --check-prefixes=OMP5,REV // RUN: %clang_cc1 -DOMP5 -fopenmp -fopenmp-version=99 -DOMP99 -x c++ -std=c++11 -emit-pch -o %t %s -// RUN: %clang_cc1 -DOMP5 -fopenmp -fopenmp-version=99 -DOMP99 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print | FileCheck %s --check-prefixes=OMP5,REV +// RUN: %clang_cc1 -DOMP5 -fopenmp -fopenmp-version=99 -DOMP99 -std=c++11 -include-pch %t -fsyntax-only -verify -Wno-vla %s -ast-print | FileCheck %s --check-prefixes=OMP5,REV -// RUN: %clang_cc1 -DOMP5 -verify -fopenmp-simd -fopenmp-version=99 -DOMP99 -ast-print %s | FileCheck %s --check-prefixes=OMP5,REV +// RUN: %clang_cc1 -DOMP5 -verify -Wno-vla -fopenmp-simd -fopenmp-version=99 -DOMP99 -ast-print %s | FileCheck %s --check-prefixes=OMP5,REV // RUN: %clang_cc1 -DOMP5 -fopenmp-simd -fopenmp-version=99 -DOMP99 -x c++ -std=c++11 -emit-pch -o %t %s -// RUN: %clang_cc1 -DOMP5 -fopenmp-simd -fopenmp-version=99 -DOMP99 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print | FileCheck %s --check-prefixes=OMP5,REV +// RUN: %clang_cc1 -DOMP5 -fopenmp-simd -fopenmp-version=99 -DOMP99 -std=c++11 -include-pch %t -fsyntax-only -verify -Wno-vla %s -ast-print | FileCheck %s --check-prefixes=OMP5,REV #ifdef OMP99 #pragma omp requires reverse_offload @@ -393,7 +393,7 @@ T tmain(T argc, T *argv) { foo(); #pragma omp target map(always,alloc: i) foo(); -#pragma omp target map(always from: i) +#pragma omp target map(always, from: i) foo(); #pragma omp target map(always) {always++;} @@ -401,7 +401,7 @@ T tmain(T argc, T *argv) { {always++;i++;} #pragma omp target map(close,alloc: i) foo(); -#pragma omp target map(close from: i) +#pragma omp target map(close, from: i) foo(); #pragma omp target map(close) {close++;} @@ -857,7 +857,7 @@ int main (int argc, char **argv) { foo(); // OMP5-NEXT: foo(); -#pragma omp target map(always from: i) +#pragma omp target map(always, from: i) // OMP5-NEXT: #pragma omp target map(always,from: i) foo(); // OMP5-NEXT: foo(); @@ -882,7 +882,7 @@ int main (int argc, char **argv) { foo(); // OMP5-NEXT: foo(); -#pragma omp target map(close from: i) +#pragma omp target map(close, from: i) // OMP5-NEXT: #pragma omp target map(close,from: i) foo(); // OMP5-NEXT: foo(); @@ -1090,13 +1090,13 @@ int main (int argc, char **argv) { #ifdef OMP51 ///==========================================================================/// -// RUN: %clang_cc1 -DOMP51 -verify -fopenmp -ast-print %s | FileCheck %s --check-prefix OMP51 +// RUN: %clang_cc1 -DOMP51 -verify -Wno-vla -fopenmp -ast-print %s | FileCheck %s --check-prefix OMP51 // RUN: %clang_cc1 -DOMP51 -fopenmp -x c++ -std=c++11 -emit-pch -o %t %s -// RUN: %clang_cc1 -DOMP51 -fopenmp -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print | FileCheck %s --check-prefix OMP51 +// RUN: %clang_cc1 -DOMP51 -fopenmp -std=c++11 -include-pch %t -fsyntax-only -verify -Wno-vla %s -ast-print | FileCheck %s --check-prefix OMP51 -// RUN: %clang_cc1 -DOMP51 -verify -fopenmp-simd -ast-print %s | FileCheck %s --check-prefix OMP51 +// RUN: %clang_cc1 -DOMP51 -verify -Wno-vla -fopenmp-simd -ast-print %s | FileCheck %s --check-prefix OMP51 // RUN: %clang_cc1 -DOMP51 -fopenmp-simd -x c++ -std=c++11 -emit-pch -o %t %s -// RUN: %clang_cc1 -DOMP51 -fopenmp-simd -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print | FileCheck %s --check-prefix OMP51 +// RUN: %clang_cc1 -DOMP51 -fopenmp-simd -std=c++11 -include-pch %t -fsyntax-only -verify -Wno-vla %s -ast-print | FileCheck %s --check-prefix OMP51 void foo() {} @@ -1146,13 +1146,13 @@ int main (int argc, char **argv) { #ifdef OMP52 ///==========================================================================/// -// RUN: %clang_cc1 -DOMP52 -verify -fopenmp -fopenmp-version=52 -ast-print %s | FileCheck %s --check-prefix OMP52 +// RUN: %clang_cc1 -DOMP52 -verify -Wno-vla -fopenmp -fopenmp-version=52 -ast-print %s | FileCheck %s --check-prefix OMP52 // RUN: %clang_cc1 -DOMP52 -fopenmp -fopenmp-version=52 -x c++ -std=c++11 -emit-pch -o %t %s -// RUN: %clang_cc1 -DOMP52 -fopenmp -fopenmp-version=52 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print | FileCheck %s --check-prefix OMP52 +// RUN: %clang_cc1 -DOMP52 -fopenmp -fopenmp-version=52 -std=c++11 -include-pch %t -fsyntax-only -verify -Wno-vla %s -ast-print | FileCheck %s --check-prefix OMP52 -// RUN: %clang_cc1 -DOMP52 -verify -fopenmp-simd -fopenmp-version=52 -ast-print %s | FileCheck %s --check-prefix OMP52 +// RUN: %clang_cc1 -DOMP52 -verify -Wno-vla -fopenmp-simd -fopenmp-version=52 -ast-print %s | FileCheck %s --check-prefix OMP52 // RUN: %clang_cc1 -DOMP52 -fopenmp-simd -fopenmp-version=52 -x c++ -std=c++11 -emit-pch -o %t %s -// RUN: %clang_cc1 -DOMP52 -fopenmp-simd -fopenmp-version=52 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print | FileCheck %s --check-prefix OMP52 +// RUN: %clang_cc1 -DOMP52 -fopenmp-simd -fopenmp-version=52 -std=c++11 -include-pch %t -fsyntax-only -verify -Wno-vla %s -ast-print | FileCheck %s --check-prefix OMP52 void foo() {} @@ -1199,13 +1199,13 @@ foo(); #ifdef OMPX -// RUN: %clang_cc1 -DOMPX -verify -fopenmp -fopenmp-extensions -ast-print %s | FileCheck %s --check-prefix=OMPX +// RUN: %clang_cc1 -DOMPX -verify -Wno-vla -fopenmp -fopenmp-extensions -ast-print %s | FileCheck %s --check-prefix=OMPX // RUN: %clang_cc1 -DOMPX -fopenmp -fopenmp-extensions -x c++ -std=c++11 -emit-pch -o %t %s -// RUN: %clang_cc1 -DOMPX -fopenmp -fopenmp-extensions -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print | FileCheck %s --check-prefix=OMPX +// RUN: %clang_cc1 -DOMPX -fopenmp -fopenmp-extensions -std=c++11 -include-pch %t -fsyntax-only -verify -Wno-vla %s -ast-print | FileCheck %s --check-prefix=OMPX -// RUN: %clang_cc1 -DOMPX -verify -fopenmp-simd -fopenmp-extensions -ast-print %s | FileCheck %s --check-prefix=OMPX +// RUN: %clang_cc1 -DOMPX -verify -Wno-vla -fopenmp-simd -fopenmp-extensions -ast-print %s | FileCheck %s --check-prefix=OMPX // RUN: %clang_cc1 -DOMPX -fopenmp-simd -fopenmp-extensions -x c++ -std=c++11 -emit-pch -o %t %s -// RUN: %clang_cc1 -DOMPX -fopenmp-simd -fopenmp-extensions -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print | FileCheck %s --check-prefix=OMPX +// RUN: %clang_cc1 -DOMPX -fopenmp-simd -fopenmp-extensions -std=c++11 -include-pch %t -fsyntax-only -verify -Wno-vla %s -ast-print | FileCheck %s --check-prefix=OMPX void foo() {} diff --git a/clang/test/OpenMP/target_codegen.cpp b/clang/test/OpenMP/target_codegen.cpp index bd3d7eb853dab..fa96d5f00920b 100644 --- a/clang/test/OpenMP/target_codegen.cpp +++ b/clang/test/OpenMP/target_codegen.cpp @@ -1,60 +1,60 @@ // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP45 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP45 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP45 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP45 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP45 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP45 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP45 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP45 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP50 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP50 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP50 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP50 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP50 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP50 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP50 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP50 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=51 -D_DOMP51 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP51 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=51 -D_DOMP51 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP51 // RUN: %clang_cc1 -fopenmp -x c++ -fopenmp-version=51 -D_DOMP51 -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -fopenmp-version=51 -D_DOMP51 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP51 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=51 -D_DOMP51 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP51 +// RUN: %clang_cc1 -fopenmp -x c++ -fopenmp-version=51 -D_DOMP51 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP51 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=51 -D_DOMP51 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP51 // RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -D_DOMP51 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -D_DOMP51 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP51 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -D_DOMP51 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP51 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s // SIMD-ONLY1-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/target_constant_device_codegen.cpp b/clang/test/OpenMP/target_constant_device_codegen.cpp index b61681614ec98..b5923325e71f7 100644 --- a/clang/test/OpenMP/target_constant_device_codegen.cpp +++ b/clang/test/OpenMP/target_constant_device_codegen.cpp @@ -1,7 +1,7 @@ // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 // expected-no-diagnostics #ifndef HEADER diff --git a/clang/test/OpenMP/target_data_codegen.cpp b/clang/test/OpenMP/target_data_codegen.cpp index 1dd2173922f4a..4f3c94d175f36 100644 --- a/clang/test/OpenMP/target_data_codegen.cpp +++ b/clang/test/OpenMP/target_data_codegen.cpp @@ -3,19 +3,19 @@ #define HEADER ///==========================================================================/// -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 // RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 // RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} #ifdef CK1 @@ -218,19 +218,19 @@ void foo(int arg) { } #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK1A -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1A --check-prefix CK1A-64 +// RUN: %clang_cc1 -DCK1A -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1A --check-prefix CK1A-64 // RUN: %clang_cc1 -DCK1A -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK1A --check-prefix CK1A-64 -// RUN: %clang_cc1 -DCK1A -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1A --check-prefix CK1A-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK1A --check-prefix CK1A-64 +// RUN: %clang_cc1 -DCK1A -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1A --check-prefix CK1A-32 // RUN: %clang_cc1 -DCK1A -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK1A --check-prefix CK1A-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK1A --check-prefix CK1A-32 -// RUN: %clang_cc1 -DCK1A -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK1A -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK1A -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -DCK1A -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK1A -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK1A -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} #ifdef CK1A @@ -312,19 +312,19 @@ void foo(int arg) { } #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-64 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-64 // RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-64 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-64 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-32 // RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-32 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -DCK2 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -DCK2 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s // SIMD-ONLY1-NOT: {{__kmpc|__tgt}} #ifdef CK2 @@ -396,19 +396,19 @@ int bar(int arg){ // CK2: [[IFEND]] #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-64 +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-64 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-64 -// RUN: %clang_cc1 -DCK3 -verify -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-64 +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-32 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-32 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s -// RUN: %clang_cc1 -DCK3 -verify -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s // SIMD-ONLY2-NOT: {{__kmpc|__tgt}} #ifdef CK3 @@ -423,19 +423,19 @@ void no_target_devices(int arg) { } #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK4 --check-prefix CK4-64 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK4 --check-prefix CK4-64 // RUN: %clang_cc1 -DCK4 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK4 --check-prefix CK4-64 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK4 --check-prefix CK4-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK4 --check-prefix CK4-64 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK4 --check-prefix CK4-32 // RUN: %clang_cc1 -DCK4 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK4 --check-prefix CK4-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK4 --check-prefix CK4-32 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -DCK4 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -DCK4 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s // SIMD-ONLY1-NOT: {{__kmpc|__tgt}} #ifdef CK4 @@ -507,19 +507,19 @@ int bar(int arg){ // CK4: [[IFEND]] #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK5 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK5 --check-prefix CK5-64 +// RUN: %clang_cc1 -DCK5 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK5 --check-prefix CK5-64 // RUN: %clang_cc1 -DCK5 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK5 --check-prefix CK5-64 -// RUN: %clang_cc1 -DCK5 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK5 --check-prefix CK5-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK5 --check-prefix CK5-64 +// RUN: %clang_cc1 -DCK5 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK5 --check-prefix CK5-32 // RUN: %clang_cc1 -DCK5 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK5 --check-prefix CK5-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK5 --check-prefix CK5-32 -// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -DCK5 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s // RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s -// RUN: %clang_cc1 -DCK5 -verify -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -DCK5 -verify -Wno-vla -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s // RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s // SIMD-ONLY2-NOT: {{__kmpc|__tgt}}#ifdef CK5 #ifdef CK5 struct S1 { @@ -541,19 +541,19 @@ void test_close_modifier(int arg) { } #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK6 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK6 --check-prefix CK6-64 +// RUN: %clang_cc1 -DCK6 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK6 --check-prefix CK6-64 // RUN: %clang_cc1 -DCK6 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK6 --check-prefix CK6-64 -// RUN: %clang_cc1 -DCK6 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK6 --check-prefix CK6-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK6 --check-prefix CK6-64 +// RUN: %clang_cc1 -DCK6 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK6 --check-prefix CK6-32 // RUN: %clang_cc1 -DCK6 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK6 --check-prefix CK6-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK6 --check-prefix CK6-32 -// RUN: %clang_cc1 -DCK6 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -DCK6 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s // RUN: %clang_cc1 -DCK6 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s -// RUN: %clang_cc1 -DCK6 -verify -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -DCK6 -verify -Wno-vla -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s // RUN: %clang_cc1 -DCK6 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s // SIMD-ONLY2-NOT: {{__kmpc|__tgt}} #ifdef CK6 void test_close_modifier(int arg) { @@ -564,13 +564,13 @@ void test_close_modifier(int arg) { } #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK7 -verify -fopenmp -fopenmp-targets=x86_64 -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK7 --check-prefix CK7-64 +// RUN: %clang_cc1 -DCK7 -verify -Wno-vla -fopenmp -fopenmp-targets=x86_64 -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK7 --check-prefix CK7-64 // RUN: %clang_cc1 -DCK7 -fopenmp -fopenmp-targets=x86_64 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=x86_64 -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK7 --check-prefix CK7-64 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=x86_64 -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK7 --check-prefix CK7-64 -// RUN: %clang_cc1 -DCK7 -verify -fopenmp-simd -fopenmp-targets=x86_64 -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY7 %s +// RUN: %clang_cc1 -DCK7 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=x86_64 -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY7 %s // RUN: %clang_cc1 -DCK7 -fopenmp-simd -fopenmp-targets=x86_64 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=x86_64 -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY7 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=x86_64 -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY7 %s // SIMD-ONLY7-NOT: {{__kmpc|__tgt}} #ifdef CK7 // CK7: private unnamed_addr constant [2 x i64] [i64 64, i64 64] @@ -596,19 +596,19 @@ void test_device_ptr_addr(int arg) { } #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK8 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK8 --check-prefix CK8-64 +// RUN: %clang_cc1 -DCK8 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK8 --check-prefix CK8-64 // RUN: %clang_cc1 -DCK8 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK8 --check-prefix CK8-64 -// RUN: %clang_cc1 -DCK8 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK8 --check-prefix CK8-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK8 --check-prefix CK8-64 +// RUN: %clang_cc1 -DCK8 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK8 --check-prefix CK8-32 // RUN: %clang_cc1 -DCK8 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK8 --check-prefix CK8-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK8 --check-prefix CK8-32 -// RUN: %clang_cc1 -DCK8 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -DCK8 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s // RUN: %clang_cc1 -DCK8 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s -// RUN: %clang_cc1 -DCK8 -verify -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -DCK8 -verify -Wno-vla -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s // RUN: %clang_cc1 -DCK8 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s // SIMD-ONLY2-NOT: {{__kmpc|__tgt}}#ifdef CK8 #ifdef CK8 struct S1 { @@ -667,19 +667,19 @@ void test_present_modifier(int arg) { } #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK9 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK9 --check-prefix CK9-64 +// RUN: %clang_cc1 -DCK9 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK9 --check-prefix CK9-64 // RUN: %clang_cc1 -DCK9 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK9 --check-prefix CK9-64 -// RUN: %clang_cc1 -DCK9 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK9 --check-prefix CK9-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK9 --check-prefix CK9-64 +// RUN: %clang_cc1 -DCK9 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK9 --check-prefix CK9-32 // RUN: %clang_cc1 -DCK9 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK9 --check-prefix CK9-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK9 --check-prefix CK9-32 -// RUN: %clang_cc1 -DCK9 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -DCK9 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s // RUN: %clang_cc1 -DCK9 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s -// RUN: %clang_cc1 -DCK9 -verify -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -DCK9 -verify -Wno-vla -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s // RUN: %clang_cc1 -DCK9 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s // SIMD-ONLY2-NOT: {{__kmpc|__tgt}} #ifdef CK9 void test_present_modifier(int arg) { diff --git a/clang/test/OpenMP/target_data_if_logical_codegen.cpp b/clang/test/OpenMP/target_data_if_logical_codegen.cpp new file mode 100644 index 0000000000000..85d98b0c3bcd4 --- /dev/null +++ b/clang/test/OpenMP/target_data_if_logical_codegen.cpp @@ -0,0 +1,120 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ --version 3 +// REQUIRES: amdgpu-registered-target + +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -o - \ +// RUN: | FileCheck %s + +// Check same results after serialization round-trip +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -include-pch %t -emit-llvm %s -o - \ +// RUN: | FileCheck %s + +// expected-no-diagnostics +#ifndef HEADER +#define HEADER + +extern bool foo(bool); + +int if_logical() { + bool a = foo(true); + bool b = foo(true); + int pp = 42; + int *p = &pp; + #pragma omp target data if(a && b) map(to: p[0]) + { + p[0]++; + } + if (p[0]) + return 1; + return 0; +} + +int main() { + return if_logical(); +} + +#endif +// CHECK-LABEL: define dso_local noundef i32 @_Z10if_logicalv( +// CHECK-SAME: ) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[A:%.*]] = alloca i8, align 1 +// CHECK-NEXT: [[B:%.*]] = alloca i8, align 1 +// CHECK-NEXT: [[PP:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[P:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 +// CHECK-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 +// CHECK-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 +// CHECK-NEXT: [[CALL:%.*]] = call noundef zeroext i1 @_Z3foob(i1 noundef zeroext true) +// CHECK-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CALL]] to i8 +// CHECK-NEXT: store i8 [[FROMBOOL]], ptr [[A]], align 1 +// CHECK-NEXT: [[CALL1:%.*]] = call noundef zeroext i1 @_Z3foob(i1 noundef zeroext true) +// CHECK-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[CALL1]] to i8 +// CHECK-NEXT: store i8 [[FROMBOOL2]], ptr [[B]], align 1 +// CHECK-NEXT: store i32 42, ptr [[PP]], align 4 +// CHECK-NEXT: store ptr [[PP]], ptr [[P]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 +// CHECK-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 +// CHECK-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] +// CHECK: land.rhs: +// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[B]], align 1 +// CHECK-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP1]] to i1 +// CHECK-NEXT: br label [[LAND_END]] +// CHECK: land.end: +// CHECK-NEXT: [[TMP2:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[TOBOOL3]], [[LAND_RHS]] ] +// CHECK-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK: omp_if.then: +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[P]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[P]], align 8 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 0 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[TMP5]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[ARRAYIDX]], ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK-NEXT: store ptr null, ptr [[TMP7]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK-NEXT: call void @__tgt_target_data_begin_mapper(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 1, ptr [[TMP8]], ptr [[TMP9]], ptr @.offload_sizes, ptr @.offload_maptypes, ptr null, ptr null) +// CHECK-NEXT: br label [[OMP_IF_END:%.*]] +// CHECK: omp_if.else: +// CHECK-NEXT: br label [[OMP_IF_END]] +// CHECK: omp_if.end: +// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[P]], align 8 +// CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, ptr [[TMP10]], i64 0 +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 +// CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK-NEXT: store i32 [[INC]], ptr [[ARRAYIDX4]], align 4 +// CHECK-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE6:%.*]] +// CHECK: omp_if.then5: +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK-NEXT: call void @__tgt_target_data_end_mapper(ptr @[[GLOB1]], i64 -1, i32 1, ptr [[TMP12]], ptr [[TMP13]], ptr @.offload_sizes, ptr @.offload_maptypes, ptr null, ptr null) +// CHECK-NEXT: br label [[OMP_IF_END7:%.*]] +// CHECK: omp_if.else6: +// CHECK-NEXT: br label [[OMP_IF_END7]] +// CHECK: omp_if.end7: +// CHECK-NEXT: [[TMP14:%.*]] = load ptr, ptr [[P]], align 8 +// CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, ptr [[TMP14]], i64 0 +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX8]], align 4 +// CHECK-NEXT: [[TOBOOL9:%.*]] = icmp ne i32 [[TMP15]], 0 +// CHECK-NEXT: br i1 [[TOBOOL9]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] +// CHECK: if.then: +// CHECK-NEXT: store i32 1, ptr [[RETVAL]], align 4 +// CHECK-NEXT: br label [[RETURN:%.*]] +// CHECK: if.end: +// CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// CHECK-NEXT: br label [[RETURN]] +// CHECK: return: +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 +// CHECK-NEXT: ret i32 [[TMP16]] +// +// +// CHECK-LABEL: define dso_local noundef i32 @main( +// CHECK-SAME: ) #[[ATTR3:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_Z10if_logicalv() +// CHECK-NEXT: ret i32 [[CALL]] +// diff --git a/clang/test/OpenMP/target_data_use_device_addr_codegen.cpp b/clang/test/OpenMP/target_data_use_device_addr_codegen.cpp index a388b04a408a3..7e70cdf74ad37 100644 --- a/clang/test/OpenMP/target_data_use_device_addr_codegen.cpp +++ b/clang/test/OpenMP/target_data_use_device_addr_codegen.cpp @@ -1,10 +1,10 @@ -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/target_defaultmap_codegen_01.cpp b/clang/test/OpenMP/target_defaultmap_codegen_01.cpp index bff76b388458a..b4a01b685e498 100644 --- a/clang/test/OpenMP/target_defaultmap_codegen_01.cpp +++ b/clang/test/OpenMP/target_defaultmap_codegen_01.cpp @@ -5,19 +5,19 @@ #ifdef CK1 ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK1 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK1 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK1 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK1 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK1 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK1 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK1 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK1 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK1 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK1 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK1 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK1 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK1 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK1 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s // SIMD-ONLY10-NOT: {{__kmpc|__tgt}} // CK1-LABEL: @.__omp_offloading_{{.*}}implicit_maps_double_complex{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0 @@ -57,19 +57,19 @@ void implicit_maps_double_complex (int a){ // CK1: {{.+}} = getelementptr inbounds { double, double }, ptr [[REF]], i32 0, i32 0 #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK2 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK2 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK2 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK2 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK2 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK2 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK2 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK2 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK2 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK2 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK2 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK2 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK2 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK2 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK2 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK2 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK2 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK2 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK2 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK2 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s // SIMD-ONLY10-NOT: {{__kmpc|__tgt}} #ifdef CK2 @@ -110,19 +110,19 @@ void implicit_maps_double_complex (int a){ // CK2: {{.+}} = getelementptr inbounds { double, double }, ptr [[REF]], i32 0, i32 0 #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK3 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK3 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK3 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK3 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK3 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK3 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK3 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK3 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK3 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK3 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK3 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK3 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK3 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK3 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK3 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK3 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK3 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK3 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK3 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK3 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s // SIMD-ONLY10-NOT: {{__kmpc|__tgt}} #ifdef CK3 @@ -163,19 +163,19 @@ void implicit_maps_double_complex (int a){ // CK3: {{.+}} = getelementptr inbounds { double, double }, ptr [[REF]], i32 0, i32 0 #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK4 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK4 --check-prefix CK4-64 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK4 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK4 --check-prefix CK4-64 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK4 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK4 --check-prefix CK4-64 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK4 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK4 --check-prefix CK4-32 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK4 --check-prefix CK4-64 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK4 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK4 --check-prefix CK4-32 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK4 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK4 --check-prefix CK4-32 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK4 --check-prefix CK4-32 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK4 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK4 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK4 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK4 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK4 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK4 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s // SIMD-ONLY6-NOT: {{__kmpc|__tgt}} #ifdef CK4 @@ -234,19 +234,19 @@ void implicit_maps_double (int a){ #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK5 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK5 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK5 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK5 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK5 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK5 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK5 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK5 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK5 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK5 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK5 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK5 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK5 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK5 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK5 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK5 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK5 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK5 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK5 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK5 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // SIMD-ONLY8-NOT: {{__kmpc|__tgt}} #ifdef CK5 @@ -288,19 +288,19 @@ void implicit_maps_array (int a){ // CK5: {{.+}} = getelementptr inbounds [2 x double], ptr [[REF]], i{{64|32}} 0, i{{64|32}} 0 #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK6 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK6 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK6 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK6 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK6 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK6 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK6 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK6 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK6 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK6 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK6 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK6 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK6 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK6 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK6 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK6 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK6 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK6 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK6 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK6 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // SIMD-ONLY8-NOT: {{__kmpc|__tgt}} #ifdef CK6 @@ -341,19 +341,19 @@ void implicit_maps_array (int a){ // CK6: {{.+}} = getelementptr inbounds [2 x double], ptr [[REF]], i{{64|32}} 0, i{{64|32}} 0 #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK7 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK7 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK7 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK7 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK7 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK7 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK7 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK7 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK7 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK7 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK7 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK7 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK7 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK7 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK7 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK7 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK7 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK7 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK7 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK7 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // SIMD-ONLY8-NOT: {{__kmpc|__tgt}} #ifdef CK7 @@ -395,19 +395,19 @@ void implicit_maps_array (int a){ // CK7: {{.+}} = getelementptr inbounds [2 x double], ptr [[REF]], i{{64|32}} 0, i{{64|32}} 0 #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK8 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK8 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK8 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK8 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK8 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK8 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK8 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK8 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK8 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK8 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK8 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK8 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK8 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK8 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK8 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK8 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK8 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK8 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK8 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK8 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // SIMD-ONLY8-NOT: {{__kmpc|__tgt}} #ifdef CK8 @@ -449,19 +449,19 @@ void implicit_maps_array (int a){ #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK9 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK9 --check-prefix CK9-64 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK9 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK9 --check-prefix CK9-64 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK9 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK9 --check-prefix CK9-64 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK9 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK9 --check-prefix CK9-32 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK9 --check-prefix CK9-64 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK9 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK9 --check-prefix CK9-32 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK9 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK9 --check-prefix CK9-32 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK9 --check-prefix CK9-32 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK9 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY26 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK9 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY26 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK9 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY26 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK9 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY26 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY26 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK9 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY26 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK9 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY26 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY26 %s // SIMD-ONLY26-NOT: {{__kmpc|__tgt}} #ifdef CK9 @@ -502,19 +502,19 @@ void zero_size_section_and_private_maps (int ii){ #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK10 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK10 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK10 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK10 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK10 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK10 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK10 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK10 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK10 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK10 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK10 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK10 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK10 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK10 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK10 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK10 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK10 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK10 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK10 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK10 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // SIMD-ONLY8-NOT: {{__kmpc|__tgt}} #ifdef CK10 @@ -553,19 +553,19 @@ void explicit_maps_single (){ // CK10: define {{.+}}[[CALL]] #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK11 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK11 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK11 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK11 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK11 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK11 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK11 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK11 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK11 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK11 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK11 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK11 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK11 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK11 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK11 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK11 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK11 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK11 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK11 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK11 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // SIMD-ONLY8-NOT: {{__kmpc|__tgt}} #ifdef CK11 @@ -604,19 +604,19 @@ void explicit_maps_single (){ // CK11: define {{.+}}[[CALL09]] #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK12 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK12 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK12 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK12 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK12 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK12 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK12 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK12 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK12 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK12 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK12 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK12 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK12 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK12 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK12 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK12 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK12 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK12 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK12 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK12 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // SIMD-ONLY8-NOT: {{__kmpc|__tgt}} #ifdef CK12 @@ -655,19 +655,19 @@ void explicit_maps_single (){ // CK12: define {{.+}}[[CALL09]] #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK13 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK13 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK13 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK13 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK13 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK13 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK13 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK13 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK13 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK13 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK13 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK13 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // SIMD-ONLY8-NOT: {{__kmpc|__tgt}} #ifdef CK13 @@ -706,19 +706,19 @@ void explicit_maps_single (){ // CK13: define {{.+}}[[CALL09]] #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK14 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK14 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK14 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK14 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK14 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK14 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK14 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK14 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK14 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK14 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK14 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK14 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK14 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK14 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK14 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK14 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK14 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK14 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK14 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK14 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // SIMD-ONLY8-NOT: {{__kmpc|__tgt}} #ifdef CK14 @@ -757,19 +757,19 @@ void explicit_maps_single (){ // CK14: define {{.+}}[[CALL09]] #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK15 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK15 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK15 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK15 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK15 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK15 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK15 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK15 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK15 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK15 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK15 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK15 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK15 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK15 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK15 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY12 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK15 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY12 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK15 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY12 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK15 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY12 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY12 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK15 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY12 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK15 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY12 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY12 %s // SIMD-ONLY12-NOT: {{__kmpc|__tgt}} #ifdef CK15 @@ -836,19 +836,19 @@ void implicit_maps_variable_length_array (int a){ // CK15: {{.+}} = getelementptr inbounds double, ptr [[REF]], i[[sz]] %{{.+}} #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK16 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK16 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK16 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK16 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK16 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK16 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK16 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK16 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK16 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK16 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK16 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK16 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK16 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK16 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK16 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK16 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK16 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK16 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK16 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK16 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s // SIMD-ONLY16-NOT: {{__kmpc|__tgt}} #ifdef CK16 @@ -896,19 +896,19 @@ void implicit_maps_struct (int a){ // CK16: {{.+}} = getelementptr inbounds [[ST]], ptr [[REF]], i32 0, i32 0 #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK17 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK17 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK17 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK17 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK17 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK17 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK17 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK17 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK17 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK17 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK17 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK17 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK17 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK17 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK17 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK17 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK17 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK17 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK17 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK17 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s // SIMD-ONLY16-NOT: {{__kmpc|__tgt}} #ifdef CK17 @@ -956,19 +956,19 @@ void implicit_maps_struct (int a){ // CK17: {{.+}} = getelementptr inbounds [[ST]], ptr [[REF]], i32 0, i32 0 #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK18 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK18 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK18 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK18 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK18 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK18 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK18 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK18 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK18 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK18 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK18 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK18 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK18 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK18 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK18 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK18 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK18 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK18 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK18 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK18 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s // SIMD-ONLY16-NOT: {{__kmpc|__tgt}} #ifdef CK18 @@ -1016,19 +1016,19 @@ void implicit_maps_struct (int a){ // CK18: {{.+}} = getelementptr inbounds [[ST]], ptr [[REF]], i32 0, i32 0 #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK19 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK19 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK19 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK19 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK19 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK19 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK19 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK19 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK19 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK19 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK19 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK19 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK19 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK19 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK19 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK19 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK19 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK19 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK19 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK19 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s // SIMD-ONLY16-NOT: {{__kmpc|__tgt}} #ifdef CK19 @@ -1076,19 +1076,19 @@ void implicit_maps_struct (int a){ // CK19: {{.+}} = getelementptr inbounds [[ST]], ptr [[REF]], i32 0, i32 0 #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK20 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK20 --check-prefix CK20-64 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK20 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK20 --check-prefix CK20-64 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK20 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK20 --check-prefix CK20-64 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK20 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK20 --check-prefix CK20-32 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK20 --check-prefix CK20-64 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK20 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK20 --check-prefix CK20-32 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK20 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK20 --check-prefix CK20-32 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK20 --check-prefix CK20-32 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK20 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK20 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK20 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK20 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK20 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK20 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s // SIMD-ONLY6-NOT: {{__kmpc|__tgt}} #ifdef CK20 @@ -1147,19 +1147,19 @@ void implicit_maps_double (int a){ #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK21 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK21 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK21 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK21 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK21 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK21 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK21 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK21 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK21 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK21 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK21 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK21 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK21 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK21 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK21 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK21 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK21 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK21 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK21 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK21 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s // SIMD-ONLY16-NOT: {{__kmpc|__tgt}} #ifdef CK21 @@ -1207,19 +1207,19 @@ void implicit_maps_struct (int a){ // CK21: {{.+}} = getelementptr inbounds [[ST]], ptr [[REF]], i32 0, i32 0 #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK22 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK22 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK22 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK22 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK22 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK22 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK22 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK22 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK22 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK22 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK22 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK22 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK22 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK22 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK22 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY9 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK22 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY9 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK22 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY9 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK22 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY9 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY9 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK22 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY9 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK22 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY9 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY9 %s // SIMD-ONLY9-NOT: {{__kmpc|__tgt}} #ifdef CK22 @@ -1262,19 +1262,19 @@ void implicit_maps_pointer (){ #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK23 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK23 --check-prefix CK23-64 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK23 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK23 --check-prefix CK23-64 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK23 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK23 --check-prefix CK23-64 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK23 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK23 --check-prefix CK23-32 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK23 --check-prefix CK23-64 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK23 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK23 --check-prefix CK23-32 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK23 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK23 --check-prefix CK23-32 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK23 --check-prefix CK23-32 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK23 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK23 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK23 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK23 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK23 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK23 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} #ifdef CK23 @@ -1466,19 +1466,19 @@ void bar(float *&a, int *&b) { #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK24 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK24 --check-prefix CK24-64 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK24 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK24 --check-prefix CK24-64 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK24 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK24 --check-prefix CK24-64 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK24 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK24 --check-prefix CK24-32 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK24 --check-prefix CK24-64 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK24 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK24 --check-prefix CK24-32 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK24 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK24 --check-prefix CK24-32 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK24 --check-prefix CK24-32 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK24 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK24 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK24 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK24 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK24 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK24 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s // SIMD-ONLY18-NOT: {{__kmpc|__tgt}} #ifdef CK24 @@ -1546,19 +1546,19 @@ void explicit_maps_single (int ii){ #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK25 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK25 --check-prefix CK25-64 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK25 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK25 --check-prefix CK25-64 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK25 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK25 --check-prefix CK25-64 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK25 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK25 --check-prefix CK25-32 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK25 --check-prefix CK25-64 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK25 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK25 --check-prefix CK25-32 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK25 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK25 --check-prefix CK25-32 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK25 --check-prefix CK25-32 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK25 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK25 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK25 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK25 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK25 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK25 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s // SIMD-ONLY18-NOT: {{__kmpc|__tgt}} #ifdef CK25 @@ -1581,19 +1581,19 @@ void declare_target_to() #endif ///==========================================================================/// -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK26 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK26 --check-prefix CK26-64 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK26 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK26 --check-prefix CK26-64 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK26 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK26 --check-prefix CK26-64 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK26 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK26 --check-prefix CK26-32 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK26 --check-prefix CK26-64 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK26 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK26 --check-prefix CK26-32 // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK26 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK26 --check-prefix CK26-32 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK26 --check-prefix CK26-32 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK26 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK26 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK26 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK26 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -DCK26 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK26 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s // SIMD-ONLY18-NOT: {{__kmpc|__tgt}} #ifdef CK26 diff --git a/clang/test/OpenMP/target_defaultmap_messages.cpp b/clang/test/OpenMP/target_defaultmap_messages.cpp index 4295760ed28d9..8052e34d5c933 100644 --- a/clang/test/OpenMP/target_defaultmap_messages.cpp +++ b/clang/test/OpenMP/target_defaultmap_messages.cpp @@ -1,11 +1,11 @@ -// RUN: %clang_cc1 -verify -fopenmp %s -verify=expected,omp51 -Wuninitialized -DOMP51 -// RUN: %clang_cc1 -verify -fopenmp-simd %s -verify=expected,omp51 -Wuninitialized -DOMP51 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp %s -verify=expected,omp51 -Wuninitialized -DOMP51 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd %s -verify=expected,omp51 -Wuninitialized -DOMP51 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 %s -verify=expected,omp5 -Wuninitialized -DOMP5 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 %s -verify=expected,omp5 -Wuninitialized -DOMP5 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=50 %s -verify=expected,omp5 -Wuninitialized -DOMP5 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=50 %s -verify=expected,omp5 -Wuninitialized -DOMP5 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 %s -verify=expected,omp45 -Wuninitialized -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 %s -verify=expected,omp45 -Wuninitialized +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 %s -verify=expected,omp45 -Wuninitialized +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 %s -verify=expected,omp45 -Wuninitialized struct Bar { int a; diff --git a/clang/test/OpenMP/target_depend_codegen.cpp b/clang/test/OpenMP/target_depend_codegen.cpp index 973c2374412d7..83430dd97b073 100644 --- a/clang/test/OpenMP/target_depend_codegen.cpp +++ b/clang/test/OpenMP/target_depend_codegen.cpp @@ -1,37 +1,37 @@ // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s // SIMD-ONLY1-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/target_enter_data_codegen.cpp b/clang/test/OpenMP/target_enter_data_codegen.cpp index 5c993e3600618..147d372fccaaf 100644 --- a/clang/test/OpenMP/target_enter_data_codegen.cpp +++ b/clang/test/OpenMP/target_enter_data_codegen.cpp @@ -3,19 +3,19 @@ #define HEADER ///==========================================================================/// -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 // RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 // RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} #ifdef CK1 @@ -219,19 +219,19 @@ void foo(int arg) { #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK1A -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1A --check-prefix CK1A-64 +// RUN: %clang_cc1 -DCK1A -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1A --check-prefix CK1A-64 // RUN: %clang_cc1 -DCK1A -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK1A --check-prefix CK1A-64 -// RUN: %clang_cc1 -DCK1A -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1A --check-prefix CK1A-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK1A --check-prefix CK1A-64 +// RUN: %clang_cc1 -DCK1A -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1A --check-prefix CK1A-32 // RUN: %clang_cc1 -DCK1A -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK1A --check-prefix CK1A-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK1A --check-prefix CK1A-32 -// RUN: %clang_cc1 -DCK1A -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK1A -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK1A -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -DCK1A -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK1A -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK1A -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} #ifdef CK1A @@ -301,19 +301,19 @@ void foo(int arg) { } #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-64 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-64 // RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-64 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-64 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-32 // RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-32 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -DCK2 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -DCK2 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s // SIMD-ONLY1-NOT: {{__kmpc|__tgt}} #ifdef CK2 @@ -375,19 +375,19 @@ int bar(int arg){ // CK2-NOT: __tgt_target_data_end #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-64 +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-64 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-64 -// RUN: %clang_cc1 -DCK3 -verify -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-64 +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-32 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-32 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s -// RUN: %clang_cc1 -DCK3 -verify -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s // SIMD-ONLY2-NOT: {{__kmpc|__tgt}} #ifdef CK3 @@ -402,38 +402,38 @@ void no_target_devices(int arg) { } #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK4 --check-prefix CK4-64 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK4 --check-prefix CK4-64 // RUN: %clang_cc1 -DCK4 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK4 --check-prefix CK4-64 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK4 --check-prefix CK4-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK4 --check-prefix CK4-64 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK4 --check-prefix CK4-32 // RUN: %clang_cc1 -DCK4 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK4 --check-prefix CK4-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK4 --check-prefix CK4-32 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY3 %s +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY3 %s // RUN: %clang_cc1 -DCK4 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY3 %s -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY3 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY3 %s +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY3 %s // RUN: %clang_cc1 -DCK4 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY3 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY3 %s // SIMD-ONLY3-NOT: {{__kmpc|__tgt}} -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCK4 --check-prefix TCK4-64 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCK4 --check-prefix TCK4-64 // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCK4 --check-prefix TCK4-64 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCK4 --check-prefix TCK4-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCK4 --check-prefix TCK4-64 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCK4 --check-prefix TCK4-32 // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCK4 --check-prefix TCK4-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCK4 --check-prefix TCK4-32 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY4 %s +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY4 %s // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY4 %s -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY4 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY4 %s +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY4 %s // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY4 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY4 %s // SIMD-ONLY4-NOT: {{__kmpc|__tgt}} #ifdef CK4 @@ -448,19 +448,19 @@ void device_side_scan(int arg) { } #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK5 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK5 --check-prefix CK5-64 +// RUN: %clang_cc1 -DCK5 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK5 --check-prefix CK5-64 // RUN: %clang_cc1 -DCK5 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK5 --check-prefix CK5-64 -// RUN: %clang_cc1 -DCK5 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK5 --check-prefix CK5-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK5 --check-prefix CK5-64 +// RUN: %clang_cc1 -DCK5 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK5 --check-prefix CK5-32 // RUN: %clang_cc1 -DCK5 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK5 --check-prefix CK5-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK5 --check-prefix CK5-32 -// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -DCK5 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -DCK5 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -DCK5 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -DCK5 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s // SIMD-ONLY1-NOT: {{__kmpc|__tgt}} #ifdef CK5 diff --git a/clang/test/OpenMP/target_enter_data_depend_codegen.cpp b/clang/test/OpenMP/target_enter_data_depend_codegen.cpp index 997bca525d473..373b36a5ad7ff 100644 --- a/clang/test/OpenMP/target_enter_data_depend_codegen.cpp +++ b/clang/test/OpenMP/target_enter_data_depend_codegen.cpp @@ -1,16 +1,16 @@ -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/target_exit_data_codegen.cpp b/clang/test/OpenMP/target_exit_data_codegen.cpp index df0d8023371f0..96a0a5063dd6e 100644 --- a/clang/test/OpenMP/target_exit_data_codegen.cpp +++ b/clang/test/OpenMP/target_exit_data_codegen.cpp @@ -3,19 +3,19 @@ #define HEADER ///==========================================================================/// -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 // RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 // RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} #ifdef CK1 diff --git a/clang/test/OpenMP/target_exit_data_depend_codegen.cpp b/clang/test/OpenMP/target_exit_data_depend_codegen.cpp index 3313398b6a568..205ab3bd772f9 100644 --- a/clang/test/OpenMP/target_exit_data_depend_codegen.cpp +++ b/clang/test/OpenMP/target_exit_data_depend_codegen.cpp @@ -1,16 +1,16 @@ -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/target_firstprivate_codegen.cpp b/clang/test/OpenMP/target_firstprivate_codegen.cpp index 2af54e3972ce8..b4ead8f50cfea 100644 --- a/clang/test/OpenMP/target_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/target_firstprivate_codegen.cpp @@ -1,37 +1,37 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK0 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK0 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK1 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK2 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK2 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK3 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK3 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY01 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY02 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY01 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY02 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY03 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY03 %s // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK1 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK2 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK2 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK3 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK3 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY11 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY12 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY11 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY12 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY13 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY13 %s // expected-no-diagnostics #ifndef HEADER diff --git a/clang/test/OpenMP/target_has_device_addr_codegen_01.cpp b/clang/test/OpenMP/target_has_device_addr_codegen_01.cpp index 53a487dc0f9b2..3fc22111a8b41 100644 --- a/clang/test/OpenMP/target_has_device_addr_codegen_01.cpp +++ b/clang/test/OpenMP/target_has_device_addr_codegen_01.cpp @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -fopenmp-version=51 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -fopenmp-version=51 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -fopenmp-version=51 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=51 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // expected-no-diagnostics struct S { diff --git a/clang/test/OpenMP/target_in_reduction_codegen.cpp b/clang/test/OpenMP/target_in_reduction_codegen.cpp index 7c092ce35b2df..2eb6058461244 100644 --- a/clang/test/OpenMP/target_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/target_in_reduction_codegen.cpp @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 // expected-no-diagnostics #ifndef HEADER #define HEADER diff --git a/clang/test/OpenMP/target_map_codegen_12.cpp b/clang/test/OpenMP/target_map_codegen_12.cpp index 2e42ccf7dff2b..d662df73078f9 100644 --- a/clang/test/OpenMP/target_map_codegen_12.cpp +++ b/clang/test/OpenMP/target_map_codegen_12.cpp @@ -3,33 +3,33 @@ #define HEADER ///==========================================================================/// -// RUN: %clang_cc1 -DCK13 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 +// RUN: %clang_cc1 -DCK13 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 // RUN: %clang_cc1 -DCK13 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 -// RUN: %clang_cc1 -DCK13 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 +// RUN: %clang_cc1 -DCK13 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 // RUN: %clang_cc1 -DCK13 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 -// RUN: %clang_cc1 -DCK13 -verify -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 +// RUN: %clang_cc1 -DCK13 -verify -Wno-vla -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 // RUN: %clang_cc1 -DCK13 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 -// RUN: %clang_cc1 -DCK13 -verify -fopenmp -fopenmp-version=45 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 +// RUN: %clang_cc1 -DCK13 -verify -Wno-vla -fopenmp -fopenmp-version=45 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 // RUN: %clang_cc1 -DCK13 -fopenmp -fopenmp-version=45 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 -// RUN: %clang_cc1 -DCK13 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 +// RUN: %clang_cc1 -DCK13 -verify -Wno-vla -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 // RUN: %clang_cc1 -DCK13 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 -// RUN: %clang_cc1 -DCK13 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 +// RUN: %clang_cc1 -DCK13 -verify -Wno-vla -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 // RUN: %clang_cc1 -DCK13 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 -// RUN: %clang_cc1 -DCK13 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY12 %s +// RUN: %clang_cc1 -DCK13 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY12 %s // RUN: %clang_cc1 -DCK13 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY12 %s -// RUN: %clang_cc1 -DCK13 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY12 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY12 %s +// RUN: %clang_cc1 -DCK13 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY12 %s // RUN: %clang_cc1 -DCK13 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY12 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY12 %s // SIMD-ONLY12-NOT: {{__kmpc|__tgt}} #ifdef CK13 diff --git a/clang/test/OpenMP/target_map_codegen_18a.cpp b/clang/test/OpenMP/target_map_codegen_18a.cpp index 63d314b4787e8..030a8b9ee5aef 100644 --- a/clang/test/OpenMP/target_map_codegen_18a.cpp +++ b/clang/test/OpenMP/target_map_codegen_18a.cpp @@ -8,15 +8,15 @@ // RUN: cp %S/target_map_codegen_18.inc %t.inc ///==========================================================================/// -// RUN: %clang_cc1 -DUSE -DCK19 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-64,CK19-USE %t.inc +// RUN: %clang_cc1 -DUSE -DCK19 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-64,CK19-USE %t.inc // RUN: %clang_cc1 -DUSE -DCK19 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -DUSE -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-64,CK19-USE %t.inc -// RUN: %clang_cc1 -DUSE -DCK19 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-32,CK19-USE %t.inc +// RUN: %clang_cc1 -DUSE -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-64,CK19-USE %t.inc +// RUN: %clang_cc1 -DUSE -DCK19 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-32,CK19-USE %t.inc // RUN: %clang_cc1 -DUSE -DCK19 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -DUSE -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-32,CK19-USE %t.inc +// RUN: %clang_cc1 -DUSE -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-32,CK19-USE %t.inc -// RUN: %clang_cc1 -DUSE -DCK19 -verify -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-64,CK19-USE %t.inc +// RUN: %clang_cc1 -DUSE -DCK19 -verify -Wno-vla -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-64,CK19-USE %t.inc // RUN: %clang_cc1 -DUSE -DCK19 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -DUSE -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-64,CK19-USE %t.inc +// RUN: %clang_cc1 -DUSE -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-64,CK19-USE %t.inc #endif diff --git a/clang/test/OpenMP/target_map_codegen_18b.cpp b/clang/test/OpenMP/target_map_codegen_18b.cpp index 4b22f2a19c1d9..00028140cacdf 100644 --- a/clang/test/OpenMP/target_map_codegen_18b.cpp +++ b/clang/test/OpenMP/target_map_codegen_18b.cpp @@ -7,15 +7,15 @@ // its full name in every FileCheck command. // RUN: cp %S/target_map_codegen_18.inc %t.inc -// RUN: %clang_cc1 -DUSE -DCK19 -verify -fopenmp -fopenmp-version=45 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-32,CK19-USE %t.inc +// RUN: %clang_cc1 -DUSE -DCK19 -verify -Wno-vla -fopenmp -fopenmp-version=45 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-32,CK19-USE %t.inc // RUN: %clang_cc1 -DUSE -DCK19 -fopenmp -fopenmp-version=45 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -DUSE -fopenmp -fopenmp-version=45 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-32,CK19-USE %t.inc +// RUN: %clang_cc1 -DUSE -fopenmp -fopenmp-version=45 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-32,CK19-USE %t.inc -// RUN: %clang_cc1 -DUSE -DCK19 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-64,CK19-USE %t.inc +// RUN: %clang_cc1 -DUSE -DCK19 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-64,CK19-USE %t.inc // RUN: %clang_cc1 -DUSE -DCK19 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -DUSE -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-64,CK19-USE %t.inc -// RUN: %clang_cc1 -DUSE -DCK19 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-32,CK19-USE %t.inc +// RUN: %clang_cc1 -DUSE -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-64,CK19-USE %t.inc +// RUN: %clang_cc1 -DUSE -DCK19 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-32,CK19-USE %t.inc // RUN: %clang_cc1 -DUSE -DCK19 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -DUSE -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-32,CK19-USE %t.inc +// RUN: %clang_cc1 -DUSE -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-32,CK19-USE %t.inc #endif diff --git a/clang/test/OpenMP/target_map_codegen_18c.cpp b/clang/test/OpenMP/target_map_codegen_18c.cpp index 5bd0e0979649f..6fd57d33f7373 100644 --- a/clang/test/OpenMP/target_map_codegen_18c.cpp +++ b/clang/test/OpenMP/target_map_codegen_18c.cpp @@ -7,22 +7,22 @@ // its full name in every FileCheck command. // RUN: cp %S/target_map_codegen_18.inc %t.inc -// RUN: %clang_cc1 -DUSE -DCK19 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %t.inc +// RUN: %clang_cc1 -DUSE -DCK19 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %t.inc // RUN: %clang_cc1 -DUSE -DCK19 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -DUSE -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %t.inc -// RUN: %clang_cc1 -DUSE -DCK19 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %t.inc +// RUN: %clang_cc1 -DUSE -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %t.inc +// RUN: %clang_cc1 -DUSE -DCK19 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %t.inc // RUN: %clang_cc1 -DUSE -DCK19 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -DUSE -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %t.inc +// RUN: %clang_cc1 -DUSE -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %t.inc -// RUN: %clang_cc1 -DCK19 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-64,CK19-NOUSE %t.inc +// RUN: %clang_cc1 -DCK19 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-64,CK19-NOUSE %t.inc // RUN: %clang_cc1 -DCK19 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-64,CK19-NOUSE %t.inc -// RUN: %clang_cc1 -DCK19 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-32,CK19-NOUSE %t.inc +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-64,CK19-NOUSE %t.inc +// RUN: %clang_cc1 -DCK19 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-32,CK19-NOUSE %t.inc // RUN: %clang_cc1 -DCK19 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-32,CK19-NOUSE %t.inc +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-32,CK19-NOUSE %t.inc -// RUN: %clang_cc1 -DCK19 -verify -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-64,CK19-NOUSE %t.inc +// RUN: %clang_cc1 -DCK19 -verify -Wno-vla -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-64,CK19-NOUSE %t.inc // RUN: %clang_cc1 -DCK19 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-64,CK19-NOUSE %t.inc +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-64,CK19-NOUSE %t.inc #endif diff --git a/clang/test/OpenMP/target_map_codegen_18d.cpp b/clang/test/OpenMP/target_map_codegen_18d.cpp index 4ec1ac57f563e..0b8a7ec6679de 100644 --- a/clang/test/OpenMP/target_map_codegen_18d.cpp +++ b/clang/test/OpenMP/target_map_codegen_18d.cpp @@ -7,22 +7,22 @@ // its full name in every FileCheck command. // RUN: cp %S/target_map_codegen_18.inc %t.inc -// RUN: %clang_cc1 -DCK19 -verify -fopenmp -fopenmp-version=45 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-32,CK19-NOUSE %t.inc +// RUN: %clang_cc1 -DCK19 -verify -Wno-vla -fopenmp -fopenmp-version=45 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-32,CK19-NOUSE %t.inc // RUN: %clang_cc1 -DCK19 -fopenmp -fopenmp-version=45 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-32,CK19-NOUSE %t.inc +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-32,CK19-NOUSE %t.inc -// RUN: %clang_cc1 -DCK19 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-64,CK19-NOUSE %t.inc +// RUN: %clang_cc1 -DCK19 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-64,CK19-NOUSE %t.inc // RUN: %clang_cc1 -DCK19 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-64,CK19-NOUSE %t.inc -// RUN: %clang_cc1 -DCK19 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-32,CK19-NOUSE %t.inc +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-64,CK19-NOUSE %t.inc +// RUN: %clang_cc1 -DCK19 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-32,CK19-NOUSE %t.inc // RUN: %clang_cc1 -DCK19 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-32,CK19-NOUSE %t.inc +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefixes=CK19,CK19-32,CK19-NOUSE %t.inc -// RUN: %clang_cc1 -DCK19 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %t.inc +// RUN: %clang_cc1 -DCK19 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %t.inc // RUN: %clang_cc1 -DCK19 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %t.inc -// RUN: %clang_cc1 -DCK19 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %t.inc +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %t.inc +// RUN: %clang_cc1 -DCK19 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %t.inc // RUN: %clang_cc1 -DCK19 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %t.inc +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %t.inc #endif diff --git a/clang/test/OpenMP/target_map_messages.cpp b/clang/test/OpenMP/target_map_messages.cpp index 436fa51a4f963..a6776ee12c0ee 100644 --- a/clang/test/OpenMP/target_map_messages.cpp +++ b/clang/test/OpenMP/target_map_messages.cpp @@ -1,35 +1,35 @@ // -fopenmp, -fno-openmp-extensions -// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp,lt51-omp -fopenmp -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -// RUN: %clang_cc1 -verify=expected,lt50,lt51,omp,lt51-omp -fopenmp -fno-openmp-extensions -fopenmp-version=40 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -// RUN: %clang_cc1 -verify=expected,lt50,lt51,omp,lt51-omp -fopenmp -fno-openmp-extensions -fopenmp-version=45 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp,lt51-omp -fopenmp -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -// RUN: %clang_cc1 -verify=expected,ge50,ge51,omp,ge51-omp -fopenmp -fno-openmp-extensions -fopenmp-version=51 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -// RUN: %clang_cc1 -verify=expected,ge50,ge51,ge52,omp,ge52-omp -fopenmp -fno-openmp-extensions -fopenmp-version=52 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -// RUN: %clang_cc1 -DCCODE -verify -fopenmp -fno-openmp-extensions -ferror-limit 300 -x c %s -Wno-openmp -Wuninitialized +// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp,lt51-omp -fopenmp -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,lt50,lt51,omp,lt51-omp -fopenmp -fno-openmp-extensions -fopenmp-version=40 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,lt50,lt51,omp,lt51-omp -fopenmp -fno-openmp-extensions -fopenmp-version=45 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp,lt51-omp -fopenmp -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge50,ge51,omp,ge51-omp -fopenmp -fno-openmp-extensions -fopenmp-version=51 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge50,ge51,ge52,omp,ge52-omp,omp52 -fopenmp -fno-openmp-extensions -fopenmp-version=52 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -DCCODE -verify -fopenmp -fno-openmp-extensions -ferror-limit 300 -x c %s -Wno-openmp -Wuninitialized -Wno-vla // -fopenmp-simd, -fno-openmp-extensions -// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp,lt51-omp -fopenmp-simd -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -// RUN: %clang_cc1 -verify=expected,lt50,lt51,omp,lt51-omp -fopenmp-simd -fno-openmp-extensions -fopenmp-version=40 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -// RUN: %clang_cc1 -verify=expected,lt50,lt51,omp,lt51-omp -fopenmp-simd -fno-openmp-extensions -fopenmp-version=45 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp,lt51-omp -fopenmp-simd -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -// RUN: %clang_cc1 -verify=expected,ge50,ge51,omp,ge51-omp -fopenmp-simd -fno-openmp-extensions -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -// RUN: %clang_cc1 -DCCODE -verify -fopenmp-simd -fno-openmp-extensions -ferror-limit 300 -x c %s -Wno-openmp-mapping -Wuninitialized +// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp,lt51-omp -fopenmp-simd -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,lt50,lt51,omp,lt51-omp -fopenmp-simd -fno-openmp-extensions -fopenmp-version=40 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,lt50,lt51,omp,lt51-omp -fopenmp-simd -fno-openmp-extensions -fopenmp-version=45 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp,lt51-omp -fopenmp-simd -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge50,ge51,omp,ge51-omp -fopenmp-simd -fno-openmp-extensions -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -DCCODE -verify -fopenmp-simd -fno-openmp-extensions -ferror-limit 300 -x c %s -Wno-openmp-mapping -Wuninitialized -Wno-vla // -fopenmp -fopenmp-extensions -// RUN: %clang_cc1 -verify=expected,ge50,lt51,ompx,lt51-ompx -fopenmp -fopenmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -// RUN: %clang_cc1 -verify=expected,lt50,lt51,ompx,lt51-ompx -fopenmp -fopenmp-extensions -fopenmp-version=40 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -// RUN: %clang_cc1 -verify=expected,lt50,lt51,ompx,lt51-ompx -fopenmp -fopenmp-extensions -fopenmp-version=45 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -// RUN: %clang_cc1 -verify=expected,ge50,lt51,ompx,lt51-ompx -fopenmp -fopenmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -// RUN: %clang_cc1 -verify=expected,ge50,ge51,ompx,ge51-ompx -fopenmp -fopenmp-extensions -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -// RUN: %clang_cc1 -DCCODE -verify -fopenmp -fopenmp-extensions -ferror-limit 300 -x c %s -Wno-openmp -Wuninitialized +// RUN: %clang_cc1 -verify=expected,ge50,lt51,ompx,lt51-ompx -fopenmp -fopenmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,lt50,lt51,ompx,lt51-ompx -fopenmp -fopenmp-extensions -fopenmp-version=40 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,lt50,lt51,ompx,lt51-ompx -fopenmp -fopenmp-extensions -fopenmp-version=45 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge50,lt51,ompx,lt51-ompx -fopenmp -fopenmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge50,ge51,ompx,ge51-ompx -fopenmp -fopenmp-extensions -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -DCCODE -verify -fopenmp -fopenmp-extensions -ferror-limit 300 -x c %s -Wno-openmp -Wuninitialized -Wno-vla // -fopenmp-simd -fopenmp-extensions -// RUN: %clang_cc1 -verify=expected,ge50,lt51,ompx,lt51-ompx -fopenmp-simd -fopenmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -// RUN: %clang_cc1 -verify=expected,lt50,lt51,ompx,lt51-ompx -fopenmp-simd -fopenmp-extensions -fopenmp-version=40 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -// RUN: %clang_cc1 -verify=expected,lt50,lt51,ompx,lt51-ompx -fopenmp-simd -fopenmp-extensions -fopenmp-version=45 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -// RUN: %clang_cc1 -verify=expected,ge50,lt51,ompx,lt51-ompx -fopenmp-simd -fopenmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -// RUN: %clang_cc1 -verify=expected,ge50,ge51,ompx,ge51-ompx -fopenmp-simd -fopenmp-extensions -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -// RUN: %clang_cc1 -DCCODE -verify -fopenmp-simd -fopenmp-extensions -ferror-limit 300 -x c %s -Wno-openmp-mapping -Wuninitialized +// RUN: %clang_cc1 -verify=expected,ge50,lt51,ompx,lt51-ompx -fopenmp-simd -fopenmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,lt50,lt51,ompx,lt51-ompx -fopenmp-simd -fopenmp-extensions -fopenmp-version=40 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,lt50,lt51,ompx,lt51-ompx -fopenmp-simd -fopenmp-extensions -fopenmp-version=45 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge50,lt51,ompx,lt51-ompx -fopenmp-simd -fopenmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge50,ge51,ompx,ge51-ompx -fopenmp-simd -fopenmp-extensions -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -DCCODE -verify -fopenmp-simd -fopenmp-extensions -ferror-limit 300 -x c %s -Wno-openmp-mapping -Wuninitialized -Wno-vla // Check #ifdef CCODE @@ -232,10 +232,11 @@ struct SA { // expected-error@+1 {{missing map type}} #pragma omp target map( , f, : a) {} - #pragma omp target map(always close: a) // expected-error {{missing map type}} + #pragma omp target map(always close: a) // expected-error {{missing map type}} omp52-error{{missing ',' after map type modifier}} {} - #pragma omp target map(always close bf: a) // expected-error {{incorrect map type, expected one of 'to', 'from', 'tofrom', 'alloc', 'release', or 'delete'}} + #pragma omp target map(always close bf: a) // omp52-error 2 {{missing ',' after map type modifier}} expected-error {{incorrect map type, expected one of 'to', 'from', 'tofrom', 'alloc', 'release', or 'delete'}} {} + // omp52-error@+4 {{missing ',' after map type modifier}} // ge51-error@+3 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present'}} // lt51-error@+2 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper'}} // expected-error@+1 {{missing map type}} @@ -245,7 +246,7 @@ struct SA { // lt51-error@+1 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper'}} #pragma omp target map(tofrom from: a) {} - #pragma omp target map(close bf: a) // expected-error {{incorrect map type, expected one of 'to', 'from', 'tofrom', 'alloc', 'release', or 'delete'}} + #pragma omp target map(close bf: a) // omp52-error {{missing ',' after map type modifier}} expected-error {{incorrect map type, expected one of 'to', 'from', 'tofrom', 'alloc', 'release', or 'delete'}} {} #pragma omp target map(([b[I]][bf])f) // lt50-error {{expected ',' or ']' in lambda capture list}} lt50-error {{expected ')'}} lt50-note {{to match this '('}} {} diff --git a/clang/test/OpenMP/target_num_teams_num_threads_attributes.cpp b/clang/test/OpenMP/target_num_teams_num_threads_attributes.cpp index da0c4946c2220..613b21ff7f75f 100644 --- a/clang/test/OpenMP/target_num_teams_num_threads_attributes.cpp +++ b/clang/test/OpenMP/target_num_teams_num_threads_attributes.cpp @@ -1,52 +1,9 @@ -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK1 -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK1 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK1 -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK1 - -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK2 -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK2 -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK2 - -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK3 -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK3 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK3 -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK3 - -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK4 -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK4 -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK4 - -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK5 -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK5 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK5 -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK5 - -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK6 -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK6 -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK6 - -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK7 -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK7 -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK7 - +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s +// RUN: %clang_cc1 -target-cpu gfx900 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=nvptx64 -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple nvptx64 -fopenmp-targets=nvptx64 -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s +// RUN: %clang_cc1 -target-cpu sm_80 -fopenmp -x c++ -std=c++11 -triple nvptx64 -fopenmp-targets=nvptx64 -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s // expected-no-diagnostics @@ -54,7 +11,6 @@ #ifndef HEADER #define HEADER -// COM: Checking for default target and thread limit: CHECK1 void default_val_num_teams() { #pragma omp target simd @@ -62,7 +18,6 @@ void default_val_num_teams() { int a_var; } -// COM: Check for num_teams(22) all the same: CHECK2 void foo1() { #pragma omp target teams num_teams(22) { int a_var; } @@ -80,7 +35,6 @@ void foo3() { int a_var; } -// COM: Check for num_teams differently: CHECK3 void bar1() { #pragma omp target teams num_teams(22) { int a_var; } @@ -98,27 +52,23 @@ void bar3() { int a_var; } -// COM: Check for const int expression: CHECK4 void const_int() { const int NT = 22; #pragma omp target teams num_teams(NT) { int a_var; } } -// COM: Checking for num threads: CHECK5 void thread_limit() { #pragma omp target teams thread_limit(22) { int a_var; } } -// COM: Checking for num threads and thread limit: CHECK6 void num_threads() { #pragma omp target teams distribute parallel for thread_limit(22) num_threads(11) for (int i = 0; i < 22; i++) int a_var; } -// COM: Checking for thread_limit and num_teams: CHECK6 void threads_and_teams() { #pragma omp target teams distribute parallel for thread_limit(22) num_teams(33) for (int i = 0; i < 22; i++) @@ -127,49 +77,15 @@ void threads_and_teams() { #endif -// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+.*}}default_val_num_teams{{[^(]*}} -// CHECK1-SAME: () #[[ATTR_OUTLINED_DEF_SIMD:[0-9]+]] { - -// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+.*}}foo1{{[^(]*}} -// CHECK2-SAME: () #[[ATTR_OUTLINED_CHECK2:[0-9]+]] { -// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+.*}}foo2{{[^(]*}} -// CHECK2-SAME: () #[[ATTR_OUTLINED_CHECK2:[0-9]+]] { -// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+.*}}foo3{{[^(]*}} -// CHECK2-SAME: () #[[ATTR_OUTLINED_CHECK2:[0-9]+]] { - -// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+.*}}bar1{{[^(]*}} -// CHECK3-SAME: () #[[ATTR_OUTLINED_CHECK3_1:[0-9]+]] { -// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+.*}}bar2{{[^(]*}} -// CHECK3-SAME: () #[[ATTR_OUTLINED_CHECK3_2:[0-9]+]] { -// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+.*}}bar3{{[^(]*}} -// CHECK3-SAME: () #[[ATTR_OUTLINED_CHECK3_3:[0-9]+]] { - -// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+.*}}const_int{{[^(]*}} -// CHECK4-SAME: () #[[ATTR_OUTLINED_CHECK4:[0-9]+]] { - -// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+.*}}thread_limit{{[^(]*}} -// CHECK5-SAME: () #[[ATTR_OUTLINED_CHECK5:[0-9]+]] { - -// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+.*}}num_threads{{[^(]*}} -// CHECK6-SAME: () #[[ATTR_OUTLINED_CHECK6:[0-9]+]] { - -// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+.*}}threads_and_teams{{[^(]*}} -// CHECK7-SAME: () #[[ATTR_OUTLINED_CHECK7:[0-9]+]] { - - - -// CHECK1: attributes #[[ATTR_OUTLINED_DEF_SIMD]] = {{{.*"omp_target_num_teams"="1".*"omp_target_thread_limit"="1".*}}} - -// CHECK2: attributes #[[ATTR_OUTLINED_CHECK2]] = {{{.*"omp_target_num_teams"="22".*}}} - -// CHECK3: attributes #[[ATTR_OUTLINED_CHECK3_1]] = {{{.*"omp_target_num_teams"="22".*}}} -// CHECK3: attributes #[[ATTR_OUTLINED_CHECK3_2]] = {{{.*"omp_target_num_teams"="33".*}}} -// CHECK3: attributes #[[ATTR_OUTLINED_CHECK3_3]] = {{{.*"omp_target_num_teams"="44".*}}} -// CHECK4: attributes #[[ATTR_OUTLINED_CHECK4]] = {{{.*"omp_target_num_teams"="22".*}}} +// CHECK: "omp_target_num_teams"="1" +// CHECK: "omp_target_num_teams"="22" +// CHECK: "omp_target_num_teams"="33" +// CHECK: "omp_target_num_teams"="44" -// CHECK5: attributes #[[ATTR_OUTLINED_CHECK5]] = {{{.*"omp_target_thread_limit"="22".*}}} +// CHECK: "omp_target_thread_limit"="22" -// CHECK6: attributes #[[ATTR_OUTLINED_CHECK6]] = {{{.*"omp_target_thread_limit"="11".*}}} +// CHECK: "omp_target_thread_limit"="11" -// CHECK7: attributes #[[ATTR_OUTLINED_CHECK7]] = {{{.*"omp_target_num_teams"="33".*"omp_target_thread_limit"="22".*}}} +// CHECK: "omp_target_num_teams"="33" +// CHECK-SAME: "omp_target_thread_limit"="22" diff --git a/clang/test/OpenMP/target_parallel_codegen.cpp b/clang/test/OpenMP/target_parallel_codegen.cpp index ef65bc4df78ba..f0c3d6917e68e 100644 --- a/clang/test/OpenMP/target_parallel_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_codegen.cpp @@ -1,71 +1,71 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -343,7 +343,7 @@ int bar(int n){ // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP11]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP11]]) #[[ATTR3:[0-9]+]] // CHECK1-NEXT: [[TMP12:%.*]] = load i16, ptr [[AA]], align 2 // CHECK1-NEXT: store i16 [[TMP12]], ptr [[AA_CASTED]], align 2 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, ptr [[AA_CASTED]], align 8 @@ -385,7 +385,7 @@ int bar(int n){ // CHECK1-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 // CHECK1-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP13]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP13]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[A]], align 4 @@ -442,12 +442,12 @@ int bar(int n){ // CHECK1-NEXT: [[TMP61:%.*]] = icmp ne i32 [[TMP60]], 0 // CHECK1-NEXT: br i1 [[TMP61]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] // CHECK1: omp_offload.failed8: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP35]], i64 [[TMP37]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP35]], i64 [[TMP37]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT9]] // CHECK1: omp_offload.cont9: // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1: omp_if.else: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP35]], i64 [[TMP37]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP35]], i64 [[TMP37]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: [[TMP62:%.*]] = load i32, ptr [[A]], align 4 @@ -552,12 +552,12 @@ int bar(int n){ // CHECK1-NEXT: [[TMP114:%.*]] = icmp ne i32 [[TMP113]], 0 // CHECK1-NEXT: br i1 [[TMP114]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] // CHECK1: omp_offload.failed17: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP63]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP63]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT18]] // CHECK1: omp_offload.cont18: // CHECK1-NEXT: br label [[OMP_IF_END20:%.*]] // CHECK1: omp_if.else19: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP63]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP63]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_IF_END20]] // CHECK1: omp_if.end20: // CHECK1-NEXT: [[TMP115:%.*]] = load i32, ptr [[A]], align 4 @@ -574,7 +574,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -584,7 +584,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 @@ -643,14 +643,14 @@ int bar(int n){ // CHECK1-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 // CHECK1-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK1: omp_offload.failed.i: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]] // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] // CHECK1: .omp_outlined..exit: // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 -// CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -663,7 +663,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -691,7 +691,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -736,7 +736,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -795,7 +795,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1001,12 +1001,12 @@ int bar(int n){ // CHECK1-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 // CHECK1-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1: omp_if.else: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]] @@ -1109,12 +1109,12 @@ int bar(int n){ // CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 // CHECK1-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1: omp_if.else: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4 @@ -1197,12 +1197,12 @@ int bar(int n){ // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1: omp_if.else: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4 @@ -1235,7 +1235,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1301,7 +1301,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1359,7 +1359,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1388,7 +1388,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK1-SAME: () #[[ATTR8:[0-9]+]] { +// CHECK1-SAME: () #[[ATTR7:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) // CHECK1-NEXT: ret void @@ -1444,7 +1444,7 @@ int bar(int n){ // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP9]]) #[[ATTR4:[0-9]+]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP9]]) #[[ATTR3:[0-9]+]] // CHECK3-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2 // CHECK3-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4 @@ -1486,7 +1486,7 @@ int bar(int n){ // CHECK3-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 // CHECK3-NEXT: br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP11]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP11]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: [[TMP32:%.*]] = load i32, ptr [[A]], align 4 @@ -1543,12 +1543,12 @@ int bar(int n){ // CHECK3-NEXT: [[TMP59:%.*]] = icmp ne i32 [[TMP58]], 0 // CHECK3-NEXT: br i1 [[TMP59]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] // CHECK3: omp_offload.failed8: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP33]], i32 [[TMP35]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP33]], i32 [[TMP35]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT9]] // CHECK3: omp_offload.cont9: // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3: omp_if.else: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP33]], i32 [[TMP35]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP33]], i32 [[TMP35]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_IF_END]] // CHECK3: omp_if.end: // CHECK3-NEXT: [[TMP60:%.*]] = load i32, ptr [[A]], align 4 @@ -1655,12 +1655,12 @@ int bar(int n){ // CHECK3-NEXT: [[TMP114:%.*]] = icmp ne i32 [[TMP113]], 0 // CHECK3-NEXT: br i1 [[TMP114]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] // CHECK3: omp_offload.failed17: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP61]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP61]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT18]] // CHECK3: omp_offload.cont18: // CHECK3-NEXT: br label [[OMP_IF_END20:%.*]] // CHECK3: omp_if.else19: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP61]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP61]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_IF_END20]] // CHECK3: omp_if.end20: // CHECK3-NEXT: [[TMP115:%.*]] = load i32, ptr [[A]], align 4 @@ -1677,7 +1677,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -1687,7 +1687,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4 @@ -1746,14 +1746,14 @@ int bar(int n){ // CHECK3-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 // CHECK3-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK3: omp_offload.failed.i: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]] // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] // CHECK3: .omp_outlined..exit: // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 -// CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -1766,7 +1766,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -1794,7 +1794,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -1839,7 +1839,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -1898,7 +1898,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -2104,12 +2104,12 @@ int bar(int n){ // CHECK3-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 // CHECK3-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3: omp_if.else: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_IF_END]] // CHECK3: omp_if.end: // CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]] @@ -2212,12 +2212,12 @@ int bar(int n){ // CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 // CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3: omp_if.else: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_IF_END]] // CHECK3: omp_if.end: // CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4 @@ -2300,12 +2300,12 @@ int bar(int n){ // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3: omp_if.else: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_IF_END]] // CHECK3: omp_if.end: // CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4 @@ -2338,7 +2338,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -2404,7 +2404,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -2462,7 +2462,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -2491,7 +2491,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK3-SAME: () #[[ATTR8:[0-9]+]] { +// CHECK3-SAME: () #[[ATTR7:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) // CHECK3-NEXT: ret void @@ -2505,7 +2505,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined -// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -2528,7 +2528,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined -// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -2573,7 +2573,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined -// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -2632,7 +2632,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined -// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -2732,7 +2732,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined -// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -2793,7 +2793,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined -// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -2853,7 +2853,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined -// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -2889,7 +2889,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined -// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -2912,7 +2912,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined -// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -2957,7 +2957,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined -// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -3016,7 +3016,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined -// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -3116,7 +3116,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined -// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -3177,7 +3177,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined -// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -3237,7 +3237,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined -// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 diff --git a/clang/test/OpenMP/target_parallel_debug_codegen.cpp b/clang/test/OpenMP/target_parallel_debug_codegen.cpp index ea872af611e02..8d13e3387e73f 100644 --- a/clang/test/OpenMP/target_parallel_debug_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_debug_codegen.cpp @@ -65,7 +65,7 @@ int main() { return 0; } // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_debug__ -// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG23:![0-9]+]] { +// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG32:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr addrspace(1), align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -77,50 +77,50 @@ int main() { // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8 // CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META39:![0-9]+]], metadata !DIExpression()), !dbg [[DBG40:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META48:![0-9]+]], metadata !DIExpression()), !dbg [[DBG49:![0-9]+]] // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META41:![0-9]+]], metadata !DIExpression()), !dbg [[DBG42:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META50:![0-9]+]], metadata !DIExpression()), !dbg [[DBG51:![0-9]+]] // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META43:![0-9]+]], metadata !DIExpression()), !dbg [[DBG44:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META52:![0-9]+]], metadata !DIExpression()), !dbg [[DBG53:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META45:![0-9]+]], metadata !DIExpression()), !dbg [[DBG46:![0-9]+]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG47:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG47]] -// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG47]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG47]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG47]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8, !dbg [[DBG47]] -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG47]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG47]] -// CHECK1-NEXT: [[TMP6:%.*]] = addrspacecast ptr addrspace(1) [[TMP5]] to ptr, !dbg [[DBG47]] -// CHECK1-NEXT: store ptr [[TMP6]], ptr [[_TMP2]], align 8, !dbg [[DBG47]] -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG47]] -// CHECK1-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_kernel_environment), !dbg [[DBG47]] -// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1, !dbg [[DBG47]] -// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG47]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META54:![0-9]+]], metadata !DIExpression()), !dbg [[DBG55:![0-9]+]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG56:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG56]] +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG56]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG56]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG56]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8, !dbg [[DBG56]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG56]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG56]] +// CHECK1-NEXT: [[TMP6:%.*]] = addrspacecast ptr addrspace(1) [[TMP5]] to ptr, !dbg [[DBG56]] +// CHECK1-NEXT: store ptr [[TMP6]], ptr [[_TMP2]], align 8, !dbg [[DBG56]] +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG56]] +// CHECK1-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_kernel_environment), !dbg [[DBG56]] +// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1, !dbg [[DBG56]] +// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG56]] // CHECK1: user_code.entry: // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]) -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG48:![0-9]+]] -// CHECK1-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4, !dbg [[DBG48]] -// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG48]] -// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG48]] -// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP12]], align 8, !dbg [[DBG48]] -// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG48]] -// CHECK1-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP11]] to ptr, !dbg [[DBG48]] -// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8, !dbg [[DBG48]] -// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG48]] -// CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP15]], align 8, !dbg [[DBG48]] -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG48]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[TMP16]], align 8, !dbg [[DBG48]] -// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB3]], i32 [[TMP9]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4), !dbg [[DBG48]] -// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG49:![0-9]+]] -// CHECK1-NEXT: ret void, !dbg [[DBG51:![0-9]+]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG57:![0-9]+]] +// CHECK1-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4, !dbg [[DBG57]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG57]] +// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG57]] +// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP12]], align 8, !dbg [[DBG57]] +// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG57]] +// CHECK1-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP11]] to ptr, !dbg [[DBG57]] +// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8, !dbg [[DBG57]] +// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG57]] +// CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP15]], align 8, !dbg [[DBG57]] +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG57]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[TMP16]], align 8, !dbg [[DBG57]] +// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB3]], i32 [[TMP9]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4), !dbg [[DBG57]] +// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG58:![0-9]+]] +// CHECK1-NEXT: ret void, !dbg [[DBG60:![0-9]+]] // CHECK1: worker.exit: -// CHECK1-NEXT: ret void, !dbg [[DBG47]] +// CHECK1-NEXT: ret void, !dbg [[DBG56]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_debug___omp_outlined_debug__ -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG52:![0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR2:[0-9]+]] !dbg [[DBG61:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -137,83 +137,83 @@ int main() { // CHECK1-NEXT: [[H:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[D:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META59:![0-9]+]], metadata !DIExpression()), !dbg [[DBG60:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META68:![0-9]+]], metadata !DIExpression()), !dbg [[DBG69:![0-9]+]] // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META61:![0-9]+]], metadata !DIExpression()), !dbg [[DBG60]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META70:![0-9]+]], metadata !DIExpression()), !dbg [[DBG69]] // CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META62:![0-9]+]], metadata !DIExpression()), !dbg [[DBG63:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META71:![0-9]+]], metadata !DIExpression()), !dbg [[DBG72:![0-9]+]] // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META64:![0-9]+]], metadata !DIExpression()), !dbg [[DBG65:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META73:![0-9]+]], metadata !DIExpression()), !dbg [[DBG74:![0-9]+]] // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META66:![0-9]+]], metadata !DIExpression()), !dbg [[DBG67:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META75:![0-9]+]], metadata !DIExpression()), !dbg [[DBG76:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META68:![0-9]+]], metadata !DIExpression()), !dbg [[DBG69:![0-9]+]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG70:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG70]] -// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG70]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG70]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG70]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8, !dbg [[DBG70]] -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG70]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG70]] -// CHECK1-NEXT: [[TMP6:%.*]] = addrspacecast ptr addrspace(1) [[TMP5]] to ptr, !dbg [[DBG70]] -// CHECK1-NEXT: store ptr [[TMP6]], ptr [[_TMP2]], align 8, !dbg [[DBG70]] -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG70]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B3]], metadata [[META71:![0-9]+]], metadata !DIExpression()), !dbg [[DBG60]] -// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B3]], ptr align 4 [[TMP4]], i64 400, i1 false), !dbg [[DBG70]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[F]], metadata [[META72:![0-9]+]], metadata !DIExpression()), !dbg [[DBG75:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG76:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG76]] -// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX4]], i64 0, i64 1, !dbg [[DBG76]] -// CHECK1-NEXT: store ptr [[ARRAYIDX5]], ptr [[F]], align 8, !dbg [[DBG75]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[G]], metadata [[META77:![0-9]+]], metadata !DIExpression()), !dbg [[DBG78:![0-9]+]] -// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[DBG78]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[H]], metadata [[META79:![0-9]+]], metadata !DIExpression()), !dbg [[DBG80:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B3]], i64 0, i64 1, !dbg [[DBG81:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX6]], i64 0, i64 1, !dbg [[DBG81]] -// CHECK1-NEXT: store ptr [[ARRAYIDX7]], ptr [[H]], align 8, !dbg [[DBG80]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[D]], metadata [[META82:![0-9]+]], metadata !DIExpression()), !dbg [[DBG83:![0-9]+]] -// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[DBG83]] -// CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG84:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B3]], i64 0, i64 0, !dbg [[DBG85:![0-9]+]] -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG86:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP8]] to i64, !dbg [[DBG85]] -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX8]], i64 0, i64 [[IDXPROM]], !dbg [[DBG85]] -// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX9]], align 4, !dbg [[DBG87:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG88:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX10]], i64 0, i64 0, !dbg [[DBG88]] -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG89:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP9]] to i64, !dbg [[DBG88]] -// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM12]], !dbg [[DBG88]] -// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX13]], align 4, !dbg [[DBG90:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG91:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX14]], i64 0, i64 0, !dbg [[DBG91]] -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG92:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP10]] to i64, !dbg [[DBG91]] -// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX15]], i64 0, i64 [[IDXPROM16]], !dbg [[DBG91]] -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX17]], align 4, !dbg [[DBG91]] -// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B3]], i64 0, i64 0, !dbg [[DBG93:![0-9]+]] -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG94:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP12]] to i64, !dbg [[DBG93]] -// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG93]] -// CHECK1-NEXT: store i32 [[TMP11]], ptr [[ARRAYIDX20]], align 4, !dbg [[DBG95:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B3]], i64 0, i64 0, !dbg [[DBG96:![0-9]+]] -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG97:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG96]] -// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG96]] -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARRAYIDX23]], align 4, !dbg [[DBG96]] -// CHECK1-NEXT: [[TMP15:%.*]] = load i8, ptr [[TMP7]], align 1, !dbg [[DBG98:![0-9]+]] -// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP15]] to i1, !dbg [[DBG98]] -// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TOBOOL]] to i32, !dbg [[DBG98]] -// CHECK1-NEXT: [[OR:%.*]] = or i32 [[CONV]], [[TMP14]], !dbg [[DBG98]] -// CHECK1-NEXT: [[TOBOOL24:%.*]] = icmp ne i32 [[OR]], 0, !dbg [[DBG98]] -// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL24]] to i8, !dbg [[DBG98]] -// CHECK1-NEXT: store i8 [[FROMBOOL]], ptr [[TMP7]], align 1, !dbg [[DBG98]] -// CHECK1-NEXT: ret void, !dbg [[DBG99:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META77:![0-9]+]], metadata !DIExpression()), !dbg [[DBG78:![0-9]+]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG79:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG79]] +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG79]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG79]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG79]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8, !dbg [[DBG79]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG79]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG79]] +// CHECK1-NEXT: [[TMP6:%.*]] = addrspacecast ptr addrspace(1) [[TMP5]] to ptr, !dbg [[DBG79]] +// CHECK1-NEXT: store ptr [[TMP6]], ptr [[_TMP2]], align 8, !dbg [[DBG79]] +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG79]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B3]], metadata [[META80:![0-9]+]], metadata !DIExpression()), !dbg [[DBG69]] +// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B3]], ptr align 4 [[TMP4]], i64 400, i1 false), !dbg [[DBG79]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[F]], metadata [[META81:![0-9]+]], metadata !DIExpression()), !dbg [[DBG84:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG85:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG85]] +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX4]], i64 0, i64 1, !dbg [[DBG85]] +// CHECK1-NEXT: store ptr [[ARRAYIDX5]], ptr [[F]], align 8, !dbg [[DBG84]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[G]], metadata [[META86:![0-9]+]], metadata !DIExpression()), !dbg [[DBG87:![0-9]+]] +// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[DBG87]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[H]], metadata [[META88:![0-9]+]], metadata !DIExpression()), !dbg [[DBG89:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B3]], i64 0, i64 1, !dbg [[DBG90:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX6]], i64 0, i64 1, !dbg [[DBG90]] +// CHECK1-NEXT: store ptr [[ARRAYIDX7]], ptr [[H]], align 8, !dbg [[DBG89]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[D]], metadata [[META91:![0-9]+]], metadata !DIExpression()), !dbg [[DBG92:![0-9]+]] +// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[DBG92]] +// CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG93:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B3]], i64 0, i64 0, !dbg [[DBG94:![0-9]+]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG95:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP8]] to i64, !dbg [[DBG94]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX8]], i64 0, i64 [[IDXPROM]], !dbg [[DBG94]] +// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX9]], align 4, !dbg [[DBG96:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG97:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX10]], i64 0, i64 0, !dbg [[DBG97]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG98:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP9]] to i64, !dbg [[DBG97]] +// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM12]], !dbg [[DBG97]] +// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX13]], align 4, !dbg [[DBG99:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG100:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX14]], i64 0, i64 0, !dbg [[DBG100]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG101:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP10]] to i64, !dbg [[DBG100]] +// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX15]], i64 0, i64 [[IDXPROM16]], !dbg [[DBG100]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX17]], align 4, !dbg [[DBG100]] +// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B3]], i64 0, i64 0, !dbg [[DBG102:![0-9]+]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG103:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP12]] to i64, !dbg [[DBG102]] +// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG102]] +// CHECK1-NEXT: store i32 [[TMP11]], ptr [[ARRAYIDX20]], align 4, !dbg [[DBG104:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B3]], i64 0, i64 0, !dbg [[DBG105:![0-9]+]] +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG106:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG105]] +// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG105]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARRAYIDX23]], align 4, !dbg [[DBG105]] +// CHECK1-NEXT: [[TMP15:%.*]] = load i8, ptr [[TMP7]], align 1, !dbg [[DBG107:![0-9]+]] +// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP15]] to i1, !dbg [[DBG107]] +// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TOBOOL]] to i32, !dbg [[DBG107]] +// CHECK1-NEXT: [[OR:%.*]] = or i32 [[CONV]], [[TMP14]], !dbg [[DBG107]] +// CHECK1-NEXT: [[TOBOOL24:%.*]] = icmp ne i32 [[OR]], 0, !dbg [[DBG107]] +// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL24]] to i8, !dbg [[DBG107]] +// CHECK1-NEXT: store i8 [[FROMBOOL]], ptr [[TMP7]], align 1, !dbg [[DBG107]] +// CHECK1-NEXT: ret void, !dbg [[DBG108:![0-9]+]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_debug___omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG100:![0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR2]] !dbg [[DBG109:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -222,62 +222,62 @@ int main() { // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META107:![0-9]+]], metadata !DIExpression()), !dbg [[DBG108:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META116:![0-9]+]], metadata !DIExpression()), !dbg [[DBG117:![0-9]+]] // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META109:![0-9]+]], metadata !DIExpression()), !dbg [[DBG108]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META118:![0-9]+]], metadata !DIExpression()), !dbg [[DBG117]] // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META110:![0-9]+]], metadata !DIExpression()), !dbg [[DBG108]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META119:![0-9]+]], metadata !DIExpression()), !dbg [[DBG117]] // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META111:![0-9]+]], metadata !DIExpression()), !dbg [[DBG108]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META120:![0-9]+]], metadata !DIExpression()), !dbg [[DBG117]] // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META112:![0-9]+]], metadata !DIExpression()), !dbg [[DBG108]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META121:![0-9]+]], metadata !DIExpression()), !dbg [[DBG117]] // CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META113:![0-9]+]], metadata !DIExpression()), !dbg [[DBG108]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG114:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG114]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG114]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG114]] -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG114]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG114]] -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG114]] -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG114]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG114]] -// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG114]] -// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG114]] -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_debug___omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], ptr addrspace(1) [[TMP9]], i32 [[TMP6]], ptr [[TMP7]], ptr addrspace(1) [[TMP10]]) #[[ATTR3:[0-9]+]], !dbg [[DBG114]] -// CHECK1-NEXT: ret void, !dbg [[DBG114]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META122:![0-9]+]], metadata !DIExpression()), !dbg [[DBG117]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG123:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG123]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG123]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG123]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG123]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG123]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG123]] +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG123]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG123]] +// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG123]] +// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG123]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_debug___omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], ptr addrspace(1) [[TMP9]], i32 [[TMP6]], ptr [[TMP7]], ptr addrspace(1) [[TMP10]]) #[[ATTR4:[0-9]+]], !dbg [[DBG123]] +// CHECK1-NEXT: ret void, !dbg [[DBG123]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23 -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR5:[0-9]+]] !dbg [[DBG115:![0-9]+]] { +// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR6:[0-9]+]] !dbg [[DBG124:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META118:![0-9]+]], metadata !DIExpression()), !dbg [[DBG119:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META127:![0-9]+]], metadata !DIExpression()), !dbg [[DBG128:![0-9]+]] // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META120:![0-9]+]], metadata !DIExpression()), !dbg [[DBG119]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META129:![0-9]+]], metadata !DIExpression()), !dbg [[DBG128]] // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META121:![0-9]+]], metadata !DIExpression()), !dbg [[DBG119]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META130:![0-9]+]], metadata !DIExpression()), !dbg [[DBG128]] // CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META122:![0-9]+]], metadata !DIExpression()), !dbg [[DBG119]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG123:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG123]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG123]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG123]] -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG123]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG123]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG123]] -// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr [[TMP3]] to ptr addrspace(1), !dbg [[DBG123]] -// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG123]] -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_debug__(ptr addrspace(1) [[TMP7]], i32 [[TMP4]], ptr [[TMP5]], ptr addrspace(1) [[TMP8]]) #[[ATTR3]], !dbg [[DBG123]] -// CHECK1-NEXT: ret void, !dbg [[DBG123]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META131:![0-9]+]], metadata !DIExpression()), !dbg [[DBG128]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG132:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG132]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG132]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG132]] +// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG132]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG132]] +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG132]] +// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr [[TMP3]] to ptr addrspace(1), !dbg [[DBG132]] +// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG132]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_debug__(ptr addrspace(1) [[TMP7]], i32 [[TMP4]], ptr [[TMP5]], ptr addrspace(1) [[TMP8]]) #[[ATTR4]], !dbg [[DBG132]] +// CHECK1-NEXT: ret void, !dbg [[DBG132]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug__ -// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG124:![0-9]+]] { +// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG133:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr addrspace(1), align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -289,51 +289,51 @@ int main() { // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8 // CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META129:![0-9]+]], metadata !DIExpression()), !dbg [[DBG130:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META138:![0-9]+]], metadata !DIExpression()), !dbg [[DBG139:![0-9]+]] // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META131:![0-9]+]], metadata !DIExpression()), !dbg [[DBG132:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META140:![0-9]+]], metadata !DIExpression()), !dbg [[DBG141:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META133:![0-9]+]], metadata !DIExpression()), !dbg [[DBG134:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META142:![0-9]+]], metadata !DIExpression()), !dbg [[DBG143:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META135:![0-9]+]], metadata !DIExpression()), !dbg [[DBG136:![0-9]+]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG137:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG137]] -// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG137]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG137]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG137]] -// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG137]] -// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG137]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG137]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG137]] -// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG137]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG137]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG137]] -// CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_kernel_environment), !dbg [[DBG137]] -// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP9]], -1, !dbg [[DBG137]] -// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG137]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META144:![0-9]+]], metadata !DIExpression()), !dbg [[DBG145:![0-9]+]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG146:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG146]] +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG146]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG146]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG146]] +// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG146]] +// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG146]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG146]] +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG146]] +// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG146]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG146]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG146]] +// CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_kernel_environment), !dbg [[DBG146]] +// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP9]], -1, !dbg [[DBG146]] +// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG146]] // CHECK1: user_code.entry: // CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7:[0-9]+]]) -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG138:![0-9]+]] -// CHECK1-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4, !dbg [[DBG138]] -// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG138]] -// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG138]] -// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP13]], align 8, !dbg [[DBG138]] -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG138]] -// CHECK1-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP12]] to ptr, !dbg [[DBG138]] -// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8, !dbg [[DBG138]] -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG138]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 8, !dbg [[DBG138]] -// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG138]] -// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP17]], align 8, !dbg [[DBG138]] -// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB7]], i32 [[TMP10]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4), !dbg [[DBG138]] -// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG139:![0-9]+]] -// CHECK1-NEXT: ret void, !dbg [[DBG141:![0-9]+]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG147:![0-9]+]] +// CHECK1-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4, !dbg [[DBG147]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG147]] +// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG147]] +// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP13]], align 8, !dbg [[DBG147]] +// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG147]] +// CHECK1-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP12]] to ptr, !dbg [[DBG147]] +// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8, !dbg [[DBG147]] +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG147]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 8, !dbg [[DBG147]] +// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG147]] +// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP17]], align 8, !dbg [[DBG147]] +// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB7]], i32 [[TMP10]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4), !dbg [[DBG147]] +// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG148:![0-9]+]] +// CHECK1-NEXT: ret void, !dbg [[DBG150:![0-9]+]] // CHECK1: worker.exit: -// CHECK1-NEXT: ret void, !dbg [[DBG137]] +// CHECK1-NEXT: ret void, !dbg [[DBG146]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug___omp_outlined_debug__ -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG142:![0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR2]] !dbg [[DBG151:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -349,74 +349,74 @@ int main() { // CHECK1-NEXT: [[H:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[D:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META145:![0-9]+]], metadata !DIExpression()), !dbg [[DBG146:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META154:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155:![0-9]+]] // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META147:![0-9]+]], metadata !DIExpression()), !dbg [[DBG146]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META156:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155]] // CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META148:![0-9]+]], metadata !DIExpression()), !dbg [[DBG149:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META157:![0-9]+]], metadata !DIExpression()), !dbg [[DBG158:![0-9]+]] // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META150:![0-9]+]], metadata !DIExpression()), !dbg [[DBG151:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META159:![0-9]+]], metadata !DIExpression()), !dbg [[DBG160:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META152:![0-9]+]], metadata !DIExpression()), !dbg [[DBG153:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META161:![0-9]+]], metadata !DIExpression()), !dbg [[DBG162:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META154:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155:![0-9]+]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG156:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG156]] -// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG156]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG156]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG156]] -// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG156]] -// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG156]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG156]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG156]] -// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG156]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG156]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG156]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[F]], metadata [[META157:![0-9]+]], metadata !DIExpression()), !dbg [[DBG159:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG160:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG160]] -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX3]], i64 0, i64 1, !dbg [[DBG160]] -// CHECK1-NEXT: store ptr [[ARRAYIDX4]], ptr [[F]], align 8, !dbg [[DBG159]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[G]], metadata [[META161:![0-9]+]], metadata !DIExpression()), !dbg [[DBG162:![0-9]+]] -// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[DBG162]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[H]], metadata [[META163:![0-9]+]], metadata !DIExpression()), !dbg [[DBG164:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 1, !dbg [[DBG165:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX5]], i64 0, i64 1, !dbg [[DBG165]] -// CHECK1-NEXT: store ptr [[ARRAYIDX6]], ptr [[H]], align 8, !dbg [[DBG164]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[D]], metadata [[META166:![0-9]+]], metadata !DIExpression()), !dbg [[DBG167:![0-9]+]] -// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[DBG167]] -// CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG168:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG169:![0-9]+]] -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG170:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64, !dbg [[DBG169]] -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], i64 0, i64 [[IDXPROM]], !dbg [[DBG169]] -// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX8]], align 4, !dbg [[DBG171:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG172:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX9]], i64 0, i64 0, !dbg [[DBG172]] -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG173:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP10]] to i64, !dbg [[DBG172]] -// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX10]], i64 0, i64 [[IDXPROM11]], !dbg [[DBG172]] -// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX12]], align 4, !dbg [[DBG174:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG175:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG175]] -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG176:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP11]] to i64, !dbg [[DBG175]] -// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG175]] -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX16]], align 4, !dbg [[DBG175]] -// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG177:![0-9]+]] -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG178:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM18:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG177]] -// CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX17]], i64 0, i64 [[IDXPROM18]], !dbg [[DBG177]] -// CHECK1-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX19]], align 4, !dbg [[DBG179:![0-9]+]] -// CHECK1-NEXT: [[TMP14:%.*]] = load i8, ptr [[TMP8]], align 1, !dbg [[DBG180:![0-9]+]] -// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP14]] to i1, !dbg [[DBG180]] -// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TOBOOL]] to i32, !dbg [[DBG180]] -// CHECK1-NEXT: store i32 [[CONV]], ptr [[D]], align 4, !dbg [[DBG181:![0-9]+]] -// CHECK1-NEXT: ret void, !dbg [[DBG182:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META163:![0-9]+]], metadata !DIExpression()), !dbg [[DBG164:![0-9]+]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG165:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG165]] +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG165]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG165]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG165]] +// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG165]] +// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG165]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG165]] +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG165]] +// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG165]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG165]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG165]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[F]], metadata [[META166:![0-9]+]], metadata !DIExpression()), !dbg [[DBG168:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG169:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG169]] +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX3]], i64 0, i64 1, !dbg [[DBG169]] +// CHECK1-NEXT: store ptr [[ARRAYIDX4]], ptr [[F]], align 8, !dbg [[DBG168]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[G]], metadata [[META170:![0-9]+]], metadata !DIExpression()), !dbg [[DBG171:![0-9]+]] +// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[DBG171]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[H]], metadata [[META172:![0-9]+]], metadata !DIExpression()), !dbg [[DBG173:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 1, !dbg [[DBG174:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX5]], i64 0, i64 1, !dbg [[DBG174]] +// CHECK1-NEXT: store ptr [[ARRAYIDX6]], ptr [[H]], align 8, !dbg [[DBG173]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[D]], metadata [[META175:![0-9]+]], metadata !DIExpression()), !dbg [[DBG176:![0-9]+]] +// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[DBG176]] +// CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG177:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG178:![0-9]+]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG179:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64, !dbg [[DBG178]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], i64 0, i64 [[IDXPROM]], !dbg [[DBG178]] +// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX8]], align 4, !dbg [[DBG180:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG181:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX9]], i64 0, i64 0, !dbg [[DBG181]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG182:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP10]] to i64, !dbg [[DBG181]] +// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX10]], i64 0, i64 [[IDXPROM11]], !dbg [[DBG181]] +// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX12]], align 4, !dbg [[DBG183:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG184:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG184]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG185:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP11]] to i64, !dbg [[DBG184]] +// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG184]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX16]], align 4, !dbg [[DBG184]] +// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG186:![0-9]+]] +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG187:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM18:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG186]] +// CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX17]], i64 0, i64 [[IDXPROM18]], !dbg [[DBG186]] +// CHECK1-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX19]], align 4, !dbg [[DBG188:![0-9]+]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i8, ptr [[TMP8]], align 1, !dbg [[DBG189:![0-9]+]] +// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP14]] to i1, !dbg [[DBG189]] +// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TOBOOL]] to i32, !dbg [[DBG189]] +// CHECK1-NEXT: store i32 [[CONV]], ptr [[D]], align 4, !dbg [[DBG190:![0-9]+]] +// CHECK1-NEXT: ret void, !dbg [[DBG191:![0-9]+]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug___omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG183:![0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR2]] !dbg [[DBG192:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -425,64 +425,64 @@ int main() { // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META184:![0-9]+]], metadata !DIExpression()), !dbg [[DBG185:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META193:![0-9]+]], metadata !DIExpression()), !dbg [[DBG194:![0-9]+]] // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META186:![0-9]+]], metadata !DIExpression()), !dbg [[DBG185]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META195:![0-9]+]], metadata !DIExpression()), !dbg [[DBG194]] // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META187:![0-9]+]], metadata !DIExpression()), !dbg [[DBG185]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META196:![0-9]+]], metadata !DIExpression()), !dbg [[DBG194]] // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META188:![0-9]+]], metadata !DIExpression()), !dbg [[DBG185]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META197:![0-9]+]], metadata !DIExpression()), !dbg [[DBG194]] // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META189:![0-9]+]], metadata !DIExpression()), !dbg [[DBG185]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META198:![0-9]+]], metadata !DIExpression()), !dbg [[DBG194]] // CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META190:![0-9]+]], metadata !DIExpression()), !dbg [[DBG185]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG191:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG191]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG191]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG191]] -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG191]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG191]] -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG191]] -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG191]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG191]] -// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG191]] -// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG191]] -// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG191]] -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug___omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], ptr addrspace(1) [[TMP9]], i32 [[TMP6]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]]) #[[ATTR3]], !dbg [[DBG191]] -// CHECK1-NEXT: ret void, !dbg [[DBG191]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META199:![0-9]+]], metadata !DIExpression()), !dbg [[DBG194]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG200:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG200]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG200]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG200]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG200]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG200]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG200]] +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG200]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG200]] +// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG200]] +// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG200]] +// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG200]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug___omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], ptr addrspace(1) [[TMP9]], i32 [[TMP6]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]]) #[[ATTR4]], !dbg [[DBG200]] +// CHECK1-NEXT: ret void, !dbg [[DBG200]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37 -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR5]] !dbg [[DBG192:![0-9]+]] { +// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR6]] !dbg [[DBG201:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META193:![0-9]+]], metadata !DIExpression()), !dbg [[DBG194:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META202:![0-9]+]], metadata !DIExpression()), !dbg [[DBG203:![0-9]+]] // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META195:![0-9]+]], metadata !DIExpression()), !dbg [[DBG194]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META204:![0-9]+]], metadata !DIExpression()), !dbg [[DBG203]] // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META196:![0-9]+]], metadata !DIExpression()), !dbg [[DBG194]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META205:![0-9]+]], metadata !DIExpression()), !dbg [[DBG203]] // CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META197:![0-9]+]], metadata !DIExpression()), !dbg [[DBG194]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG198:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG198]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG198]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG198]] -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG198]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG198]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG198]] -// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr [[TMP3]] to ptr addrspace(1), !dbg [[DBG198]] -// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG198]] -// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG198]] -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug__(ptr addrspace(1) [[TMP7]], i32 [[TMP4]], ptr addrspace(1) [[TMP8]], ptr addrspace(1) [[TMP9]]) #[[ATTR3]], !dbg [[DBG198]] -// CHECK1-NEXT: ret void, !dbg [[DBG198]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META206:![0-9]+]], metadata !DIExpression()), !dbg [[DBG203]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG207:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG207]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG207]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG207]] +// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG207]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG207]] +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG207]] +// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr [[TMP3]] to ptr addrspace(1), !dbg [[DBG207]] +// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG207]] +// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG207]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug__(ptr addrspace(1) [[TMP7]], i32 [[TMP4]], ptr addrspace(1) [[TMP8]], ptr addrspace(1) [[TMP9]]) #[[ATTR4]], !dbg [[DBG207]] +// CHECK1-NEXT: ret void, !dbg [[DBG207]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_debug__ -// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], ptr addrspace(1) noalias noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG199:![0-9]+]] { +// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], ptr addrspace(1) noalias noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG208:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr addrspace(1), align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr addrspace(1), align 8 @@ -494,51 +494,51 @@ int main() { // CHECK1-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8 // CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META204:![0-9]+]], metadata !DIExpression()), !dbg [[DBG205:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META213:![0-9]+]], metadata !DIExpression()), !dbg [[DBG214:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META206:![0-9]+]], metadata !DIExpression()), !dbg [[DBG207:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META215:![0-9]+]], metadata !DIExpression()), !dbg [[DBG216:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META208:![0-9]+]], metadata !DIExpression()), !dbg [[DBG209:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META217:![0-9]+]], metadata !DIExpression()), !dbg [[DBG218:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META210:![0-9]+]], metadata !DIExpression()), !dbg [[DBG211:![0-9]+]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG212:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG212]] -// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG212]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG212]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[A_ADDR]], align 8, !dbg [[DBG212]] -// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG212]] -// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG212]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG212]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG212]] -// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG212]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG212]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG212]] -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG212]] -// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(1) [[TMP9]] to ptr, !dbg [[DBG212]] -// CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG212]] -// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG212]] -// CHECK1-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_kernel_environment), !dbg [[DBG212]] -// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP12]], -1, !dbg [[DBG212]] -// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG212]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META219:![0-9]+]], metadata !DIExpression()), !dbg [[DBG220:![0-9]+]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG221:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG221]] +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG221]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG221]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[A_ADDR]], align 8, !dbg [[DBG221]] +// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG221]] +// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG221]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG221]] +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG221]] +// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG221]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG221]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG221]] +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG221]] +// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(1) [[TMP9]] to ptr, !dbg [[DBG221]] +// CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG221]] +// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG221]] +// CHECK1-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_kernel_environment), !dbg [[DBG221]] +// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP12]], -1, !dbg [[DBG221]] +// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG221]] // CHECK1: user_code.entry: // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB11:[0-9]+]]) -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG213:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP14]], align 8, !dbg [[DBG213]] -// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG213]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP15]], align 8, !dbg [[DBG213]] -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG213]] -// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP16]], align 8, !dbg [[DBG213]] -// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG213]] -// CHECK1-NEXT: store ptr [[TMP11]], ptr [[TMP17]], align 8, !dbg [[DBG213]] -// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB11]], i32 [[TMP13]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4), !dbg [[DBG213]] -// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG214:![0-9]+]] -// CHECK1-NEXT: ret void, !dbg [[DBG216:![0-9]+]] +// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG222:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP14]], align 8, !dbg [[DBG222]] +// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG222]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP15]], align 8, !dbg [[DBG222]] +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG222]] +// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP16]], align 8, !dbg [[DBG222]] +// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG222]] +// CHECK1-NEXT: store ptr [[TMP11]], ptr [[TMP17]], align 8, !dbg [[DBG222]] +// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB11]], i32 [[TMP13]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4), !dbg [[DBG222]] +// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG223:![0-9]+]] +// CHECK1-NEXT: ret void, !dbg [[DBG225:![0-9]+]] // CHECK1: worker.exit: -// CHECK1-NEXT: ret void, !dbg [[DBG212]] +// CHECK1-NEXT: ret void, !dbg [[DBG221]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_debug___omp_outlined_debug__ -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], ptr addrspace(1) noalias noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG217:![0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], ptr addrspace(1) noalias noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR2]] !dbg [[DBG226:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -555,82 +555,82 @@ int main() { // CHECK1-NEXT: [[H:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[D:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META220:![0-9]+]], metadata !DIExpression()), !dbg [[DBG221:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META229:![0-9]+]], metadata !DIExpression()), !dbg [[DBG230:![0-9]+]] // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META222:![0-9]+]], metadata !DIExpression()), !dbg [[DBG221]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META231:![0-9]+]], metadata !DIExpression()), !dbg [[DBG230]] // CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META223:![0-9]+]], metadata !DIExpression()), !dbg [[DBG224:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META232:![0-9]+]], metadata !DIExpression()), !dbg [[DBG233:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META225:![0-9]+]], metadata !DIExpression()), !dbg [[DBG226:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META234:![0-9]+]], metadata !DIExpression()), !dbg [[DBG235:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META227:![0-9]+]], metadata !DIExpression()), !dbg [[DBG228:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META236:![0-9]+]], metadata !DIExpression()), !dbg [[DBG237:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META229:![0-9]+]], metadata !DIExpression()), !dbg [[DBG230:![0-9]+]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG231:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG231]] -// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG231]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG231]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[A_ADDR]], align 8, !dbg [[DBG231]] -// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG231]] -// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG231]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG231]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG231]] -// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG231]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG231]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG231]] -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG231]] -// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(1) [[TMP9]] to ptr, !dbg [[DBG231]] -// CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG231]] -// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG231]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[F]], metadata [[META232:![0-9]+]], metadata !DIExpression()), !dbg [[DBG234:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG235:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG235]] -// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX4]], i64 0, i64 1, !dbg [[DBG235]] -// CHECK1-NEXT: store ptr [[ARRAYIDX5]], ptr [[F]], align 8, !dbg [[DBG234]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[G]], metadata [[META236:![0-9]+]], metadata !DIExpression()), !dbg [[DBG237:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[G]], align 8, !dbg [[DBG237]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[H]], metadata [[META238:![0-9]+]], metadata !DIExpression()), !dbg [[DBG239:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 1, !dbg [[DBG240:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX6]], i64 0, i64 1, !dbg [[DBG240]] -// CHECK1-NEXT: store ptr [[ARRAYIDX7]], ptr [[H]], align 8, !dbg [[DBG239]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[D]], metadata [[META241:![0-9]+]], metadata !DIExpression()), !dbg [[DBG242:![0-9]+]] -// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[DBG242]] -// CHECK1-NEXT: store i32 5, ptr [[TMP5]], align 4, !dbg [[DBG243:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG244:![0-9]+]] -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG245:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64, !dbg [[DBG244]] -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX8]], i64 0, i64 [[IDXPROM]], !dbg [[DBG244]] -// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX9]], align 4, !dbg [[DBG246:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG247:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX10]], i64 0, i64 0, !dbg [[DBG247]] -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG248:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG247]] -// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM12]], !dbg [[DBG247]] -// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX13]], align 4, !dbg [[DBG249:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG250:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX14]], i64 0, i64 0, !dbg [[DBG250]] -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG251:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP14]] to i64, !dbg [[DBG250]] -// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX15]], i64 0, i64 [[IDXPROM16]], !dbg [[DBG250]] -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX17]], align 4, !dbg [[DBG250]] -// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG252:![0-9]+]] -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG253:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG252]] -// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG252]] -// CHECK1-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX20]], align 4, !dbg [[DBG254:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG255:![0-9]+]] -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG256:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP17]] to i64, !dbg [[DBG255]] -// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX23]], align 4, !dbg [[DBG255]] -// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP18]], 0, !dbg [[DBG255]] -// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8, !dbg [[DBG257:![0-9]+]] -// CHECK1-NEXT: store i8 [[FROMBOOL]], ptr [[TMP11]], align 1, !dbg [[DBG257]] -// CHECK1-NEXT: ret void, !dbg [[DBG258:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META238:![0-9]+]], metadata !DIExpression()), !dbg [[DBG239:![0-9]+]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG240:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG240]] +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG240]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG240]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[A_ADDR]], align 8, !dbg [[DBG240]] +// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG240]] +// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG240]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG240]] +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG240]] +// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG240]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG240]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG240]] +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG240]] +// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(1) [[TMP9]] to ptr, !dbg [[DBG240]] +// CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG240]] +// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG240]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[F]], metadata [[META241:![0-9]+]], metadata !DIExpression()), !dbg [[DBG243:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG244:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG244]] +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX4]], i64 0, i64 1, !dbg [[DBG244]] +// CHECK1-NEXT: store ptr [[ARRAYIDX5]], ptr [[F]], align 8, !dbg [[DBG243]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[G]], metadata [[META245:![0-9]+]], metadata !DIExpression()), !dbg [[DBG246:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[G]], align 8, !dbg [[DBG246]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[H]], metadata [[META247:![0-9]+]], metadata !DIExpression()), !dbg [[DBG248:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 1, !dbg [[DBG249:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX6]], i64 0, i64 1, !dbg [[DBG249]] +// CHECK1-NEXT: store ptr [[ARRAYIDX7]], ptr [[H]], align 8, !dbg [[DBG248]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[D]], metadata [[META250:![0-9]+]], metadata !DIExpression()), !dbg [[DBG251:![0-9]+]] +// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[DBG251]] +// CHECK1-NEXT: store i32 5, ptr [[TMP5]], align 4, !dbg [[DBG252:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG253:![0-9]+]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG254:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64, !dbg [[DBG253]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX8]], i64 0, i64 [[IDXPROM]], !dbg [[DBG253]] +// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX9]], align 4, !dbg [[DBG255:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG256:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX10]], i64 0, i64 0, !dbg [[DBG256]] +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG257:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG256]] +// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM12]], !dbg [[DBG256]] +// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX13]], align 4, !dbg [[DBG258:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG259:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX14]], i64 0, i64 0, !dbg [[DBG259]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG260:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP14]] to i64, !dbg [[DBG259]] +// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX15]], i64 0, i64 [[IDXPROM16]], !dbg [[DBG259]] +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX17]], align 4, !dbg [[DBG259]] +// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG261:![0-9]+]] +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG262:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG261]] +// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG261]] +// CHECK1-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX20]], align 4, !dbg [[DBG263:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG264:![0-9]+]] +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG265:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP17]] to i64, !dbg [[DBG264]] +// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX23]], align 4, !dbg [[DBG264]] +// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP18]], 0, !dbg [[DBG264]] +// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8, !dbg [[DBG266:![0-9]+]] +// CHECK1-NEXT: store i8 [[FROMBOOL]], ptr [[TMP11]], align 1, !dbg [[DBG266]] +// CHECK1-NEXT: ret void, !dbg [[DBG267:![0-9]+]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_debug___omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG259:![0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR2]] !dbg [[DBG268:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -639,62 +639,62 @@ int main() { // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META262:![0-9]+]], metadata !DIExpression()), !dbg [[DBG263:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META271:![0-9]+]], metadata !DIExpression()), !dbg [[DBG272:![0-9]+]] // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META264:![0-9]+]], metadata !DIExpression()), !dbg [[DBG263]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META273:![0-9]+]], metadata !DIExpression()), !dbg [[DBG272]] // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META265:![0-9]+]], metadata !DIExpression()), !dbg [[DBG263]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META274:![0-9]+]], metadata !DIExpression()), !dbg [[DBG272]] // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META266:![0-9]+]], metadata !DIExpression()), !dbg [[DBG263]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META275:![0-9]+]], metadata !DIExpression()), !dbg [[DBG272]] // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META267:![0-9]+]], metadata !DIExpression()), !dbg [[DBG263]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META276:![0-9]+]], metadata !DIExpression()), !dbg [[DBG272]] // CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META268:![0-9]+]], metadata !DIExpression()), !dbg [[DBG263]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG269:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG269]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG269]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG269]] -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG269]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG269]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG269]] -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG269]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG269]] -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG269]] -// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG269]] -// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG269]] -// CHECK1-NEXT: [[TMP12:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG269]] -// CHECK1-NEXT: [[TMP13:%.*]] = addrspacecast ptr [[TMP9]] to ptr addrspace(1), !dbg [[DBG269]] -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_debug___omp_outlined_debug__(ptr [[TMP4]], ptr [[TMP5]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]], ptr addrspace(1) [[TMP12]], ptr addrspace(1) [[TMP13]]) #[[ATTR3]], !dbg [[DBG269]] -// CHECK1-NEXT: ret void, !dbg [[DBG269]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META277:![0-9]+]], metadata !DIExpression()), !dbg [[DBG272]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG278:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG278]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG278]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG278]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG278]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG278]] +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG278]] +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG278]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG278]] +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG278]] +// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG278]] +// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG278]] +// CHECK1-NEXT: [[TMP12:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG278]] +// CHECK1-NEXT: [[TMP13:%.*]] = addrspacecast ptr [[TMP9]] to ptr addrspace(1), !dbg [[DBG278]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_debug___omp_outlined_debug__(ptr [[TMP4]], ptr [[TMP5]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]], ptr addrspace(1) [[TMP12]], ptr addrspace(1) [[TMP13]]) #[[ATTR4]], !dbg [[DBG278]] +// CHECK1-NEXT: ret void, !dbg [[DBG278]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51 -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR5]] !dbg [[DBG270:![0-9]+]] { +// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR6]] !dbg [[DBG279:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META273:![0-9]+]], metadata !DIExpression()), !dbg [[DBG274:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META282:![0-9]+]], metadata !DIExpression()), !dbg [[DBG283:![0-9]+]] // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META275:![0-9]+]], metadata !DIExpression()), !dbg [[DBG274]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META284:![0-9]+]], metadata !DIExpression()), !dbg [[DBG283]] // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META276:![0-9]+]], metadata !DIExpression()), !dbg [[DBG274]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META285:![0-9]+]], metadata !DIExpression()), !dbg [[DBG283]] // CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META277:![0-9]+]], metadata !DIExpression()), !dbg [[DBG274]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG278:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG278]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG278]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG278]] -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG278]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG278]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG278]] -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG278]] -// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[TMP4]] to ptr addrspace(1), !dbg [[DBG278]] -// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG278]] -// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG278]] -// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG278]] -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_debug__(ptr addrspace(1) [[TMP8]], ptr addrspace(1) [[TMP9]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]]) #[[ATTR3]], !dbg [[DBG278]] -// CHECK1-NEXT: ret void, !dbg [[DBG278]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META286:![0-9]+]], metadata !DIExpression()), !dbg [[DBG283]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG287:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG287]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG287]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG287]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG287]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG287]] +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG287]] +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG287]] +// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[TMP4]] to ptr addrspace(1), !dbg [[DBG287]] +// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG287]] +// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG287]] +// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG287]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_debug__(ptr addrspace(1) [[TMP8]], ptr addrspace(1) [[TMP9]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]]) #[[ATTR4]], !dbg [[DBG287]] +// CHECK1-NEXT: ret void, !dbg [[DBG287]] // diff --git a/clang/test/OpenMP/target_parallel_defaultmap_messages.cpp b/clang/test/OpenMP/target_parallel_defaultmap_messages.cpp index cd562a30e3226..4c226e9ca2aef 100644 --- a/clang/test/OpenMP/target_parallel_defaultmap_messages.cpp +++ b/clang/test/OpenMP/target_parallel_defaultmap_messages.cpp @@ -1,11 +1,11 @@ -// RUN: %clang_cc1 -verify -fopenmp %s -verify=expected,omp51 -Wuninitialized -DOMP51 -// RUN: %clang_cc1 -verify -fopenmp-simd %s -verify=expected,omp51 -Wuninitialized -DOMP51 +// RUN: %clang_cc1 -verify -fopenmp %s -verify=expected,omp51 -Wuninitialized -Wno-vla -DOMP51 +// RUN: %clang_cc1 -verify -fopenmp-simd %s -verify=expected,omp51 -Wuninitialized -Wno-vla -DOMP51 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 %s -verify=expected,omp5 -Wuninitialized -DOMP5 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 %s -verify=expected,omp5 -Wuninitialized -DOMP5 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 %s -verify=expected,omp5 -Wuninitialized -Wno-vla -DOMP5 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 %s -verify=expected,omp5 -Wuninitialized -Wno-vla -DOMP5 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 %s -verify=expected,omp45 -Wuninitialized -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 %s -verify=expected,omp45 -Wuninitialized +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 %s -verify=expected,omp45 -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 %s -verify=expected,omp45 -Wuninitialized -Wno-vla struct Bar { int a; diff --git a/clang/test/OpenMP/target_parallel_depend_codegen.cpp b/clang/test/OpenMP/target_parallel_depend_codegen.cpp index 18e124ba4db07..22bf654691de6 100644 --- a/clang/test/OpenMP/target_parallel_depend_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_depend_codegen.cpp @@ -1,37 +1,37 @@ // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s // SIMD-ONLY1-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/target_parallel_for_ast_print.cpp b/clang/test/OpenMP/target_parallel_for_ast_print.cpp index 6edbc26a11ab5..16c2175099acd 100644 --- a/clang/test/OpenMP/target_parallel_for_ast_print.cpp +++ b/clang/test/OpenMP/target_parallel_for_ast_print.cpp @@ -208,7 +208,7 @@ int main(int argc, char **argv) { for (int i = 0; i < 10; ++i) for (int j = 0; j < 10; ++j) foo(); - // CHECK-NEXT: #pragma omp target parallel for private(argc,b) firstprivate(argv,c) lastprivate(d,f) collapse(2) schedule(auto) ordered if(target: argc) num_threads(a) default(shared) shared(e) reduction(+: h) linear(a: -5) + // CHECK-NEXT: #pragma omp target parallel for private(argc,b) firstprivate(argv,c) lastprivate(d,f) collapse(2) schedule(auto) ordered if(target: argc) num_threads(a) default(shared) shared(e) reduction(+: h) linear(a: step(-5)) // CHECK-NEXT: for (int i = 0; i < 10; ++i) // CHECK-NEXT: for (int j = 0; j < 10; ++j) // CHECK-NEXT: foo(); diff --git a/clang/test/OpenMP/target_parallel_for_codegen.cpp b/clang/test/OpenMP/target_parallel_for_codegen.cpp index e3999498faa7d..c4680d1ea6c4a 100644 --- a/clang/test/OpenMP/target_parallel_for_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_for_codegen.cpp @@ -1,71 +1,71 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -395,7 +395,7 @@ int bar(int n){ // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 // CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() @@ -406,7 +406,7 @@ int bar(int n){ // CHECK1-NEXT: [[TMP24:%.*]] = load i64, ptr [[K]], align 8 // CHECK1-NEXT: store i64 [[TMP24]], ptr [[K_CASTED]], align 8 // CHECK1-NEXT: [[TMP25:%.*]] = load i64, ptr [[K_CASTED]], align 8 -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP23]], i64 [[TMP25]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP23]], i64 [[TMP25]]) #[[ATTR3]] // CHECK1-NEXT: store i32 12, ptr [[LIN]], align 4 // CHECK1-NEXT: [[TMP26:%.*]] = load i16, ptr [[AA]], align 2 // CHECK1-NEXT: store i16 [[TMP26]], ptr [[AA_CASTED]], align 2 @@ -516,12 +516,12 @@ int bar(int n){ // CHECK1-NEXT: [[TMP87:%.*]] = icmp ne i32 [[TMP86]], 0 // CHECK1-NEXT: br i1 [[TMP87]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] // CHECK1: omp_offload.failed9: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i64 [[TMP61]], i64 [[TMP63]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i64 [[TMP61]], i64 [[TMP63]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT10]] // CHECK1: omp_offload.cont10: // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1: omp_if.else: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i64 [[TMP61]], i64 [[TMP63]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i64 [[TMP61]], i64 [[TMP63]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: [[TMP88:%.*]] = load i32, ptr [[A]], align 4 @@ -637,12 +637,12 @@ int bar(int n){ // CHECK1-NEXT: [[TMP146:%.*]] = icmp ne i32 [[TMP145]], 0 // CHECK1-NEXT: br i1 [[TMP146]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] // CHECK1: omp_offload.failed18: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP90]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP92]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP90]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP92]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT19]] // CHECK1: omp_offload.cont19: // CHECK1-NEXT: br label [[OMP_IF_END21:%.*]] // CHECK1: omp_if.else20: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP90]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP92]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP90]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP92]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_IF_END21]] // CHECK1: omp_if.end21: // CHECK1-NEXT: [[TMP147:%.*]] = load i32, ptr [[A]], align 4 @@ -659,7 +659,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -736,7 +736,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 @@ -755,7 +755,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -862,7 +862,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -971,7 +971,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 @@ -1000,7 +1000,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 @@ -1040,7 +1040,7 @@ int bar(int n){ // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !24 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 -// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] +// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24 // CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24 @@ -1085,7 +1085,7 @@ int bar(int n){ // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP17]], align 4 // CHECK1-NEXT: store i32 [[TMP36]], ptr [[A_CASTED_I]], align 4, !noalias !24 // CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[A_CASTED_I]], align 8, !noalias !24 -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128(i64 [[TMP33]], i64 [[TMP35]], i64 [[TMP37]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128(i64 [[TMP33]], i64 [[TMP35]], i64 [[TMP37]]) #[[ATTR3]] // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] // CHECK1: .omp_outlined..exit: // CHECK1-NEXT: ret i32 0 @@ -1111,7 +1111,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1227,7 +1227,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1504,12 +1504,12 @@ int bar(int n){ // CHECK1-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 // CHECK1-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1: omp_if.else: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]] @@ -1612,12 +1612,12 @@ int bar(int n){ // CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 // CHECK1-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1: omp_if.else: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4 @@ -1700,12 +1700,12 @@ int bar(int n){ // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1: omp_if.else: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4 @@ -1738,7 +1738,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1854,7 +1854,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1897,7 +1897,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1976,7 +1976,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK1-SAME: () #[[ATTR6]] { +// CHECK1-SAME: () #[[ATTR5]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) // CHECK1-NEXT: ret void @@ -2068,7 +2068,7 @@ int bar(int n){ // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 // CHECK3-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() @@ -2076,7 +2076,7 @@ int bar(int n){ // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[A]], align 4 // CHECK3-NEXT: store i32 [[TMP20]], ptr [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP21]], ptr [[K]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP21]], ptr [[K]]) #[[ATTR3]] // CHECK3-NEXT: store i32 12, ptr [[LIN]], align 4 // CHECK3-NEXT: [[TMP22:%.*]] = load i16, ptr [[AA]], align 2 // CHECK3-NEXT: store i16 [[TMP22]], ptr [[AA_CASTED]], align 2 @@ -2186,12 +2186,12 @@ int bar(int n){ // CHECK3-NEXT: [[TMP83:%.*]] = icmp ne i32 [[TMP82]], 0 // CHECK3-NEXT: br i1 [[TMP83]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] // CHECK3: omp_offload.failed9: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i32 [[TMP57]], i32 [[TMP59]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i32 [[TMP57]], i32 [[TMP59]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT10]] // CHECK3: omp_offload.cont10: // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3: omp_if.else: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i32 [[TMP57]], i32 [[TMP59]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i32 [[TMP57]], i32 [[TMP59]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_IF_END]] // CHECK3: omp_if.end: // CHECK3-NEXT: [[TMP84:%.*]] = load i32, ptr [[A]], align 4 @@ -2309,12 +2309,12 @@ int bar(int n){ // CHECK3-NEXT: [[TMP144:%.*]] = icmp ne i32 [[TMP143]], 0 // CHECK3-NEXT: br i1 [[TMP144]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] // CHECK3: omp_offload.failed18: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP86]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP88]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP86]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP88]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT19]] // CHECK3: omp_offload.cont19: // CHECK3-NEXT: br label [[OMP_IF_END21:%.*]] // CHECK3: omp_if.else20: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP86]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP88]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP86]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP88]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_IF_END21]] // CHECK3: omp_if.end21: // CHECK3-NEXT: [[TMP145:%.*]] = load i32, ptr [[A]], align 4 @@ -2331,7 +2331,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -2408,7 +2408,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 4 @@ -2424,7 +2424,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -2532,7 +2532,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -2641,7 +2641,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK3-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK3-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 @@ -2670,7 +2670,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4 @@ -2710,7 +2710,7 @@ int bar(int n){ // CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !25 // CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 // CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 -// CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] +// CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] // CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25 // CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25 // CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25 @@ -2755,7 +2755,7 @@ int bar(int n){ // CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP17]], align 4 // CHECK3-NEXT: store i32 [[TMP36]], ptr [[A_CASTED_I]], align 4, !noalias !25 // CHECK3-NEXT: [[TMP37:%.*]] = load i32, ptr [[A_CASTED_I]], align 4, !noalias !25 -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128(i32 [[TMP33]], i32 [[TMP35]], i32 [[TMP37]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128(i32 [[TMP33]], i32 [[TMP35]], i32 [[TMP37]]) #[[ATTR3]] // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] // CHECK3: .omp_outlined..exit: // CHECK3-NEXT: ret i32 0 @@ -2781,7 +2781,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -2897,7 +2897,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -3174,12 +3174,12 @@ int bar(int n){ // CHECK3-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 // CHECK3-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3: omp_if.else: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_IF_END]] // CHECK3: omp_if.end: // CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]] @@ -3282,12 +3282,12 @@ int bar(int n){ // CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 // CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3: omp_if.else: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_IF_END]] // CHECK3: omp_if.end: // CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4 @@ -3370,12 +3370,12 @@ int bar(int n){ // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3: omp_if.else: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_IF_END]] // CHECK3: omp_if.end: // CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4 @@ -3408,7 +3408,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -3524,7 +3524,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -3567,7 +3567,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -3646,7 +3646,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK3-SAME: () #[[ATTR6]] { +// CHECK3-SAME: () #[[ATTR5]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) // CHECK3-NEXT: ret void @@ -3660,7 +3660,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined -// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -3762,7 +3762,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined -// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -3790,7 +3790,7 @@ int bar(int n){ // CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK9-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR4:[0-9]+]] // CHECK9-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 // CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 // CHECK9-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 @@ -3871,7 +3871,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK9-SAME: () #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: ret i64 0 // @@ -3896,7 +3896,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined -// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -4012,7 +4012,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined -// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -4183,7 +4183,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined -// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -4229,7 +4229,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined -// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -4339,7 +4339,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined -// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -4425,7 +4425,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined -// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -4527,7 +4527,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined -// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -4555,7 +4555,7 @@ int bar(int n){ // CHECK11-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK11-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR4:[0-9]+]] // CHECK11-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 // CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 // CHECK11-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 @@ -4636,7 +4636,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK11-SAME: () #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: ret i64 0 // @@ -4661,7 +4661,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined -// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -4777,7 +4777,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined -// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -4948,7 +4948,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined -// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -4994,7 +4994,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined -// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -5104,7 +5104,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined -// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -5271,7 +5271,7 @@ int bar(int n){ // CHECK17-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 // CHECK17-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]] // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK17: omp_offload.cont: // CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() @@ -5282,7 +5282,7 @@ int bar(int n){ // CHECK17-NEXT: [[TMP24:%.*]] = load i64, ptr [[K]], align 8 // CHECK17-NEXT: store i64 [[TMP24]], ptr [[K_CASTED]], align 8 // CHECK17-NEXT: [[TMP25:%.*]] = load i64, ptr [[K_CASTED]], align 8 -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP23]], i64 [[TMP25]]) #[[ATTR4]] +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP23]], i64 [[TMP25]]) #[[ATTR3]] // CHECK17-NEXT: store i32 12, ptr [[LIN]], align 4 // CHECK17-NEXT: [[TMP26:%.*]] = load i16, ptr [[AA]], align 2 // CHECK17-NEXT: store i16 [[TMP26]], ptr [[AA_CASTED]], align 2 @@ -5392,12 +5392,12 @@ int bar(int n){ // CHECK17-NEXT: [[TMP87:%.*]] = icmp ne i32 [[TMP86]], 0 // CHECK17-NEXT: br i1 [[TMP87]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] // CHECK17: omp_offload.failed9: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i64 [[TMP61]], i64 [[TMP63]]) #[[ATTR4]] +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i64 [[TMP61]], i64 [[TMP63]]) #[[ATTR3]] // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT10]] // CHECK17: omp_offload.cont10: // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] // CHECK17: omp_if.else: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i64 [[TMP61]], i64 [[TMP63]]) #[[ATTR4]] +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i64 [[TMP61]], i64 [[TMP63]]) #[[ATTR3]] // CHECK17-NEXT: br label [[OMP_IF_END]] // CHECK17: omp_if.end: // CHECK17-NEXT: [[TMP88:%.*]] = load i32, ptr [[A]], align 4 @@ -5513,12 +5513,12 @@ int bar(int n){ // CHECK17-NEXT: [[TMP146:%.*]] = icmp ne i32 [[TMP145]], 0 // CHECK17-NEXT: br i1 [[TMP146]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] // CHECK17: omp_offload.failed18: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP90]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP92]]) #[[ATTR4]] +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP90]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP92]]) #[[ATTR3]] // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT19]] // CHECK17: omp_offload.cont19: // CHECK17-NEXT: br label [[OMP_IF_END21:%.*]] // CHECK17: omp_if.else20: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP90]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP92]]) #[[ATTR4]] +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP90]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP92]]) #[[ATTR3]] // CHECK17-NEXT: br label [[OMP_IF_END21]] // CHECK17: omp_if.end21: // CHECK17-NEXT: [[TMP147:%.*]] = load i32, ptr [[A]], align 4 @@ -5535,7 +5535,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -5612,7 +5612,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 @@ -5631,7 +5631,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -5738,7 +5738,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -5847,7 +5847,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK17-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK17-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 @@ -5876,7 +5876,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK17-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK17-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 @@ -5916,7 +5916,7 @@ int bar(int n){ // CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !24 // CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 // CHECK17-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 -// CHECK17-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] +// CHECK17-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] // CHECK17-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24 // CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24 // CHECK17-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24 @@ -5961,7 +5961,7 @@ int bar(int n){ // CHECK17-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP17]], align 4 // CHECK17-NEXT: store i32 [[TMP36]], ptr [[A_CASTED_I]], align 4, !noalias !24 // CHECK17-NEXT: [[TMP37:%.*]] = load i64, ptr [[A_CASTED_I]], align 8, !noalias !24 -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128(i64 [[TMP33]], i64 [[TMP35]], i64 [[TMP37]]) #[[ATTR4]] +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128(i64 [[TMP33]], i64 [[TMP35]], i64 [[TMP37]]) #[[ATTR3]] // CHECK17-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] // CHECK17: .omp_outlined..exit: // CHECK17-NEXT: ret i32 0 @@ -5987,7 +5987,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -6103,7 +6103,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -6380,12 +6380,12 @@ int bar(int n){ // CHECK17-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 // CHECK17-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR4]] +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]] // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK17: omp_offload.cont: // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] // CHECK17: omp_if.else: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR4]] +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]] // CHECK17-NEXT: br label [[OMP_IF_END]] // CHECK17: omp_if.end: // CHECK17-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]] @@ -6488,12 +6488,12 @@ int bar(int n){ // CHECK17-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 // CHECK17-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR4]] +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]] // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK17: omp_offload.cont: // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] // CHECK17: omp_if.else: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR4]] +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]] // CHECK17-NEXT: br label [[OMP_IF_END]] // CHECK17: omp_if.end: // CHECK17-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4 @@ -6576,12 +6576,12 @@ int bar(int n){ // CHECK17-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 // CHECK17-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK17: omp_offload.cont: // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] // CHECK17: omp_if.else: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK17-NEXT: br label [[OMP_IF_END]] // CHECK17: omp_if.end: // CHECK17-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4 @@ -6614,7 +6614,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -6730,7 +6730,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -6773,7 +6773,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -6852,7 +6852,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK17-SAME: () #[[ATTR6]] { +// CHECK17-SAME: () #[[ATTR5]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: call void @__tgt_register_requires(i64 1) // CHECK17-NEXT: ret void @@ -6944,7 +6944,7 @@ int bar(int n){ // CHECK19-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 // CHECK19-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]] // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK19: omp_offload.cont: // CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() @@ -6952,7 +6952,7 @@ int bar(int n){ // CHECK19-NEXT: [[TMP20:%.*]] = load i32, ptr [[A]], align 4 // CHECK19-NEXT: store i32 [[TMP20]], ptr [[A_CASTED]], align 4 // CHECK19-NEXT: [[TMP21:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP21]], ptr [[K]]) #[[ATTR4]] +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP21]], ptr [[K]]) #[[ATTR3]] // CHECK19-NEXT: store i32 12, ptr [[LIN]], align 4 // CHECK19-NEXT: [[TMP22:%.*]] = load i16, ptr [[AA]], align 2 // CHECK19-NEXT: store i16 [[TMP22]], ptr [[AA_CASTED]], align 2 @@ -7062,12 +7062,12 @@ int bar(int n){ // CHECK19-NEXT: [[TMP83:%.*]] = icmp ne i32 [[TMP82]], 0 // CHECK19-NEXT: br i1 [[TMP83]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] // CHECK19: omp_offload.failed9: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i32 [[TMP57]], i32 [[TMP59]]) #[[ATTR4]] +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i32 [[TMP57]], i32 [[TMP59]]) #[[ATTR3]] // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT10]] // CHECK19: omp_offload.cont10: // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] // CHECK19: omp_if.else: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i32 [[TMP57]], i32 [[TMP59]]) #[[ATTR4]] +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i32 [[TMP57]], i32 [[TMP59]]) #[[ATTR3]] // CHECK19-NEXT: br label [[OMP_IF_END]] // CHECK19: omp_if.end: // CHECK19-NEXT: [[TMP84:%.*]] = load i32, ptr [[A]], align 4 @@ -7185,12 +7185,12 @@ int bar(int n){ // CHECK19-NEXT: [[TMP144:%.*]] = icmp ne i32 [[TMP143]], 0 // CHECK19-NEXT: br i1 [[TMP144]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] // CHECK19: omp_offload.failed18: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP86]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP88]]) #[[ATTR4]] +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP86]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP88]]) #[[ATTR3]] // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT19]] // CHECK19: omp_offload.cont19: // CHECK19-NEXT: br label [[OMP_IF_END21:%.*]] // CHECK19: omp_if.else20: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP86]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP88]]) #[[ATTR4]] +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP86]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP88]]) #[[ATTR3]] // CHECK19-NEXT: br label [[OMP_IF_END21]] // CHECK19: omp_if.end21: // CHECK19-NEXT: [[TMP145:%.*]] = load i32, ptr [[A]], align 4 @@ -7207,7 +7207,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -7284,7 +7284,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK19-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 4 @@ -7300,7 +7300,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -7408,7 +7408,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -7517,7 +7517,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK19-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK19-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 @@ -7546,7 +7546,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK19-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK19-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4 @@ -7586,7 +7586,7 @@ int bar(int n){ // CHECK19-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !25 // CHECK19-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 // CHECK19-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 -// CHECK19-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] +// CHECK19-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] // CHECK19-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25 // CHECK19-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25 // CHECK19-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25 @@ -7631,7 +7631,7 @@ int bar(int n){ // CHECK19-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP17]], align 4 // CHECK19-NEXT: store i32 [[TMP36]], ptr [[A_CASTED_I]], align 4, !noalias !25 // CHECK19-NEXT: [[TMP37:%.*]] = load i32, ptr [[A_CASTED_I]], align 4, !noalias !25 -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128(i32 [[TMP33]], i32 [[TMP35]], i32 [[TMP37]]) #[[ATTR4]] +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128(i32 [[TMP33]], i32 [[TMP35]], i32 [[TMP37]]) #[[ATTR3]] // CHECK19-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] // CHECK19: .omp_outlined..exit: // CHECK19-NEXT: ret i32 0 @@ -7657,7 +7657,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -7773,7 +7773,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -8050,12 +8050,12 @@ int bar(int n){ // CHECK19-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 // CHECK19-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR4]] +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK19: omp_offload.cont: // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] // CHECK19: omp_if.else: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR4]] +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] // CHECK19-NEXT: br label [[OMP_IF_END]] // CHECK19: omp_if.end: // CHECK19-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]] @@ -8158,12 +8158,12 @@ int bar(int n){ // CHECK19-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 // CHECK19-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR4]] +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]] // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK19: omp_offload.cont: // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] // CHECK19: omp_if.else: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR4]] +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]] // CHECK19-NEXT: br label [[OMP_IF_END]] // CHECK19: omp_if.end: // CHECK19-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4 @@ -8246,12 +8246,12 @@ int bar(int n){ // CHECK19-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 // CHECK19-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK19: omp_offload.cont: // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] // CHECK19: omp_if.else: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK19-NEXT: br label [[OMP_IF_END]] // CHECK19: omp_if.end: // CHECK19-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4 @@ -8284,7 +8284,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -8400,7 +8400,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -8443,7 +8443,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -8522,7 +8522,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK19-SAME: () #[[ATTR6]] { +// CHECK19-SAME: () #[[ATTR5]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: call void @__tgt_register_requires(i64 1) // CHECK19-NEXT: ret void diff --git a/clang/test/OpenMP/target_parallel_for_debug_codegen.cpp b/clang/test/OpenMP/target_parallel_for_debug_codegen.cpp index 12dbf4229f5ba..a49c0c92a9e3f 100644 --- a/clang/test/OpenMP/target_parallel_for_debug_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_for_debug_codegen.cpp @@ -55,7 +55,7 @@ int main() { return 0; } // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug__ -// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]], i1 noundef zeroext [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG13:![0-9]+]] { +// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]], i1 noundef zeroext [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG22:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr addrspace(1), align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -68,56 +68,56 @@ int main() { // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8 // CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META31:![0-9]+]], metadata !DIExpression()), !dbg [[DBG32:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META40:![0-9]+]], metadata !DIExpression()), !dbg [[DBG41:![0-9]+]] // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META33:![0-9]+]], metadata !DIExpression()), !dbg [[DBG34:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META42:![0-9]+]], metadata !DIExpression()), !dbg [[DBG43:![0-9]+]] // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META35:![0-9]+]], metadata !DIExpression()), !dbg [[DBG36:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META44:![0-9]+]], metadata !DIExpression()), !dbg [[DBG45:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META37:![0-9]+]], metadata !DIExpression()), !dbg [[DBG38:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META46:![0-9]+]], metadata !DIExpression()), !dbg [[DBG47:![0-9]+]] // CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[DOTCAPTURE_EXPR_]] to i8 // CHECK1-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTCAPTURE_EXPR__ADDR]], metadata [[META39:![0-9]+]], metadata !DIExpression()), !dbg [[DBG40:![0-9]+]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG41:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG41]] -// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG41]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG41]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG41]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8, !dbg [[DBG41]] -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG41]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG41]] -// CHECK1-NEXT: [[TMP6:%.*]] = addrspacecast ptr addrspace(1) [[TMP5]] to ptr, !dbg [[DBG41]] -// CHECK1-NEXT: store ptr [[TMP6]], ptr [[_TMP2]], align 8, !dbg [[DBG41]] -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG41]] -// CHECK1-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_kernel_environment), !dbg [[DBG41]] -// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1, !dbg [[DBG41]] -// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG41]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTCAPTURE_EXPR__ADDR]], metadata [[META48:![0-9]+]], metadata !DIExpression()), !dbg [[DBG49:![0-9]+]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG50:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG50]] +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG50]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG50]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG50]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8, !dbg [[DBG50]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG50]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG50]] +// CHECK1-NEXT: [[TMP6:%.*]] = addrspacecast ptr addrspace(1) [[TMP5]] to ptr, !dbg [[DBG50]] +// CHECK1-NEXT: store ptr [[TMP6]], ptr [[_TMP2]], align 8, !dbg [[DBG50]] +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG50]] +// CHECK1-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_kernel_environment), !dbg [[DBG50]] +// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1, !dbg [[DBG50]] +// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG50]] // CHECK1: user_code.entry: // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6:[0-9]+]]) -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG42:![0-9]+]] -// CHECK1-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4, !dbg [[DBG42]] -// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG42]] -// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG42]] -// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP12]], align 8, !dbg [[DBG42]] -// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG42]] -// CHECK1-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP11]] to ptr, !dbg [[DBG42]] -// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8, !dbg [[DBG42]] -// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG42]] -// CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP15]], align 8, !dbg [[DBG42]] -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG42]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[TMP16]], align 8, !dbg [[DBG42]] -// CHECK1-NEXT: [[TMP17:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !dbg [[DBG43:![0-9]+]] -// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP17]] to i1, !dbg [[DBG43]] -// CHECK1-NEXT: [[TMP18:%.*]] = zext i1 [[TOBOOL]] to i32, !dbg [[DBG42]] -// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB6]], i32 [[TMP9]], i32 [[TMP18]], i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4), !dbg [[DBG42]] -// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG45:![0-9]+]] -// CHECK1-NEXT: ret void, !dbg [[DBG46:![0-9]+]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG51:![0-9]+]] +// CHECK1-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4, !dbg [[DBG51]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG51]] +// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG51]] +// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP12]], align 8, !dbg [[DBG51]] +// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG51]] +// CHECK1-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP11]] to ptr, !dbg [[DBG51]] +// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8, !dbg [[DBG51]] +// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG51]] +// CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP15]], align 8, !dbg [[DBG51]] +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG51]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[TMP16]], align 8, !dbg [[DBG51]] +// CHECK1-NEXT: [[TMP17:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !dbg [[DBG52:![0-9]+]] +// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP17]] to i1, !dbg [[DBG52]] +// CHECK1-NEXT: [[TMP18:%.*]] = zext i1 [[TOBOOL]] to i32, !dbg [[DBG51]] +// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB6]], i32 [[TMP9]], i32 [[TMP18]], i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4), !dbg [[DBG51]] +// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG54:![0-9]+]] +// CHECK1-NEXT: ret void, !dbg [[DBG55:![0-9]+]] // CHECK1: worker.exit: -// CHECK1-NEXT: ret void, !dbg [[DBG41]] +// CHECK1-NEXT: ret void, !dbg [[DBG50]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug___omp_outlined_debug__ -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG47:![0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR2:[0-9]+]] !dbg [[DBG56:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -141,149 +141,149 @@ int main() { // CHECK1-NEXT: [[H:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[D:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META54:![0-9]+]], metadata !DIExpression()), !dbg [[DBG55:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META63:![0-9]+]], metadata !DIExpression()), !dbg [[DBG64:![0-9]+]] // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META56:![0-9]+]], metadata !DIExpression()), !dbg [[DBG55]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META65:![0-9]+]], metadata !DIExpression()), !dbg [[DBG64]] // CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META57:![0-9]+]], metadata !DIExpression()), !dbg [[DBG58:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META66:![0-9]+]], metadata !DIExpression()), !dbg [[DBG67:![0-9]+]] // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META59:![0-9]+]], metadata !DIExpression()), !dbg [[DBG60:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META68:![0-9]+]], metadata !DIExpression()), !dbg [[DBG69:![0-9]+]] // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META61:![0-9]+]], metadata !DIExpression()), !dbg [[DBG62:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META70:![0-9]+]], metadata !DIExpression()), !dbg [[DBG71:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META63:![0-9]+]], metadata !DIExpression()), !dbg [[DBG64:![0-9]+]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG65:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG65]] -// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG65]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG65]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG65]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8, !dbg [[DBG65]] -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG65]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG65]] -// CHECK1-NEXT: [[TMP6:%.*]] = addrspacecast ptr addrspace(1) [[TMP5]] to ptr, !dbg [[DBG65]] -// CHECK1-NEXT: store ptr [[TMP6]], ptr [[_TMP2]], align 8, !dbg [[DBG65]] -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG65]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_IV]], metadata [[META66:![0-9]+]], metadata !DIExpression()), !dbg [[DBG55]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_LB]], metadata [[META67:![0-9]+]], metadata !DIExpression()), !dbg [[DBG55]] -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG68:![0-9]+]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_UB]], metadata [[META69:![0-9]+]], metadata !DIExpression()), !dbg [[DBG55]] -// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_STRIDE]], metadata [[META70:![0-9]+]], metadata !DIExpression()), !dbg [[DBG55]] -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_IS_LAST]], metadata [[META71:![0-9]+]], metadata !DIExpression()), !dbg [[DBG55]] -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B4]], metadata [[META72:![0-9]+]], metadata !DIExpression()), !dbg [[DBG55]] -// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B4]], ptr align 4 [[TMP4]], i64 400, i1 false), !dbg [[DBG65]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[I]], metadata [[META73:![0-9]+]], metadata !DIExpression()), !dbg [[DBG55]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG65]] -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4, !dbg [[DBG65]] -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3:[0-9]+]], i32 [[TMP9]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG74:![0-9]+]] -// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG65]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META72:![0-9]+]], metadata !DIExpression()), !dbg [[DBG73:![0-9]+]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG74:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG74]] +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG74]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG74]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG74]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8, !dbg [[DBG74]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG74]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG74]] +// CHECK1-NEXT: [[TMP6:%.*]] = addrspacecast ptr addrspace(1) [[TMP5]] to ptr, !dbg [[DBG74]] +// CHECK1-NEXT: store ptr [[TMP6]], ptr [[_TMP2]], align 8, !dbg [[DBG74]] +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG74]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_IV]], metadata [[META75:![0-9]+]], metadata !DIExpression()), !dbg [[DBG64]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_LB]], metadata [[META76:![0-9]+]], metadata !DIExpression()), !dbg [[DBG64]] +// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG77:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_UB]], metadata [[META78:![0-9]+]], metadata !DIExpression()), !dbg [[DBG64]] +// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_STRIDE]], metadata [[META79:![0-9]+]], metadata !DIExpression()), !dbg [[DBG64]] +// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_IS_LAST]], metadata [[META80:![0-9]+]], metadata !DIExpression()), !dbg [[DBG64]] +// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B4]], metadata [[META81:![0-9]+]], metadata !DIExpression()), !dbg [[DBG64]] +// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B4]], ptr align 4 [[TMP4]], i64 400, i1 false), !dbg [[DBG74]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[I]], metadata [[META82:![0-9]+]], metadata !DIExpression()), !dbg [[DBG64]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG74]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4, !dbg [[DBG74]] +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3:[0-9]+]], i32 [[TMP9]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG83:![0-9]+]] +// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG74]] // CHECK1: omp.dispatch.cond: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9, !dbg [[DBG68]] -// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG68]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9, !dbg [[DBG77]] +// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG77]] // CHECK1: cond.true: -// CHECK1-NEXT: br label [[COND_END:%.*]], !dbg [[DBG68]] +// CHECK1-NEXT: br label [[COND_END:%.*]], !dbg [[DBG77]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: br label [[COND_END]], !dbg [[DBG68]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: br label [[COND_END]], !dbg [[DBG77]] // CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ], !dbg [[DBG68]] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]], !dbg [[DBG65]] -// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG65]] +// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ], !dbg [[DBG77]] +// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]], !dbg [[DBG74]] +// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG74]] // CHECK1: omp.dispatch.body: -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG65]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG74]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]], !dbg [[DBG65]] -// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG65]] +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]], !dbg [[DBG74]] +// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG74]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1, !dbg [[DBG75:![0-9]+]] -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG75]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG75]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[F]], metadata [[META76:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG80:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG80]] -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], i64 0, i64 1, !dbg [[DBG80]] -// CHECK1-NEXT: store ptr [[ARRAYIDX8]], ptr [[F]], align 8, !dbg [[DBG79]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[G]], metadata [[META81:![0-9]+]], metadata !DIExpression()), !dbg [[DBG82:![0-9]+]] -// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[DBG82]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[H]], metadata [[META83:![0-9]+]], metadata !DIExpression()), !dbg [[DBG84:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 1, !dbg [[DBG85:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX9]], i64 0, i64 1, !dbg [[DBG85]] -// CHECK1-NEXT: store ptr [[ARRAYIDX10]], ptr [[H]], align 8, !dbg [[DBG84]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[D]], metadata [[META86:![0-9]+]], metadata !DIExpression()), !dbg [[DBG87:![0-9]+]] -// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[DBG87]] -// CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG88:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG89:![0-9]+]] -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG90:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64, !dbg [[DBG89]] -// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM]], !dbg [[DBG89]] -// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX12]], align 4, !dbg [[DBG91:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG92:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG92]] -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG93:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG92]] -// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG92]] -// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX16]], align 4, !dbg [[DBG94:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG95:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX17]], i64 0, i64 0, !dbg [[DBG95]] -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG96:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP20]] to i64, !dbg [[DBG95]] -// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG95]] -// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[ARRAYIDX20]], align 4, !dbg [[DBG95]] -// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG97:![0-9]+]] -// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG98:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG97]] -// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG97]] -// CHECK1-NEXT: store i32 [[TMP21]], ptr [[ARRAYIDX23]], align 4, !dbg [[DBG99:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG100:![0-9]+]] -// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG101:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG100]] -// CHECK1-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX24]], i64 0, i64 [[IDXPROM25]], !dbg [[DBG100]] -// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[ARRAYIDX26]], align 4, !dbg [[DBG100]] -// CHECK1-NEXT: [[TMP25:%.*]] = load i8, ptr [[TMP7]], align 1, !dbg [[DBG102:![0-9]+]] -// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP25]] to i1, !dbg [[DBG102]] -// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TOBOOL]] to i32, !dbg [[DBG102]] -// CHECK1-NEXT: [[OR:%.*]] = or i32 [[CONV]], [[TMP24]], !dbg [[DBG102]] -// CHECK1-NEXT: [[TOBOOL27:%.*]] = icmp ne i32 [[OR]], 0, !dbg [[DBG102]] -// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL27]] to i8, !dbg [[DBG102]] -// CHECK1-NEXT: store i8 [[FROMBOOL]], ptr [[TMP7]], align 1, !dbg [[DBG102]] -// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG103:![0-9]+]] +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1, !dbg [[DBG84:![0-9]+]] +// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG84]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG84]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[F]], metadata [[META85:![0-9]+]], metadata !DIExpression()), !dbg [[DBG88:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG89:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG89]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], i64 0, i64 1, !dbg [[DBG89]] +// CHECK1-NEXT: store ptr [[ARRAYIDX8]], ptr [[F]], align 8, !dbg [[DBG88]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[G]], metadata [[META90:![0-9]+]], metadata !DIExpression()), !dbg [[DBG91:![0-9]+]] +// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[DBG91]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[H]], metadata [[META92:![0-9]+]], metadata !DIExpression()), !dbg [[DBG93:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 1, !dbg [[DBG94:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX9]], i64 0, i64 1, !dbg [[DBG94]] +// CHECK1-NEXT: store ptr [[ARRAYIDX10]], ptr [[H]], align 8, !dbg [[DBG93]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[D]], metadata [[META95:![0-9]+]], metadata !DIExpression()), !dbg [[DBG96:![0-9]+]] +// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[DBG96]] +// CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG97:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG98:![0-9]+]] +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG99:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64, !dbg [[DBG98]] +// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM]], !dbg [[DBG98]] +// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX12]], align 4, !dbg [[DBG100:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG101:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG101]] +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG102:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG101]] +// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG101]] +// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX16]], align 4, !dbg [[DBG103:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG104:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX17]], i64 0, i64 0, !dbg [[DBG104]] +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG105:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP20]] to i64, !dbg [[DBG104]] +// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG104]] +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[ARRAYIDX20]], align 4, !dbg [[DBG104]] +// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG106:![0-9]+]] +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG107:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG106]] +// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG106]] +// CHECK1-NEXT: store i32 [[TMP21]], ptr [[ARRAYIDX23]], align 4, !dbg [[DBG108:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG109:![0-9]+]] +// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG110:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG109]] +// CHECK1-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX24]], i64 0, i64 [[IDXPROM25]], !dbg [[DBG109]] +// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[ARRAYIDX26]], align 4, !dbg [[DBG109]] +// CHECK1-NEXT: [[TMP25:%.*]] = load i8, ptr [[TMP7]], align 1, !dbg [[DBG111:![0-9]+]] +// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP25]] to i1, !dbg [[DBG111]] +// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TOBOOL]] to i32, !dbg [[DBG111]] +// CHECK1-NEXT: [[OR:%.*]] = or i32 [[CONV]], [[TMP24]], !dbg [[DBG111]] +// CHECK1-NEXT: [[TOBOOL27:%.*]] = icmp ne i32 [[OR]], 0, !dbg [[DBG111]] +// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL27]] to i8, !dbg [[DBG111]] +// CHECK1-NEXT: store i8 [[FROMBOOL]], ptr [[TMP7]], align 1, !dbg [[DBG111]] +// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG112:![0-9]+]] // CHECK1: omp.body.continue: -// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG74]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG83]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP26]], 1, !dbg [[DBG65]] -// CHECK1-NEXT: store i32 [[ADD28]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG65]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG74]], !llvm.loop [[LOOP104:![0-9]+]] +// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP26]], 1, !dbg [[DBG74]] +// CHECK1-NEXT: store i32 [[ADD28]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG74]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG83]], !llvm.loop [[LOOP113:![0-9]+]] // CHECK1: omp.inner.for.end: -// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG74]] +// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG83]] // CHECK1: omp.dispatch.inc: -// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP27]], [[TMP28]], !dbg [[DBG65]] -// CHECK1-NEXT: store i32 [[ADD29]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG65]] -// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[ADD30:%.*]] = add nsw i32 [[TMP29]], [[TMP30]], !dbg [[DBG65]] -// CHECK1-NEXT: store i32 [[ADD30]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG65]] -// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG74]], !llvm.loop [[LOOP106:![0-9]+]] +// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP27]], [[TMP28]], !dbg [[DBG74]] +// CHECK1-NEXT: store i32 [[ADD29]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG74]] +// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[ADD30:%.*]] = add nsw i32 [[TMP29]], [[TMP30]], !dbg [[DBG74]] +// CHECK1-NEXT: store i32 [[ADD30]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG74]] +// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG83]], !llvm.loop [[LOOP115:![0-9]+]] // CHECK1: omp.dispatch.end: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB5:[0-9]+]], i32 [[TMP9]]), !dbg [[DBG105:![0-9]+]] -// CHECK1-NEXT: ret void, !dbg [[DBG107:![0-9]+]] +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB5:[0-9]+]], i32 [[TMP9]]), !dbg [[DBG114:![0-9]+]] +// CHECK1-NEXT: ret void, !dbg [[DBG116:![0-9]+]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug___omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG108:![0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR2]] !dbg [[DBG117:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -292,34 +292,34 @@ int main() { // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META115:![0-9]+]], metadata !DIExpression()), !dbg [[DBG116:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META124:![0-9]+]], metadata !DIExpression()), !dbg [[DBG125:![0-9]+]] // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META117:![0-9]+]], metadata !DIExpression()), !dbg [[DBG116]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META126:![0-9]+]], metadata !DIExpression()), !dbg [[DBG125]] // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META118:![0-9]+]], metadata !DIExpression()), !dbg [[DBG116]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META127:![0-9]+]], metadata !DIExpression()), !dbg [[DBG125]] // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META119:![0-9]+]], metadata !DIExpression()), !dbg [[DBG116]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META128:![0-9]+]], metadata !DIExpression()), !dbg [[DBG125]] // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META120:![0-9]+]], metadata !DIExpression()), !dbg [[DBG116]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META129:![0-9]+]], metadata !DIExpression()), !dbg [[DBG125]] // CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META121:![0-9]+]], metadata !DIExpression()), !dbg [[DBG116]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG122:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG122]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG122]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG122]] -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG122]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG122]] -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG122]] -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG122]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG122]] -// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG122]] -// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG122]] -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug___omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], ptr addrspace(1) [[TMP9]], i32 [[TMP6]], ptr [[TMP7]], ptr addrspace(1) [[TMP10]]) #[[ATTR3:[0-9]+]], !dbg [[DBG122]] -// CHECK1-NEXT: ret void, !dbg [[DBG122]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META130:![0-9]+]], metadata !DIExpression()), !dbg [[DBG125]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG131:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG131]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG131]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG131]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG131]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG131]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG131]] +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG131]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG131]] +// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG131]] +// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG131]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug___omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], ptr addrspace(1) [[TMP9]], i32 [[TMP6]], ptr [[TMP7]], ptr addrspace(1) [[TMP10]]) #[[ATTR4:[0-9]+]], !dbg [[DBG131]] +// CHECK1-NEXT: ret void, !dbg [[DBG131]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13 -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR5:[0-9]+]] !dbg [[DBG123:![0-9]+]] { +// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR6:[0-9]+]] !dbg [[DBG132:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -327,32 +327,32 @@ int main() { // CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META126:![0-9]+]], metadata !DIExpression()), !dbg [[DBG127:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META135:![0-9]+]], metadata !DIExpression()), !dbg [[DBG136:![0-9]+]] // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META128:![0-9]+]], metadata !DIExpression()), !dbg [[DBG127]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META137:![0-9]+]], metadata !DIExpression()), !dbg [[DBG136]] // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META129:![0-9]+]], metadata !DIExpression()), !dbg [[DBG127]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META138:![0-9]+]], metadata !DIExpression()), !dbg [[DBG136]] // CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META130:![0-9]+]], metadata !DIExpression()), !dbg [[DBG127]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META139:![0-9]+]], metadata !DIExpression()), !dbg [[DBG136]] // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTCAPTURE_EXPR__ADDR]], metadata [[META131:![0-9]+]], metadata !DIExpression()), !dbg [[DBG127]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG132:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG132]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG132]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG132]] -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG132]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG132]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG132]] -// CHECK1-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !dbg [[DBG132]] -// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1, !dbg [[DBG132]] -// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[TMP3]] to ptr addrspace(1), !dbg [[DBG132]] -// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG132]] -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug__(ptr addrspace(1) [[TMP8]], i32 [[TMP4]], ptr [[TMP5]], ptr addrspace(1) [[TMP9]], i1 [[TOBOOL]]) #[[ATTR3]], !dbg [[DBG132]] -// CHECK1-NEXT: ret void, !dbg [[DBG132]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTCAPTURE_EXPR__ADDR]], metadata [[META140:![0-9]+]], metadata !DIExpression()), !dbg [[DBG136]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG141:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG141]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG141]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG141]] +// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG141]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG141]] +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG141]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !dbg [[DBG141]] +// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1, !dbg [[DBG141]] +// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[TMP3]] to ptr addrspace(1), !dbg [[DBG141]] +// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG141]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug__(ptr addrspace(1) [[TMP8]], i32 [[TMP4]], ptr [[TMP5]], ptr addrspace(1) [[TMP9]], i1 [[TOBOOL]]) #[[ATTR4]], !dbg [[DBG141]] +// CHECK1-NEXT: ret void, !dbg [[DBG141]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug__ -// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG133:![0-9]+]] { +// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG142:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr addrspace(1), align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -364,51 +364,51 @@ int main() { // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8 // CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META138:![0-9]+]], metadata !DIExpression()), !dbg [[DBG139:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META147:![0-9]+]], metadata !DIExpression()), !dbg [[DBG148:![0-9]+]] // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META140:![0-9]+]], metadata !DIExpression()), !dbg [[DBG141:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META149:![0-9]+]], metadata !DIExpression()), !dbg [[DBG150:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META142:![0-9]+]], metadata !DIExpression()), !dbg [[DBG143:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META151:![0-9]+]], metadata !DIExpression()), !dbg [[DBG152:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META144:![0-9]+]], metadata !DIExpression()), !dbg [[DBG145:![0-9]+]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG146:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG146]] -// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG146]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG146]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG146]] -// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG146]] -// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG146]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG146]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG146]] -// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG146]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG146]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG146]] -// CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_kernel_environment), !dbg [[DBG146]] -// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP9]], -1, !dbg [[DBG146]] -// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG146]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META153:![0-9]+]], metadata !DIExpression()), !dbg [[DBG154:![0-9]+]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG155:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG155]] +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG155]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG155]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG155]] +// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG155]] +// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG155]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG155]] +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG155]] +// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG155]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG155]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG155]] +// CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_kernel_environment), !dbg [[DBG155]] +// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP9]], -1, !dbg [[DBG155]] +// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG155]] // CHECK1: user_code.entry: // CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB13:[0-9]+]]) -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG147:![0-9]+]] -// CHECK1-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4, !dbg [[DBG147]] -// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG147]] -// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG147]] -// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP13]], align 8, !dbg [[DBG147]] -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG147]] -// CHECK1-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP12]] to ptr, !dbg [[DBG147]] -// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8, !dbg [[DBG147]] -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG147]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 8, !dbg [[DBG147]] -// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG147]] -// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP17]], align 8, !dbg [[DBG147]] -// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB13]], i32 [[TMP10]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4), !dbg [[DBG147]] -// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG148:![0-9]+]] -// CHECK1-NEXT: ret void, !dbg [[DBG150:![0-9]+]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG156:![0-9]+]] +// CHECK1-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4, !dbg [[DBG156]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG156]] +// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG156]] +// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP13]], align 8, !dbg [[DBG156]] +// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG156]] +// CHECK1-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP12]] to ptr, !dbg [[DBG156]] +// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8, !dbg [[DBG156]] +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG156]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 8, !dbg [[DBG156]] +// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG156]] +// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP17]], align 8, !dbg [[DBG156]] +// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB13]], i32 [[TMP10]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4), !dbg [[DBG156]] +// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG157:![0-9]+]] +// CHECK1-NEXT: ret void, !dbg [[DBG159:![0-9]+]] // CHECK1: worker.exit: -// CHECK1-NEXT: ret void, !dbg [[DBG146]] +// CHECK1-NEXT: ret void, !dbg [[DBG155]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___omp_outlined_debug__ -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG151:![0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR2]] !dbg [[DBG160:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -431,140 +431,140 @@ int main() { // CHECK1-NEXT: [[H:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[D:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META154:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META163:![0-9]+]], metadata !DIExpression()), !dbg [[DBG164:![0-9]+]] // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META156:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META165:![0-9]+]], metadata !DIExpression()), !dbg [[DBG164]] // CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META157:![0-9]+]], metadata !DIExpression()), !dbg [[DBG158:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META166:![0-9]+]], metadata !DIExpression()), !dbg [[DBG167:![0-9]+]] // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META159:![0-9]+]], metadata !DIExpression()), !dbg [[DBG160:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META168:![0-9]+]], metadata !DIExpression()), !dbg [[DBG169:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META161:![0-9]+]], metadata !DIExpression()), !dbg [[DBG162:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META170:![0-9]+]], metadata !DIExpression()), !dbg [[DBG171:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META163:![0-9]+]], metadata !DIExpression()), !dbg [[DBG164:![0-9]+]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG165:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG165]] -// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG165]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG165]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG165]] -// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG165]] -// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG165]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG165]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG165]] -// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG165]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG165]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG165]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_IV]], metadata [[META166:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_LB]], metadata [[META167:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155]] -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG168:![0-9]+]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_UB]], metadata [[META169:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155]] -// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_STRIDE]], metadata [[META170:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155]] -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_IS_LAST]], metadata [[META171:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155]] -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[I]], metadata [[META172:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155]] -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG165]] -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4, !dbg [[DBG165]] -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB10:[0-9]+]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG173:![0-9]+]] -// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG165]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META172:![0-9]+]], metadata !DIExpression()), !dbg [[DBG173:![0-9]+]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG174:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG174]] +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG174]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG174]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG174]] +// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG174]] +// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG174]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG174]] +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG174]] +// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG174]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG174]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG174]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_IV]], metadata [[META175:![0-9]+]], metadata !DIExpression()), !dbg [[DBG164]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_LB]], metadata [[META176:![0-9]+]], metadata !DIExpression()), !dbg [[DBG164]] +// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG177:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_UB]], metadata [[META178:![0-9]+]], metadata !DIExpression()), !dbg [[DBG164]] +// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_STRIDE]], metadata [[META179:![0-9]+]], metadata !DIExpression()), !dbg [[DBG164]] +// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_IS_LAST]], metadata [[META180:![0-9]+]], metadata !DIExpression()), !dbg [[DBG164]] +// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[I]], metadata [[META181:![0-9]+]], metadata !DIExpression()), !dbg [[DBG164]] +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG174]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4, !dbg [[DBG174]] +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB10:[0-9]+]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG182:![0-9]+]] +// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG174]] // CHECK1: omp.dispatch.cond: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9, !dbg [[DBG168]] -// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG168]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9, !dbg [[DBG177]] +// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG177]] // CHECK1: cond.true: -// CHECK1-NEXT: br label [[COND_END:%.*]], !dbg [[DBG168]] +// CHECK1-NEXT: br label [[COND_END:%.*]], !dbg [[DBG177]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: br label [[COND_END]], !dbg [[DBG168]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: br label [[COND_END]], !dbg [[DBG177]] // CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ], !dbg [[DBG168]] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]], !dbg [[DBG165]] -// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG165]] +// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ], !dbg [[DBG177]] +// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]], !dbg [[DBG174]] +// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG174]] // CHECK1: omp.dispatch.body: -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG165]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG174]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]], !dbg [[DBG165]] -// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG165]] +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]], !dbg [[DBG174]] +// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG174]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1, !dbg [[DBG174:![0-9]+]] -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG174]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG174]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[F]], metadata [[META175:![0-9]+]], metadata !DIExpression()), !dbg [[DBG177:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG178:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG178]] -// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX6]], i64 0, i64 1, !dbg [[DBG178]] -// CHECK1-NEXT: store ptr [[ARRAYIDX7]], ptr [[F]], align 8, !dbg [[DBG177]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[G]], metadata [[META179:![0-9]+]], metadata !DIExpression()), !dbg [[DBG180:![0-9]+]] -// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[DBG180]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[H]], metadata [[META181:![0-9]+]], metadata !DIExpression()), !dbg [[DBG182:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 1, !dbg [[DBG183:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX8]], i64 0, i64 1, !dbg [[DBG183]] -// CHECK1-NEXT: store ptr [[ARRAYIDX9]], ptr [[H]], align 8, !dbg [[DBG182]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[D]], metadata [[META184:![0-9]+]], metadata !DIExpression()), !dbg [[DBG185:![0-9]+]] -// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[DBG185]] -// CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG186:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG187:![0-9]+]] -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG188:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG187]] -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX10]], i64 0, i64 [[IDXPROM]], !dbg [[DBG187]] -// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX11]], align 4, !dbg [[DBG189:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG190:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX12]], i64 0, i64 0, !dbg [[DBG190]] -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG191:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP20]] to i64, !dbg [[DBG190]] -// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX13]], i64 0, i64 [[IDXPROM14]], !dbg [[DBG190]] -// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX15]], align 4, !dbg [[DBG192:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG193:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX16]], i64 0, i64 0, !dbg [[DBG193]] -// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG194:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM18:%.*]] = sext i32 [[TMP21]] to i64, !dbg [[DBG193]] -// CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX17]], i64 0, i64 [[IDXPROM18]], !dbg [[DBG193]] -// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[ARRAYIDX19]], align 4, !dbg [[DBG193]] -// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG195:![0-9]+]] -// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG196:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM21:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG195]] -// CHECK1-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX20]], i64 0, i64 [[IDXPROM21]], !dbg [[DBG195]] -// CHECK1-NEXT: store i32 [[TMP22]], ptr [[ARRAYIDX22]], align 4, !dbg [[DBG197:![0-9]+]] -// CHECK1-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP8]], align 1, !dbg [[DBG198:![0-9]+]] -// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP24]] to i1, !dbg [[DBG198]] -// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TOBOOL]] to i32, !dbg [[DBG198]] -// CHECK1-NEXT: store i32 [[CONV]], ptr [[D]], align 4, !dbg [[DBG199:![0-9]+]] -// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG200:![0-9]+]] +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1, !dbg [[DBG183:![0-9]+]] +// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG183]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG183]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[F]], metadata [[META184:![0-9]+]], metadata !DIExpression()), !dbg [[DBG186:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG187:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG187]] +// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX6]], i64 0, i64 1, !dbg [[DBG187]] +// CHECK1-NEXT: store ptr [[ARRAYIDX7]], ptr [[F]], align 8, !dbg [[DBG186]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[G]], metadata [[META188:![0-9]+]], metadata !DIExpression()), !dbg [[DBG189:![0-9]+]] +// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[DBG189]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[H]], metadata [[META190:![0-9]+]], metadata !DIExpression()), !dbg [[DBG191:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 1, !dbg [[DBG192:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX8]], i64 0, i64 1, !dbg [[DBG192]] +// CHECK1-NEXT: store ptr [[ARRAYIDX9]], ptr [[H]], align 8, !dbg [[DBG191]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[D]], metadata [[META193:![0-9]+]], metadata !DIExpression()), !dbg [[DBG194:![0-9]+]] +// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[DBG194]] +// CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG195:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG196:![0-9]+]] +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG197:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG196]] +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX10]], i64 0, i64 [[IDXPROM]], !dbg [[DBG196]] +// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX11]], align 4, !dbg [[DBG198:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG199:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX12]], i64 0, i64 0, !dbg [[DBG199]] +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG200:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP20]] to i64, !dbg [[DBG199]] +// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX13]], i64 0, i64 [[IDXPROM14]], !dbg [[DBG199]] +// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX15]], align 4, !dbg [[DBG201:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG202:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX16]], i64 0, i64 0, !dbg [[DBG202]] +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG203:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM18:%.*]] = sext i32 [[TMP21]] to i64, !dbg [[DBG202]] +// CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX17]], i64 0, i64 [[IDXPROM18]], !dbg [[DBG202]] +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[ARRAYIDX19]], align 4, !dbg [[DBG202]] +// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG204:![0-9]+]] +// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG205:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM21:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG204]] +// CHECK1-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX20]], i64 0, i64 [[IDXPROM21]], !dbg [[DBG204]] +// CHECK1-NEXT: store i32 [[TMP22]], ptr [[ARRAYIDX22]], align 4, !dbg [[DBG206:![0-9]+]] +// CHECK1-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP8]], align 1, !dbg [[DBG207:![0-9]+]] +// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP24]] to i1, !dbg [[DBG207]] +// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TOBOOL]] to i32, !dbg [[DBG207]] +// CHECK1-NEXT: store i32 [[CONV]], ptr [[D]], align 4, !dbg [[DBG208:![0-9]+]] +// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG209:![0-9]+]] // CHECK1: omp.body.continue: -// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG173]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG182]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP25]], 1, !dbg [[DBG165]] -// CHECK1-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG165]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG173]], !llvm.loop [[LOOP201:![0-9]+]] +// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP25]], 1, !dbg [[DBG174]] +// CHECK1-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG174]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG182]], !llvm.loop [[LOOP210:![0-9]+]] // CHECK1: omp.inner.for.end: -// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG173]] +// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG182]] // CHECK1: omp.dispatch.inc: -// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP26]], [[TMP27]], !dbg [[DBG165]] -// CHECK1-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG165]] -// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]], !dbg [[DBG165]] -// CHECK1-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG165]] -// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG173]], !llvm.loop [[LOOP203:![0-9]+]] +// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP26]], [[TMP27]], !dbg [[DBG174]] +// CHECK1-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG174]] +// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]], !dbg [[DBG174]] +// CHECK1-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG174]] +// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG182]], !llvm.loop [[LOOP212:![0-9]+]] // CHECK1: omp.dispatch.end: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB12:[0-9]+]], i32 [[TMP10]]), !dbg [[DBG202:![0-9]+]] -// CHECK1-NEXT: ret void, !dbg [[DBG204:![0-9]+]] +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB12:[0-9]+]], i32 [[TMP10]]), !dbg [[DBG211:![0-9]+]] +// CHECK1-NEXT: ret void, !dbg [[DBG213:![0-9]+]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG205:![0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR2]] !dbg [[DBG214:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -573,64 +573,64 @@ int main() { // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META206:![0-9]+]], metadata !DIExpression()), !dbg [[DBG207:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META215:![0-9]+]], metadata !DIExpression()), !dbg [[DBG216:![0-9]+]] // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META208:![0-9]+]], metadata !DIExpression()), !dbg [[DBG207]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META217:![0-9]+]], metadata !DIExpression()), !dbg [[DBG216]] // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META209:![0-9]+]], metadata !DIExpression()), !dbg [[DBG207]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META218:![0-9]+]], metadata !DIExpression()), !dbg [[DBG216]] // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META210:![0-9]+]], metadata !DIExpression()), !dbg [[DBG207]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META219:![0-9]+]], metadata !DIExpression()), !dbg [[DBG216]] // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META211:![0-9]+]], metadata !DIExpression()), !dbg [[DBG207]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META220:![0-9]+]], metadata !DIExpression()), !dbg [[DBG216]] // CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META212:![0-9]+]], metadata !DIExpression()), !dbg [[DBG207]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG213:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG213]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG213]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG213]] -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG213]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG213]] -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG213]] -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG213]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG213]] -// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG213]] -// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG213]] -// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG213]] -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], ptr addrspace(1) [[TMP9]], i32 [[TMP6]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]]) #[[ATTR3]], !dbg [[DBG213]] -// CHECK1-NEXT: ret void, !dbg [[DBG213]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META221:![0-9]+]], metadata !DIExpression()), !dbg [[DBG216]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG222:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG222]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG222]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG222]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG222]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG222]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG222]] +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG222]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG222]] +// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG222]] +// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG222]] +// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG222]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], ptr addrspace(1) [[TMP9]], i32 [[TMP6]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]]) #[[ATTR4]], !dbg [[DBG222]] +// CHECK1-NEXT: ret void, !dbg [[DBG222]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27 -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR5]] !dbg [[DBG214:![0-9]+]] { +// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR6]] !dbg [[DBG223:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META217:![0-9]+]], metadata !DIExpression()), !dbg [[DBG218:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META226:![0-9]+]], metadata !DIExpression()), !dbg [[DBG227:![0-9]+]] // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META219:![0-9]+]], metadata !DIExpression()), !dbg [[DBG218]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META228:![0-9]+]], metadata !DIExpression()), !dbg [[DBG227]] // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META220:![0-9]+]], metadata !DIExpression()), !dbg [[DBG218]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META229:![0-9]+]], metadata !DIExpression()), !dbg [[DBG227]] // CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META221:![0-9]+]], metadata !DIExpression()), !dbg [[DBG218]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG222:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG222]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG222]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG222]] -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG222]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG222]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG222]] -// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr [[TMP3]] to ptr addrspace(1), !dbg [[DBG222]] -// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG222]] -// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG222]] -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug__(ptr addrspace(1) [[TMP7]], i32 [[TMP4]], ptr addrspace(1) [[TMP8]], ptr addrspace(1) [[TMP9]]) #[[ATTR3]], !dbg [[DBG222]] -// CHECK1-NEXT: ret void, !dbg [[DBG222]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META230:![0-9]+]], metadata !DIExpression()), !dbg [[DBG227]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG231:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG231]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG231]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG231]] +// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG231]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG231]] +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG231]] +// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr [[TMP3]] to ptr addrspace(1), !dbg [[DBG231]] +// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG231]] +// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG231]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug__(ptr addrspace(1) [[TMP7]], i32 [[TMP4]], ptr addrspace(1) [[TMP8]], ptr addrspace(1) [[TMP9]]) #[[ATTR4]], !dbg [[DBG231]] +// CHECK1-NEXT: ret void, !dbg [[DBG231]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug__ -// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], ptr addrspace(1) noalias noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG223:![0-9]+]] { +// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], ptr addrspace(1) noalias noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG232:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr addrspace(1), align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr addrspace(1), align 8 @@ -642,51 +642,51 @@ int main() { // CHECK1-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8 // CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META228:![0-9]+]], metadata !DIExpression()), !dbg [[DBG229:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META237:![0-9]+]], metadata !DIExpression()), !dbg [[DBG238:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META230:![0-9]+]], metadata !DIExpression()), !dbg [[DBG231:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META239:![0-9]+]], metadata !DIExpression()), !dbg [[DBG240:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META232:![0-9]+]], metadata !DIExpression()), !dbg [[DBG233:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META241:![0-9]+]], metadata !DIExpression()), !dbg [[DBG242:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META234:![0-9]+]], metadata !DIExpression()), !dbg [[DBG235:![0-9]+]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG236:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG236]] -// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG236]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG236]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[A_ADDR]], align 8, !dbg [[DBG236]] -// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG236]] -// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG236]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG236]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG236]] -// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG236]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG236]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG236]] -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG236]] -// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(1) [[TMP9]] to ptr, !dbg [[DBG236]] -// CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG236]] -// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG236]] -// CHECK1-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_kernel_environment), !dbg [[DBG236]] -// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP12]], -1, !dbg [[DBG236]] -// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG236]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META243:![0-9]+]], metadata !DIExpression()), !dbg [[DBG244:![0-9]+]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG245:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG245]] +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG245]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG245]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[A_ADDR]], align 8, !dbg [[DBG245]] +// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG245]] +// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG245]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG245]] +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG245]] +// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG245]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG245]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG245]] +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG245]] +// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(1) [[TMP9]] to ptr, !dbg [[DBG245]] +// CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG245]] +// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG245]] +// CHECK1-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_kernel_environment), !dbg [[DBG245]] +// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP12]], -1, !dbg [[DBG245]] +// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG245]] // CHECK1: user_code.entry: // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB20:[0-9]+]]) -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG237:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP14]], align 8, !dbg [[DBG237]] -// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG237]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP15]], align 8, !dbg [[DBG237]] -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG237]] -// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP16]], align 8, !dbg [[DBG237]] -// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG237]] -// CHECK1-NEXT: store ptr [[TMP11]], ptr [[TMP17]], align 8, !dbg [[DBG237]] -// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB20]], i32 [[TMP13]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4), !dbg [[DBG237]] -// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG238:![0-9]+]] -// CHECK1-NEXT: ret void, !dbg [[DBG240:![0-9]+]] +// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG246:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP14]], align 8, !dbg [[DBG246]] +// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG246]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP15]], align 8, !dbg [[DBG246]] +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG246]] +// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP16]], align 8, !dbg [[DBG246]] +// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG246]] +// CHECK1-NEXT: store ptr [[TMP11]], ptr [[TMP17]], align 8, !dbg [[DBG246]] +// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB20]], i32 [[TMP13]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4), !dbg [[DBG246]] +// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG247:![0-9]+]] +// CHECK1-NEXT: ret void, !dbg [[DBG249:![0-9]+]] // CHECK1: worker.exit: -// CHECK1-NEXT: ret void, !dbg [[DBG236]] +// CHECK1-NEXT: ret void, !dbg [[DBG245]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___omp_outlined_debug__ -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], ptr addrspace(1) noalias noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG241:![0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], ptr addrspace(1) noalias noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR2]] !dbg [[DBG250:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -710,148 +710,148 @@ int main() { // CHECK1-NEXT: [[H:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[D:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META244:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META253:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254:![0-9]+]] // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META246:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META255:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254]] // CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META247:![0-9]+]], metadata !DIExpression()), !dbg [[DBG248:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META256:![0-9]+]], metadata !DIExpression()), !dbg [[DBG257:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META249:![0-9]+]], metadata !DIExpression()), !dbg [[DBG250:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META258:![0-9]+]], metadata !DIExpression()), !dbg [[DBG259:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META251:![0-9]+]], metadata !DIExpression()), !dbg [[DBG252:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META260:![0-9]+]], metadata !DIExpression()), !dbg [[DBG261:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META253:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254:![0-9]+]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG255:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG255]] -// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[A_ADDR]], align 8, !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG255]] -// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG255]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(1) [[TMP9]] to ptr, !dbg [[DBG255]] -// CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG255]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_IV]], metadata [[META256:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_LB]], metadata [[META257:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245]] -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG258:![0-9]+]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_UB]], metadata [[META259:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245]] -// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_STRIDE]], metadata [[META260:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245]] -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_IS_LAST]], metadata [[META261:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245]] -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[I]], metadata [[META262:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245]] -// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG255]] -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB17:[0-9]+]], i32 [[TMP13]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG263:![0-9]+]] -// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG255]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META262:![0-9]+]], metadata !DIExpression()), !dbg [[DBG263:![0-9]+]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG264:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG264]] +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[A_ADDR]], align 8, !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG264]] +// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG264]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(1) [[TMP9]] to ptr, !dbg [[DBG264]] +// CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG264]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_IV]], metadata [[META265:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_LB]], metadata [[META266:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254]] +// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG267:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_UB]], metadata [[META268:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254]] +// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_STRIDE]], metadata [[META269:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254]] +// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_IS_LAST]], metadata [[META270:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254]] +// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[I]], metadata [[META271:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254]] +// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG264]] +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB17:[0-9]+]], i32 [[TMP13]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG272:![0-9]+]] +// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG264]] // CHECK1: omp.dispatch.cond: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP14]], 9, !dbg [[DBG258]] -// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG258]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP14]], 9, !dbg [[DBG267]] +// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG267]] // CHECK1: cond.true: -// CHECK1-NEXT: br label [[COND_END:%.*]], !dbg [[DBG258]] +// CHECK1-NEXT: br label [[COND_END:%.*]], !dbg [[DBG267]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: br label [[COND_END]], !dbg [[DBG258]] +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: br label [[COND_END]], !dbg [[DBG267]] // CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ], !dbg [[DBG258]] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]], !dbg [[DBG255]] -// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG255]] +// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ], !dbg [[DBG267]] +// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]], !dbg [[DBG264]] +// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG264]] // CHECK1: omp.dispatch.body: -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG255]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG264]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]], !dbg [[DBG255]] -// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG255]] +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]], !dbg [[DBG264]] +// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG264]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1, !dbg [[DBG264:![0-9]+]] -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG264]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG264]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[F]], metadata [[META265:![0-9]+]], metadata !DIExpression()), !dbg [[DBG267:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG268:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG268]] -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], i64 0, i64 1, !dbg [[DBG268]] -// CHECK1-NEXT: store ptr [[ARRAYIDX8]], ptr [[F]], align 8, !dbg [[DBG267]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[G]], metadata [[META269:![0-9]+]], metadata !DIExpression()), !dbg [[DBG270:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[G]], align 8, !dbg [[DBG270]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[H]], metadata [[META271:![0-9]+]], metadata !DIExpression()), !dbg [[DBG272:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 1, !dbg [[DBG273:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX9]], i64 0, i64 1, !dbg [[DBG273]] -// CHECK1-NEXT: store ptr [[ARRAYIDX10]], ptr [[H]], align 8, !dbg [[DBG272]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[D]], metadata [[META274:![0-9]+]], metadata !DIExpression()), !dbg [[DBG275:![0-9]+]] -// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[DBG275]] -// CHECK1-NEXT: store i32 5, ptr [[TMP5]], align 4, !dbg [[DBG276:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG277:![0-9]+]] -// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG278:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG277]] -// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM]], !dbg [[DBG277]] -// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX12]], align 4, !dbg [[DBG279:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG280:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG280]] -// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG281:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG280]] -// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG280]] -// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX16]], align 4, !dbg [[DBG282:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG283:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX17]], i64 0, i64 0, !dbg [[DBG283]] -// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG284:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP24]] to i64, !dbg [[DBG283]] -// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG283]] -// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[ARRAYIDX20]], align 4, !dbg [[DBG283]] -// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG285:![0-9]+]] -// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG286:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP26]] to i64, !dbg [[DBG285]] -// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG285]] -// CHECK1-NEXT: store i32 [[TMP25]], ptr [[ARRAYIDX23]], align 4, !dbg [[DBG287:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG288:![0-9]+]] -// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG289:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP27]] to i64, !dbg [[DBG288]] -// CHECK1-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX24]], i64 0, i64 [[IDXPROM25]], !dbg [[DBG288]] -// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARRAYIDX26]], align 4, !dbg [[DBG288]] -// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP28]], 0, !dbg [[DBG288]] -// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8, !dbg [[DBG290:![0-9]+]] -// CHECK1-NEXT: store i8 [[FROMBOOL]], ptr [[TMP11]], align 1, !dbg [[DBG290]] -// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG291:![0-9]+]] +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1, !dbg [[DBG273:![0-9]+]] +// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG273]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG273]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[F]], metadata [[META274:![0-9]+]], metadata !DIExpression()), !dbg [[DBG276:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG277:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG277]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], i64 0, i64 1, !dbg [[DBG277]] +// CHECK1-NEXT: store ptr [[ARRAYIDX8]], ptr [[F]], align 8, !dbg [[DBG276]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[G]], metadata [[META278:![0-9]+]], metadata !DIExpression()), !dbg [[DBG279:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[G]], align 8, !dbg [[DBG279]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[H]], metadata [[META280:![0-9]+]], metadata !DIExpression()), !dbg [[DBG281:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 1, !dbg [[DBG282:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX9]], i64 0, i64 1, !dbg [[DBG282]] +// CHECK1-NEXT: store ptr [[ARRAYIDX10]], ptr [[H]], align 8, !dbg [[DBG281]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[D]], metadata [[META283:![0-9]+]], metadata !DIExpression()), !dbg [[DBG284:![0-9]+]] +// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[DBG284]] +// CHECK1-NEXT: store i32 5, ptr [[TMP5]], align 4, !dbg [[DBG285:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG286:![0-9]+]] +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG287:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG286]] +// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM]], !dbg [[DBG286]] +// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX12]], align 4, !dbg [[DBG288:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG289:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG289]] +// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG290:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG289]] +// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG289]] +// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX16]], align 4, !dbg [[DBG291:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG292:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX17]], i64 0, i64 0, !dbg [[DBG292]] +// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG293:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP24]] to i64, !dbg [[DBG292]] +// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG292]] +// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[ARRAYIDX20]], align 4, !dbg [[DBG292]] +// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG294:![0-9]+]] +// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG295:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP26]] to i64, !dbg [[DBG294]] +// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG294]] +// CHECK1-NEXT: store i32 [[TMP25]], ptr [[ARRAYIDX23]], align 4, !dbg [[DBG296:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG297:![0-9]+]] +// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG298:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP27]] to i64, !dbg [[DBG297]] +// CHECK1-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX24]], i64 0, i64 [[IDXPROM25]], !dbg [[DBG297]] +// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARRAYIDX26]], align 4, !dbg [[DBG297]] +// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP28]], 0, !dbg [[DBG297]] +// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8, !dbg [[DBG299:![0-9]+]] +// CHECK1-NEXT: store i8 [[FROMBOOL]], ptr [[TMP11]], align 1, !dbg [[DBG299]] +// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG300:![0-9]+]] // CHECK1: omp.body.continue: -// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG263]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG272]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP29]], 1, !dbg [[DBG255]] -// CHECK1-NEXT: store i32 [[ADD27]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG255]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG263]], !llvm.loop [[LOOP292:![0-9]+]] +// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP29]], 1, !dbg [[DBG264]] +// CHECK1-NEXT: store i32 [[ADD27]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG264]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG272]], !llvm.loop [[LOOP301:![0-9]+]] // CHECK1: omp.inner.for.end: -// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG263]] +// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG272]] // CHECK1: omp.dispatch.inc: -// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]], !dbg [[DBG255]] -// CHECK1-NEXT: store i32 [[ADD28]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP32]], [[TMP33]], !dbg [[DBG255]] -// CHECK1-NEXT: store i32 [[ADD29]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG255]] -// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG263]], !llvm.loop [[LOOP294:![0-9]+]] +// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]], !dbg [[DBG264]] +// CHECK1-NEXT: store i32 [[ADD28]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP32]], [[TMP33]], !dbg [[DBG264]] +// CHECK1-NEXT: store i32 [[ADD29]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG264]] +// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG272]], !llvm.loop [[LOOP303:![0-9]+]] // CHECK1: omp.dispatch.end: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB19:[0-9]+]], i32 [[TMP13]]), !dbg [[DBG293:![0-9]+]] -// CHECK1-NEXT: ret void, !dbg [[DBG295:![0-9]+]] +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB19:[0-9]+]], i32 [[TMP13]]), !dbg [[DBG302:![0-9]+]] +// CHECK1-NEXT: ret void, !dbg [[DBG304:![0-9]+]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG296:![0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR2]] !dbg [[DBG305:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -860,62 +860,62 @@ int main() { // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META299:![0-9]+]], metadata !DIExpression()), !dbg [[DBG300:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META308:![0-9]+]], metadata !DIExpression()), !dbg [[DBG309:![0-9]+]] // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META301:![0-9]+]], metadata !DIExpression()), !dbg [[DBG300]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META310:![0-9]+]], metadata !DIExpression()), !dbg [[DBG309]] // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META302:![0-9]+]], metadata !DIExpression()), !dbg [[DBG300]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META311:![0-9]+]], metadata !DIExpression()), !dbg [[DBG309]] // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META303:![0-9]+]], metadata !DIExpression()), !dbg [[DBG300]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META312:![0-9]+]], metadata !DIExpression()), !dbg [[DBG309]] // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META304:![0-9]+]], metadata !DIExpression()), !dbg [[DBG300]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META313:![0-9]+]], metadata !DIExpression()), !dbg [[DBG309]] // CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META305:![0-9]+]], metadata !DIExpression()), !dbg [[DBG300]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG306:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG306]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG306]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG306]] -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG306]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG306]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG306]] -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG306]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG306]] -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG306]] -// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG306]] -// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG306]] -// CHECK1-NEXT: [[TMP12:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG306]] -// CHECK1-NEXT: [[TMP13:%.*]] = addrspacecast ptr [[TMP9]] to ptr addrspace(1), !dbg [[DBG306]] -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___omp_outlined_debug__(ptr [[TMP4]], ptr [[TMP5]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]], ptr addrspace(1) [[TMP12]], ptr addrspace(1) [[TMP13]]) #[[ATTR3]], !dbg [[DBG306]] -// CHECK1-NEXT: ret void, !dbg [[DBG306]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META314:![0-9]+]], metadata !DIExpression()), !dbg [[DBG309]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG315:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG315]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG315]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG315]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG315]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG315]] +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG315]] +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG315]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG315]] +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG315]] +// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG315]] +// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG315]] +// CHECK1-NEXT: [[TMP12:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG315]] +// CHECK1-NEXT: [[TMP13:%.*]] = addrspacecast ptr [[TMP9]] to ptr addrspace(1), !dbg [[DBG315]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___omp_outlined_debug__(ptr [[TMP4]], ptr [[TMP5]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]], ptr addrspace(1) [[TMP12]], ptr addrspace(1) [[TMP13]]) #[[ATTR4]], !dbg [[DBG315]] +// CHECK1-NEXT: ret void, !dbg [[DBG315]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41 -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR5]] !dbg [[DBG307:![0-9]+]] { +// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR6]] !dbg [[DBG316:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META310:![0-9]+]], metadata !DIExpression()), !dbg [[DBG311:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META319:![0-9]+]], metadata !DIExpression()), !dbg [[DBG320:![0-9]+]] // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META312:![0-9]+]], metadata !DIExpression()), !dbg [[DBG311]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META321:![0-9]+]], metadata !DIExpression()), !dbg [[DBG320]] // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META313:![0-9]+]], metadata !DIExpression()), !dbg [[DBG311]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META322:![0-9]+]], metadata !DIExpression()), !dbg [[DBG320]] // CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META314:![0-9]+]], metadata !DIExpression()), !dbg [[DBG311]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG315:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG315]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG315]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG315]] -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG315]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG315]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG315]] -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG315]] -// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[TMP4]] to ptr addrspace(1), !dbg [[DBG315]] -// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG315]] -// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG315]] -// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG315]] -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug__(ptr addrspace(1) [[TMP8]], ptr addrspace(1) [[TMP9]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]]) #[[ATTR3]], !dbg [[DBG315]] -// CHECK1-NEXT: ret void, !dbg [[DBG315]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META323:![0-9]+]], metadata !DIExpression()), !dbg [[DBG320]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG324:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG324]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG324]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG324]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG324]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG324]] +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG324]] +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG324]] +// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[TMP4]] to ptr addrspace(1), !dbg [[DBG324]] +// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG324]] +// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG324]] +// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG324]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug__(ptr addrspace(1) [[TMP8]], ptr addrspace(1) [[TMP9]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]]) #[[ATTR4]], !dbg [[DBG324]] +// CHECK1-NEXT: ret void, !dbg [[DBG324]] // diff --git a/clang/test/OpenMP/target_parallel_for_depend_codegen.cpp b/clang/test/OpenMP/target_parallel_for_depend_codegen.cpp index f06bffa1b72ea..801b188e97ca9 100644 --- a/clang/test/OpenMP/target_parallel_for_depend_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_for_depend_codegen.cpp @@ -1,37 +1,37 @@ // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s // SIMD-ONLY1-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/target_parallel_for_linear_messages.cpp b/clang/test/OpenMP/target_parallel_for_linear_messages.cpp index 1d79b2c38303f..5a78cf0623f61 100644 --- a/clang/test/OpenMP/target_parallel_for_linear_messages.cpp +++ b/clang/test/OpenMP/target_parallel_for_linear_messages.cpp @@ -1,6 +1,8 @@ // RUN: %clang_cc1 -verify -fopenmp %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp -fopenmp-version=52 -DOMP52 %s -Wuninitialized // RUN: %clang_cc1 -verify -fopenmp-simd %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp-simd -fopenmp-version=52 -DOMP52 %s -Wuninitialized typedef void **omp_allocator_handle_t; extern const omp_allocator_handle_t omp_null_allocator; @@ -14,8 +16,8 @@ extern const omp_allocator_handle_t omp_pteam_mem_alloc; extern const omp_allocator_handle_t omp_thread_mem_alloc; void xxx(int argc) { - int i, lin, step; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step' to silence this warning}} -#pragma omp target parallel for linear(lin : step) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step' is uninitialized when used here}} + int i, lin, step_sz; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step_sz' to silence this warning}} +#pragma omp target parallel for linear(lin : step_sz) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step_sz' is uninitialized when used here}} for (i = 0; i < 10; ++i) ; } @@ -270,16 +272,28 @@ int main(int argc, char **argv) { #pragma omp target parallel for linear(i) for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 +#pragma omp target parallel for linear(i : uval, step(4)) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} +#else #pragma omp target parallel for linear(i : 4) +#endif for (int k = 0; k < argc; ++k) { ++k; i += 4; } } +#ifdef OMP52 +#pragma omp target parallel for linear(j: step() //omp52-error 2 {{expected expression}} omp52-error{{expected ')'}} omp52-note{{to match this '('}} +#else #pragma omp target parallel for linear(j) +#endif for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 +#pragma omp target parallel for linear(i: step(1), step(2)) // omp52-error {{multiple 'step size' found in linear clause}} +#else #pragma omp target parallel for linear(i) +#endif for (int k = 0; k < argc; ++k) ++k; diff --git a/clang/test/OpenMP/target_parallel_for_map_messages.cpp b/clang/test/OpenMP/target_parallel_for_map_messages.cpp index 89ed76e960a04..a3f13814a6a59 100644 --- a/clang/test/OpenMP/target_parallel_for_map_messages.cpp +++ b/clang/test/OpenMP/target_parallel_for_map_messages.cpp @@ -1,10 +1,12 @@ // RUN: %clang_cc1 -verify=expected,lt50,lt51 -fopenmp -fno-openmp-extensions -fopenmp-version=45 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,lt51 -fopenmp -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,ge51 -fopenmp -fno-openmp-extensions -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized +// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp52 -fopenmp -fno-openmp-extensions -fopenmp-version=52 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,lt50,lt51 -fopenmp-simd -fno-openmp-extensions -fopenmp-version=45 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,lt51 -fopenmp-simd -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,ge51 -fopenmp-simd -fno-openmp-extensions -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized +// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp52 -fopenmp-simd -fno-openmp-extensions -fopenmp-version=52 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized void foo() { } @@ -307,6 +309,8 @@ int main(int argc, char **argv) { for (i = 0; i < argc; ++i) foo(); #pragma omp target parallel for map(always, tofrom: always, tofrom, x) for (i = 0; i < argc; ++i) foo(); +#pragma omp target parallel for map(always tofrom: x) // omp52-error {{missing ',' after map type modifier}} + for (i = 0; i < argc; ++i) foo(); #pragma omp target parallel for map(tofrom j) // expected-error {{expected ',' or ')' in 'map' clause}} for (i = 0; i < argc; ++i) foo(); #pragma omp target parallel for map(delete: j) // expected-error {{map type 'delete' is not allowed for '#pragma omp target parallel for'}} diff --git a/clang/test/OpenMP/target_parallel_for_simd_ast_print.cpp b/clang/test/OpenMP/target_parallel_for_simd_ast_print.cpp index 828ceef0374e1..c3b115dafa091 100644 --- a/clang/test/OpenMP/target_parallel_for_simd_ast_print.cpp +++ b/clang/test/OpenMP/target_parallel_for_simd_ast_print.cpp @@ -7,6 +7,9 @@ // RUN: %clang_cc1 -verify -fopenmp -ast-print %s -Wno-openmp-mapping -DOMP51 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP51 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -emit-pch -o %t %s -Wno-openmp-mapping -DOMP51 // RUN: %clang_cc1 -fopenmp -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -Wno-openmp-mapping -DOMP51 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP51 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=52 -ast-print %s -Wno-openmp-mapping -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=52 -x c++ -std=c++11 -emit-pch -o %t %s -Wno-openmp-mapping -DOMP52 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=52 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -Wno-openmp-mapping -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -ast-print %s -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK --check-prefix=OMP45 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -emit-pch -o %t %s -Wno-openmp-mapping @@ -18,6 +21,10 @@ // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -emit-pch -o %t %s -Wno-openmp-mapping -DOMP51 // RUN: %clang_cc1 -fopenmp-simd -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -Wno-openmp-mapping -DOMP51 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP51 // expected-no-diagnostics +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=52 -ast-print %s -Wno-openmp-mapping -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=52 -x c++ -std=c++11 -emit-pch -o %t %s -Wno-openmp-mapping -DOMP52 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=52 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -Wno-openmp-mapping -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 +// expected-no-diagnostics #ifndef HEADER #define HEADER @@ -131,7 +138,7 @@ T tmain(T argc, T *argv) { // CHECK-NEXT: for (T i = 0; i < 2; ++i) { // CHECK-NEXT: } -#ifdef OMP51 +#if defined(OMP51) || defined(OMP52) #pragma omp target parallel for simd if(target:argc > 0) if (simd: argc) nontemporal(argc, c, d) order(unconstrained:concurrent) allocate(omp_high_bw_mem_alloc:f) private(f) uses_allocators(omp_high_bw_mem_alloc) #elif OMP5 #pragma omp target parallel for simd if(target:argc > 0) if (simd: argc) nontemporal(argc, c, d) order(concurrent) allocate(omp_high_bw_mem_alloc:f) private(f) uses_allocators(omp_high_bw_mem_alloc) @@ -142,6 +149,7 @@ T tmain(T argc, T *argv) { // OMP45: #pragma omp target parallel for simd if(target: argc > 0) // OMP50: #pragma omp target parallel for simd if(target: argc > 0) if(simd: argc) nontemporal(argc,c,d) order(concurrent) allocate(omp_high_bw_mem_alloc: f) private(f) uses_allocators(omp_high_bw_mem_alloc) // OMP51: #pragma omp target parallel for simd if(target: argc > 0) if(simd: argc) nontemporal(argc,c,d) order(unconstrained: concurrent) allocate(omp_high_bw_mem_alloc: f) private(f) uses_allocators(omp_high_bw_mem_alloc) + // OMP52: #pragma omp target parallel for simd if(target: argc > 0) if(simd: argc) nontemporal(argc,c,d) order(unconstrained: concurrent) allocate(omp_high_bw_mem_alloc: f) private(f) uses_allocators(omp_high_bw_mem_alloc) // CHECK-NEXT: for (T i = 0; i < 2; ++i) { // CHECK-NEXT: } @@ -237,12 +245,15 @@ int main(int argc, char **argv) { a = 2; // CHECK-NEXT: for (int i = 0; i < 2; ++i) // CHECK-NEXT: a = 2; - +#ifdef OMP52 +#pragma omp target parallel for simd private(argc, b), firstprivate(argv, c), lastprivate(d, f) collapse(2) schedule(auto) ordered if (target: argc) num_threads(a) default(shared) shared(e) reduction(+ : h) linear(a: step(-5)) +#else #pragma omp target parallel for simd private(argc, b), firstprivate(argv, c), lastprivate(d, f) collapse(2) schedule(auto) ordered if (target: argc) num_threads(a) default(shared) shared(e) reduction(+ : h) linear(a:-5) +#endif for (int i = 0; i < 10; ++i) for (int j = 0; j < 10; ++j) foo(); - // CHECK: #pragma omp target parallel for simd private(argc,b) firstprivate(argv,c) lastprivate(d,f) collapse(2) schedule(auto) ordered if(target: argc) num_threads(a) default(shared) shared(e) reduction(+: h) linear(a: -5) + // CHECK: #pragma omp target parallel for simd private(argc,b) firstprivate(argv,c) lastprivate(d,f) collapse(2) schedule(auto) ordered if(target: argc) num_threads(a) default(shared) shared(e) reduction(+: h) linear(a: step(-5)) // CHECK-NEXT: for (int i = 0; i < 10; ++i) // CHECK-NEXT: for (int j = 0; j < 10; ++j) // CHECK-NEXT: foo(); @@ -265,7 +276,7 @@ int main(int argc, char **argv) { // CHECK-NEXT: for (int i = 0; i < 2; ++i) { // CHECK-NEXT: } -#ifdef OMP51 +#if defined(OMP51) || defined(OMP52) #pragma omp target parallel for simd if (parallel:argc > 0) #elif OMP5 #pragma omp target parallel for simd if (parallel:argc > 0) if(simd: argc) @@ -276,6 +287,7 @@ int main(int argc, char **argv) { // OMP45: #pragma omp target parallel for simd if(parallel: argc > 0) // OMP50: #pragma omp target parallel for simd if(parallel: argc > 0) if(simd: argc) // OMP51: #pragma omp target parallel for simd if(parallel: argc > 0) + // OMP52: #pragma omp target parallel for simd if(parallel: argc > 0) // CHECK-NEXT: for (int i = 0; i < 2; ++i) { // CHECK-NEXT: } diff --git a/clang/test/OpenMP/target_parallel_for_simd_codegen.cpp b/clang/test/OpenMP/target_parallel_for_simd_codegen.cpp index 31c9afbdc57b3..8205d1f217817 100644 --- a/clang/test/OpenMP/target_parallel_for_simd_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_for_simd_codegen.cpp @@ -1,65 +1,65 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 -// RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK21 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK21 -// RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK23 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK23 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 // expected-no-diagnostics #ifndef HEADER @@ -363,7 +363,7 @@ int bar(int n){ // CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[K]], align 8 // CHECK1-NEXT: store i64 [[TMP12]], ptr [[K_CASTED]], align 8 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, ptr [[K_CASTED]], align 8 -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR3:[0-9]+]] // CHECK1-NEXT: store i32 12, ptr [[LIN]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2 // CHECK1-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2 @@ -424,7 +424,7 @@ int bar(int n){ // CHECK1-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 // CHECK1-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 4 @@ -481,12 +481,12 @@ int bar(int n){ // CHECK1-NEXT: [[TMP73:%.*]] = icmp ne i32 [[TMP72]], 0 // CHECK1-NEXT: br i1 [[TMP73]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] // CHECK1: omp_offload.failed9: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP47]], i64 [[TMP49]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP47]], i64 [[TMP49]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT10]] // CHECK1: omp_offload.cont10: // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1: omp_if.else: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP47]], i64 [[TMP49]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP47]], i64 [[TMP49]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: [[TMP74:%.*]] = load i32, ptr [[A]], align 4 @@ -602,12 +602,12 @@ int bar(int n){ // CHECK1-NEXT: [[TMP132:%.*]] = icmp ne i32 [[TMP131]], 0 // CHECK1-NEXT: br i1 [[TMP132]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] // CHECK1: omp_offload.failed18: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP76]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP78]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP76]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP78]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT19]] // CHECK1: omp_offload.cont19: // CHECK1-NEXT: br label [[OMP_IF_END21:%.*]] // CHECK1: omp_if.else20: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP76]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP78]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP76]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP78]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_IF_END21]] // CHECK1: omp_if.end21: // CHECK1-NEXT: [[TMP133:%.*]] = load i32, ptr [[A]], align 4 @@ -624,7 +624,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -691,7 +691,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 @@ -750,14 +750,14 @@ int bar(int n){ // CHECK1-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 // CHECK1-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK1: omp_offload.failed.i: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR3]] // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] // CHECK1: .omp_outlined..exit: // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 @@ -776,7 +776,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -890,7 +890,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1025,7 +1025,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1148,7 +1148,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1432,12 +1432,12 @@ int bar(int n){ // CHECK1-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 // CHECK1-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1: omp_if.else: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]] @@ -1540,12 +1540,12 @@ int bar(int n){ // CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 // CHECK1-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1: omp_if.else: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4 @@ -1628,12 +1628,12 @@ int bar(int n){ // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1: omp_if.else: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4 @@ -1666,7 +1666,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1789,7 +1789,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1832,7 +1832,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1918,7 +1918,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK1-SAME: () #[[ATTR8:[0-9]+]] { +// CHECK1-SAME: () #[[ATTR7:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) // CHECK1-NEXT: ret void @@ -1988,7 +1988,7 @@ int bar(int n){ // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP9]], ptr [[K]]) #[[ATTR4:[0-9]+]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP9]], ptr [[K]]) #[[ATTR3:[0-9]+]] // CHECK3-NEXT: store i32 12, ptr [[LIN]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2 // CHECK3-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2 @@ -2049,7 +2049,7 @@ int bar(int n){ // CHECK3-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 // CHECK3-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i32 [[TMP11]], i32 [[TMP13]], i32 [[TMP15]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i32 [[TMP11]], i32 [[TMP13]], i32 [[TMP15]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: [[TMP42:%.*]] = load i32, ptr [[A]], align 4 @@ -2106,12 +2106,12 @@ int bar(int n){ // CHECK3-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 // CHECK3-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] // CHECK3: omp_offload.failed9: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP43]], i32 [[TMP45]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP43]], i32 [[TMP45]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT10]] // CHECK3: omp_offload.cont10: // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3: omp_if.else: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP43]], i32 [[TMP45]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP43]], i32 [[TMP45]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_IF_END]] // CHECK3: omp_if.end: // CHECK3-NEXT: [[TMP70:%.*]] = load i32, ptr [[A]], align 4 @@ -2229,12 +2229,12 @@ int bar(int n){ // CHECK3-NEXT: [[TMP130:%.*]] = icmp ne i32 [[TMP129]], 0 // CHECK3-NEXT: br i1 [[TMP130]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] // CHECK3: omp_offload.failed18: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP72]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP74]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP72]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP74]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT19]] // CHECK3: omp_offload.cont19: // CHECK3-NEXT: br label [[OMP_IF_END21:%.*]] // CHECK3: omp_if.else20: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP72]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP74]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP72]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP74]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_IF_END21]] // CHECK3: omp_if.end21: // CHECK3-NEXT: [[TMP131:%.*]] = load i32, ptr [[A]], align 4 @@ -2251,7 +2251,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -2318,7 +2318,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4 @@ -2377,14 +2377,14 @@ int bar(int n){ // CHECK3-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 // CHECK3-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK3: omp_offload.failed.i: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR3]] // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] // CHECK3: .omp_outlined..exit: // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 4 @@ -2400,7 +2400,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -2515,7 +2515,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -2650,7 +2650,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -2773,7 +2773,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -3057,12 +3057,12 @@ int bar(int n){ // CHECK3-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 // CHECK3-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3: omp_if.else: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_IF_END]] // CHECK3: omp_if.end: // CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]] @@ -3165,12 +3165,12 @@ int bar(int n){ // CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 // CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3: omp_if.else: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_IF_END]] // CHECK3: omp_if.end: // CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4 @@ -3253,12 +3253,12 @@ int bar(int n){ // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3: omp_if.else: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_IF_END]] // CHECK3: omp_if.end: // CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4 @@ -3291,7 +3291,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -3414,7 +3414,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -3457,7 +3457,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -3543,7 +3543,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK3-SAME: () #[[ATTR8:[0-9]+]] { +// CHECK3-SAME: () #[[ATTR7:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) // CHECK3-NEXT: ret void @@ -3619,7 +3619,7 @@ int bar(int n){ // CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[K]], align 8 // CHECK5-NEXT: store i64 [[TMP12]], ptr [[K_CASTED]], align 8 // CHECK5-NEXT: [[TMP13:%.*]] = load i64, ptr [[K_CASTED]], align 8 -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR4:[0-9]+]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR3:[0-9]+]] // CHECK5-NEXT: store i32 12, ptr [[LIN]], align 4 // CHECK5-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2 // CHECK5-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2 @@ -3680,7 +3680,7 @@ int bar(int n){ // CHECK5-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 // CHECK5-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK5: omp_offload.failed: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK5: omp_offload.cont: // CHECK5-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 4 @@ -3737,12 +3737,12 @@ int bar(int n){ // CHECK5-NEXT: [[TMP73:%.*]] = icmp ne i32 [[TMP72]], 0 // CHECK5-NEXT: br i1 [[TMP73]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] // CHECK5: omp_offload.failed9: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP47]], i64 [[TMP49]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP47]], i64 [[TMP49]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT10]] // CHECK5: omp_offload.cont10: // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] // CHECK5: omp_if.else: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP47]], i64 [[TMP49]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP47]], i64 [[TMP49]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_IF_END]] // CHECK5: omp_if.end: // CHECK5-NEXT: [[TMP74:%.*]] = load i32, ptr [[A]], align 4 @@ -3858,12 +3858,12 @@ int bar(int n){ // CHECK5-NEXT: [[TMP132:%.*]] = icmp ne i32 [[TMP131]], 0 // CHECK5-NEXT: br i1 [[TMP132]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] // CHECK5: omp_offload.failed18: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP76]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP78]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP76]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP78]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT19]] // CHECK5: omp_offload.cont19: // CHECK5-NEXT: br label [[OMP_IF_END21:%.*]] // CHECK5: omp_if.else20: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP76]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP78]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP76]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP78]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_IF_END21]] // CHECK5: omp_if.end21: // CHECK5-NEXT: [[TMP133:%.*]] = load i32, ptr [[A]], align 4 @@ -3880,7 +3880,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -3947,7 +3947,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK5-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK5-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 @@ -4006,14 +4006,14 @@ int bar(int n){ // CHECK5-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 // CHECK5-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK5: omp_offload.failed.i: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR3]] // CHECK5-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] // CHECK5: .omp_outlined..exit: // CHECK5-NEXT: ret i32 0 // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 @@ -4032,7 +4032,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -4146,7 +4146,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -4281,7 +4281,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -4404,7 +4404,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -4709,12 +4709,12 @@ int bar(int n){ // CHECK5-NEXT: [[TMP52:%.*]] = icmp ne i32 [[TMP51]], 0 // CHECK5-NEXT: br i1 [[TMP52]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK5: omp_offload.failed: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(ptr [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], ptr [[VLA]], i64 [[TMP9]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(ptr [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], ptr [[VLA]], i64 [[TMP9]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK5: omp_offload.cont: // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] // CHECK5: omp_if.else: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(ptr [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], ptr [[VLA]], i64 [[TMP9]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(ptr [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], ptr [[VLA]], i64 [[TMP9]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_IF_END]] // CHECK5: omp_if.end: // CHECK5-NEXT: [[TMP53:%.*]] = mul nsw i64 1, [[TMP2]] @@ -4817,12 +4817,12 @@ int bar(int n){ // CHECK5-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 // CHECK5-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK5: omp_offload.failed: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK5: omp_offload.cont: // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] // CHECK5: omp_if.else: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_IF_END]] // CHECK5: omp_if.end: // CHECK5-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4 @@ -4905,12 +4905,12 @@ int bar(int n){ // CHECK5-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 // CHECK5-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK5: omp_offload.failed: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK5: omp_offload.cont: // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] // CHECK5: omp_if.else: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_IF_END]] // CHECK5: omp_if.end: // CHECK5-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4 @@ -4959,7 +4959,7 @@ int bar(int n){ // CHECK5-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4 // CHECK5-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], ptr [[TMP4]], i64 [[TMP8]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], ptr [[TMP4]], i64 [[TMP8]]) #[[ATTR3]] // CHECK5-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) // CHECK5-NEXT: br label [[OMP_IF_END]] // CHECK5: omp_if.end: @@ -4967,7 +4967,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -5152,7 +5152,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -5195,7 +5195,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -5281,7 +5281,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK5-SAME: () #[[ATTR8:[0-9]+]] { +// CHECK5-SAME: () #[[ATTR7:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: call void @__tgt_register_requires(i64 1) // CHECK5-NEXT: ret void @@ -5351,7 +5351,7 @@ int bar(int n){ // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // CHECK7-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP9]], ptr [[K]]) #[[ATTR4:[0-9]+]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP9]], ptr [[K]]) #[[ATTR3:[0-9]+]] // CHECK7-NEXT: store i32 12, ptr [[LIN]], align 4 // CHECK7-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2 // CHECK7-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2 @@ -5412,7 +5412,7 @@ int bar(int n){ // CHECK7-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 // CHECK7-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK7: omp_offload.failed: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i32 [[TMP11]], i32 [[TMP13]], i32 [[TMP15]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i32 [[TMP11]], i32 [[TMP13]], i32 [[TMP15]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK7: omp_offload.cont: // CHECK7-NEXT: [[TMP42:%.*]] = load i32, ptr [[A]], align 4 @@ -5469,12 +5469,12 @@ int bar(int n){ // CHECK7-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 // CHECK7-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] // CHECK7: omp_offload.failed9: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP43]], i32 [[TMP45]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP43]], i32 [[TMP45]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT10]] // CHECK7: omp_offload.cont10: // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] // CHECK7: omp_if.else: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP43]], i32 [[TMP45]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP43]], i32 [[TMP45]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_IF_END]] // CHECK7: omp_if.end: // CHECK7-NEXT: [[TMP70:%.*]] = load i32, ptr [[A]], align 4 @@ -5592,12 +5592,12 @@ int bar(int n){ // CHECK7-NEXT: [[TMP130:%.*]] = icmp ne i32 [[TMP129]], 0 // CHECK7-NEXT: br i1 [[TMP130]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] // CHECK7: omp_offload.failed18: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP72]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP74]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP72]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP74]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT19]] // CHECK7: omp_offload.cont19: // CHECK7-NEXT: br label [[OMP_IF_END21:%.*]] // CHECK7: omp_if.else20: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP72]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP74]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP72]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP74]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_IF_END21]] // CHECK7: omp_if.end21: // CHECK7-NEXT: [[TMP131:%.*]] = load i32, ptr [[A]], align 4 @@ -5614,7 +5614,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined -// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -5681,7 +5681,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK7-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK7-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4 @@ -5740,14 +5740,14 @@ int bar(int n){ // CHECK7-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 // CHECK7-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK7: omp_offload.failed.i: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR3]] // CHECK7-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] // CHECK7: .omp_outlined..exit: // CHECK7-NEXT: ret i32 0 // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK7-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 4 @@ -5763,7 +5763,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined -// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -5878,7 +5878,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined -// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -6013,7 +6013,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined -// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -6136,7 +6136,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined -// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -6441,12 +6441,12 @@ int bar(int n){ // CHECK7-NEXT: [[TMP52:%.*]] = icmp ne i32 [[TMP51]], 0 // CHECK7-NEXT: br i1 [[TMP52]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK7: omp_offload.failed: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(ptr [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], ptr [[VLA]], i32 [[TMP8]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(ptr [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], ptr [[VLA]], i32 [[TMP8]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK7: omp_offload.cont: // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] // CHECK7: omp_if.else: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(ptr [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], ptr [[VLA]], i32 [[TMP8]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(ptr [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], ptr [[VLA]], i32 [[TMP8]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_IF_END]] // CHECK7: omp_if.end: // CHECK7-NEXT: [[TMP53:%.*]] = mul nsw i32 1, [[TMP1]] @@ -6549,12 +6549,12 @@ int bar(int n){ // CHECK7-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 // CHECK7-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK7: omp_offload.failed: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK7: omp_offload.cont: // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] // CHECK7: omp_if.else: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_IF_END]] // CHECK7: omp_if.end: // CHECK7-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4 @@ -6637,12 +6637,12 @@ int bar(int n){ // CHECK7-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 // CHECK7-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK7: omp_offload.failed: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK7: omp_offload.cont: // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] // CHECK7: omp_if.else: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_IF_END]] // CHECK7: omp_if.end: // CHECK7-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4 @@ -6691,7 +6691,7 @@ int bar(int n){ // CHECK7-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4 // CHECK7-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], ptr [[TMP4]], i32 [[TMP8]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], ptr [[TMP4]], i32 [[TMP8]]) #[[ATTR3]] // CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) // CHECK7-NEXT: br label [[OMP_IF_END]] // CHECK7: omp_if.end: @@ -6699,7 +6699,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined -// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -6884,7 +6884,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined -// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -6927,7 +6927,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined -// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -7013,7 +7013,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK7-SAME: () #[[ATTR8:[0-9]+]] { +// CHECK7-SAME: () #[[ATTR7:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: call void @__tgt_register_requires(i64 1) // CHECK7-NEXT: ret void @@ -9031,7 +9031,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -9123,7 +9123,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -9151,7 +9151,7 @@ int bar(int n){ // CHECK17-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR4:[0-9]+]] // CHECK17-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 // CHECK17-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 // CHECK17-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 @@ -9239,7 +9239,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK17-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK17-SAME: () #[[ATTR2:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: ret i64 0 // @@ -9264,7 +9264,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -9387,7 +9387,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -9565,7 +9565,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -9611,7 +9611,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -9728,7 +9728,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -9821,7 +9821,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -9913,7 +9913,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -9941,7 +9941,7 @@ int bar(int n){ // CHECK19-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR4:[0-9]+]] // CHECK19-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 // CHECK19-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 // CHECK19-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 @@ -10029,7 +10029,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK19-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK19-SAME: () #[[ATTR2:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: ret i64 0 // @@ -10054,7 +10054,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -10177,7 +10177,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -10355,7 +10355,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -10401,7 +10401,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -10518,7 +10518,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -10611,7 +10611,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined -// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -10703,7 +10703,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined -// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -10731,7 +10731,7 @@ int bar(int n){ // CHECK21-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK21-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK21-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR4:[0-9]+]] // CHECK21-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 // CHECK21-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 // CHECK21-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 @@ -10819,7 +10819,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK21-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK21-SAME: () #[[ATTR2:[0-9]+]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: ret i64 0 // @@ -10844,7 +10844,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined -// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -10967,7 +10967,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined -// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -11145,7 +11145,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined -// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -11207,7 +11207,7 @@ int bar(int n){ // CHECK21-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) // CHECK21-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4 // CHECK21-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK21-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], ptr [[TMP4]], i64 [[TMP8]]) #[[ATTR2:[0-9]+]] +// CHECK21-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], ptr [[TMP4]], i64 [[TMP8]]) #[[ATTR1:[0-9]+]] // CHECK21-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) // CHECK21-NEXT: br label [[OMP_IF_END]] // CHECK21: omp_if.end: @@ -11215,7 +11215,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined -// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -11394,7 +11394,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined -// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -11487,7 +11487,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined -// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -11579,7 +11579,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined -// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -11607,7 +11607,7 @@ int bar(int n){ // CHECK23-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK23-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK23-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR4:[0-9]+]] // CHECK23-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8 // CHECK23-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 // CHECK23-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 @@ -11695,7 +11695,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK23-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK23-SAME: () #[[ATTR2:[0-9]+]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: ret i64 0 // @@ -11720,7 +11720,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined -// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -11843,7 +11843,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined -// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -12021,7 +12021,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined -// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -12083,7 +12083,7 @@ int bar(int n){ // CHECK23-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) // CHECK23-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4 // CHECK23-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK23-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], ptr [[TMP4]], i32 [[TMP8]]) #[[ATTR2:[0-9]+]] +// CHECK23-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], ptr [[TMP4]], i32 [[TMP8]]) #[[ATTR1:[0-9]+]] // CHECK23-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) // CHECK23-NEXT: br label [[OMP_IF_END]] // CHECK23: omp_if.end: @@ -12091,7 +12091,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined -// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -12270,7 +12270,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined -// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 diff --git a/clang/test/OpenMP/target_parallel_for_simd_depend_codegen.cpp b/clang/test/OpenMP/target_parallel_for_simd_depend_codegen.cpp index 3d9868179dca6..f848922a034e6 100644 --- a/clang/test/OpenMP/target_parallel_for_simd_depend_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_for_simd_depend_codegen.cpp @@ -1,37 +1,37 @@ // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s // SIMD-ONLY1-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/target_parallel_for_simd_linear_messages.cpp b/clang/test/OpenMP/target_parallel_for_simd_linear_messages.cpp index 36f9f2967b2a9..1da49a9a5e4c4 100644 --- a/clang/test/OpenMP/target_parallel_for_simd_linear_messages.cpp +++ b/clang/test/OpenMP/target_parallel_for_simd_linear_messages.cpp @@ -1,6 +1,8 @@ // RUN: %clang_cc1 -verify -fopenmp %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp -fopenmp-version=52 -DOMP52 %s -Wuninitialized // RUN: %clang_cc1 -verify -fopenmp-simd %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp-simd -fopenmp-version=52 -DOMP52 %s -Wuninitialized #pragma omp requires dynamic_allocators @@ -16,8 +18,8 @@ extern const omp_allocator_handle_t omp_pteam_mem_alloc; extern const omp_allocator_handle_t omp_thread_mem_alloc; void xxx(int argc) { - int i, lin, step; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step' to silence this warning}} -#pragma omp target parallel for simd linear(i, lin : step) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step' is uninitialized when used here}} + int i, lin, step_sz; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step_sz' to silence this warning}} +#pragma omp target parallel for simd linear(i, lin : step_sz) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step_sz' is uninitialized when used here}} for (i = 0; i < 10; ++i) ; } @@ -272,16 +274,28 @@ int main(int argc, char **argv) { #pragma omp target parallel for simd linear(i) for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 +#pragma omp target parallel for simd linear(i : uval, step(4)) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} +#else #pragma omp target parallel for simd linear(i : 4) +#endif for (int k = 0; k < argc; ++k) { ++k; i += 4; } } +#ifdef OMP52 +#pragma omp target parallel for simd linear(j: step() //omp52-error 2 {{expected expression}} omp52-error{{expected ')'}} omp52-note{{to match this '('}} +#else #pragma omp target parallel for simd linear(j) +#endif for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 +#pragma omp target parallel for simd linear(i: step(1), step(2)) // omp52-error {{multiple 'step size' found in linear clause}} +#else #pragma omp target parallel for simd linear(i) +#endif for (int k = 0; k < argc; ++k) ++k; diff --git a/clang/test/OpenMP/target_parallel_for_simd_map_messages.cpp b/clang/test/OpenMP/target_parallel_for_simd_map_messages.cpp index fed418e619761..a7cd7e4ebc1b5 100644 --- a/clang/test/OpenMP/target_parallel_for_simd_map_messages.cpp +++ b/clang/test/OpenMP/target_parallel_for_simd_map_messages.cpp @@ -1,10 +1,12 @@ // RUN: %clang_cc1 -verify=expected,lt50,lt51 -fopenmp -fno-openmp-extensions -fopenmp-version=45 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,lt51 -fopenmp -fno-openmp-extensions -fopenmp-version=50 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,ge51 -fopenmp -fno-openmp-extensions %s -Wno-openmp-mapping -Wuninitialized +// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp52 -fopenmp -fno-openmp-extensions -fopenmp-version=52 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,lt50,lt51 -fopenmp-simd -fno-openmp-extensions -fopenmp-version=45 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,lt51 -fopenmp-simd -fno-openmp-extensions -fopenmp-version=50 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,ge51 -fopenmp-simd -fno-openmp-extensions %s -Wno-openmp-mapping -Wuninitialized +// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp52 -fopenmp-simd -fno-openmp-extensions -fopenmp-version=52 %s -Wno-openmp-mapping -Wuninitialized void foo() { } @@ -307,6 +309,8 @@ int main(int argc, char **argv) { for (i = 0; i < argc; ++i) foo(); #pragma omp target parallel for simd map(always, tofrom: always, tofrom, x) for (i = 0; i < argc; ++i) foo(); +#pragma omp target parallel for simd map(always tofrom: x) // omp52-error {{missing ',' after map type modifier}} + for (i = 0; i < argc; ++i) foo(); #pragma omp target parallel for simd map(tofrom j) // expected-error {{expected ',' or ')' in 'map' clause}} for (i = 0; i < argc; ++i) foo(); #pragma omp target parallel for simd map(delete: j) // expected-error {{map type 'delete' is not allowed for '#pragma omp target parallel for simd'}} diff --git a/clang/test/OpenMP/target_parallel_generic_loop_codegen-3.cpp b/clang/test/OpenMP/target_parallel_generic_loop_codegen-3.cpp index b92d173e13d63..a8e55c51aafd8 100644 --- a/clang/test/OpenMP/target_parallel_generic_loop_codegen-3.cpp +++ b/clang/test/OpenMP/target_parallel_generic_loop_codegen-3.cpp @@ -55,7 +55,7 @@ int main() { return 0; } // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug__ -// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]], i1 noundef zeroext [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG13:![0-9]+]] { +// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]], i1 noundef zeroext [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG22:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr addrspace(1), align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -68,56 +68,56 @@ int main() { // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8 // CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META31:![0-9]+]], metadata !DIExpression()), !dbg [[DBG32:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META40:![0-9]+]], metadata !DIExpression()), !dbg [[DBG41:![0-9]+]] // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META33:![0-9]+]], metadata !DIExpression()), !dbg [[DBG34:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META42:![0-9]+]], metadata !DIExpression()), !dbg [[DBG43:![0-9]+]] // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META35:![0-9]+]], metadata !DIExpression()), !dbg [[DBG36:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META44:![0-9]+]], metadata !DIExpression()), !dbg [[DBG45:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META37:![0-9]+]], metadata !DIExpression()), !dbg [[DBG38:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META46:![0-9]+]], metadata !DIExpression()), !dbg [[DBG47:![0-9]+]] // CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[DOTCAPTURE_EXPR_]] to i8 // CHECK1-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTCAPTURE_EXPR__ADDR]], metadata [[META39:![0-9]+]], metadata !DIExpression()), !dbg [[DBG40:![0-9]+]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG41:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG41]] -// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG41]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG41]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG41]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8, !dbg [[DBG41]] -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG41]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG41]] -// CHECK1-NEXT: [[TMP6:%.*]] = addrspacecast ptr addrspace(1) [[TMP5]] to ptr, !dbg [[DBG41]] -// CHECK1-NEXT: store ptr [[TMP6]], ptr [[_TMP2]], align 8, !dbg [[DBG41]] -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG41]] -// CHECK1-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_kernel_environment), !dbg [[DBG41]] -// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1, !dbg [[DBG41]] -// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG41]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTCAPTURE_EXPR__ADDR]], metadata [[META48:![0-9]+]], metadata !DIExpression()), !dbg [[DBG49:![0-9]+]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG50:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG50]] +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG50]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG50]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG50]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8, !dbg [[DBG50]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG50]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG50]] +// CHECK1-NEXT: [[TMP6:%.*]] = addrspacecast ptr addrspace(1) [[TMP5]] to ptr, !dbg [[DBG50]] +// CHECK1-NEXT: store ptr [[TMP6]], ptr [[_TMP2]], align 8, !dbg [[DBG50]] +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG50]] +// CHECK1-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_kernel_environment), !dbg [[DBG50]] +// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1, !dbg [[DBG50]] +// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG50]] // CHECK1: user_code.entry: // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6:[0-9]+]]) -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG42:![0-9]+]] -// CHECK1-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4, !dbg [[DBG42]] -// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG42]] -// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG42]] -// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP12]], align 8, !dbg [[DBG42]] -// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG42]] -// CHECK1-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP11]] to ptr, !dbg [[DBG42]] -// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8, !dbg [[DBG42]] -// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG42]] -// CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP15]], align 8, !dbg [[DBG42]] -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG42]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[TMP16]], align 8, !dbg [[DBG42]] -// CHECK1-NEXT: [[TMP17:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !dbg [[DBG43:![0-9]+]] -// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP17]] to i1, !dbg [[DBG43]] -// CHECK1-NEXT: [[TMP18:%.*]] = zext i1 [[TOBOOL]] to i32, !dbg [[DBG42]] -// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB6]], i32 [[TMP9]], i32 [[TMP18]], i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4), !dbg [[DBG42]] -// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG45:![0-9]+]] -// CHECK1-NEXT: ret void, !dbg [[DBG46:![0-9]+]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG51:![0-9]+]] +// CHECK1-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4, !dbg [[DBG51]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG51]] +// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG51]] +// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP12]], align 8, !dbg [[DBG51]] +// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG51]] +// CHECK1-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP11]] to ptr, !dbg [[DBG51]] +// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8, !dbg [[DBG51]] +// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG51]] +// CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP15]], align 8, !dbg [[DBG51]] +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG51]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[TMP16]], align 8, !dbg [[DBG51]] +// CHECK1-NEXT: [[TMP17:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !dbg [[DBG52:![0-9]+]] +// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP17]] to i1, !dbg [[DBG52]] +// CHECK1-NEXT: [[TMP18:%.*]] = zext i1 [[TOBOOL]] to i32, !dbg [[DBG51]] +// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB6]], i32 [[TMP9]], i32 [[TMP18]], i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4), !dbg [[DBG51]] +// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG54:![0-9]+]] +// CHECK1-NEXT: ret void, !dbg [[DBG55:![0-9]+]] // CHECK1: worker.exit: -// CHECK1-NEXT: ret void, !dbg [[DBG41]] +// CHECK1-NEXT: ret void, !dbg [[DBG50]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug___omp_outlined_debug__ -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG47:![0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR2:[0-9]+]] !dbg [[DBG56:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -141,149 +141,149 @@ int main() { // CHECK1-NEXT: [[H:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[D:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META54:![0-9]+]], metadata !DIExpression()), !dbg [[DBG55:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META63:![0-9]+]], metadata !DIExpression()), !dbg [[DBG64:![0-9]+]] // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META56:![0-9]+]], metadata !DIExpression()), !dbg [[DBG55]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META65:![0-9]+]], metadata !DIExpression()), !dbg [[DBG64]] // CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META57:![0-9]+]], metadata !DIExpression()), !dbg [[DBG58:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META66:![0-9]+]], metadata !DIExpression()), !dbg [[DBG67:![0-9]+]] // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META59:![0-9]+]], metadata !DIExpression()), !dbg [[DBG60:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META68:![0-9]+]], metadata !DIExpression()), !dbg [[DBG69:![0-9]+]] // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META61:![0-9]+]], metadata !DIExpression()), !dbg [[DBG62:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META70:![0-9]+]], metadata !DIExpression()), !dbg [[DBG71:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META63:![0-9]+]], metadata !DIExpression()), !dbg [[DBG64:![0-9]+]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG65:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG65]] -// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG65]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG65]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG65]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8, !dbg [[DBG65]] -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG65]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG65]] -// CHECK1-NEXT: [[TMP6:%.*]] = addrspacecast ptr addrspace(1) [[TMP5]] to ptr, !dbg [[DBG65]] -// CHECK1-NEXT: store ptr [[TMP6]], ptr [[_TMP2]], align 8, !dbg [[DBG65]] -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG65]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_IV]], metadata [[META66:![0-9]+]], metadata !DIExpression()), !dbg [[DBG55]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_LB]], metadata [[META67:![0-9]+]], metadata !DIExpression()), !dbg [[DBG55]] -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG68:![0-9]+]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_UB]], metadata [[META69:![0-9]+]], metadata !DIExpression()), !dbg [[DBG55]] -// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_STRIDE]], metadata [[META70:![0-9]+]], metadata !DIExpression()), !dbg [[DBG55]] -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_IS_LAST]], metadata [[META71:![0-9]+]], metadata !DIExpression()), !dbg [[DBG55]] -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B4]], metadata [[META72:![0-9]+]], metadata !DIExpression()), !dbg [[DBG55]] -// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B4]], ptr align 4 [[TMP4]], i64 400, i1 false), !dbg [[DBG65]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[I]], metadata [[META73:![0-9]+]], metadata !DIExpression()), !dbg [[DBG55]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG65]] -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4, !dbg [[DBG65]] -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3:[0-9]+]], i32 [[TMP9]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG74:![0-9]+]] -// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG65]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META72:![0-9]+]], metadata !DIExpression()), !dbg [[DBG73:![0-9]+]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG74:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG74]] +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG74]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG74]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG74]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8, !dbg [[DBG74]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG74]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG74]] +// CHECK1-NEXT: [[TMP6:%.*]] = addrspacecast ptr addrspace(1) [[TMP5]] to ptr, !dbg [[DBG74]] +// CHECK1-NEXT: store ptr [[TMP6]], ptr [[_TMP2]], align 8, !dbg [[DBG74]] +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG74]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_IV]], metadata [[META75:![0-9]+]], metadata !DIExpression()), !dbg [[DBG64]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_LB]], metadata [[META76:![0-9]+]], metadata !DIExpression()), !dbg [[DBG64]] +// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG77:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_UB]], metadata [[META78:![0-9]+]], metadata !DIExpression()), !dbg [[DBG64]] +// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_STRIDE]], metadata [[META79:![0-9]+]], metadata !DIExpression()), !dbg [[DBG64]] +// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_IS_LAST]], metadata [[META80:![0-9]+]], metadata !DIExpression()), !dbg [[DBG64]] +// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B4]], metadata [[META81:![0-9]+]], metadata !DIExpression()), !dbg [[DBG64]] +// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B4]], ptr align 4 [[TMP4]], i64 400, i1 false), !dbg [[DBG74]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[I]], metadata [[META82:![0-9]+]], metadata !DIExpression()), !dbg [[DBG64]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG74]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4, !dbg [[DBG74]] +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3:[0-9]+]], i32 [[TMP9]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG83:![0-9]+]] +// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG74]] // CHECK1: omp.dispatch.cond: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9, !dbg [[DBG68]] -// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG68]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9, !dbg [[DBG77]] +// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG77]] // CHECK1: cond.true: -// CHECK1-NEXT: br label [[COND_END:%.*]], !dbg [[DBG68]] +// CHECK1-NEXT: br label [[COND_END:%.*]], !dbg [[DBG77]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: br label [[COND_END]], !dbg [[DBG68]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: br label [[COND_END]], !dbg [[DBG77]] // CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ], !dbg [[DBG68]] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]], !dbg [[DBG65]] -// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG65]] +// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ], !dbg [[DBG77]] +// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]], !dbg [[DBG74]] +// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG74]] // CHECK1: omp.dispatch.body: -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG65]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG74]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]], !dbg [[DBG65]] -// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG65]] +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]], !dbg [[DBG74]] +// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG74]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1, !dbg [[DBG75:![0-9]+]] -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG75]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG75]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[F]], metadata [[META76:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG80:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG80]] -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], i64 0, i64 1, !dbg [[DBG80]] -// CHECK1-NEXT: store ptr [[ARRAYIDX8]], ptr [[F]], align 8, !dbg [[DBG79]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[G]], metadata [[META81:![0-9]+]], metadata !DIExpression()), !dbg [[DBG82:![0-9]+]] -// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[DBG82]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[H]], metadata [[META83:![0-9]+]], metadata !DIExpression()), !dbg [[DBG84:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 1, !dbg [[DBG85:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX9]], i64 0, i64 1, !dbg [[DBG85]] -// CHECK1-NEXT: store ptr [[ARRAYIDX10]], ptr [[H]], align 8, !dbg [[DBG84]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[D]], metadata [[META86:![0-9]+]], metadata !DIExpression()), !dbg [[DBG87:![0-9]+]] -// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[DBG87]] -// CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG88:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG89:![0-9]+]] -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG90:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64, !dbg [[DBG89]] -// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM]], !dbg [[DBG89]] -// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX12]], align 4, !dbg [[DBG91:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG92:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG92]] -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG93:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG92]] -// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG92]] -// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX16]], align 4, !dbg [[DBG94:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG95:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX17]], i64 0, i64 0, !dbg [[DBG95]] -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG96:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP20]] to i64, !dbg [[DBG95]] -// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG95]] -// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[ARRAYIDX20]], align 4, !dbg [[DBG95]] -// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG97:![0-9]+]] -// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG98:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG97]] -// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG97]] -// CHECK1-NEXT: store i32 [[TMP21]], ptr [[ARRAYIDX23]], align 4, !dbg [[DBG99:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG100:![0-9]+]] -// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG101:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG100]] -// CHECK1-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX24]], i64 0, i64 [[IDXPROM25]], !dbg [[DBG100]] -// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[ARRAYIDX26]], align 4, !dbg [[DBG100]] -// CHECK1-NEXT: [[TMP25:%.*]] = load i8, ptr [[TMP7]], align 1, !dbg [[DBG102:![0-9]+]] -// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP25]] to i1, !dbg [[DBG102]] -// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TOBOOL]] to i32, !dbg [[DBG102]] -// CHECK1-NEXT: [[OR:%.*]] = or i32 [[CONV]], [[TMP24]], !dbg [[DBG102]] -// CHECK1-NEXT: [[TOBOOL27:%.*]] = icmp ne i32 [[OR]], 0, !dbg [[DBG102]] -// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL27]] to i8, !dbg [[DBG102]] -// CHECK1-NEXT: store i8 [[FROMBOOL]], ptr [[TMP7]], align 1, !dbg [[DBG102]] -// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG103:![0-9]+]] +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1, !dbg [[DBG84:![0-9]+]] +// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG84]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG84]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[F]], metadata [[META85:![0-9]+]], metadata !DIExpression()), !dbg [[DBG88:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG89:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG89]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], i64 0, i64 1, !dbg [[DBG89]] +// CHECK1-NEXT: store ptr [[ARRAYIDX8]], ptr [[F]], align 8, !dbg [[DBG88]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[G]], metadata [[META90:![0-9]+]], metadata !DIExpression()), !dbg [[DBG91:![0-9]+]] +// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[DBG91]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[H]], metadata [[META92:![0-9]+]], metadata !DIExpression()), !dbg [[DBG93:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 1, !dbg [[DBG94:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX9]], i64 0, i64 1, !dbg [[DBG94]] +// CHECK1-NEXT: store ptr [[ARRAYIDX10]], ptr [[H]], align 8, !dbg [[DBG93]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[D]], metadata [[META95:![0-9]+]], metadata !DIExpression()), !dbg [[DBG96:![0-9]+]] +// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[DBG96]] +// CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG97:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG98:![0-9]+]] +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG99:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64, !dbg [[DBG98]] +// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM]], !dbg [[DBG98]] +// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX12]], align 4, !dbg [[DBG100:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG101:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG101]] +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG102:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG101]] +// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG101]] +// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX16]], align 4, !dbg [[DBG103:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG104:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX17]], i64 0, i64 0, !dbg [[DBG104]] +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG105:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP20]] to i64, !dbg [[DBG104]] +// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG104]] +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[ARRAYIDX20]], align 4, !dbg [[DBG104]] +// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG106:![0-9]+]] +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG107:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG106]] +// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG106]] +// CHECK1-NEXT: store i32 [[TMP21]], ptr [[ARRAYIDX23]], align 4, !dbg [[DBG108:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG109:![0-9]+]] +// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG110:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG109]] +// CHECK1-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX24]], i64 0, i64 [[IDXPROM25]], !dbg [[DBG109]] +// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[ARRAYIDX26]], align 4, !dbg [[DBG109]] +// CHECK1-NEXT: [[TMP25:%.*]] = load i8, ptr [[TMP7]], align 1, !dbg [[DBG111:![0-9]+]] +// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP25]] to i1, !dbg [[DBG111]] +// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TOBOOL]] to i32, !dbg [[DBG111]] +// CHECK1-NEXT: [[OR:%.*]] = or i32 [[CONV]], [[TMP24]], !dbg [[DBG111]] +// CHECK1-NEXT: [[TOBOOL27:%.*]] = icmp ne i32 [[OR]], 0, !dbg [[DBG111]] +// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL27]] to i8, !dbg [[DBG111]] +// CHECK1-NEXT: store i8 [[FROMBOOL]], ptr [[TMP7]], align 1, !dbg [[DBG111]] +// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG112:![0-9]+]] // CHECK1: omp.body.continue: -// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG74]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG83]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP26]], 1, !dbg [[DBG65]] -// CHECK1-NEXT: store i32 [[ADD28]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG65]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG74]], !llvm.loop [[LOOP104:![0-9]+]] +// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP26]], 1, !dbg [[DBG74]] +// CHECK1-NEXT: store i32 [[ADD28]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG74]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG83]], !llvm.loop [[LOOP113:![0-9]+]] // CHECK1: omp.inner.for.end: -// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG74]] +// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG83]] // CHECK1: omp.dispatch.inc: -// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP27]], [[TMP28]], !dbg [[DBG65]] -// CHECK1-NEXT: store i32 [[ADD29]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG65]] -// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG68]] -// CHECK1-NEXT: [[ADD30:%.*]] = add nsw i32 [[TMP29]], [[TMP30]], !dbg [[DBG65]] -// CHECK1-NEXT: store i32 [[ADD30]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG65]] -// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG74]], !llvm.loop [[LOOP106:![0-9]+]] +// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP27]], [[TMP28]], !dbg [[DBG74]] +// CHECK1-NEXT: store i32 [[ADD29]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG74]] +// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG77]] +// CHECK1-NEXT: [[ADD30:%.*]] = add nsw i32 [[TMP29]], [[TMP30]], !dbg [[DBG74]] +// CHECK1-NEXT: store i32 [[ADD30]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG74]] +// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG83]], !llvm.loop [[LOOP115:![0-9]+]] // CHECK1: omp.dispatch.end: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB5:[0-9]+]], i32 [[TMP9]]), !dbg [[DBG105:![0-9]+]] -// CHECK1-NEXT: ret void, !dbg [[DBG107:![0-9]+]] +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB5:[0-9]+]], i32 [[TMP9]]), !dbg [[DBG114:![0-9]+]] +// CHECK1-NEXT: ret void, !dbg [[DBG116:![0-9]+]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug___omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG108:![0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR2]] !dbg [[DBG117:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -292,34 +292,34 @@ int main() { // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META115:![0-9]+]], metadata !DIExpression()), !dbg [[DBG116:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META124:![0-9]+]], metadata !DIExpression()), !dbg [[DBG125:![0-9]+]] // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META117:![0-9]+]], metadata !DIExpression()), !dbg [[DBG116]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META126:![0-9]+]], metadata !DIExpression()), !dbg [[DBG125]] // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META118:![0-9]+]], metadata !DIExpression()), !dbg [[DBG116]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META127:![0-9]+]], metadata !DIExpression()), !dbg [[DBG125]] // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META119:![0-9]+]], metadata !DIExpression()), !dbg [[DBG116]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META128:![0-9]+]], metadata !DIExpression()), !dbg [[DBG125]] // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META120:![0-9]+]], metadata !DIExpression()), !dbg [[DBG116]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META129:![0-9]+]], metadata !DIExpression()), !dbg [[DBG125]] // CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META121:![0-9]+]], metadata !DIExpression()), !dbg [[DBG116]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG122:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG122]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG122]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG122]] -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG122]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG122]] -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG122]] -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG122]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG122]] -// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG122]] -// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG122]] -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug___omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], ptr addrspace(1) [[TMP9]], i32 [[TMP6]], ptr [[TMP7]], ptr addrspace(1) [[TMP10]]) #[[ATTR3:[0-9]+]], !dbg [[DBG122]] -// CHECK1-NEXT: ret void, !dbg [[DBG122]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META130:![0-9]+]], metadata !DIExpression()), !dbg [[DBG125]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG131:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG131]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG131]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG131]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG131]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG131]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG131]] +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG131]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG131]] +// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG131]] +// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG131]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug___omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], ptr addrspace(1) [[TMP9]], i32 [[TMP6]], ptr [[TMP7]], ptr addrspace(1) [[TMP10]]) #[[ATTR4:[0-9]+]], !dbg [[DBG131]] +// CHECK1-NEXT: ret void, !dbg [[DBG131]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13 -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR5:[0-9]+]] !dbg [[DBG123:![0-9]+]] { +// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR6:[0-9]+]] !dbg [[DBG132:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -327,32 +327,32 @@ int main() { // CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META126:![0-9]+]], metadata !DIExpression()), !dbg [[DBG127:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META135:![0-9]+]], metadata !DIExpression()), !dbg [[DBG136:![0-9]+]] // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META128:![0-9]+]], metadata !DIExpression()), !dbg [[DBG127]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META137:![0-9]+]], metadata !DIExpression()), !dbg [[DBG136]] // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META129:![0-9]+]], metadata !DIExpression()), !dbg [[DBG127]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META138:![0-9]+]], metadata !DIExpression()), !dbg [[DBG136]] // CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META130:![0-9]+]], metadata !DIExpression()), !dbg [[DBG127]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META139:![0-9]+]], metadata !DIExpression()), !dbg [[DBG136]] // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTCAPTURE_EXPR__ADDR]], metadata [[META131:![0-9]+]], metadata !DIExpression()), !dbg [[DBG127]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG132:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG132]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG132]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG132]] -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG132]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG132]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG132]] -// CHECK1-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !dbg [[DBG132]] -// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1, !dbg [[DBG132]] -// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[TMP3]] to ptr addrspace(1), !dbg [[DBG132]] -// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG132]] -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug__(ptr addrspace(1) [[TMP8]], i32 [[TMP4]], ptr [[TMP5]], ptr addrspace(1) [[TMP9]], i1 [[TOBOOL]]) #[[ATTR3]], !dbg [[DBG132]] -// CHECK1-NEXT: ret void, !dbg [[DBG132]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTCAPTURE_EXPR__ADDR]], metadata [[META140:![0-9]+]], metadata !DIExpression()), !dbg [[DBG136]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG141:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG141]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG141]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG141]] +// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG141]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG141]] +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG141]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !dbg [[DBG141]] +// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1, !dbg [[DBG141]] +// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[TMP3]] to ptr addrspace(1), !dbg [[DBG141]] +// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG141]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug__(ptr addrspace(1) [[TMP8]], i32 [[TMP4]], ptr [[TMP5]], ptr addrspace(1) [[TMP9]], i1 [[TOBOOL]]) #[[ATTR4]], !dbg [[DBG141]] +// CHECK1-NEXT: ret void, !dbg [[DBG141]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug__ -// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG133:![0-9]+]] { +// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG142:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr addrspace(1), align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -364,51 +364,51 @@ int main() { // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8 // CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META138:![0-9]+]], metadata !DIExpression()), !dbg [[DBG139:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META147:![0-9]+]], metadata !DIExpression()), !dbg [[DBG148:![0-9]+]] // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META140:![0-9]+]], metadata !DIExpression()), !dbg [[DBG141:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META149:![0-9]+]], metadata !DIExpression()), !dbg [[DBG150:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META142:![0-9]+]], metadata !DIExpression()), !dbg [[DBG143:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META151:![0-9]+]], metadata !DIExpression()), !dbg [[DBG152:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META144:![0-9]+]], metadata !DIExpression()), !dbg [[DBG145:![0-9]+]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG146:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG146]] -// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG146]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG146]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG146]] -// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG146]] -// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG146]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG146]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG146]] -// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG146]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG146]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG146]] -// CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_kernel_environment), !dbg [[DBG146]] -// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP9]], -1, !dbg [[DBG146]] -// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG146]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META153:![0-9]+]], metadata !DIExpression()), !dbg [[DBG154:![0-9]+]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG155:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG155]] +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG155]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG155]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG155]] +// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG155]] +// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG155]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG155]] +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG155]] +// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG155]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG155]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG155]] +// CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_kernel_environment), !dbg [[DBG155]] +// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP9]], -1, !dbg [[DBG155]] +// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG155]] // CHECK1: user_code.entry: // CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB13:[0-9]+]]) -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG147:![0-9]+]] -// CHECK1-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4, !dbg [[DBG147]] -// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG147]] -// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG147]] -// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP13]], align 8, !dbg [[DBG147]] -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG147]] -// CHECK1-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP12]] to ptr, !dbg [[DBG147]] -// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8, !dbg [[DBG147]] -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG147]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 8, !dbg [[DBG147]] -// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG147]] -// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP17]], align 8, !dbg [[DBG147]] -// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB13]], i32 [[TMP10]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4), !dbg [[DBG147]] -// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG148:![0-9]+]] -// CHECK1-NEXT: ret void, !dbg [[DBG150:![0-9]+]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG156:![0-9]+]] +// CHECK1-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4, !dbg [[DBG156]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG156]] +// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG156]] +// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP13]], align 8, !dbg [[DBG156]] +// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG156]] +// CHECK1-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP12]] to ptr, !dbg [[DBG156]] +// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8, !dbg [[DBG156]] +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG156]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 8, !dbg [[DBG156]] +// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG156]] +// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP17]], align 8, !dbg [[DBG156]] +// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB13]], i32 [[TMP10]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4), !dbg [[DBG156]] +// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG157:![0-9]+]] +// CHECK1-NEXT: ret void, !dbg [[DBG159:![0-9]+]] // CHECK1: worker.exit: -// CHECK1-NEXT: ret void, !dbg [[DBG146]] +// CHECK1-NEXT: ret void, !dbg [[DBG155]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___omp_outlined_debug__ -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG151:![0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR2]] !dbg [[DBG160:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -431,140 +431,140 @@ int main() { // CHECK1-NEXT: [[H:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[D:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META154:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META163:![0-9]+]], metadata !DIExpression()), !dbg [[DBG164:![0-9]+]] // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META156:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META165:![0-9]+]], metadata !DIExpression()), !dbg [[DBG164]] // CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META157:![0-9]+]], metadata !DIExpression()), !dbg [[DBG158:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META166:![0-9]+]], metadata !DIExpression()), !dbg [[DBG167:![0-9]+]] // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META159:![0-9]+]], metadata !DIExpression()), !dbg [[DBG160:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META168:![0-9]+]], metadata !DIExpression()), !dbg [[DBG169:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META161:![0-9]+]], metadata !DIExpression()), !dbg [[DBG162:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META170:![0-9]+]], metadata !DIExpression()), !dbg [[DBG171:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META163:![0-9]+]], metadata !DIExpression()), !dbg [[DBG164:![0-9]+]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG165:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG165]] -// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG165]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG165]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG165]] -// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG165]] -// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG165]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG165]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG165]] -// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG165]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG165]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG165]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_IV]], metadata [[META166:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_LB]], metadata [[META167:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155]] -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG168:![0-9]+]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_UB]], metadata [[META169:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155]] -// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_STRIDE]], metadata [[META170:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155]] -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_IS_LAST]], metadata [[META171:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155]] -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[I]], metadata [[META172:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155]] -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG165]] -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4, !dbg [[DBG165]] -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB10:[0-9]+]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG173:![0-9]+]] -// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG165]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META172:![0-9]+]], metadata !DIExpression()), !dbg [[DBG173:![0-9]+]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG174:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG174]] +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG174]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG174]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG174]] +// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG174]] +// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG174]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG174]] +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG174]] +// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG174]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG174]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG174]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_IV]], metadata [[META175:![0-9]+]], metadata !DIExpression()), !dbg [[DBG164]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_LB]], metadata [[META176:![0-9]+]], metadata !DIExpression()), !dbg [[DBG164]] +// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG177:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_UB]], metadata [[META178:![0-9]+]], metadata !DIExpression()), !dbg [[DBG164]] +// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_STRIDE]], metadata [[META179:![0-9]+]], metadata !DIExpression()), !dbg [[DBG164]] +// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_IS_LAST]], metadata [[META180:![0-9]+]], metadata !DIExpression()), !dbg [[DBG164]] +// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[I]], metadata [[META181:![0-9]+]], metadata !DIExpression()), !dbg [[DBG164]] +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG174]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4, !dbg [[DBG174]] +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB10:[0-9]+]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG182:![0-9]+]] +// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG174]] // CHECK1: omp.dispatch.cond: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9, !dbg [[DBG168]] -// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG168]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9, !dbg [[DBG177]] +// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG177]] // CHECK1: cond.true: -// CHECK1-NEXT: br label [[COND_END:%.*]], !dbg [[DBG168]] +// CHECK1-NEXT: br label [[COND_END:%.*]], !dbg [[DBG177]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: br label [[COND_END]], !dbg [[DBG168]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: br label [[COND_END]], !dbg [[DBG177]] // CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ], !dbg [[DBG168]] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]], !dbg [[DBG165]] -// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG165]] +// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ], !dbg [[DBG177]] +// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]], !dbg [[DBG174]] +// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG174]] // CHECK1: omp.dispatch.body: -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG165]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG174]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]], !dbg [[DBG165]] -// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG165]] +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]], !dbg [[DBG174]] +// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG174]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1, !dbg [[DBG174:![0-9]+]] -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG174]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG174]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[F]], metadata [[META175:![0-9]+]], metadata !DIExpression()), !dbg [[DBG177:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG178:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG178]] -// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX6]], i64 0, i64 1, !dbg [[DBG178]] -// CHECK1-NEXT: store ptr [[ARRAYIDX7]], ptr [[F]], align 8, !dbg [[DBG177]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[G]], metadata [[META179:![0-9]+]], metadata !DIExpression()), !dbg [[DBG180:![0-9]+]] -// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[DBG180]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[H]], metadata [[META181:![0-9]+]], metadata !DIExpression()), !dbg [[DBG182:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 1, !dbg [[DBG183:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX8]], i64 0, i64 1, !dbg [[DBG183]] -// CHECK1-NEXT: store ptr [[ARRAYIDX9]], ptr [[H]], align 8, !dbg [[DBG182]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[D]], metadata [[META184:![0-9]+]], metadata !DIExpression()), !dbg [[DBG185:![0-9]+]] -// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[DBG185]] -// CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG186:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG187:![0-9]+]] -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG188:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG187]] -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX10]], i64 0, i64 [[IDXPROM]], !dbg [[DBG187]] -// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX11]], align 4, !dbg [[DBG189:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG190:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX12]], i64 0, i64 0, !dbg [[DBG190]] -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG191:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP20]] to i64, !dbg [[DBG190]] -// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX13]], i64 0, i64 [[IDXPROM14]], !dbg [[DBG190]] -// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX15]], align 4, !dbg [[DBG192:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG193:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX16]], i64 0, i64 0, !dbg [[DBG193]] -// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG194:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM18:%.*]] = sext i32 [[TMP21]] to i64, !dbg [[DBG193]] -// CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX17]], i64 0, i64 [[IDXPROM18]], !dbg [[DBG193]] -// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[ARRAYIDX19]], align 4, !dbg [[DBG193]] -// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG195:![0-9]+]] -// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG196:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM21:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG195]] -// CHECK1-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX20]], i64 0, i64 [[IDXPROM21]], !dbg [[DBG195]] -// CHECK1-NEXT: store i32 [[TMP22]], ptr [[ARRAYIDX22]], align 4, !dbg [[DBG197:![0-9]+]] -// CHECK1-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP8]], align 1, !dbg [[DBG198:![0-9]+]] -// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP24]] to i1, !dbg [[DBG198]] -// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TOBOOL]] to i32, !dbg [[DBG198]] -// CHECK1-NEXT: store i32 [[CONV]], ptr [[D]], align 4, !dbg [[DBG199:![0-9]+]] -// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG200:![0-9]+]] +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1, !dbg [[DBG183:![0-9]+]] +// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG183]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG183]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[F]], metadata [[META184:![0-9]+]], metadata !DIExpression()), !dbg [[DBG186:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG187:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG187]] +// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX6]], i64 0, i64 1, !dbg [[DBG187]] +// CHECK1-NEXT: store ptr [[ARRAYIDX7]], ptr [[F]], align 8, !dbg [[DBG186]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[G]], metadata [[META188:![0-9]+]], metadata !DIExpression()), !dbg [[DBG189:![0-9]+]] +// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[DBG189]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[H]], metadata [[META190:![0-9]+]], metadata !DIExpression()), !dbg [[DBG191:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 1, !dbg [[DBG192:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX8]], i64 0, i64 1, !dbg [[DBG192]] +// CHECK1-NEXT: store ptr [[ARRAYIDX9]], ptr [[H]], align 8, !dbg [[DBG191]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[D]], metadata [[META193:![0-9]+]], metadata !DIExpression()), !dbg [[DBG194:![0-9]+]] +// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[DBG194]] +// CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG195:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG196:![0-9]+]] +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG197:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG196]] +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX10]], i64 0, i64 [[IDXPROM]], !dbg [[DBG196]] +// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX11]], align 4, !dbg [[DBG198:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG199:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX12]], i64 0, i64 0, !dbg [[DBG199]] +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG200:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP20]] to i64, !dbg [[DBG199]] +// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX13]], i64 0, i64 [[IDXPROM14]], !dbg [[DBG199]] +// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX15]], align 4, !dbg [[DBG201:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG202:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX16]], i64 0, i64 0, !dbg [[DBG202]] +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG203:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM18:%.*]] = sext i32 [[TMP21]] to i64, !dbg [[DBG202]] +// CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX17]], i64 0, i64 [[IDXPROM18]], !dbg [[DBG202]] +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[ARRAYIDX19]], align 4, !dbg [[DBG202]] +// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG204:![0-9]+]] +// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG205:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM21:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG204]] +// CHECK1-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX20]], i64 0, i64 [[IDXPROM21]], !dbg [[DBG204]] +// CHECK1-NEXT: store i32 [[TMP22]], ptr [[ARRAYIDX22]], align 4, !dbg [[DBG206:![0-9]+]] +// CHECK1-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP8]], align 1, !dbg [[DBG207:![0-9]+]] +// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP24]] to i1, !dbg [[DBG207]] +// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TOBOOL]] to i32, !dbg [[DBG207]] +// CHECK1-NEXT: store i32 [[CONV]], ptr [[D]], align 4, !dbg [[DBG208:![0-9]+]] +// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG209:![0-9]+]] // CHECK1: omp.body.continue: -// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG173]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG182]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP25]], 1, !dbg [[DBG165]] -// CHECK1-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG165]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG173]], !llvm.loop [[LOOP201:![0-9]+]] +// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP25]], 1, !dbg [[DBG174]] +// CHECK1-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG174]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG182]], !llvm.loop [[LOOP210:![0-9]+]] // CHECK1: omp.inner.for.end: -// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG173]] +// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG182]] // CHECK1: omp.dispatch.inc: -// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP26]], [[TMP27]], !dbg [[DBG165]] -// CHECK1-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG165]] -// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG168]] -// CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]], !dbg [[DBG165]] -// CHECK1-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG165]] -// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG173]], !llvm.loop [[LOOP203:![0-9]+]] +// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP26]], [[TMP27]], !dbg [[DBG174]] +// CHECK1-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG174]] +// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG177]] +// CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]], !dbg [[DBG174]] +// CHECK1-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG174]] +// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG182]], !llvm.loop [[LOOP212:![0-9]+]] // CHECK1: omp.dispatch.end: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB12:[0-9]+]], i32 [[TMP10]]), !dbg [[DBG202:![0-9]+]] -// CHECK1-NEXT: ret void, !dbg [[DBG204:![0-9]+]] +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB12:[0-9]+]], i32 [[TMP10]]), !dbg [[DBG211:![0-9]+]] +// CHECK1-NEXT: ret void, !dbg [[DBG213:![0-9]+]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG205:![0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR2]] !dbg [[DBG214:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -573,64 +573,64 @@ int main() { // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META206:![0-9]+]], metadata !DIExpression()), !dbg [[DBG207:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META215:![0-9]+]], metadata !DIExpression()), !dbg [[DBG216:![0-9]+]] // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META208:![0-9]+]], metadata !DIExpression()), !dbg [[DBG207]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META217:![0-9]+]], metadata !DIExpression()), !dbg [[DBG216]] // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META209:![0-9]+]], metadata !DIExpression()), !dbg [[DBG207]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META218:![0-9]+]], metadata !DIExpression()), !dbg [[DBG216]] // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META210:![0-9]+]], metadata !DIExpression()), !dbg [[DBG207]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META219:![0-9]+]], metadata !DIExpression()), !dbg [[DBG216]] // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META211:![0-9]+]], metadata !DIExpression()), !dbg [[DBG207]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META220:![0-9]+]], metadata !DIExpression()), !dbg [[DBG216]] // CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META212:![0-9]+]], metadata !DIExpression()), !dbg [[DBG207]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG213:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG213]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG213]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG213]] -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG213]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG213]] -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG213]] -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG213]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG213]] -// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG213]] -// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG213]] -// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG213]] -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], ptr addrspace(1) [[TMP9]], i32 [[TMP6]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]]) #[[ATTR3]], !dbg [[DBG213]] -// CHECK1-NEXT: ret void, !dbg [[DBG213]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META221:![0-9]+]], metadata !DIExpression()), !dbg [[DBG216]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG222:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG222]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG222]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG222]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG222]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG222]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG222]] +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG222]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG222]] +// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG222]] +// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG222]] +// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG222]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___omp_outlined_debug__(ptr [[TMP3]], ptr [[TMP4]], ptr addrspace(1) [[TMP9]], i32 [[TMP6]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]]) #[[ATTR4]], !dbg [[DBG222]] +// CHECK1-NEXT: ret void, !dbg [[DBG222]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27 -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR5]] !dbg [[DBG214:![0-9]+]] { +// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR6]] !dbg [[DBG223:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META217:![0-9]+]], metadata !DIExpression()), !dbg [[DBG218:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META226:![0-9]+]], metadata !DIExpression()), !dbg [[DBG227:![0-9]+]] // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META219:![0-9]+]], metadata !DIExpression()), !dbg [[DBG218]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META228:![0-9]+]], metadata !DIExpression()), !dbg [[DBG227]] // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META220:![0-9]+]], metadata !DIExpression()), !dbg [[DBG218]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META229:![0-9]+]], metadata !DIExpression()), !dbg [[DBG227]] // CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META221:![0-9]+]], metadata !DIExpression()), !dbg [[DBG218]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG222:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG222]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG222]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG222]] -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG222]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG222]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG222]] -// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr [[TMP3]] to ptr addrspace(1), !dbg [[DBG222]] -// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG222]] -// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG222]] -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug__(ptr addrspace(1) [[TMP7]], i32 [[TMP4]], ptr addrspace(1) [[TMP8]], ptr addrspace(1) [[TMP9]]) #[[ATTR3]], !dbg [[DBG222]] -// CHECK1-NEXT: ret void, !dbg [[DBG222]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META230:![0-9]+]], metadata !DIExpression()), !dbg [[DBG227]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG231:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG231]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG231]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG231]] +// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG231]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG231]] +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG231]] +// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr [[TMP3]] to ptr addrspace(1), !dbg [[DBG231]] +// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG231]] +// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG231]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug__(ptr addrspace(1) [[TMP7]], i32 [[TMP4]], ptr addrspace(1) [[TMP8]], ptr addrspace(1) [[TMP9]]) #[[ATTR4]], !dbg [[DBG231]] +// CHECK1-NEXT: ret void, !dbg [[DBG231]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug__ -// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], ptr addrspace(1) noalias noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG223:![0-9]+]] { +// CHECK1-SAME: (ptr addrspace(1) noalias noundef [[C:%.*]], ptr addrspace(1) noalias noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG232:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr addrspace(1), align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr addrspace(1), align 8 @@ -642,51 +642,51 @@ int main() { // CHECK1-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8 // CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META228:![0-9]+]], metadata !DIExpression()), !dbg [[DBG229:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META237:![0-9]+]], metadata !DIExpression()), !dbg [[DBG238:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META230:![0-9]+]], metadata !DIExpression()), !dbg [[DBG231:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META239:![0-9]+]], metadata !DIExpression()), !dbg [[DBG240:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META232:![0-9]+]], metadata !DIExpression()), !dbg [[DBG233:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META241:![0-9]+]], metadata !DIExpression()), !dbg [[DBG242:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META234:![0-9]+]], metadata !DIExpression()), !dbg [[DBG235:![0-9]+]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG236:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG236]] -// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG236]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG236]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[A_ADDR]], align 8, !dbg [[DBG236]] -// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG236]] -// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG236]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG236]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG236]] -// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG236]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG236]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG236]] -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG236]] -// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(1) [[TMP9]] to ptr, !dbg [[DBG236]] -// CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG236]] -// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG236]] -// CHECK1-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_kernel_environment), !dbg [[DBG236]] -// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP12]], -1, !dbg [[DBG236]] -// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG236]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META243:![0-9]+]], metadata !DIExpression()), !dbg [[DBG244:![0-9]+]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG245:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG245]] +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG245]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG245]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[A_ADDR]], align 8, !dbg [[DBG245]] +// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG245]] +// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG245]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG245]] +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG245]] +// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG245]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG245]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG245]] +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG245]] +// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(1) [[TMP9]] to ptr, !dbg [[DBG245]] +// CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG245]] +// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG245]] +// CHECK1-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_kernel_environment), !dbg [[DBG245]] +// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP12]], -1, !dbg [[DBG245]] +// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG245]] // CHECK1: user_code.entry: // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB20:[0-9]+]]) -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG237:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP14]], align 8, !dbg [[DBG237]] -// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG237]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP15]], align 8, !dbg [[DBG237]] -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG237]] -// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP16]], align 8, !dbg [[DBG237]] -// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG237]] -// CHECK1-NEXT: store ptr [[TMP11]], ptr [[TMP17]], align 8, !dbg [[DBG237]] -// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB20]], i32 [[TMP13]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4), !dbg [[DBG237]] -// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG238:![0-9]+]] -// CHECK1-NEXT: ret void, !dbg [[DBG240:![0-9]+]] +// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG246:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP14]], align 8, !dbg [[DBG246]] +// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG246]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP15]], align 8, !dbg [[DBG246]] +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG246]] +// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP16]], align 8, !dbg [[DBG246]] +// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG246]] +// CHECK1-NEXT: store ptr [[TMP11]], ptr [[TMP17]], align 8, !dbg [[DBG246]] +// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB20]], i32 [[TMP13]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4), !dbg [[DBG246]] +// CHECK1-NEXT: call void @__kmpc_target_deinit(), !dbg [[DBG247:![0-9]+]] +// CHECK1-NEXT: ret void, !dbg [[DBG249:![0-9]+]] // CHECK1: worker.exit: -// CHECK1-NEXT: ret void, !dbg [[DBG236]] +// CHECK1-NEXT: ret void, !dbg [[DBG245]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___omp_outlined_debug__ -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], ptr addrspace(1) noalias noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG241:![0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr addrspace(1) noalias noundef [[C:%.*]], ptr addrspace(1) noalias noundef [[A:%.*]], ptr addrspace(1) noalias noundef [[B:%.*]], ptr addrspace(1) noalias noundef [[BB:%.*]]) #[[ATTR2]] !dbg [[DBG250:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -710,148 +710,148 @@ int main() { // CHECK1-NEXT: [[H:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[D:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META244:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META253:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254:![0-9]+]] // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META246:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META255:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254]] // CHECK1-NEXT: store ptr addrspace(1) [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META247:![0-9]+]], metadata !DIExpression()), !dbg [[DBG248:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META256:![0-9]+]], metadata !DIExpression()), !dbg [[DBG257:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META249:![0-9]+]], metadata !DIExpression()), !dbg [[DBG250:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META258:![0-9]+]], metadata !DIExpression()), !dbg [[DBG259:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META251:![0-9]+]], metadata !DIExpression()), !dbg [[DBG252:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META260:![0-9]+]], metadata !DIExpression()), !dbg [[DBG261:![0-9]+]] // CHECK1-NEXT: store ptr addrspace(1) [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META253:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254:![0-9]+]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG255:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG255]] -// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[A_ADDR]], align 8, !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG255]] -// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG255]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(1) [[TMP9]] to ptr, !dbg [[DBG255]] -// CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG255]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_IV]], metadata [[META256:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_LB]], metadata [[META257:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245]] -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG258:![0-9]+]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_UB]], metadata [[META259:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245]] -// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_STRIDE]], metadata [[META260:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245]] -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_IS_LAST]], metadata [[META261:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245]] -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[I]], metadata [[META262:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245]] -// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG255]] -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB17:[0-9]+]], i32 [[TMP13]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG263:![0-9]+]] -// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG255]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META262:![0-9]+]], metadata !DIExpression()), !dbg [[DBG263:![0-9]+]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr addrspace(1), ptr [[C_ADDR]], align 8, !dbg [[DBG264:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[TMP0]] to ptr, !dbg [[DBG264]] +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr [[A_ADDR]], align 8, !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[TMP3]] to ptr, !dbg [[DBG264]] +// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8, !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr [[B_ADDR]], align 8, !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast ptr addrspace(1) [[TMP6]] to ptr, !dbg [[DBG264]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr addrspace(1), ptr [[BB_ADDR]], align 8, !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(1) [[TMP9]] to ptr, !dbg [[DBG264]] +// CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG264]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_IV]], metadata [[META265:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_LB]], metadata [[META266:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254]] +// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG267:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_UB]], metadata [[META268:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254]] +// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_STRIDE]], metadata [[META269:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254]] +// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTOMP_IS_LAST]], metadata [[META270:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254]] +// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[I]], metadata [[META271:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254]] +// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG264]] +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB17:[0-9]+]], i32 [[TMP13]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG272:![0-9]+]] +// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG264]] // CHECK1: omp.dispatch.cond: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP14]], 9, !dbg [[DBG258]] -// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG258]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP14]], 9, !dbg [[DBG267]] +// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG267]] // CHECK1: cond.true: -// CHECK1-NEXT: br label [[COND_END:%.*]], !dbg [[DBG258]] +// CHECK1-NEXT: br label [[COND_END:%.*]], !dbg [[DBG267]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: br label [[COND_END]], !dbg [[DBG258]] +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: br label [[COND_END]], !dbg [[DBG267]] // CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ], !dbg [[DBG258]] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]], !dbg [[DBG255]] -// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG255]] +// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ], !dbg [[DBG267]] +// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]], !dbg [[DBG264]] +// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG264]] // CHECK1: omp.dispatch.body: -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG255]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG264]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]], !dbg [[DBG255]] -// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG255]] +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]], !dbg [[DBG264]] +// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG264]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1, !dbg [[DBG264:![0-9]+]] -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG264]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG264]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[F]], metadata [[META265:![0-9]+]], metadata !DIExpression()), !dbg [[DBG267:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG268:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG268]] -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], i64 0, i64 1, !dbg [[DBG268]] -// CHECK1-NEXT: store ptr [[ARRAYIDX8]], ptr [[F]], align 8, !dbg [[DBG267]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[G]], metadata [[META269:![0-9]+]], metadata !DIExpression()), !dbg [[DBG270:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[G]], align 8, !dbg [[DBG270]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[H]], metadata [[META271:![0-9]+]], metadata !DIExpression()), !dbg [[DBG272:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 1, !dbg [[DBG273:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX9]], i64 0, i64 1, !dbg [[DBG273]] -// CHECK1-NEXT: store ptr [[ARRAYIDX10]], ptr [[H]], align 8, !dbg [[DBG272]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[D]], metadata [[META274:![0-9]+]], metadata !DIExpression()), !dbg [[DBG275:![0-9]+]] -// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[DBG275]] -// CHECK1-NEXT: store i32 5, ptr [[TMP5]], align 4, !dbg [[DBG276:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG277:![0-9]+]] -// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG278:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG277]] -// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM]], !dbg [[DBG277]] -// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX12]], align 4, !dbg [[DBG279:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG280:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG280]] -// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG281:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG280]] -// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG280]] -// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX16]], align 4, !dbg [[DBG282:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG283:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX17]], i64 0, i64 0, !dbg [[DBG283]] -// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG284:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP24]] to i64, !dbg [[DBG283]] -// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG283]] -// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[ARRAYIDX20]], align 4, !dbg [[DBG283]] -// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG285:![0-9]+]] -// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG286:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP26]] to i64, !dbg [[DBG285]] -// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG285]] -// CHECK1-NEXT: store i32 [[TMP25]], ptr [[ARRAYIDX23]], align 4, !dbg [[DBG287:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG288:![0-9]+]] -// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG289:![0-9]+]] -// CHECK1-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP27]] to i64, !dbg [[DBG288]] -// CHECK1-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX24]], i64 0, i64 [[IDXPROM25]], !dbg [[DBG288]] -// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARRAYIDX26]], align 4, !dbg [[DBG288]] -// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP28]], 0, !dbg [[DBG288]] -// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8, !dbg [[DBG290:![0-9]+]] -// CHECK1-NEXT: store i8 [[FROMBOOL]], ptr [[TMP11]], align 1, !dbg [[DBG290]] -// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG291:![0-9]+]] +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1, !dbg [[DBG273:![0-9]+]] +// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG273]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG273]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[F]], metadata [[META274:![0-9]+]], metadata !DIExpression()), !dbg [[DBG276:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG277:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG277]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], i64 0, i64 1, !dbg [[DBG277]] +// CHECK1-NEXT: store ptr [[ARRAYIDX8]], ptr [[F]], align 8, !dbg [[DBG276]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[G]], metadata [[META278:![0-9]+]], metadata !DIExpression()), !dbg [[DBG279:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[G]], align 8, !dbg [[DBG279]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[H]], metadata [[META280:![0-9]+]], metadata !DIExpression()), !dbg [[DBG281:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 1, !dbg [[DBG282:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX9]], i64 0, i64 1, !dbg [[DBG282]] +// CHECK1-NEXT: store ptr [[ARRAYIDX10]], ptr [[H]], align 8, !dbg [[DBG281]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[D]], metadata [[META283:![0-9]+]], metadata !DIExpression()), !dbg [[DBG284:![0-9]+]] +// CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[DBG284]] +// CHECK1-NEXT: store i32 5, ptr [[TMP5]], align 4, !dbg [[DBG285:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG286:![0-9]+]] +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG287:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG286]] +// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM]], !dbg [[DBG286]] +// CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX12]], align 4, !dbg [[DBG288:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG289:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG289]] +// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG290:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG289]] +// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG289]] +// CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX16]], align 4, !dbg [[DBG291:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG292:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX17]], i64 0, i64 0, !dbg [[DBG292]] +// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG293:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP24]] to i64, !dbg [[DBG292]] +// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG292]] +// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[ARRAYIDX20]], align 4, !dbg [[DBG292]] +// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG294:![0-9]+]] +// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG295:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP26]] to i64, !dbg [[DBG294]] +// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG294]] +// CHECK1-NEXT: store i32 [[TMP25]], ptr [[ARRAYIDX23]], align 4, !dbg [[DBG296:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG297:![0-9]+]] +// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG298:![0-9]+]] +// CHECK1-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP27]] to i64, !dbg [[DBG297]] +// CHECK1-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX24]], i64 0, i64 [[IDXPROM25]], !dbg [[DBG297]] +// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARRAYIDX26]], align 4, !dbg [[DBG297]] +// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP28]], 0, !dbg [[DBG297]] +// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8, !dbg [[DBG299:![0-9]+]] +// CHECK1-NEXT: store i8 [[FROMBOOL]], ptr [[TMP11]], align 1, !dbg [[DBG299]] +// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG300:![0-9]+]] // CHECK1: omp.body.continue: -// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG263]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG272]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP29]], 1, !dbg [[DBG255]] -// CHECK1-NEXT: store i32 [[ADD27]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG255]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG263]], !llvm.loop [[LOOP292:![0-9]+]] +// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP29]], 1, !dbg [[DBG264]] +// CHECK1-NEXT: store i32 [[ADD27]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG264]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG272]], !llvm.loop [[LOOP301:![0-9]+]] // CHECK1: omp.inner.for.end: -// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG263]] +// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG272]] // CHECK1: omp.dispatch.inc: -// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]], !dbg [[DBG255]] -// CHECK1-NEXT: store i32 [[ADD28]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG255]] -// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG258]] -// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP32]], [[TMP33]], !dbg [[DBG255]] -// CHECK1-NEXT: store i32 [[ADD29]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG255]] -// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG263]], !llvm.loop [[LOOP294:![0-9]+]] +// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]], !dbg [[DBG264]] +// CHECK1-NEXT: store i32 [[ADD28]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG264]] +// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG267]] +// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP32]], [[TMP33]], !dbg [[DBG264]] +// CHECK1-NEXT: store i32 [[ADD29]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG264]] +// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG272]], !llvm.loop [[LOOP303:![0-9]+]] // CHECK1: omp.dispatch.end: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB19:[0-9]+]], i32 [[TMP13]]), !dbg [[DBG293:![0-9]+]] -// CHECK1-NEXT: ret void, !dbg [[DBG295:![0-9]+]] +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB19:[0-9]+]], i32 [[TMP13]]), !dbg [[DBG302:![0-9]+]] +// CHECK1-NEXT: ret void, !dbg [[DBG304:![0-9]+]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG296:![0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR2]] !dbg [[DBG305:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -860,62 +860,62 @@ int main() { // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META299:![0-9]+]], metadata !DIExpression()), !dbg [[DBG300:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META308:![0-9]+]], metadata !DIExpression()), !dbg [[DBG309:![0-9]+]] // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META301:![0-9]+]], metadata !DIExpression()), !dbg [[DBG300]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META310:![0-9]+]], metadata !DIExpression()), !dbg [[DBG309]] // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META302:![0-9]+]], metadata !DIExpression()), !dbg [[DBG300]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META311:![0-9]+]], metadata !DIExpression()), !dbg [[DBG309]] // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META303:![0-9]+]], metadata !DIExpression()), !dbg [[DBG300]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META312:![0-9]+]], metadata !DIExpression()), !dbg [[DBG309]] // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META304:![0-9]+]], metadata !DIExpression()), !dbg [[DBG300]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META313:![0-9]+]], metadata !DIExpression()), !dbg [[DBG309]] // CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META305:![0-9]+]], metadata !DIExpression()), !dbg [[DBG300]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG306:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG306]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG306]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG306]] -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG306]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG306]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG306]] -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG306]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG306]] -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG306]] -// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG306]] -// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG306]] -// CHECK1-NEXT: [[TMP12:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG306]] -// CHECK1-NEXT: [[TMP13:%.*]] = addrspacecast ptr [[TMP9]] to ptr addrspace(1), !dbg [[DBG306]] -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___omp_outlined_debug__(ptr [[TMP4]], ptr [[TMP5]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]], ptr addrspace(1) [[TMP12]], ptr addrspace(1) [[TMP13]]) #[[ATTR3]], !dbg [[DBG306]] -// CHECK1-NEXT: ret void, !dbg [[DBG306]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META314:![0-9]+]], metadata !DIExpression()), !dbg [[DBG309]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG315:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG315]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG315]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG315]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG315]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG315]] +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG315]] +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG315]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG315]] +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG315]] +// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG315]] +// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG315]] +// CHECK1-NEXT: [[TMP12:%.*]] = addrspacecast ptr [[TMP8]] to ptr addrspace(1), !dbg [[DBG315]] +// CHECK1-NEXT: [[TMP13:%.*]] = addrspacecast ptr [[TMP9]] to ptr addrspace(1), !dbg [[DBG315]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___omp_outlined_debug__(ptr [[TMP4]], ptr [[TMP5]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]], ptr addrspace(1) [[TMP12]], ptr addrspace(1) [[TMP13]]) #[[ATTR4]], !dbg [[DBG315]] +// CHECK1-NEXT: ret void, !dbg [[DBG315]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41 -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR5]] !dbg [[DBG307:![0-9]+]] { +// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR6]] !dbg [[DBG316:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META310:![0-9]+]], metadata !DIExpression()), !dbg [[DBG311:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[C_ADDR]], metadata [[META319:![0-9]+]], metadata !DIExpression()), !dbg [[DBG320:![0-9]+]] // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META312:![0-9]+]], metadata !DIExpression()), !dbg [[DBG311]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META321:![0-9]+]], metadata !DIExpression()), !dbg [[DBG320]] // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META313:![0-9]+]], metadata !DIExpression()), !dbg [[DBG311]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B_ADDR]], metadata [[META322:![0-9]+]], metadata !DIExpression()), !dbg [[DBG320]] // CHECK1-NEXT: store ptr [[BB]], ptr [[BB_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META314:![0-9]+]], metadata !DIExpression()), !dbg [[DBG311]] -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG315:![0-9]+]] -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG315]] -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG315]] -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG315]] -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG315]] -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG315]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG315]] -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG315]] -// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[TMP4]] to ptr addrspace(1), !dbg [[DBG315]] -// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG315]] -// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG315]] -// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG315]] -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug__(ptr addrspace(1) [[TMP8]], ptr addrspace(1) [[TMP9]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]]) #[[ATTR3]], !dbg [[DBG315]] -// CHECK1-NEXT: ret void, !dbg [[DBG315]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[BB_ADDR]], metadata [[META323:![0-9]+]], metadata !DIExpression()), !dbg [[DBG320]] +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG324:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG324]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG324]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG324]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG324]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG324]] +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG324]] +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[BB_ADDR]], align 8, !dbg [[DBG324]] +// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[TMP4]] to ptr addrspace(1), !dbg [[DBG324]] +// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[TMP5]] to ptr addrspace(1), !dbg [[DBG324]] +// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[TMP6]] to ptr addrspace(1), !dbg [[DBG324]] +// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast ptr [[TMP7]] to ptr addrspace(1), !dbg [[DBG324]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug__(ptr addrspace(1) [[TMP8]], ptr addrspace(1) [[TMP9]], ptr addrspace(1) [[TMP10]], ptr addrspace(1) [[TMP11]]) #[[ATTR4]], !dbg [[DBG324]] +// CHECK1-NEXT: ret void, !dbg [[DBG324]] // diff --git a/clang/test/OpenMP/target_parallel_generic_loop_depend_codegen.cpp b/clang/test/OpenMP/target_parallel_generic_loop_depend_codegen.cpp index feaa33c198392..6403240091b48 100644 --- a/clang/test/OpenMP/target_parallel_generic_loop_depend_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_generic_loop_depend_codegen.cpp @@ -1,37 +1,37 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s // expected-no-diagnostics #ifndef HEADER diff --git a/clang/test/OpenMP/target_parallel_map_messages.cpp b/clang/test/OpenMP/target_parallel_map_messages.cpp index 683c26b693d07..fa0ee01265b64 100644 --- a/clang/test/OpenMP/target_parallel_map_messages.cpp +++ b/clang/test/OpenMP/target_parallel_map_messages.cpp @@ -1,10 +1,12 @@ // RUN: %clang_cc1 -verify=expected,lt50,lt51 -fopenmp -fno-openmp-extensions -fopenmp-version=45 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,lt51 -fopenmp -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,ge51 -fopenmp -fno-openmp-extensions -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized +// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp52 -fopenmp -fno-openmp-extensions -fopenmp-version=52 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,lt50,lt51 -fopenmp-simd -fno-openmp-extensions -fopenmp-version=45 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,lt51 -fopenmp-simd -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,ge51 -fopenmp-simd -fno-openmp-extensions -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized +// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp52 -fopenmp-simd -fno-openmp-extensions -fopenmp-version=52 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized void foo() { } @@ -303,6 +305,8 @@ int main(int argc, char **argv) { foo(); #pragma omp target parallel map(always, tofrom: always, tofrom, x) foo(); +#pragma omp target parallel map(always tofrom: x) // omp52-error {{missing ',' after map type modifier}} + foo(); #pragma omp target parallel map(tofrom j) // expected-error {{expected ',' or ')' in 'map' clause}} foo(); #pragma omp target parallel map(delete: j) // expected-error {{map type 'delete' is not allowed for '#pragma omp target parallel'}} diff --git a/clang/test/OpenMP/target_private_codegen.cpp b/clang/test/OpenMP/target_private_codegen.cpp index 61d66334037fe..4173313073d19 100644 --- a/clang/test/OpenMP/target_private_codegen.cpp +++ b/clang/test/OpenMP/target_private_codegen.cpp @@ -1,22 +1,22 @@ // Only test codegen on target side, as private clause does not require any action on the host side // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/target_reduction_codegen.cpp b/clang/test/OpenMP/target_reduction_codegen.cpp index a28990929ba2c..8cf22d8229c84 100644 --- a/clang/test/OpenMP/target_reduction_codegen.cpp +++ b/clang/test/OpenMP/target_reduction_codegen.cpp @@ -1,22 +1,22 @@ // Only test codegen on target side, as private clause does not require any action on the host side // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/target_simd_ast_print.cpp b/clang/test/OpenMP/target_simd_ast_print.cpp index 62f9e380adbd3..ec9de55392b41 100644 --- a/clang/test/OpenMP/target_simd_ast_print.cpp +++ b/clang/test/OpenMP/target_simd_ast_print.cpp @@ -7,6 +7,9 @@ // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=51 -ast-print %s -Wno-openmp-mapping -DOMP51 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP51 // RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -x c++ -std=c++11 -emit-pch -o %t %s -Wno-openmp-mapping -DOMP51 // RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -Wno-openmp-mapping -DOMP51 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP51 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=52 -ast-print %s -Wno-openmp-mapping -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=52 -x c++ -std=c++11 -emit-pch -o %t %s -Wno-openmp-mapping -DOMP52 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=52 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -Wno-openmp-mapping -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -ast-print %s -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK --check-prefix=OMP45 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -emit-pch -o %t %s -Wno-openmp-mapping @@ -18,6 +21,10 @@ // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=51 -x c++ -std=c++11 -emit-pch -o %t %s -Wno-openmp-mapping -DOMP51 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=51 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -Wno-openmp-mapping -DOMP51 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP51 // expected-no-diagnostics +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=52 -ast-print %s -Wno-openmp-mapping -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=52 -x c++ -std=c++11 -emit-pch -o %t %s -Wno-openmp-mapping -DOMP52 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=52 -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print -Wno-openmp-mapping -DOMP52 | FileCheck %s --check-prefix=CHECK --check-prefix=OMP52 +// expected-no-diagnostics #ifndef HEADER #define HEADER @@ -141,6 +148,7 @@ T tmain(T argc, T *argv) { // OMP45: #pragma omp target simd if(target: argc > 0) // OMP50: #pragma omp target simd if(target: argc > 0) if(simd: argc) allocate(omp_default_mem_alloc: f) private(f) uses_allocators(omp_default_mem_alloc) // OMP51: #pragma omp target simd if(target: argc > 0) + // OMP52: #pragma omp target simd if(target: argc > 0) // CHECK-NEXT: for (T i = 0; i < 2; ++i) { // CHECK-NEXT: } @@ -238,11 +246,15 @@ int main(int argc, char **argv) { // CHECK-NEXT: for (int i = 0; i < 2; ++i) // CHECK-NEXT: a = 2; +#ifdef OMP52 +#pragma omp target simd private(argc, b), firstprivate(argv, c), lastprivate(d, f) collapse(2) if (target: argc) reduction(+ : h) linear(a: step(-5)) +#else #pragma omp target simd private(argc, b), firstprivate(argv, c), lastprivate(d, f) collapse(2) if (target: argc) reduction(+ : h) linear(a:-5) +#endif for (int i = 0; i < 10; ++i) for (int j = 0; j < 10; ++j) foo(); - // CHECK: #pragma omp target simd private(argc,b) firstprivate(argv,c) lastprivate(d,f) collapse(2) if(target: argc) reduction(+: h) linear(a: -5) + // CHECK: #pragma omp target simd private(argc,b) firstprivate(argv,c) lastprivate(d,f) collapse(2) if(target: argc) reduction(+: h) linear(a: step(-5)) // CHECK-NEXT: for (int i = 0; i < 10; ++i) // CHECK-NEXT: for (int j = 0; j < 10; ++j) // CHECK-NEXT: foo(); @@ -259,7 +271,7 @@ int main(int argc, char **argv) { // CHECK-NEXT: for (int i = 0; i < 2; ++i) { // CHECK-NEXT: } -#ifdef OMP51 +#if defined(OMP51) || defined(OMP52) #pragma omp target simd if (target:argc > 0) if(simd:argc) nontemporal(argc, c, d) lastprivate(conditional: d, f) order(reproducible:concurrent) #elif OMP5 #pragma omp target simd if (target:argc > 0) if(simd:argc) nontemporal(argc, c, d) lastprivate(conditional: d, f) order(concurrent) @@ -270,6 +282,7 @@ int main(int argc, char **argv) { // OMP45: #pragma omp target simd if(target: argc > 0) // OMP50: #pragma omp target simd if(target: argc > 0) if(simd: argc) nontemporal(argc,c,d) lastprivate(conditional: d,f) order(concurrent) // OMP51: #pragma omp target simd if(target: argc > 0) if(simd: argc) nontemporal(argc,c,d) lastprivate(conditional: d,f) order(reproducible: concurrent) + // OMP52: #pragma omp target simd if(target: argc > 0) if(simd: argc) nontemporal(argc,c,d) lastprivate(conditional: d,f) order(reproducible: concurrent) // CHECK-NEXT: for (int i = 0; i < 2; ++i) { // CHECK-NEXT: } diff --git a/clang/test/OpenMP/target_simd_codegen.cpp b/clang/test/OpenMP/target_simd_codegen.cpp index ce8310b279a98..9dd8b07010f13 100644 --- a/clang/test/OpenMP/target_simd_codegen.cpp +++ b/clang/test/OpenMP/target_simd_codegen.cpp @@ -1,65 +1,65 @@ // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP45 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP45 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP45 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP45 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP45 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP45 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP45 -// RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP51 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP45 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP51 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP51 -// RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP51 +// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP51 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP51 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP51 +// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP51 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 --check-prefix TOMP45 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 --check-prefix TOMP45 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 --check-prefix TOMP45 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 --check-prefix TOMP45 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 --check-prefix TOMP45 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 --check-prefix TOMP45 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 --check-prefix TOMP45 -// RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 --check-prefix TOMP51 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 --check-prefix TOMP45 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 --check-prefix TOMP51 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 --check-prefix TOMP51 -// RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 --check-prefix TOMP51 +// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 --check-prefix TOMP51 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 --check-prefix TOMP51 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 --check-prefix TOMP51 +// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 --check-prefix TOMP51 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s // SIMD-ONLY1-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/target_simd_depend_codegen.cpp b/clang/test/OpenMP/target_simd_depend_codegen.cpp index c02e430bb328f..e7ce853d7eb0c 100644 --- a/clang/test/OpenMP/target_simd_depend_codegen.cpp +++ b/clang/test/OpenMP/target_simd_depend_codegen.cpp @@ -1,37 +1,37 @@ // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s // SIMD-ONLY1-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/target_simd_linear_messages.cpp b/clang/test/OpenMP/target_simd_linear_messages.cpp index 18dde74dbbaa1..d39d626ea0194 100644 --- a/clang/test/OpenMP/target_simd_linear_messages.cpp +++ b/clang/test/OpenMP/target_simd_linear_messages.cpp @@ -1,6 +1,8 @@ // RUN: %clang_cc1 -verify -fopenmp %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp -fopenmp-version=52 -DOMP52 %s -Wuninitialized // RUN: %clang_cc1 -verify -fopenmp-simd %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp-simd -fopenmp-version=52 -DOMP52 %s -Wuninitialized #pragma omp requires dynamic_allocators typedef void **omp_allocator_handle_t; @@ -15,8 +17,8 @@ extern const omp_allocator_handle_t omp_pteam_mem_alloc; extern const omp_allocator_handle_t omp_thread_mem_alloc; void xxx(int argc) { - int i, lin, step; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step' to silence this warning}} -#pragma omp target simd linear(i, lin : step) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step' is uninitialized when used here}} + int i, lin, step_sz; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step_sz' to silence this warning}} +#pragma omp target simd linear(i, lin : step_sz) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step_sz' is uninitialized when used here}} for (i = 0; i < 10; ++i) ; } @@ -271,16 +273,28 @@ int main(int argc, char **argv) { #pragma omp target simd linear(i) for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 +#pragma omp target simd linear(i : uval, step(4)) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} +#else #pragma omp target simd linear(i : 4) +#endif for (int k = 0; k < argc; ++k) { ++k; i += 4; } } +#ifdef OMP52 +#pragma omp target simd linear(j: step() //omp52-error 2 {{expected expression}} omp52-error{{expected ')'}} omp52-note{{to match this '('}} +#else #pragma omp target simd linear(j) +#endif for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 +#pragma omp target simd linear(i: step(1), step(2)) // omp52-error {{multiple 'step size' found in linear clause}} +#else #pragma omp target simd linear(i) +#endif for (int k = 0; k < argc; ++k) ++k; diff --git a/clang/test/OpenMP/target_simd_map_messages.cpp b/clang/test/OpenMP/target_simd_map_messages.cpp index b1a0bb86abf10..4e0f569b1f1c4 100644 --- a/clang/test/OpenMP/target_simd_map_messages.cpp +++ b/clang/test/OpenMP/target_simd_map_messages.cpp @@ -1,10 +1,12 @@ // RUN: %clang_cc1 -verify=expected,lt50,lt51 -fopenmp -fopenmp-version=45 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,lt51 -fopenmp -fopenmp-version=50 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,ge51 -fopenmp %s -Wno-openmp-mapping -Wuninitialized +// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp52 -fopenmp -fopenmp-version=52 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,lt50,lt51 -fopenmp-simd -fopenmp-version=45 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,lt51 -fopenmp-simd -fopenmp-version=50 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,ge51 -fopenmp-simd %s -Wno-openmp-mapping -Wuninitialized +// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp52 -fopenmp-simd -fopenmp-version=52 %s -Wno-openmp-mapping -Wuninitialized void foo() { } @@ -300,6 +302,8 @@ int main(int argc, char **argv) { for (i = 0; i < argc; ++i) foo(); #pragma omp target simd map(always, tofrom: always, tofrom, x) for (i = 0; i < argc; ++i) foo(); +#pragma omp target simd map(always tofrom: x) // omp52-error {{missing ',' after map type modifier}} + for (i = 0; i < argc; ++i) foo(); #pragma omp target simd map(tofrom j) // expected-error {{expected ',' or ')' in 'map' clause}} for (i = 0; i < argc; ++i) foo(); #pragma omp target simd map(delete: j) // expected-error {{map type 'delete' is not allowed for '#pragma omp target simd'}} diff --git a/clang/test/OpenMP/target_teams_codegen.cpp b/clang/test/OpenMP/target_teams_codegen.cpp index 3185d90b5ef14..9ee1f74e8fdc4 100644 --- a/clang/test/OpenMP/target_teams_codegen.cpp +++ b/clang/test/OpenMP/target_teams_codegen.cpp @@ -1,70 +1,70 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER diff --git a/clang/test/OpenMP/target_teams_depend_codegen.cpp b/clang/test/OpenMP/target_teams_depend_codegen.cpp index 8b4158681a6b5..844dc83857837 100644 --- a/clang/test/OpenMP/target_teams_depend_codegen.cpp +++ b/clang/test/OpenMP/target_teams_depend_codegen.cpp @@ -1,37 +1,37 @@ // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s // SIMD-ONLY1-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/target_teams_distribute_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_codegen.cpp index 1ef51aa9ab696..a7358090164ed 100644 --- a/clang/test/OpenMP/target_teams_distribute_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_codegen.cpp @@ -1,71 +1,71 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER diff --git a/clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp index 6be515e14d96e..298568f8b75db 100644 --- a/clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp @@ -4,19 +4,19 @@ #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -46,19 +46,19 @@ int teams_template_struct(void) { #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template diff --git a/clang/test/OpenMP/target_teams_distribute_depend_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_depend_codegen.cpp index a0c71eac85b8f..108a6811dbc1c 100644 --- a/clang/test/OpenMP/target_teams_distribute_depend_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_depend_codegen.cpp @@ -1,37 +1,37 @@ // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s // SIMD-ONLY1-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp index 821d3e8668c1f..f4b424eb25c7e 100644 --- a/clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp @@ -4,19 +4,19 @@ #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -55,19 +55,19 @@ int teams_template_struct(void) { #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template diff --git a/clang/test/OpenMP/target_teams_distribute_map_messages.cpp b/clang/test/OpenMP/target_teams_distribute_map_messages.cpp index 0edff19801f15..8fcac5a7b6028 100644 --- a/clang/test/OpenMP/target_teams_distribute_map_messages.cpp +++ b/clang/test/OpenMP/target_teams_distribute_map_messages.cpp @@ -1,10 +1,12 @@ // RUN: %clang_cc1 -verify=expected,lt50,lt51 -fopenmp -fopenmp-version=45 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,lt51 -fopenmp -fopenmp-version=50 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,ge51 -fopenmp -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized +// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp52 -fopenmp -fopenmp-version=52 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,lt50,lt51 -fopenmp-simd -fopenmp-version=45 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,lt51 -fopenmp-simd -fopenmp-version=50 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,ge51 -fopenmp-simd -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized +// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp52 -fopenmp-simd -fopenmp-version=52 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized void foo() { } @@ -307,6 +309,8 @@ int main(int argc, char **argv) { for (i = 0; i < argc; ++i) foo(); #pragma omp target teams distribute map(always, tofrom: always, tofrom, x) for (i = 0; i < argc; ++i) foo(); +#pragma omp target teams distribute map(always close tofrom: x) // omp52-error 2 {{missing ',' after map type modifier}} + for (i = 0; i < argc; ++i) foo(); #pragma omp target teams distribute map(tofrom j) // expected-error {{expected ',' or ')' in 'map' clause}} for (i = 0; i < argc; ++i) foo(); #pragma omp target teams distribute map(delete: j) // expected-error {{map type 'delete' is not allowed for '#pragma omp target teams distribute'}} diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp index 709b5ea996991..1eeab3cbf0688 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp @@ -4,19 +4,19 @@ #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -47,19 +47,19 @@ int teams_template_struct(void) { #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_depend_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_depend_codegen.cpp index eb93cd3c5c555..f6e201e2fc802 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_depend_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_depend_codegen.cpp @@ -1,37 +1,37 @@ // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s // SIMD-ONLY1-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp index 19998d295bfbb..019869514a029 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp @@ -4,19 +4,19 @@ #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -59,19 +59,19 @@ int teams_template_struct(void) { #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_map_messages.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_map_messages.cpp index 336ceeb0c79c5..66508215a1569 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_map_messages.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_map_messages.cpp @@ -1,6 +1,7 @@ // RUN: %clang_cc1 -verify=expected,lt50,lt51 -fopenmp -fno-openmp-extensions -fopenmp-version=45 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,lt51 -fopenmp -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,ge51 -fopenmp -fno-openmp-extensions -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized +// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp52 -fopenmp -fno-openmp-extensions -fopenmp-version=52 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,lt50,lt51 -fopenmp-simd -fno-openmp-extensions -fopenmp-version=45 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized @@ -309,6 +310,8 @@ int main(int argc, char **argv) { for (i = 0; i < argc; ++i) foo(); #pragma omp target teams distribute parallel for map(always, tofrom: always, tofrom, x) for (i = 0; i < argc; ++i) foo(); +#pragma omp target teams distribute parallel for map(always close tofrom: x) // omp52-error 2 {{missing ',' after map type modifier}} + for (i = 0; i < argc; ++i) foo(); #pragma omp target teams distribute parallel for map(tofrom j) // expected-error {{expected ',' or ')' in 'map' clause}} for (i = 0; i < argc; ++i) foo(); #pragma omp target teams distribute parallel for map(delete: j) // expected-error {{map type 'delete' is not allowed for '#pragma omp target teams distribute parallel for'}} diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp index 2a8b885b053a6..d6f9b412bebe8 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp @@ -4,26 +4,26 @@ #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 @@ -83,26 +83,26 @@ int teams_template_struct(void) { #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp index d5fbd0f2f0e28..44976df6849b1 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp @@ -4,19 +4,19 @@ #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 #ifdef CK1 template @@ -47,19 +47,19 @@ int teams_template_struct(void) { #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 #ifdef CK2 template diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_depend_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_depend_codegen.cpp index 330be35b76236..bea0ffce42d1c 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_depend_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_depend_codegen.cpp @@ -1,37 +1,37 @@ // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s // SIMD-ONLY1-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp index 03d5486308572..0d1374ddb645f 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp @@ -4,19 +4,19 @@ #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 #ifdef CK1 template @@ -59,19 +59,19 @@ int teams_template_struct(void) { #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 #ifdef CK2 template diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_linear_messages.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_linear_messages.cpp index 371a7ef4925af..7b76fa11d9592 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_linear_messages.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_linear_messages.cpp @@ -1,6 +1,8 @@ // RUN: %clang_cc1 -verify -fopenmp %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp -fopenmp-version=52 -DOMP52 %s -Wuninitialized // RUN: %clang_cc1 -verify -fopenmp-simd %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp-simd -fopenmp-version=52 -DOMP52 %s -Wuninitialized typedef void **omp_allocator_handle_t; extern const omp_allocator_handle_t omp_default_mem_alloc; @@ -13,8 +15,8 @@ extern const omp_allocator_handle_t omp_pteam_mem_alloc; extern const omp_allocator_handle_t omp_thread_mem_alloc; void xxx(int argc) { - int i, step; // expected-note {{initialize the variable 'step' to silence this warning}} -#pragma omp target teams distribute parallel for simd linear(i : step) // expected-warning {{variable 'step' is uninitialized when used here}} + int i, step_sz; // expected-note {{initialize the variable 'step_sz' to silence this warning}} +#pragma omp target teams distribute parallel for simd linear(i : step_sz) // expected-warning {{variable 'step_sz' is uninitialized when used here}} for (i = 0; i < 10; ++i) ; } diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_map_messages.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_map_messages.cpp index 7ded33ea3919b..1d162d45072c6 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_map_messages.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_map_messages.cpp @@ -1,10 +1,12 @@ // RUN: %clang_cc1 -verify=expected,lt50,lt51 -fopenmp -fno-openmp-extensions -fopenmp-version=45 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,lt51 -fopenmp -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,ge51 -fopenmp -fno-openmp-extensions -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized +// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp52 -fopenmp -fno-openmp-extensions -fopenmp-version=52 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,lt50,lt51 -fopenmp-simd -fno-openmp-extensions -fopenmp-version=45 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,lt51 -fopenmp-simd -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,ge51 -fopenmp-simd -fno-openmp-extensions -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized +// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp52 -fopenmp-simd -fno-openmp-extensions -fopenmp-version=52 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized void foo() { } @@ -180,6 +182,8 @@ T tmain(T argc) { #pragma omp target teams distribute parallel for simd map(always, tofrom: x) for (i = 0; i < argc; ++i) foo(); +#pragma omp target teams distribute parallel for simd map(always tofrom: x) // omp52-error {{missing ',' after map type modifier}} + for (i = 0; i < argc; ++i) foo(); #pragma omp target teams distribute parallel for simd map(always: x) // expected-error {{missing map type}} for (i = 0; i < argc; ++i) foo(); // ge51-error@+3 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present'}} diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp index e65545ceb015a..aba9968fac967 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp @@ -4,26 +4,26 @@ #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 #ifdef CK1 @@ -83,26 +83,26 @@ int teams_template_struct(void) { #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK21 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK23 #ifdef CK2 template diff --git a/clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp index b208f65460a6f..9735f69119174 100644 --- a/clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp @@ -1,65 +1,65 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK17 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK19 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 -// RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK21 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK21 -// RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK23 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK23 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 // expected-no-diagnostics #ifndef HEADER @@ -411,7 +411,7 @@ int bar(int n){ // CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: store i32 [[TMP43]], ptr [[A_CASTED]], align 4 // CHECK1-NEXT: [[TMP44:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP44]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP44]]) #[[ATTR3:[0-9]+]] // CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[AA]], align 2 // CHECK1-NEXT: store i16 [[TMP45]], ptr [[AA_CASTED4]], align 2 // CHECK1-NEXT: [[TMP46:%.*]] = load i64, ptr [[AA_CASTED4]], align 8 @@ -453,7 +453,7 @@ int bar(int n){ // CHECK1-NEXT: [[TMP66:%.*]] = icmp ne i32 [[TMP65]], 0 // CHECK1-NEXT: br i1 [[TMP66]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP46]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP46]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: [[TMP67:%.*]] = load i32, ptr [[A]], align 4 @@ -510,12 +510,12 @@ int bar(int n){ // CHECK1-NEXT: [[TMP94:%.*]] = icmp ne i32 [[TMP93]], 0 // CHECK1-NEXT: br i1 [[TMP94]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] // CHECK1: omp_offload.failed15: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT16]] // CHECK1: omp_offload.cont16: // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1: omp_if.else: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: [[TMP95:%.*]] = load i32, ptr [[A]], align 4 @@ -620,12 +620,12 @@ int bar(int n){ // CHECK1-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0 // CHECK1-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]] // CHECK1: omp_offload.failed25: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP96]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP96]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT26]] // CHECK1: omp_offload.cont26: // CHECK1-NEXT: br label [[OMP_IF_END28:%.*]] // CHECK1: omp_if.else27: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP96]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP96]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_IF_END28]] // CHECK1: omp_if.end28: // CHECK1-NEXT: [[TMP148:%.*]] = load i32, ptr [[A]], align 4 @@ -656,7 +656,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -693,23 +693,23 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]] -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK1-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -725,7 +725,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 @@ -754,7 +754,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 @@ -781,74 +781,74 @@ int bar(int n){ // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META31:![0-9]+]]) -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !33 -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !33 -// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !33 -// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !33 -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !33 -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !33 -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !33 -// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !33 -// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !33 -// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] -// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !33 -// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !33 -// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !33 -// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !33 +// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26 +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !26 +// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !26 +// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !26 +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !26 +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !26 +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !26 +// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !26 +// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !26 +// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !26 +// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !26 +// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !26 +// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !26 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4 // CHECK1-NEXT: [[TMP19:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP18]], 0 -// CHECK1-NEXT: store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !33 +// CHECK1-NEXT: store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !26 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1 -// CHECK1-NEXT: store i32 3, ptr [[TMP20]], align 4, !noalias !33 +// CHECK1-NEXT: store i32 3, ptr [[TMP20]], align 4, !noalias !26 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2 -// CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP21]], align 8, !noalias !33 +// CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP21]], align 8, !noalias !26 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3 -// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP22]], align 8, !noalias !33 +// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP22]], align 8, !noalias !26 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4 -// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP23]], align 8, !noalias !33 +// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP23]], align 8, !noalias !26 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5 -// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP24]], align 8, !noalias !33 +// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP24]], align 8, !noalias !26 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6 -// CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8, !noalias !33 +// CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8, !noalias !26 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7 -// CHECK1-NEXT: store ptr null, ptr [[TMP26]], align 8, !noalias !33 +// CHECK1-NEXT: store ptr null, ptr [[TMP26]], align 8, !noalias !26 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8 -// CHECK1-NEXT: store i64 10, ptr [[TMP27]], align 8, !noalias !33 +// CHECK1-NEXT: store i64 10, ptr [[TMP27]], align 8, !noalias !26 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9 -// CHECK1-NEXT: store i64 1, ptr [[TMP28]], align 8, !noalias !33 +// CHECK1-NEXT: store i64 1, ptr [[TMP28]], align 8, !noalias !26 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10 -// CHECK1-NEXT: store [3 x i32] [[TMP19]], ptr [[TMP29]], align 4, !noalias !33 +// CHECK1-NEXT: store [3 x i32] [[TMP19]], ptr [[TMP29]], align 4, !noalias !26 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11 -// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP30]], align 4, !noalias !33 +// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP30]], align 4, !noalias !26 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12 -// CHECK1-NEXT: store i32 0, ptr [[TMP31]], align 4, !noalias !33 +// CHECK1-NEXT: store i32 0, ptr [[TMP31]], align 4, !noalias !26 // CHECK1-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 [[TMP18]], i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, ptr [[KERNEL_ARGS_I]]) // CHECK1-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 // CHECK1-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK1: omp_offload.failed.i: // CHECK1-NEXT: [[TMP34:%.*]] = load i16, ptr [[TMP12]], align 2 -// CHECK1-NEXT: store i16 [[TMP34]], ptr [[AA_CASTED_I]], align 2, !noalias !33 -// CHECK1-NEXT: [[TMP35:%.*]] = load i64, ptr [[AA_CASTED_I]], align 8, !noalias !33 +// CHECK1-NEXT: store i16 [[TMP34]], ptr [[AA_CASTED_I]], align 2, !noalias !26 +// CHECK1-NEXT: [[TMP35:%.*]] = load i64, ptr [[AA_CASTED_I]], align 8, !noalias !26 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP16]], align 4 -// CHECK1-NEXT: store i32 [[TMP36]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !33 -// CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !33 +// CHECK1-NEXT: store i32 [[TMP36]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !26 +// CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !26 // CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[TMP17]], align 4 -// CHECK1-NEXT: store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !33 -// CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 8, !noalias !33 -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i64 [[TMP35]], i64 [[TMP37]], i64 [[TMP39]]) #[[ATTR4]] +// CHECK1-NEXT: store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !26 +// CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 8, !noalias !26 +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i64 [[TMP35]], i64 [[TMP37]], i64 [[TMP39]]) #[[ATTR3]] // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] // CHECK1: .omp_outlined..exit: // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 -// CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -861,7 +861,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -917,7 +917,7 @@ int bar(int n){ // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -946,7 +946,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -983,28 +983,28 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]] -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29:![0-9]+]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP29]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP36]] -// CHECK1-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP36]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 // CHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK1-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP36]] +// CHECK1-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]] // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1039,7 +1039,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1078,31 +1078,31 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39:![0-9]+]] -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP32]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]] -// CHECK1-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP39]] +// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]] // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP39]] +// CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1155,7 +1155,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1218,59 +1218,59 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42:![0-9]+]] -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35:![0-9]+]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP42]] -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK1-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 -// CHECK1-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double // CHECK1-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00 // CHECK1-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float -// CHECK1-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3 -// CHECK1-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double // CHECK1-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 // CHECK1-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK1-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 // CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i64 0, i64 2 -// CHECK1-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00 -// CHECK1-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]] // CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP20]] // CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i64 3 -// CHECK1-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00 -// CHECK1-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1 -// CHECK1-NEXT: store i64 [[ADD19]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: store i64 [[ADD19]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i32 // CHECK1-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1 // CHECK1-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8 -// CHECK1-NEXT: store i8 [[CONV22]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: store i8 [[CONV22]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK1-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1421,12 +1421,12 @@ int bar(int n){ // CHECK1-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 // CHECK1-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1: omp_if.else: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]] @@ -1558,12 +1558,12 @@ int bar(int n){ // CHECK1-NEXT: [[TMP46:%.*]] = icmp ne i32 [[TMP45]], 0 // CHECK1-NEXT: br i1 [[TMP46]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], ptr [[B]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], ptr [[B]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1: omp_if.else: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], ptr [[B]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], ptr [[B]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: [[TMP47:%.*]] = load i32, ptr [[A]], align 4 @@ -1647,12 +1647,12 @@ int bar(int n){ // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1: omp_if.else: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4 @@ -1685,7 +1685,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1734,37 +1734,37 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]] -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38:![0-9]+]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]] -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double // CHECK1-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 -// CHECK1-NEXT: store double [[ADD4]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP45]] +// CHECK1-NEXT: store double [[ADD4]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP38]] // CHECK1-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP45]] +// CHECK1-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP38]] // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK1-NEXT: store double [[INC]], ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP45]] +// CHECK1-NEXT: store double [[INC]], ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP38]] // CHECK1-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 // CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]] // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 -// CHECK1-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP45]] +// CHECK1-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP38]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK1-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1814,7 +1814,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1886,42 +1886,42 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48:![0-9]+]] -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP48]] +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41:![0-9]+]] +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP41]] // CHECK1-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 1 // CHECK1-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]] // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP48]] -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48]] +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP41]] +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41]] // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK1-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]] -// CHECK1-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP48]] -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP48]] +// CHECK1-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP41]] +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP41]] // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK1-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP48]] -// CHECK1-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP48]] +// CHECK1-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP41]] +// CHECK1-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]] // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i32 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 1 // CHECK1-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16 -// CHECK1-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP48]] -// CHECK1-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP48]] +// CHECK1-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]] +// CHECK1-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP41]] // CHECK1-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i32 // CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1 // CHECK1-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8 -// CHECK1-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP48]] +// CHECK1-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP41]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 -// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP48]] +// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP41]] // CHECK1-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK1-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP48]] +// CHECK1-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP41]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48]] +// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41]] // CHECK1-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 1 -// CHECK1-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP49:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1972,7 +1972,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -2014,35 +2014,35 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP51:![0-9]+]] -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP51]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44:![0-9]+]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP44]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP51]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP51]] -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP51]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP44]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]] // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP51]] -// CHECK1-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP51]] +// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP44]] // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP51]] +// CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP44]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP51]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]] // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK1-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP51]] +// CHECK1-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP51]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]] // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP51]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP52:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -2058,7 +2058,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK1-SAME: () #[[ATTR5]] { +// CHECK1-SAME: () #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) // CHECK1-NEXT: ret void @@ -2180,7 +2180,7 @@ int bar(int n){ // CHECK3-NEXT: [[TMP41:%.*]] = load i32, ptr [[A]], align 4 // CHECK3-NEXT: store i32 [[TMP41]], ptr [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP42:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP42]]) #[[ATTR4:[0-9]+]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP42]]) #[[ATTR3:[0-9]+]] // CHECK3-NEXT: [[TMP43:%.*]] = load i16, ptr [[AA]], align 2 // CHECK3-NEXT: store i16 [[TMP43]], ptr [[AA_CASTED4]], align 2 // CHECK3-NEXT: [[TMP44:%.*]] = load i32, ptr [[AA_CASTED4]], align 4 @@ -2222,7 +2222,7 @@ int bar(int n){ // CHECK3-NEXT: [[TMP64:%.*]] = icmp ne i32 [[TMP63]], 0 // CHECK3-NEXT: br i1 [[TMP64]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP44]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP44]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: [[TMP65:%.*]] = load i32, ptr [[A]], align 4 @@ -2279,12 +2279,12 @@ int bar(int n){ // CHECK3-NEXT: [[TMP92:%.*]] = icmp ne i32 [[TMP91]], 0 // CHECK3-NEXT: br i1 [[TMP92]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] // CHECK3: omp_offload.failed15: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT16]] // CHECK3: omp_offload.cont16: // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3: omp_if.else: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_IF_END]] // CHECK3: omp_if.end: // CHECK3-NEXT: [[TMP93:%.*]] = load i32, ptr [[A]], align 4 @@ -2391,12 +2391,12 @@ int bar(int n){ // CHECK3-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0 // CHECK3-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]] // CHECK3: omp_offload.failed25: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP94]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP94]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT26]] // CHECK3: omp_offload.cont26: // CHECK3-NEXT: br label [[OMP_IF_END28:%.*]] // CHECK3: omp_if.else27: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP94]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP94]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_IF_END28]] // CHECK3: omp_if.end28: // CHECK3-NEXT: [[TMP148:%.*]] = load i32, ptr [[A]], align 4 @@ -2427,7 +2427,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -2464,23 +2464,23 @@ int bar(int n){ // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK3-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -2496,7 +2496,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK3-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK3-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 @@ -2525,7 +2525,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4 @@ -2552,74 +2552,74 @@ int bar(int n){ // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]]) -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]]) -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]]) -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META32:![0-9]+]]) -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !34 -// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias !34 -// CHECK3-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !34 -// CHECK3-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !34 -// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias !34 -// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !34 -// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !34 -// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !34 -// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !34 -// CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] -// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !34 -// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !34 -// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !34 -// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !34 +// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !27 +// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias !27 +// CHECK3-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !27 +// CHECK3-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !27 +// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias !27 +// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !27 +// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !27 +// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !27 +// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !27 +// CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !27 +// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !27 +// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !27 +// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !27 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4 // CHECK3-NEXT: [[TMP19:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP18]], 0 -// CHECK3-NEXT: store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !34 +// CHECK3-NEXT: store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !27 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1 -// CHECK3-NEXT: store i32 3, ptr [[TMP20]], align 4, !noalias !34 +// CHECK3-NEXT: store i32 3, ptr [[TMP20]], align 4, !noalias !27 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2 -// CHECK3-NEXT: store ptr [[TMP13]], ptr [[TMP21]], align 4, !noalias !34 +// CHECK3-NEXT: store ptr [[TMP13]], ptr [[TMP21]], align 4, !noalias !27 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3 -// CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP22]], align 4, !noalias !34 +// CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP22]], align 4, !noalias !27 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4 -// CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP23]], align 4, !noalias !34 +// CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP23]], align 4, !noalias !27 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5 -// CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP24]], align 4, !noalias !34 +// CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP24]], align 4, !noalias !27 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6 -// CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 4, !noalias !34 +// CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 4, !noalias !27 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7 -// CHECK3-NEXT: store ptr null, ptr [[TMP26]], align 4, !noalias !34 +// CHECK3-NEXT: store ptr null, ptr [[TMP26]], align 4, !noalias !27 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8 -// CHECK3-NEXT: store i64 10, ptr [[TMP27]], align 8, !noalias !34 +// CHECK3-NEXT: store i64 10, ptr [[TMP27]], align 8, !noalias !27 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9 -// CHECK3-NEXT: store i64 1, ptr [[TMP28]], align 8, !noalias !34 +// CHECK3-NEXT: store i64 1, ptr [[TMP28]], align 8, !noalias !27 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10 -// CHECK3-NEXT: store [3 x i32] [[TMP19]], ptr [[TMP29]], align 4, !noalias !34 +// CHECK3-NEXT: store [3 x i32] [[TMP19]], ptr [[TMP29]], align 4, !noalias !27 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11 -// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP30]], align 4, !noalias !34 +// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP30]], align 4, !noalias !27 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12 -// CHECK3-NEXT: store i32 0, ptr [[TMP31]], align 4, !noalias !34 +// CHECK3-NEXT: store i32 0, ptr [[TMP31]], align 4, !noalias !27 // CHECK3-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 [[TMP18]], i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, ptr [[KERNEL_ARGS_I]]) // CHECK3-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 // CHECK3-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK3: omp_offload.failed.i: // CHECK3-NEXT: [[TMP34:%.*]] = load i16, ptr [[TMP12]], align 2 -// CHECK3-NEXT: store i16 [[TMP34]], ptr [[AA_CASTED_I]], align 2, !noalias !34 -// CHECK3-NEXT: [[TMP35:%.*]] = load i32, ptr [[AA_CASTED_I]], align 4, !noalias !34 +// CHECK3-NEXT: store i16 [[TMP34]], ptr [[AA_CASTED_I]], align 2, !noalias !27 +// CHECK3-NEXT: [[TMP35:%.*]] = load i32, ptr [[AA_CASTED_I]], align 4, !noalias !27 // CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP16]], align 4 -// CHECK3-NEXT: store i32 [[TMP36]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !34 -// CHECK3-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !34 +// CHECK3-NEXT: store i32 [[TMP36]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !27 +// CHECK3-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !27 // CHECK3-NEXT: [[TMP38:%.*]] = load i32, ptr [[TMP17]], align 4 -// CHECK3-NEXT: store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !34 -// CHECK3-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !34 -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i32 [[TMP35]], i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR4]] +// CHECK3-NEXT: store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !27 +// CHECK3-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !27 +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i32 [[TMP35]], i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR3]] // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] // CHECK3: .omp_outlined..exit: // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 -// CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -2632,7 +2632,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -2688,7 +2688,7 @@ int bar(int n){ // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -2717,7 +2717,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -2754,28 +2754,28 @@ int bar(int n){ // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37:![0-9]+]] -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP37]] +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30:![0-9]+]] +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]] +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP37]] -// CHECK3-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP37]] +// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK3-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]] // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK3-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP37]] +// CHECK3-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]] +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]] -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -2810,7 +2810,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -2849,31 +2849,31 @@ int bar(int n){ // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40:![0-9]+]] -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP40]] +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]] +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]] +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP40]] -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP40]] +// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP40]] -// CHECK3-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP40]] +// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK3-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP40]] +// CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]] +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]] -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -2926,7 +2926,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -2989,59 +2989,59 @@ int bar(int n){ // CHECK3-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP43:![0-9]+]] -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]] +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP43]] -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK3-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK3-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK3-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double // CHECK3-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00 // CHECK3-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float -// CHECK3-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK3-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3 -// CHECK3-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK3-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK3-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double // CHECK3-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 // CHECK3-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK3-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK3-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP43]] +// CHECK3-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP36]] // CHECK3-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00 -// CHECK3-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP43]] +// CHECK3-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP36]] // CHECK3-NEXT: [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]] // CHECK3-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP20]] // CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i32 3 -// CHECK3-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP43]] +// CHECK3-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP36]] // CHECK3-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00 -// CHECK3-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP43]] +// CHECK3-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP36]] // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK3-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK3-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1 -// CHECK3-NEXT: store i64 [[ADD19]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK3-NEXT: store i64 [[ADD19]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK3-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK3-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i32 // CHECK3-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1 // CHECK3-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8 -// CHECK3-NEXT: store i8 [[CONV22]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK3-NEXT: store i8 [[CONV22]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK3-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK3-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP43]] -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -3192,12 +3192,12 @@ int bar(int n){ // CHECK3-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 // CHECK3-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3: omp_if.else: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_IF_END]] // CHECK3: omp_if.end: // CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]] @@ -3329,12 +3329,12 @@ int bar(int n){ // CHECK3-NEXT: [[TMP46:%.*]] = icmp ne i32 [[TMP45]], 0 // CHECK3-NEXT: br i1 [[TMP46]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], ptr [[B]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], ptr [[B]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3: omp_if.else: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], ptr [[B]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], ptr [[B]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_IF_END]] // CHECK3: omp_if.end: // CHECK3-NEXT: [[TMP47:%.*]] = load i32, ptr [[A]], align 4 @@ -3418,12 +3418,12 @@ int bar(int n){ // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3: omp_if.else: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_IF_END]] // CHECK3: omp_if.end: // CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4 @@ -3456,7 +3456,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -3505,37 +3505,37 @@ int bar(int n){ // CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46:![0-9]+]] -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP46]] +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39:![0-9]+]] +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46]] +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP46]] -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP46]] +// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double // CHECK3-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 -// CHECK3-NEXT: store double [[ADD4]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP46]] +// CHECK3-NEXT: store double [[ADD4]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK3-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP46]] +// CHECK3-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK3-NEXT: store double [[INC]], ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP46]] +// CHECK3-NEXT: store double [[INC]], ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK3-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 // CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]] // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 -// CHECK3-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP46]] +// CHECK3-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP39]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46]] +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK3-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46]] -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -3585,7 +3585,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -3657,42 +3657,42 @@ int bar(int n){ // CHECK3-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49:![0-9]+]] -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP49]] +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42:![0-9]+]] +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP42]] // CHECK3-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 1 // CHECK3-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]] // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP49]] -// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49]] +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] // CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]] -// CHECK3-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP49]] -// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP49]] +// CHECK3-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP42]] // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK3-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP49]] -// CHECK3-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP49]] +// CHECK3-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK3-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP42]] // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i32 // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 1 // CHECK3-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16 -// CHECK3-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP49]] -// CHECK3-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP49]] +// CHECK3-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP42]] +// CHECK3-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP42]] // CHECK3-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i32 // CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1 // CHECK3-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8 -// CHECK3-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP49]] +// CHECK3-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP42]] // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP49]] +// CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP42]] // CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK3-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP49]] +// CHECK3-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP42]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49]] +// CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] // CHECK3-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 1 -// CHECK3-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49]] -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -3743,7 +3743,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -3785,35 +3785,35 @@ int bar(int n){ // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52:![0-9]+]] -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP52]] +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]] +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52]] +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP52]] -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP52]] +// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP52]] -// CHECK3-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP52]] +// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK3-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP45]] // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP52]] +// CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP45]] // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP52]] +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK3-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP52]] +// CHECK3-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52]] +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52]] -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP53:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -3829,7 +3829,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK3-SAME: () #[[ATTR5]] { +// CHECK3-SAME: () #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) // CHECK3-NEXT: ret void @@ -3953,7 +3953,7 @@ int bar(int n){ // CHECK5-NEXT: [[TMP43:%.*]] = load i32, ptr [[A]], align 4 // CHECK5-NEXT: store i32 [[TMP43]], ptr [[A_CASTED]], align 4 // CHECK5-NEXT: [[TMP44:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102(i64 [[TMP44]]) #[[ATTR4:[0-9]+]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102(i64 [[TMP44]]) #[[ATTR3:[0-9]+]] // CHECK5-NEXT: [[TMP45:%.*]] = load i16, ptr [[AA]], align 2 // CHECK5-NEXT: store i16 [[TMP45]], ptr [[AA_CASTED4]], align 2 // CHECK5-NEXT: [[TMP46:%.*]] = load i64, ptr [[AA_CASTED4]], align 8 @@ -3995,7 +3995,7 @@ int bar(int n){ // CHECK5-NEXT: [[TMP66:%.*]] = icmp ne i32 [[TMP65]], 0 // CHECK5-NEXT: br i1 [[TMP66]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK5: omp_offload.failed: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP46]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP46]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK5: omp_offload.cont: // CHECK5-NEXT: [[TMP67:%.*]] = load i32, ptr [[A]], align 4 @@ -4052,12 +4052,12 @@ int bar(int n){ // CHECK5-NEXT: [[TMP94:%.*]] = icmp ne i32 [[TMP93]], 0 // CHECK5-NEXT: br i1 [[TMP94]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] // CHECK5: omp_offload.failed15: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT16]] // CHECK5: omp_offload.cont16: // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] // CHECK5: omp_if.else: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_IF_END]] // CHECK5: omp_if.end: // CHECK5-NEXT: [[TMP95:%.*]] = load i32, ptr [[A]], align 4 @@ -4162,12 +4162,12 @@ int bar(int n){ // CHECK5-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0 // CHECK5-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]] // CHECK5: omp_offload.failed25: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP96]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP96]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT26]] // CHECK5: omp_offload.cont26: // CHECK5-NEXT: br label [[OMP_IF_END28:%.*]] // CHECK5: omp_if.else27: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP96]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP96]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_IF_END28]] // CHECK5: omp_if.end28: // CHECK5-NEXT: [[TMP148:%.*]] = load i32, ptr [[A]], align 4 @@ -4198,7 +4198,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -4235,23 +4235,23 @@ int bar(int n){ // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -4267,7 +4267,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK5-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK5-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 @@ -4296,7 +4296,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK5-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK5-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 @@ -4323,74 +4323,74 @@ int bar(int n){ // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 +// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) +// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) +// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META31:![0-9]+]]) -// CHECK5-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !33 -// CHECK5-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !33 -// CHECK5-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !33 -// CHECK5-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !33 -// CHECK5-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !33 -// CHECK5-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !33 -// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !33 -// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !33 -// CHECK5-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !33 -// CHECK5-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !33 -// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !33 -// CHECK5-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !33 -// CHECK5-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !33 +// CHECK5-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26 +// CHECK5-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !26 +// CHECK5-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !26 +// CHECK5-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !26 +// CHECK5-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !26 +// CHECK5-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !26 +// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !26 +// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !26 +// CHECK5-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !26 +// CHECK5-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !26 +// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !26 +// CHECK5-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !26 +// CHECK5-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !26 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4 // CHECK5-NEXT: [[TMP19:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP18]], 0 -// CHECK5-NEXT: store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !33 +// CHECK5-NEXT: store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !26 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1 -// CHECK5-NEXT: store i32 3, ptr [[TMP20]], align 4, !noalias !33 +// CHECK5-NEXT: store i32 3, ptr [[TMP20]], align 4, !noalias !26 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2 -// CHECK5-NEXT: store ptr [[TMP13]], ptr [[TMP21]], align 8, !noalias !33 +// CHECK5-NEXT: store ptr [[TMP13]], ptr [[TMP21]], align 8, !noalias !26 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3 -// CHECK5-NEXT: store ptr [[TMP14]], ptr [[TMP22]], align 8, !noalias !33 +// CHECK5-NEXT: store ptr [[TMP14]], ptr [[TMP22]], align 8, !noalias !26 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4 -// CHECK5-NEXT: store ptr [[TMP15]], ptr [[TMP23]], align 8, !noalias !33 +// CHECK5-NEXT: store ptr [[TMP15]], ptr [[TMP23]], align 8, !noalias !26 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5 -// CHECK5-NEXT: store ptr @.offload_maptypes, ptr [[TMP24]], align 8, !noalias !33 +// CHECK5-NEXT: store ptr @.offload_maptypes, ptr [[TMP24]], align 8, !noalias !26 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6 -// CHECK5-NEXT: store ptr null, ptr [[TMP25]], align 8, !noalias !33 +// CHECK5-NEXT: store ptr null, ptr [[TMP25]], align 8, !noalias !26 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7 -// CHECK5-NEXT: store ptr null, ptr [[TMP26]], align 8, !noalias !33 +// CHECK5-NEXT: store ptr null, ptr [[TMP26]], align 8, !noalias !26 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8 -// CHECK5-NEXT: store i64 10, ptr [[TMP27]], align 8, !noalias !33 +// CHECK5-NEXT: store i64 10, ptr [[TMP27]], align 8, !noalias !26 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9 -// CHECK5-NEXT: store i64 1, ptr [[TMP28]], align 8, !noalias !33 +// CHECK5-NEXT: store i64 1, ptr [[TMP28]], align 8, !noalias !26 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10 -// CHECK5-NEXT: store [3 x i32] [[TMP19]], ptr [[TMP29]], align 4, !noalias !33 +// CHECK5-NEXT: store [3 x i32] [[TMP19]], ptr [[TMP29]], align 4, !noalias !26 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11 -// CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP30]], align 4, !noalias !33 +// CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP30]], align 4, !noalias !26 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12 -// CHECK5-NEXT: store i32 0, ptr [[TMP31]], align 4, !noalias !33 +// CHECK5-NEXT: store i32 0, ptr [[TMP31]], align 4, !noalias !26 // CHECK5-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 [[TMP18]], i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, ptr [[KERNEL_ARGS_I]]) // CHECK5-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 // CHECK5-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK5: omp_offload.failed.i: // CHECK5-NEXT: [[TMP34:%.*]] = load i16, ptr [[TMP12]], align 2 -// CHECK5-NEXT: store i16 [[TMP34]], ptr [[AA_CASTED_I]], align 2, !noalias !33 -// CHECK5-NEXT: [[TMP35:%.*]] = load i64, ptr [[AA_CASTED_I]], align 8, !noalias !33 +// CHECK5-NEXT: store i16 [[TMP34]], ptr [[AA_CASTED_I]], align 2, !noalias !26 +// CHECK5-NEXT: [[TMP35:%.*]] = load i64, ptr [[AA_CASTED_I]], align 8, !noalias !26 // CHECK5-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP16]], align 4 -// CHECK5-NEXT: store i32 [[TMP36]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !33 -// CHECK5-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !33 +// CHECK5-NEXT: store i32 [[TMP36]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !26 +// CHECK5-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !26 // CHECK5-NEXT: [[TMP38:%.*]] = load i32, ptr [[TMP17]], align 4 -// CHECK5-NEXT: store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !33 -// CHECK5-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 8, !noalias !33 -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i64 [[TMP35]], i64 [[TMP37]], i64 [[TMP39]]) #[[ATTR4]] +// CHECK5-NEXT: store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !26 +// CHECK5-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 8, !noalias !26 +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i64 [[TMP35]], i64 [[TMP37]], i64 [[TMP39]]) #[[ATTR3]] // CHECK5-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] // CHECK5: .omp_outlined..exit: // CHECK5-NEXT: ret i32 0 // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102 -// CHECK5-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -4403,7 +4403,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -4448,10 +4448,10 @@ int bar(int n){ // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[A1]], align 4, !nontemporal !34 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4, !nontemporal !34 +// CHECK5-NEXT: store i32 [[ADD]], ptr [[A1]], align 4, !nontemporal !27 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4, !nontemporal !27 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], ptr [[A1]], align 4, !nontemporal !34 +// CHECK5-NEXT: store i32 [[ADD3]], ptr [[A1]], align 4, !nontemporal !27 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -4459,7 +4459,7 @@ int bar(int n){ // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -4488,7 +4488,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -4525,28 +4525,28 @@ int bar(int n){ // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37:![0-9]+]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP37]] +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30:![0-9]+]] +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP37]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP37]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]] // CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 // CHECK5-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK5-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP37]] +// CHECK5-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -4581,7 +4581,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -4620,31 +4620,31 @@ int bar(int n){ // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40:![0-9]+]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP40]] +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]] +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP40]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP40]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP40]] -// CHECK5-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP40]] +// CHECK5-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] // CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK5-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK5-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP40]] +// CHECK5-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]] +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -4697,7 +4697,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -4760,59 +4760,59 @@ int bar(int n){ // CHECK5-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP43:![0-9]+]] -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]] +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP43]] -// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK5-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK5-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK5-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double // CHECK5-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00 // CHECK5-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float -// CHECK5-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK5-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3 -// CHECK5-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK5-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double // CHECK5-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 // CHECK5-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK5-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK5-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 // CHECK5-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP43]] +// CHECK5-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP43]] +// CHECK5-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]] // CHECK5-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP20]] // CHECK5-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i64 3 -// CHECK5-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP43]] +// CHECK5-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP43]] +// CHECK5-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP43]] +// CHECK5-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1 -// CHECK5-NEXT: store i64 [[ADD19]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP43]] +// CHECK5-NEXT: store i64 [[ADD19]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP43]] +// CHECK5-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i32 // CHECK5-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1 // CHECK5-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8 -// CHECK5-NEXT: store i8 [[CONV22]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP43]] +// CHECK5-NEXT: store i8 [[CONV22]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK5-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP43]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -4980,12 +4980,12 @@ int bar(int n){ // CHECK5-NEXT: [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 0 // CHECK5-NEXT: br i1 [[TMP49]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK5: omp_offload.failed: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], ptr [[VLA]], i64 [[TMP9]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], ptr [[VLA]], i64 [[TMP9]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK5: omp_offload.cont: // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] // CHECK5: omp_if.else: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], ptr [[VLA]], i64 [[TMP9]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], ptr [[VLA]], i64 [[TMP9]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_IF_END]] // CHECK5: omp_if.end: // CHECK5-NEXT: [[TMP50:%.*]] = mul nsw i64 1, [[TMP2]] @@ -5117,12 +5117,12 @@ int bar(int n){ // CHECK5-NEXT: [[TMP46:%.*]] = icmp ne i32 [[TMP45]], 0 // CHECK5-NEXT: br i1 [[TMP46]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK5: omp_offload.failed: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], ptr [[B]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], ptr [[B]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK5: omp_offload.cont: // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] // CHECK5: omp_if.else: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], ptr [[B]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], ptr [[B]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_IF_END]] // CHECK5: omp_if.end: // CHECK5-NEXT: [[TMP47:%.*]] = load i32, ptr [[A]], align 4 @@ -5206,12 +5206,12 @@ int bar(int n){ // CHECK5-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 // CHECK5-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK5: omp_offload.failed: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK5: omp_offload.cont: // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] // CHECK5: omp_if.else: -// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK5-NEXT: br label [[OMP_IF_END]] // CHECK5: omp_if.end: // CHECK5-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4 @@ -5252,7 +5252,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -5307,37 +5307,37 @@ int bar(int n){ // CHECK5: omp_if.then: // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46:![0-9]+]] -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP46]] +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39:![0-9]+]] +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46]] +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP46]] -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP46]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double // CHECK5-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 -// CHECK5-NEXT: store double [[ADD4]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP46]] +// CHECK5-NEXT: store double [[ADD4]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP39]] // CHECK5-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP14:%.*]] = load double, ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP46]] +// CHECK5-NEXT: [[TMP14:%.*]] = load double, ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP39]] // CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 -// CHECK5-NEXT: store double [[INC]], ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP46]] +// CHECK5-NEXT: store double [[INC]], ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP39]] // CHECK5-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 // CHECK5-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]] // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP15]] // CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 -// CHECK5-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP46]] +// CHECK5-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP39]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46]] +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK5-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] // CHECK5: omp_if.else: @@ -5373,7 +5373,7 @@ int bar(int n){ // CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK5-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP49:![0-9]+]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP42:![0-9]+]] // CHECK5: omp.inner.for.end25: // CHECK5-NEXT: br label [[OMP_IF_END]] // CHECK5: omp_if.end: @@ -5425,7 +5425,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -5497,42 +5497,42 @@ int bar(int n){ // CHECK5-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP51:![0-9]+]] -// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP51]] +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44:![0-9]+]] +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP44]] // CHECK5-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 1 // CHECK5-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]] // CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP51]] -// CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP51]] +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP44]] +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]] // CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK5-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]] -// CHECK5-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP51]] -// CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP51]] +// CHECK5-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP44]] +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]] // CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK5-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP51]] -// CHECK5-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP51]] +// CHECK5-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]] +// CHECK5-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP44]] // CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i32 // CHECK5-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 1 // CHECK5-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16 -// CHECK5-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP51]] -// CHECK5-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP51]] +// CHECK5-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP44]] +// CHECK5-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP44]] // CHECK5-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i32 // CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1 // CHECK5-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8 -// CHECK5-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP51]] +// CHECK5-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP44]] // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP51]] +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]] // CHECK5-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK5-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP51]] +// CHECK5-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP51]] +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]] // CHECK5-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 1 -// CHECK5-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP51]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP52:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -5583,7 +5583,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -5625,35 +5625,35 @@ int bar(int n){ // CHECK5-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP54:![0-9]+]] -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP54]] +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP47:![0-9]+]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP47]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP54]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP47]] // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP54]] -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP54]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP47]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP47]] // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK5-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP54]] -// CHECK5-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP54]] +// CHECK5-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP47]] +// CHECK5-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP47]] // CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK5-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK5-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP54]] +// CHECK5-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP47]] // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP54]] +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP47]] // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK5-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP54]] +// CHECK5-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP47]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP54]] +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP47]] // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK5-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP54]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP55:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP47]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP48:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -5669,7 +5669,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK5-SAME: () #[[ATTR5]] { +// CHECK5-SAME: () #[[ATTR4]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: call void @__tgt_register_requires(i64 1) // CHECK5-NEXT: ret void @@ -5791,7 +5791,7 @@ int bar(int n){ // CHECK7-NEXT: [[TMP41:%.*]] = load i32, ptr [[A]], align 4 // CHECK7-NEXT: store i32 [[TMP41]], ptr [[A_CASTED]], align 4 // CHECK7-NEXT: [[TMP42:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102(i32 [[TMP42]]) #[[ATTR4:[0-9]+]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102(i32 [[TMP42]]) #[[ATTR3:[0-9]+]] // CHECK7-NEXT: [[TMP43:%.*]] = load i16, ptr [[AA]], align 2 // CHECK7-NEXT: store i16 [[TMP43]], ptr [[AA_CASTED4]], align 2 // CHECK7-NEXT: [[TMP44:%.*]] = load i32, ptr [[AA_CASTED4]], align 4 @@ -5833,7 +5833,7 @@ int bar(int n){ // CHECK7-NEXT: [[TMP64:%.*]] = icmp ne i32 [[TMP63]], 0 // CHECK7-NEXT: br i1 [[TMP64]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK7: omp_offload.failed: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP44]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP44]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK7: omp_offload.cont: // CHECK7-NEXT: [[TMP65:%.*]] = load i32, ptr [[A]], align 4 @@ -5890,12 +5890,12 @@ int bar(int n){ // CHECK7-NEXT: [[TMP92:%.*]] = icmp ne i32 [[TMP91]], 0 // CHECK7-NEXT: br i1 [[TMP92]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] // CHECK7: omp_offload.failed15: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT16]] // CHECK7: omp_offload.cont16: // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] // CHECK7: omp_if.else: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_IF_END]] // CHECK7: omp_if.end: // CHECK7-NEXT: [[TMP93:%.*]] = load i32, ptr [[A]], align 4 @@ -6002,12 +6002,12 @@ int bar(int n){ // CHECK7-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0 // CHECK7-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]] // CHECK7: omp_offload.failed25: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP94]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP94]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT26]] // CHECK7: omp_offload.cont26: // CHECK7-NEXT: br label [[OMP_IF_END28:%.*]] // CHECK7: omp_if.else27: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP94]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP94]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_IF_END28]] // CHECK7: omp_if.end28: // CHECK7-NEXT: [[TMP148:%.*]] = load i32, ptr [[A]], align 4 @@ -6038,7 +6038,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined -// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -6075,23 +6075,23 @@ int bar(int n){ // CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK7-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK7: omp.loop.exit: @@ -6107,7 +6107,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK7-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK7-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 @@ -6136,7 +6136,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK7-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK7-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4 @@ -6163,74 +6163,74 @@ int bar(int n){ // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 +// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) +// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) +// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]]) -// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]]) -// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]]) -// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META32:![0-9]+]]) -// CHECK7-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !34 -// CHECK7-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias !34 -// CHECK7-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !34 -// CHECK7-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !34 -// CHECK7-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias !34 -// CHECK7-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !34 -// CHECK7-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !34 -// CHECK7-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !34 -// CHECK7-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !34 -// CHECK7-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] -// CHECK7-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !34 -// CHECK7-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !34 -// CHECK7-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !34 -// CHECK7-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !34 +// CHECK7-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !27 +// CHECK7-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias !27 +// CHECK7-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !27 +// CHECK7-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !27 +// CHECK7-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias !27 +// CHECK7-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !27 +// CHECK7-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !27 +// CHECK7-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !27 +// CHECK7-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !27 +// CHECK7-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK7-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !27 +// CHECK7-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !27 +// CHECK7-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !27 +// CHECK7-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !27 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4 // CHECK7-NEXT: [[TMP19:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP18]], 0 -// CHECK7-NEXT: store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !34 +// CHECK7-NEXT: store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !27 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1 -// CHECK7-NEXT: store i32 3, ptr [[TMP20]], align 4, !noalias !34 +// CHECK7-NEXT: store i32 3, ptr [[TMP20]], align 4, !noalias !27 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2 -// CHECK7-NEXT: store ptr [[TMP13]], ptr [[TMP21]], align 4, !noalias !34 +// CHECK7-NEXT: store ptr [[TMP13]], ptr [[TMP21]], align 4, !noalias !27 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3 -// CHECK7-NEXT: store ptr [[TMP14]], ptr [[TMP22]], align 4, !noalias !34 +// CHECK7-NEXT: store ptr [[TMP14]], ptr [[TMP22]], align 4, !noalias !27 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4 -// CHECK7-NEXT: store ptr [[TMP15]], ptr [[TMP23]], align 4, !noalias !34 +// CHECK7-NEXT: store ptr [[TMP15]], ptr [[TMP23]], align 4, !noalias !27 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5 -// CHECK7-NEXT: store ptr @.offload_maptypes, ptr [[TMP24]], align 4, !noalias !34 +// CHECK7-NEXT: store ptr @.offload_maptypes, ptr [[TMP24]], align 4, !noalias !27 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6 -// CHECK7-NEXT: store ptr null, ptr [[TMP25]], align 4, !noalias !34 +// CHECK7-NEXT: store ptr null, ptr [[TMP25]], align 4, !noalias !27 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7 -// CHECK7-NEXT: store ptr null, ptr [[TMP26]], align 4, !noalias !34 +// CHECK7-NEXT: store ptr null, ptr [[TMP26]], align 4, !noalias !27 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8 -// CHECK7-NEXT: store i64 10, ptr [[TMP27]], align 8, !noalias !34 +// CHECK7-NEXT: store i64 10, ptr [[TMP27]], align 8, !noalias !27 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9 -// CHECK7-NEXT: store i64 1, ptr [[TMP28]], align 8, !noalias !34 +// CHECK7-NEXT: store i64 1, ptr [[TMP28]], align 8, !noalias !27 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10 -// CHECK7-NEXT: store [3 x i32] [[TMP19]], ptr [[TMP29]], align 4, !noalias !34 +// CHECK7-NEXT: store [3 x i32] [[TMP19]], ptr [[TMP29]], align 4, !noalias !27 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11 -// CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP30]], align 4, !noalias !34 +// CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP30]], align 4, !noalias !27 // CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12 -// CHECK7-NEXT: store i32 0, ptr [[TMP31]], align 4, !noalias !34 +// CHECK7-NEXT: store i32 0, ptr [[TMP31]], align 4, !noalias !27 // CHECK7-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 [[TMP18]], i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, ptr [[KERNEL_ARGS_I]]) // CHECK7-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 // CHECK7-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK7: omp_offload.failed.i: // CHECK7-NEXT: [[TMP34:%.*]] = load i16, ptr [[TMP12]], align 2 -// CHECK7-NEXT: store i16 [[TMP34]], ptr [[AA_CASTED_I]], align 2, !noalias !34 -// CHECK7-NEXT: [[TMP35:%.*]] = load i32, ptr [[AA_CASTED_I]], align 4, !noalias !34 +// CHECK7-NEXT: store i16 [[TMP34]], ptr [[AA_CASTED_I]], align 2, !noalias !27 +// CHECK7-NEXT: [[TMP35:%.*]] = load i32, ptr [[AA_CASTED_I]], align 4, !noalias !27 // CHECK7-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP16]], align 4 -// CHECK7-NEXT: store i32 [[TMP36]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !34 -// CHECK7-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !34 +// CHECK7-NEXT: store i32 [[TMP36]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !27 +// CHECK7-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !27 // CHECK7-NEXT: [[TMP38:%.*]] = load i32, ptr [[TMP17]], align 4 -// CHECK7-NEXT: store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !34 -// CHECK7-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !34 -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i32 [[TMP35]], i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR4]] +// CHECK7-NEXT: store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !27 +// CHECK7-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !27 +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i32 [[TMP35]], i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR3]] // CHECK7-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] // CHECK7: .omp_outlined..exit: // CHECK7-NEXT: ret i32 0 // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102 -// CHECK7-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -6243,7 +6243,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102.omp_outlined -// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -6288,10 +6288,10 @@ int bar(int n){ // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK7-NEXT: store i32 [[ADD]], ptr [[A1]], align 4, !nontemporal !35 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4, !nontemporal !35 +// CHECK7-NEXT: store i32 [[ADD]], ptr [[A1]], align 4, !nontemporal !28 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4, !nontemporal !28 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[ADD3]], ptr [[A1]], align 4, !nontemporal !35 +// CHECK7-NEXT: store i32 [[ADD3]], ptr [[A1]], align 4, !nontemporal !28 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -6299,7 +6299,7 @@ int bar(int n){ // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK7-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK7: omp.loop.exit: @@ -6328,7 +6328,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined -// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -6365,28 +6365,28 @@ int bar(int n){ // CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38:![0-9]+]] -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31:![0-9]+]] +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP38]] -// CHECK7-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP38]] +// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK7-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP31]] // CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 // CHECK7-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK7-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP38]] +// CHECK7-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP31]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK7-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]] -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]] +// CHECK7-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK7: omp.loop.exit: @@ -6421,7 +6421,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined -// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -6460,31 +6460,31 @@ int bar(int n){ // CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41:![0-9]+]] -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP41]] +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34:![0-9]+]] +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41]] +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP41]] -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP41]] +// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP41]] -// CHECK7-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]] +// CHECK7-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK7-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP34]] // CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK7-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK7-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]] +// CHECK7-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP34]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41]] +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK7-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41]] -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]] +// CHECK7-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK7: omp.loop.exit: @@ -6537,7 +6537,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined -// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -6600,59 +6600,59 @@ int bar(int n){ // CHECK7-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44:![0-9]+]] -// CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP44]] +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37:![0-9]+]] +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]] +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP44]] -// CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]] +// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP37]] +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK7-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]] +// CHECK7-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]] +// CHECK7-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK7-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double // CHECK7-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00 // CHECK7-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float -// CHECK7-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]] +// CHECK7-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK7-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3 -// CHECK7-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP44]] +// CHECK7-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK7-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double // CHECK7-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 // CHECK7-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK7-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP44]] +// CHECK7-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK7-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 // CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP44]] +// CHECK7-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP37]] // CHECK7-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP44]] +// CHECK7-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP37]] // CHECK7-NEXT: [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]] // CHECK7-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP20]] // CHECK7-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i32 3 -// CHECK7-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP44]] +// CHECK7-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP37]] // CHECK7-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP44]] +// CHECK7-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP37]] // CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP44]] +// CHECK7-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK7-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1 -// CHECK7-NEXT: store i64 [[ADD19]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP44]] +// CHECK7-NEXT: store i64 [[ADD19]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP44]] +// CHECK7-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK7-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i32 // CHECK7-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1 // CHECK7-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8 -// CHECK7-NEXT: store i8 [[CONV22]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP44]] +// CHECK7-NEXT: store i8 [[CONV22]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]] +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK7-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK7-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]] -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]] +// CHECK7-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]] +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK7: omp.loop.exit: @@ -6820,12 +6820,12 @@ int bar(int n){ // CHECK7-NEXT: [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 0 // CHECK7-NEXT: br i1 [[TMP49]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK7: omp_offload.failed: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], ptr [[VLA]], i32 [[TMP8]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], ptr [[VLA]], i32 [[TMP8]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK7: omp_offload.cont: // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] // CHECK7: omp_if.else: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], ptr [[VLA]], i32 [[TMP8]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], ptr [[VLA]], i32 [[TMP8]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_IF_END]] // CHECK7: omp_if.end: // CHECK7-NEXT: [[TMP50:%.*]] = mul nsw i32 1, [[TMP1]] @@ -6957,12 +6957,12 @@ int bar(int n){ // CHECK7-NEXT: [[TMP46:%.*]] = icmp ne i32 [[TMP45]], 0 // CHECK7-NEXT: br i1 [[TMP46]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK7: omp_offload.failed: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], ptr [[B]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], ptr [[B]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK7: omp_offload.cont: // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] // CHECK7: omp_if.else: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], ptr [[B]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], ptr [[B]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_IF_END]] // CHECK7: omp_if.end: // CHECK7-NEXT: [[TMP47:%.*]] = load i32, ptr [[A]], align 4 @@ -7046,12 +7046,12 @@ int bar(int n){ // CHECK7-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 // CHECK7-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK7: omp_offload.failed: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK7: omp_offload.cont: // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] // CHECK7: omp_if.else: -// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]] +// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK7-NEXT: br label [[OMP_IF_END]] // CHECK7: omp_if.end: // CHECK7-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4 @@ -7092,7 +7092,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined -// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -7147,37 +7147,37 @@ int bar(int n){ // CHECK7: omp_if.then: // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP47:![0-9]+]] -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP47]] +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40:![0-9]+]] +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK7-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK7-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP47]] +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP47]] -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP47]] +// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP40]] +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double // CHECK7-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 -// CHECK7-NEXT: store double [[ADD4]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP47]] +// CHECK7-NEXT: store double [[ADD4]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK7-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP14:%.*]] = load double, ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP47]] +// CHECK7-NEXT: [[TMP14:%.*]] = load double, ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 -// CHECK7-NEXT: store double [[INC]], ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP47]] +// CHECK7-NEXT: store double [[INC]], ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK7-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 // CHECK7-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]] // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP15]] // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 -// CHECK7-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP47]] +// CHECK7-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP40]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP47]] +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK7-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP47]] -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP48:![0-9]+]] +// CHECK7-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]] +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] // CHECK7: omp_if.else: @@ -7213,7 +7213,7 @@ int bar(int n){ // CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK7-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK7-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4 -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP50:![0-9]+]] +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP43:![0-9]+]] // CHECK7: omp.inner.for.end25: // CHECK7-NEXT: br label [[OMP_IF_END]] // CHECK7: omp_if.end: @@ -7265,7 +7265,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined -// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -7337,42 +7337,42 @@ int bar(int n){ // CHECK7-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52:![0-9]+]] -// CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP52]] +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]] +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK7-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 1 // CHECK7-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]] // CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP52]] -// CHECK7-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52]] +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK7-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK7-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]] -// CHECK7-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP52]] -// CHECK7-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP52]] +// CHECK7-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK7-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK7-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP52]] -// CHECK7-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP52]] +// CHECK7-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK7-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP45]] // CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i32 // CHECK7-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 1 // CHECK7-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16 -// CHECK7-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP52]] -// CHECK7-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP52]] +// CHECK7-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP45]] +// CHECK7-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP45]] // CHECK7-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i32 // CHECK7-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1 // CHECK7-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8 -// CHECK7-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP52]] +// CHECK7-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP45]] // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP52]] +// CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK7-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK7-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP52]] +// CHECK7-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52]] +// CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK7-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 1 -// CHECK7-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52]] -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP53:![0-9]+]] +// CHECK7-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK7: omp.loop.exit: @@ -7423,7 +7423,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined -// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -7465,35 +7465,35 @@ int bar(int n){ // CHECK7-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP55:![0-9]+]] -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP55]] +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48:![0-9]+]] +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP48]] // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP55]] +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48]] // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP55]] -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP55]] +// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP48]] +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP48]] // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK7-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP55]] -// CHECK7-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP55]] +// CHECK7-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP48]] +// CHECK7-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP48]] // CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK7-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK7-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP55]] +// CHECK7-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP48]] // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP55]] +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP48]] // CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK7-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP55]] +// CHECK7-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP48]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP55]] +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48]] // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK7-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP55]] -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP56:![0-9]+]] +// CHECK7-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48]] +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP49:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK7: omp.loop.exit: @@ -7509,7 +7509,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK7-SAME: () #[[ATTR5]] { +// CHECK7-SAME: () #[[ATTR4]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: call void @__tgt_register_requires(i64 1) // CHECK7-NEXT: ret void @@ -9669,7 +9669,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -9706,23 +9706,23 @@ int bar(int n){ // CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK17-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK17-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK17: omp.inner.for.end: // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK17: omp.loop.exit: @@ -9751,7 +9751,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -9788,28 +9788,28 @@ int bar(int n){ // CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]] -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK17-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP25]] +// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK17-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]] // CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 // CHECK17-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK17-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP25]] +// CHECK17-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK17-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK17-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK17: omp.inner.for.end: // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK17: omp.loop.exit: @@ -9844,7 +9844,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -9883,31 +9883,31 @@ int bar(int n){ // CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]] -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]] -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK17-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP28]] -// CHECK17-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP28]] +// CHECK17-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK17-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]] // CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK17-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP28]] +// CHECK17-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK17-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK17-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK17: omp.inner.for.end: // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK17: omp.loop.exit: @@ -9960,7 +9960,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -10023,59 +10023,59 @@ int bar(int n){ // CHECK17-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31:![0-9]+]] -// CHECK17-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] +// CHECK17-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK17-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK17-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 -// CHECK17-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK17-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double // CHECK17-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00 // CHECK17-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float -// CHECK17-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK17-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3 -// CHECK17-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK17-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double // CHECK17-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 // CHECK17-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK17-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK17-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 // CHECK17-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i64 0, i64 2 -// CHECK17-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP31]] +// CHECK17-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00 -// CHECK17-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP31]] +// CHECK17-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]] // CHECK17-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP20]] // CHECK17-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i64 3 -// CHECK17-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP31]] +// CHECK17-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00 -// CHECK17-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP31]] +// CHECK17-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP31]] +// CHECK17-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1 -// CHECK17-NEXT: store i64 [[ADD19]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP31]] +// CHECK17-NEXT: store i64 [[ADD19]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP31]] +// CHECK17-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i32 // CHECK17-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1 // CHECK17-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8 -// CHECK17-NEXT: store i8 [[CONV22]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP31]] +// CHECK17-NEXT: store i8 [[CONV22]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK17-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK17-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] +// CHECK17-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK17: omp.inner.for.end: // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK17: omp.loop.exit: @@ -10125,7 +10125,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -10197,42 +10197,42 @@ int bar(int n){ // CHECK17-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34:![0-9]+]] -// CHECK17-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] +// CHECK17-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK17-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 1 // CHECK17-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]] // CHECK17-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK17-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK17-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]] -// CHECK17-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK17-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK17-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK17-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK17-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK17-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP34]] +// CHECK17-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK17-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP27]] // CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i32 // CHECK17-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 1 // CHECK17-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16 -// CHECK17-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP34]] -// CHECK17-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP34]] +// CHECK17-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP27]] +// CHECK17-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP27]] // CHECK17-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i32 // CHECK17-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1 // CHECK17-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8 -// CHECK17-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP34]] +// CHECK17-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP27]] // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 -// CHECK17-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK17-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK17-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK17-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK17-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK17-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK17-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 1 -// CHECK17-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] +// CHECK17-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] // CHECK17: omp.inner.for.end: // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK17: omp.loop.exit: @@ -10286,7 +10286,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -10335,37 +10335,37 @@ int bar(int n){ // CHECK17-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37:![0-9]+]] -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP37]] +// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30:![0-9]+]] +// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK17-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]] +// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP37]] -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP37]] +// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK17-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double // CHECK17-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 -// CHECK17-NEXT: store double [[ADD4]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP37]] +// CHECK17-NEXT: store double [[ADD4]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP30]] // CHECK17-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP37]] +// CHECK17-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP30]] // CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK17-NEXT: store double [[INC]], ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP37]] +// CHECK17-NEXT: store double [[INC]], ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP30]] // CHECK17-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 // CHECK17-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]] // CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 -// CHECK17-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP37]] +// CHECK17-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP30]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]] +// CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK17-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]] -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]] +// CHECK17-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] // CHECK17: omp.inner.for.end: // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK17: omp.loop.exit: @@ -10403,7 +10403,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -10445,35 +10445,35 @@ int bar(int n){ // CHECK17-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40:![0-9]+]] -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP40]] +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]] +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]] +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP40]] -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP40]] +// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK17-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP40]] -// CHECK17-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP40]] +// CHECK17-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK17-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] // CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK17-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP40]] +// CHECK17-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP40]] +// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK17-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP40]] +// CHECK17-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]] +// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK17-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]] -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]] +// CHECK17-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] // CHECK17: omp.inner.for.end: // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK17: omp.loop.exit: @@ -10510,7 +10510,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -10547,23 +10547,23 @@ int bar(int n){ // CHECK19-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK19-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK19-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK19: omp.inner.for.end: // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK19: omp.loop.exit: @@ -10592,7 +10592,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -10629,28 +10629,28 @@ int bar(int n){ // CHECK19-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]] -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] -// CHECK19-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP26]] +// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK19-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP19]] // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 // CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK19-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP26]] +// CHECK19-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP19]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK19-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] +// CHECK19-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK19: omp.inner.for.end: // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK19: omp.loop.exit: @@ -10685,7 +10685,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -10724,31 +10724,31 @@ int bar(int n){ // CHECK19-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29:![0-9]+]] -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]] +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP29]] -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK19-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP29]] -// CHECK19-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] +// CHECK19-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK19-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP22]] // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK19-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] +// CHECK19-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP22]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK19-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]] -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] +// CHECK19-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK19: omp.inner.for.end: // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK19: omp.loop.exit: @@ -10801,7 +10801,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -10864,59 +10864,59 @@ int bar(int n){ // CHECK19-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]] -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]] +// CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]] -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK19-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK19-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK19-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double // CHECK19-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00 // CHECK19-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float -// CHECK19-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK19-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3 -// CHECK19-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK19-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double // CHECK19-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 // CHECK19-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK19-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK19-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 // CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP32]] +// CHECK19-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00 -// CHECK19-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP32]] +// CHECK19-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]] // CHECK19-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP20]] // CHECK19-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i32 3 -// CHECK19-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP32]] +// CHECK19-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00 -// CHECK19-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP32]] +// CHECK19-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK19-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1 -// CHECK19-NEXT: store i64 [[ADD19]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK19-NEXT: store i64 [[ADD19]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK19-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i32 // CHECK19-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1 // CHECK19-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8 -// CHECK19-NEXT: store i8 [[CONV22]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK19-NEXT: store i8 [[CONV22]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK19-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK19-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] +// CHECK19-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] // CHECK19: omp.inner.for.end: // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK19: omp.loop.exit: @@ -10966,7 +10966,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -11038,42 +11038,42 @@ int bar(int n){ // CHECK19-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35:![0-9]+]] -// CHECK19-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]] +// CHECK19-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK19-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 1 // CHECK19-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]] // CHECK19-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP35]] -// CHECK19-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK19-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK19-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK19-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]] -// CHECK19-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP35]] -// CHECK19-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK19-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK19-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK19-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK19-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] -// CHECK19-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP35]] +// CHECK19-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK19-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP28]] // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i32 // CHECK19-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 1 // CHECK19-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16 -// CHECK19-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP35]] -// CHECK19-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP35]] +// CHECK19-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP28]] +// CHECK19-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP28]] // CHECK19-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i32 // CHECK19-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1 // CHECK19-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8 -// CHECK19-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP35]] +// CHECK19-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP28]] // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK19-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK19-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK19-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK19-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK19-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK19-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 1 -// CHECK19-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] +// CHECK19-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] // CHECK19: omp.inner.for.end: // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK19: omp.loop.exit: @@ -11127,7 +11127,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -11176,37 +11176,37 @@ int bar(int n){ // CHECK19-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38:![0-9]+]] -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31:![0-9]+]] +// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK19-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK19-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP38]] -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double // CHECK19-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 -// CHECK19-NEXT: store double [[ADD4]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK19-NEXT: store double [[ADD4]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK19-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK19-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK19-NEXT: store double [[INC]], ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK19-NEXT: store double [[INC]], ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK19-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 // CHECK19-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]] // CHECK19-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 -// CHECK19-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP38]] +// CHECK19-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP31]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK19-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]] -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]] +// CHECK19-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] // CHECK19: omp.inner.for.end: // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK19: omp.loop.exit: @@ -11244,7 +11244,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -11286,35 +11286,35 @@ int bar(int n){ // CHECK19-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41:![0-9]+]] -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP41]] +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34:![0-9]+]] +// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41]] +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP41]] -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP41]] +// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK19-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP41]] -// CHECK19-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]] +// CHECK19-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK19-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP34]] // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK19-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]] +// CHECK19-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP34]] // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP41]] +// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK19-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP41]] +// CHECK19-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41]] +// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK19-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41]] -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]] +// CHECK19-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] // CHECK19: omp.inner.for.end: // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK19: omp.loop.exit: @@ -11351,7 +11351,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined -// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -11388,23 +11388,23 @@ int bar(int n){ // CHECK21-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK21: omp.inner.for.cond: -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] +// CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK21: omp.inner.for.body: -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK21: omp.body.continue: // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK21: omp.inner.for.inc: -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK21-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK21-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] +// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK21: omp.inner.for.end: // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK21: omp.loop.exit: @@ -11433,7 +11433,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined -// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -11470,28 +11470,28 @@ int bar(int n){ // CHECK21-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK21: omp.inner.for.cond: -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]] -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] +// CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK21: omp.inner.for.body: -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK21-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP25]] +// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK21-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]] // CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32 // CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 // CHECK21-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK21-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP25]] +// CHECK21-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK21: omp.body.continue: // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK21: omp.inner.for.inc: -// CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK21-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK21-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK21: omp.inner.for.end: // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK21: omp.loop.exit: @@ -11526,7 +11526,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined -// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -11565,31 +11565,31 @@ int bar(int n){ // CHECK21-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK21: omp.inner.for.cond: -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]] -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] +// CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK21: omp.inner.for.body: -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]] -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK21-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP28]] -// CHECK21-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP28]] +// CHECK21-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK21-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]] // CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 // CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK21-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK21-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP28]] +// CHECK21-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK21: omp.body.continue: // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK21: omp.inner.for.inc: -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK21-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] -// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK21-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK21: omp.inner.for.end: // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK21: omp.loop.exit: @@ -11642,7 +11642,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined -// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -11705,59 +11705,59 @@ int bar(int n){ // CHECK21-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK21: omp.inner.for.cond: -// CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31:![0-9]+]] -// CHECK21-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] +// CHECK21-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK21-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK21: omp.inner.for.body: -// CHECK21-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK21-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK21-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK21-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK21-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK21-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK21-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double // CHECK21-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00 // CHECK21-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float -// CHECK21-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK21-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3 -// CHECK21-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK21-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double // CHECK21-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 // CHECK21-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK21-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK21-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 // CHECK21-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP31]] +// CHECK21-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00 -// CHECK21-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP31]] +// CHECK21-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]] // CHECK21-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP20]] // CHECK21-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i64 3 -// CHECK21-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP31]] +// CHECK21-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00 -// CHECK21-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP31]] +// CHECK21-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP31]] +// CHECK21-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1 -// CHECK21-NEXT: store i64 [[ADD19]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP31]] +// CHECK21-NEXT: store i64 [[ADD19]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 -// CHECK21-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP31]] +// CHECK21-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i32 // CHECK21-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1 // CHECK21-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8 -// CHECK21-NEXT: store i8 [[CONV22]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP31]] +// CHECK21-NEXT: store i8 [[CONV22]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK21: omp.body.continue: // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK21: omp.inner.for.inc: -// CHECK21-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK21-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK21-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] +// CHECK21-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK21: omp.inner.for.end: // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK21: omp.loop.exit: @@ -11807,7 +11807,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined -// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -11879,42 +11879,42 @@ int bar(int n){ // CHECK21-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK21: omp.inner.for.cond: -// CHECK21-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34:![0-9]+]] -// CHECK21-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK21-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] +// CHECK21-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK21-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 1 // CHECK21-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]] // CHECK21-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK21: omp.inner.for.body: -// CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK21-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK21-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK21-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK21-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]] -// CHECK21-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK21-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK21-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK21-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK21-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK21-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK21-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP34]] +// CHECK21-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK21-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP27]] // CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i32 // CHECK21-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 1 // CHECK21-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16 -// CHECK21-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP34]] -// CHECK21-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP34]] +// CHECK21-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP27]] +// CHECK21-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP27]] // CHECK21-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i32 // CHECK21-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1 // CHECK21-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8 -// CHECK21-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP34]] +// CHECK21-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP27]] // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK21-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK21-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK21-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK21-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK21: omp.body.continue: // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK21: omp.inner.for.inc: -// CHECK21-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK21-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK21-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 1 -// CHECK21-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] +// CHECK21-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] // CHECK21: omp.inner.for.end: // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK21: omp.loop.exit: @@ -11976,7 +11976,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined -// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -12031,37 +12031,37 @@ int bar(int n){ // CHECK21: omp_if.then: // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK21: omp.inner.for.cond: -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37:![0-9]+]] -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP37]] +// CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30:![0-9]+]] +// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK21-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK21-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK21: omp.inner.for.body: -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]] +// CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP37]] -// CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP37]] +// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double // CHECK21-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 // CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 -// CHECK21-NEXT: store double [[ADD4]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP37]] +// CHECK21-NEXT: store double [[ADD4]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP30]] // CHECK21-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP14:%.*]] = load double, ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP37]] +// CHECK21-NEXT: [[TMP14:%.*]] = load double, ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP30]] // CHECK21-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 -// CHECK21-NEXT: store double [[INC]], ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP37]] +// CHECK21-NEXT: store double [[INC]], ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP30]] // CHECK21-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 // CHECK21-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]] // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP15]] // CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 -// CHECK21-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP37]] +// CHECK21-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP30]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK21: omp.body.continue: // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK21: omp.inner.for.inc: -// CHECK21-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]] +// CHECK21-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK21-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK21-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]] -// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]] +// CHECK21-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] // CHECK21: omp.inner.for.end: // CHECK21-NEXT: br label [[OMP_IF_END:%.*]] // CHECK21: omp_if.else: @@ -12097,7 +12097,7 @@ int bar(int n){ // CHECK21-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK21-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK21-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4 -// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP40:![0-9]+]] +// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP33:![0-9]+]] // CHECK21: omp.inner.for.end25: // CHECK21-NEXT: br label [[OMP_IF_END]] // CHECK21: omp_if.end: @@ -12137,7 +12137,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined -// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -12179,35 +12179,35 @@ int bar(int n){ // CHECK21-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK21: omp.inner.for.cond: -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42:![0-9]+]] -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35:![0-9]+]] +// CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK21: omp.inner.for.body: -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP42]] -// CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK21-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP42]] -// CHECK21-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP42]] +// CHECK21-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK21-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP35]] // CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 // CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK21-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK21-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP42]] +// CHECK21-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP35]] // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK21-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK21-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK21: omp.body.continue: // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK21: omp.inner.for.inc: -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK21-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] -// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] +// CHECK21-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] // CHECK21: omp.inner.for.end: // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK21: omp.loop.exit: @@ -12244,7 +12244,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined -// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -12281,23 +12281,23 @@ int bar(int n){ // CHECK23-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK23: omp.inner.for.cond: -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] +// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK23: omp.inner.for.body: -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK23: omp.body.continue: // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK23: omp.inner.for.inc: -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK23-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK23-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK23: omp.inner.for.end: // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK23: omp.loop.exit: @@ -12326,7 +12326,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined -// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -12363,28 +12363,28 @@ int bar(int n){ // CHECK23-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK23: omp.inner.for.cond: -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]] -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] +// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK23: omp.inner.for.body: -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] -// CHECK23-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP26]] +// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK23-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP19]] // CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 // CHECK23-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK23-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP26]] +// CHECK23-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP19]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK23: omp.body.continue: // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK23: omp.inner.for.inc: -// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] +// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK23-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] -// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] +// CHECK23-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK23: omp.inner.for.end: // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK23: omp.loop.exit: @@ -12419,7 +12419,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined -// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -12458,31 +12458,31 @@ int bar(int n){ // CHECK23-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK23: omp.inner.for.cond: -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29:![0-9]+]] -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]] +// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK23: omp.inner.for.body: -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP29]] -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK23-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP29]] -// CHECK23-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] +// CHECK23-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK23-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP22]] // CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 // CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK23-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK23-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] +// CHECK23-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP22]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK23: omp.body.continue: // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK23: omp.inner.for.inc: -// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]] +// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK23-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]] -// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] +// CHECK23-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK23: omp.inner.for.end: // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK23: omp.loop.exit: @@ -12535,7 +12535,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined -// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -12598,59 +12598,59 @@ int bar(int n){ // CHECK23-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK23: omp.inner.for.cond: -// CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]] -// CHECK23-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]] +// CHECK23-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK23-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK23-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK23: omp.inner.for.body: -// CHECK23-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK23-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]] -// CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK23-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK23-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK23-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK23-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double // CHECK23-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00 // CHECK23-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float -// CHECK23-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK23-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK23-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3 -// CHECK23-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK23-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK23-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double // CHECK23-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 // CHECK23-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK23-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK23-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK23-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 // CHECK23-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP32]] +// CHECK23-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP25]] // CHECK23-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00 -// CHECK23-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP32]] +// CHECK23-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP25]] // CHECK23-NEXT: [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]] // CHECK23-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP20]] // CHECK23-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i32 3 -// CHECK23-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP32]] +// CHECK23-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP25]] // CHECK23-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00 -// CHECK23-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP32]] +// CHECK23-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP25]] // CHECK23-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK23-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK23-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1 -// CHECK23-NEXT: store i64 [[ADD19]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK23-NEXT: store i64 [[ADD19]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK23-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 -// CHECK23-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK23-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK23-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i32 // CHECK23-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1 // CHECK23-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8 -// CHECK23-NEXT: store i8 [[CONV22]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK23-NEXT: store i8 [[CONV22]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK23: omp.body.continue: // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK23: omp.inner.for.inc: -// CHECK23-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] +// CHECK23-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK23-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK23-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] -// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] +// CHECK23-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] // CHECK23: omp.inner.for.end: // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK23: omp.loop.exit: @@ -12700,7 +12700,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined -// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -12772,42 +12772,42 @@ int bar(int n){ // CHECK23-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK23: omp.inner.for.cond: -// CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35:![0-9]+]] -// CHECK23-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]] +// CHECK23-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK23-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 1 // CHECK23-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]] // CHECK23-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK23: omp.inner.for.body: -// CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP35]] -// CHECK23-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK23-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK23-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK23-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]] -// CHECK23-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP35]] -// CHECK23-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK23-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK23-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK23-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK23-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] -// CHECK23-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP35]] +// CHECK23-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK23-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP28]] // CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i32 // CHECK23-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 1 // CHECK23-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16 -// CHECK23-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP35]] -// CHECK23-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP35]] +// CHECK23-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP28]] +// CHECK23-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP28]] // CHECK23-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i32 // CHECK23-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1 // CHECK23-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8 -// CHECK23-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP35]] +// CHECK23-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP28]] // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK23-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK23-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK23-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK23-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK23: omp.body.continue: // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK23: omp.inner.for.inc: -// CHECK23-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] +// CHECK23-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK23-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 1 -// CHECK23-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] -// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] +// CHECK23-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] // CHECK23: omp.inner.for.end: // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK23: omp.loop.exit: @@ -12869,7 +12869,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined -// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -12924,37 +12924,37 @@ int bar(int n){ // CHECK23: omp_if.then: // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK23: omp.inner.for.cond: -// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38:![0-9]+]] -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31:![0-9]+]] +// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK23-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK23-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK23: omp.inner.for.body: -// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP38]] -// CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double // CHECK23-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 // CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 -// CHECK23-NEXT: store double [[ADD4]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK23-NEXT: store double [[ADD4]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK23-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP14:%.*]] = load double, ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK23-NEXT: [[TMP14:%.*]] = load double, ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK23-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 -// CHECK23-NEXT: store double [[INC]], ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK23-NEXT: store double [[INC]], ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK23-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 // CHECK23-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]] // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP15]] // CHECK23-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 -// CHECK23-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP38]] +// CHECK23-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP31]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK23: omp.body.continue: // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK23: omp.inner.for.inc: -// CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]] +// CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK23-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK23-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]] -// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]] +// CHECK23-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] // CHECK23: omp.inner.for.end: // CHECK23-NEXT: br label [[OMP_IF_END:%.*]] // CHECK23: omp_if.else: @@ -12990,7 +12990,7 @@ int bar(int n){ // CHECK23-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK23-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK23-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4 -// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP41:![0-9]+]] +// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP34:![0-9]+]] // CHECK23: omp.inner.for.end25: // CHECK23-NEXT: br label [[OMP_IF_END]] // CHECK23: omp_if.end: @@ -13030,7 +13030,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined -// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -13072,35 +13072,35 @@ int bar(int n){ // CHECK23-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK23: omp.inner.for.cond: -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP43:![0-9]+]] -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]] +// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK23: omp.inner.for.body: -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP43]] -// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK23-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP43]] -// CHECK23-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP43]] +// CHECK23-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK23-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP36]] // CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 // CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK23-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK23-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP43]] +// CHECK23-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP36]] // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK23-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK23-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK23: omp.body.continue: // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK23: omp.inner.for.inc: -// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK23-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP43]] -// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]] +// CHECK23-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] // CHECK23: omp.inner.for.end: // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK23: omp.loop.exit: diff --git a/clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp index 88d7dd168ccd5..b4e68abe3cd72 100644 --- a/clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp @@ -4,19 +4,19 @@ #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 #ifdef CK1 template @@ -46,19 +46,19 @@ int teams_template_struct(void) { #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 #ifdef CK2 template diff --git a/clang/test/OpenMP/target_teams_distribute_simd_depend_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_simd_depend_codegen.cpp index 64390bde1c095..ffe85c1624b56 100644 --- a/clang/test/OpenMP/target_teams_distribute_simd_depend_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_simd_depend_codegen.cpp @@ -1,46 +1,46 @@ // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP50 --check-prefix OMP50-64 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP45 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP50 --check-prefix OMP50-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP45 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP50 --check-prefix OMP50-64 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP50 --check-prefix OMP50-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP50 --check-prefix OMP50-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP50 --check-prefix OMP50-32 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP50 --check-prefix OMP50-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP50 --check-prefix OMP50-32 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP45 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP45 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 --check-prefix OMP45 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP45 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP45 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 --check-prefix OMP45 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s // SIMD-ONLY1-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_codegen.cpp index 83993fb965de7..aebbe0e695aa7 100644 --- a/clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_codegen.cpp @@ -4,19 +4,19 @@ #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 #ifdef CK1 template @@ -55,19 +55,19 @@ int teams_template_struct(void) { #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 #ifdef CK2 template diff --git a/clang/test/OpenMP/target_teams_distribute_simd_linear_messages.cpp b/clang/test/OpenMP/target_teams_distribute_simd_linear_messages.cpp index 11c24cbd7c736..9a875a4d544d4 100644 --- a/clang/test/OpenMP/target_teams_distribute_simd_linear_messages.cpp +++ b/clang/test/OpenMP/target_teams_distribute_simd_linear_messages.cpp @@ -1,6 +1,8 @@ // RUN: %clang_cc1 -verify -fopenmp %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp -fopenmp-version=52 -DOMP52 %s -Wuninitialized // RUN: %clang_cc1 -verify -fopenmp-simd %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp-simd -fopenmp-version=52 -DOMP52 %s -Wuninitialized typedef void **omp_allocator_handle_t; extern const omp_allocator_handle_t omp_default_mem_alloc; @@ -13,8 +15,8 @@ extern const omp_allocator_handle_t omp_pteam_mem_alloc; extern const omp_allocator_handle_t omp_thread_mem_alloc; void xxx(int argc) { - int i, step; // expected-note {{initialize the variable 'step' to silence this warning}} -#pragma omp target teams distribute simd linear(i : step) // expected-warning {{variable 'step' is uninitialized when used here}} + int i, step_sz; // expected-note {{initialize the variable 'step_sz' to silence this warning}} +#pragma omp target teams distribute simd linear(i : step_sz) // expected-warning {{variable 'step_sz' is uninitialized when used here}} for (i = 0; i < 10; ++i) ; } diff --git a/clang/test/OpenMP/target_teams_distribute_simd_map_messages.cpp b/clang/test/OpenMP/target_teams_distribute_simd_map_messages.cpp index 7ccc583533cd0..e80d99ad5647f 100644 --- a/clang/test/OpenMP/target_teams_distribute_simd_map_messages.cpp +++ b/clang/test/OpenMP/target_teams_distribute_simd_map_messages.cpp @@ -1,10 +1,12 @@ // RUN: %clang_cc1 -verify=expected,lt50,lt51 -fopenmp -fno-openmp-extensions -fopenmp-version=45 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,lt51 -fopenmp -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,ge51 -fopenmp -fno-openmp-extensions -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized +// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp52 -fopenmp -fno-openmp-extensions -fopenmp-version=52 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,lt50,lt51 -fopenmp-simd -fno-openmp-extensions -fopenmp-version=45 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,lt51 -fopenmp-simd -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized // RUN: %clang_cc1 -verify=expected,ge50,ge51 -fopenmp-simd -fno-openmp-extensions -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized +// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp52 -fopenmp-simd -fno-openmp-extensions -fopenmp-version=52 -ferror-limit 100 %s -Wno-openmp-mapping -Wuninitialized void foo() { } @@ -189,6 +191,8 @@ T tmain(T argc) { for (i = 0; i < argc; ++i) foo(); #pragma omp target teams distribute simd map(always, tofrom: always, tofrom, x) for (i = 0; i < argc; ++i) foo(); +#pragma omp target teams distribute simd map(always tofrom: x) // omp52-error {{missing ',' after map type modifier}} + for (i = 0; i < argc; ++i) foo(); #pragma omp target teams distribute simd map(tofrom j) // expected-error {{expected ',' or ')' in 'map' clause}} for (i = 0; i < argc; ++i) foo(); diff --git a/clang/test/OpenMP/target_teams_generic_loop_collapse_codegen.cpp b/clang/test/OpenMP/target_teams_generic_loop_collapse_codegen.cpp index 3201902e8602c..558d9ab15c940 100644 --- a/clang/test/OpenMP/target_teams_generic_loop_collapse_codegen.cpp +++ b/clang/test/OpenMP/target_teams_generic_loop_collapse_codegen.cpp @@ -4,19 +4,19 @@ #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -47,19 +47,19 @@ int teams_template_struct(void) { #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template diff --git a/clang/test/OpenMP/target_teams_generic_loop_depend_codegen.cpp b/clang/test/OpenMP/target_teams_generic_loop_depend_codegen.cpp index f9a33278dfc50..a712cd7d33b88 100644 --- a/clang/test/OpenMP/target_teams_generic_loop_depend_codegen.cpp +++ b/clang/test/OpenMP/target_teams_generic_loop_depend_codegen.cpp @@ -1,37 +1,37 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ // Test host codegen. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s // expected-no-diagnostics #ifndef HEADER diff --git a/clang/test/OpenMP/target_teams_map_messages.cpp b/clang/test/OpenMP/target_teams_map_messages.cpp index 9cbd2a20ec135..9da3e752f635b 100644 --- a/clang/test/OpenMP/target_teams_map_messages.cpp +++ b/clang/test/OpenMP/target_teams_map_messages.cpp @@ -1,11 +1,11 @@ -// RUN: %clang_cc1 -verify=expected,ge45,ge50,lt51 -fopenmp -fno-openmp-extensions -ferror-limit 200 %s -Wno-openmp-mapping -Wuninitialized -// RUN: %clang_cc1 -verify=expected,lt45,lt50,lt51 -fopenmp -fno-openmp-extensions -fopenmp-version=40 -ferror-limit 200 %s -Wno-openmp-mapping -Wuninitialized -// RUN: %clang_cc1 -verify=expected,ge45,lt50,lt51 -fopenmp -fno-openmp-extensions -fopenmp-version=45 -ferror-limit 200 %s -Wno-openmp-mapping -Wuninitialized -// RUN: %clang_cc1 -verify=expected,ge45,ge50,lt51 -fopenmp -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 200 %s -Wno-openmp-mapping -Wuninitialized -// RUN: %clang_cc1 -verify=expected,ge45,ge50,ge51 -fopenmp -fno-openmp-extensions -ferror-limit 200 %s -Wno-openmp-mapping -Wuninitialized - -// RUN: %clang_cc1 -verify=expected,ge45,ge50,lt51 -fopenmp-simd -fno-openmp-extensions -ferror-limit 200 %s -Wno-openmp-mapping -Wuninitialized -// RUN: %clang_cc1 -DCCODE -verify=expected,ge45,ge50,lt51 -fopenmp -fno-openmp-extensions -ferror-limit 200 -x c %s -Wno-openmp-mapping -Wuninitialized +// RUN: %clang_cc1 -verify=expected,ge45,ge50,lt51 -fopenmp -fno-openmp-extensions -ferror-limit 200 %s -Wno-openmp-mapping -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,lt45,lt50,lt51 -fopenmp -fno-openmp-extensions -fopenmp-version=40 -ferror-limit 200 %s -Wno-openmp-mapping -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge45,lt50,lt51 -fopenmp -fno-openmp-extensions -fopenmp-version=45 -ferror-limit 200 %s -Wno-openmp-mapping -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge45,ge50,lt51 -fopenmp -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 200 %s -Wno-openmp-mapping -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge45,ge50,ge51 -fopenmp -fno-openmp-extensions -ferror-limit 200 %s -Wno-openmp-mapping -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge45,ge50,lt51 -fopenmp-simd -fno-openmp-extensions -ferror-limit 200 %s -Wno-openmp-mapping -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -DCCODE -verify=expected,ge45,ge50,lt51 -fopenmp -fno-openmp-extensions -ferror-limit 200 -x c %s -Wno-openmp-mapping -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge45,ge50,lt51,omp52 -fopenmp -fno-openmp-extensions -fopenmp-version=52 -ferror-limit 200 %s -Wno-openmp-mapping -Wuninitialized #ifdef CCODE void foo(int arg) { const int n = 0; @@ -85,6 +85,8 @@ struct SA { {} #pragma omp target teams map(always, tofrom: c,f[:]) // expected-error {{section length is unspecified and cannot be inferred because subscripted value is not an array}} {} + #pragma omp target teams map(always tofrom: c) // omp52-error {{missing ',' after map type modifier}} + {} return; } }; diff --git a/clang/test/OpenMP/target_update_codegen.cpp b/clang/test/OpenMP/target_update_codegen.cpp index 7e9e4d8be0831..b577be3c1b496 100644 --- a/clang/test/OpenMP/target_update_codegen.cpp +++ b/clang/test/OpenMP/target_update_codegen.cpp @@ -3,19 +3,19 @@ #define HEADER ///==========================================================================/// -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 // RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 // RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} #ifdef CK1 @@ -160,19 +160,19 @@ void foo(int arg) { // CK1: } #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-64 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-64 // RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-64 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-64 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-32 // RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-32 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -DCK2 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -DCK2 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s // SIMD-ONLY1-NOT: {{__kmpc|__tgt}} #ifdef CK2 @@ -234,19 +234,19 @@ int bar(int arg){ // CK2: %{{.+}} = add nsw i32 %{{[^,]+}}, 1 #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-64 +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-64 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-64 -// RUN: %clang_cc1 -DCK3 -verify -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-64 +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-32 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-32 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s -// RUN: %clang_cc1 -DCK3 -verify -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY2 %s // SIMD-ONLY2-NOT: {{__kmpc|__tgt}} #ifdef CK3 @@ -260,38 +260,38 @@ void no_target_devices(int arg) { } #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK4 --check-prefix CK4-64 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK4 --check-prefix CK4-64 // RUN: %clang_cc1 -DCK4 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK4 --check-prefix CK4-64 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK4 --check-prefix CK4-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK4 --check-prefix CK4-64 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK4 --check-prefix CK4-32 // RUN: %clang_cc1 -DCK4 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK4 --check-prefix CK4-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK4 --check-prefix CK4-32 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY3 %s +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY3 %s // RUN: %clang_cc1 -DCK4 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY3 %s -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY3 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY3 %s +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY3 %s // RUN: %clang_cc1 -DCK4 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY3 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY3 %s // SIMD-ONLY3-NOT: {{__kmpc|__tgt}} -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCK4 --check-prefix TCK4-64 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCK4 --check-prefix TCK4-64 // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCK4 --check-prefix TCK4-64 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCK4 --check-prefix TCK4-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCK4 --check-prefix TCK4-64 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCK4 --check-prefix TCK4-32 // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCK4 --check-prefix TCK4-32 +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix TCK4 --check-prefix TCK4-32 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY4 %s +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY4 %s // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY4 %s -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY4 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY4 %s +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY4 %s // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY4 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY4 %s // SIMD-ONLY4-NOT: {{__kmpc|__tgt}} #ifdef CK4 @@ -306,19 +306,19 @@ void device_side_scan(int arg) { } #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK5 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK5 --check-prefix CK5-64 +// RUN: %clang_cc1 -DCK5 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK5 --check-prefix CK5-64 // RUN: %clang_cc1 -DCK5 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK5 --check-prefix CK5-64 -// RUN: %clang_cc1 -DCK5 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK5 --check-prefix CK5-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK5 --check-prefix CK5-64 +// RUN: %clang_cc1 -DCK5 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK5 --check-prefix CK5-32 // RUN: %clang_cc1 -DCK5 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK5 --check-prefix CK5-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK5 --check-prefix CK5-32 -// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK5 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK5 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK5 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK5 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} #ifdef CK5 @@ -346,19 +346,19 @@ void lvalue(int *B, int l, int e) { #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK6 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK6 --check-prefix CK6-64 +// RUN: %clang_cc1 -DCK6 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK6 --check-prefix CK6-64 // RUN: %clang_cc1 -DCK6 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK6 --check-prefix CK6-64 -// RUN: %clang_cc1 -DCK6 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK6 --check-prefix CK6-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK6 --check-prefix CK6-64 +// RUN: %clang_cc1 -DCK6 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK6 --check-prefix CK6-32 // RUN: %clang_cc1 -DCK6 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK6 --check-prefix CK6-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK6 --check-prefix CK6-32 -// RUN: %clang_cc1 -DCK6 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK6 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK6 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -DCK6 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK6 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK6 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} #ifdef CK6 @@ -391,19 +391,19 @@ void lvalue(int *B, int l, int e) { #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK7 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK7 --check-prefix CK7-64 +// RUN: %clang_cc1 -DCK7 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK7 --check-prefix CK7-64 // RUN: %clang_cc1 -DCK7 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK7 --check-prefix CK7-64 -// RUN: %clang_cc1 -DCK7 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK7 --check-prefix CK7-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK7 --check-prefix CK7-64 +// RUN: %clang_cc1 -DCK7 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK7 --check-prefix CK7-32 // RUN: %clang_cc1 -DCK7 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK7 --check-prefix CK7-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK7 --check-prefix CK7-32 -// RUN: %clang_cc1 -DCK7 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK7 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK7 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -DCK7 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK7 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK7 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} #ifdef CK7 @@ -440,19 +440,19 @@ void lvalue(int *B, int l, int e) { #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK8 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK8 --check-prefix CK8-64 +// RUN: %clang_cc1 -DCK8 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK8 --check-prefix CK8-64 // RUN: %clang_cc1 -DCK8 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK8 --check-prefix CK8-64 -// RUN: %clang_cc1 -DCK8 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK8 --check-prefix CK8-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK8 --check-prefix CK8-64 +// RUN: %clang_cc1 -DCK8 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK8 --check-prefix CK8-32 // RUN: %clang_cc1 -DCK8 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK8 --check-prefix CK8-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK8 --check-prefix CK8-32 -// RUN: %clang_cc1 -DCK8 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK8 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK8 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -DCK8 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK8 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK8 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} #ifdef CK8 @@ -488,19 +488,19 @@ void lvalue(int **B, int l, int e) { #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK9 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK9 --check-prefix CK9-64 +// RUN: %clang_cc1 -DCK9 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK9 --check-prefix CK9-64 // RUN: %clang_cc1 -DCK9 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK9 --check-prefix CK9-64 -// RUN: %clang_cc1 -DCK9 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK9 --check-prefix CK9-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK9 --check-prefix CK9-64 +// RUN: %clang_cc1 -DCK9 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK9 --check-prefix CK9-32 // RUN: %clang_cc1 -DCK9 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK9 --check-prefix CK9-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK9 --check-prefix CK9-32 -// RUN: %clang_cc1 -DCK9 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK9 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK9 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -DCK9 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK9 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK9 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} #ifdef CK9 @@ -536,19 +536,19 @@ void lvalue(struct S *s, int l, int e) { #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK10 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK10 --check-prefix CK10-64 +// RUN: %clang_cc1 -DCK10 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK10 --check-prefix CK10-64 // RUN: %clang_cc1 -DCK10 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK10 --check-prefix CK10-64 -// RUN: %clang_cc1 -DCK10 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK10 --check-prefix CK10-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK10 --check-prefix CK10-64 +// RUN: %clang_cc1 -DCK10 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK10 --check-prefix CK10-32 // RUN: %clang_cc1 -DCK10 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK10 --check-prefix CK10-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK10 --check-prefix CK10-32 -// RUN: %clang_cc1 -DCK10 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK10 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK10 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -DCK10 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK10 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK10 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} #ifdef CK10 @@ -584,19 +584,19 @@ void lvalue(struct S *s, int l, int e) { #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK11 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK11 --check-prefix CK11-64 +// RUN: %clang_cc1 -DCK11 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK11 --check-prefix CK11-64 // RUN: %clang_cc1 -DCK11 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK11 --check-prefix CK11-64 -// RUN: %clang_cc1 -DCK11 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK11 --check-prefix CK11-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK11 --check-prefix CK11-64 +// RUN: %clang_cc1 -DCK11 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK11 --check-prefix CK11-32 // RUN: %clang_cc1 -DCK11 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK11 --check-prefix CK11-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK11 --check-prefix CK11-32 -// RUN: %clang_cc1 -DCK11 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK11 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK11 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -DCK11 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK11 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK11 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} #ifdef CK11 @@ -632,19 +632,19 @@ void lvalue(struct S *s, int l, int e) { #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK12 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK12 --check-prefix CK12-64 +// RUN: %clang_cc1 -DCK12 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK12 --check-prefix CK12-64 // RUN: %clang_cc1 -DCK12 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK12 --check-prefix CK12-64 -// RUN: %clang_cc1 -DCK12 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK12 --check-prefix CK12-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK12 --check-prefix CK12-64 +// RUN: %clang_cc1 -DCK12 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK12 --check-prefix CK12-32 // RUN: %clang_cc1 -DCK12 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK12 --check-prefix CK12-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK12 --check-prefix CK12-32 -// RUN: %clang_cc1 -DCK12 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK12 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK12 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -DCK12 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK12 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK12 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} #ifdef CK12 @@ -688,19 +688,19 @@ void lvalue(struct S *s, int l, int e) { #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK13 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK13 --check-prefix CK13-64 +// RUN: %clang_cc1 -DCK13 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK13 --check-prefix CK13-64 // RUN: %clang_cc1 -DCK13 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK13 --check-prefix CK13-64 -// RUN: %clang_cc1 -DCK13 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK13 --check-prefix CK13-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK13 --check-prefix CK13-64 +// RUN: %clang_cc1 -DCK13 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK13 --check-prefix CK13-32 // RUN: %clang_cc1 -DCK13 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK13 --check-prefix CK13-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK13 --check-prefix CK13-32 -// RUN: %clang_cc1 -DCK13 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK13 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK13 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -DCK13 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK13 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK13 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} #ifdef CK13 @@ -733,19 +733,19 @@ void lvalue(int **BB, int a, int b) { #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK14 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK14 --check-prefix CK14-64 +// RUN: %clang_cc1 -DCK14 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK14 --check-prefix CK14-64 // RUN: %clang_cc1 -DCK14 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK14 --check-prefix CK14-64 -// RUN: %clang_cc1 -DCK14 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK14 --check-prefix CK14-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK14 --check-prefix CK14-64 +// RUN: %clang_cc1 -DCK14 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK14 --check-prefix CK14-32 // RUN: %clang_cc1 -DCK14 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK14 --check-prefix CK14-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK14 --check-prefix CK14-32 -// RUN: %clang_cc1 -DCK14 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK14 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK14 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -DCK14 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK14 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK14 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} #ifdef CK14 @@ -801,19 +801,19 @@ void lvalue_member(SSA *sap) { #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK15 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK15 --check-prefix CK15-64 +// RUN: %clang_cc1 -DCK15 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK15 --check-prefix CK15-64 // RUN: %clang_cc1 -DCK15 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK15 --check-prefix CK15-64 -// RUN: %clang_cc1 -DCK15 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK15 --check-prefix CK15-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK15 --check-prefix CK15-64 +// RUN: %clang_cc1 -DCK15 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK15 --check-prefix CK15-32 // RUN: %clang_cc1 -DCK15 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK15 --check-prefix CK15-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK15 --check-prefix CK15-32 -// RUN: %clang_cc1 -DCK15 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK15 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK15 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -DCK15 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK15 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK15 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} #ifdef CK15 @@ -859,19 +859,19 @@ void lvalue_member(SSA *sap) { #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK16 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK16 --check-prefix CK16-64 +// RUN: %clang_cc1 -DCK16 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK16 --check-prefix CK16-64 // RUN: %clang_cc1 -DCK16 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK16 --check-prefix CK16-64 -// RUN: %clang_cc1 -DCK16 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK16 --check-prefix CK16-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK16 --check-prefix CK16-64 +// RUN: %clang_cc1 -DCK16 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK16 --check-prefix CK16-32 // RUN: %clang_cc1 -DCK16 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK16 --check-prefix CK16-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK16 --check-prefix CK16-32 -// RUN: %clang_cc1 -DCK16 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK16 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK16 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -DCK16 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK16 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK16 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} #ifdef CK16 @@ -902,19 +902,19 @@ void lvalue_find_base(float *f, int *i) { #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK17 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK17 --check-prefix CK17-64 +// RUN: %clang_cc1 -DCK17 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK17 --check-prefix CK17-64 // RUN: %clang_cc1 -DCK17 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK17 --check-prefix CK17-64 -// RUN: %clang_cc1 -DCK17 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK17 --check-prefix CK17-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK17 --check-prefix CK17-64 +// RUN: %clang_cc1 -DCK17 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK17 --check-prefix CK17-32 // RUN: %clang_cc1 -DCK17 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK17 --check-prefix CK17-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK17 --check-prefix CK17-32 -// RUN: %clang_cc1 -DCK17 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK17 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK17 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -DCK17 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK17 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK17 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} #ifdef CK17 @@ -958,19 +958,19 @@ void lvalue_find_base(float **f, SSA *sa) { #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK18 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK18 --check-prefix CK18-64 +// RUN: %clang_cc1 -DCK18 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK18 --check-prefix CK18-64 // RUN: %clang_cc1 -DCK18 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK18 --check-prefix CK18-64 -// RUN: %clang_cc1 -DCK18 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK18 --check-prefix CK18-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK18 --check-prefix CK18-64 +// RUN: %clang_cc1 -DCK18 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK18 --check-prefix CK18-32 // RUN: %clang_cc1 -DCK18 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK18 --check-prefix CK18-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK18 --check-prefix CK18-32 -// RUN: %clang_cc1 -DCK18 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -DCK18 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY18 %s // RUN: %clang_cc1 -DCK18 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY18 %s -// RUN: %clang_cc1 -DCK18 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -DCK18 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY18 %s // RUN: %clang_cc1 -DCK18 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY18 %s // SIMD-ONLY18-NOT: {{__kmpc|__tgt}} #ifdef CK18 @@ -1027,19 +1027,19 @@ void array_shaping(float *f, int sa) { #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK19 -verify -fopenmp -fopenmp-version=51 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK19 --check-prefix CK19-64 +// RUN: %clang_cc1 -DCK19 -verify -Wno-vla -fopenmp -fopenmp-version=51 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK19 --check-prefix CK19-64 // RUN: %clang_cc1 -DCK19 -fopenmp -fopenmp-version=51 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK19 --check-prefix CK19-64 -// RUN: %clang_cc1 -DCK19 -verify -fopenmp -fopenmp-version=51 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK19 --check-prefix CK19-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK19 --check-prefix CK19-64 +// RUN: %clang_cc1 -DCK19 -verify -Wno-vla -fopenmp -fopenmp-version=51 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK19 --check-prefix CK19-32 // RUN: %clang_cc1 -DCK19 -fopenmp -fopenmp-version=51 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK19 --check-prefix CK19-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK19 --check-prefix CK19-32 -// RUN: %clang_cc1 -DCK19 -verify -fopenmp-simd -fopenmp-version=51 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK19 -verify -Wno-vla -fopenmp-simd -fopenmp-version=51 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK19 -fopenmp-simd -fopenmp-version=51 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=51 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -DCK19 -verify -fopenmp-version=51 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=51 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK19 -verify -Wno-vla -fopenmp-version=51 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DCK19 -fopenmp-simd -fopenmp-version=51 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=51 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=51 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} #ifdef CK19 @@ -1087,19 +1087,19 @@ void check_present(int arg) { #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK20 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK20 --check-prefix CK20-64 +// RUN: %clang_cc1 -DCK20 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK20 --check-prefix CK20-64 // RUN: %clang_cc1 -DCK20 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK20 --check-prefix CK20-64 -// RUN: %clang_cc1 -DCK20 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK20 --check-prefix CK20-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK20 --check-prefix CK20-64 +// RUN: %clang_cc1 -DCK20 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK20 --check-prefix CK20-32 // RUN: %clang_cc1 -DCK20 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK20 --check-prefix CK20-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK20 --check-prefix CK20-32 -// RUN: %clang_cc1 -DCK20 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY19 %s +// RUN: %clang_cc1 -DCK20 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY19 %s // RUN: %clang_cc1 -DCK20 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY19 %s -// RUN: %clang_cc1 -DCK20 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY19 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY19 %s +// RUN: %clang_cc1 -DCK20 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY19 %s // RUN: %clang_cc1 -DCK20 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY19 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY19 %s // SIMD-ONLY19-NOT: {{__kmpc|__tgt}} #ifdef CK20 @@ -1158,19 +1158,19 @@ void foo(int arg) { #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK21 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK21 --check-prefix CK21-64 +// RUN: %clang_cc1 -DCK21 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK21 --check-prefix CK21-64 // RUN: %clang_cc1 -DCK21 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK21 --check-prefix CK21-64 -// RUN: %clang_cc1 -DCK21 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK21 --check-prefix CK21-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK21 --check-prefix CK21-64 +// RUN: %clang_cc1 -DCK21 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK21 --check-prefix CK21-32 // RUN: %clang_cc1 -DCK21 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK21 --check-prefix CK21-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK21 --check-prefix CK21-32 -// RUN: %clang_cc1 -DCK21 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY19 %s +// RUN: %clang_cc1 -DCK21 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY19 %s // RUN: %clang_cc1 -DCK21 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY19 %s -// RUN: %clang_cc1 -DCK21 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY19 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY19 %s +// RUN: %clang_cc1 -DCK21 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY19 %s // RUN: %clang_cc1 -DCK21 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY19 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY19 %s // SIMD-ONLY19-NOT: {{__kmpc|__tgt}} #ifdef CK21 @@ -1237,19 +1237,19 @@ void bar() { #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK22 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK22 --check-prefix CK22-64 +// RUN: %clang_cc1 -DCK22 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK22 --check-prefix CK22-64 // RUN: %clang_cc1 -DCK22 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK22 --check-prefix CK22-64 -// RUN: %clang_cc1 -DCK22 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK22 --check-prefix CK22-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK22 --check-prefix CK22-64 +// RUN: %clang_cc1 -DCK22 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK22 --check-prefix CK22-32 // RUN: %clang_cc1 -DCK22 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK22 --check-prefix CK22-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK22 --check-prefix CK22-32 -// RUN: %clang_cc1 -DCK22 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY19 %s +// RUN: %clang_cc1 -DCK22 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY19 %s // RUN: %clang_cc1 -DCK22 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY19 %s -// RUN: %clang_cc1 -DCK22 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY19 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY19 %s +// RUN: %clang_cc1 -DCK22 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY19 %s // RUN: %clang_cc1 -DCK22 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY19 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY19 %s // SIMD-ONLY19-NOT: {{__kmpc|__tgt}} #ifdef CK22 @@ -1312,19 +1312,19 @@ void bar() { #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK23 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK23 --check-prefix CK23-64 +// RUN: %clang_cc1 -DCK23 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK23 --check-prefix CK23-64 // RUN: %clang_cc1 -DCK23 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK23 --check-prefix CK23-64 -// RUN: %clang_cc1 -DCK23 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK23 --check-prefix CK23-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK23 --check-prefix CK23-64 +// RUN: %clang_cc1 -DCK23 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK23 --check-prefix CK23-32 // RUN: %clang_cc1 -DCK23 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK23 --check-prefix CK23-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK23 --check-prefix CK23-32 -// RUN: %clang_cc1 -DCK23 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY19 %s +// RUN: %clang_cc1 -DCK23 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY19 %s // RUN: %clang_cc1 -DCK23 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY19 %s -// RUN: %clang_cc1 -DCK23 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY19 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY19 %s +// RUN: %clang_cc1 -DCK23 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY19 %s // RUN: %clang_cc1 -DCK23 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY19 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY19 %s // SIMD-ONLY19-NOT: {{__kmpc|__tgt}} #ifdef CK23 @@ -1386,19 +1386,19 @@ void foo(int arg) { #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK24 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK24 --check-prefix CK24-64 +// RUN: %clang_cc1 -DCK24 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK24 --check-prefix CK24-64 // RUN: %clang_cc1 -DCK24 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK24 --check-prefix CK24-64 -// RUN: %clang_cc1 -DCK24 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK24 --check-prefix CK24-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK24 --check-prefix CK24-64 +// RUN: %clang_cc1 -DCK24 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK24 --check-prefix CK24-32 // RUN: %clang_cc1 -DCK24 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK24 --check-prefix CK24-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK24 --check-prefix CK24-32 -// RUN: %clang_cc1 -DCK24 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY19 %s +// RUN: %clang_cc1 -DCK24 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY19 %s // RUN: %clang_cc1 -DCK24 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY19 %s -// RUN: %clang_cc1 -DCK24 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY19 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY19 %s +// RUN: %clang_cc1 -DCK24 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY19 %s // RUN: %clang_cc1 -DCK24 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY19 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY19 %s // SIMD-ONLY19-NOT: {{__kmpc|__tgt}} #ifdef CK24 @@ -1460,19 +1460,19 @@ void foo(int arg) { } #endif ///==========================================================================/// -// RUN: %clang_cc1 -DCK25 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK25 --check-prefix CK25-64 +// RUN: %clang_cc1 -DCK25 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK25 --check-prefix CK25-64 // RUN: %clang_cc1 -DCK25 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK25 --check-prefix CK25-64 -// RUN: %clang_cc1 -DCK25 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK25 --check-prefix CK25-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK25 --check-prefix CK25-64 +// RUN: %clang_cc1 -DCK25 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK25 --check-prefix CK25-32 // RUN: %clang_cc1 -DCK25 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK25 --check-prefix CK25-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK25 --check-prefix CK25-32 -// RUN: %clang_cc1 -DCK25 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY19 %s +// RUN: %clang_cc1 -DCK25 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY19 %s // RUN: %clang_cc1 -DCK25 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY19 %s -// RUN: %clang_cc1 -DCK25 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY19 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY19 %s +// RUN: %clang_cc1 -DCK25 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY19 %s // RUN: %clang_cc1 -DCK25 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY19 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY19 %s // SIMD-ONLY19-NOT: {{__kmpc|__tgt}} #ifdef CK25 diff --git a/clang/test/OpenMP/target_update_depend_codegen.cpp b/clang/test/OpenMP/target_update_depend_codegen.cpp index a19ff8fe3acc8..cfb8b286cc648 100644 --- a/clang/test/OpenMP/target_update_depend_codegen.cpp +++ b/clang/test/OpenMP/target_update_depend_codegen.cpp @@ -1,16 +1,16 @@ -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64 +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 +// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/task_ast_print.cpp b/clang/test/OpenMP/task_ast_print.cpp index 8615eebed7181..79f56b0362f1e 100644 --- a/clang/test/OpenMP/task_ast_print.cpp +++ b/clang/test/OpenMP/task_ast_print.cpp @@ -1,10 +1,10 @@ -// RUN: %clang_cc1 -verify -fopenmp -ast-print %s | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -ast-print %s | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print | FileCheck %s +// RUN: %clang_cc1 -fopenmp -std=c++11 -include-pch %t -fsyntax-only -verify -Wno-vla %s -ast-print | FileCheck %s -// RUN: %clang_cc1 -verify -fopenmp-simd -ast-print %s | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -ast-print %s | FileCheck %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print | FileCheck %s +// RUN: %clang_cc1 -fopenmp-simd -std=c++11 -include-pch %t -fsyntax-only -verify -Wno-vla %s -ast-print | FileCheck %s // expected-no-diagnostics #ifndef HEADER diff --git a/clang/test/OpenMP/task_codegen.cpp b/clang/test/OpenMP/task_codegen.cpp index d6e9e2e96c517..5a4dd22ccdbf7 100644 --- a/clang/test/OpenMP/task_codegen.cpp +++ b/clang/test/OpenMP/task_codegen.cpp @@ -1,43 +1,43 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -fopenmp-version=50 -x c++ -emit-llvm %s -o - -DUNTIEDRT | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp -fopenmp-version=50 -x c++ -emit-llvm %s -o - -DUNTIEDRT | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ \ +// RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp -x c++ \ // RUN: -fopenmp-version=51 -emit-llvm %s -o - -DUNTIEDRT -DOMP51 \ // RUN: | FileCheck %s --check-prefix=CHECK1-51 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -DUNTIEDRT -// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 // RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -x c++ -triple \ // RUN: x86_64-apple-darwin10 -emit-pch -o %t %s -DUNTIEDRT -DOMP51 // RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -x c++ -triple \ -// RUN: x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - \ +// RUN: x86_64-apple-darwin10 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - \ // RUN: -DOMP51 | FileCheck %s --check-prefix=CHECK2-51 -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -fopenmp-version=50 -fopenmp-enable-irbuilder -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp -fopenmp-version=50 -fopenmp-enable-irbuilder -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-enable-irbuilder -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-enable-irbuilder -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-enable-irbuilder -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp \ +// RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp \ // RUN: -fopenmp-version=51 -fopenmp-enable-irbuilder -x c++ -emit-llvm \ // RUN: %s -o - -DOMP51 | FileCheck %s --check-prefix=CHECK3-51 // RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -fopenmp-enable-irbuilder \ // RUN: -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -fopenmp-enable-irbuilder \ -// RUN: -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s \ +// RUN: -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify -Wno-vla %s \ // RUN: -emit-llvm -o - -DOMP51 | FileCheck %s --check-prefix=CHECK4-51 -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd \ +// RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp-simd \ // RUN: -fopenmp-version=51 -x c++ -emit-llvm %s -o - -DOMP51 \ // RUN: | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=51 -x c++ \ // RUN: -triple x86_64-apple-darwin10 -emit-pch -o %t %s -DOMP51 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=51 -x c++ \ -// RUN: -triple x86_64-apple-darwin10 -include-pch %t -verify %s \ +// RUN: -triple x86_64-apple-darwin10 -include-pch %t -verify -Wno-vla %s \ // RUN: -emit-llvm -o - -DOMP51 | FileCheck %s \ // RUN: --implicit-check-not="{{__kmpc|__tgt}}" diff --git a/clang/test/OpenMP/task_firstprivate_codegen.cpp b/clang/test/OpenMP/task_firstprivate_codegen.cpp index 5f0828112164f..4b1def869be3d 100644 --- a/clang/test/OpenMP/task_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/task_firstprivate_codegen.cpp @@ -1,16 +1,16 @@ -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics #ifndef ARRAY diff --git a/clang/test/OpenMP/task_in_reduction_codegen.cpp b/clang/test/OpenMP/task_in_reduction_codegen.cpp index 33c29dc9941c7..41e6eaa1d6885 100644 --- a/clang/test/OpenMP/task_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/task_in_reduction_codegen.cpp @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER diff --git a/clang/test/OpenMP/task_private_codegen.cpp b/clang/test/OpenMP/task_private_codegen.cpp index 0dc04b79d91f7..28ee182da543c 100644 --- a/clang/test/OpenMP/task_private_codegen.cpp +++ b/clang/test/OpenMP/task_private_codegen.cpp @@ -1,16 +1,16 @@ -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/taskgroup_task_reduction_codegen.cpp b/clang/test/OpenMP/taskgroup_task_reduction_codegen.cpp index f4f840d124ab2..1e20171f9e073 100644 --- a/clang/test/OpenMP/taskgroup_task_reduction_codegen.cpp +++ b/clang/test/OpenMP/taskgroup_task_reduction_codegen.cpp @@ -1,12 +1,12 @@ -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -fopenmp -x c++ %s -verify -debug-info-kind=limited -emit-llvm -o - -triple x86_64-apple-darwin10 | FileCheck %s --check-prefix=CHECK --check-prefix=DEBUG +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -fopenmp -x c++ %s -verify -Wno-vla -debug-info-kind=limited -emit-llvm -o - -triple x86_64-apple-darwin10 | FileCheck %s --check-prefix=CHECK --check-prefix=DEBUG -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ %s -verify -debug-info-kind=limited -emit-llvm -o - -triple x86_64-apple-darwin10 | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ %s -verify -Wno-vla -debug-info-kind=limited -emit-llvm -o - -triple x86_64-apple-darwin10 | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics #ifndef HEADER diff --git a/clang/test/OpenMP/taskloop_firstprivate_codegen.cpp b/clang/test/OpenMP/taskloop_firstprivate_codegen.cpp index a67b74de843d0..da97a03893ad2 100644 --- a/clang/test/OpenMP/taskloop_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/taskloop_firstprivate_codegen.cpp @@ -1,16 +1,16 @@ -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/taskloop_in_reduction_codegen.cpp b/clang/test/OpenMP/taskloop_in_reduction_codegen.cpp index a2cb0ac170d9f..73ca0a7a4ca9c 100644 --- a/clang/test/OpenMP/taskloop_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/taskloop_in_reduction_codegen.cpp @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER diff --git a/clang/test/OpenMP/taskloop_lastprivate_codegen.cpp b/clang/test/OpenMP/taskloop_lastprivate_codegen.cpp index f9dd2a4dac843..96a974dc38858 100644 --- a/clang/test/OpenMP/taskloop_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/taskloop_lastprivate_codegen.cpp @@ -1,18 +1,18 @@ -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLOOP -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LOOP %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLOOP -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LOOP %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLOOP -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLOOP -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/taskloop_private_codegen.cpp b/clang/test/OpenMP/taskloop_private_codegen.cpp index 5a752904bbee6..2d1c86f529775 100644 --- a/clang/test/OpenMP/taskloop_private_codegen.cpp +++ b/clang/test/OpenMP/taskloop_private_codegen.cpp @@ -1,16 +1,16 @@ -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/taskloop_reduction_codegen.cpp b/clang/test/OpenMP/taskloop_reduction_codegen.cpp index ee2dde82e24f0..762f280131261 100644 --- a/clang/test/OpenMP/taskloop_reduction_codegen.cpp +++ b/clang/test/OpenMP/taskloop_reduction_codegen.cpp @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 -fopenmp -x c++ %s -verify -debug-info-kind=limited -emit-llvm -o - -triple powerpc64le-unknown-linux-gnu -std=c++98 | FileCheck %s +// RUN: %clang_cc1 -fopenmp -x c++ %s -verify -Wno-vla -debug-info-kind=limited -emit-llvm -o - -triple powerpc64le-unknown-linux-gnu -std=c++98 | FileCheck %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ %s -verify -debug-info-kind=limited -emit-llvm -o - -triple powerpc64le-unknown-linux-gnu -std=c++98 | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ %s -verify -Wno-vla -debug-info-kind=limited -emit-llvm -o - -triple powerpc64le-unknown-linux-gnu -std=c++98 | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/taskloop_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/taskloop_simd_firstprivate_codegen.cpp index a4e3915b819b6..969ee1d1dddb6 100644 --- a/clang/test/OpenMP/taskloop_simd_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/taskloop_simd_firstprivate_codegen.cpp @@ -1,16 +1,16 @@ -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/taskloop_simd_in_reduction_codegen.cpp b/clang/test/OpenMP/taskloop_simd_in_reduction_codegen.cpp index 049947297a28d..85df70f25a8ba 100644 --- a/clang/test/OpenMP/taskloop_simd_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/taskloop_simd_in_reduction_codegen.cpp @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 // expected-no-diagnostics #ifndef HEADER #define HEADER diff --git a/clang/test/OpenMP/taskloop_simd_lastprivate_codegen.cpp b/clang/test/OpenMP/taskloop_simd_lastprivate_codegen.cpp index 788a0acfdeb52..5781f07e643fd 100644 --- a/clang/test/OpenMP/taskloop_simd_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/taskloop_simd_lastprivate_codegen.cpp @@ -1,16 +1,16 @@ -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/taskloop_simd_linear_messages.cpp b/clang/test/OpenMP/taskloop_simd_linear_messages.cpp index 4007b139606fc..22e2d26cb5561 100644 --- a/clang/test/OpenMP/taskloop_simd_linear_messages.cpp +++ b/clang/test/OpenMP/taskloop_simd_linear_messages.cpp @@ -1,6 +1,8 @@ // RUN: %clang_cc1 -verify -fopenmp %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp -fopenmp-version=52 -DOMP52 %s -Wuninitialized // RUN: %clang_cc1 -verify -fopenmp-simd %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp-simd -fopenmp-version=52 -DOMP52 %s -Wuninitialized typedef void **omp_allocator_handle_t; extern const omp_allocator_handle_t omp_null_allocator; @@ -14,8 +16,8 @@ extern const omp_allocator_handle_t omp_pteam_mem_alloc; extern const omp_allocator_handle_t omp_thread_mem_alloc; void xxx(int argc) { - int i, lin, step; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step' to silence this warning}} -#pragma omp taskloop simd linear(i, lin : step) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step' is uninitialized when used here}} + int i, lin, step_sz; // expected-note {{initialize the variable 'lin' to silence this warning}} expected-note {{initialize the variable 'step_sz' to silence this warning}} +#pragma omp taskloop simd linear(i, lin : step_sz) // expected-warning {{variable 'lin' is uninitialized when used here}} expected-warning {{variable 'step_sz' is uninitialized when used here}} for (i = 0; i < 10; ++i) ; } @@ -129,11 +131,11 @@ template int foomain(I argc, C **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp taskloop simd linear (val // expected-error {{use of undeclared identifier 'val'}} expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp taskloop simd linear (uval( // expected-error {{expected expression}} expected-error 2 {{expected ')'}} expected-note 2 {{to match this '('}} + #pragma omp taskloop simd linear (uval( // expected-error {{expected expression}} expected-error 2 {{expected ')'}} expected-note 2 {{to match this '('}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp taskloop simd linear (ref() // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} + #pragma omp taskloop simd linear (ref() // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp taskloop simd linear (foo() // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} + #pragma omp taskloop simd linear (foo() // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp taskloop simd linear () // expected-error {{expected expression}} for (int k = 0; k < argc; ++k) ++k; @@ -141,7 +143,7 @@ template int foomain(I argc, C **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp taskloop simd linear (val argc // expected-error {{use of undeclared identifier 'val'}} expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp taskloop simd linear (val(argc, // expected-error {{expected expression}} expected-error 2 {{expected ')'}} expected-note 2 {{to match this '('}} + #pragma omp taskloop simd linear (val(argc, // expected-error {{expected expression}} expected-error 2 {{expected ')'}} expected-note 2 {{to match this '('}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp taskloop simd linear (argc > 0 ? argv[1] : argv[2]) // expected-error {{expected variable name}} for (int k = 0; k < argc; ++k) ++k; @@ -149,17 +151,25 @@ template int foomain(I argc, C **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp taskloop simd linear (S1) // expected-error {{'S1' does not refer to a value}} for (int k = 0; k < argc; ++k) ++k; +#if defined(OMP52) + // omp52-error@+3{{step simple modifier is exclusive and can't be use with 'val', 'uval' or 'ref' modifier}} + // expected-error@+2 {{linear variable with incomplete type 'S1'}} + // expected-error@+1 {{argument of a linear clause should be of integral or pointer type, not 'S2'}} + #pragma omp taskloop simd linear (a, b: val, B::ib) +#else + // omp52-error@+3 {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} // expected-error@+2 {{linear variable with incomplete type 'S1'}} // expected-error@+1 {{argument of a linear clause should be of integral or pointer type, not 'S2'}} #pragma omp taskloop simd linear (val(a, b):B::ib) +#endif for (int k = 0; k < argc; ++k) ++k; #pragma omp taskloop simd linear (argv[1]) // expected-error {{expected variable name}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp taskloop simd linear(ref(e, g)) // expected-error 2 {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'ref'}} + #pragma omp taskloop simd linear(ref(e, g)) // expected-error 2 {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'ref'}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp taskloop simd linear(h, z) // expected-error {{threadprivate or thread local variable cannot be linear}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp taskloop simd linear(uval(i)) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} + #pragma omp taskloop simd linear(uval(i)) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp parallel { @@ -168,9 +178,9 @@ template int foomain(I argc, C **argv) { #pragma omp taskloop simd allocate(omp_thread_mem_alloc: v) linear(v:i) // expected-warning {{allocator with the 'thread' trait access has unspecified behavior on 'taskloop simd' directive}} for (int k = 0; k < argc; ++k) { i = k; v += i; } } - #pragma omp taskloop simd linear(ref(j)) + #pragma omp taskloop simd linear(ref(j)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp taskloop simd linear(uval(j)) + #pragma omp taskloop simd linear(uval(j)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; int v = 0; #pragma omp taskloop simd linear(v:j) @@ -192,13 +202,13 @@ void linear_modifiers(int argc) { int &f = argc; #pragma omp taskloop simd linear(f) for (int k = 0; k < argc; ++k) ++k; - #pragma omp taskloop simd linear(val(f)) + #pragma omp taskloop simd linear(val(f)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp taskloop simd linear(uval(f)) + #pragma omp taskloop simd linear(uval(f)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp taskloop simd linear(ref(f)) + #pragma omp taskloop simd linear(ref(f)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp taskloop simd linear(foo(f)) // expected-error {{expected one of 'ref', val' or 'uval' modifiers}} + #pragma omp taskloop simd linear(foo(f)) // expected-error {{expected one of 'ref', val' or 'uval' modifiers}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; } @@ -224,9 +234,9 @@ int main(int argc, char **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp taskloop simd linear (val // expected-error {{use of undeclared identifier 'val'}} expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp taskloop simd linear (ref()) // expected-error {{expected expression}} + #pragma omp taskloop simd linear (ref()) // expected-error {{expected expression}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; - #pragma omp taskloop simd linear (foo()) // expected-error {{expected expression}} + #pragma omp taskloop simd linear (foo()) // expected-error {{expected expression}} omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; #pragma omp taskloop simd linear (argc // expected-error {{expected ')'}} expected-note {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; @@ -244,6 +254,7 @@ int main(int argc, char **argv) { for (int k = 0; k < argc; ++k) ++k; #pragma omp taskloop simd linear (argv[1]) // expected-error {{expected variable name}} for (int k = 0; k < argc; ++k) ++k; + // omp52-error@+3 {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} // expected-error@+2 {{argument of a linear clause should be of integral or pointer type, not 'S4'}} // expected-error@+1 {{argument of a linear clause should be of integral or pointer type, not 'S5'}} #pragma omp taskloop simd linear(val(e, g)) @@ -253,15 +264,37 @@ int main(int argc, char **argv) { #pragma omp parallel { int i; - #pragma omp taskloop simd linear(val(i)) + #pragma omp taskloop simd linear(val(i)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp taskloop simd linear(i : uval, step(4)) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} +#else #pragma omp taskloop simd linear(uval(i) : 4) // expected-error {{variable of non-reference type 'int' can be used only with 'val' modifier, but used with 'uval'}} +#endif for (int k = 0; k < argc; ++k) { ++k; i += 4; } } - #pragma omp taskloop simd linear(ref(j)) - for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp taskloop simd linear(j: ref) +#else + #pragma omp taskloop simd linear(ref(j)) // omp52-error {{old syntax 'linear-modifier(list)' on 'linear' clause was deprecated, use new syntax 'linear(list: [linear-modifier,] step(step-size))'}} +#endif + for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp taskloop simd linear(i: step(1), step(2)) // omp52-error {{multiple 'step size' found in linear clause}} +#else #pragma omp taskloop simd linear(i) +#endif + for (int k = 0; k < argc; ++k) ++k; +#ifdef OMP52 + #pragma omp taskloop simd linear(i: val, val) // omp52-error {{multiple 'linear modifier' found in linear clause}} + for (int k = 0; k < argc; ++k) ++k; + #pragma omp taskloop simd linear(j: step()) // omp52-error 2 {{expected expression}} + for (int k = 0; k < argc; ++k) ++k; + #pragma omp taskloop simd linear(j: pval) // omp52-error {{use of undeclared identifier 'pval'}} + for (int k = 0; k < argc; ++k) ++k; + #pragma omp taskloop simd linear(i: val, step(2 // omp52-error {{expected ')' or ',' after 'step expression'}} omp52-error 2 {{expected ')'}} omp52-note 2 {{to match this '('}} for (int k = 0; k < argc; ++k) ++k; +#endif foomain(argc,argv); // expected-note {{in instantiation of function template specialization 'foomain' requested here}} return 0; diff --git a/clang/test/OpenMP/taskloop_simd_private_codegen.cpp b/clang/test/OpenMP/taskloop_simd_private_codegen.cpp index f2d064dd6c133..29505414266a3 100644 --- a/clang/test/OpenMP/taskloop_simd_private_codegen.cpp +++ b/clang/test/OpenMP/taskloop_simd_private_codegen.cpp @@ -1,16 +1,16 @@ -// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/taskloop_simd_reduction_codegen.cpp b/clang/test/OpenMP/taskloop_simd_reduction_codegen.cpp index 0e2a0ae6b58ef..64221ad3affab 100644 --- a/clang/test/OpenMP/taskloop_simd_reduction_codegen.cpp +++ b/clang/test/OpenMP/taskloop_simd_reduction_codegen.cpp @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 -fopenmp -x c++ %s -verify -debug-info-kind=limited -emit-llvm -o - -triple powerpc64le-unknown-linux-gnu -fnoopenmp-use-tls -std=c++98 | FileCheck %s +// RUN: %clang_cc1 -fopenmp -x c++ %s -verify -Wno-vla -debug-info-kind=limited -emit-llvm -o - -triple powerpc64le-unknown-linux-gnu -fnoopenmp-use-tls -std=c++98 | FileCheck %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ %s -verify -debug-info-kind=limited -emit-llvm -o - -triple powerpc64le-unknown-linux-gnu -fnoopenmp-use-tls -std=c++98 | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ %s -verify -Wno-vla -debug-info-kind=limited -emit-llvm -o - -triple powerpc64le-unknown-linux-gnu -fnoopenmp-use-tls -std=c++98 | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/teams_distribute_codegen.cpp b/clang/test/OpenMP/teams_distribute_codegen.cpp index 973ad8cf38476..6856482539ea7 100644 --- a/clang/test/OpenMP/teams_distribute_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_codegen.cpp @@ -3,19 +3,19 @@ #ifndef HEADER #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 int a[100]; @@ -51,19 +51,19 @@ int teams_argument_global(int n) { #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 int teams_local_arg(void) { @@ -84,19 +84,19 @@ int teams_local_arg(void) { #endif // CK2 // Test host codegen. -// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK3 @@ -127,19 +127,19 @@ int teams_template_struct(void) { #endif // CK3 // Test host codegen. -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK25 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK25 // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK25 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK27 +// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK25 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK27 // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK27 +// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK27 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK4 diff --git a/clang/test/OpenMP/teams_distribute_collapse_codegen.cpp b/clang/test/OpenMP/teams_distribute_collapse_codegen.cpp index 4d7223f25eb1a..fccd4268a405f 100644 --- a/clang/test/OpenMP/teams_distribute_collapse_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_collapse_codegen.cpp @@ -4,19 +4,19 @@ #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -47,19 +47,19 @@ int teams_template_struct(void) { #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template diff --git a/clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp b/clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp index 05262df4809cf..40b03586adf9b 100644 --- a/clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp @@ -4,19 +4,19 @@ #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -58,19 +58,19 @@ int teams_template_struct(void) { #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp index e347770b84421..54dfac4922d45 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp @@ -3,19 +3,19 @@ #ifndef HEADER #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 int a[100]; @@ -51,19 +51,19 @@ int teams_argument_global(int n){ #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 int teams_local_arg(void) { @@ -84,19 +84,19 @@ int teams_local_arg(void) { #endif // CK2 // Test host codegen. -// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK3 @@ -127,19 +127,19 @@ int teams_template_struct(void) { #endif // CK3 // Test host codegen. -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK25 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK25 // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK25 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK27 +// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK25 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK27 // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK27 +// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK27 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK4 diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp index 86ec6b7952979..e909bccab23f9 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp @@ -4,19 +4,19 @@ #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -48,19 +48,19 @@ int teams_template_struct(void) { #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp index 4fca9c52dab7e..f446746aef20f 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp @@ -4,19 +4,19 @@ #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -62,19 +62,19 @@ int teams_template_struct(void) { #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp index 412d94cb4b424..76a451ba8ef03 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp @@ -4,26 +4,26 @@ #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -87,26 +87,26 @@ int teams_template_struct(void) { #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 // RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 // RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_codegen.cpp index 70d82636c5550..f35f650792d38 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_codegen.cpp @@ -3,19 +3,19 @@ #ifndef HEADER #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 #ifdef CK1 int a[100]; @@ -52,19 +52,19 @@ int teams_argument_global(int n){ #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 #ifdef CK2 int teams_local_arg(void) { @@ -87,19 +87,19 @@ int teams_local_arg(void) { #endif // CK2 // Test host codegen. -// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK21 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK23 #ifdef CK3 @@ -131,19 +131,19 @@ int teams_template_struct(void) { #endif // CK3 // Test host codegen. -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK25 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK25 // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK25 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK27 +// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK25 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK27 // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK27 +// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK27 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK29 // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK29 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK31 // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK31 #ifdef CK4 diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp index 1f72e1065181c..518a6dc6d8e23 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp @@ -4,19 +4,19 @@ #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 #ifdef CK1 template @@ -51,19 +51,19 @@ int teams_template_struct(void) { #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 #ifdef CK2 template diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp index e5c5a11d488d4..ab483ce94b6f7 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp @@ -4,19 +4,19 @@ #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 #ifdef CK1 template @@ -64,19 +64,19 @@ int teams_template_struct(void) { #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 #ifdef CK2 template diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_linear_messages.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_linear_messages.cpp index 1d2b7a73cd698..8e3864ba5e2a4 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_linear_messages.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_linear_messages.cpp @@ -1,12 +1,14 @@ // RUN: %clang_cc1 -verify -fopenmp %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp -fopenmp-version=52 -DOMP52 %s -Wuninitialized // RUN: %clang_cc1 -verify -fopenmp-simd %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp-simd -fopenmp-version=52 -DOMP52 %s -Wuninitialized extern int omp_default_mem_alloc; void xxx(int argc) { - int i, step; // expected-note {{initialize the variable 'step' to silence this warning}} + int i, step_sz; // expected-note {{initialize the variable 'step_sz' to silence this warning}} #pragma omp target -#pragma omp teams distribute parallel for simd linear(i : step) // expected-warning {{variable 'step' is uninitialized when used here}} +#pragma omp teams distribute parallel for simd linear(i : step_sz) // expected-warning {{variable 'step_sz' is uninitialized when used here}} for (i = 0; i < 10; ++i) ; } diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp index 2f05daa171715..8f49b4b4239aa 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp @@ -4,27 +4,27 @@ #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK2 // RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 // RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 #ifdef CK1 template @@ -89,30 +89,30 @@ int teams_template_struct(void) { #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK14 // RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 // RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK21 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK23 #ifdef CK2 template diff --git a/clang/test/OpenMP/teams_distribute_simd_codegen.cpp b/clang/test/OpenMP/teams_distribute_simd_codegen.cpp index ee84b490c6a3c..751bb6ca35ba8 100644 --- a/clang/test/OpenMP/teams_distribute_simd_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_simd_codegen.cpp @@ -3,19 +3,19 @@ #ifndef HEADER #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 #ifdef CK1 int a[100]; @@ -53,19 +53,19 @@ int teams_argument_global(int n) { #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 #ifdef CK2 int teams_local_arg(void) { @@ -86,31 +86,31 @@ int teams_local_arg(void) { #endif // CK2 // Test host codegen. -// RUN: %clang_cc1 -DCK3 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 // RUN: %clang_cc1 -DCK3 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK3 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 // RUN: %clang_cc1 -DCK3 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DCK3 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 // RUN: %clang_cc1 -DCK3 -fopenmp -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK21 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -DCK3 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 // RUN: %clang_cc1 -DCK3 -fopenmp -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -DCK3 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK23 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK25 +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK25 // RUN: %clang_cc1 -DCK3 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK25 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK27 +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK25 +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK27 // RUN: %clang_cc1 -DCK3 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK27 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK27 +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK29 // RUN: %clang_cc1 -DCK3 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK29 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK31 // RUN: %clang_cc1 -DCK3 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK31 #ifdef CK3 @@ -145,31 +145,31 @@ int teams_template_struct(void) { #endif // CK3 // Test host codegen. -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK33 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK33 // RUN: %clang_cc1 -DCK4 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK33 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK35 +// RUN: %clang_cc1 -DCK4 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK33 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK35 // RUN: %clang_cc1 -DCK4 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK35 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK37 +// RUN: %clang_cc1 -DCK4 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK35 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK37 // RUN: %clang_cc1 -DCK4 -fopenmp -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK37 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK39 +// RUN: %clang_cc1 -DCK4 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK37 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK39 // RUN: %clang_cc1 -DCK4 -fopenmp -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK39 +// RUN: %clang_cc1 -DCK4 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK39 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK41 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK41 // RUN: %clang_cc1 -DCK4 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK41 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK43 +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK41 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK43 // RUN: %clang_cc1 -DCK4 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK43 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK45 +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK43 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK45 // RUN: %clang_cc1 -DCK4 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK45 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK47 +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK45 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK47 // RUN: %clang_cc1 -DCK4 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK47 +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK47 #ifdef CK4 @@ -331,7 +331,7 @@ int main (int argc, char **argv) { // CHECK1-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 // CHECK1-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l30(i64 [[TMP2]], i64 [[TMP4]], ptr @a, i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l30(i64 [[TMP2]], i64 [[TMP4]], ptr @a, i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR3:[0-9]+]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: [[TMP51:%.*]] = load i32, ptr [[N_ADDR]], align 4 @@ -391,7 +391,7 @@ int main (int argc, char **argv) { // CHECK1-NEXT: [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0 // CHECK1-NEXT: br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] // CHECK1: omp_offload.failed16: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l36(i64 [[TMP52]], ptr @a) #[[ATTR4]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l36(i64 [[TMP52]], ptr @a) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT17]] // CHECK1: omp_offload.cont17: // CHECK1-NEXT: [[TMP80:%.*]] = load i32, ptr @a, align 4 @@ -421,7 +421,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l30.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -485,27 +485,27 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP7]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP2]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] +// CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -542,7 +542,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l36.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -621,7 +621,7 @@ int main (int argc, char **argv) { // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -646,7 +646,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK1-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK1-SAME: () #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) // CHECK1-NEXT: ret void @@ -773,7 +773,7 @@ int main (int argc, char **argv) { // CHECK3-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 // CHECK3-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l30(i32 [[TMP2]], i32 [[TMP4]], ptr @a, i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR4:[0-9]+]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l30(i32 [[TMP2]], i32 [[TMP4]], ptr @a, i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR3:[0-9]+]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: [[TMP51:%.*]] = load i32, ptr [[N_ADDR]], align 4 @@ -833,7 +833,7 @@ int main (int argc, char **argv) { // CHECK3-NEXT: [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0 // CHECK3-NEXT: br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] // CHECK3: omp_offload.failed16: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l36(i32 [[TMP52]], ptr @a) #[[ATTR4]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l36(i32 [[TMP52]], ptr @a) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT17]] // CHECK3: omp_offload.cont17: // CHECK3-NEXT: [[TMP80:%.*]] = load i32, ptr @a, align 4 @@ -863,7 +863,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l30.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -927,26 +927,26 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]] -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP8]] -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK3-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP2]], i32 0, i32 [[TMP17]] -// CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK3-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -983,7 +983,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l36.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -1061,7 +1061,7 @@ int main (int argc, char **argv) { // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 // CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1086,7 +1086,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK3-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK3-SAME: () #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) // CHECK3-NEXT: ret void @@ -1450,7 +1450,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 // CHECK9-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK9: omp_offload.failed: -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l75(i64 [[TMP4]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR4:[0-9]+]] +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l75(i64 [[TMP4]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i64 0 @@ -1476,7 +1476,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l75.omp_outlined -// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1538,27 +1538,27 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]] +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP5]] -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK9-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP4]] +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK9-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1583,7 +1583,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK9-SAME: () #[[ATTR5:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) // CHECK9-NEXT: ret void @@ -1679,7 +1679,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 // CHECK11-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK11: omp_offload.failed: -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l75(i32 [[TMP3]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR4:[0-9]+]] +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l75(i32 [[TMP3]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i32 0 @@ -1705,7 +1705,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l75.omp_outlined -// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -1767,26 +1767,26 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK11-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i32 [[TMP17]] -// CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK11-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -1811,7 +1811,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK11-SAME: () #[[ATTR5:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: call void @__tgt_register_requires(i64 1) // CHECK11-NEXT: ret void @@ -2050,7 +2050,7 @@ int main (int argc, char **argv) { // CHECK17-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 // CHECK17-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK17: omp_offload.failed: -// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l123(ptr [[THIS1]]) #[[ATTR3:[0-9]+]] +// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l123(ptr [[THIS1]]) #[[ATTR2:[0-9]+]] // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK17: omp_offload.cont: // CHECK17-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 @@ -2070,7 +2070,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l123.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -2108,31 +2108,31 @@ int main (int argc, char **argv) { // CHECK17-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]] +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP9:%.*]] = load float, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK17-NEXT: [[TMP9:%.*]] = load float, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK17-NEXT: [[CONV:%.*]] = fptosi float [[TMP9]] to i32 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] -// CHECK17-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK17-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK17-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK17-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK17: omp.inner.for.end: // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK17: omp.loop.exit: @@ -2148,7 +2148,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK17-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK17-SAME: () #[[ATTR4:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: call void @__tgt_register_requires(i64 1) // CHECK17-NEXT: ret void @@ -2235,7 +2235,7 @@ int main (int argc, char **argv) { // CHECK19-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 // CHECK19-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK19: omp_offload.failed: -// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l123(ptr [[THIS1]]) #[[ATTR3:[0-9]+]] +// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l123(ptr [[THIS1]]) #[[ATTR2:[0-9]+]] // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK19: omp_offload.cont: // CHECK19-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 @@ -2255,7 +2255,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l123.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -2293,30 +2293,30 @@ int main (int argc, char **argv) { // CHECK19-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK19: omp.inner.for.cond: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] +// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP9:%.*]] = load float, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK19-NEXT: [[TMP9:%.*]] = load float, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK19-NEXT: [[CONV:%.*]] = fptosi float [[TMP9]] to i32 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP10]] -// CHECK19-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK19-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK19-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK19-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK19: omp.inner.for.end: // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK19: omp.loop.exit: @@ -2332,7 +2332,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK19-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK19-SAME: () #[[ATTR4:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: call void @__tgt_register_requires(i64 1) // CHECK19-NEXT: ret void @@ -2419,7 +2419,7 @@ int main (int argc, char **argv) { // CHECK21-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 // CHECK21-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK21: omp_offload.failed: -// CHECK21-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l123(ptr [[THIS1]]) #[[ATTR3:[0-9]+]] +// CHECK21-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l123(ptr [[THIS1]]) #[[ATTR2:[0-9]+]] // CHECK21-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK21: omp_offload.cont: // CHECK21-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 @@ -2451,7 +2451,7 @@ int main (int argc, char **argv) { // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l123.omp_outlined -// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -2495,31 +2495,31 @@ int main (int argc, char **argv) { // CHECK21: omp_if.then: // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK21: omp.inner.for.cond: -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]] +// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK21: omp.inner.for.body: -// CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK21-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 1 -// CHECK21-NEXT: [[TMP10:%.*]] = load float, ptr [[B]], align 4, !nontemporal !6, !llvm.access.group [[ACC_GRP5]] +// CHECK21-NEXT: [[TMP10:%.*]] = load float, ptr [[B]], align 4, !nontemporal !5, !llvm.access.group [[ACC_GRP4]] // CHECK21-NEXT: [[CONV:%.*]] = fptosi float [[TMP10]] to i32 // CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] -// CHECK21-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK21-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK21: omp.body.continue: // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK21: omp.inner.for.inc: -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK21-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] -// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK21-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] +// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK21: omp.inner.for.end: // CHECK21-NEXT: br label [[OMP_IF_END:%.*]] // CHECK21: omp_if.else: @@ -2549,7 +2549,7 @@ int main (int argc, char **argv) { // CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK21-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1 // CHECK21-NEXT: store i32 [[ADD15]], ptr [[DOTOMP_IV]], align 4 -// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND3]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND3]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK21: omp.inner.for.end16: // CHECK21-NEXT: br label [[OMP_IF_END]] // CHECK21: omp_if.end: @@ -2567,7 +2567,7 @@ int main (int argc, char **argv) { // // // CHECK21-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK21-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK21-SAME: () #[[ATTR4:[0-9]+]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: call void @__tgt_register_requires(i64 1) // CHECK21-NEXT: ret void @@ -2654,7 +2654,7 @@ int main (int argc, char **argv) { // CHECK23-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 // CHECK23-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK23: omp_offload.failed: -// CHECK23-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l123(ptr [[THIS1]]) #[[ATTR3:[0-9]+]] +// CHECK23-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l123(ptr [[THIS1]]) #[[ATTR2:[0-9]+]] // CHECK23-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK23: omp_offload.cont: // CHECK23-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 @@ -2686,7 +2686,7 @@ int main (int argc, char **argv) { // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l123.omp_outlined -// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -2730,30 +2730,30 @@ int main (int argc, char **argv) { // CHECK23: omp_if.then: // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK23: omp.inner.for.cond: -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] +// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK23: omp.inner.for.body: -// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK23-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 1 -// CHECK23-NEXT: [[TMP10:%.*]] = load float, ptr [[B]], align 4, !nontemporal !7, !llvm.access.group [[ACC_GRP6]] +// CHECK23-NEXT: [[TMP10:%.*]] = load float, ptr [[B]], align 4, !nontemporal !6, !llvm.access.group [[ACC_GRP5]] // CHECK23-NEXT: [[CONV:%.*]] = fptosi float [[TMP10]] to i32 // CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] -// CHECK23-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK23-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK23: omp.body.continue: // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK23: omp.inner.for.inc: -// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK23-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK23-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK23: omp.inner.for.end: // CHECK23-NEXT: br label [[OMP_IF_END:%.*]] // CHECK23: omp_if.else: @@ -2782,7 +2782,7 @@ int main (int argc, char **argv) { // CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK23-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP18]], 1 // CHECK23-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4 -// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND3]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND3]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK23: omp.inner.for.end15: // CHECK23-NEXT: br label [[OMP_IF_END]] // CHECK23: omp_if.end: @@ -2800,7 +2800,7 @@ int main (int argc, char **argv) { // // // CHECK23-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK23-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK23-SAME: () #[[ATTR4:[0-9]+]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: call void @__tgt_register_requires(i64 1) // CHECK23-NEXT: ret void @@ -3215,7 +3215,7 @@ int main (int argc, char **argv) { // CHECK33-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 // CHECK33-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK33: omp_offload.failed: -// CHECK33-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192(i64 [[TMP4]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR4:[0-9]+]] +// CHECK33-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192(i64 [[TMP4]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK33-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK33: omp_offload.cont: // CHECK33-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 @@ -3243,7 +3243,7 @@ int main (int argc, char **argv) { // // // CHECK33-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192.omp_outlined -// CHECK33-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK33-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK33-NEXT: entry: // CHECK33-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK33-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -3305,27 +3305,27 @@ int main (int argc, char **argv) { // CHECK33-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 // CHECK33-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK33: omp.inner.for.cond: -// CHECK33-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] -// CHECK33-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]] +// CHECK33-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] +// CHECK33-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK33-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK33-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK33: omp.inner.for.body: -// CHECK33-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] +// CHECK33-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK33-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK33-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK33-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK33-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP7]] +// CHECK33-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK33-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK33-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK33-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 [[IDXPROM]] -// CHECK33-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] +// CHECK33-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK33-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK33: omp.body.continue: // CHECK33-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK33: omp.inner.for.inc: -// CHECK33-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] +// CHECK33-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK33-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK33-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK33-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK33-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK33-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK33: omp.inner.for.end: // CHECK33-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK33: omp.loop.exit: @@ -3350,7 +3350,7 @@ int main (int argc, char **argv) { // // // CHECK33-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK33-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR6:[0-9]+]] comdat { +// CHECK33-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { // CHECK33-NEXT: entry: // CHECK33-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK33-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -3428,7 +3428,7 @@ int main (int argc, char **argv) { // CHECK33-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 // CHECK33-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK33: omp_offload.failed: -// CHECK33-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l181(i64 [[TMP1]], i64 [[TMP3]], ptr [[A]]) #[[ATTR4]] +// CHECK33-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l181(i64 [[TMP1]], i64 [[TMP3]], ptr [[A]]) #[[ATTR3]] // CHECK33-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK33: omp_offload.cont: // CHECK33-NEXT: ret i32 0 @@ -3453,7 +3453,7 @@ int main (int argc, char **argv) { // // // CHECK33-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l181.omp_outlined -// CHECK33-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { +// CHECK33-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK33-NEXT: entry: // CHECK33-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK33-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -3491,27 +3491,27 @@ int main (int argc, char **argv) { // CHECK33-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK33-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK33: omp.inner.for.cond: -// CHECK33-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] -// CHECK33-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK33-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] +// CHECK33-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK33-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK33-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK33: omp.inner.for.body: -// CHECK33-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK33-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK33-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK33-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK33-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK33-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK33-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] +// CHECK33-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK33-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK33-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK33-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK33-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK33-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK33: omp.body.continue: // CHECK33-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK33: omp.inner.for.inc: -// CHECK33-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK33-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK33-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK33-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK33-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK33-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] +// CHECK33-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK33: omp.inner.for.end: // CHECK33-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK33: omp.loop.exit: @@ -3527,7 +3527,7 @@ int main (int argc, char **argv) { // // // CHECK33-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK33-SAME: () #[[ATTR7:[0-9]+]] { +// CHECK33-SAME: () #[[ATTR6:[0-9]+]] { // CHECK33-NEXT: entry: // CHECK33-NEXT: call void @__tgt_register_requires(i64 1) // CHECK33-NEXT: ret void @@ -3629,7 +3629,7 @@ int main (int argc, char **argv) { // CHECK35-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 // CHECK35-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK35: omp_offload.failed: -// CHECK35-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192(i32 [[TMP3]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR4:[0-9]+]] +// CHECK35-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192(i32 [[TMP3]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK35-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK35: omp_offload.cont: // CHECK35-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 @@ -3657,7 +3657,7 @@ int main (int argc, char **argv) { // // // CHECK35-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192.omp_outlined -// CHECK35-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK35-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK35-NEXT: entry: // CHECK35-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK35-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -3719,26 +3719,26 @@ int main (int argc, char **argv) { // CHECK35-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 // CHECK35-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK35: omp.inner.for.cond: -// CHECK35-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]] -// CHECK35-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK35-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] +// CHECK35-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK35-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK35-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK35: omp.inner.for.body: -// CHECK35-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK35-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK35-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK35-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK35-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP8]] -// CHECK35-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK35-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK35-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK35-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i32 [[TMP17]] -// CHECK35-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK35-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK35-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK35: omp.body.continue: // CHECK35-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK35: omp.inner.for.inc: -// CHECK35-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK35-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK35-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK35-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] -// CHECK35-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK35-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK35-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK35: omp.inner.for.end: // CHECK35-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK35: omp.loop.exit: @@ -3763,7 +3763,7 @@ int main (int argc, char **argv) { // // // CHECK35-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK35-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR6:[0-9]+]] comdat { +// CHECK35-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { // CHECK35-NEXT: entry: // CHECK35-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK35-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -3841,7 +3841,7 @@ int main (int argc, char **argv) { // CHECK35-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 // CHECK35-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK35: omp_offload.failed: -// CHECK35-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l181(i32 [[TMP1]], i32 [[TMP3]], ptr [[A]]) #[[ATTR4]] +// CHECK35-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l181(i32 [[TMP1]], i32 [[TMP3]], ptr [[A]]) #[[ATTR3]] // CHECK35-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK35: omp_offload.cont: // CHECK35-NEXT: ret i32 0 @@ -3866,7 +3866,7 @@ int main (int argc, char **argv) { // // // CHECK35-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l181.omp_outlined -// CHECK35-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { +// CHECK35-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK35-NEXT: entry: // CHECK35-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK35-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -3904,26 +3904,26 @@ int main (int argc, char **argv) { // CHECK35-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK35-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK35: omp.inner.for.cond: -// CHECK35-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]] -// CHECK35-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK35-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] +// CHECK35-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK35-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK35-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK35: omp.inner.for.body: -// CHECK35-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK35-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK35-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK35-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK35-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK35-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK35-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK35-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK35-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP9]] -// CHECK35-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK35-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK35-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK35: omp.body.continue: // CHECK35-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK35: omp.inner.for.inc: -// CHECK35-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK35-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK35-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK35-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK35-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK35-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] +// CHECK35-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK35: omp.inner.for.end: // CHECK35-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK35: omp.loop.exit: @@ -3939,7 +3939,7 @@ int main (int argc, char **argv) { // // // CHECK35-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK35-SAME: () #[[ATTR7:[0-9]+]] { +// CHECK35-SAME: () #[[ATTR6:[0-9]+]] { // CHECK35-NEXT: entry: // CHECK35-NEXT: call void @__tgt_register_requires(i64 1) // CHECK35-NEXT: ret void @@ -4051,7 +4051,7 @@ int main (int argc, char **argv) { // CHECK37-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 // CHECK37-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK37: omp_offload.failed: -// CHECK37-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR4:[0-9]+]] +// CHECK37-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK37-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK37: omp_offload.cont: // CHECK37-NEXT: [[TMP43:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 @@ -4092,7 +4092,7 @@ int main (int argc, char **argv) { // // // CHECK37-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192.omp_outlined -// CHECK37-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK37-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK37-NEXT: entry: // CHECK37-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK37-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -4160,27 +4160,27 @@ int main (int argc, char **argv) { // CHECK37: omp_if.then: // CHECK37-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK37: omp.inner.for.cond: -// CHECK37-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] -// CHECK37-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]] +// CHECK37-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] +// CHECK37-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK37-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK37-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK37: omp.inner.for.body: -// CHECK37-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] +// CHECK37-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK37-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK37-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK37-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK37-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP7]] +// CHECK37-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK37-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK37-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK37-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 [[IDXPROM]] -// CHECK37-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] +// CHECK37-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK37-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK37: omp.body.continue: // CHECK37-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK37: omp.inner.for.inc: -// CHECK37-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] +// CHECK37-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK37-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK37-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK37-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK37-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK37-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK37: omp.inner.for.end: // CHECK37-NEXT: br label [[OMP_IF_END:%.*]] // CHECK37: omp_if.else: @@ -4206,7 +4206,7 @@ int main (int argc, char **argv) { // CHECK37-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK37-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK37-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4 -// CHECK37-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK37-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK37: omp.inner.for.end18: // CHECK37-NEXT: br label [[OMP_IF_END]] // CHECK37: omp_if.end: @@ -4233,7 +4233,7 @@ int main (int argc, char **argv) { // // // CHECK37-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK37-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR6:[0-9]+]] comdat { +// CHECK37-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { // CHECK37-NEXT: entry: // CHECK37-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK37-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -4311,7 +4311,7 @@ int main (int argc, char **argv) { // CHECK37-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 // CHECK37-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK37: omp_offload.failed: -// CHECK37-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l181(i64 [[TMP1]], i64 [[TMP3]], ptr [[A]]) #[[ATTR4]] +// CHECK37-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l181(i64 [[TMP1]], i64 [[TMP3]], ptr [[A]]) #[[ATTR3]] // CHECK37-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK37: omp_offload.cont: // CHECK37-NEXT: ret i32 0 @@ -4336,7 +4336,7 @@ int main (int argc, char **argv) { // // // CHECK37-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l181.omp_outlined -// CHECK37-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { +// CHECK37-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK37-NEXT: entry: // CHECK37-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK37-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -4374,27 +4374,27 @@ int main (int argc, char **argv) { // CHECK37-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK37-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK37: omp.inner.for.cond: -// CHECK37-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] -// CHECK37-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK37-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] +// CHECK37-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK37-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK37-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK37: omp.inner.for.body: -// CHECK37-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK37-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK37-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK37-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK37-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK37-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK37-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK37-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK37-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK37-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK37-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK37-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK37-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK37: omp.body.continue: // CHECK37-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK37: omp.inner.for.inc: -// CHECK37-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK37-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK37-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK37-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK37-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK37-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK37-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK37: omp.inner.for.end: // CHECK37-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK37: omp.loop.exit: @@ -4410,7 +4410,7 @@ int main (int argc, char **argv) { // // // CHECK37-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK37-SAME: () #[[ATTR7:[0-9]+]] { +// CHECK37-SAME: () #[[ATTR6:[0-9]+]] { // CHECK37-NEXT: entry: // CHECK37-NEXT: call void @__tgt_register_requires(i64 1) // CHECK37-NEXT: ret void @@ -4522,7 +4522,7 @@ int main (int argc, char **argv) { // CHECK39-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 // CHECK39-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK39: omp_offload.failed: -// CHECK39-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192(i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR4:[0-9]+]] +// CHECK39-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192(i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK39-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK39: omp_offload.cont: // CHECK39-NEXT: [[TMP43:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 @@ -4563,7 +4563,7 @@ int main (int argc, char **argv) { // // // CHECK39-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192.omp_outlined -// CHECK39-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK39-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK39-NEXT: entry: // CHECK39-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK39-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -4631,26 +4631,26 @@ int main (int argc, char **argv) { // CHECK39: omp_if.then: // CHECK39-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK39: omp.inner.for.cond: -// CHECK39-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]] -// CHECK39-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK39-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] +// CHECK39-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK39-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK39-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK39: omp.inner.for.body: -// CHECK39-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK39-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK39-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK39-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK39-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP8]] -// CHECK39-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK39-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK39-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK39-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i32 [[TMP18]] -// CHECK39-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK39-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK39-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK39: omp.body.continue: // CHECK39-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK39: omp.inner.for.inc: -// CHECK39-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK39-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK39-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK39-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] -// CHECK39-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK39-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK39-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK39: omp.inner.for.end: // CHECK39-NEXT: br label [[OMP_IF_END:%.*]] // CHECK39: omp_if.else: @@ -4675,7 +4675,7 @@ int main (int argc, char **argv) { // CHECK39-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK39-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK39-NEXT: store i32 [[ADD16]], ptr [[DOTOMP_IV]], align 4 -// CHECK39-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK39-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK39: omp.inner.for.end17: // CHECK39-NEXT: br label [[OMP_IF_END]] // CHECK39: omp_if.end: @@ -4702,7 +4702,7 @@ int main (int argc, char **argv) { // // // CHECK39-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK39-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR6:[0-9]+]] comdat { +// CHECK39-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { // CHECK39-NEXT: entry: // CHECK39-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK39-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -4780,7 +4780,7 @@ int main (int argc, char **argv) { // CHECK39-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 // CHECK39-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK39: omp_offload.failed: -// CHECK39-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l181(i32 [[TMP1]], i32 [[TMP3]], ptr [[A]]) #[[ATTR4]] +// CHECK39-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l181(i32 [[TMP1]], i32 [[TMP3]], ptr [[A]]) #[[ATTR3]] // CHECK39-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK39: omp_offload.cont: // CHECK39-NEXT: ret i32 0 @@ -4805,7 +4805,7 @@ int main (int argc, char **argv) { // // // CHECK39-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l181.omp_outlined -// CHECK39-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { +// CHECK39-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK39-NEXT: entry: // CHECK39-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK39-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -4843,26 +4843,26 @@ int main (int argc, char **argv) { // CHECK39-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK39-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK39: omp.inner.for.cond: -// CHECK39-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] -// CHECK39-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK39-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]] +// CHECK39-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK39-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK39-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK39: omp.inner.for.body: -// CHECK39-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK39-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK39-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK39-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK39-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK39-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK39-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK39-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK39-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP9]] -// CHECK39-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK39-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK39-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK39: omp.body.continue: // CHECK39-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK39: omp.inner.for.inc: -// CHECK39-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK39-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK39-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK39-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK39-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK39-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK39-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK39: omp.inner.for.end: // CHECK39-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK39: omp.loop.exit: @@ -4878,7 +4878,7 @@ int main (int argc, char **argv) { // // // CHECK39-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK39-SAME: () #[[ATTR7:[0-9]+]] { +// CHECK39-SAME: () #[[ATTR6:[0-9]+]] { // CHECK39-NEXT: entry: // CHECK39-NEXT: call void @__tgt_register_requires(i64 1) // CHECK39-NEXT: ret void diff --git a/clang/test/OpenMP/teams_distribute_simd_collapse_codegen.cpp b/clang/test/OpenMP/teams_distribute_simd_collapse_codegen.cpp index 60e2494096a28..9562d2d973446 100644 --- a/clang/test/OpenMP/teams_distribute_simd_collapse_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_simd_collapse_codegen.cpp @@ -4,19 +4,19 @@ #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 #ifdef CK1 template @@ -48,19 +48,19 @@ int teams_template_struct(void) { #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 #ifdef CK2 template diff --git a/clang/test/OpenMP/teams_distribute_simd_dist_schedule_codegen.cpp b/clang/test/OpenMP/teams_distribute_simd_dist_schedule_codegen.cpp index c3d67664cce5c..0076e442d2c97 100644 --- a/clang/test/OpenMP/teams_distribute_simd_dist_schedule_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_simd_dist_schedule_codegen.cpp @@ -4,19 +4,19 @@ #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 #ifdef CK1 template @@ -58,19 +58,19 @@ int teams_template_struct(void) { #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 #ifdef CK2 template diff --git a/clang/test/OpenMP/teams_distribute_simd_linear_messages.cpp b/clang/test/OpenMP/teams_distribute_simd_linear_messages.cpp index 6f4592e07cfd5..d6c74eb853a5d 100644 --- a/clang/test/OpenMP/teams_distribute_simd_linear_messages.cpp +++ b/clang/test/OpenMP/teams_distribute_simd_linear_messages.cpp @@ -1,12 +1,14 @@ // RUN: %clang_cc1 -verify -fopenmp %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp -fopenmp-version=52 -DOMP52 %s -Wuninitialized // RUN: %clang_cc1 -verify -fopenmp-simd %s -Wuninitialized +// RUN: %clang_cc1 -verify=expected,omp52 -fopenmp-simd -fopenmp-version=52 -DOMP52 %s -Wuninitialized extern int omp_default_mem_alloc; void xxx(int argc) { - int i, step; // expected-note {{initialize the variable 'step' to silence this warning}} + int i, sz; // expected-note {{initialize the variable 'sz' to silence this warning}} #pragma omp target -#pragma omp teams distribute simd linear(i : step) // expected-warning {{variable 'step' is uninitialized when used here}} +#pragma omp teams distribute simd linear(i : sz) // expected-warning {{variable 'sz' is uninitialized when used here}} for (i = 0; i < 10; ++i) ; } diff --git a/clang/test/OpenMP/teams_firstprivate_codegen.cpp b/clang/test/OpenMP/teams_firstprivate_codegen.cpp index d99151b0368db..dbdd5f912bb6a 100644 --- a/clang/test/OpenMP/teams_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_firstprivate_codegen.cpp @@ -1,46 +1,46 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ // Test host codegen. -// RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -verify -Wno-vla -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -verify -Wno-vla -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -verify -Wno-vla -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK17 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK17 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -verify -Wno-vla -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK19 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify -Wno-vla %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK19 -// RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify -Wno-vla %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER diff --git a/clang/test/OpenMP/teams_generic_loop_codegen-1.cpp b/clang/test/OpenMP/teams_generic_loop_codegen-1.cpp index a0a75f244f2a9..d0ae405306b8e 100644 --- a/clang/test/OpenMP/teams_generic_loop_codegen-1.cpp +++ b/clang/test/OpenMP/teams_generic_loop_codegen-1.cpp @@ -3,19 +3,19 @@ #ifndef HEADER #define HEADER // Test host codegen. -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 int a[100]; @@ -50,19 +50,19 @@ int teams_argument_global(int n){ #endif // CK1 // Test host codegen. -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 int teams_local_arg(void) { @@ -83,19 +83,19 @@ int teams_local_arg(void) { #endif // CK2 // Test host codegen. -// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK3 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK3 @@ -126,19 +126,19 @@ int teams_template_struct(void) { #endif // CK3 // Test host codegen. -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK25 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK25 // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK25 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK27 +// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK25 +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK27 // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK27 +// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK27 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK4 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK4 diff --git a/clang/test/OpenMP/thread_limit_nvptx.c b/clang/test/OpenMP/thread_limit_nvptx.c index 14312ab436a4e..2132e1aa7834a 100644 --- a/clang/test/OpenMP/thread_limit_nvptx.c +++ b/clang/test/OpenMP/thread_limit_nvptx.c @@ -1,5 +1,5 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ // Test target codegen - host bc file has to be created first. +// // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s // expected-no-diagnostics @@ -15,15 +15,15 @@ void foo(int N) { #pragma omp target teams distribute parallel for simd thread_limit(4) for (int i = 0; i < N; ++i) ; -// TODO: We should not emit two maxntidx annotations. -// CHECK: l21, !"maxntidx", i32 128} +// CHECK-NOT: l21, !"maxntidx", i32 128} // CHECK: l21, !"maxntidx", i32 42} +// CHECK-NOT: l21, !"maxntidx", i32 128} #pragma omp target teams distribute parallel for simd ompx_attribute(__attribute__((launch_bounds(42, 42)))) for (int i = 0; i < N; ++i) ; -// TODO: We should not emit two maxntidx annotations. +// CHECK-NOT: l27, !"maxntidx", i32 42} // CHECK: l27, !"maxntidx", i32 22} -// CHECK: l27, !"maxntidx", i32 42} +// CHECK-NOT: l27, !"maxntidx", i32 42} #pragma omp target teams distribute parallel for simd ompx_attribute(__attribute__((launch_bounds(42, 42)))) num_threads(22) for (int i = 0; i < N; ++i) ; diff --git a/clang/test/PCH/Inputs/gch-probe.h b/clang/test/PCH/Inputs/gch-probe.h new file mode 100644 index 0000000000000..940adf12a97ae --- /dev/null +++ b/clang/test/PCH/Inputs/gch-probe.h @@ -0,0 +1 @@ +void g(void); diff --git a/clang/test/PCH/Inputs/gch-probe.h.gch b/clang/test/PCH/Inputs/gch-probe.h.gch new file mode 100644 index 0000000000000..fc551fc058b7c --- /dev/null +++ b/clang/test/PCH/Inputs/gch-probe.h.gch @@ -0,0 +1 @@ +This is not a pch file. diff --git a/clang/test/PCH/aarch64-sve-types.c b/clang/test/PCH/aarch64-sve-types.c index d9be6daa127e7..4c4549af0b6d6 100644 --- a/clang/test/PCH/aarch64-sve-types.c +++ b/clang/test/PCH/aarch64-sve-types.c @@ -18,6 +18,6 @@ __SVFloat16_t *f16; __SVFloat32_t *f32; __SVFloat64_t *f64; -__SVBFloat16_t *bf16; +__SVBfloat16_t *bf16; __SVBool_t *b8; diff --git a/clang/test/PCH/gch-probe.c b/clang/test/PCH/gch-probe.c new file mode 100644 index 0000000000000..8b1e1fab5ad97 --- /dev/null +++ b/clang/test/PCH/gch-probe.c @@ -0,0 +1,9 @@ +// For GCC compatibility, clang should probe also with the .gch extension. +// RUN: %clang -x c-header -c %s -o %t.h.gch +// RUN: %clang -fsyntax-only -include %t.h %s + +// gch probing should ignore files which are not clang pch files. +// RUN: %clang -fsyntax-only -include %S/Inputs/gch-probe.h %s 2>&1 | FileCheck %s +// CHECK: warning: precompiled header '{{.*}}gch-probe.h.gch' was ignored because it is not a clang PCH file + +void f(void); diff --git a/clang/test/PCH/pch-dir.c b/clang/test/PCH/pch-dir.c index d8ec687b4d724..fd7d24f9f83ff 100644 --- a/clang/test/PCH/pch-dir.c +++ b/clang/test/PCH/pch-dir.c @@ -23,19 +23,25 @@ // RUN: not %clang_cc1 -include-pch %t.h.gch -DFOO=baz -fsyntax-only %s -print-stats 2> %t.missinglog // RUN: FileCheck -check-prefix=CHECK-NO-SUITABLE %s < %t.missinglog +// Don't gch probe directories which contain no pch files. +// RUN: rm -rf %t.x.h.gch +// RUN: mkdir -p %t.x.h.gch +// RUN: not %clang -include %t.x.h -fsyntax-only %s 2>&1 | FileCheck -check-prefix=CHECK-IGNORED-DIR %s + // CHECK-CBAR: int bar int FOO; int get(void) { #ifdef __cplusplus - // CHECK-CPP: warning: '-include {{.*}}.h' probing .gch is deprecated. Use '-include-pch {{.*}}.h.gch' or switch to .pch instead // CHECK-CPP: .h.gch{{[/\\]}}cpp.gch return i; #else - // CHECK-C: warning: '-include {{.*}}.h' probing .gch is deprecated. Use '-include-pch {{.*}}.h.gch' or switch to .pch instead // CHECK-C: .h.gch{{[/\\]}}c.gch return j; #endif } // CHECK-NO-SUITABLE: no suitable precompiled header file found in directory + +// CHECK-IGNORED-DIR: precompiled header directory '{{.*}}pch-dir.c.tmp.x.h.gch' was ignored because it contains no clang PCH files +// CHECK-IGNORED-DIR: '{{.*}}pch-dir.c.tmp.x.h' file not found diff --git a/clang/test/Parser/objcxx11-attributes.mm b/clang/test/Parser/objcxx11-attributes.mm index 3c14d03cb28b0..d7ba609ebd74b 100644 --- a/clang/test/Parser/objcxx11-attributes.mm +++ b/clang/test/Parser/objcxx11-attributes.mm @@ -10,12 +10,12 @@ - (X*) getSelf; void f(X *noreturn) { // An array size which is computed by a message send is OK. - int a[ [noreturn getSize] ]; + int a[ [noreturn getSize] ]; // expected-warning {{variable length arrays in C++ are a Clang extension}} // ... but is interpreted as an attribute where possible. int b[ [noreturn] ]; // expected-error {{'noreturn' attribute only applies to functions}} - int c[ [noreturn getSize] + 1 ]; + int c[ [noreturn getSize] + 1 ]; // expected-warning {{variable length arrays in C++ are a Clang extension}} // An array size which is computed by a lambda is not OK. int d[ [noreturn] { return 3; } () ]; // expected-error {{expected ']'}} expected-error {{'noreturn' attribute only applies to functions}} diff --git a/clang/test/Parser/pragma-loop.cpp b/clang/test/Parser/pragma-loop.cpp index 0203e90104d4f..4078210f96e1b 100644 --- a/clang/test/Parser/pragma-loop.cpp +++ b/clang/test/Parser/pragma-loop.cpp @@ -82,7 +82,7 @@ void test_type_template_vectorize(int *List, int Length) { } } -void test(int *List, int Length) { +void test(int *List, int Length) { // expected-note {{declared here}} int i = 0; #pragma clang loop vectorize(enable) @@ -118,7 +118,8 @@ void test(int *List, int Length) { List[i] = i; } - int VList[Length]; + int VList[Length]; // expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{function parameter 'Length' with unknown value cannot be used in a constant expression}} #pragma clang loop vectorize(disable) interleave(disable) unroll(disable) vectorize_predicate(disable) for (int j : VList) { VList[j] = List[j]; diff --git a/clang/test/Preprocessor/init-mips.c b/clang/test/Preprocessor/init-mips.c index a07cee64e6848..34091ea3690da 100644 --- a/clang/test/Preprocessor/init-mips.c +++ b/clang/test/Preprocessor/init-mips.c @@ -10,6 +10,7 @@ // MIPS32BE:#define _MIPS_ARCH_MIPS32R2 1 // MIPS32BE:#define _MIPS_FPSET 16 // MIPS32BE:#define _MIPS_SIM _ABIO32 +// MIPS32BE:#define _MIPS_SPFPSET 16 // MIPS32BE:#define _MIPS_SZINT 32 // MIPS32BE:#define _MIPS_SZLONG 32 // MIPS32BE:#define _MIPS_SZPTR 32 @@ -220,6 +221,7 @@ // MIPS32EL:#define _MIPS_ARCH_MIPS32R2 1 // MIPS32EL:#define _MIPS_FPSET 16 // MIPS32EL:#define _MIPS_SIM _ABIO32 +// MIPS32EL:#define _MIPS_SPFPSET 16 // MIPS32EL:#define _MIPS_SZINT 32 // MIPS32EL:#define _MIPS_SZLONG 32 // MIPS32EL:#define _MIPS_SZPTR 32 @@ -432,6 +434,7 @@ // MIPSN32BE: #define _MIPS_FPSET 32 // MIPSN32BE: #define _MIPS_ISA _MIPS_ISA_MIPS64 // MIPSN32BE: #define _MIPS_SIM _ABIN32 +// MIPSN32BE: #define _MIPS_SPFPSET 32 // MIPSN32BE: #define _MIPS_SZINT 32 // MIPSN32BE: #define _MIPS_SZLONG 32 // MIPSN32BE: #define _MIPS_SZPTR 32 @@ -739,6 +742,7 @@ // MIPSN32EL: #define _MIPS_FPSET 32 // MIPSN32EL: #define _MIPS_ISA _MIPS_ISA_MIPS64 // MIPSN32EL: #define _MIPS_SIM _ABIN32 +// MIPSN32EL: #define _MIPS_SPFPSET 32 // MIPSN32EL: #define _MIPS_SZINT 32 // MIPSN32EL: #define _MIPS_SZLONG 32 // MIPSN32EL: #define _MIPS_SZPTR 32 @@ -1043,6 +1047,7 @@ // MIPS64BE:#define _MIPS_ARCH_MIPS64R2 1 // MIPS64BE:#define _MIPS_FPSET 32 // MIPS64BE:#define _MIPS_SIM _ABI64 +// MIPS64BE:#define _MIPS_SPFPSET 32 // MIPS64BE:#define _MIPS_SZINT 32 // MIPS64BE:#define _MIPS_SZLONG 64 // MIPS64BE:#define _MIPS_SZPTR 64 @@ -1253,6 +1258,7 @@ // MIPS64EL:#define _MIPS_ARCH_MIPS64R2 1 // MIPS64EL:#define _MIPS_FPSET 32 // MIPS64EL:#define _MIPS_SIM _ABI64 +// MIPS64EL:#define _MIPS_SPFPSET 32 // MIPS64EL:#define _MIPS_SZINT 32 // MIPS64EL:#define _MIPS_SZLONG 64 // MIPS64EL:#define _MIPS_SZPTR 64 @@ -1506,6 +1512,7 @@ // MIPS-ARCH-32R6:#define _MIPS_ARCH "mips32r6" // MIPS-ARCH-32R6:#define _MIPS_ARCH_MIPS32R6 1 // MIPS-ARCH-32R6:#define _MIPS_ISA _MIPS_ISA_MIPS32 +// MIPS-ARCH-32R6:#define __mips_fpr 64 // MIPS-ARCH-32R6:#define __mips_isa_rev 6 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=mips64-none-none \ @@ -1682,14 +1689,28 @@ // RUN: | FileCheck -match-full-lines -check-prefix MIPS32-NOFP %s // MIPS32-NOFP:#define __mips_fpr 0 +// RUN: %clang_cc1 -target-feature -nooddspreg \ +// RUN: -E -dM -triple=mips-none-none < /dev/null \ +// RUN: | FileCheck -match-full-lines -check-prefix MIPS32-NOFP-ODD %s +// MIPS32-NOFP-ODD:#define _MIPS_SPFPSET 32 +// MIPS32-NOFP-ODD:#define __mips_fpr 0 + +// RUN: %clang_cc1 -target-feature +nooddspreg -target-feature -fp64 \ +// RUN: -E -dM -triple=mips-none-none < /dev/null \ +// RUN: | FileCheck -match-full-lines -check-prefix MIPS32-FP64-NOODD %s +// MIPS32-FP64-NOODD:#define _MIPS_SPFPSET 16 +// MIPS32-FP64-NOODD:#define __mips_fpr 32 + // RUN: %clang_cc1 -target-feature +fpxx \ // RUN: -E -dM -triple=mips-none-none < /dev/null \ // RUN: | FileCheck -match-full-lines -check-prefix MIPS32-MFPXX %s +// MIPS32-MFPXX:#define _MIPS_SPFPSET 16 // MIPS32-MFPXX:#define __mips_fpr 0 // RUN: %clang_cc1 -target-cpu mips32r6 -target-feature +fpxx \ // RUN: -E -dM -triple=mips-none-none < /dev/null \ // RUN: | FileCheck -match-full-lines -check-prefix MIPS32R6-MFPXX %s +// MIPS32R6-MFPXX:#define _MIPS_SPFPSET 16 // MIPS32R6-MFPXX:#define __mips_fpr 0 // RUN: %clang_cc1 \ @@ -1716,30 +1737,35 @@ // RUN: -E -dM -triple=mips-none-none < /dev/null \ // RUN: | FileCheck -match-full-lines -check-prefix MIPS32-MFP32 %s // MIPS32-MFP32:#define _MIPS_FPSET 16 +// MIPS32-MFP32:#define _MIPS_SPFPSET 32 // MIPS32-MFP32:#define __mips_fpr 32 // RUN: %clang_cc1 -target-feature +fp64 \ // RUN: -E -dM -triple=mips-none-none < /dev/null \ // RUN: | FileCheck -match-full-lines -check-prefix MIPS32-MFP64 %s // MIPS32-MFP64:#define _MIPS_FPSET 32 +// MIPS32-MFP64:#define _MIPS_SPFPSET 32 // MIPS32-MFP64:#define __mips_fpr 64 // // RUN: %clang_cc1 -target-feature +single-float \ // RUN: -E -dM -triple=mips-none-none < /dev/null \ // RUN: | FileCheck -match-full-lines -check-prefix MIPS32-MFP32SF %s // MIPS32-MFP32SF:#define _MIPS_FPSET 32 +// MIPS32-MFP32SF:#define _MIPS_SPFPSET 16 // MIPS32-MFP32SF:#define __mips_fpr 0 // RUN: %clang_cc1 -target-feature +fp64 \ // RUN: -E -dM -triple=mips64-none-none < /dev/null \ // RUN: | FileCheck -match-full-lines -check-prefix MIPS64-MFP64 %s // MIPS64-MFP64:#define _MIPS_FPSET 32 +// MIPS64-MFP64:#define _MIPS_SPFPSET 32 // MIPS64-MFP64:#define __mips_fpr 64 // RUN: %clang_cc1 -target-feature -fp64 -target-feature +single-float \ // RUN: -E -dM -triple=mips64-none-none < /dev/null \ // RUN: | FileCheck -match-full-lines -check-prefix MIPS64-NOMFP64 %s // MIPS64-NOMFP64:#define _MIPS_FPSET 32 +// MIPS64-NOMFP64:#define _MIPS_SPFPSET 32 // MIPS64-NOMFP64:#define __mips_fpr 32 // RUN: %clang_cc1 -target-cpu mips32r6 \ @@ -1749,6 +1775,7 @@ // RUN: -E -dM -triple=mips64-none-none < /dev/null \ // RUN: | FileCheck -match-full-lines -check-prefix MIPS-XXR6 %s // MIPS-XXR6:#define _MIPS_FPSET 32 +// MIPS-XXR6:#define _MIPS_SPFPSET 32 // MIPS-XXR6:#define __mips_fpr 64 // MIPS-XXR6:#define __mips_nan2008 1 diff --git a/clang/test/Preprocessor/init-x86.c b/clang/test/Preprocessor/init-x86.c index 58be9b7165717..1268419e18a5c 100644 --- a/clang/test/Preprocessor/init-x86.c +++ b/clang/test/Preprocessor/init-x86.c @@ -802,9 +802,6 @@ // X86_64H:#define __x86_64h 1 // X86_64H:#define __x86_64h__ 1 -// RUN: %clang -xc - -E -dM -mcmodel=medium --target=i386-unknown-linux < /dev/null | FileCheck -match-full-lines -check-prefix X86_MEDIUM %s -// X86_MEDIUM:#define __code_model_medium__ 1 - // RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=x86_64-none-none-gnux32 < /dev/null | FileCheck -match-full-lines -check-prefix X32 %s // RUN: %clang_cc1 -x c++ -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=x86_64-none-none-gnux32 < /dev/null | FileCheck -match-full-lines -check-prefix X32 -check-prefix X32-CXX %s // diff --git a/clang/test/Preprocessor/init.c b/clang/test/Preprocessor/init.c index 59c5122afe1e4..a0a2879cb58c7 100644 --- a/clang/test/Preprocessor/init.c +++ b/clang/test/Preprocessor/init.c @@ -1454,6 +1454,13 @@ // RUN: %clang_cc1 -triple lanai-unknown-unknown -E -dM < /dev/null | FileCheck -match-full-lines -check-prefix LANAI %s // LANAI: #define __lanai__ 1 // +// RUN: %clang_cc1 -triple=aarch64-unknown-haiku -E -dM < /dev/null | FileCheck -match-full-lines -check-prefix HAIKU %s +// RUN: %clang_cc1 -triple=arm-unknown-haiku -E -dM < /dev/null | FileCheck -match-full-lines -check-prefix HAIKU %s +// RUN: %clang_cc1 -triple=riscv64-unknown-haiku -E -dM < /dev/null | FileCheck -match-full-lines -check-prefix HAIKU %s +// RUN: %clang_cc1 -triple=x86_64-unknown-haiku -E -dM < /dev/null | FileCheck -match-full-lines -check-prefix HAIKU %s +// RUN: %clang_cc1 -triple=i386-unknown-haiku -E -dM < /dev/null | FileCheck -match-full-lines -check-prefix HAIKU %s +// HAIKU: #define __HAIKU__ 1 +// // RUN: %clang_cc1 -E -dM -ffreestanding -triple=amd64-unknown-openbsd6.1 < /dev/null | FileCheck -match-full-lines -check-prefix OPENBSD %s // RUN: %clang_cc1 -E -dM -ffreestanding -triple=aarch64-unknown-openbsd6.1 < /dev/null | FileCheck -match-full-lines -check-prefix OPENBSD %s // RUN: %clang_cc1 -E -dM -ffreestanding -triple=arm-unknown-openbsd6.1-gnueabi < /dev/null | FileCheck -match-full-lines -check-prefix OPENBSD %s diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 242197e3f129a..3a0435f9c9790 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -33,6 +33,8 @@ // CHECK-NOT: __riscv_xcvsimd {{.*$}} // CHECK-NOT: __riscv_xsfcie {{.*$}} // CHECK-NOT: __riscv_xsfvcp {{.*$}} +// CHECK-NOT: __riscv_xsfqmaccdod {{.*$}} +// CHECK-NOT: __riscv_xsfvqmaccqoq {{.*$}} // CHECK-NOT: __riscv_xtheadba {{.*$}} // CHECK-NOT: __riscv_xtheadbb {{.*$}} // CHECK-NOT: __riscv_xtheadbs {{.*$}} @@ -323,6 +325,22 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-XSFVCP-EXT %s // CHECK-XSFVCP-EXT: __riscv_xsfvcp 1000000{{$}} +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32ixsfvqmaccdod -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVQMACCDOD-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64ixsfvqmaccdod -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVQMACCDOD-EXT %s +// CHECK-XSFVQMACCDOD-EXT: __riscv_xsfvqmaccdod 1000000{{$}} + +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32ixsfvqmaccqoq -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVQMACCQOQ-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64ixsfvqmaccqoq -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVQMACCQOQ-EXT %s +// CHECK-XSFVQMACCQOQ-EXT: __riscv_xsfvqmaccqoq 1000000{{$}} + // RUN: %clang --target=riscv32-unknown-linux-gnu \ // RUN: -march=rv32ixtheadba -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-XTHEADBA-EXT %s @@ -1228,3 +1246,15 @@ // RUN: -march=rv64i_zve32x_zvkt1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKT-EXT %s // CHECK-ZVKT-EXT: __riscv_zvkt 1000000{{$}} + +// RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \ +// RUN: -o - | FileCheck %s --check-prefix=CHECK-MISALIGNED-AVOID +// RUN: %clang --target=riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \ +// RUN: -o - | FileCheck %s --check-prefix=CHECK-MISALIGNED-AVOID +// CHECK-MISALIGNED-AVOID: __riscv_misaligned_avoid 1 + +// RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -E -dM %s \ +// RUN: -munaligned-access -o - | FileCheck %s --check-prefix=CHECK-MISALIGNED-FAST +// RUN: %clang --target=riscv64-unknown-linux-gnu -march=rv64i -E -dM %s \ +// RUN: -munaligned-access -o - | FileCheck %s --check-prefix=CHECK-MISALIGNED-FAST +// CHECK-MISALIGNED-FAST: __riscv_misaligned_fast 1 diff --git a/clang/test/Sema/aarch64-sve-types.c b/clang/test/Sema/aarch64-sve-types.c index dc327d380456f..4525e71de6eba 100644 --- a/clang/test/Sema/aarch64-sve-types.c +++ b/clang/test/Sema/aarch64-sve-types.c @@ -34,8 +34,8 @@ void f(void) { int size_f64[sizeof(__SVFloat64_t) == 0 ? 1 : -1]; // expected-error {{invalid application of 'sizeof' to sizeless type '__SVFloat64_t'}} int align_f64[__alignof__(__SVFloat64_t) == 16 ? 1 : -1]; // expected-error {{invalid application of '__alignof' to sizeless type '__SVFloat64_t'}} - int size_bf16[sizeof(__SVBFloat16_t) == 0 ? 1 : -1]; // expected-error {{invalid application of 'sizeof' to sizeless type '__SVBFloat16_t'}} - int align_bf16[__alignof__(__SVBFloat16_t) == 16 ? 1 : -1]; // expected-error {{invalid application of '__alignof' to sizeless type '__SVBFloat16_t'}} + int size_bf16[sizeof(__SVBfloat16_t) == 0 ? 1 : -1]; // expected-error {{invalid application of 'sizeof' to sizeless type '__SVBfloat16_t'}} + int align_bf16[__alignof__(__SVBfloat16_t) == 16 ? 1 : -1]; // expected-error {{invalid application of '__alignof' to sizeless type '__SVBfloat16_t'}} int size_b8[sizeof(__SVBool_t) == 0 ? 1 : -1]; // expected-error {{invalid application of 'sizeof' to sizeless type '__SVBool_t'}} int align_b8[__alignof__(__SVBool_t) == 2 ? 1 : -1]; // expected-error {{invalid application of '__alignof' to sizeless type '__SVBool_t'}} diff --git a/clang/test/Sema/attr-arm-sve-vector-bits.c b/clang/test/Sema/attr-arm-sve-vector-bits.c index 08780b3e11a6b..d34b13a74df6d 100644 --- a/clang/test/Sema/attr-arm-sve-vector-bits.c +++ b/clang/test/Sema/attr-arm-sve-vector-bits.c @@ -25,7 +25,7 @@ typedef __SVFloat64_t svfloat64_t; #if defined(__ARM_FEATURE_SVE_BF16) typedef __bf16 bfloat16_t; -typedef __SVBFloat16_t svbfloat16_t; +typedef __SVBfloat16_t svbfloat16_t; #endif typedef __SVBool_t svbool_t; diff --git a/clang/test/Sema/attr-preferred-type.cpp b/clang/test/Sema/attr-preferred-type.cpp new file mode 100644 index 0000000000000..dfa7e636c21e9 --- /dev/null +++ b/clang/test/Sema/attr-preferred-type.cpp @@ -0,0 +1,19 @@ +// RUN: %clang_cc1 -verify %s + +struct A { + enum E : unsigned {}; + enum E2 : int {}; + [[clang::preferred_type(E)]] unsigned b : 2; + [[clang::preferred_type(E)]] int b2 : 2; + [[clang::preferred_type(E2)]] const unsigned b3 : 2; + [[clang::preferred_type(bool)]] unsigned b4 : 1; + [[clang::preferred_type(bool)]] unsigned b5 : 2; + [[clang::preferred_type()]] unsigned b6 : 2; + // expected-error@-1 {{'preferred_type' attribute takes one argument}} + [[clang::preferred_type]] unsigned b7 : 2; + // expected-error@-1 {{'preferred_type' attribute takes one argument}} + [[clang::preferred_type(E, int)]] unsigned b8 : 2; + // expected-error@-1 {{expected ')'}} + // expected-error@-2 {{expected ','}} + // expected-warning@-3 {{unknown attribute 'int' ignored}} +}; diff --git a/clang/test/Sema/builtin-memcpy.c b/clang/test/Sema/builtin-memcpy.c new file mode 100644 index 0000000000000..2a55e78034a02 --- /dev/null +++ b/clang/test/Sema/builtin-memcpy.c @@ -0,0 +1,22 @@ +// RUN: %clang_cc1 %s -triple x86_64-unknown-linux -fsyntax-only -verify=c +// RUN: %clang_cc1 -x c++ %s -triple x86_64-unknown-linux -fsyntax-only -verify=cxx + +// cxx-no-diagnostics + + +/// Zero-sized structs should not crash. +int b() { + struct { } a[10]; + __builtin_memcpy(&a[2], a, 2); // c-warning {{buffer has size 0, but size argument is 2}} + return 0; +} + +#ifdef __cplusplus +// FIXME: This is UB and GCC correctly diagnoses it. Clang should do the same. +constexpr int b2() { + struct { } a[10]; + __builtin_memcpy(&a[2], a, 2); + return 0; +} +static_assert(b2() == 0, ""); +#endif diff --git a/clang/test/Sema/c2x-expr-range.c b/clang/test/Sema/c2x-expr-range.c index 73683e6bfe684..eff0b7cd4d9f5 100644 --- a/clang/test/Sema/c2x-expr-range.c +++ b/clang/test/Sema/c2x-expr-range.c @@ -12,3 +12,15 @@ void test1(int *a) { void test2(__uint128_t *a) { (void)(*a >> ((__uint128_t)__UINT64_MAX__ + 1) <= 0); // expected-warning {{shift count >= width of type}} } + +// Regression test for bug where a faulty warning was given. We don't expect to +// see any warning in this case. +_BitInt(128) test3(_BitInt(128) a) { + return a << 12wb; +} + +// Similar to test3 above, but with a too large shift count. We expect to see a +// warning in this case. +_BitInt(128) test4(_BitInt(128) a) { + return a << 129wb; // expected-warning {{shift count >= width of type}} +} diff --git a/clang/test/Sema/complex-imag.c b/clang/test/Sema/complex-imag.c index 69121271f4b78..8014addf4d3a4 100644 --- a/clang/test/Sema/complex-imag.c +++ b/clang/test/Sema/complex-imag.c @@ -27,3 +27,9 @@ void f4(void) { double *c = &__real a; double *d = &__imag a; } + +// PR69218 +int f5(void) { + float _Complex a; + return (0 < &__real__ a) && (0 < &__imag__ a); +} diff --git a/clang/test/Sema/riscv-rvv-lax-vector-conversions.c b/clang/test/Sema/riscv-rvv-lax-vector-conversions.c index 8ab01620b82aa..bc731f90f6a9a 100644 --- a/clang/test/Sema/riscv-rvv-lax-vector-conversions.c +++ b/clang/test/Sema/riscv-rvv-lax-vector-conversions.c @@ -33,8 +33,12 @@ void rvv_allowed_with_integer_lax_conversions() { // -flax-vector-conversions={integer,all}. fi32 = si64; // lax-vector-none-error@-1 {{assigning to 'rvv_fixed_int32m1_t' (vector of 16 'int' values) from incompatible type}} + // lax-vector-integer-error@-2 {{assigning to 'rvv_fixed_int32m1_t' (vector of 16 'int' values) from incompatible type}} + // lax-vector-all-error@-3 {{assigning to 'rvv_fixed_int32m1_t' (vector of 16 'int' values) from incompatible type}} si64 = fi32; // lax-vector-none-error@-1 {{assigning to 'vint64m1_t' (aka '__rvv_int64m1_t') from incompatible type}} + // lax-vector-integer-error@-2 {{assigning to 'vint64m1_t' (aka '__rvv_int64m1_t') from incompatible type}} + // lax-vector-all-error@-3 {{assigning to 'vint64m1_t' (aka '__rvv_int64m1_t') from incompatible type}} } void rvv_allowed_with_all_lax_conversions() { @@ -46,9 +50,11 @@ void rvv_allowed_with_all_lax_conversions() { ff32 = sf64; // lax-vector-none-error@-1 {{assigning to 'rvv_fixed_float32m1_t' (vector of 16 'float' values) from incompatible type}} // lax-vector-integer-error@-2 {{assigning to 'rvv_fixed_float32m1_t' (vector of 16 'float' values) from incompatible type}} + // lax-vector-all-error@-3 {{assigning to 'rvv_fixed_float32m1_t' (vector of 16 'float' values) from incompatible type}} sf64 = ff32; // lax-vector-none-error@-1 {{assigning to 'vfloat64m1_t' (aka '__rvv_float64m1_t') from incompatible type}} // lax-vector-integer-error@-2 {{assigning to 'vfloat64m1_t' (aka '__rvv_float64m1_t') from incompatible type}} + // lax-vector-all-error@-3 {{assigning to 'vfloat64m1_t' (aka '__rvv_float64m1_t') from incompatible type}} } void gnu_allowed_with_integer_lax_conversions() { diff --git a/clang/test/Sema/rvv-required-features-invalid.c b/clang/test/Sema/rvv-required-features-invalid.c index 0d0d00764a31e..56f201a507ef7 100644 --- a/clang/test/Sema/rvv-required-features-invalid.c +++ b/clang/test/Sema/rvv-required-features-invalid.c @@ -15,3 +15,11 @@ void test_vsoxei64_v_i8m1(int8_t *base, vuint64m8_t bindex, vint8m1_t value, siz void test_xsfvcp_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) { __riscv_sf_vc_x_se_u64m1(1, 1, 1, rs1, vl); // expected-error {{call to undeclared function '__riscv_sf_vc_x_se_u64m1'}} } + +void test_xsfvqmaccdod() { + __riscv_sf_vqmacc_2x8x2(); // expected-error {{call to undeclared function '__riscv_sf_vqmacc_2x8x2'}} +} + +void test_xsfvqmaccqoq() { + __riscv_sf_vqmacc_4x8x4(); // expected-error {{call to undeclared function '__riscv_sf_vqmacc_4x8x4'}} +} diff --git a/clang/test/Sema/rvv-required-features.c b/clang/test/Sema/rvv-required-features.c index c3b7965599e68..ed665c8ecbd49 100644 --- a/clang/test/Sema/rvv-required-features.c +++ b/clang/test/Sema/rvv-required-features.c @@ -1,5 +1,6 @@ // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp %s -fsyntax-only -verify +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp \ +// RUN: -target-feature +xsfvqmaccdod -target-feature +xsfvqmaccqoq %s -fsyntax-only -verify // expected-no-diagnostics @@ -17,3 +18,11 @@ void test_vsoxei64_v_i8m1(int8_t *base, vuint64m8_t bindex, vint8m1_t value, siz void test_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) { __riscv_sf_vc_x_se_u64m1(1, 1, 1, rs1, vl); } + +void test_xsfvqmaccdod(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) { + __riscv_sf_vqmacc_2x8x2(vd, vs1, vs2, vl); +} + +void test_xsfvqmaccqoq(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) { + __riscv_sf_vqmacc_4x8x4(vd, vs1, vs2, vl); +} diff --git a/clang/test/Sema/thread_local.c b/clang/test/Sema/thread_local.c new file mode 100644 index 0000000000000..a0de0aa4e39a6 --- /dev/null +++ b/clang/test/Sema/thread_local.c @@ -0,0 +1,19 @@ +// RUN: %clang_cc1 -fsyntax-only -std=c23 %s -verify + +// Ensure that thread_local and _Thread_local are synonyms in C23 and both +// restrict local variables to be explicitly static or extern. +void func(void) { + // FIXME: it would be nice if the diagnostic said 'thread_local' in this case. + thread_local int i = 12; // expected-error {{'_Thread_local' variables must have global storage}} + _Thread_local int j = 13; // expected-error {{'_Thread_local' variables must have global storage}} + + static thread_local int k = 14; + static _Thread_local int l = 15; + + extern thread_local int m; + extern thread_local int n; +} + +// This would previously fail because the tls models were different. +extern thread_local unsigned a; +_Thread_local unsigned a = 0; diff --git a/clang/test/Sema/vla-ext.c b/clang/test/Sema/vla-ext.c new file mode 100644 index 0000000000000..4ad96d97901c9 --- /dev/null +++ b/clang/test/Sema/vla-ext.c @@ -0,0 +1,24 @@ +/* RUN: %clang_cc1 -verify=off -std=c89 %s + * RUN: %clang_cc1 -verify=off -Wall -std=c89 %s + * RUN: %clang_cc1 -verify -pedantic -std=c89 %s + * RUN: %clang_cc1 -verify -Wvla-extension -std=c89 %s + * RUN: %clang_cc1 -verify=off -Wvla-cxx-extension -std=c89 %s + * RUN: %clang_cc1 -verify=off -pedantic -std=c99 %s + * RUN: %clang_cc1 -verify=off -Wall -std=c99 %s + * RUN: %clang_cc1 -verify=off -std=c99 -Wvla-extension %s + * The next run line still issues the extension warning because VLAs are an + * extension in C89, but the line after it will issue the congratulatory + * diagnostic. + * RUN: %clang_cc1 -verify -Wvla -std=c89 %s + * RUN: %clang_cc1 -verify=wvla -Wvla -std=c99 %s + */ + +/* off-no-diagnostics */ + +void func(int n) { + int array[n]; /* expected-warning {{variable length arrays are a C99 feature}} + wvla-warning {{variable length array used}} + */ + (void)array; +} + diff --git a/clang/test/Sema/vla.cpp b/clang/test/Sema/vla.cpp index f7d2669fb499b..d4f74d8c14edf 100644 --- a/clang/test/Sema/vla.cpp +++ b/clang/test/Sema/vla.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 %s -verify -fsyntax-only +// RUN: %clang_cc1 %s -verify -fsyntax-only -Wno-vla void f1(int n) { typedef int x[n]; diff --git a/clang/test/Sema/wasm-refs-and-tables.c b/clang/test/Sema/wasm-refs-and-tables.c index 1fee2f83b8e4c..dd8536c52cd03 100644 --- a/clang/test/Sema/wasm-refs-and-tables.c +++ b/clang/test/Sema/wasm-refs-and-tables.c @@ -87,7 +87,7 @@ __externref_t func(__externref_t ref) { static __externref_t(*lt4)[0]; // expected-error {{cannot form a pointer to a WebAssembly table}} // conly-error@+2 {{cannot use WebAssembly table as a function parameter}} // cpp-error@+1 {{no matching function for call to 'illegal_argument_1'}} - illegal_argument_1(table); + illegal_argument_1(table); varargs(1, table); // expected-error {{cannot use WebAssembly table as a function parameter}} table == 1; // expected-error {{invalid operands to binary expression ('__attribute__((address_space(1))) __externref_t[0]' and 'int')}} 1 >= table; // expected-error {{invalid operands to binary expression ('int' and '__attribute__((address_space(1))) __externref_t[0]')}} @@ -97,7 +97,7 @@ __externref_t func(__externref_t ref) { 1 && table; // expected-error {{invalid operands to binary expression ('int' and '__attribute__((address_space(1))) __externref_t[0]')}} table || 1; // expected-error {{invalid operands to binary expression ('__attribute__((address_space(1))) __externref_t[0]' and 'int')}} 1 ? table : table; // expected-error {{cannot use a WebAssembly table within a branch of a conditional expression}} - table ? : other_table; // expected-error {{cannot use a WebAssembly table within a branch of a conditional expression}} + table ? : other_table; // expected-error {{cannot use a WebAssembly table within a branch of a conditional expression}} (void *)table; // expected-error {{cannot cast from a WebAssembly table}} void *u; u = table; // expected-error {{cannot assign a WebAssembly table}} @@ -108,9 +108,11 @@ __externref_t func(__externref_t ref) { table[0]; // expected-error {{cannot subscript a WebAssembly table}} table[0] = ref; // expected-error {{cannot subscript a WebAssembly table}} - int i = 0; - __externref_t oh_no_vlas[i]; // expected-error {{WebAssembly table cannot be declared within a function}} - + int i = 0; // cpp-note {{declared here}} + __externref_t oh_no_vlas[i]; // expected-error {{WebAssembly table cannot be declared within a function}} \ + cpp-warning {{variable length arrays in C++ are a Clang extension}} \ + cpp-note {{read of non-const variable 'i' is not allowed in a constant expression}} + return ref; } diff --git a/clang/test/SemaCUDA/call-stack-for-deferred-err.cu b/clang/test/SemaCUDA/call-stack-for-deferred-err.cu index 35f71dd0f1246..76bb5116ea283 100644 --- a/clang/test/SemaCUDA/call-stack-for-deferred-err.cu +++ b/clang/test/SemaCUDA/call-stack-for-deferred-err.cu @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple nvptx64-nvidia-cuda -fcuda-is-device -fsyntax-only -verify %s +// RUN: %clang_cc1 -triple nvptx64-nvidia-cuda -fcuda-is-device -fsyntax-only -verify -Wno-vla %s #include "Inputs/cuda.h" diff --git a/clang/test/SemaCUDA/no-call-stack-for-immediate-errs.cu b/clang/test/SemaCUDA/no-call-stack-for-immediate-errs.cu index f7e9eb7e9211d..6b967d8901322 100644 --- a/clang/test/SemaCUDA/no-call-stack-for-immediate-errs.cu +++ b/clang/test/SemaCUDA/no-call-stack-for-immediate-errs.cu @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple nvptx64-nvidia-cuda -fcuda-is-device -fsyntax-only -verify %s +// RUN: %clang_cc1 -triple nvptx64-nvidia-cuda -fcuda-is-device -fsyntax-only -verify -Wno-vla %s #include "Inputs/cuda.h" diff --git a/clang/test/SemaCUDA/vla.cu b/clang/test/SemaCUDA/vla.cu index cf3054cd8e95f..935fa50766128 100644 --- a/clang/test/SemaCUDA/vla.cu +++ b/clang/test/SemaCUDA/vla.cu @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -triple nvptx64-nvidia-cuda -fcuda-is-device -verify %s -// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -DHOST %s +// RUN: %clang_cc1 -triple nvptx64-nvidia-cuda -fcuda-is-device -verify -Wno-vla %s +// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -DHOST -Wno-vla %s #ifndef __CUDA_ARCH__ // expected-no-diagnostics diff --git a/clang/test/SemaCXX/PR10177.cpp b/clang/test/SemaCXX/PR10177.cpp index 0d2e792f5227f..25cb9161e2d5c 100644 --- a/clang/test/SemaCXX/PR10177.cpp +++ b/clang/test/SemaCXX/PR10177.cpp @@ -45,15 +45,16 @@ int main() { } namespace N { - template struct S { static int n; }; + template struct S { static int n; }; // expected-note {{declared here}} template int S::n = 5; void g(int*); template int f() { - int k[S::n]; + int k[S::n]; // expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{read of non-const variable 'n' is not allowed in a constant expression}} g(k); return k[3]; } - int j = f(); + int j = f(); // expected-note {{in instantiation of function template specialization 'N::f' requested here}} } #else diff --git a/clang/test/SemaCXX/alias-template.cpp b/clang/test/SemaCXX/alias-template.cpp index c27c79ebd7cb6..5189405e23db5 100644 --- a/clang/test/SemaCXX/alias-template.cpp +++ b/clang/test/SemaCXX/alias-template.cpp @@ -31,12 +31,14 @@ namespace IllegalSyntax { namespace VariableLengthArrays { template using T = int[42]; // ok - int n = 32; - template using T = int[n]; // expected-error {{variable length array declaration not allowed at file scope}} + int n = 32; // expected-note {{declared here}} + template using T = int[n]; // expected-error {{variable length array declaration not allowed at file scope}} \ + expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{read of non-const variable 'n' is not allowed in a constant expression}} const int m = 42; template using U = int[m]; - template using U = int[42]; // expected-note {{previous definition}} + template using U = int[42]; // expected-note {{previous definition}} template using U = int; // expected-error {{type alias template redefinition with different types ('int' vs 'int[42]')}} } diff --git a/clang/test/SemaCXX/anonymous-struct.cpp b/clang/test/SemaCXX/anonymous-struct.cpp index e46bdc28d5059..e1db98d2b2f50 100644 --- a/clang/test/SemaCXX/anonymous-struct.cpp +++ b/clang/test/SemaCXX/anonymous-struct.cpp @@ -133,6 +133,7 @@ namespace ValidButUnsupported { int arr[&f ? 1 : 2]; #if __cplusplus < 201103L // expected-warning@-2 {{folded to constant}} + // expected-warning@-3 {{variable length arrays in C++ are a Clang extension}} #endif } C; // expected-note {{by this typedef}} } diff --git a/clang/test/SemaCXX/bitfield-width.c b/clang/test/SemaCXX/bitfield-width.c deleted file mode 100644 index 7b4e4444c245b..0000000000000 --- a/clang/test/SemaCXX/bitfield-width.c +++ /dev/null @@ -1,42 +0,0 @@ -// RUN: %clang_cc1 -Wconversion -fsyntax-only -verify %s -// RUN: %clang_cc1 -Wbitfield-conversion -fsyntax-only -verify %s -// RUN: %clang_cc1 -triple armebv7-unknown-linux -Wbitfield-conversion \ -// RUN: -fsyntax-only -verify %s -// RUN: %clang_cc1 -triple arm64-unknown-linux -Wbitfield-conversion \ -// RUN: -fsyntax-only -verify %s -// RUN: %clang_cc1 -triple arm-unknown-linux -Wbitfield-conversion \ -// RUN: -fsyntax-only -verify %s -// RUN: %clang_cc1 -triple aarch64-unknown-linux -Wbitfield-conversion \ -// RUN: -fsyntax-only -verify %s -// RUN: %clang_cc1 -triple mipsel-unknown-linux -Wbitfield-conversion \ -// RUN: -fsyntax-only -verify %s -// RUN: %clang_cc1 -triple mips64el-unknown-linux -Wbitfield-conversion \ -// RUN: -fsyntax-only -verify %s - -typedef struct _xx { - int bf:9; // expected-note 3{{declared here}} - } xx, *pxx; - - xx vxx; - - void foo1(int x) { - vxx.bf = x; // expected-warning{{conversion from 'int' (32 bits) to bit-field 'bf' (9 bits) may change value}} - } - void foo2(short x) { - vxx.bf = x; // expected-warning{{conversion from 'short' (16 bits) to bit-field 'bf' (9 bits) may change value}} - } - void foo3(char x) { - vxx.bf = x; // no warning expected - } - void foo4(short x) { - vxx.bf = 0xff & x; // no warning expected - } - void foo5(short x) { - vxx.bf = 0x1ff & x; // no warning expected - } - void foo6(short x) { - vxx.bf = 0x3ff & x; // expected-warning{{conversion from 'int' (10 bits) to bit-field 'bf' (9 bits) may change value}} - } - int fee(void) { - return 0; - } diff --git a/clang/test/SemaCXX/c99-variable-length-array-cxx11.cpp b/clang/test/SemaCXX/c99-variable-length-array-cxx11.cpp index 15757f52af8b8..29a817d0409f2 100644 --- a/clang/test/SemaCXX/c99-variable-length-array-cxx11.cpp +++ b/clang/test/SemaCXX/c99-variable-length-array-cxx11.cpp @@ -18,12 +18,12 @@ struct POD { // We allow VLAs of POD types, only. void vla(int N) { // expected-note 5{{here}} - int array1[N]; // expected-warning{{variable length arrays are a C99 feature}} expected-note {{parameter 'N'}} - POD array2[N]; // expected-warning{{variable length arrays are a C99 feature}} expected-note {{parameter 'N'}} - StillPOD array3[N]; // expected-warning{{variable length arrays are a C99 feature}} expected-note {{parameter 'N'}} - StillPOD2 array4[N][3]; // expected-warning{{variable length arrays are a C99 feature}} expected-note {{parameter 'N'}} + int array1[N]; // expected-warning{{variable length arrays in C++ are a Clang extension}} expected-note {{parameter 'N'}} + POD array2[N]; // expected-warning{{variable length arrays in C++ are a Clang extension}} expected-note {{parameter 'N'}} + StillPOD array3[N]; // expected-warning{{variable length arrays in C++ are a Clang extension}} expected-note {{parameter 'N'}} + StillPOD2 array4[N][3]; // expected-warning{{variable length arrays in C++ are a Clang extension}} expected-note {{parameter 'N'}} NonPOD array5[N]; // expected-error{{no matching constructor for initialization of 'NonPOD[N]'}} - // expected-warning@-1{{variable length arrays are a C99 feature}} expected-note@-1 {{parameter 'N'}} + // expected-warning@-1{{variable length arrays in C++ are a Clang extension}} expected-note@-1 {{parameter 'N'}} // expected-note@-16{{candidate constructor not viable}} // expected-note@-18{{candidate constructor (the implicit copy constructor) not viable}} // expected-note@-19{{candidate constructor (the implicit move constructor) not viable}} diff --git a/clang/test/SemaCXX/c99-variable-length-array.cpp b/clang/test/SemaCXX/c99-variable-length-array.cpp index 7885af2b403ed..82ddb0fd2e233 100644 --- a/clang/test/SemaCXX/c99-variable-length-array.cpp +++ b/clang/test/SemaCXX/c99-variable-length-array.cpp @@ -18,16 +18,16 @@ struct POD { // We allow VLAs of POD types, only. void vla(int N) { - int array1[N]; // expected-warning{{variable length arrays are a C99 feature}} - POD array2[N]; // expected-warning{{variable length arrays are a C99 feature}} - NonPOD array3[N]; // expected-warning{{variable length arrays are a C99 feature}} - NonPOD2 array4[N][3]; // expected-warning{{variable length arrays are a C99 feature}} + int array1[N]; // expected-warning{{variable length arrays in C++ are a Clang extension}} + POD array2[N]; // expected-warning{{variable length arrays in C++ are a Clang extension}} + NonPOD array3[N]; // expected-warning{{variable length arrays in C++ are a Clang extension}} + NonPOD2 array4[N][3]; // expected-warning{{variable length arrays in C++ are a Clang extension}} } /// Warn about VLAs in templates. template void vla_in_template(int N, T t) { - int array1[N]; // expected-warning{{variable length arrays are a C99 feature}} + int array1[N]; // expected-warning{{variable length arrays in C++ are a Clang extension}} } struct HasConstantValue { @@ -40,7 +40,7 @@ struct HasNonConstantValue { template void vla_in_template(T t) { - int array2[T::value]; // expected-warning{{variable length arrays are a C99 feature}} + int array2[T::value]; // expected-warning{{variable length arrays in C++ are a Clang extension}} } template void vla_in_template(HasConstantValue); @@ -51,16 +51,16 @@ template struct X0 { }; // Cannot use any variably-modified type with a template parameter or // argument. void inst_with_vla(int N) { - int array[N]; // expected-warning{{variable length arrays are a C99 feature}} + int array[N]; // expected-warning{{variable length arrays in C++ are a Clang extension}} X0<__typeof__(array)> x0a; // expected-error{{variably modified type 'typeof (array)' (aka 'int[N]') cannot be used as a template argument}} } template struct X1 { template // expected-error{{non-type template parameter of variably modified type 'int (&)[HasNonConstantValue::value]'}} \ - // expected-warning{{variable length arrays are a C99 feature}} + // expected-warning{{variable length arrays in C++ are a Clang extension}} struct Inner { - + }; }; @@ -73,7 +73,7 @@ template void accept_array(T (&array)[N]); // expected-note{{candidate template ignored: could not match 'T[N]' against 'int[N]'}} void test_accept_array(int N) { - int array[N]; // expected-warning{{variable length arrays are a C99 feature}} + int array[N]; // expected-warning{{variable length arrays in C++ are a Clang extension}} accept_array(array); // expected-error{{no matching function for call to 'accept_array'}} } @@ -83,7 +83,7 @@ void local_classes(int N) { int size; int array[N]; // expected-error{{fields must have a constant size: 'variable length array in structure' extension will never be supported}} \ // expected-error{{reference to local variable 'N' declared in enclosing function 'local_classes'}} \ - // expected-warning{{variable length arrays are a C99 feature}} + // expected-warning{{variable length arrays in C++ are a Clang extension}} }; } @@ -93,7 +93,7 @@ namespace PR7206 { float left; float right; }; - struct edge_info edgeInfo[x]; // expected-warning{{variable length arrays are a C99 feature}} + struct edge_info edgeInfo[x]; // expected-warning{{variable length arrays in C++ are a Clang extension}} } } @@ -101,7 +101,7 @@ namespace rdar8020206 { template void f(int i) { const unsigned value = i; - int array[value * i]; // expected-warning 2{{variable length arrays are a C99 feature}} expected-note 2{{initializer of 'value' is not a constant}} + int array[value * i]; // expected-warning 2{{variable length arrays in C++ are a Clang extension}} expected-note 2{{initializer of 'value' is not a constant}} } template void f(int); // expected-note{{instantiation of}} @@ -115,7 +115,7 @@ namespace rdar8021385 { typedef typename T::my_int my_int; void f0() { int M = 4; - my_int a[M]; // expected-warning{{variable length arrays are a C99 feature}} + my_int a[M]; // expected-warning{{variable length arrays in C++ are a Clang extension}} } }; B a; @@ -123,7 +123,7 @@ namespace rdar8021385 { namespace PR8209 { void f(int n) { - typedef int vla_type[n]; // expected-warning{{variable length arrays are a C99 feature}} + typedef int vla_type[n]; // expected-warning{{variable length arrays in C++ are a Clang extension}} (void)new vla_type; // expected-error{{variably}} } } @@ -139,7 +139,7 @@ static const int k_cVal3 = (int)(1000*0.2f); namespace PR11744 { template int f(int n) { - T arr[3][n]; // expected-warning 3 {{variable length arrays are a C99 feature}} + T arr[3][n]; // expected-warning 3 {{variable length arrays in C++ are a Clang extension}} return 3; } int test = f(0); // expected-note {{instantiation of}} @@ -153,7 +153,7 @@ namespace pr18633 { const int A1::sz2 = 11; template void func () { - int arr[A1::sz]; // expected-warning{{variable length arrays are a C99 feature}} expected-note {{initializer of 'sz' is unknown}} + int arr[A1::sz]; // expected-warning{{variable length arrays in C++ are a Clang extension}} expected-note {{initializer of 'sz' is unknown}} } template void func2 () { diff --git a/clang/test/SemaCXX/co_await-ast.cpp b/clang/test/SemaCXX/co_await-ast.cpp index b9eae493be952..10cee21da0e87 100644 --- a/clang/test/SemaCXX/co_await-ast.cpp +++ b/clang/test/SemaCXX/co_await-ast.cpp @@ -47,13 +47,13 @@ awaitable foo() { // CHECK: |-CompoundStmt {{.*}} // CHECK: | `-ExprWithCleanups {{.*}} 'void' // CHECK: | `-CoawaitExpr {{.*}} 'void' -// CHECK: | |-CXXTemporaryObjectExpr {{.*}} 'executor':'executor' 'void (){{.*}} noexcept' zeroing +// CHECK: | |-CXXTemporaryObjectExpr {{.*}} 'executor' 'void (){{.*}} noexcept' zeroing // CHECK: | |-MaterializeTemporaryExpr {{.*}} 'result_t':'awaitable_frame::result_t' lvalue // CHECK: | | `-CXXBindTemporaryExpr {{.*}} 'result_t':'awaitable_frame::result_t' (CXXTemporary {{.*}}) // CHECK: | | `-CXXMemberCallExpr {{.*}} 'result_t':'awaitable_frame::result_t' // CHECK: | | |-MemberExpr {{.*}} '' .await_transform {{.*}} // CHECK: | | | `-DeclRefExpr {{.*}} 'std::coroutine_traits::promise_type':'awaitable_frame' lvalue Var {{.*}} '__promise' 'std::coroutine_traits::promise_type':'awaitable_frame' -// CHECK: | | `-CXXTemporaryObjectExpr {{.*}} 'executor':'executor' 'void (){{.*}} noexcept' zeroing +// CHECK: | | `-CXXTemporaryObjectExpr {{.*}} 'executor' 'void (){{.*}} noexcept' zeroing // CHECK: | |-ExprWithCleanups {{.*}} 'bool' // CHECK: | | `-CXXMemberCallExpr {{.*}} 'bool' // CHECK: | | `-MemberExpr {{.*}} '' .await_ready {{.*}} @@ -64,7 +64,7 @@ awaitable foo() { // CHECK: | | `-CXXMemberCallExpr {{.*}} 'result_t':'awaitable_frame::result_t' // CHECK: | | |-MemberExpr {{.*}} '' .await_transform {{.*}} // CHECK: | | | `-DeclRefExpr {{.*}} 'std::coroutine_traits::promise_type':'awaitable_frame' lvalue Var {{.*}} '__promise' 'std::coroutine_traits::promise_type':'awaitable_frame' -// CHECK: | | `-CXXTemporaryObjectExpr {{.*}} 'executor':'executor' 'void (){{.*}} noexcept' zeroing +// CHECK: | | `-CXXTemporaryObjectExpr {{.*}} 'executor' 'void (){{.*}} noexcept' zeroing // CHECK: | |-ExprWithCleanups {{.*}} 'void' // CHECK: | | `-CXXMemberCallExpr {{.*}} 'void' // CHECK: | | |-MemberExpr {{.*}} '' .await_suspend {{.*}} @@ -74,9 +74,9 @@ awaitable foo() { // CHECK: | | | `-CXXMemberCallExpr {{.*}} 'result_t':'awaitable_frame::result_t' // CHECK: | | | |-MemberExpr {{.*}} '' .await_transform {{.*}} // CHECK: | | | | `-DeclRefExpr {{.*}} 'std::coroutine_traits::promise_type':'awaitable_frame' lvalue Var {{.*}} '__promise' 'std::coroutine_traits::promise_type':'awaitable_frame' -// CHECK: | | | `-CXXTemporaryObjectExpr {{.*}} 'executor':'executor' 'void (){{.*}} noexcept' zeroing -// CHECK: | | `-ImplicitCastExpr {{.*}} 'std::coroutine_handle':'std::coroutine_handle' -// CHECK: | | `-CXXConstructExpr {{.*}} 'std::coroutine_handle':'std::coroutine_handle' 'void (coroutine_handle &&){{.*}} noexcept' +// CHECK: | | | `-CXXTemporaryObjectExpr {{.*}} 'executor' 'void (){{.*}} noexcept' zeroing +// CHECK: | | `-ImplicitCastExpr {{.*}} 'std::coroutine_handle' +// CHECK: | | `-CXXConstructExpr {{.*}} 'std::coroutine_handle' 'void (coroutine_handle &&){{.*}} noexcept' // CHECK: | | `-MaterializeTemporaryExpr {{.*}} 'coroutine_handle':'std::coroutine_handle' xvalue // CHECK: | | `-CallExpr {{.*}} 'coroutine_handle':'std::coroutine_handle' // CHECK: | | |-ImplicitCastExpr {{.*}} 'coroutine_handle (*)(void *) noexcept' @@ -93,6 +93,6 @@ awaitable foo() { // CHECK: | `-CXXMemberCallExpr {{.*}} 'result_t':'awaitable_frame::result_t' // CHECK: | |-MemberExpr {{.*}} '' .await_transform {{.*}} // CHECK: | | `-DeclRefExpr {{.*}} 'std::coroutine_traits::promise_type':'awaitable_frame' lvalue Var {{.*}} '__promise' 'std::coroutine_traits::promise_type':'awaitable_frame' -// CHECK: | `-CXXTemporaryObjectExpr {{.*}} 'executor':'executor' 'void (){{.*}} noexcept' zeroing +// CHECK: | `-CXXTemporaryObjectExpr {{.*}} 'executor' 'void (){{.*}} noexcept' zeroing // Rest of the generated coroutine statements omitted. diff --git a/clang/test/SemaCXX/constant-expression-cxx11.cpp b/clang/test/SemaCXX/constant-expression-cxx11.cpp index 8fb994224853b..9e2ae07cbe4c9 100644 --- a/clang/test/SemaCXX/constant-expression-cxx11.cpp +++ b/clang/test/SemaCXX/constant-expression-cxx11.cpp @@ -11,7 +11,7 @@ static_assert(false, "test"); // expected-error {{test}} } -int array[(long)(char *)0]; // expected-warning {{variable length arrays are a C99 feature}} \ +int array[(long)(char *)0]; // expected-warning {{variable length arrays in C++ are a Clang extension}} \ // expected-warning {{variable length array folded to constant array as an extension}} \ // expected-note {{cast that performs the conversions of a reinterpret_cast is not allowed in a constant expression}} @@ -185,7 +185,7 @@ namespace FunctionCast { constexpr int f() { return 1; } typedef double (*DoubleFn)(); typedef int (*IntFn)(); - int a[(int)DoubleFn(f)()]; // expected-error {{variable length array}} expected-warning{{C99 feature}} + int a[(int)DoubleFn(f)()]; // expected-error {{variable length array}} expected-warning{{Clang extension}} int b[(int)IntFn(f)()]; // ok } @@ -1606,7 +1606,7 @@ namespace RecursiveOpaqueExpr { namespace VLASizeof { void f(int k) { // expected-note {{here}} - int arr[k]; // expected-warning {{C99}} expected-note {{function parameter 'k'}} + int arr[k]; // expected-warning {{Clang extension}} expected-note {{function parameter 'k'}} constexpr int n = 1 + sizeof(arr) // expected-error {{constant expression}} * 3; diff --git a/clang/test/SemaCXX/constant-expression-cxx2a.cpp b/clang/test/SemaCXX/constant-expression-cxx2a.cpp index 09f17d5b38949..e4d97dcb73562 100644 --- a/clang/test/SemaCXX/constant-expression-cxx2a.cpp +++ b/clang/test/SemaCXX/constant-expression-cxx2a.cpp @@ -1492,3 +1492,9 @@ class B{ class D : B{}; // expected-error {{deleted function '~D' cannot override a non-deleted function}} // expected-note@-1 {{destructor of 'D' is implicitly deleted because base class 'B' has an inaccessible destructor}} } + +namespace GH67317 { + constexpr unsigned char a = // expected-error {{constexpr variable 'a' must be initialized by a constant expression}} \ + // expected-note {{subobject of type 'const unsigned char' is not initialized}} + __builtin_bit_cast(unsigned char, *new char[3][1]); +}; diff --git a/clang/test/SemaCXX/consteval-cleanup.cpp b/clang/test/SemaCXX/consteval-cleanup.cpp index ddc56174b484f..499c45db50177 100644 --- a/clang/test/SemaCXX/consteval-cleanup.cpp +++ b/clang/test/SemaCXX/consteval-cleanup.cpp @@ -21,11 +21,11 @@ void foo() { // CHECK: foo // CHECK: ExprWithCleanups // CHECK-NEXT: BinaryOperator {{.*}} 'bool' ',' - // CHECK-NEXT: BinaryOperator {{.*}} 'P':'P' ',' - // CHECK-NEXT: CXXFunctionalCastExpr {{.*}} 'A':'A' - // CHECK-NEXT: CXXBindTemporaryExpr {{.*}} 'A':'A' - // CHECK-NEXT: CXXConstructExpr {{.*}} 'A':'A' - // CHECK: ConstantExpr {{.*}} 'P':'P' + // CHECK-NEXT: BinaryOperator {{.*}} 'P' ',' + // CHECK-NEXT: CXXFunctionalCastExpr {{.*}} 'A' + // CHECK-NEXT: CXXBindTemporaryExpr {{.*}} 'A' + // CHECK-NEXT: CXXConstructExpr {{.*}} 'A' + // CHECK: ConstantExpr {{.*}} 'P' // CHECK-NEXT: value: // CHECK-NEXT: ExprWithCleanups } @@ -36,10 +36,10 @@ void foobar() { // CHECK: ExprWithCleanups // CHECK-NEXT: cleanup Block // CHECK-NEXT: BinaryOperator {{.*}} 'bool' ',' - // CHECK-NEXT: BinaryOperator {{.*}} 'P':'P' ',' + // CHECK-NEXT: BinaryOperator {{.*}} 'P' ',' // CHECK-NEXT: CallExpr // CHECK-NEXT: BlockExpr - // CHECK: ConstantExpr {{.*}} 'P':'P' + // CHECK: ConstantExpr {{.*}} 'P' // CHECK-NEXT: value: // CHECK-NEXT: ExprWithCleanups // CHECK-NOT: cleanup Block diff --git a/clang/test/SemaCXX/constexpr-array-unknown-bound.cpp b/clang/test/SemaCXX/constexpr-array-unknown-bound.cpp index 395c4cbd127b2..2b09a1cf8be70 100644 --- a/clang/test/SemaCXX/constexpr-array-unknown-bound.cpp +++ b/clang/test/SemaCXX/constexpr-array-unknown-bound.cpp @@ -15,12 +15,14 @@ struct A {int m[];} a; constexpr auto p3 = a.m; // expected-error {{constant expression}} expected-note {{without known bound}} constexpr auto p4 = a.m + 1; // expected-error {{constant expression}} expected-note {{without known bound}} -void g(int i) { - int arr[i]; +void g(int i) { // expected-note 2{{declared here}} + int arr[i]; // expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{function parameter 'i' with unknown value cannot be used in a constant expression}} constexpr auto *p = arr + 2; // expected-error {{constant expression}} expected-note {{without known bound}} // FIXME: Give a better diagnostic here. The issue is that computing // sizeof(*arr2) within the array indexing fails due to the VLA. - int arr2[2][i]; + int arr2[2][i]; // expected-warning 2{{variable length arrays in C++ are a Clang extension}} \ + expected-note {{function parameter 'i' with unknown value cannot be used in a constant expression}} constexpr int m = ((void)arr2[2], 0); // expected-error {{constant expression}} } diff --git a/clang/test/SemaCXX/constexpr-builtin-bit-cast-fp80.cpp b/clang/test/SemaCXX/constexpr-builtin-bit-cast-fp80.cpp new file mode 100644 index 0000000000000..b37b362c81e75 --- /dev/null +++ b/clang/test/SemaCXX/constexpr-builtin-bit-cast-fp80.cpp @@ -0,0 +1,66 @@ +// RUN: %clang_cc1 -verify -std=c++2a -fsyntax-only -triple i386-pc-linux-gnu %s + +// This is separate from constexpr-builtin-bit-cast.cpp because we want to +// compile for i386 so that sizeof(long double) is 12. + +typedef long double fp80x2_v __attribute__((ext_vector_type(2))); + +static_assert(sizeof(long double) == 12, ""); +static_assert(sizeof(fp80x2_v) == 32, ""); + +struct fp80x2_s { + char _data[2 * 10]; + unsigned char _pad[sizeof(fp80x2_v) - 2 * 10]; + + constexpr bool operator==(const fp80x2_s& rhs) const { + for (int i = 0; i < 2 * 10; ++i) + if (_data[i] != rhs._data[i]) + return false; + return true; + } +}; + +namespace builtin_bit_cast { + constexpr static fp80x2_v test_vec_fp80 = { 1, 2 }; + constexpr static fp80x2_s test_str_fp80 = { { 0, 0, 0, 0, 0, 0, 0, -128, -1, 63, 0, 0, 0, 0, 0, 0, 0, -128, 0, 64 }, {} }; + + // expected-error@+2 {{static assertion expression is not an integral constant expression}} + // expected-note@+1 {{constexpr bit cast involving type 'long double' is not yet supported}} + static_assert(__builtin_bit_cast(fp80x2_s, test_vec_fp80) == test_str_fp80, ""); + + // expected-error@+2 {{static assertion expression is not an integral constant expression}} + // expected-note@+1 {{constexpr bit cast involving type 'long double' is not yet supported}} + static_assert(__builtin_bit_cast(fp80x2_s, __builtin_bit_cast(fp80x2_v, test_str_fp80)) == test_str_fp80, ""); + + // expected-error@+2 {{constexpr variable 'bad_str_fp80_0' must be initialized by a constant expression}} + // expected-note@+1 {{constexpr bit cast involving type 'long double' is not yet supported}} + constexpr static char bad_str_fp80_0 = __builtin_bit_cast(fp80x2_s, test_vec_fp80)._pad[0]; + + // expected-error@+2 {{constexpr variable 'bad_str_fp80_1' must be initialized by a constant expression}} + // expected-note@+1 {{constexpr bit cast involving type 'long double' is not yet supported}} + constexpr static char bad_str_fp80_1 = __builtin_bit_cast(fp80x2_s, test_vec_fp80)._pad[1]; + + // expected-error@+2 {{constexpr variable 'bad_str_fp80_11' must be initialized by a constant expression}} + // expected-note@+1 {{constexpr bit cast involving type 'long double' is not yet supported}} + constexpr static char bad_str_fp80_11 = __builtin_bit_cast(fp80x2_s, test_vec_fp80)._pad[11]; + + // expected-error@+2 {{constexpr variable 'struct2v' must be initialized by a constant expression}} + // expected-note@+1 {{constexpr bit cast involving type 'long double' is not yet supported}} + constexpr static fp80x2_v struct2v = __builtin_bit_cast(fp80x2_v, test_str_fp80); +} + +namespace c_cast { + typedef short v12i16 __attribute((vector_size(24))); + typedef long double v2f80 __attribute((vector_size(24))); + + // FIXME: re-enable the corresponding test cases in CodeGen/const-init.c when + // constexpr bitcast with x86_fp80 is supported + + // expected-error@+2 {{constexpr variable 'b' must be initialized by a constant expression}} + // expected-note@+1 {{constexpr bit cast involving type 'long double' is not yet supported}} + constexpr static v12i16 b = (v12i16)(v2f80){1,2}; + + // expected-error@+2 {{constexpr variable 'c' must be initialized by a constant expression}} + // expected-note@+1 {{constexpr bit cast involving type 'long double' is not yet supported}} + constexpr static v2f80 c = (v2f80)(v12i16){0,0,0,-32768,16383,0,0,0,0,-32768,16384,0}; +} diff --git a/clang/test/SemaCXX/constexpr-builtin-bit-cast.cpp b/clang/test/SemaCXX/constexpr-builtin-bit-cast.cpp index a6ebe0572d063..c5b8032f40b13 100644 --- a/clang/test/SemaCXX/constexpr-builtin-bit-cast.cpp +++ b/clang/test/SemaCXX/constexpr-builtin-bit-cast.cpp @@ -463,3 +463,47 @@ static_assert(bit_cast(ld539) == fivehundredandthirtynine, ""); static_assert(round_trip<__int128_t>(34.0L)); #endif } + +namespace test_vector { + +typedef unsigned uint2 __attribute__((vector_size(2 * sizeof(unsigned)))); +typedef char byte8 __attribute__((vector_size(sizeof(unsigned long long)))); + +constexpr uint2 test_vector = { 0x0C05FEFE, 0xCAFEBABE }; + +static_assert(bit_cast(test_vector) == (LITTLE_END + ? 0xCAFEBABE0C05FEFE + : 0x0C05FEFECAFEBABE), ""); + +static_assert(round_trip(0xCAFEBABE0C05FEFEULL), ""); +static_assert(round_trip(0xCAFEBABE0C05FEFEULL), ""); + +typedef bool bool8 __attribute__((ext_vector_type(8))); +typedef bool bool9 __attribute__((ext_vector_type(9))); +typedef bool bool16 __attribute__((ext_vector_type(16))); +typedef bool bool17 __attribute__((ext_vector_type(17))); +typedef bool bool32 __attribute__((ext_vector_type(32))); +typedef bool bool128 __attribute__((ext_vector_type(128))); + +static_assert(bit_cast(bool8{1,0,1,0,1,0,1,0}) == (LITTLE_END ? 0x55 : 0xAA), ""); +static_assert(round_trip(static_cast(0)), ""); +static_assert(round_trip(static_cast(1)), ""); +static_assert(round_trip(static_cast(0x55)), ""); + +static_assert(bit_cast(bool16{1,1,1,1,1,0,0,0, 1,1,1,1,0,1,0,0}) == (LITTLE_END ? 0x2F1F : 0xF8F4), ""); + +static_assert(round_trip(static_cast(0xCAFE)), ""); +static_assert(round_trip(static_cast(0xCAFEBABE)), ""); +static_assert(round_trip(static_cast<__int128_t>(0xCAFEBABE0C05FEFEULL)), ""); + +// expected-error@+2 {{constexpr variable 'bad_bool9_to_short' must be initialized by a constant expression}} +// expected-note@+1 {{bit_cast involving type 'bool __attribute__((ext_vector_type(9)))' (vector of 9 'bool' values) is not allowed in a constant expression; element size 1 * element count 9 is not a multiple of the byte size 8}} +constexpr unsigned short bad_bool9_to_short = __builtin_bit_cast(unsigned short, bool9{1,1,0,1,0,1,0,1,0}); +// expected-error@+2 {{constexpr variable 'bad_short_to_bool9' must be initialized by a constant expression}} +// expected-note@+1 {{bit_cast involving type 'bool __attribute__((ext_vector_type(9)))' (vector of 9 'bool' values) is not allowed in a constant expression; element size 1 * element count 9 is not a multiple of the byte size 8}} +constexpr bool9 bad_short_to_bool9 = __builtin_bit_cast(bool9, static_cast(0)); +// expected-error@+2 {{constexpr variable 'bad_int_to_bool17' must be initialized by a constant expression}} +// expected-note@+1 {{bit_cast involving type 'bool __attribute__((ext_vector_type(17)))' (vector of 17 'bool' values) is not allowed in a constant expression; element size 1 * element count 17 is not a multiple of the byte size 8}} +constexpr bool17 bad_int_to_bool17 = __builtin_bit_cast(bool17, 0x0001CAFEU); + +} diff --git a/clang/test/SemaCXX/coroutine-vla.cpp b/clang/test/SemaCXX/coroutine-vla.cpp new file mode 100644 index 0000000000000..176e35f346e2b --- /dev/null +++ b/clang/test/SemaCXX/coroutine-vla.cpp @@ -0,0 +1,29 @@ +// RUN: %clang_cc1 %s -std=c++20 -fsyntax-only -Wno-vla-cxx-extension -verify +#include "Inputs/std-coroutine.h" + +struct promise; + +struct coroutine : std::coroutine_handle { + using promise_type = ::promise; +}; + +struct promise +{ + coroutine get_return_object(); + std::suspend_always initial_suspend() noexcept; + std::suspend_always final_suspend() noexcept; + void return_void(); + void unhandled_exception(); +}; + +coroutine foo(int n) { + int array[n]; // expected-error {{variable length arrays in a coroutine are not supported}} + co_return; +} + +void lambda() { + [](int n) -> coroutine { + int array[n]; // expected-error {{variable length arrays in a coroutine are not supported}} + co_return; + }(10); +} diff --git a/clang/test/SemaCXX/cxx0x-initializer-aggregates.cpp b/clang/test/SemaCXX/cxx0x-initializer-aggregates.cpp index 0350aa567f147..b74e638577c05 100644 --- a/clang/test/SemaCXX/cxx0x-initializer-aggregates.cpp +++ b/clang/test/SemaCXX/cxx0x-initializer-aggregates.cpp @@ -136,7 +136,9 @@ namespace PR24816 { namespace no_crash { class Foo; // expected-note {{forward declaration}} -void test(int size) { - Foo array[size] = {0}; // expected-error {{variable has incomplete type}} +void test(int size) { // expected-note {{declared here}} + Foo array[size] = {0}; // expected-error {{variable has incomplete type}} \ + expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{function parameter 'size' with unknown value cannot be used in a constant expression}} } } diff --git a/clang/test/SemaCXX/cxx0x-noexcept-expression.cpp b/clang/test/SemaCXX/cxx0x-noexcept-expression.cpp index 6afeeefec40da..c2b2244c117a0 100644 --- a/clang/test/SemaCXX/cxx0x-noexcept-expression.cpp +++ b/clang/test/SemaCXX/cxx0x-noexcept-expression.cpp @@ -66,15 +66,20 @@ void stmt_expr() { }))); } -void vla(bool b) { +void vla(bool b) { // expected-note 5{{declared here}} static_assert(noexcept(static_cast(0)), ""); // FIXME: This can't actually throw, but we conservatively assume any VLA // type can throw for now. - static_assert(!noexcept(static_cast(0)), ""); - static_assert(!noexcept(static_cast(0)), ""); - static_assert(!noexcept(reinterpret_cast(0)), ""); - static_assert(!noexcept((int(*)[b ? throw : 42])0), ""); - static_assert(!noexcept((int(*)[b ? throw : 42]){0}), ""); + static_assert(!noexcept(static_cast(0)), ""); // expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{function parameter 'b' with unknown value cannot be used in a constant expression}} + static_assert(!noexcept(static_cast(0)), ""); // expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{function parameter 'b' with unknown value cannot be used in a constant expression}} + static_assert(!noexcept(reinterpret_cast(0)), ""); // expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{function parameter 'b' with unknown value cannot be used in a constant expression}} + static_assert(!noexcept((int(*)[b ? throw : 42])0), ""); // expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{function parameter 'b' with unknown value cannot be used in a constant expression}} + static_assert(!noexcept((int(*)[b ? throw : 42]){0}), ""); // expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{function parameter 'b' with unknown value cannot be used in a constant expression}} } struct pr_44514 { diff --git a/clang/test/SemaCXX/cxx1y-generic-lambdas.cpp b/clang/test/SemaCXX/cxx1y-generic-lambdas.cpp index 3c2d460ab9b4a..22205db6984f0 100644 --- a/clang/test/SemaCXX/cxx1y-generic-lambdas.cpp +++ b/clang/test/SemaCXX/cxx1y-generic-lambdas.cpp @@ -24,7 +24,7 @@ int test() { L.operator()(3); L.operator()(3.14); //expected-warning{{implicit conversion}} return 0; -} +} } //end ns namespace test_conversion_to_fptr_2 { @@ -32,12 +32,12 @@ namespace test_conversion_to_fptr_2 { template struct X { T (*fp)(T) = [](auto a) { return a; }; - + }; X xi; -template +template void fooT(T t, T (*fp)(T) = [](auto a) { return a; }) { fp(t); } @@ -108,11 +108,11 @@ int test() { { auto L = [=](auto b) { - return [](auto a) { - return [=](auto c) { - return [](auto d) ->decltype(a + b + c + d) { return d; }; - }; - }; + return [](auto a) { + return [=](auto c) { + return [](auto d) ->decltype(a + b + c + d) { return d; }; + }; + }; }; int (*fp)(int) = L('8')(3)(short{}); double (*fs)(char) = L(3.14)(short{})('4'); @@ -146,12 +146,12 @@ int test() { f2(glambda); // expected-error{{no matching function}} g(glambda); // expected-error{{call to 'g' is ambiguous}} h(glambda); // OK: calls #3 since it is convertible from ID - + int& (*fpi)(int*) = [](auto* a) -> auto& { return *a; }; // OK - + } { - + auto L = [](auto a) { return a; }; int (*fp)(int) = L; fp(5); @@ -202,7 +202,7 @@ int variadic_test() { int (*fp)(int, char, double) = [](auto ... a) -> int { vfun(a...); return 4; }; fp(3, '4', 3.14); - + int (*fp2)(int, char, double) = [](auto ... a) { vfun(a...); return 4; }; fp(3, '4', 3.14); return 2; @@ -213,7 +213,7 @@ int variadic_test() { namespace conversion_operator { void test() { auto L = [](auto a) -> int { return a; }; // expected-error {{cannot initialize}} - int (*fp)(int) = L; + int (*fp)(int) = L; int (&fp2)(int) = [](auto a) { return a; }; // expected-error{{non-const lvalue}} int (&&fp3)(int) = [](auto a) { return a; }; // expected-error@-1 {{no viable conversion}} @@ -233,9 +233,9 @@ namespace conversion_operator { } namespace return_type_deduction_ok { - auto l = [](auto a) ->auto { return a; }(2); - auto l2 = [](auto a) ->decltype(auto) { return a; }(2); - auto l3 = [](auto a) { return a; }(2); + auto l = [](auto a) ->auto { return a; }(2); + auto l2 = [](auto a) ->decltype(auto) { return a; }(2); + auto l3 = [](auto a) { return a; }(2); } @@ -268,10 +268,10 @@ int test() { M(4.15); //expected-note{{instantiation}} } { - int i = 10; + int i = 10; auto L = [](auto a) { - return [](auto b) { - b = sizeof(i); //ok + return [](auto b) { + b = sizeof(i); //ok return b; }; }; @@ -287,7 +287,7 @@ int test() { auto M = L(3); M(4.15); } - + { auto L = [](auto a) ->decltype(a) { print("a = ", a, "\n"); @@ -321,7 +321,7 @@ int test() { }; }; auto M = L(3); - int (*fp)(double, int, const char*) = M; + int (*fp)(double, int, const char*) = M; fp(4.15, 3, "fv"); } @@ -367,7 +367,7 @@ int test() { { struct X { - static void foo(double d) { } + static void foo(double d) { } void test() { auto L = [](auto a) { print("a = ", a, "\n"); @@ -398,7 +398,7 @@ x.test(); // Make sure we can escape the function { struct X { - static void foo(double d) { } + static void foo(double d) { } auto test() { auto L = [](auto a) { print("a = ", a, "\n"); @@ -430,7 +430,7 @@ x.test(); { struct X { - static void foo(double d) { } + static void foo(double d) { } auto test() { auto L = [](auto a) { print("a = ", a, "\n"); @@ -464,7 +464,7 @@ x.test(); char (*np)(const char*, int, const char*, double, const char*, int) = O; np("\n3 = ", 3, "\n6.14 = ", 6.14, "\n4'123'456 = ", 4'123'456); int (*np2)(const char*, int, const char*, double, const char*, int) = O; // expected-error{{no viable conversion}} - + } } // end test() @@ -472,17 +472,17 @@ namespace wrapped_within_templates { namespace explicit_return { template int fooT(T t) { - auto L = [](auto a) -> void { + auto L = [](auto a) -> void { auto M = [](char b) -> void { auto N = [](auto c) -> void { int x = 0; - x = sizeof(a); + x = sizeof(a); x = sizeof(b); x = sizeof(c); - }; + }; N('a'); N(decltype(a){}); - }; + }; }; L(t); L(3.14); @@ -495,17 +495,17 @@ int run = fooT('a') + fooT(3.14); namespace implicit_return_deduction { template auto fooT(T t) { - auto L = [](auto a) { + auto L = [](auto a) { auto M = [](char b) { auto N = [](auto c) { int x = 0; - x = sizeof(a); + x = sizeof(a); x = sizeof(b); x = sizeof(c); - }; + }; N('a'); N(decltype(a){}); - }; + }; }; L(t); L(3.14); @@ -517,20 +517,20 @@ int run = fooT('a') + fooT(3.14); template void print(Ts ... ts) { } template auto fooV(Ts ... ts) { - auto L = [](auto ... a) { - auto M = [](decltype(a) ... b) { + auto L = [](auto ... a) { + auto M = [](decltype(a) ... b) { auto N = [](auto c) { int x = 0; - x = sizeof...(a); + x = sizeof...(a); x = sizeof...(b); x = sizeof(c); - }; + }; N('a'); N(N); N(first{}); }; M(a...); - print("a = ", a..., "\n"); + print("a = ", a..., "\n"); }; L(L, ts...); print("ts = ", ts..., "\n"); @@ -580,28 +580,28 @@ int (*np2)(const char*, int, const char*, double, const char*, int) = O; // expe -} +} namespace variadic_tests_1 { template void print(Ts ... ts) { } template F& FirstArg(F& f, Rest...) { return f; } - + template int fooV(Ts ... ts) { - auto L = [](auto ... a) -> void { - auto M = [](decltype(a) ... b) -> void { + auto L = [](auto ... a) -> void { + auto M = [](decltype(a) ... b) -> void { auto N = [](auto c) -> void { int x = 0; - x = sizeof...(a); + x = sizeof...(a); x = sizeof...(b); x = sizeof(c); - }; + }; N('a'); N(N); N(first{}); }; M(a...); - print("a = ", a..., "\n"); + print("a = ", a..., "\n"); }; L(L, ts...); print("ts = ", ts..., "\n"); @@ -613,14 +613,14 @@ int run2 = fooV(3.14, " ", '4', 5) + fooV("BC", 3, 2.77, 'A', float{}, short{}, namespace more_variadic_1 { template int fooV(Ts ... ts) { - auto L = [](auto ... a) { - auto M = [](decltype(a) ... b) -> void { + auto L = [](auto ... a) { + auto M = [](decltype(a) ... b) -> void { auto N = [](auto c) -> void { int x = 0; - x = sizeof...(a); + x = sizeof...(a); x = sizeof...(b); x = sizeof(c); - }; + }; N('a'); N(N); N(first{}); @@ -631,16 +631,16 @@ template int fooV(Ts ... ts) { auto M = L(L, ts...); decltype(L(L, ts...)) (*fp)(decltype(L), decltype(ts) ...) = L; void (*fp2)(decltype(L), decltype(ts) ...) = L(L, ts...); - + { - auto L = [](auto ... a) { - auto M = [](decltype(a) ... b) { + auto L = [](auto ... a) { + auto M = [](decltype(a) ... b) { auto N = [](auto c) -> void { int x = 0; - x = sizeof...(a); + x = sizeof...(a); x = sizeof...(b); x = sizeof(c); - }; + }; N('a'); N(N); N(first{}); @@ -669,7 +669,7 @@ int run2 = fooV(3.14, " ", '4', 5) + fooV("BC", 3, 2.77, 'A', float{}, short{}, namespace at_ns_scope_within_class_member { struct X { - static void foo(double d) { } + static void foo(double d) { } auto test() { auto L = [](auto a) { print("a = ", a, "\n"); @@ -703,13 +703,13 @@ auto O = N("\n3 = ", 3, "\n6.14 = ", 6.14, "\n4'123'456 = ", 4'123'456); char (*np)(const char*, int, const char*, double, const char*, int) = O; auto NP_result = np("\n3 = ", 3, "\n6.14 = ", 6.14, "\n4'123'456 = ", 4'123'456); int (*np2)(const char*, int, const char*, double, const char*, int) = O; // expected-error{{no viable conversion}} - + } //end at_ns_scope_within_class_member namespace at_ns_scope_within_class_template_member { struct X { - static void foo(double d) { } + static void foo(double d) { } template auto test(T = T{}) { auto L = [](auto a) { @@ -733,7 +733,7 @@ namespace at_ns_scope_within_class_template_member { }; return L; } - + }; X x; auto L = x.test(); @@ -745,24 +745,24 @@ auto O = N("\n3 = ", 3, "\n6.14 = ", 6.14, "\n4'123'456 = ", 4'123'456); char (*np)(const char*, int, const char*, double, const char*, int) = O; auto NP_result = np("\n3 = ", 3, "\n6.14 = ", 6.14, "\n4'123'456 = ", 4'123'456); int (*np2)(const char*, int, const char*, double, const char*, int) = O; // expected-error{{no viable conversion}} - + } //end at_ns_scope_within_class_member namespace nested_generic_lambdas_123 { void test() { auto L = [](auto a) -> int { - auto M = [](auto b, decltype(a) b2) -> int { + auto M = [](auto b, decltype(a) b2) -> int { return 1; }; M(a, a); }; - L(3); + L(3); } template void foo(T) { - auto L = [](auto a) { return a; }; + auto L = [](auto a) { return a; }; } -template void foo(int); +template void foo(int); } // end ns nested_generic_lambdas_123 namespace nested_fptr_235 { @@ -796,7 +796,7 @@ int test() { { auto L = [](auto ... As) { - return [](auto b) ->decltype(b) { + return [](auto b) ->decltype(b) { vfun([](decltype(As) a) -> decltype(a) { return a; } ...)(first{}); return decltype(b){}; }; @@ -817,7 +817,7 @@ struct string { string &operator+=(const string &__str) { return *this; } }; -template +template void finalizeDefaultAtomValues() { auto startEnd = [](const char * sym) -> void { string start("__"); @@ -828,7 +828,7 @@ void finalizeDefaultAtomValues() { void f() { finalizeDefaultAtomValues(); } -} +} namespace PR17476_variant { struct string { @@ -836,7 +836,7 @@ struct string { string &operator+=(const string &__str) { return *this; } }; -template +template void finalizeDefaultAtomValues() { auto startEnd = [](const T *sym) -> void { string start("__"); @@ -847,7 +847,7 @@ void finalizeDefaultAtomValues() { void f() { finalizeDefaultAtomValues(); } -} +} namespace PR17877_lambda_declcontext_and_get_cur_lambda_disconnect { @@ -857,7 +857,7 @@ template struct U { }; template -struct V { +struct V { U size() const { return U{}; } }; @@ -872,7 +872,7 @@ void Do() { namespace inclass_lambdas_within_nested_classes { namespace ns1 { -struct X1 { +struct X1 { struct X2 { enum { E = [](auto i) { return i; }(3) }; //expected-error{{inside of a constant expression}}\ //expected-error{{constant}}\ @@ -883,7 +883,9 @@ struct X1 { //expected-error{{not an integral constant}}\ //expected-note{{non-literal type}} int arr[([](int i) { return i; })(3)]; //expected-error{{inside of a constant expression}}\ - //expected-error{{must have a constant size}} + //expected-error{{must have a constant size}}\ + //expected-warning{{variable length arrays in C++ are a Clang extension}}\ + //expected-note-re{{non-literal type '{{.*}}' cannot be used in a constant expression}} int (*fp)(int) = [](int i) { return i; }; void fooptr(int (*fp)(char) = [](char c) { return 0; }) { } int L2 = ([](auto i) { return i; })(2); @@ -892,7 +894,10 @@ struct X1 { //expected-error{{not an integral constant}}\ //expected-note{{non-literal type}} int arrG[([](auto i) { return i; })(3)]; //expected-error{{inside of a constant expression}}\ - //expected-error{{must have a constant size}} + //expected-error{{must have a constant size}}\ + //expected-warning{{variable length arrays in C++ are a Clang extension}}\ + //expected-note-re{{non-literal type '{{.*}}' cannot be used in a constant expression}} + int (*fpG)(int) = [](auto i) { return i; }; void fooptrG(int (*fp)(char) = [](auto c) { return 0; }) { } }; @@ -900,7 +905,7 @@ struct X1 { } //end ns namespace ns2 { -struct X1 { +struct X1 { template struct X2 { int L = ([] (T i) { return i; })(2); @@ -909,7 +914,10 @@ struct X1 { //expected-error{{not an integral constant}}\ //expected-note{{non-literal type}} int arr[([](T i) { return i; })(3)]; //expected-error{{inside of a constant expression}}\ - //expected-error{{must have a constant size}} + //expected-error{{must have a constant size}}\ + //expected-warning{{variable length arrays in C++ are a Clang extension}}\ + //expected-note-re{{non-literal type '{{.*}}' cannot be used in a constant expression}} + int (*fp)(T) = [](T i) { return i; }; void fooptr(T (*fp)(char) = [](char c) { return 0; }) { } int L2 = ([](auto i) { return i; })(2); @@ -918,16 +926,19 @@ struct X1 { //expected-note{{non-literal type}}\ //expected-error{{inside of a constant expression}} int arrG[([](auto i) { return i; })(3)]; //expected-error{{must have a constant size}} \ - //expected-error{{inside of a constant expression}} + //expected-error{{inside of a constant expression}}\ + //expected-warning{{variable length arrays in C++ are a Clang extension}}\ + //expected-note-re{{non-literal type '{{.*}}' cannot be used in a constant expression}} + int (*fpG)(T) = [](auto i) { return i; }; void fooptrG(T (*fp)(char) = [](auto c) { return 0; }) { } template int fooG2(T (*fp)(U) = [](auto a) { return 0; }) { return 0; } template int fooG3(T (*fp)(U) = [](auto a) { return 0; }); }; }; -template +template template -int X1::X2::fooG3(T (*fp)(U)) { return 0; } +int X1::X2::fooG3(T (*fp)(U)) { return 0; } X1::X2 x2; //expected-note {{in instantiation of}} int run1 = x2.fooG2(); int run2 = x2.fooG3(); diff --git a/clang/test/SemaCXX/cxx1z-noexcept-function-type.cpp b/clang/test/SemaCXX/cxx1z-noexcept-function-type.cpp index 6cbc6b69e82f9..11b1093f9064f 100644 --- a/clang/test/SemaCXX/cxx1z-noexcept-function-type.cpp +++ b/clang/test/SemaCXX/cxx1z-noexcept-function-type.cpp @@ -120,7 +120,9 @@ namespace Builtins { extern "C" int strncmp(const char *, const char *, decltype(sizeof(0))) noexcept; // Check we recognized both as builtins. - typedef int arr[strcmp("bar", "foo") + 4 * strncmp("foo", "bar", 4)]; // expected-warning {{variable length array}} + typedef int arr[strcmp("bar", "foo") + 4 * strncmp("foo", "bar", 4)]; // expected-warning {{variable length array folded to constant array as an extension}} \ + expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{non-constexpr function 'strcmp' cannot be used in a constant expression}} typedef int arr[3]; } diff --git a/clang/test/SemaCXX/cxx2a-consteval.cpp b/clang/test/SemaCXX/cxx2a-consteval.cpp index 38cc4be32a27c..d8482ec53f0ed 100644 --- a/clang/test/SemaCXX/cxx2a-consteval.cpp +++ b/clang/test/SemaCXX/cxx2a-consteval.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -std=c++2a -emit-llvm-only -Wno-unused-value %s -verify +// RUN: %clang_cc1 -std=c++2a -emit-llvm-only -Wno-unused-value -Wno-vla %s -verify typedef __SIZE_TYPE__ size_t; diff --git a/clang/test/SemaCXX/cxx2a-constexpr-dynalloc-limits.cpp b/clang/test/SemaCXX/cxx2a-constexpr-dynalloc-limits.cpp index 2178154b2e363..8bcb4d45d4af8 100644 --- a/clang/test/SemaCXX/cxx2a-constexpr-dynalloc-limits.cpp +++ b/clang/test/SemaCXX/cxx2a-constexpr-dynalloc-limits.cpp @@ -87,10 +87,10 @@ constexpr int f = stack_array<1025>(); // expected-error {{constexpr variable 'f // expected-note {{in call}} void ohno() { int bar[stack_array<1024>()]; - int foo[stack_array<1025>()]; // expected-warning {{variable length arrays are a C99 feature}} \ + int foo[stack_array<1025>()]; // expected-warning {{variable length arrays in C++ are a Clang extension}} \ // expected-note {{in call to 'stack_array<1025>()'}} - constexpr int foo[stack_array<1025>()]; // expected-warning {{variable length arrays are a C99 feature}} \ + constexpr int foo[stack_array<1025>()]; // expected-warning {{variable length arrays in C++ are a Clang extension}} \ // expected-error {{constexpr variable cannot have non-literal type 'const int[stack_array<1025>()]'}} \ // expected-note {{in call to 'stack_array<1025>()'}} } diff --git a/clang/test/SemaCXX/cxx2b-deducing-this.cpp b/clang/test/SemaCXX/cxx2b-deducing-this.cpp index cb83270752443..0033541fa322d 100644 --- a/clang/test/SemaCXX/cxx2b-deducing-this.cpp +++ b/clang/test/SemaCXX/cxx2b-deducing-this.cpp @@ -542,3 +542,87 @@ void foo(C c) { } } + + +namespace GH69838 { +struct S { + S(this auto &self) {} // expected-error {{an explicit object parameter cannot appear in a constructor}} + virtual void f(this S self) {} // expected-error {{an explicit object parameter cannot appear in a virtual function}} + void g(this auto &self) const {} // expected-error {{explicit object member function cannot have 'const' qualifier}} + void h(this S self = S{}) {} // expected-error {{the explicit object parameter cannot have a default argument}} + void i(int i, this S self = S{}) {} // expected-error {{an explicit object parameter can only appear as the first parameter of the function}} + ~S(this S &&self); // expected-error {{an explicit object parameter cannot appear in a destructor}} \ + // expected-error {{destructor cannot have any parameters}} + + static void j(this S s); // expected-error {{an explicit object parameter cannot appear in a static function}} +}; + +void nonmember(this S s); // expected-error {{an explicit object parameter cannot appear in a non-member function}} + +int test() { + S s; + s.f(); + s.g(); + s.h(); + s.i(0); + s.j({}); + nonmember(S{}); +} + +} + +namespace GH69962 { +struct S { + S(const S&); +}; + +struct Thing { + template + Thing(this Self&& self, Args&& ... args) { } // expected-error {{an explicit object parameter cannot appear in a constructor}} +}; + +class Server : public Thing { + S name_; +}; +} + +namespace GH69233 { +struct Base {}; +struct S : Base { + int j; + S& operator=(this Base& self, const S&) = default; + // expected-warning@-1 {{explicitly defaulted copy assignment operator is implicitly deleted}} + // expected-note@-2 {{function is implicitly deleted because its declared type does not match the type of an implicit copy assignment operator}} + // expected-note@-3 {{explicitly defaulted function was implicitly deleted here}} +}; + +struct S2 { + S2& operator=(this int&& self, const S2&); + S2& operator=(this int&& self, S2&&); + operator int(); +}; + +S2& S2::operator=(this int&& self, const S2&) = default; +// expected-error@-1 {{the type of the explicit object parameter of an explicitly-defaulted copy assignment operator should match the type of the class 'S2'}} + +S2& S2::operator=(this int&& self, S2&&) = default; +// expected-error@-1 {{the type of the explicit object parameter of an explicitly-defaulted move assignment operator should match the type of the class 'S2'}} + +struct Move { + Move& operator=(this int&, Move&&) = default; + // expected-warning@-1 {{explicitly defaulted move assignment operator is implicitly deleted}} + // expected-note@-2 {{function is implicitly deleted because its declared type does not match the type of an implicit move assignment operator}} + // expected-note@-3 {{copy assignment operator is implicitly deleted because 'Move' has a user-declared move assignment operator}} +}; + +void test() { + S s; + s = s; // expected-error {{object of type 'S' cannot be assigned because its copy assignment operator is implicitly deleted}} + S2 s2; + s2 = s2; + + Move m; + m = Move{}; // expected-error {{object of type 'Move' cannot be assigned because its copy assignment operator is implicitly deleted}} +} + +} diff --git a/clang/test/SemaCXX/cxx2b-designated-initializers.cpp b/clang/test/SemaCXX/cxx2b-designated-initializers.cpp index 5588926f419a9..1d9b9183b3679 100644 --- a/clang/test/SemaCXX/cxx2b-designated-initializers.cpp +++ b/clang/test/SemaCXX/cxx2b-designated-initializers.cpp @@ -9,17 +9,36 @@ union S { }; void f(int x, auto) { - const S result { // expected-error {{field designator (null) does not refer to any field in type 'const S'}} + const S result { .a = x }; } void g(void) { - f(0, 0); // expected-note {{in instantiation of function template specialization 'PR61118::f' requested here}} + f(0, 0); } } // end namespace PR61118 +namespace GH65143 { +struct Inner { + int a; +}; + +struct Outer { + struct { + Inner inner; + }; +}; + +template void f() { + constexpr Outer x{.inner = {val}}; + static_assert(x.inner.a == val); +} + +void bar() { f<4>(); } +} + namespace GH62156 { union U1 { int x; diff --git a/clang/test/SemaCXX/dependent-noexcept-uninstantiated.cpp b/clang/test/SemaCXX/dependent-noexcept-uninstantiated.cpp new file mode 100644 index 0000000000000..ddb2698902275 --- /dev/null +++ b/clang/test/SemaCXX/dependent-noexcept-uninstantiated.cpp @@ -0,0 +1,11 @@ +// RUN: %clang_cc1 -fsyntax-only -std=c++17 %s +// expected-no-diagnostics + +using A = int; +using B = char; + +template struct C { + template void f0() noexcept(sizeof(T) == sizeof(A) && sizeof(V) == sizeof(B)) {} +}; + +void (C::*tmp1)() noexcept = &C::f0; diff --git a/clang/test/SemaCXX/diagnose-prioritiy-exception-redefining.cpp b/clang/test/SemaCXX/diagnose-prioritiy-exception-redefining.cpp new file mode 100644 index 0000000000000..ad025bf041ce5 --- /dev/null +++ b/clang/test/SemaCXX/diagnose-prioritiy-exception-redefining.cpp @@ -0,0 +1,9 @@ +// RUN: %clang_cc1 -fsyntax-only -verify -fcxx-exceptions -std=c++11 %s + +struct ExplicitlySpecialMethod { + ExplicitlySpecialMethod() = default; +}; +ExplicitlySpecialMethod::ExplicitlySpecialMethod() {} // expected-error{{definition of explicitly defaulted default constructor}} + +struct ImplicitlySpecialMethod {}; +ImplicitlySpecialMethod::ImplicitlySpecialMethod() {} // expected-error{{definition of implicitly declared default constructor}} diff --git a/clang/test/SemaCXX/eval-crashes.cpp b/clang/test/SemaCXX/eval-crashes.cpp index 3e59ad31c559d..ac04b113f99b7 100644 --- a/clang/test/SemaCXX/eval-crashes.cpp +++ b/clang/test/SemaCXX/eval-crashes.cpp @@ -54,3 +54,10 @@ namespace pr33140_10 { int a(const int &n = 0); bool b() { return a() == a(); } } + +namespace GH67317 { +struct array { + int (&data)[2]; + array() : data(*new int[1][2]) {} +}; +} diff --git a/clang/test/SemaCXX/exceptions.cpp b/clang/test/SemaCXX/exceptions.cpp index 3a410b1bfe439..c2e5adca3e650 100644 --- a/clang/test/SemaCXX/exceptions.cpp +++ b/clang/test/SemaCXX/exceptions.cpp @@ -117,12 +117,12 @@ class foo { namespace PR6831 { namespace NA { struct S; } namespace NB { struct S; } - + void f() { using namespace NA; using namespace NB; try { - } catch (int S) { + } catch (int S) { } } } @@ -276,15 +276,19 @@ void g() { } namespace PR28047 { -void test1(int i) { +void test1(int i) { // expected-note {{declared here}} try { - } catch (int(*)[i]) { // expected-error{{cannot catch variably modified type}} + } catch (int(*)[i]) { // expected-error{{cannot catch variably modified type}} \ + expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{function parameter 'i' with unknown value cannot be used in a constant expression}} } } void test2() { - int i; + int i; // expected-note {{declared here}} try { - } catch (int(*)[i]) { // expected-error{{cannot catch variably modified type}} + } catch (int(*)[i]) { // expected-error{{cannot catch variably modified type}} \ + expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{read of non-const variable 'i' is not allowed in a constant expression}} } } } diff --git a/clang/test/SemaCXX/for-range-examples.cpp b/clang/test/SemaCXX/for-range-examples.cpp index 1bbf042f0aa6c..d129d50d673e1 100644 --- a/clang/test/SemaCXX/for-range-examples.cpp +++ b/clang/test/SemaCXX/for-range-examples.cpp @@ -241,19 +241,22 @@ namespace pr18587 { namespace PR32933 { // https://bugs.llvm.org/show_bug.cgi?id=32933 void foo () -{ - int b = 1, a[b]; +{ + int b = 1, a[b]; // expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{read of non-const variable 'b' is not allowed in a constant expression}} \ + expected-note {{declared here}} a[0] = 0; [&] { for (int c : a) 0; } (); // expected-warning {{expression result unused}} } -int foo(int b) { - int varr[b][(b+=8)]; - b = 15; +int foo(int b) { // expected-note {{declared here}} + int varr[b][(b+=8)]; // expected-warning 2{{variable length arrays in C++ are a Clang extension}} \ + expected-note {{function parameter 'b' with unknown value cannot be used in a constant expression}} + b = 15; [&] { int i = 0; - for (auto &c : varr) + for (auto &c : varr) { c[0] = ++b; } diff --git a/clang/test/SemaCXX/i-c-e-cxx.cpp b/clang/test/SemaCXX/i-c-e-cxx.cpp index 70a500ea89f11..5121769002a83 100644 --- a/clang/test/SemaCXX/i-c-e-cxx.cpp +++ b/clang/test/SemaCXX/i-c-e-cxx.cpp @@ -39,7 +39,7 @@ namespace pr6206 { }; const int Foo::kBar = 20; - + char Test() { char str[Foo::kBar]; str[0] = '0'; @@ -54,7 +54,7 @@ void pr6373(const unsigned x = 0) { namespace rdar9204520 { - + struct A { static const int B = int(0.75 * 1000 * 1000); #if __cplusplus <= 199711L @@ -76,7 +76,7 @@ struct PR8836 { char _; long long a; }; #endif int PR8836test[(__typeof(sizeof(int)))&reinterpret_cast((((PR8836*)0)->a))]; -// expected-warning@-1 0-1{{C99 feature}} expected-warning@-1 {{folded to constant array as an extension}} +// expected-warning@-1 0-1{{variable length arrays in C++ are a Clang extension}} expected-warning@-1 {{folded to constant array as an extension}} // expected-note@-2 {{cast that performs the conversions of a reinterpret_cast is not allowed in a constant expression}} const int nonconst = 1.0; @@ -85,7 +85,7 @@ const int nonconst = 1.0; #endif int arr[nonconst]; #if __cplusplus <= 199711L -// expected-warning@-2 0-1{{C99 feature}} expected-warning@-2 {{folded to constant array as an extension}} +// expected-warning@-2 0-1{{variable length arrays in C++ are a Clang extension}} expected-warning@-2 {{folded to constant array as an extension}} // expected-note@-3 {{initializer of 'nonconst' is not a constant expression}} #endif diff --git a/clang/test/SemaCXX/lambda-expressions.cpp b/clang/test/SemaCXX/lambda-expressions.cpp index 9cf81a0a195a5..1797eef320b86 100644 --- a/clang/test/SemaCXX/lambda-expressions.cpp +++ b/clang/test/SemaCXX/lambda-expressions.cpp @@ -150,9 +150,10 @@ namespace Array { int &f(int *p); char &f(...); void g() { - int n = -1; + int n = -1; // expected-note {{declared here}} [=] { - int arr[n]; // VLA + int arr[n]; // expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{read of non-const variable 'n' is not allowed in a constant expression}} } (); const int m = -1; @@ -381,6 +382,14 @@ namespace PR18128 { }; } +namespace gh67687 { +struct S { + int n; + int a = (4, []() { return n; }()); // expected-error {{'this' cannot be implicitly captured in this context}} \ + // expected-note {{explicitly capture 'this'}} +}; +} + namespace PR18473 { template void f() { T t(0); diff --git a/clang/test/SemaCXX/new-delete-0x.cpp b/clang/test/SemaCXX/new-delete-0x.cpp index 972ad1d1b07ef..a4b43308d010f 100644 --- a/clang/test/SemaCXX/new-delete-0x.cpp +++ b/clang/test/SemaCXX/new-delete-0x.cpp @@ -23,7 +23,9 @@ void bad_news(int *ip) auto t = new (int(*)[[]]); // expected-error {{an attribute list cannot appear here}} auto u = new (int(*)[[]{return 1;}()][2]); // expected-error {{C++11 only allows consecutive left square brackets when introducing an attribute}} \ expected-error {{variably modified type}} \ - expected-error {{a lambda expression may not appear inside of a constant expression}} + expected-error {{a lambda expression may not appear inside of a constant expression}} \ + expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note-re {{non-literal type '(lambda at {{.*}})' cannot be used in a constant expression}} } void good_deletes() diff --git a/clang/test/SemaCXX/new-delete.cpp b/clang/test/SemaCXX/new-delete.cpp index 77c756e080e45..0270e42b7389f 100644 --- a/clang/test/SemaCXX/new-delete.cpp +++ b/clang/test/SemaCXX/new-delete.cpp @@ -644,4 +644,5 @@ int (*const_fold)[12] = new int[3][&const_fold + 12 - &const_fold]; // expected-note@-3 {{cannot refer to element 12 of non-array}} #elif __cplusplus < 201103L // expected-error@-5 {{cannot allocate object of variably modified type}} +// expected-warning@-6 {{variable length arrays in C++ are a Clang extension}} #endif diff --git a/clang/test/SemaCXX/offsetof.cpp b/clang/test/SemaCXX/offsetof.cpp index c4e86369f007d..1722b91fafc86 100644 --- a/clang/test/SemaCXX/offsetof.cpp +++ b/clang/test/SemaCXX/offsetof.cpp @@ -27,7 +27,7 @@ struct HasArray { // Constant and non-constant offsetof expressions void test_ice(int i) { int array0[__builtin_offsetof(HasArray, array[5])]; - int array1[__builtin_offsetof(HasArray, array[i])]; + int array1[__builtin_offsetof(HasArray, array[i])]; // expected-warning {{variable length arrays in C++ are a Clang extension}} } // Bitfields @@ -39,7 +39,7 @@ struct has_bitfields { int test3 = __builtin_offsetof(struct has_bitfields, j); // expected-error{{cannot compute offset of bit-field 'j'}} // offsetof referring to members of a base class. -struct Base1 { +struct Base1 { int x; }; @@ -48,7 +48,7 @@ struct Base2 { }; struct Derived2 : public Base1, public Base2 { - int z; + int z; }; int derived1[__builtin_offsetof(Derived2, x) == 0? 1 : -1]; // expected-warning{{offset of on non-POD type 'Derived2'}} diff --git a/clang/test/SemaCXX/overloaded-operators-display-order-crash.cpp b/clang/test/SemaCXX/overloaded-operators-display-order-crash.cpp new file mode 100644 index 0000000000000..5abd048f1d136 --- /dev/null +++ b/clang/test/SemaCXX/overloaded-operators-display-order-crash.cpp @@ -0,0 +1,54 @@ +// RUN: %clang_cc1 -fsyntax-only -verify %s +// RUN: not %clang_cc1 -fsyntax-only %s 2>&1 | FileCheck %s + +namespace ambig { + struct Foo { + operator int(); + operator const char *(); + }; + + + void func(const char*, long); + void func(const char*, const char*); + void func(int, int); + + bool doit(Foo x) { + func(x, x); // expected-error {{call to 'func' is ambiguous}} + // expected-note@* 3{{candidate}} + // Check that two functions with best conversions are at the top. + // CHECK: error: call to 'func' is ambiguous + // CHECK-NEXT: func(x, x) + // CHECK-NEXT: ^~~~ + // CHECK-NEXT: note: candidate function + // CHECK-NEXT: void func(const char*, const char*) + // CHECK-NEXT: ^ + // CHECK-NEXT: note: candidate function + // CHECK-NEXT: void func(int, int) + } +} + +namespace bad_conversion { + struct Foo { + operator int(); + operator const char *(); + }; + + + void func(double*, const char*, long); + void func(double*, const char*, const char*); + void func(double*, int, int); + + bool doit(Foo x) { + func((int*)0, x, x); // expected-error {{no matching function for call to 'func'}} + // expected-note@* 3{{candidate}} + // Check that two functions with best conversions are at the top. + // CHECK: error: no matching function for call to 'func' + // CHECK-NEXT: func((int*)0, x, x) + // CHECK-NEXT: ^~~~ + // CHECK-NEXT: note: candidate function + // CHECK-NEXT: void func(double*, const char*, const char*) + // CHECK-NEXT: ^ + // CHECK-NEXT: note: candidate function + // CHECK-NEXT: void func(double*, int, int) + } +} diff --git a/clang/test/SemaCXX/paren-list-agg-init.cpp b/clang/test/SemaCXX/paren-list-agg-init.cpp index ef6e67f263cae..f60b20e0d4656 100644 --- a/clang/test/SemaCXX/paren-list-agg-init.cpp +++ b/clang/test/SemaCXX/paren-list-agg-init.cpp @@ -92,7 +92,7 @@ T Construct(Args... args) { // beforecxx20-warning@-1 {{aggregate initialization of type 'A' from a parenthesized list of values is a C++20 extension}} } -void foo(int n) { +void foo(int n) { // expected-note {{declared here}} A a1(1954, 9, 21); // expected-error@-1 {{excess elements in struct initializer}} A a2(2.1); @@ -175,8 +175,9 @@ void foo(int n) { int arr5[2](1, 2); // beforecxx20-warning@-1 {{aggregate initialization of type 'int[2]' from a parenthesized list of values is a C++20 extension}} - int arr6[n](1, 2, 3); - // expected-error@-1 {{variable-sized object may not be initialized}} + int arr6[n](1, 2, 3); // expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{function parameter 'n' with unknown value cannot be used in a constant expression}} \ + expected-error {{variable-sized object may not be initialized}} I i(1, 2); // expected-error@-1 {{no matching constructor for initialization of 'I'}} diff --git a/clang/test/SemaCXX/riscv-rvv-lax-vector-conversions.cpp b/clang/test/SemaCXX/riscv-rvv-lax-vector-conversions.cpp index ff3e028aa314d..00a043797a9d3 100644 --- a/clang/test/SemaCXX/riscv-rvv-lax-vector-conversions.cpp +++ b/clang/test/SemaCXX/riscv-rvv-lax-vector-conversions.cpp @@ -2,8 +2,6 @@ // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f -target-feature +d -target-feature +zve64d -mvscale-min=8 -mvscale-max=8 -flax-vector-conversions=integer -ffreestanding -fsyntax-only -verify=lax-vector-integer %s // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f -target-feature +d -target-feature +zve64d -mvscale-min=8 -mvscale-max=8 -flax-vector-conversions=all -ffreestanding -fsyntax-only -verify=lax-vector-all %s -// lax-vector-all-no-diagnostics - // REQUIRES: riscv-registered-target #define RVV_FIXED_ATTR __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen))) @@ -33,8 +31,12 @@ void rvv_allowed_with_integer_lax_conversions() { // -flax-vector-conversions={integer,all}. fi32 = si64; // lax-vector-none-error@-1 {{assigning to 'rvv_fixed_int32m1_t' (vector of 16 'int' values) from incompatible type}} + // lax-vector-integer-error@-2 {{assigning to 'rvv_fixed_int32m1_t' (vector of 16 'int' values) from incompatible type}} + // lax-vector-all-error@-3 {{assigning to 'rvv_fixed_int32m1_t' (vector of 16 'int' values) from incompatible type}} si64 = fi32; // lax-vector-none-error@-1 {{assigning to 'vint64m1_t' (aka '__rvv_int64m1_t') from incompatible type}} + // lax-vector-integer-error@-2 {{assigning to 'vint64m1_t' (aka '__rvv_int64m1_t') from incompatible type}} + // lax-vector-all-error@-3 {{assigning to 'vint64m1_t' (aka '__rvv_int64m1_t') from incompatible type}} } void rvv_allowed_with_all_lax_conversions() { @@ -46,9 +48,11 @@ void rvv_allowed_with_all_lax_conversions() { ff32 = sf64; // lax-vector-none-error@-1 {{assigning to 'rvv_fixed_float32m1_t' (vector of 16 'float' values) from incompatible type}} // lax-vector-integer-error@-2 {{assigning to 'rvv_fixed_float32m1_t' (vector of 16 'float' values) from incompatible type}} + // lax-vector-all-error@-3 {{assigning to 'rvv_fixed_float32m1_t' (vector of 16 'float' values) from incompatible type}} sf64 = ff32; // lax-vector-none-error@-1 {{assigning to 'vfloat64m1_t' (aka '__rvv_float64m1_t') from incompatible type}} // lax-vector-integer-error@-2 {{assigning to 'vfloat64m1_t' (aka '__rvv_float64m1_t') from incompatible type}} + // lax-vector-all-error@-3 {{assigning to 'vfloat64m1_t' (aka '__rvv_float64m1_t') from incompatible type}} } void gnu_allowed_with_integer_lax_conversions() { diff --git a/clang/test/SemaCXX/vararg-non-pod.cpp b/clang/test/SemaCXX/vararg-non-pod.cpp index a17eec0ab15f7..0c24ced40f7aa 100644 --- a/clang/test/SemaCXX/vararg-non-pod.cpp +++ b/clang/test/SemaCXX/vararg-non-pod.cpp @@ -1,11 +1,11 @@ // RUN: %clang_cc1 -fsyntax-only -verify -fblocks %s -Wno-error=non-pod-varargs -// RUN: %clang_cc1 -fsyntax-only -verify -fblocks -std=c++98 %s -Wno-error=non-pod-varargs -// RUN: %clang_cc1 -fsyntax-only -verify -fblocks -std=c++11 %s -Wno-error=non-pod-varargs +// RUN: %clang_cc1 -fsyntax-only -verify -fblocks -std=gnu++98 %s -Wno-error=non-pod-varargs +// RUN: %clang_cc1 -fsyntax-only -verify -fblocks -std=gnu++11 %s -Wno-error=non-pod-varargs // Check that the warning is still there under -fms-compatibility. // RUN: %clang_cc1 -fsyntax-only -verify -fblocks %s -Wno-error=non-pod-varargs -fms-compatibility -// RUN: %clang_cc1 -fsyntax-only -verify -fblocks -std=c++98 %s -Wno-error=non-pod-varargs -fms-compatibility -// RUN: %clang_cc1 -fsyntax-only -verify -fblocks -std=c++11 %s -Wno-error=non-pod-varargs -fms-compatibility +// RUN: %clang_cc1 -fsyntax-only -verify -fblocks -std=gnu++98 %s -Wno-error=non-pod-varargs -fms-compatibility +// RUN: %clang_cc1 -fsyntax-only -verify -fblocks -std=gnu++11 %s -Wno-error=non-pod-varargs -fms-compatibility extern char version[]; @@ -21,7 +21,7 @@ void g(int a, ...); void t1() { C c(10); - + g(10, c); #if __cplusplus <= 199711L // expected-warning@-2 {{cannot pass object of non-POD type 'C' through variadic function; call will abort at runtime}} @@ -56,7 +56,7 @@ void t2() #endif (c.*ptr)(10, version); - + C::h(10, c); #if __cplusplus <= 199711L // expected-warning@-2 {{cannot pass object of non-POD type 'C' through variadic function; call will abort at runtime}} @@ -64,7 +64,7 @@ void t2() C::h(10, version); - void (*static_ptr)(int, ...) = &C::h; + void (*static_ptr)(int, ...) = &C::h; static_ptr(10, c); #if __cplusplus <= 199711L // expected-warning@-2 {{cannot pass object of non-POD type 'C' through variadic function; call will abort at runtime}} @@ -78,7 +78,7 @@ int (^block)(int, ...); void t3() { C c(10); - + block(10, c); #if __cplusplus <= 199711L // expected-warning@-2 {{cannot pass object of non-POD type 'C' through variadic block; call will abort at runtime}} @@ -97,7 +97,7 @@ void t4() C c(10); D d; - + d(10, c); #if __cplusplus <= 199711L // expected-warning@-2 {{cannot pass object of non-POD type 'C' through variadic method; call will abort at runtime}} @@ -113,7 +113,7 @@ class E { void t5() { C c(10); - + E e(10, c); #if __cplusplus <= 199711L // expected-warning@-2 {{cannot pass object of non-POD type 'C' through variadic constructor; call will abort at runtime}} diff --git a/clang/test/SemaCXX/vla-construct.cpp b/clang/test/SemaCXX/vla-construct.cpp index 5a7d833425422..502e09351438d 100644 --- a/clang/test/SemaCXX/vla-construct.cpp +++ b/clang/test/SemaCXX/vla-construct.cpp @@ -1,9 +1,7 @@ -// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fcxx-exceptions -fexceptions -O0 -verify %s -// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fcxx-exceptions -fexceptions -pedantic-errors -DPE -O0 -verify %s +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fcxx-exceptions -fexceptions -O0 -verify -Wno-vla %s +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fcxx-exceptions -fexceptions -pedantic-errors -O0 -verify=pe %s -# ifndef PE // expected-no-diagnostics -# endif extern "C" int printf(const char*, ...); @@ -21,11 +19,7 @@ void print(int n, int a, int b, int c, int d) { } void test(int n) { - S array_t[n][n+1]; -# ifdef PE - // expected-error@-2 {{variable length arrays are a C99 feature}} expected-note@-2 {{parameter}} expected-note@-3 {{here}} - // expected-error@-3 {{variable length arrays are a C99 feature}} expected-note@-3 {{parameter}} expected-note@-4 {{here}} -# endif + S array_t[n][n+1]; // pe-error 2{{variable length arrays in C++ are a Clang extension}} pe-note 2{{parameter}} pe-note@-1 2{{here}} int sizeof_S = sizeof(S); int sizeof_array_t_0_0 = sizeof(array_t[0][0]); int sizeof_array_t_0 = sizeof(array_t[0]); diff --git a/clang/test/SemaCXX/vla-ext-diag.cpp b/clang/test/SemaCXX/vla-ext-diag.cpp new file mode 100644 index 0000000000000..7492bbae6c468 --- /dev/null +++ b/clang/test/SemaCXX/vla-ext-diag.cpp @@ -0,0 +1,40 @@ +// RUN: %clang_cc1 -verify=gnu -std=gnu++11 %s +// RUN: %clang_cc1 -verify=expected,cxx11 -Wvla -std=gnu++11 %s +// RUN: %clang_cc1 -verify=expected,cxx11 -std=c++11 %s +// RUN: %clang_cc1 -verify=expected,cxx98 -std=c++98 %s +// RUN: %clang_cc1 -verify=expected,off -std=c++11 -Wno-vla-extension-static-assert %s +// gnu-no-diagnostics + +// Demonstrate that we do not diagnose use of VLAs by default in GNU mode, but +// we do diagnose them in C++ mode. Also note that we suggest use of +// static_assert, but only in C++11 and later and only if the warning group is +// not disabled. + +// C++98 mode does not emit the same notes as C++11 mode because in C++98, +// we're looking for an integer constant expression, whereas in C++11 and later, +// we're looking for a constant expression that is of integer type (these are +// different operations; ICE looks at the syntactic form of the expression, but +// C++11 constant expressions require calculating the expression value). +void func(int n) { // cxx11-note {{declared here}} off-note {{declared here}} + int vla[n]; // expected-warning {{variable length arrays in C++ are a Clang extension}} \ + cxx11-note {{function parameter 'n' with unknown value cannot be used in a constant expression}} \ + off-note {{function parameter 'n' with unknown value cannot be used in a constant expression}} +} + +void old_style_static_assert(int n) { // cxx11-note 5 {{declared here}} off-note 2 {{declared here}} + int array1[n != 12 ? 1 : -1]; // cxx11-warning {{variable length arrays in C++ are a Clang extension; did you mean to use 'static_assert'?}} \ + cxx98-warning {{variable length arrays in C++ are a Clang extension}} \ + cxx11-note {{function parameter 'n' with unknown value cannot be used in a constant expression}} + int array2[n != 12 ? -1 : 1]; // cxx11-warning {{variable length arrays in C++ are a Clang extension; did you mean to use 'static_assert'?}} \ + cxx98-warning {{variable length arrays in C++ are a Clang extension}} \ + cxx11-note {{function parameter 'n' with unknown value cannot be used in a constant expression}} + int array3[n != 12 ? 1 : n]; // expected-warning {{variable length arrays in C++ are a Clang extension}} \ + cxx11-note {{function parameter 'n' with unknown value cannot be used in a constant expression}} \ + off-note {{function parameter 'n' with unknown value cannot be used in a constant expression}} + int array4[(n ? 1 : -1)]; // cxx11-warning {{variable length arrays in C++ are a Clang extension; did you mean to use 'static_assert'?}} \ + cxx98-warning {{variable length arrays in C++ are a Clang extension}} \ + cxx11-note {{function parameter 'n' with unknown value cannot be used in a constant expression}} + int array5[n ? 1 : 0]; // expected-warning {{variable length arrays in C++ are a Clang extension}} \ + cxx11-note {{function parameter 'n' with unknown value cannot be used in a constant expression}} \ + off-note {{function parameter 'n' with unknown value cannot be used in a constant expression}} +} diff --git a/clang/test/SemaCXX/vla.cpp b/clang/test/SemaCXX/vla.cpp index f7cae9e370f4a..3657ab2d156e4 100644 --- a/clang/test/SemaCXX/vla.cpp +++ b/clang/test/SemaCXX/vla.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple x86_64-apple-macosx10.14.0 -verify %s +// RUN: %clang_cc1 -triple x86_64-apple-macosx10.14.0 -verify -Wno-vla %s // PR11925 int n; @@ -26,3 +26,18 @@ void test_fold() { char a2[(unsigned long)(int *)0+1] = {}; // expected-warning{{variable length array folded to constant array as an extension}} char a3[(unsigned long)(int *)0+1]; } + +// Demonstrate that the check for a static_assert-like use of VLA does not +// crash when there's no array size expression at all. +void test_null_array_size_expr() { + int array1[]; // expected-error {{definition of variable with array type needs an explicit size or an initializer}} + int array2[] = { 1, 2, 3 }; +} + +// Show that the check for a static_assert-like use of a VLA properly handles a +// dependent array size expression. +template +void func(int expr) { + int array[sizeof(Ty) ? sizeof(Ty{}) : sizeof(int)]; + int old_style_assert[expr ? Ty::one : Ty::Neg_one]; // We don't diagnose as a VLA until instantiation +} diff --git a/clang/test/SemaCXX/warn-unsafe-buffer-usage-debug-unclaimed/lit.local.cfg b/clang/test/SemaCXX/warn-unsafe-buffer-usage-debug-unclaimed/lit.local.cfg new file mode 100644 index 0000000000000..07bac415a1a64 --- /dev/null +++ b/clang/test/SemaCXX/warn-unsafe-buffer-usage-debug-unclaimed/lit.local.cfg @@ -0,0 +1,11 @@ +# -*- Python -*- + +config.substitutions.append( + ( + "%analyze_safe_buffer_debug_notes", + "'%s' %s" % ( + config.python_executable, + os.path.join(config.clang_src_dir, "utils", "analyze_safe_buffer_debug_notes.py") + ) + ) +) diff --git a/clang/test/SemaCXX/warn-unsafe-buffer-usage-debug-unclaimed/warn-unsafe-buffer-usage-debug-unclaimed.cpp b/clang/test/SemaCXX/warn-unsafe-buffer-usage-debug-unclaimed/warn-unsafe-buffer-usage-debug-unclaimed.cpp new file mode 100644 index 0000000000000..ab3d925753d47 --- /dev/null +++ b/clang/test/SemaCXX/warn-unsafe-buffer-usage-debug-unclaimed/warn-unsafe-buffer-usage-debug-unclaimed.cpp @@ -0,0 +1,49 @@ +// RUN: %clang_cc1 -Wno-unused-value -Wunsafe-buffer-usage -fsafe-buffer-usage-suggestions \ +// RUN: -mllvm -debug-only=SafeBuffers \ +// RUN: -std=c++20 -verify=expected %s + +// RUN: %clang_cc1 -Wno-unused-value -Wunsafe-buffer-usage -fsafe-buffer-usage-suggestions \ +// RUN: -mllvm -debug-only=SafeBuffers \ +// RUN: -std=c++20 %s \ +// RUN: 2>&1 | grep 'The unclaimed DRE trace:' \ +// RUN: | sed 's/^The unclaimed DRE trace://' \ +// RUN: | %analyze_safe_buffer_debug_notes \ +// RUN: | FileCheck %s + +// This debugging facility is only available in debug builds. +// +// REQUIRES: asserts +// REQUIRES: shell + +void test_unclaimed_use(int *p) { // expected-warning{{'p' is an unsafe pointer used for buffer access}} + p++; // expected-note{{used in pointer arithmetic here}} \ + expected-note{{safe buffers debug: failed to produce fixit for 'p' : has an unclaimed use\n \ + The unclaimed DRE trace: DeclRefExpr, UnaryOperator(++), CompoundStmt}} + *((p + 1) + 1); // expected-warning{{unsafe pointer arithmetic}} \ + expected-note{{used in pointer arithmetic here}} \ + expected-note{{safe buffers debug: failed to produce fixit for 'p' : has an unclaimed use\n \ + The unclaimed DRE trace: DeclRefExpr, ImplicitCastExpr(LValueToRValue), BinaryOperator(+), ParenExpr, BinaryOperator(+), ParenExpr, UnaryOperator(*), CompoundStmt}} + p -= 1; // expected-note{{used in pointer arithmetic here}} \ + expected-note{{safe buffers debug: failed to produce fixit for 'p' : has an unclaimed use\n \ + The unclaimed DRE trace: DeclRefExpr, BinaryOperator(-=), CompoundStmt}} + p--; // expected-note{{used in pointer arithmetic here}} \ + expected-note{{safe buffers debug: failed to produce fixit for 'p' : has an unclaimed use\n \ + The unclaimed DRE trace: DeclRefExpr, UnaryOperator(--), CompoundStmt}} + p[5] = 5; // expected-note{{used in buffer access here}} +} + +// CHECK: Root # 1 +// CHECK: |- DeclRefExpr # 4 +// CHECK: |-- UnaryOperator(++) # 1 +// CHECK: |--- CompoundStmt # 1 +// CHECK: |-- ImplicitCastExpr(LValueToRValue) # 1 +// CHECK: |--- BinaryOperator(+) # 1 +// CHECK: |---- ParenExpr # 1 +// CHECK: |----- BinaryOperator(+) # 1 +// CHECK: |------ ParenExpr # 1 +// CHECK: |------- UnaryOperator(*) # 1 +// CHECK: |-------- CompoundStmt # 1 +// CHECK: |-- BinaryOperator(-=) # 1 +// CHECK: |--- CompoundStmt # 1 +// CHECK: |-- UnaryOperator(--) # 1 +// CHECK: |--- CompoundStmt # 1 diff --git a/clang/test/SemaCXX/warn-unused-lambda-capture.cpp b/clang/test/SemaCXX/warn-unused-lambda-capture.cpp index 67b8fc3b661c8..4214a3c6ce09a 100644 --- a/clang/test/SemaCXX/warn-unused-lambda-capture.cpp +++ b/clang/test/SemaCXX/warn-unused-lambda-capture.cpp @@ -193,9 +193,10 @@ void test_use_template() { } namespace pr35555 { -int a; +int a; // expected-note {{declared here}} void b() { - int c[a]; + int c[a]; // expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{read of non-const variable 'a' is not allowed in a constant expression}} auto vla_used = [&c] { return c[0]; }; auto vla_unused = [&c] {}; // expected-warning{{lambda capture 'c' is not used}} } diff --git a/clang/test/SemaCXX/warn-unused-variables.cpp b/clang/test/SemaCXX/warn-unused-variables.cpp index 1d5aa729dda68..b649c7d808935 100644 --- a/clang/test/SemaCXX/warn-unused-variables.cpp +++ b/clang/test/SemaCXX/warn-unused-variables.cpp @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -fsyntax-only -Wunused-variable -Wunused-label -Wno-c++1y-extensions -verify %s -// RUN: %clang_cc1 -fsyntax-only -Wunused-variable -Wunused-label -Wno-c++1y-extensions -verify -std=c++11 %s +// RUN: %clang_cc1 -fsyntax-only -Wunused-variable -Wunused-label -Wno-c++1y-extensions -verify -std=gnu++11 %s template void f() { T t; t = 17; diff --git a/clang/test/SemaCXX/warn-zero-nullptr.cpp b/clang/test/SemaCXX/warn-zero-nullptr.cpp index 45f05fa5703b1..684572f8ef67d 100644 --- a/clang/test/SemaCXX/warn-zero-nullptr.cpp +++ b/clang/test/SemaCXX/warn-zero-nullptr.cpp @@ -16,10 +16,10 @@ int (S::*mp1) = 0; // expected-warning{{zero as null pointer constant}} void (*fp1)() = 0; // expected-warning{{zero as null pointer constant}} void* p1 = 0; // expected-warning{{zero as null pointer constant}} -// NULL is an integer constant expression, so warn on it too: -void* p2 = __null; // expected-warning{{zero as null pointer constant}} -void (*fp2)() = __null; // expected-warning{{zero as null pointer constant}} -int (S::*mp2) = __null; // expected-warning{{zero as null pointer constant}} +// __null is not treated as an integer constant expression for GCC compatibility +void* p2 = __null; +void (*fp2)() = __null; +int (S::*mp2) = __null; void f0(void* v = MACRO); // expected-warning{{zero as null pointer constant}} void f1(void* v = NULL); // expected-warning{{zero as null pointer constant}} diff --git a/clang/test/SemaObjC/aarch64-sve-types.m b/clang/test/SemaObjC/aarch64-sve-types.m index 376ffe648e2c2..b50f43cee76f6 100644 --- a/clang/test/SemaObjC/aarch64-sve-types.m +++ b/clang/test/SemaObjC/aarch64-sve-types.m @@ -18,7 +18,7 @@ @interface foo @property(nullable) __SVFloat32_t f32; // expected-error {{cannot be applied to non-pointer type}} @property(nullable) __SVFloat64_t f64; // expected-error {{cannot be applied to non-pointer type}} -@property(nullable) __SVBFloat16_t bf16; // expected-error {{cannot be applied to non-pointer type}} +@property(nullable) __SVBfloat16_t bf16; // expected-error {{cannot be applied to non-pointer type}} @property(nullable) __SVBool_t b8; // expected-error {{cannot be applied to non-pointer type}} @end diff --git a/clang/test/SemaObjCXX/properties.mm b/clang/test/SemaObjCXX/properties.mm index 1c4e1470beef5..a3d67d9a360d7 100644 --- a/clang/test/SemaObjCXX/properties.mm +++ b/clang/test/SemaObjCXX/properties.mm @@ -35,7 +35,8 @@ @interface Test3 - (int) length; @end void test3(Test3 *t) { - char vla[t.length] = {}; // expected-error {{variable-sized object may not be initialized}} + char vla[t.length] = {}; // expected-error {{variable-sized object may not be initialized}} \ + expected-warning {{variable length arrays in C++ are a Clang extension}} char *heaparray = new char[t.length]; } diff --git a/clang/test/SemaObjCXX/vla.mm b/clang/test/SemaObjCXX/vla.mm index e1d556e9921a0..7ee15743efa37 100644 --- a/clang/test/SemaObjCXX/vla.mm +++ b/clang/test/SemaObjCXX/vla.mm @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -fsyntax-only -verify %s +// RUN: %clang_cc1 -fsyntax-only -verify -Wno-vla %s // expected-no-diagnostics @interface Data diff --git a/clang/test/SemaOpenCLCXX/address-space-deduction.clcpp b/clang/test/SemaOpenCLCXX/address-space-deduction.clcpp index 3c801f2c4db76..526e86584c77b 100644 --- a/clang/test/SemaOpenCLCXX/address-space-deduction.clcpp +++ b/clang/test/SemaOpenCLCXX/address-space-deduction.clcpp @@ -6,7 +6,7 @@ constexpr int foo = 0; //CHECK: |-VarDecl {{.*}} foo1 'T' cinit -//CHECK: `-VarTemplateSpecializationDecl {{.*}} used foo1 '__global long':'__global long' implicit_instantiation cinit +//CHECK: `-VarTemplateSpecializationDecl {{.*}} used foo1 '__global long' implicit_instantiation cinit template T foo1 = 0; diff --git a/clang/test/SemaOpenCLCXX/addrspace-auto.clcpp b/clang/test/SemaOpenCLCXX/addrspace-auto.clcpp index 7862564d1b4ef..97fad5939955c 100644 --- a/clang/test/SemaOpenCLCXX/addrspace-auto.clcpp +++ b/clang/test/SemaOpenCLCXX/addrspace-auto.clcpp @@ -1,18 +1,18 @@ //RUN: %clang_cc1 %s -pedantic -ast-dump -verify | FileCheck %s __constant int i = 1; -//CHECK: |-VarDecl {{.*}} ai '__global int':'__global int' +//CHECK: |-VarDecl {{.*}} ai '__global int' auto ai = i; kernel void test() { int i; - //CHECK: VarDecl {{.*}} ai '__private int':'__private int' + //CHECK: VarDecl {{.*}} ai '__private int' auto ai = i; constexpr int c = 1; - //CHECK: VarDecl {{.*}} used cai '__constant int':'__constant int' + //CHECK: VarDecl {{.*}} used cai '__constant int' __constant auto cai = c; - //CHECK: VarDecl {{.*}} aii '__private int':'__private int' + //CHECK: VarDecl {{.*}} aii '__private int' auto aii = cai; //CHECK: VarDecl {{.*}} ref '__private int &__private' diff --git a/clang/test/SemaSYCL/unique_stable_name.cpp b/clang/test/SemaSYCL/unique_stable_name.cpp index 2a0230d06137f..fb3b0dbe9e0ee 100644 --- a/clang/test/SemaSYCL/unique_stable_name.cpp +++ b/clang/test/SemaSYCL/unique_stable_name.cpp @@ -173,7 +173,8 @@ void f() { // an unevaluated context because the use within a VLA extent forces // evaluation. int j = 55; - __builtin_sycl_unique_stable_name(int[++j]); // no warning expected + __builtin_sycl_unique_stable_name(int[++j]); // expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{a constant expression cannot modify an object that is visible outside that expression}} } template diff --git a/clang/test/SemaTemplate/aggregate-deduction-candidate.cpp b/clang/test/SemaTemplate/aggregate-deduction-candidate.cpp index d455d424ab3d0..7f535651bb815 100644 --- a/clang/test/SemaTemplate/aggregate-deduction-candidate.cpp +++ b/clang/test/SemaTemplate/aggregate-deduction-candidate.cpp @@ -21,8 +21,8 @@ namespace Basic { // CHECK: `-CXXDeductionGuideDecl {{.*}} implicit used 'auto (double, double) -> Basic::A' // CHECK: |-TemplateArgument type 'double' // CHECK: | `-BuiltinType {{.*}} 'double' - // CHECK: |-ParmVarDecl {{.*}} 'double':'double' - // CHECK: `-ParmVarDecl {{.*}} 'double':'double' + // CHECK: |-ParmVarDecl {{.*}} 'double' + // CHECK: `-ParmVarDecl {{.*}} 'double' // CHECK: FunctionProtoType {{.*}} 'auto (T, T) -> A' dependent trailing_return cdecl // CHECK: |-InjectedClassNameType {{.*}} 'A' dependent // CHECK: | `-CXXRecord {{.*}} 'A' @@ -65,13 +65,13 @@ namespace Basic { // CHECK: FunctionTemplateDecl {{.*}} implicit // CHECK: |-TemplateTypeParmDecl {{.*}} referenced typename depth 0 index 0 T // CHECK: |-CXXDeductionGuideDecl {{.*}} implicit 'auto (S, T) -> C' - // CHECK: | |-ParmVarDecl {{.*}} 'S':'S' + // CHECK: | |-ParmVarDecl {{.*}} 'S' // CHECK: | `-ParmVarDecl {{.*}} 'T' // CHECK: `-CXXDeductionGuideDecl {{.*}} implicit used 'auto (S, int) -> Basic::C' // CHECK: |-TemplateArgument type 'int' // CHECK: | `-BuiltinType {{.*}} 'int' // CHECK: |-ParmVarDecl {{.*}} 'S':'Basic::S' - // CHECK: `-ParmVarDecl {{.*}} 'int':'int' + // CHECK: `-ParmVarDecl {{.*}} 'int' // CHECK: FunctionProtoType {{.*}} 'auto (S, T) -> C' dependent trailing_return cdecl // CHECK: |-InjectedClassNameType {{.*}} 'C' dependent // CHECK: | `-CXXRecord {{.*}} 'C' @@ -87,8 +87,8 @@ namespace Basic { // CHECK: FunctionTemplateDecl {{.*}} implicit // CHECK: |-TemplateTypeParmDecl {{.*}} referenced typename depth 0 index 0 T // CHECK: `-CXXDeductionGuideDecl {{.*}} implicit 'auto (int, int) -> D' - // CHECK: |-ParmVarDecl {{.*}} 'int':'int' - // CHECK: `-ParmVarDecl {{.*}} 'int':'int' + // CHECK: |-ParmVarDecl {{.*}} 'int' + // CHECK: `-ParmVarDecl {{.*}} 'int' // CHECK: FunctionProtoType {{.*}} 'auto (int, int) -> D' dependent trailing_return cdecl // CHECK: |-InjectedClassNameType {{.*}} 'D' dependent // CHECK: | `-CXXRecord {{.*}} 'D' @@ -117,7 +117,7 @@ namespace Basic { // CHECK: `-CXXDeductionGuideDecl {{.*}} implicit used 'auto (int, decltype(t)) -> Basic::E' // CHECK: |-TemplateArgument type 'int' // CHECK: | `-BuiltinType {{.*}} 'int' - // CHECK: |-ParmVarDecl {{.*}} 'int':'int' + // CHECK: |-ParmVarDecl {{.*}} 'int' // CHECK: `-ParmVarDecl {{.*}} 'decltype(t)':'int' // CHECK: FunctionProtoType {{.*}} 'auto (T, decltype(t)) -> E' dependent trailing_return cdecl // CHECK: |-InjectedClassNameType {{.*}} 'E' dependent @@ -150,7 +150,7 @@ namespace Basic { // CHECK: |-TemplateArgument type 'int' // CHECK: | `-BuiltinType {{.*}} 'int' // CHECK: |-ParmVarDecl {{.*}} 'typename I::type':'int' - // CHECK: `-ParmVarDecl {{.*}} 'int':'int' + // CHECK: `-ParmVarDecl {{.*}} 'int' // CHECK: FunctionProtoType {{.*}} 'auto (typename I::type, T) -> F' dependent trailing_return cdecl // CHECK: |-InjectedClassNameType {{.*}} 'F' dependent // CHECK: | `-CXXRecord {{.*}} 'F' @@ -235,8 +235,8 @@ namespace BraceElision { // CHECK: `-CXXDeductionGuideDecl {{.*}} implicit used 'auto (int, int) -> BraceElision::A' // CHECK: |-TemplateArgument type 'int' // CHECK: | `-BuiltinType {{.*}} 'int' - // CHECK: |-ParmVarDecl {{.*}} 'int':'int' - // CHECK: `-ParmVarDecl {{.*}} 'int':'int' + // CHECK: |-ParmVarDecl {{.*}} 'int' + // CHECK: `-ParmVarDecl {{.*}} 'int' // CHECK: FunctionProtoType {{.*}} 'auto (T, T) -> A' dependent trailing_return cdecl // CHECK: |-InjectedClassNameType {{.*}} 'A' dependent // CHECK: | `-CXXRecord {{.*}} 'A' @@ -275,8 +275,8 @@ namespace TrailingPack { // CHECK: | `-TemplateArgument type 'TrailingPack::(lambda at {{.*}})' // CHECK: | `-RecordType {{.*}} 'TrailingPack::(lambda at {{.*}})' // CHECK: | `-CXXRecord {{.*}} '' - // CHECK: |-ParmVarDecl {{.*}} 'TrailingPack::(lambda at {{.*}})':'TrailingPack::(lambda at {{.*}})' - // CHECK: `-ParmVarDecl {{.*}} 'TrailingPack::(lambda at {{.*}})':'TrailingPack::(lambda at {{.*}})' + // CHECK: |-ParmVarDecl {{.*}} 'TrailingPack::(lambda at {{.*}})' + // CHECK: `-ParmVarDecl {{.*}} 'TrailingPack::(lambda at {{.*}})' // CHECK: FunctionProtoType {{.*}} 'auto (T...) -> A' dependent trailing_return cdecl // CHECK: |-InjectedClassNameType {{.*}} 'A' dependent // CHECK: | `-CXXRecord {{.*}} 'A' @@ -324,7 +324,7 @@ namespace DeduceArity { // CHECK: FunctionTemplateDecl {{.*}} implicit // CHECK: |-TemplateTypeParmDecl {{.*}} referenced typename depth 0 index 0 ... T // CHECK: |-CXXDeductionGuideDecl {{.*}} implicit 'auto (Types, T...) -> F' - // CHECK: | |-ParmVarDecl {{.*}} 'Types':'Types' + // CHECK: | |-ParmVarDecl {{.*}} 'Types' // CHECK: | `-ParmVarDecl {{.*}} 'T...' pack // CHECK: |-CXXDeductionGuideDecl {{.*}} implicit used // CHECK-SAME: 'auto (Types, DeduceArity::X, DeduceArity::Y, DeduceArity::Z) -> @@ -340,16 +340,16 @@ namespace DeduceArity { // CHECK: | | `-RecordType {{.*}} 'DeduceArity::Z' // CHECK: | | `-CXXRecord {{.*}} 'Z' // CHECK: | |-ParmVarDecl {{.*}} 'Types':'DeduceArity::Types' - // CHECK: | |-ParmVarDecl {{.*}} 'DeduceArity::X':'DeduceArity::X' - // CHECK: | |-ParmVarDecl {{.*}} 'DeduceArity::Y':'DeduceArity::Y' - // CHECK: | `-ParmVarDecl {{.*}} 'DeduceArity::Z':'DeduceArity::Z' + // CHECK: | |-ParmVarDecl {{.*}} 'DeduceArity::X' + // CHECK: | |-ParmVarDecl {{.*}} 'DeduceArity::Y' + // CHECK: | `-ParmVarDecl {{.*}} 'DeduceArity::Z' // CHECK: `-CXXDeductionGuideDecl {{.*}} implicit 'auto (Types, DeduceArity::X) -> DeduceArity::F' // CHECK: |-TemplateArgument pack // CHECK: | `-TemplateArgument type 'DeduceArity::X' // CHECK: | `-RecordType {{.*}} 'DeduceArity::X' // CHECK: | `-CXXRecord {{.*}} 'X' // CHECK: |-ParmVarDecl {{.*}} 'Types':'DeduceArity::Types' - // CHECK: `-ParmVarDecl {{.*}} 'DeduceArity::X':'DeduceArity::X' + // CHECK: `-ParmVarDecl {{.*}} 'DeduceArity::X' // CHECK: FunctionProtoType {{.*}} 'auto (Types, T...) -> F' dependent trailing_return cdecl // CHECK: |-InjectedClassNameType {{.*}} 'F' dependent // CHECK: | `-CXXRecord {{.*}} 'F' diff --git a/clang/test/SemaTemplate/concepts-out-of-line-def.cpp b/clang/test/SemaTemplate/concepts-out-of-line-def.cpp index ed2d50d7e0a6b..f134394615fb2 100644 --- a/clang/test/SemaTemplate/concepts-out-of-line-def.cpp +++ b/clang/test/SemaTemplate/concepts-out-of-line-def.cpp @@ -1,5 +1,4 @@ // RUN: %clang_cc1 -std=c++20 -verify %s -// expected-no-diagnostics static constexpr int PRIMARY = 0; static constexpr int SPECIALIZATION_CONCEPT = 1; @@ -227,7 +226,9 @@ namespace constrained_member_sfinae { template struct S { template - static constexpr int constrained_method() requires (sizeof(int[N * 1073741824 + 4]) == 16) { + static constexpr int constrained_method() requires (sizeof(int[N * 1073741824 + 4]) == 16) { // expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{value 4294967296 is outside the range of representable values of type 'int'}} \ + expected-note {{while calculating associated constraint of template 'constrained_method' here}} return CONSTRAINED_METHOD_1; } diff --git a/clang/test/SemaTemplate/deduction-guide.cpp b/clang/test/SemaTemplate/deduction-guide.cpp index 9de2975656ee2..16c7083df29d0 100644 --- a/clang/test/SemaTemplate/deduction-guide.cpp +++ b/clang/test/SemaTemplate/deduction-guide.cpp @@ -37,7 +37,7 @@ using AT = A; // CHECK: | | `-Var {{.*}} 'arr1' 'int[3]' // CHECK: | `-TemplateArgument decl // CHECK: | `-Var {{.*}} 'arr2' 'int[3]' -// CHECK: |-ParmVarDecl {{.*}} 'X<&arr1, &arr2>':'X<&arr1, &arr2>' +// CHECK: |-ParmVarDecl {{.*}} 'X<&arr1, &arr2>' // CHECK: |-ParmVarDecl {{.*}} 'int (*)[3]' // CHECK: |-ParmVarDecl {{.*}} 'int (*)[3]' // CHECK: `-ParmVarDecl {{.*}} 'short (*)[4]' @@ -76,7 +76,7 @@ using BT = B; // CHECK: |-TemplateArgument integral 120 // CHECK: |-TemplateArgument type 'std::nullptr_t' // CHECK: |-TemplateArgument nullptr -// CHECK: `-ParmVarDecl {{.*}} 'X':'X' +// CHECK: `-ParmVarDecl {{.*}} 'X' // CHECK: FunctionProtoType {{.*}} 'auto (X) -> B' dependent trailing_return // CHECK: |-InjectedClassNameType {{.*}} 'B' dependent // CHECK: `-TemplateSpecializationType {{.*}} 'X' dependent X @@ -111,9 +111,9 @@ using CT = C; // CHECK: |-TemplateArgument template B // CHECK: |-TemplateArgument type 'int' // CHECK: |-TemplateArgument integral 0 -// CHECK: |-ParmVarDecl {{.*}} 'int':'int' -// CHECK: |-ParmVarDecl {{.*}} 'Y':'Y' -// CHECK: `-ParmVarDecl {{.*}} 'int':'int' +// CHECK: |-ParmVarDecl {{.*}} 'int' +// CHECK: |-ParmVarDecl {{.*}} 'Y' +// CHECK: `-ParmVarDecl {{.*}} 'int' // CHECK: FunctionProtoType {{.*}} 'auto (A, Y<>, type-parameter-0-2) -> C' dependent trailing_return cdecl // CHECK: |-InjectedClassNameType {{.*}} 'C' dependent // CHECK: |-TemplateTypeParmType {{.*}} 'A' dependent depth 0 index 0 @@ -234,7 +234,7 @@ F s(0); // CHECK: |-TemplateArgument integral 120 // CHECK: |-TemplateArgument type 'int' // CHECK: | `-BuiltinType {{.*}} 'int' -// CHECK: `-ParmVarDecl {{.*}} 'int':'int' +// CHECK: `-ParmVarDecl {{.*}} 'int' // CHECK: FunctionProtoType {{.*}} 'auto (type-parameter-0-1) -> F<>' dependent trailing_return cdecl // CHECK: |-InjectedClassNameType {{.*}} 'F<>' dependent // CHECK: | `-CXXRecord {{.*}} 'F' diff --git a/clang/test/SemaTemplate/deduction.cpp b/clang/test/SemaTemplate/deduction.cpp index 2556fe86e1b48..ad98de61d9e12 100644 --- a/clang/test/SemaTemplate/deduction.cpp +++ b/clang/test/SemaTemplate/deduction.cpp @@ -3,7 +3,7 @@ // RUN: %clang_cc1 -fsyntax-only -verify %s -std=c++23 // Template argument deduction with template template parameters. -template class A> +template class A> struct X0 { static const unsigned value = 0; }; @@ -192,8 +192,9 @@ void g() { namespace test8 { template void foo(T); -void test(int a) { - char n[a]; +void test(int a) { // expected-note {{declared here}} + char n[a]; // expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{function parameter 'a' with unknown value cannot be used in a constant expression}} foo(n); } } // namespace test8 @@ -310,7 +311,7 @@ int main() { get_helper(t); return 0; } -} // end ns2 +} // end ns2 } namespace multiple_deduction_different_type { diff --git a/clang/test/SemaTemplate/default-expr-arguments-3.cpp b/clang/test/SemaTemplate/default-expr-arguments-3.cpp index 4bbdb6f91ec7e..4d04209e110b3 100644 --- a/clang/test/SemaTemplate/default-expr-arguments-3.cpp +++ b/clang/test/SemaTemplate/default-expr-arguments-3.cpp @@ -4,7 +4,7 @@ // CHECK: FunctionDecl {{.*}} used func 'void ()' // CHECK-NEXT: TemplateArgument type 'int' // CHECK: LambdaExpr {{.*}} '(lambda at -// CHECK: ParmVarDecl {{.*}} used f 'foo':'foo' cinit +// CHECK: ParmVarDecl {{.*}} used f 'foo' cinit // CHECK-NEXT: DeclRefExpr {{.*}} 'foo' EnumConstant {{.*}} 'a' 'foo' namespace PR28795 { @@ -23,7 +23,7 @@ namespace PR28795 { // CHECK: ClassTemplateSpecializationDecl {{.*}} struct class2 definition // CHECK: TemplateArgument type 'int' // CHECK: LambdaExpr {{.*}} '(lambda at -// CHECK: ParmVarDecl {{.*}} used f 'foo':'foo' cinit +// CHECK: ParmVarDecl {{.*}} used f 'foo' cinit // CHECK-NEXT: DeclRefExpr {{.*}} 'foo' EnumConstant {{.*}} 'a' 'foo' // Template struct case: @@ -41,7 +41,7 @@ template struct class2; // CHECK-NEXT: FunctionDecl {{.*}} f1 'void ()' // CHECK: FunctionDecl {{.*}} f1 'void ()' // CHECK-NEXT: TemplateArgument type 'int' -// CHECK: ParmVarDecl {{.*}} n 'foo':'foo' cinit +// CHECK: ParmVarDecl {{.*}} n 'foo' cinit // CHECK-NEXT: DeclRefExpr {{.*}} 'foo' EnumConstant {{.*}} 'a' 'foo' template diff --git a/clang/test/SemaTemplate/instantiate-sizeof.cpp b/clang/test/SemaTemplate/instantiate-sizeof.cpp index 660e70549e30f..0931ef2335c4b 100644 --- a/clang/test/SemaTemplate/instantiate-sizeof.cpp +++ b/clang/test/SemaTemplate/instantiate-sizeof.cpp @@ -1,12 +1,14 @@ // RUN: %clang_cc1 -triple x86_64-linux-gnu -fsyntax-only -verify -std=c++11 %s // Make sure we handle contexts correctly with sizeof -template void f(T n) { - int buffer[n]; +template void f(T n) { // expected-note {{declared here}} + int buffer[n]; // expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{function parameter 'n' with unknown value cannot be used in a constant expression}} \ + expected-note@#instantiate {{in instantiation of function template specialization 'f' requested here}} [] { int x = sizeof(sizeof(buffer)); }(); } int main() { - f(1); + f(1); // #instantiate } // Make sure we handle references to non-static data members in unevaluated diff --git a/clang/test/SemaTemplate/instantiate-typeof.cpp b/clang/test/SemaTemplate/instantiate-typeof.cpp index f4d7847e4fa62..bc6027fad2b42 100644 --- a/clang/test/SemaTemplate/instantiate-typeof.cpp +++ b/clang/test/SemaTemplate/instantiate-typeof.cpp @@ -1,11 +1,11 @@ // RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 %s -// expected-no-diagnostics // Make sure we correctly treat __typeof as potentially-evaluated when appropriate -template void f(T n) { - int buffer[n]; +template void f(T n) { // expected-note {{declared here}} + int buffer[n]; // expected-warning {{variable length arrays in C++ are a Clang extension}} \ + expected-note {{function parameter 'n' with unknown value cannot be used in a constant expression}} [&buffer] { __typeof(buffer) x; }(); } int main() { - f(1); + f(1); // expected-note {{in instantiation of function template specialization 'f' requested here}} } diff --git a/clang/test/SemaTemplate/make_integer_seq.cpp b/clang/test/SemaTemplate/make_integer_seq.cpp index 12520167b93e5..644bf41f8614c 100644 --- a/clang/test/SemaTemplate/make_integer_seq.cpp +++ b/clang/test/SemaTemplate/make_integer_seq.cpp @@ -37,7 +37,7 @@ using test2 = B; // CHECK-NEXT: `-ElaboratedType 0x{{[0-9A-Fa-f]+}} '__make_integer_seq' sugar // CHECK-NEXT: `-TemplateSpecializationType 0x{{[0-9A-Fa-f]+}} '__make_integer_seq' sugar alias __make_integer_seq // CHECK-NEXT: |-TemplateArgument template A -// CHECK-NEXT: |-TemplateArgument type 'int':'int' +// CHECK-NEXT: |-TemplateArgument type 'int' // CHECK-NEXT: | `-SubstTemplateTypeParmType 0x{{[0-9A-Fa-f]+}} 'int' sugar class depth 0 index 0 B1 // CHECK-NEXT: | |-TypeAliasTemplate 0x{{[0-9A-Fa-f]+}} 'B' // CHECK-NEXT: | `-BuiltinType 0x{{[0-9A-Fa-f]+}} 'int' @@ -48,14 +48,14 @@ using test2 = B; // CHECK-NEXT: | |-NonTypeTemplateParmDecl 0x{{[0-9A-Fa-f]+}} col:24 referenced 'B1' depth 0 index 1 B2 // CHECK-NEXT: | `-IntegerLiteral 0x{{[0-9A-Fa-f]+}} 'int' 1 // CHECK-NEXT: `-TemplateSpecializationType 0x{{[0-9A-Fa-f]+}} 'A' sugar A -// CHECK-NEXT: |-TemplateArgument type 'int':'int' +// CHECK-NEXT: |-TemplateArgument type 'int' // CHECK-NEXT: | `-SubstTemplateTypeParmType 0x{{[0-9A-Fa-f]+}} 'int' sugar class depth 0 index 0 B1 // CHECK-NEXT: | |-TypeAliasTemplate 0x{{[0-9A-Fa-f]+}} 'B' // CHECK-NEXT: | `-BuiltinType 0x{{[0-9A-Fa-f]+}} 'int' // CHECK-NEXT: |-TemplateArgument expr // CHECK-NEXT: | `-ConstantExpr 0x{{[0-9A-Fa-f]+}} 'int' // CHECK-NEXT: | |-value: Int 0 -// CHECK-NEXT: | `-IntegerLiteral 0x{{[0-9A-Fa-f]+}} 'int':'int' 0 +// CHECK-NEXT: | `-IntegerLiteral 0x{{[0-9A-Fa-f]+}} 'int' 0 // CHECK-NEXT: `-RecordType 0x{{[0-9A-Fa-f]+}} 'A' // CHECK-NEXT: `-ClassTemplateSpecialization 0x{{[0-9A-Fa-f]+}} 'A' @@ -99,7 +99,7 @@ template