diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 3c72269d1e00c..3857861521f7a 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -595,6 +595,13 @@ void RISCVInstructionSelector::preISelLower(MachineInstr &MI,
     MRI.setType(DstReg, sXLen);
     break;
   }
+  case TargetOpcode::G_PTRMASK: {
+    Register DstReg = MI.getOperand(0).getReg();
+    const LLT sXLen = LLT::scalar(STI.getXLen());
+    replacePtrWithInt(MI.getOperand(1), MIB, MRI);
+    MI.setDesc(TII.get(TargetOpcode::G_AND));
+    MRI.setType(DstReg, sXLen);
+  }
   }
 }
 
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 9eb5812e024b9..6442c67b802f1 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -145,7 +145,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
   LoadStoreActions.clampScalar(0, s32, sXLen).lower();
   ExtLoadActions.widenScalarToNextPow2(0).clampScalar(0, s32, sXLen).lower();
 
-  getActionDefinitionsBuilder(G_PTR_ADD).legalFor({{p0, sXLen}});
+  getActionDefinitionsBuilder({G_PTR_ADD, G_PTRMASK}).legalFor({{p0, sXLen}});
 
   getActionDefinitionsBuilder(G_PTRTOINT)
       .legalFor({{sXLen, p0}})
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptrmask-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptrmask-rv32.mir
new file mode 100644
index 0000000000000..f92b689b9ca13
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptrmask-rv32.mir
@@ -0,0 +1,47 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name:            ptrmask_p0_s32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10, $x11
+    ; CHECK-LABEL: name: ptrmask_p0_s32
+    ; CHECK: liveins: $x10, $x11
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $x10 = COPY [[AND]]
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:gprb(p0) = COPY $x10
+    %1:gprb(s32) = COPY $x11
+    %2:gprb(p0) = G_PTRMASK %0(p0), %1(s32)
+    $x10 = COPY %2(p0)
+    PseudoRET implicit $x10
+...
+
+---
+name:            ptrmask_p0_const_s32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10
+    ; CHECK-LABEL: name: ptrmask_p0_const_s32
+    ; CHECK: liveins: $x10
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 10
+    ; CHECK-NEXT: $x10 = COPY [[ANDI]]
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:gprb(p0) = COPY $x10
+    %1:gprb(s32) = G_CONSTANT i32 10
+    %2:gprb(p0) = G_PTRMASK %0(p0), %1(s32)
+    $x10 = COPY %2(p0)
+    PseudoRET implicit $x10
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptrmask-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptrmask-rv64.mir
new file mode 100644
index 0000000000000..5dd943d0dc3e4
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptrmask-rv64.mir
@@ -0,0 +1,47 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name:            ptrmask_p0_s64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10, $x11
+    ; CHECK-LABEL: name: ptrmask_p0_s64
+    ; CHECK: liveins: $x10, $x11
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $x10 = COPY [[AND]]
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:gprb(p0) = COPY $x10
+    %1:gprb(s64) = COPY $x11
+    %2:gprb(p0) = G_PTRMASK %0(p0), %1(s64)
+    $x10 = COPY %2(p0)
+    PseudoRET implicit $x10
+...
+
+---
+name:            ptrmask_p0_const_s64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10
+    ; CHECK-LABEL: name: ptrmask_p0_const_s64
+    ; CHECK: liveins: $x10
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 10
+    ; CHECK-NEXT: $x10 = COPY [[ANDI]]
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:gprb(p0) = COPY $x10
+    %1:gprb(s64) = G_CONSTANT i64 10
+    %2:gprb(p0) = G_PTRMASK %0(p0), %1(s64)
+    $x10 = COPY %2(p0)
+    PseudoRET implicit $x10
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv32.mir
new file mode 100644
index 0000000000000..dd645b0bc12ee
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv32.mir
@@ -0,0 +1,22 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name:            ptrmask_p0_s32
+body:             |
+  bb.0:
+    liveins: $x10, $x11
+    ; CHECK-LABEL: name: ptrmask_p0_s32
+    ; CHECK: liveins: $x10, $x11
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+    ; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[COPY]], [[COPY1]](s32)
+    ; CHECK-NEXT: $x10 = COPY [[PTRMASK]](p0)
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(p0) = G_PTRMASK %0(p0), %1(s32)
+    $x10 = COPY %2(p0)
+    PseudoRET implicit $x10
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv64.mir
new file mode 100644
index 0000000000000..eced48ff15500
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv64.mir
@@ -0,0 +1,22 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name:            ptrmask_p0_s64
+body:             |
+  bb.0:
+    liveins: $x10, $x11
+    ; CHECK-LABEL: name: ptrmask_p0_s64
+    ; CHECK: liveins: $x10, $x11
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+    ; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[COPY]], [[COPY1]](s64)
+    ; CHECK-NEXT: $x10 = COPY [[PTRMASK]](p0)
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(p0) = G_PTRMASK %0(p0), %1(s64)
+    $x10 = COPY %2(p0)
+    PseudoRET implicit $x10
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv32.mir
new file mode 100644
index 0000000000000..089dd7ada0a9b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv32.mir
@@ -0,0 +1,24 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name:            ptrmask_p0_s32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10, $x11
+    ; CHECK-LABEL: name: ptrmask_p0_s32
+    ; CHECK: liveins: $x10, $x11
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:gprb(p0) = G_PTRMASK [[COPY]], [[COPY1]](s32)
+    ; CHECK-NEXT: $x10 = COPY [[PTRMASK]](p0)
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(p0) = G_PTRMASK %0(p0), %1(s32)
+    $x10 = COPY %2(p0)
+    PseudoRET implicit $x10
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv64.mir
new file mode 100644
index 0000000000000..e0e765e368d1d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv64.mir
@@ -0,0 +1,24 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name:            ptrmask_p0_s64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10, $x11
+    ; CHECK-LABEL: name: ptrmask_p0_s64
+    ; CHECK: liveins: $x10, $x11
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:gprb(p0) = G_PTRMASK [[COPY]], [[COPY1]](s64)
+    ; CHECK-NEXT: $x10 = COPY [[PTRMASK]](p0)
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(p0) = G_PTRMASK %0(p0), %1(s64)
+    $x10 = COPY %2(p0)
+    PseudoRET implicit $x10
+...