diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index d181755bb5850..015df83e77800 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -228,14 +228,20 @@ // MCPU-SIFIVE-P450-SAME: "-target-feature" "+f" // MCPU-SIFIVE-P450-SAME: "-target-feature" "+d" // MCPU-SIFIVE-P450-SAME: "-target-feature" "+c" +// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zic64b" // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicbom" // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicbop" // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicboz" +// MCPU-SIFIVE-P450-SAME: "-target-feature" "+ziccamoa" +// MCPU-SIFIVE-P450-SAME: "-target-feature" "+ziccif" +// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicclsm" +// MCPU-SIFIVE-P450-SAME: "-target-feature" "+ziccrse" // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicsr" // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zifencei" // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zihintntl" // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zihintpause" // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zihpm" +// MCPU-SIFIVE-P450-SAME: "-target-feature" "+za64rs" // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zfhmin" // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zba" // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbb" diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index d1cd9ba1dd84d..c8cf3644b21fb 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -223,9 +223,15 @@ def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model, FeatureStdExtF, FeatureStdExtD, FeatureStdExtC, + FeatureStdExtZa64rs, + FeatureStdExtZic64b, FeatureStdExtZicbop, FeatureStdExtZicbom, FeatureStdExtZicboz, + FeatureStdExtZiccamoa, + FeatureStdExtZiccif, + FeatureStdExtZicclsm, + FeatureStdExtZiccrse, FeatureStdExtZihintntl, FeatureStdExtZihintpause, FeatureStdExtZihpm,