release/18.x: [RISCV] Support rv{32, 64}e in the compiler builtins (#88252) #88525
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@kito-cheng What do you think about merging this PR to the release branch? |
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compiler-rt doesn't build for RISC-V embedded targets without this patch so to me it'd make sense to backport :) |
Register spills (save/restore) in RISC-V embedded work differently because there are less registers and different stack alignment. [GCC equivalent ](https://github.com/gcc-mirror/gcc/blob/master/libgcc/config/riscv/save-restore.S#L298C16-L336) Follow up from llvm#76777. --------- Signed-off-by: xermicus <cyrill@parity.io> (cherry picked from commit bd32aaa)
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Hi @wangpc-pp (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. |
Yeah, the description can be: |
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Backport bd32aaa
Requested by: @wangpc-pp