From 994bdb10e688540a6097a6deaded04c47af90b1b Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 30 Apr 2024 16:06:52 +0200 Subject: [PATCH 1/2] SystemZ: Implement copyPhysReg between vr128 and gr128 I have no idea if this is correct and I probably swapped the element ordering somewhere. --- llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 35 ++++++++ .../SystemZ/copy-phys-reg-gr128-to-vr128.mir | 82 +++++++++++++++++++ .../SystemZ/copy-phys-reg-vr128-to-gr128.mir | 70 ++++++++++++++++ 3 files changed, 187 insertions(+) create mode 100644 llvm/test/CodeGen/SystemZ/copy-phys-reg-gr128-to-vr128.mir create mode 100644 llvm/test/CodeGen/SystemZ/copy-phys-reg-vr128-to-gr128.mir diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp index 6b75c30943b40..ced7b38a1d717 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -840,6 +840,41 @@ void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB, return; } + if (SystemZ::GR128BitRegClass.contains(DestReg) && + SystemZ::VR128BitRegClass.contains(SrcReg)) { + MCRegister DestH64 = RI.getSubReg(DestReg, SystemZ::subreg_h64); + MCRegister DestL64 = RI.getSubReg(DestReg, SystemZ::subreg_l64); + + BuildMI(MBB, MBBI, DL, get(SystemZ::VLGVG), DestL64) + .addReg(SrcReg) + .addReg(SystemZ::NoRegister) + .addImm(0) + .addDef(DestReg, RegState::Implicit); + BuildMI(MBB, MBBI, DL, get(SystemZ::VLGVG), DestH64) + .addReg(SrcReg, getKillRegState(KillSrc)) + .addReg(SystemZ::NoRegister) + .addImm(1); + return; + } + + if (SystemZ::VR128BitRegClass.contains(DestReg) && + SystemZ::GR128BitRegClass.contains(SrcReg)) { + MCRegister SrcH64 = RI.getSubReg(SrcReg, SystemZ::subreg_h64); + MCRegister SrcL64 = RI.getSubReg(SrcReg, SystemZ::subreg_l64); + + BuildMI(MBB, MBBI, DL, get(SystemZ::VLVGG), DestReg) + .addReg(DestReg, RegState::Undef) + .addReg(SrcH64) + .addReg(SystemZ::NoRegister) + .addImm(0); + BuildMI(MBB, MBBI, DL, get(SystemZ::VLVGG), DestReg) + .addReg(DestReg) + .addReg(SrcL64) + .addReg(SystemZ::NoRegister) + .addImm(1); + return; + } + // Everything else needs only one instruction. unsigned Opcode; if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg)) diff --git a/llvm/test/CodeGen/SystemZ/copy-phys-reg-gr128-to-vr128.mir b/llvm/test/CodeGen/SystemZ/copy-phys-reg-gr128-to-vr128.mir new file mode 100644 index 0000000000000..537d5b2ae0df1 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/copy-phys-reg-gr128-to-vr128.mir @@ -0,0 +1,82 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=s390x-ibm-linux -mcpu=z13 -run-pass=postrapseudos -o - %s | FileCheck %s + +--- +name: copy_gr128_to_vr128__r0q_to_v0 +tracksRegLiveness: true +body: | + bb.0: + liveins: $r0q + ; CHECK-LABEL: name: copy_gr128_to_vr128__r0q_to_v0 + ; CHECK: liveins: $r0q + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $v0 = VLVGG undef $v0, $r0d, $noreg, 0 + ; CHECK-NEXT: $v0 = VLVGG $v0, $r1d, $noreg, 1 + ; CHECK-NEXT: Return implicit $v0 + $v0 = COPY $r0q + Return implicit $v0 +... + +--- +name: copy_gr128_to_vr128__r0q_to_v0_killed +tracksRegLiveness: true +body: | + bb.0: + liveins: $r0q + ; CHECK-LABEL: name: copy_gr128_to_vr128__r0q_to_v0_killed + ; CHECK: liveins: $r0q + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $v0 = VLVGG undef $v0, $r0d, $noreg, 0 + ; CHECK-NEXT: $v0 = VLVGG $v0, $r1d, $noreg, 1 + ; CHECK-NEXT: Return implicit $v0 + $v0 = COPY killed $r0q + Return implicit $v0 +... + +--- +name: copy_gr128_to_vr128__r0q_to_v0_undef +tracksRegLiveness: true +body: | + bb.0: + liveins: $r0q + ; CHECK-LABEL: name: copy_gr128_to_vr128__r0q_to_v0_undef + ; CHECK: liveins: $r0q + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $v0 = KILL undef $r0q + ; CHECK-NEXT: Return implicit $v0 + $v0 = COPY undef $r0q + Return implicit $v0 +... + +--- +name: copy_gr128_to_vr128__r0q_to_v0_subreg0 +tracksRegLiveness: true +body: | + bb.0: + liveins: $r0d + ; CHECK-LABEL: name: copy_gr128_to_vr128__r0q_to_v0_subreg0 + ; CHECK: liveins: $r0d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $v0 = VLVGG undef $v0, $r0d, $noreg, 0 + ; CHECK-NEXT: $v0 = VLVGG $v0, $r1d, $noreg, 1 + ; CHECK-NEXT: Return implicit $v0 + $v0 = COPY $r0q + Return implicit $v0 +... + +--- +name: copy_gr128_to_vr128__r0q_to_v0_subreg1 +tracksRegLiveness: true +body: | + bb.0: + liveins: $r1d + ; CHECK-LABEL: name: copy_gr128_to_vr128__r0q_to_v0_subreg1 + ; CHECK: liveins: $r1d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $v0 = VLVGG undef $v0, $r0d, $noreg, 0 + ; CHECK-NEXT: $v0 = VLVGG $v0, $r1d, $noreg, 1 + ; CHECK-NEXT: Return implicit $v0 + $v0 = COPY $r0q + Return implicit $v0 +... + diff --git a/llvm/test/CodeGen/SystemZ/copy-phys-reg-vr128-to-gr128.mir b/llvm/test/CodeGen/SystemZ/copy-phys-reg-vr128-to-gr128.mir new file mode 100644 index 0000000000000..b75e999c0c2f9 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/copy-phys-reg-vr128-to-gr128.mir @@ -0,0 +1,70 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=s390x-ibm-linux -mcpu=z13 -run-pass=postrapseudos -o - %s | FileCheck %s + +--- +name: copy_vr128_to_gr128__v0_to_r0q +tracksRegLiveness: true +body: | + bb.0: + liveins: $v0 + ; CHECK-LABEL: name: copy_vr128_to_gr128__v0_to_r0q + ; CHECK: liveins: $v0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r1d = VLGVG $v0, $noreg, 0, implicit-def $r0q + ; CHECK-NEXT: $r0d = VLGVG $v0, $noreg, 1 + ; CHECK-NEXT: Return implicit $r0q + $r0q = COPY $v0 + Return implicit $r0q +... + +--- +name: copy_vr128_to_gr128__v0_to_r0q_killed +tracksRegLiveness: true +body: | + bb.0: + liveins: $v0 + ; CHECK-LABEL: name: copy_vr128_to_gr128__v0_to_r0q_killed + ; CHECK: liveins: $v0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r1d = VLGVG $v0, $noreg, 0, implicit-def $r0q + ; CHECK-NEXT: $r0d = VLGVG killed $v0, $noreg, 1 + ; CHECK-NEXT: Return implicit $r0q + $r0q = COPY killed $v0 + Return implicit $r0q +... + +--- +name: copy_vr128_to_gr128__v0_to_r0q_undef +tracksRegLiveness: true +body: | + bb.0: + ; CHECK-LABEL: name: copy_vr128_to_gr128__v0_to_r0q_undef + ; CHECK: $r0q = KILL undef $v0 + ; CHECK-NEXT: Return implicit $r0q + $r0q = COPY undef $v0 + Return implicit $r0q +... + +--- +name: copy_vr128_to_gr128__v0_to_r0q_undef_use_subreg0 +tracksRegLiveness: true +body: | + bb.0: + ; CHECK-LABEL: name: copy_vr128_to_gr128__v0_to_r0q_undef_use_subreg0 + ; CHECK: $r0q = KILL undef $v0 + ; CHECK-NEXT: Return implicit $r0d + $r0q = COPY undef $v0 + Return implicit $r0d +... + +--- +name: copy_vr128_to_gr128__v0_to_r0q_undef_use_subreg1 +tracksRegLiveness: true +body: | + bb.0: + ; CHECK-LABEL: name: copy_vr128_to_gr128__v0_to_r0q_undef_use_subreg1 + ; CHECK: $r0q = KILL undef $v0 + ; CHECK-NEXT: Return implicit $r1d + $r0q = COPY undef $v0 + Return implicit $r1d +... From 9d662485aec753b6a7df3ad2c21e6ab6163b311c Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 30 Apr 2024 20:05:47 +0200 Subject: [PATCH 2/2] Address comments --- llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 20 +++++-------------- .../SystemZ/copy-phys-reg-gr128-to-vr128.mir | 12 ++++------- .../SystemZ/copy-phys-reg-vr128-to-gr128.mir | 8 ++++---- 3 files changed, 13 insertions(+), 27 deletions(-) diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp index ced7b38a1d717..4e28000f19a2f 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -845,12 +845,12 @@ void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB, MCRegister DestH64 = RI.getSubReg(DestReg, SystemZ::subreg_h64); MCRegister DestL64 = RI.getSubReg(DestReg, SystemZ::subreg_l64); - BuildMI(MBB, MBBI, DL, get(SystemZ::VLGVG), DestL64) + BuildMI(MBB, MBBI, DL, get(SystemZ::VLGVG), DestH64) .addReg(SrcReg) .addReg(SystemZ::NoRegister) .addImm(0) .addDef(DestReg, RegState::Implicit); - BuildMI(MBB, MBBI, DL, get(SystemZ::VLGVG), DestH64) + BuildMI(MBB, MBBI, DL, get(SystemZ::VLGVG), DestL64) .addReg(SrcReg, getKillRegState(KillSrc)) .addReg(SystemZ::NoRegister) .addImm(1); @@ -859,19 +859,9 @@ void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB, if (SystemZ::VR128BitRegClass.contains(DestReg) && SystemZ::GR128BitRegClass.contains(SrcReg)) { - MCRegister SrcH64 = RI.getSubReg(SrcReg, SystemZ::subreg_h64); - MCRegister SrcL64 = RI.getSubReg(SrcReg, SystemZ::subreg_l64); - - BuildMI(MBB, MBBI, DL, get(SystemZ::VLVGG), DestReg) - .addReg(DestReg, RegState::Undef) - .addReg(SrcH64) - .addReg(SystemZ::NoRegister) - .addImm(0); - BuildMI(MBB, MBBI, DL, get(SystemZ::VLVGG), DestReg) - .addReg(DestReg) - .addReg(SrcL64) - .addReg(SystemZ::NoRegister) - .addImm(1); + BuildMI(MBB, MBBI, DL, get(SystemZ::VLVGP), DestReg) + .addReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64)) + .addReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64)); return; } diff --git a/llvm/test/CodeGen/SystemZ/copy-phys-reg-gr128-to-vr128.mir b/llvm/test/CodeGen/SystemZ/copy-phys-reg-gr128-to-vr128.mir index 537d5b2ae0df1..a2a07ac5c7f5a 100644 --- a/llvm/test/CodeGen/SystemZ/copy-phys-reg-gr128-to-vr128.mir +++ b/llvm/test/CodeGen/SystemZ/copy-phys-reg-gr128-to-vr128.mir @@ -10,8 +10,7 @@ body: | ; CHECK-LABEL: name: copy_gr128_to_vr128__r0q_to_v0 ; CHECK: liveins: $r0q ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: $v0 = VLVGG undef $v0, $r0d, $noreg, 0 - ; CHECK-NEXT: $v0 = VLVGG $v0, $r1d, $noreg, 1 + ; CHECK-NEXT: $v0 = VLVGP $r0d, $r1d ; CHECK-NEXT: Return implicit $v0 $v0 = COPY $r0q Return implicit $v0 @@ -26,8 +25,7 @@ body: | ; CHECK-LABEL: name: copy_gr128_to_vr128__r0q_to_v0_killed ; CHECK: liveins: $r0q ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: $v0 = VLVGG undef $v0, $r0d, $noreg, 0 - ; CHECK-NEXT: $v0 = VLVGG $v0, $r1d, $noreg, 1 + ; CHECK-NEXT: $v0 = VLVGP $r0d, $r1d ; CHECK-NEXT: Return implicit $v0 $v0 = COPY killed $r0q Return implicit $v0 @@ -57,8 +55,7 @@ body: | ; CHECK-LABEL: name: copy_gr128_to_vr128__r0q_to_v0_subreg0 ; CHECK: liveins: $r0d ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: $v0 = VLVGG undef $v0, $r0d, $noreg, 0 - ; CHECK-NEXT: $v0 = VLVGG $v0, $r1d, $noreg, 1 + ; CHECK-NEXT: $v0 = VLVGP $r0d, $r1d ; CHECK-NEXT: Return implicit $v0 $v0 = COPY $r0q Return implicit $v0 @@ -73,8 +70,7 @@ body: | ; CHECK-LABEL: name: copy_gr128_to_vr128__r0q_to_v0_subreg1 ; CHECK: liveins: $r1d ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: $v0 = VLVGG undef $v0, $r0d, $noreg, 0 - ; CHECK-NEXT: $v0 = VLVGG $v0, $r1d, $noreg, 1 + ; CHECK-NEXT: $v0 = VLVGP $r0d, $r1d ; CHECK-NEXT: Return implicit $v0 $v0 = COPY $r0q Return implicit $v0 diff --git a/llvm/test/CodeGen/SystemZ/copy-phys-reg-vr128-to-gr128.mir b/llvm/test/CodeGen/SystemZ/copy-phys-reg-vr128-to-gr128.mir index b75e999c0c2f9..c1141aaf7a2ee 100644 --- a/llvm/test/CodeGen/SystemZ/copy-phys-reg-vr128-to-gr128.mir +++ b/llvm/test/CodeGen/SystemZ/copy-phys-reg-vr128-to-gr128.mir @@ -10,8 +10,8 @@ body: | ; CHECK-LABEL: name: copy_vr128_to_gr128__v0_to_r0q ; CHECK: liveins: $v0 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: $r1d = VLGVG $v0, $noreg, 0, implicit-def $r0q - ; CHECK-NEXT: $r0d = VLGVG $v0, $noreg, 1 + ; CHECK-NEXT: $r0d = VLGVG $v0, $noreg, 0, implicit-def $r0q + ; CHECK-NEXT: $r1d = VLGVG $v0, $noreg, 1 ; CHECK-NEXT: Return implicit $r0q $r0q = COPY $v0 Return implicit $r0q @@ -26,8 +26,8 @@ body: | ; CHECK-LABEL: name: copy_vr128_to_gr128__v0_to_r0q_killed ; CHECK: liveins: $v0 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: $r1d = VLGVG $v0, $noreg, 0, implicit-def $r0q - ; CHECK-NEXT: $r0d = VLGVG killed $v0, $noreg, 1 + ; CHECK-NEXT: $r0d = VLGVG $v0, $noreg, 0, implicit-def $r0q + ; CHECK-NEXT: $r1d = VLGVG killed $v0, $noreg, 1 ; CHECK-NEXT: Return implicit $r0q $r0q = COPY killed $v0 Return implicit $r0q