diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.cpp b/clang/lib/CodeGen/CGOpenMPRuntime.cpp index f6d12d46cfc07..c542e34af7ba6 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntime.cpp +++ b/clang/lib/CodeGen/CGOpenMPRuntime.cpp @@ -5927,12 +5927,16 @@ void CGOpenMPRuntime::emitTargetOutlinedFunctionHelper( CodeGenFunction CGF(CGM, true); llvm::OpenMPIRBuilder::FunctionGenCallback &&GenerateOutlinedFunction = - [&CGF, &D, &CodeGen](StringRef EntryFnName) { + [&CGF, &D, &CodeGen, this](StringRef EntryFnName) { const CapturedStmt &CS = *D.getCapturedStmt(OMPD_target); CGOpenMPTargetRegionInfo CGInfo(CS, CodeGen, EntryFnName); CodeGenFunction::CGCapturedStmtRAII CapInfoRAII(CGF, &CGInfo); - return CGF.GenerateOpenMPCapturedStmtFunction(CS, D.getBeginLoc()); + if (CGM.getLangOpts().OpenMPIsTargetDevice && !isGPU()) + return CGF.GenerateOpenMPCapturedStmtFunctionAggregate( + CS, D.getBeginLoc()); + else + return CGF.GenerateOpenMPCapturedStmtFunction(CS, D.getBeginLoc()); }; OMPBuilder.emitTargetRegionFunction(EntryInfo, GenerateOutlinedFunction, diff --git a/clang/lib/CodeGen/CGStmtOpenMP.cpp b/clang/lib/CodeGen/CGStmtOpenMP.cpp index 6410f9e102c90..7b95b51f86b77 100644 --- a/clang/lib/CodeGen/CGStmtOpenMP.cpp +++ b/clang/lib/CodeGen/CGStmtOpenMP.cpp @@ -629,6 +629,102 @@ static llvm::Function *emitOutlinedFunctionPrologue( return F; } +static llvm::Function *emitOutlinedFunctionPrologueAggregate( + CodeGenFunction &CGF, FunctionArgList &Args, + llvm::MapVector> + &LocalAddrs, + llvm::DenseMap> + &VLASizes, + llvm::Value *&CXXThisValue, const CapturedStmt &CS, SourceLocation Loc, + StringRef FunctionName) { + const CapturedDecl *CD = CS.getCapturedDecl(); + const RecordDecl *RD = CS.getCapturedRecordDecl(); + + CXXThisValue = nullptr; + // Build the argument list. + CodeGenModule &CGM = CGF.CGM; + ASTContext &Ctx = CGM.getContext(); + Args.append(CD->param_begin(), CD->param_end()); + + // Create the function declaration. + const CGFunctionInfo &FuncInfo = + CGM.getTypes().arrangeBuiltinFunctionDeclaration(Ctx.VoidTy, Args); + llvm::FunctionType *FuncLLVMTy = CGM.getTypes().GetFunctionType(FuncInfo); + + auto *F = + llvm::Function::Create(FuncLLVMTy, llvm::GlobalValue::InternalLinkage, + FunctionName, &CGM.getModule()); + CGM.SetInternalFunctionAttributes(CD, F, FuncInfo); + if (CD->isNothrow()) + F->setDoesNotThrow(); + F->setDoesNotRecurse(); + + // Generate the function. + CGF.StartFunction(CD, Ctx.VoidTy, F, FuncInfo, Args, Loc, Loc); + Address ContextAddr = CGF.GetAddrOfLocalVar(CD->getContextParam()); + llvm::Value *ContextV = CGF.Builder.CreateLoad(ContextAddr); + LValue ContextLV = CGF.MakeNaturalAlignAddrLValue( + ContextV, CGM.getContext().getTagDeclType(RD)); + auto I = CS.captures().begin(); + for (const FieldDecl *FD : RD->fields()) { + LValue FieldLV = CGF.EmitLValueForFieldInitialization(ContextLV, FD); + // Do not map arguments if we emit function with non-original types. + Address LocalAddr = FieldLV.getAddress(CGF); + // If we are capturing a pointer by copy we don't need to do anything, just + // use the value that we get from the arguments. + if (I->capturesVariableByCopy() && FD->getType()->isAnyPointerType()) { + const VarDecl *CurVD = I->getCapturedVar(); + LocalAddrs.insert({FD, {CurVD, LocalAddr}}); + ++I; + continue; + } + + LValue ArgLVal = + CGF.MakeAddrLValue(LocalAddr, FD->getType(), AlignmentSource::Decl); + if (FD->hasCapturedVLAType()) { + llvm::Value *ExprArg = CGF.EmitLoadOfScalar(ArgLVal, I->getLocation()); + const VariableArrayType *VAT = FD->getCapturedVLAType(); + VLASizes.try_emplace(FD, VAT->getSizeExpr(), ExprArg); + } else if (I->capturesVariable()) { + const VarDecl *Var = I->getCapturedVar(); + QualType VarTy = Var->getType(); + Address ArgAddr = ArgLVal.getAddress(CGF); + if (ArgLVal.getType()->isLValueReferenceType()) { + ArgAddr = CGF.EmitLoadOfReference(ArgLVal); + } else if (!VarTy->isVariablyModifiedType() || !VarTy->isPointerType()) { + assert(ArgLVal.getType()->isPointerType()); + ArgAddr = CGF.EmitLoadOfPointer( + ArgAddr, ArgLVal.getType()->castAs()); + } + LocalAddrs.insert( + {FD, + {Var, Address(ArgAddr.getBasePointer(), ArgAddr.getElementType(), + Ctx.getDeclAlign(Var))}}); + } else if (I->capturesVariableByCopy()) { + assert(!FD->getType()->isAnyPointerType() && + "Not expecting a captured pointer."); + const VarDecl *Var = I->getCapturedVar(); + Address CopyAddr = CGF.CreateMemTemp(FD->getType(), Ctx.getDeclAlign(FD), + Var->getName()); + LValue CopyLVal = + CGF.MakeAddrLValue(CopyAddr, FD->getType(), AlignmentSource::Decl); + + RValue ArgRVal = CGF.EmitLoadOfLValue(ArgLVal, I->getLocation()); + CGF.EmitStoreThroughLValue(ArgRVal, CopyLVal); + + LocalAddrs.insert({FD, {Var, CopyAddr}}); + } else { + // If 'this' is captured, load it into CXXThisValue. + assert(I->capturesThis()); + CXXThisValue = CGF.EmitLoadOfScalar(ArgLVal, I->getLocation()); + LocalAddrs.insert({FD, {nullptr, ArgLVal.getAddress(CGF)}}); + } + ++I; + } + + return F; +} + llvm::Function * CodeGenFunction::GenerateOpenMPCapturedStmtFunction(const CapturedStmt &S, SourceLocation Loc) { @@ -711,6 +807,36 @@ CodeGenFunction::GenerateOpenMPCapturedStmtFunction(const CapturedStmt &S, return WrapperF; } +llvm::Function *CodeGenFunction::GenerateOpenMPCapturedStmtFunctionAggregate( + const CapturedStmt &S, SourceLocation Loc) { + assert( + CapturedStmtInfo && + "CapturedStmtInfo should be set when generating the captured function"); + const CapturedDecl *CD = S.getCapturedDecl(); + // Build the argument list. + FunctionArgList Args; + llvm::MapVector> LocalAddrs; + llvm::DenseMap> VLASizes; + StringRef FunctionName = CapturedStmtInfo->getHelperName(); + llvm::Function *F = emitOutlinedFunctionPrologueAggregate( + *this, Args, LocalAddrs, VLASizes, CXXThisValue, S, Loc, FunctionName); + CodeGenFunction::OMPPrivateScope LocalScope(*this); + for (const auto &LocalAddrPair : LocalAddrs) { + if (LocalAddrPair.second.first) { + LocalScope.addPrivate(LocalAddrPair.second.first, + LocalAddrPair.second.second); + } + } + (void)LocalScope.Privatize(); + for (const auto &VLASizePair : VLASizes) + VLASizeMap[VLASizePair.second.first] = VLASizePair.second.second; + PGO.assignRegionCounters(GlobalDecl(CD), F); + CapturedStmtInfo->EmitBody(*this, CD->getBody()); + (void)LocalScope.ForceCleanup(); + FinishFunction(CD->getBodyRBrace()); + return F; +} + //===----------------------------------------------------------------------===// // OpenMP Directive Emission //===----------------------------------------------------------------------===// diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h index 45585361a4fc9..f5186ca5c3332 100644 --- a/clang/lib/CodeGen/CodeGenFunction.h +++ b/clang/lib/CodeGen/CodeGenFunction.h @@ -3643,6 +3643,9 @@ class CodeGenFunction : public CodeGenTypeCache { Address GenerateCapturedStmtArgument(const CapturedStmt &S); llvm::Function *GenerateOpenMPCapturedStmtFunction(const CapturedStmt &S, SourceLocation Loc); + llvm::Function * + GenerateOpenMPCapturedStmtFunctionAggregate(const CapturedStmt &S, + SourceLocation Loc); void GenerateOpenMPCapturedVars(const CapturedStmt &S, SmallVectorImpl &CapturedVars); void emitOMPSimpleStore(LValue LVal, RValue RVal, QualType RValTy, diff --git a/clang/test/OpenMP/declare_target_codegen.cpp b/clang/test/OpenMP/declare_target_codegen.cpp index ba93772ede3e8..81116c6617b5b 100644 --- a/clang/test/OpenMP/declare_target_codegen.cpp +++ b/clang/test/OpenMP/declare_target_codegen.cpp @@ -150,7 +150,7 @@ int bar() { return 1 + foo() + bar() + baz1() + baz2(); } int maini1() { int a; static long aa = 32 + bbb + ccc + fff + ggg; -// CHECK-DAG: define weak_odr protected void @__omp_offloading_{{.*}}maini1{{.*}}_l[[@LINE+1]](ptr {{.*}}, ptr noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %{{.*}}, i64 {{.*}}, i64 {{.*}}) +// CHECK-DAG: define weak_odr protected void @__omp_offloading_{{.*}}maini1{{.*}}_l[[@LINE+1]](ptr {{.*}}, ptr {{.*}}) #pragma omp target map(tofrom \ : a, b) { @@ -163,7 +163,7 @@ int maini1() { int baz3() { return 2 + baz2(); } int baz2() { -// CHECK-DAG: define weak_odr protected void @__omp_offloading_{{.*}}baz2{{.*}}_l[[@LINE+1]](ptr {{.*}}, i64 {{.*}}) +// CHECK-DAG: define weak_odr protected void @__omp_offloading_{{.*}}baz2{{.*}}_l[[@LINE+1]](ptr {{.*}}, ptr {{.*}}) #pragma omp target parallel ++c; return 2 + baz3(); @@ -175,7 +175,7 @@ static __typeof(create) __t_create __attribute__((__weakref__("__create"))); int baz5() { bool a; -// CHECK-DAG: define weak_odr protected void @__omp_offloading_{{.*}}baz5{{.*}}_l[[@LINE+1]](ptr {{.*}}, i64 {{.*}}) +// CHECK-DAG: define weak_odr protected void @__omp_offloading_{{.*}}baz5{{.*}}_l[[@LINE+1]](ptr {{.*}}, ptr {{.*}}) #pragma omp target a = __extension__(void *) & __t_create != 0; return a; diff --git a/clang/test/OpenMP/declare_target_link_codegen.cpp b/clang/test/OpenMP/declare_target_link_codegen.cpp index 189c9ac59c153..ba63a4bc54347 100644 --- a/clang/test/OpenMP/declare_target_link_codegen.cpp +++ b/clang/test/OpenMP/declare_target_link_codegen.cpp @@ -52,7 +52,7 @@ int maini1() { return 0; } -// DEVICE: define weak_odr protected void @__omp_offloading_{{.*}}_{{.*}}maini1{{.*}}_l44(ptr {{[^,]+}}, ptr noundef nonnull align {{[0-9]+}} dereferenceable{{[^,]*}} +// DEVICE: define weak_odr protected void @__omp_offloading_{{.*}}_{{.*}}maini1{{.*}}_l44(ptr {{[^,]+}}, ptr {{[^,]*}} // DEVICE: [[C_REF:%.+]] = load ptr, ptr @c_decl_tgt_ref_ptr, // DEVICE: [[C:%.+]] = load i32, ptr [[C_REF]], // DEVICE: store i32 [[C]], ptr % diff --git a/clang/test/OpenMP/distribute_codegen.cpp b/clang/test/OpenMP/distribute_codegen.cpp index 34d14c89fedae..aaa2898083966 100644 --- a/clang/test/OpenMP/distribute_codegen.cpp +++ b/clang/test/OpenMP/distribute_codegen.cpp @@ -1947,19 +1947,18 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 3 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.omp_outlined, ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]]) // CHECK17-NEXT: ret void // // @@ -2058,19 +2057,18 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 3 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.omp_outlined, ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]]) // CHECK17-NEXT: ret void // // @@ -2169,19 +2167,18 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 3 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.omp_outlined, ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]]) // CHECK17-NEXT: ret void // // @@ -2297,13 +2294,18 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[A:%.*]] = alloca i8, align 1 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.omp_outlined, ptr [[A_ADDR]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1 +// CHECK17-NEXT: store i8 [[TMP2]], ptr [[A]], align 1 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.omp_outlined, ptr [[A]]) // CHECK17-NEXT: ret void // // @@ -2401,13 +2403,18 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.omp_outlined, ptr [[AA_ADDR]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 2 +// CHECK17-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.omp_outlined, ptr [[AA]]) // CHECK17-NEXT: ret void // // @@ -2494,19 +2501,18 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 -// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) +// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 3 +// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.omp_outlined, ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]]) // CHECK19-NEXT: ret void // // @@ -2601,19 +2607,18 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 -// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) +// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 3 +// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.omp_outlined, ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]]) // CHECK19-NEXT: ret void // // @@ -2708,19 +2713,18 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 -// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) +// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 3 +// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.omp_outlined, ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]]) // CHECK19-NEXT: ret void // // @@ -2832,13 +2836,18 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 -// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i8, align 1 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.omp_outlined, ptr [[A_ADDR]]) +// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1 +// CHECK19-NEXT: store i8 [[TMP2]], ptr [[A]], align 1 +// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.omp_outlined, ptr [[A]]) // CHECK19-NEXT: ret void // // @@ -2936,13 +2945,18 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 -// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.omp_outlined, ptr [[AA_ADDR]]) +// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 2 +// CHECK19-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.omp_outlined, ptr [[AA]]) // CHECK19-NEXT: ret void // // diff --git a/clang/test/OpenMP/distribute_simd_codegen.cpp b/clang/test/OpenMP/distribute_simd_codegen.cpp index 9a192502125f9..d2464e821e292 100644 --- a/clang/test/OpenMP/distribute_simd_codegen.cpp +++ b/clang/test/OpenMP/distribute_simd_codegen.cpp @@ -5461,19 +5461,18 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 3 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]]) // CHECK17-NEXT: ret void // // @@ -5581,19 +5580,18 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 3 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]]) // CHECK17-NEXT: ret void // // @@ -5699,19 +5697,18 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 3 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]]) // CHECK17-NEXT: ret void // // @@ -5834,15 +5831,22 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[I:%.*]] = alloca i8, align 1 +// CHECK17-NEXT: [[A:%.*]] = alloca i8, align 1 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[I]], ptr [[I_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I_ADDR]], ptr [[A_ADDR]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1 +// CHECK17-NEXT: store i8 [[TMP2]], ptr [[I]], align 1 +// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 +// CHECK17-NEXT: store i8 [[TMP4]], ptr [[A]], align 1 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I]], ptr [[A]]) // CHECK17-NEXT: ret void // // @@ -5961,13 +5965,18 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA_ADDR]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 2 +// CHECK17-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA]]) // CHECK17-NEXT: ret void // // @@ -6061,19 +6070,18 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 -// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) +// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 3 +// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]]) // CHECK19-NEXT: ret void // // @@ -6177,19 +6185,18 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 -// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) +// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 3 +// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]]) // CHECK19-NEXT: ret void // // @@ -6291,19 +6298,18 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 -// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) +// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 3 +// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]]) // CHECK19-NEXT: ret void // // @@ -6422,15 +6428,22 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 -// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[I:%.*]] = alloca i8, align 1 +// CHECK19-NEXT: [[A:%.*]] = alloca i8, align 1 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I_ADDR]], ptr [[A_ADDR]]) +// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1 +// CHECK19-NEXT: store i8 [[TMP2]], ptr [[I]], align 1 +// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 +// CHECK19-NEXT: store i8 [[TMP4]], ptr [[A]], align 1 +// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I]], ptr [[A]]) // CHECK19-NEXT: ret void // // @@ -6549,13 +6562,18 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 -// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA_ADDR]]) +// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 2 +// CHECK19-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA]]) // CHECK19-NEXT: ret void // // @@ -6649,19 +6667,18 @@ int fint(void) { return ftemplate(); } // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 -// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 +// CHECK21-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 -// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) +// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK21-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 1 +// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 2 +// CHECK21-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 3 +// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]]) // CHECK21-NEXT: ret void // // @@ -6769,19 +6786,18 @@ int fint(void) { return ftemplate(); } // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 -// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 +// CHECK21-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 -// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) +// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK21-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// CHECK21-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 3 +// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]]) // CHECK21-NEXT: ret void // // @@ -6887,19 +6903,18 @@ int fint(void) { return ftemplate(); } // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 -// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 +// CHECK21-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 -// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) +// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK21-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 2 +// CHECK21-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 3 +// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]]) // CHECK21-NEXT: ret void // // @@ -7022,15 +7037,22 @@ int fint(void) { return ftemplate(); } // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 -// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK21-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK21-NEXT: [[I:%.*]] = alloca i8, align 1 +// CHECK21-NEXT: [[A:%.*]] = alloca i8, align 1 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[I]], ptr [[I_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I_ADDR]], ptr [[A_ADDR]]) +// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK21-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1 +// CHECK21-NEXT: store i8 [[TMP2]], ptr [[I]], align 1 +// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 1 +// CHECK21-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 +// CHECK21-NEXT: store i8 [[TMP4]], ptr [[A]], align 1 +// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I]], ptr [[A]]) // CHECK21-NEXT: ret void // // @@ -7180,13 +7202,18 @@ int fint(void) { return ftemplate(); } // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 -// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK21-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA_ADDR]]) +// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK21-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 2 +// CHECK21-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA]]) // CHECK21-NEXT: ret void // // @@ -7280,19 +7307,18 @@ int fint(void) { return ftemplate(); } // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 -// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 +// CHECK23-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 -// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) +// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK23-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 1 +// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 2 +// CHECK23-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 3 +// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]]) // CHECK23-NEXT: ret void // // @@ -7396,19 +7422,18 @@ int fint(void) { return ftemplate(); } // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 -// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 +// CHECK23-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 -// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) +// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK23-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// CHECK23-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 3 +// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]]) // CHECK23-NEXT: ret void // // @@ -7510,19 +7535,18 @@ int fint(void) { return ftemplate(); } // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 -// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 +// CHECK23-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 -// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) +// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK23-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 2 +// CHECK23-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 3 +// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]]) // CHECK23-NEXT: ret void // // @@ -7641,15 +7665,22 @@ int fint(void) { return ftemplate(); } // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 -// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK23-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK23-NEXT: [[I:%.*]] = alloca i8, align 1 +// CHECK23-NEXT: [[A:%.*]] = alloca i8, align 1 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I_ADDR]], ptr [[A_ADDR]]) +// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK23-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1 +// CHECK23-NEXT: store i8 [[TMP2]], ptr [[I]], align 1 +// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 1 +// CHECK23-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1 +// CHECK23-NEXT: store i8 [[TMP4]], ptr [[A]], align 1 +// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I]], ptr [[A]]) // CHECK23-NEXT: ret void // // @@ -7799,13 +7830,18 @@ int fint(void) { return ftemplate(); } // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 -// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK23-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA_ADDR]]) +// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK23-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 2 +// CHECK23-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA]]) // CHECK23-NEXT: ret void // // diff --git a/clang/test/OpenMP/openmp_offload_codegen.cpp b/clang/test/OpenMP/openmp_offload_codegen.cpp index 5246c7f6d7827..33563472b7253 100644 --- a/clang/test/OpenMP/openmp_offload_codegen.cpp +++ b/clang/test/OpenMP/openmp_offload_codegen.cpp @@ -25,7 +25,7 @@ void target_maps_parallel_integer(int a){ } } -// CK1-DEVICE: {{.*}}void @__omp_offloading_{{.*}}(ptr {{[^,]+}}, ptr noundef nonnull align 4 dereferenceable(4){{.*}} +// CK1-DEVICE: {{.*}}void @__omp_offloading_{{.*}}(ptr {{[^,]+}}, ptr {{.*}} // CK1: {{.*}}void {{.*}}target_maps_parallel_integer{{.*}} { diff --git a/clang/test/OpenMP/target_firstprivate_codegen.cpp b/clang/test/OpenMP/target_firstprivate_codegen.cpp index 02de48e6aa395..800291fe0a24d 100644 --- a/clang/test/OpenMP/target_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/target_firstprivate_codegen.cpp @@ -9961,874 +9961,934 @@ int bar(int n, double *ptr) { // // // TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63 -// TCHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] { +// TCHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // TCHECK-NEXT: entry: // TCHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// TCHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK-NEXT: [[GA_ADDR:%.*]] = alloca i64, align 8 +// TCHECK-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-NEXT: [[A:%.*]] = alloca i32, align 4 +// TCHECK-NEXT: [[GA:%.*]] = alloca i32, align 4 // TCHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// TCHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// TCHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 8 -// TCHECK-NEXT: store i64 [[GA]], ptr [[GA_ADDR]], align 8 +// TCHECK-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// TCHECK-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// TCHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 3 +// TCHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8 +// TCHECK-NEXT: store i32 [[TMP5]], ptr [[GA]], align 4 // TCHECK-NEXT: ret void // // // TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70 -// TCHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// TCHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // TCHECK-NEXT: entry: // TCHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// TCHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// TCHECK-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// TCHECK-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// TCHECK-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK-NEXT: [[B5:%.*]] = alloca [10 x float], align 4 +// TCHECK-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-NEXT: [[AA:%.*]] = alloca i16, align 2 +// TCHECK-NEXT: [[B:%.*]] = alloca [10 x float], align 4 // TCHECK-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // TCHECK-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// TCHECK-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8 +// TCHECK-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 // TCHECK-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 // TCHECK-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 8 -// TCHECK-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// TCHECK-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 // TCHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// TCHECK-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// TCHECK-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// TCHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 -// TCHECK-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 -// TCHECK-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// TCHECK-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 -// TCHECK-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 -// TCHECK-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 -// TCHECK-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 -// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// TCHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// TCHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 -// TCHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// TCHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// TCHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 -// TCHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 -// TCHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 -// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i64 40, i1 false) -// TCHECK-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave.p0() -// TCHECK-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 8 -// TCHECK-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 4 -// TCHECK-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 -// TCHECK-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP1]], 4 -// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i64 [[TMP9]], i1 false) -// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i64 400, i1 false) -// TCHECK-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]] -// TCHECK-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP10]], align 8 -// TCHECK-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 -// TCHECK-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR2]], align 8 -// TCHECK-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]] -// TCHECK-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 8 -// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[VLA8]], ptr align 8 [[TMP6]], i64 [[TMP12]], i1 false) -// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[D9]], ptr align 8 [[TMP7]], i64 16, i1 false) -// TCHECK-NEXT: [[TMP13:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// TCHECK-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i32 +// TCHECK-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 8 +// TCHECK-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// TCHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// TCHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8 +// TCHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 3 +// TCHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8 +// TCHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 4 +// TCHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// TCHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 5 +// TCHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8 +// TCHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 6 +// TCHECK-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8 +// TCHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 7 +// TCHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// TCHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 8 +// TCHECK-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 +// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B]], ptr align 4 [[TMP4]], i64 40, i1 false) +// TCHECK-NEXT: [[TMP19:%.*]] = call ptr @llvm.stacksave.p0() +// TCHECK-NEXT: store ptr [[TMP19]], ptr [[SAVED_STACK]], align 8 +// TCHECK-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP6]], align 4 +// TCHECK-NEXT: store i64 [[TMP6]], ptr [[__VLA_EXPR0]], align 8 +// TCHECK-NEXT: [[TMP20:%.*]] = mul nuw i64 [[TMP6]], 4 +// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VLA]], ptr align 4 [[TMP8]], i64 [[TMP20]], i1 false) +// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C]], ptr align 8 [[TMP10]], i64 400, i1 false) +// TCHECK-NEXT: [[TMP21:%.*]] = mul nuw i64 [[TMP12]], [[TMP14]] +// TCHECK-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP21]], align 8 +// TCHECK-NEXT: store i64 [[TMP12]], ptr [[__VLA_EXPR1]], align 8 +// TCHECK-NEXT: store i64 [[TMP14]], ptr [[__VLA_EXPR2]], align 8 +// TCHECK-NEXT: [[TMP22:%.*]] = mul nuw i64 [[TMP12]], [[TMP14]] +// TCHECK-NEXT: [[TMP23:%.*]] = mul nuw i64 [[TMP22]], 8 +// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[VLA1]], ptr align 8 [[TMP16]], i64 [[TMP23]], i1 false) +// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[D]], ptr align 8 [[TMP18]], i64 16, i1 false) +// TCHECK-NEXT: [[TMP24:%.*]] = load i16, ptr [[AA]], align 2 +// TCHECK-NEXT: [[CONV:%.*]] = sext i16 [[TMP24]] to i32 // TCHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// TCHECK-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 -// TCHECK-NEXT: store i16 [[CONV10]], ptr [[AA_ADDR]], align 2 -// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B5]], i64 0, i64 2 +// TCHECK-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// TCHECK-NEXT: store i16 [[CONV2]], ptr [[AA]], align 2 +// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 2 // TCHECK-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 -// TCHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[VLA6]], i64 3 -// TCHECK-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX11]], align 4 -// TCHECK-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C7]], i64 0, i64 1 -// TCHECK-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX12]], i64 0, i64 2 -// TCHECK-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX13]], align 8 -// TCHECK-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP5]] -// TCHECK-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i64 [[TMP14]] -// TCHECK-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 3 -// TCHECK-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8 -// TCHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0 +// TCHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 3 +// TCHECK-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX3]], align 4 +// TCHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 1 +// TCHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX4]], i64 0, i64 2 +// TCHECK-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX5]], align 8 +// TCHECK-NEXT: [[TMP25:%.*]] = mul nsw i64 1, [[TMP14]] +// TCHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i64 [[TMP25]] +// TCHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX6]], i64 3 +// TCHECK-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX7]], align 8 +// TCHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 // TCHECK-NEXT: store i64 1, ptr [[X]], align 8 -// TCHECK-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1 +// TCHECK-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 // TCHECK-NEXT: store i8 1, ptr [[Y]], align 8 -// TCHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 -// TCHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]]) +// TCHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// TCHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP26]]) // TCHECK-NEXT: ret void // // // TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111 -// TCHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] { +// TCHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // TCHECK-NEXT: entry: // TCHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // TCHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// TCHECK-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8 -// TCHECK-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 8 -// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[E_ADDR]], align 8 -// TCHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0:%.*]], ptr [[TMP0]], i32 0, i32 0 -// TCHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 4 -// TCHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// TCHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 -// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i64 0 +// TCHECK-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 +// TCHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_2:%.*]], ptr [[TMP3]], i32 0, i32 0 +// TCHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[X]], align 4 +// TCHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double +// TCHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP1]], align 8 +// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP5]], i64 0 // TCHECK-NEXT: store double [[CONV]], ptr [[ARRAYIDX]], align 8 -// TCHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 -// TCHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i64 0 -// TCHECK-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX1]], align 8 -// TCHECK-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00 +// TCHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP1]], align 8 +// TCHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 0 +// TCHECK-NEXT: [[TMP7:%.*]] = load double, ptr [[ARRAYIDX1]], align 8 +// TCHECK-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 // TCHECK-NEXT: store double [[INC]], ptr [[ARRAYIDX1]], align 8 // TCHECK-NEXT: ret void // // // TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142 -// TCHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// TCHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // TCHECK-NEXT: entry: // TCHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// TCHECK-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// TCHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4 +// TCHECK-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-NEXT: [[A:%.*]] = alloca i32, align 4 +// TCHECK-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// TCHECK-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // TCHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// TCHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// TCHECK-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 -// TCHECK-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i64 40, i1 false) -// TCHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// TCHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// TCHECK-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 -// TCHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 -// TCHECK-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 -// TCHECK-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// TCHECK-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i8 -// TCHECK-NEXT: store i8 [[CONV3]], ptr [[AAA_ADDR]], align 1 -// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i64 0, i64 2 -// TCHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 -// TCHECK-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 -// TCHECK-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4 +// TCHECK-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// TCHECK-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// TCHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 4 +// TCHECK-NEXT: store i8 [[TMP4]], ptr [[AAA]], align 1 +// TCHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B]], ptr align 4 [[TMP6]], i64 40, i1 false) +// TCHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 +// TCHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 1 +// TCHECK-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// TCHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[AAA]], align 1 +// TCHECK-NEXT: [[CONV:%.*]] = sext i8 [[TMP8]] to i32 +// TCHECK-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 +// TCHECK-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8 +// TCHECK-NEXT: store i8 [[CONV2]], ptr [[AAA]], align 1 +// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 +// TCHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// TCHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// TCHECK-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 // TCHECK-NEXT: ret void // // // TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167 -// TCHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// TCHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // TCHECK-NEXT: entry: // TCHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// TCHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// TCHECK-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// TCHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-NEXT: [[B:%.*]] = alloca i32, align 4 // TCHECK-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // TCHECK-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // TCHECK-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 // TCHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// TCHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// TCHECK-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 -// TCHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 -// TCHECK-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 -// TCHECK-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// TCHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// TCHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// TCHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// TCHECK-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0() -// TCHECK-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 -// TCHECK-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]] -// TCHECK-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 2 -// TCHECK-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 -// TCHECK-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR1]], align 8 -// TCHECK-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]] -// TCHECK-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2 -// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i64 [[TMP7]], i1 false) -// TCHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// TCHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double +// TCHECK-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// TCHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8 +// TCHECK-NEXT: store i32 [[TMP4]], ptr [[B]], align 4 +// TCHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8 +// TCHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 3 +// TCHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8 +// TCHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 4 +// TCHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// TCHECK-NEXT: [[TMP11:%.*]] = call ptr @llvm.stacksave.p0() +// TCHECK-NEXT: store ptr [[TMP11]], ptr [[SAVED_STACK]], align 8 +// TCHECK-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP6]], [[TMP8]] +// TCHECK-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP12]], align 2 +// TCHECK-NEXT: store i64 [[TMP6]], ptr [[__VLA_EXPR0]], align 8 +// TCHECK-NEXT: store i64 [[TMP8]], ptr [[__VLA_EXPR1]], align 8 +// TCHECK-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP6]], [[TMP8]] +// TCHECK-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 2 +// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 2 [[VLA]], ptr align 2 [[TMP10]], i64 [[TMP14]], i1 false) +// TCHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 4 +// TCHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP15]] to double // TCHECK-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// TCHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP2]], i32 0, i32 0 // TCHECK-NEXT: store double [[ADD]], ptr [[A]], align 8 -// TCHECK-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 -// TCHECK-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 8 -// TCHECK-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 -// TCHECK-NEXT: store double [[INC]], ptr [[A4]], align 8 -// TCHECK-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 -// TCHECK-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i64 [[TMP10]] -// TCHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 -// TCHECK-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2 -// TCHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 -// TCHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]]) +// TCHECK-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP2]], i32 0, i32 0 +// TCHECK-NEXT: [[TMP16:%.*]] = load double, ptr [[A1]], align 8 +// TCHECK-NEXT: [[INC:%.*]] = fadd double [[TMP16]], 1.000000e+00 +// TCHECK-NEXT: store double [[INC]], ptr [[A1]], align 8 +// TCHECK-NEXT: [[CONV2:%.*]] = fptosi double [[INC]] to i16 +// TCHECK-NEXT: [[TMP17:%.*]] = mul nsw i64 1, [[TMP8]] +// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP17]] +// TCHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 +// TCHECK-NEXT: store i16 [[CONV2]], ptr [[ARRAYIDX3]], align 2 +// TCHECK-NEXT: [[TMP18:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// TCHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP18]]) // TCHECK-NEXT: ret void // // // TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128 -// TCHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// TCHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // TCHECK-NEXT: entry: // TCHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// TCHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4 +// TCHECK-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-NEXT: [[A:%.*]] = alloca i32, align 4 +// TCHECK-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // TCHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// TCHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// TCHECK-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i64 40, i1 false) -// TCHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// TCHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// TCHECK-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 -// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i64 0, i64 2 -// TCHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 -// TCHECK-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// TCHECK-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4 +// TCHECK-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// TCHECK-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// TCHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B]], ptr align 4 [[TMP4]], i64 40, i1 false) +// TCHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 +// TCHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 1 +// TCHECK-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 +// TCHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// TCHECK-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP6]], 1 +// TCHECK-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4 // TCHECK-NEXT: ret void // // // TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63 -// TCHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] { +// TCHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // TCHECK1-NEXT: entry: // TCHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// TCHECK1-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK1-NEXT: [[GA_ADDR:%.*]] = alloca i64, align 8 +// TCHECK1-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 +// TCHECK1-NEXT: [[GA:%.*]] = alloca i32, align 4 // TCHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// TCHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// TCHECK1-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 8 -// TCHECK1-NEXT: store i64 [[GA]], ptr [[GA_ADDR]], align 8 +// TCHECK1-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// TCHECK1-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// TCHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 3 +// TCHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8 +// TCHECK1-NEXT: store i32 [[TMP5]], ptr [[GA]], align 4 // TCHECK1-NEXT: ret void // // // TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70 -// TCHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// TCHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // TCHECK1-NEXT: entry: // TCHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// TCHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// TCHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// TCHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// TCHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK1-NEXT: [[B5:%.*]] = alloca [10 x float], align 4 +// TCHECK1-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 +// TCHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4 // TCHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // TCHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// TCHECK1-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8 +// TCHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 // TCHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 // TCHECK1-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 8 -// TCHECK1-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// TCHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 // TCHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// TCHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// TCHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// TCHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 -// TCHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 -// TCHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// TCHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 -// TCHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 -// TCHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 -// TCHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// TCHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 -// TCHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 -// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i64 40, i1 false) -// TCHECK1-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave.p0() -// TCHECK1-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 8 -// TCHECK1-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 4 -// TCHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 -// TCHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP1]], 4 -// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i64 [[TMP9]], i1 false) -// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i64 400, i1 false) -// TCHECK1-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]] -// TCHECK1-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP10]], align 8 -// TCHECK1-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 -// TCHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR2]], align 8 -// TCHECK1-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]] -// TCHECK1-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 8 -// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[VLA8]], ptr align 8 [[TMP6]], i64 [[TMP12]], i1 false) -// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[D9]], ptr align 8 [[TMP7]], i64 16, i1 false) -// TCHECK1-NEXT: [[TMP13:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// TCHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i32 +// TCHECK1-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 8 +// TCHECK1-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// TCHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// TCHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8 +// TCHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 3 +// TCHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8 +// TCHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 4 +// TCHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// TCHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 5 +// TCHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8 +// TCHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 6 +// TCHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8 +// TCHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 7 +// TCHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// TCHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 8 +// TCHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 +// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B]], ptr align 4 [[TMP4]], i64 40, i1 false) +// TCHECK1-NEXT: [[TMP19:%.*]] = call ptr @llvm.stacksave.p0() +// TCHECK1-NEXT: store ptr [[TMP19]], ptr [[SAVED_STACK]], align 8 +// TCHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP6]], align 4 +// TCHECK1-NEXT: store i64 [[TMP6]], ptr [[__VLA_EXPR0]], align 8 +// TCHECK1-NEXT: [[TMP20:%.*]] = mul nuw i64 [[TMP6]], 4 +// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VLA]], ptr align 4 [[TMP8]], i64 [[TMP20]], i1 false) +// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C]], ptr align 8 [[TMP10]], i64 400, i1 false) +// TCHECK1-NEXT: [[TMP21:%.*]] = mul nuw i64 [[TMP12]], [[TMP14]] +// TCHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP21]], align 8 +// TCHECK1-NEXT: store i64 [[TMP12]], ptr [[__VLA_EXPR1]], align 8 +// TCHECK1-NEXT: store i64 [[TMP14]], ptr [[__VLA_EXPR2]], align 8 +// TCHECK1-NEXT: [[TMP22:%.*]] = mul nuw i64 [[TMP12]], [[TMP14]] +// TCHECK1-NEXT: [[TMP23:%.*]] = mul nuw i64 [[TMP22]], 8 +// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[VLA1]], ptr align 8 [[TMP16]], i64 [[TMP23]], i1 false) +// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[D]], ptr align 8 [[TMP18]], i64 16, i1 false) +// TCHECK1-NEXT: [[TMP24:%.*]] = load i16, ptr [[AA]], align 2 +// TCHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP24]] to i32 // TCHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// TCHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 -// TCHECK1-NEXT: store i16 [[CONV10]], ptr [[AA_ADDR]], align 2 -// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B5]], i64 0, i64 2 +// TCHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// TCHECK1-NEXT: store i16 [[CONV2]], ptr [[AA]], align 2 +// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 2 // TCHECK1-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 -// TCHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[VLA6]], i64 3 -// TCHECK1-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX11]], align 4 -// TCHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C7]], i64 0, i64 1 -// TCHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX12]], i64 0, i64 2 -// TCHECK1-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX13]], align 8 -// TCHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP5]] -// TCHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i64 [[TMP14]] -// TCHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 3 -// TCHECK1-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8 -// TCHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0 +// TCHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 3 +// TCHECK1-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX3]], align 4 +// TCHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 1 +// TCHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX4]], i64 0, i64 2 +// TCHECK1-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX5]], align 8 +// TCHECK1-NEXT: [[TMP25:%.*]] = mul nsw i64 1, [[TMP14]] +// TCHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i64 [[TMP25]] +// TCHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX6]], i64 3 +// TCHECK1-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX7]], align 8 +// TCHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 // TCHECK1-NEXT: store i64 1, ptr [[X]], align 8 -// TCHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1 +// TCHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 // TCHECK1-NEXT: store i8 1, ptr [[Y]], align 8 -// TCHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 -// TCHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]]) +// TCHECK1-NEXT: [[TMP26:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// TCHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP26]]) // TCHECK1-NEXT: ret void // // // TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111 -// TCHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] { +// TCHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // TCHECK1-NEXT: entry: // TCHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK1-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK1-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK1-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // TCHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// TCHECK1-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8 -// TCHECK1-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[E_ADDR]], align 8 -// TCHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0:%.*]], ptr [[TMP0]], i32 0, i32 0 -// TCHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 4 -// TCHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// TCHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 -// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i64 0 +// TCHECK1-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 +// TCHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_2:%.*]], ptr [[TMP3]], i32 0, i32 0 +// TCHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[X]], align 4 +// TCHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double +// TCHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP1]], align 8 +// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP5]], i64 0 // TCHECK1-NEXT: store double [[CONV]], ptr [[ARRAYIDX]], align 8 -// TCHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 -// TCHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i64 0 -// TCHECK1-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX1]], align 8 -// TCHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00 +// TCHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP1]], align 8 +// TCHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 0 +// TCHECK1-NEXT: [[TMP7:%.*]] = load double, ptr [[ARRAYIDX1]], align 8 +// TCHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 // TCHECK1-NEXT: store double [[INC]], ptr [[ARRAYIDX1]], align 8 // TCHECK1-NEXT: ret void // // // TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142 -// TCHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// TCHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // TCHECK1-NEXT: entry: // TCHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// TCHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// TCHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK1-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4 +// TCHECK1-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 +// TCHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// TCHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // TCHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// TCHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// TCHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 -// TCHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i64 40, i1 false) -// TCHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// TCHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// TCHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 -// TCHECK1-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 -// TCHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 -// TCHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// TCHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i8 -// TCHECK1-NEXT: store i8 [[CONV3]], ptr [[AAA_ADDR]], align 1 -// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i64 0, i64 2 -// TCHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 -// TCHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 -// TCHECK1-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4 +// TCHECK1-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// TCHECK1-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// TCHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK1-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 4 +// TCHECK1-NEXT: store i8 [[TMP4]], ptr [[AAA]], align 1 +// TCHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B]], ptr align 4 [[TMP6]], i64 40, i1 false) +// TCHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 +// TCHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 1 +// TCHECK1-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// TCHECK1-NEXT: [[TMP8:%.*]] = load i8, ptr [[AAA]], align 1 +// TCHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP8]] to i32 +// TCHECK1-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 +// TCHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8 +// TCHECK1-NEXT: store i8 [[CONV2]], ptr [[AAA]], align 1 +// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 +// TCHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// TCHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// TCHECK1-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 // TCHECK1-NEXT: ret void // // // TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167 -// TCHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// TCHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // TCHECK1-NEXT: entry: // TCHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// TCHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// TCHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// TCHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK1-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 // TCHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // TCHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // TCHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 // TCHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// TCHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// TCHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 -// TCHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 -// TCHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 -// TCHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// TCHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0() -// TCHECK1-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 -// TCHECK1-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]] -// TCHECK1-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 2 -// TCHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 -// TCHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR1]], align 8 -// TCHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]] -// TCHECK1-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2 -// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i64 [[TMP7]], i1 false) -// TCHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// TCHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double +// TCHECK1-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// TCHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8 +// TCHECK1-NEXT: store i32 [[TMP4]], ptr [[B]], align 4 +// TCHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8 +// TCHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 3 +// TCHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8 +// TCHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 4 +// TCHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// TCHECK1-NEXT: [[TMP11:%.*]] = call ptr @llvm.stacksave.p0() +// TCHECK1-NEXT: store ptr [[TMP11]], ptr [[SAVED_STACK]], align 8 +// TCHECK1-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP6]], [[TMP8]] +// TCHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP12]], align 2 +// TCHECK1-NEXT: store i64 [[TMP6]], ptr [[__VLA_EXPR0]], align 8 +// TCHECK1-NEXT: store i64 [[TMP8]], ptr [[__VLA_EXPR1]], align 8 +// TCHECK1-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP6]], [[TMP8]] +// TCHECK1-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 2 +// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 2 [[VLA]], ptr align 2 [[TMP10]], i64 [[TMP14]], i1 false) +// TCHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 4 +// TCHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP15]] to double // TCHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// TCHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP2]], i32 0, i32 0 // TCHECK1-NEXT: store double [[ADD]], ptr [[A]], align 8 -// TCHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 -// TCHECK1-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 8 -// TCHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 -// TCHECK1-NEXT: store double [[INC]], ptr [[A4]], align 8 -// TCHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 -// TCHECK1-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i64 [[TMP10]] -// TCHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 -// TCHECK1-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2 -// TCHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 -// TCHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]]) +// TCHECK1-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP2]], i32 0, i32 0 +// TCHECK1-NEXT: [[TMP16:%.*]] = load double, ptr [[A1]], align 8 +// TCHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP16]], 1.000000e+00 +// TCHECK1-NEXT: store double [[INC]], ptr [[A1]], align 8 +// TCHECK1-NEXT: [[CONV2:%.*]] = fptosi double [[INC]] to i16 +// TCHECK1-NEXT: [[TMP17:%.*]] = mul nsw i64 1, [[TMP8]] +// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP17]] +// TCHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 +// TCHECK1-NEXT: store i16 [[CONV2]], ptr [[ARRAYIDX3]], align 2 +// TCHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// TCHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP18]]) // TCHECK1-NEXT: ret void // // // TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128 -// TCHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// TCHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // TCHECK1-NEXT: entry: // TCHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// TCHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK1-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4 +// TCHECK1-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 +// TCHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // TCHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// TCHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// TCHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i64 40, i1 false) -// TCHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// TCHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// TCHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 -// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i64 0, i64 2 -// TCHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 -// TCHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// TCHECK1-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4 +// TCHECK1-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// TCHECK1-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// TCHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B]], ptr align 4 [[TMP4]], i64 40, i1 false) +// TCHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 +// TCHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 1 +// TCHECK1-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 +// TCHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// TCHECK1-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP6]], 1 +// TCHECK1-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4 // TCHECK1-NEXT: ret void // // // TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63 -// TCHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] { +// TCHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // TCHECK2-NEXT: entry: // TCHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// TCHECK2-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK2-NEXT: [[GA_ADDR:%.*]] = alloca i32, align 4 +// TCHECK2-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 +// TCHECK2-NEXT: [[GA:%.*]] = alloca i32, align 4 // TCHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// TCHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// TCHECK2-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 4 -// TCHECK2-NEXT: store i32 [[GA]], ptr [[GA_ADDR]], align 4 +// TCHECK2-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// TCHECK2-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// TCHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// TCHECK2-NEXT: store i32 [[TMP5]], ptr [[GA]], align 4 // TCHECK2-NEXT: ret void // // // TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70 -// TCHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// TCHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // TCHECK2-NEXT: entry: // TCHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// TCHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// TCHECK2-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// TCHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// TCHECK2-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK2-NEXT: [[B5:%.*]] = alloca [10 x float], align 4 +// TCHECK2-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2 +// TCHECK2-NEXT: [[B:%.*]] = alloca [10 x float], align 4 // TCHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // TCHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// TCHECK2-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8 +// TCHECK2-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 // TCHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 // TCHECK2-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 4 -// TCHECK2-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// TCHECK2-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 // TCHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// TCHECK2-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// TCHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// TCHECK2-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 -// TCHECK2-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 -// TCHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// TCHECK2-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 -// TCHECK2-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 -// TCHECK2-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 -// TCHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 -// TCHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 -// TCHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 -// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i32 40, i1 false) -// TCHECK2-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave.p0() -// TCHECK2-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 4 -// TCHECK2-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 4 -// TCHECK2-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 -// TCHECK2-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP1]], 4 -// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i32 [[TMP9]], i1 false) -// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i32 400, i1 false) -// TCHECK2-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]] -// TCHECK2-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP10]], align 8 -// TCHECK2-NEXT: store i32 [[TMP4]], ptr [[__VLA_EXPR1]], align 4 -// TCHECK2-NEXT: store i32 [[TMP5]], ptr [[__VLA_EXPR2]], align 4 -// TCHECK2-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]] -// TCHECK2-NEXT: [[TMP12:%.*]] = mul nuw i32 [[TMP11]], 8 -// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[VLA8]], ptr align 8 [[TMP6]], i32 [[TMP12]], i1 false) -// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[D9]], ptr align 4 [[TMP7]], i32 12, i1 false) -// TCHECK2-NEXT: [[TMP13:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// TCHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i32 +// TCHECK2-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK2-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4 +// TCHECK2-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// TCHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4 +// TCHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// TCHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 3 +// TCHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4 +// TCHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 4 +// TCHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4 +// TCHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 5 +// TCHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 +// TCHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 6 +// TCHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 +// TCHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 7 +// TCHECK2-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 4 +// TCHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 8 +// TCHECK2-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 4 +// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B]], ptr align 4 [[TMP4]], i32 40, i1 false) +// TCHECK2-NEXT: [[TMP19:%.*]] = call ptr @llvm.stacksave.p0() +// TCHECK2-NEXT: store ptr [[TMP19]], ptr [[SAVED_STACK]], align 4 +// TCHECK2-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP6]], align 4 +// TCHECK2-NEXT: store i32 [[TMP6]], ptr [[__VLA_EXPR0]], align 4 +// TCHECK2-NEXT: [[TMP20:%.*]] = mul nuw i32 [[TMP6]], 4 +// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VLA]], ptr align 4 [[TMP8]], i32 [[TMP20]], i1 false) +// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[C]], ptr align 8 [[TMP10]], i32 400, i1 false) +// TCHECK2-NEXT: [[TMP21:%.*]] = mul nuw i32 [[TMP12]], [[TMP14]] +// TCHECK2-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP21]], align 8 +// TCHECK2-NEXT: store i32 [[TMP12]], ptr [[__VLA_EXPR1]], align 4 +// TCHECK2-NEXT: store i32 [[TMP14]], ptr [[__VLA_EXPR2]], align 4 +// TCHECK2-NEXT: [[TMP22:%.*]] = mul nuw i32 [[TMP12]], [[TMP14]] +// TCHECK2-NEXT: [[TMP23:%.*]] = mul nuw i32 [[TMP22]], 8 +// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[VLA1]], ptr align 8 [[TMP16]], i32 [[TMP23]], i1 false) +// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[D]], ptr align 4 [[TMP18]], i32 12, i1 false) +// TCHECK2-NEXT: [[TMP24:%.*]] = load i16, ptr [[AA]], align 2 +// TCHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP24]] to i32 // TCHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// TCHECK2-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 -// TCHECK2-NEXT: store i16 [[CONV10]], ptr [[AA_ADDR]], align 2 -// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B5]], i32 0, i32 2 +// TCHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// TCHECK2-NEXT: store i16 [[CONV2]], ptr [[AA]], align 2 +// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 2 // TCHECK2-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 -// TCHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[VLA6]], i32 3 -// TCHECK2-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX11]], align 4 -// TCHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C7]], i32 0, i32 1 -// TCHECK2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX12]], i32 0, i32 2 -// TCHECK2-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX13]], align 8 -// TCHECK2-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP5]] -// TCHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i32 [[TMP14]] -// TCHECK2-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 3 -// TCHECK2-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8 -// TCHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0 +// TCHECK2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[VLA]], i32 3 +// TCHECK2-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX3]], align 4 +// TCHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 1 +// TCHECK2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX4]], i32 0, i32 2 +// TCHECK2-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX5]], align 8 +// TCHECK2-NEXT: [[TMP25:%.*]] = mul nsw i32 1, [[TMP14]] +// TCHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i32 [[TMP25]] +// TCHECK2-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX6]], i32 3 +// TCHECK2-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX7]], align 8 +// TCHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 // TCHECK2-NEXT: store i64 1, ptr [[X]], align 4 -// TCHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1 +// TCHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 // TCHECK2-NEXT: store i8 1, ptr [[Y]], align 4 -// TCHECK2-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 -// TCHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]]) +// TCHECK2-NEXT: [[TMP26:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// TCHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP26]]) // TCHECK2-NEXT: ret void // // // TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111 -// TCHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] { +// TCHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // TCHECK2-NEXT: entry: // TCHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK2-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK2-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK2-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // TCHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// TCHECK2-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4 -// TCHECK2-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[E_ADDR]], align 4 -// TCHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0:%.*]], ptr [[TMP0]], i32 0, i32 0 -// TCHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 4 -// TCHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// TCHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 -// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i32 0 +// TCHECK2-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4 +// TCHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_2:%.*]], ptr [[TMP3]], i32 0, i32 0 +// TCHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[X]], align 4 +// TCHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double +// TCHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP1]], align 4 +// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP5]], i32 0 // TCHECK2-NEXT: store double [[CONV]], ptr [[ARRAYIDX]], align 4 -// TCHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 -// TCHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i32 0 -// TCHECK2-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX1]], align 4 -// TCHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00 +// TCHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP1]], align 4 +// TCHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 0 +// TCHECK2-NEXT: [[TMP7:%.*]] = load double, ptr [[ARRAYIDX1]], align 4 +// TCHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 // TCHECK2-NEXT: store double [[INC]], ptr [[ARRAYIDX1]], align 4 // TCHECK2-NEXT: ret void // // // TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142 -// TCHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// TCHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // TCHECK2-NEXT: entry: // TCHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// TCHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// TCHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK2-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4 +// TCHECK2-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 +// TCHECK2-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// TCHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // TCHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// TCHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// TCHECK2-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 -// TCHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i32 40, i1 false) -// TCHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// TCHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// TCHECK2-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 -// TCHECK2-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 -// TCHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// TCHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i8 -// TCHECK2-NEXT: store i8 [[CONV3]], ptr [[AAA_ADDR]], align 1 -// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i32 0, i32 2 -// TCHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 -// TCHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 -// TCHECK2-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4 +// TCHECK2-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// TCHECK2-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// TCHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK2-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 4 +// TCHECK2-NEXT: store i8 [[TMP4]], ptr [[AAA]], align 1 +// TCHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4 +// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B]], ptr align 4 [[TMP6]], i32 40, i1 false) +// TCHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 +// TCHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 1 +// TCHECK2-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// TCHECK2-NEXT: [[TMP8:%.*]] = load i8, ptr [[AAA]], align 1 +// TCHECK2-NEXT: [[CONV:%.*]] = sext i8 [[TMP8]] to i32 +// TCHECK2-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 +// TCHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8 +// TCHECK2-NEXT: store i8 [[CONV2]], ptr [[AAA]], align 1 +// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 +// TCHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// TCHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// TCHECK2-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 // TCHECK2-NEXT: ret void // // // TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167 -// TCHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// TCHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // TCHECK2-NEXT: entry: // TCHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK2-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// TCHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// TCHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// TCHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK2-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK2-NEXT: [[B:%.*]] = alloca i32, align 4 // TCHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // TCHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 // TCHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 // TCHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// TCHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 -// TCHECK2-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 -// TCHECK2-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 -// TCHECK2-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 -// TCHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 -// TCHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0() -// TCHECK2-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 4 -// TCHECK2-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] -// TCHECK2-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 2 -// TCHECK2-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 -// TCHECK2-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 -// TCHECK2-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] -// TCHECK2-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2 -// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i32 [[TMP7]], i1 false) -// TCHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// TCHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double +// TCHECK2-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// TCHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// TCHECK2-NEXT: store i32 [[TMP4]], ptr [[B]], align 4 +// TCHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// TCHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 3 +// TCHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 +// TCHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 4 +// TCHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4 +// TCHECK2-NEXT: [[TMP11:%.*]] = call ptr @llvm.stacksave.p0() +// TCHECK2-NEXT: store ptr [[TMP11]], ptr [[SAVED_STACK]], align 4 +// TCHECK2-NEXT: [[TMP12:%.*]] = mul nuw i32 [[TMP6]], [[TMP8]] +// TCHECK2-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP12]], align 2 +// TCHECK2-NEXT: store i32 [[TMP6]], ptr [[__VLA_EXPR0]], align 4 +// TCHECK2-NEXT: store i32 [[TMP8]], ptr [[__VLA_EXPR1]], align 4 +// TCHECK2-NEXT: [[TMP13:%.*]] = mul nuw i32 [[TMP6]], [[TMP8]] +// TCHECK2-NEXT: [[TMP14:%.*]] = mul nuw i32 [[TMP13]], 2 +// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[VLA]], ptr align 2 [[TMP10]], i32 [[TMP14]], i1 false) +// TCHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 4 +// TCHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP15]] to double // TCHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// TCHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP2]], i32 0, i32 0 // TCHECK2-NEXT: store double [[ADD]], ptr [[A]], align 4 -// TCHECK2-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 -// TCHECK2-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 4 -// TCHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 -// TCHECK2-NEXT: store double [[INC]], ptr [[A4]], align 4 -// TCHECK2-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 -// TCHECK2-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP2]] -// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i32 [[TMP10]] -// TCHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 -// TCHECK2-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2 -// TCHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 -// TCHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]]) +// TCHECK2-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP2]], i32 0, i32 0 +// TCHECK2-NEXT: [[TMP16:%.*]] = load double, ptr [[A1]], align 4 +// TCHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP16]], 1.000000e+00 +// TCHECK2-NEXT: store double [[INC]], ptr [[A1]], align 4 +// TCHECK2-NEXT: [[CONV2:%.*]] = fptosi double [[INC]] to i16 +// TCHECK2-NEXT: [[TMP17:%.*]] = mul nsw i32 1, [[TMP8]] +// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP17]] +// TCHECK2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 +// TCHECK2-NEXT: store i16 [[CONV2]], ptr [[ARRAYIDX3]], align 2 +// TCHECK2-NEXT: [[TMP18:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// TCHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP18]]) // TCHECK2-NEXT: ret void // // // TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128 -// TCHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// TCHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // TCHECK2-NEXT: entry: // TCHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// TCHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK2-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4 +// TCHECK2-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 +// TCHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // TCHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// TCHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// TCHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i32 40, i1 false) -// TCHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// TCHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// TCHECK2-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 -// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i32 0, i32 2 -// TCHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 -// TCHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// TCHECK2-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4 +// TCHECK2-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// TCHECK2-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// TCHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4 +// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B]], ptr align 4 [[TMP4]], i32 40, i1 false) +// TCHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 +// TCHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 1 +// TCHECK2-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 +// TCHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// TCHECK2-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP6]], 1 +// TCHECK2-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4 // TCHECK2-NEXT: ret void // // // TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63 -// TCHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] { +// TCHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // TCHECK3-NEXT: entry: // TCHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// TCHECK3-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK3-NEXT: [[GA_ADDR:%.*]] = alloca i32, align 4 +// TCHECK3-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 +// TCHECK3-NEXT: [[GA:%.*]] = alloca i32, align 4 // TCHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// TCHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// TCHECK3-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 4 -// TCHECK3-NEXT: store i32 [[GA]], ptr [[GA_ADDR]], align 4 +// TCHECK3-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// TCHECK3-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// TCHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// TCHECK3-NEXT: store i32 [[TMP5]], ptr [[GA]], align 4 // TCHECK3-NEXT: ret void // // // TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70 -// TCHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// TCHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // TCHECK3-NEXT: entry: // TCHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// TCHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// TCHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// TCHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// TCHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK3-NEXT: [[B5:%.*]] = alloca [10 x float], align 4 +// TCHECK3-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 +// TCHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4 // TCHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // TCHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// TCHECK3-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8 +// TCHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 // TCHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 // TCHECK3-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 4 -// TCHECK3-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// TCHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 // TCHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// TCHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// TCHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// TCHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 -// TCHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 -// TCHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// TCHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 -// TCHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 -// TCHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 -// TCHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 -// TCHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 -// TCHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 -// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i32 40, i1 false) -// TCHECK3-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave.p0() -// TCHECK3-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 4 -// TCHECK3-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 4 -// TCHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 -// TCHECK3-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP1]], 4 -// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i32 [[TMP9]], i1 false) -// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i32 400, i1 false) -// TCHECK3-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]] -// TCHECK3-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP10]], align 8 -// TCHECK3-NEXT: store i32 [[TMP4]], ptr [[__VLA_EXPR1]], align 4 -// TCHECK3-NEXT: store i32 [[TMP5]], ptr [[__VLA_EXPR2]], align 4 -// TCHECK3-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]] -// TCHECK3-NEXT: [[TMP12:%.*]] = mul nuw i32 [[TMP11]], 8 -// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[VLA8]], ptr align 8 [[TMP6]], i32 [[TMP12]], i1 false) -// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[D9]], ptr align 4 [[TMP7]], i32 12, i1 false) -// TCHECK3-NEXT: [[TMP13:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// TCHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i32 +// TCHECK3-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4 +// TCHECK3-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// TCHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4 +// TCHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// TCHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 3 +// TCHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4 +// TCHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 4 +// TCHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4 +// TCHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 5 +// TCHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 +// TCHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 6 +// TCHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 +// TCHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 7 +// TCHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 4 +// TCHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 8 +// TCHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 4 +// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B]], ptr align 4 [[TMP4]], i32 40, i1 false) +// TCHECK3-NEXT: [[TMP19:%.*]] = call ptr @llvm.stacksave.p0() +// TCHECK3-NEXT: store ptr [[TMP19]], ptr [[SAVED_STACK]], align 4 +// TCHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP6]], align 4 +// TCHECK3-NEXT: store i32 [[TMP6]], ptr [[__VLA_EXPR0]], align 4 +// TCHECK3-NEXT: [[TMP20:%.*]] = mul nuw i32 [[TMP6]], 4 +// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VLA]], ptr align 4 [[TMP8]], i32 [[TMP20]], i1 false) +// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[C]], ptr align 8 [[TMP10]], i32 400, i1 false) +// TCHECK3-NEXT: [[TMP21:%.*]] = mul nuw i32 [[TMP12]], [[TMP14]] +// TCHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP21]], align 8 +// TCHECK3-NEXT: store i32 [[TMP12]], ptr [[__VLA_EXPR1]], align 4 +// TCHECK3-NEXT: store i32 [[TMP14]], ptr [[__VLA_EXPR2]], align 4 +// TCHECK3-NEXT: [[TMP22:%.*]] = mul nuw i32 [[TMP12]], [[TMP14]] +// TCHECK3-NEXT: [[TMP23:%.*]] = mul nuw i32 [[TMP22]], 8 +// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[VLA1]], ptr align 8 [[TMP16]], i32 [[TMP23]], i1 false) +// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[D]], ptr align 4 [[TMP18]], i32 12, i1 false) +// TCHECK3-NEXT: [[TMP24:%.*]] = load i16, ptr [[AA]], align 2 +// TCHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP24]] to i32 // TCHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// TCHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 -// TCHECK3-NEXT: store i16 [[CONV10]], ptr [[AA_ADDR]], align 2 -// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B5]], i32 0, i32 2 +// TCHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 +// TCHECK3-NEXT: store i16 [[CONV2]], ptr [[AA]], align 2 +// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 2 // TCHECK3-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 -// TCHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[VLA6]], i32 3 -// TCHECK3-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX11]], align 4 -// TCHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C7]], i32 0, i32 1 -// TCHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX12]], i32 0, i32 2 -// TCHECK3-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX13]], align 8 -// TCHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP5]] -// TCHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i32 [[TMP14]] -// TCHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 3 -// TCHECK3-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8 -// TCHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0 +// TCHECK3-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[VLA]], i32 3 +// TCHECK3-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX3]], align 4 +// TCHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 1 +// TCHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX4]], i32 0, i32 2 +// TCHECK3-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX5]], align 8 +// TCHECK3-NEXT: [[TMP25:%.*]] = mul nsw i32 1, [[TMP14]] +// TCHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i32 [[TMP25]] +// TCHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX6]], i32 3 +// TCHECK3-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX7]], align 8 +// TCHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 // TCHECK3-NEXT: store i64 1, ptr [[X]], align 4 -// TCHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1 +// TCHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 // TCHECK3-NEXT: store i8 1, ptr [[Y]], align 4 -// TCHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 -// TCHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]]) +// TCHECK3-NEXT: [[TMP26:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// TCHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP26]]) // TCHECK3-NEXT: ret void // // // TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111 -// TCHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] { +// TCHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // TCHECK3-NEXT: entry: // TCHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK3-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK3-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK3-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // TCHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// TCHECK3-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4 -// TCHECK3-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[E_ADDR]], align 4 -// TCHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0:%.*]], ptr [[TMP0]], i32 0, i32 0 -// TCHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 4 -// TCHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// TCHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 -// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i32 0 +// TCHECK3-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4 +// TCHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_2:%.*]], ptr [[TMP3]], i32 0, i32 0 +// TCHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[X]], align 4 +// TCHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double +// TCHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP1]], align 4 +// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP5]], i32 0 // TCHECK3-NEXT: store double [[CONV]], ptr [[ARRAYIDX]], align 4 -// TCHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 -// TCHECK3-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i32 0 -// TCHECK3-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX1]], align 4 -// TCHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00 +// TCHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP1]], align 4 +// TCHECK3-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 0 +// TCHECK3-NEXT: [[TMP7:%.*]] = load double, ptr [[ARRAYIDX1]], align 4 +// TCHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 // TCHECK3-NEXT: store double [[INC]], ptr [[ARRAYIDX1]], align 4 // TCHECK3-NEXT: ret void // // // TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142 -// TCHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// TCHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // TCHECK3-NEXT: entry: // TCHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// TCHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// TCHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK3-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4 +// TCHECK3-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 +// TCHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// TCHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // TCHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// TCHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// TCHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 -// TCHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i32 40, i1 false) -// TCHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// TCHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// TCHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 -// TCHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 -// TCHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// TCHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i8 -// TCHECK3-NEXT: store i8 [[CONV3]], ptr [[AAA_ADDR]], align 1 -// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i32 0, i32 2 -// TCHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 -// TCHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 -// TCHECK3-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4 +// TCHECK3-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// TCHECK3-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// TCHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK3-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 4 +// TCHECK3-NEXT: store i8 [[TMP4]], ptr [[AAA]], align 1 +// TCHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4 +// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B]], ptr align 4 [[TMP6]], i32 40, i1 false) +// TCHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 +// TCHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 1 +// TCHECK3-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// TCHECK3-NEXT: [[TMP8:%.*]] = load i8, ptr [[AAA]], align 1 +// TCHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP8]] to i32 +// TCHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 +// TCHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8 +// TCHECK3-NEXT: store i8 [[CONV2]], ptr [[AAA]], align 1 +// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 +// TCHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// TCHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 +// TCHECK3-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 // TCHECK3-NEXT: ret void // // // TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167 -// TCHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// TCHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // TCHECK3-NEXT: entry: // TCHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// TCHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// TCHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// TCHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK3-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 // TCHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // TCHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 // TCHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 // TCHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// TCHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 -// TCHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 -// TCHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 -// TCHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 -// TCHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 -// TCHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0() -// TCHECK3-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 4 -// TCHECK3-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] -// TCHECK3-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 2 -// TCHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 -// TCHECK3-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 -// TCHECK3-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] -// TCHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2 -// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i32 [[TMP7]], i1 false) -// TCHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// TCHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double +// TCHECK3-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// TCHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// TCHECK3-NEXT: store i32 [[TMP4]], ptr [[B]], align 4 +// TCHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// TCHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 3 +// TCHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 +// TCHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 4 +// TCHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4 +// TCHECK3-NEXT: [[TMP11:%.*]] = call ptr @llvm.stacksave.p0() +// TCHECK3-NEXT: store ptr [[TMP11]], ptr [[SAVED_STACK]], align 4 +// TCHECK3-NEXT: [[TMP12:%.*]] = mul nuw i32 [[TMP6]], [[TMP8]] +// TCHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP12]], align 2 +// TCHECK3-NEXT: store i32 [[TMP6]], ptr [[__VLA_EXPR0]], align 4 +// TCHECK3-NEXT: store i32 [[TMP8]], ptr [[__VLA_EXPR1]], align 4 +// TCHECK3-NEXT: [[TMP13:%.*]] = mul nuw i32 [[TMP6]], [[TMP8]] +// TCHECK3-NEXT: [[TMP14:%.*]] = mul nuw i32 [[TMP13]], 2 +// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[VLA]], ptr align 2 [[TMP10]], i32 [[TMP14]], i1 false) +// TCHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 4 +// TCHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP15]] to double // TCHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// TCHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP2]], i32 0, i32 0 // TCHECK3-NEXT: store double [[ADD]], ptr [[A]], align 4 -// TCHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 -// TCHECK3-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 4 -// TCHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 -// TCHECK3-NEXT: store double [[INC]], ptr [[A4]], align 4 -// TCHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 -// TCHECK3-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP2]] -// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i32 [[TMP10]] -// TCHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 -// TCHECK3-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2 -// TCHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 -// TCHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]]) +// TCHECK3-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP2]], i32 0, i32 0 +// TCHECK3-NEXT: [[TMP16:%.*]] = load double, ptr [[A1]], align 4 +// TCHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP16]], 1.000000e+00 +// TCHECK3-NEXT: store double [[INC]], ptr [[A1]], align 4 +// TCHECK3-NEXT: [[CONV2:%.*]] = fptosi double [[INC]] to i16 +// TCHECK3-NEXT: [[TMP17:%.*]] = mul nsw i32 1, [[TMP8]] +// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP17]] +// TCHECK3-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 +// TCHECK3-NEXT: store i16 [[CONV2]], ptr [[ARRAYIDX3]], align 2 +// TCHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// TCHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP18]]) // TCHECK3-NEXT: ret void // // // TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128 -// TCHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// TCHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // TCHECK3-NEXT: entry: // TCHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// TCHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK3-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4 +// TCHECK3-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 +// TCHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // TCHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// TCHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// TCHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i32 40, i1 false) -// TCHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// TCHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// TCHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 -// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i32 0, i32 2 -// TCHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 -// TCHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// TCHECK3-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4 +// TCHECK3-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// TCHECK3-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// TCHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4 +// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B]], ptr align 4 [[TMP4]], i32 40, i1 false) +// TCHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 +// TCHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 1 +// TCHECK3-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 +// TCHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// TCHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP6]], 1 +// TCHECK3-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4 // TCHECK3-NEXT: ret void // // diff --git a/clang/test/OpenMP/target_ompx_dyn_cgroup_mem_codegen.cpp b/clang/test/OpenMP/target_ompx_dyn_cgroup_mem_codegen.cpp index 10c4ac38e6a89..3f96b670b77e0 100644 --- a/clang/test/OpenMP/target_ompx_dyn_cgroup_mem_codegen.cpp +++ b/clang/test/OpenMP/target_ompx_dyn_cgroup_mem_codegen.cpp @@ -1936,24 +1936,33 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[N_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined, i64 [[TMP3]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], ptr [[N]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK9-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP8]], i32 0) +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[N]], align 4 +// CHECK9-NEXT: store i32 [[TMP9]], ptr [[N_CASTED]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined, i64 [[TMP10]]) // CHECK9-NEXT: ret void // // @@ -2164,12 +2173,17 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined) // CHECK9-NEXT: ret void // @@ -2185,22 +2199,28 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP1]], ptr [[B_CASTED]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[B_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP0]], i64 [[TMP2]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8 +// CHECK9-NEXT: store i32 [[TMP4]], ptr [[B]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[B]], align 4 +// CHECK9-NEXT: store i32 [[TMP7]], ptr [[B_CASTED]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[B_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP2]], i64 [[TMP8]]) // CHECK9-NEXT: ret void // // @@ -2225,23 +2245,28 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: store double 2.500000e+00, ptr [[A]], align 8 // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.omp_outlined) // CHECK9-NEXT: ret void // @@ -2257,29 +2282,38 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR__ADDR]], align 2 -// CHECK9-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 0) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[B_ADDR]], align 2 -// CHECK9-NEXT: store i16 [[TMP5]], ptr [[B_CASTED]], align 2 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP4]], i64 [[TMP6]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 4 +// CHECK9-NEXT: store i16 [[TMP5]], ptr [[B]], align 2 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP1]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 2 +// CHECK9-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2 +// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2 +// CHECK9-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP9]], i32 0) +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2 +// CHECK9-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2 +// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[B_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP11]], i64 [[TMP13]]) // CHECK9-NEXT: ret void // // @@ -2303,24 +2337,33 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined, i32 [[TMP3]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], ptr [[N]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP8]], i32 0) +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[N]], align 4 +// CHECK11-NEXT: store i32 [[TMP9]], ptr [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[N_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined, i32 [[TMP10]]) // CHECK11-NEXT: ret void // // @@ -2527,12 +2570,17 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined) // CHECK11-NEXT: ret void // @@ -2548,22 +2596,28 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], ptr [[B_CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[B_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP0]], i32 [[TMP2]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], ptr [[B]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK11-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[B]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], ptr [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP2]], i32 [[TMP8]]) // CHECK11-NEXT: ret void // // @@ -2588,23 +2642,28 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: store double 2.500000e+00, ptr [[A]], align 4 // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.omp_outlined) // CHECK11-NEXT: ret void // @@ -2620,29 +2679,38 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR__ADDR]], align 2 -// CHECK11-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 0) -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[B_ADDR]], align 2 -// CHECK11-NEXT: store i16 [[TMP5]], ptr [[B_CASTED]], align 2 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP4]], i32 [[TMP6]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP1]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 4 +// CHECK11-NEXT: store i16 [[TMP5]], ptr [[B]], align 2 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP1]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 2 +// CHECK11-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2 +// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2 +// CHECK11-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP9]], i32 0) +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2 +// CHECK11-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP11]], i32 [[TMP13]]) // CHECK11-NEXT: ret void // // diff --git a/clang/test/OpenMP/target_parallel_codegen.cpp b/clang/test/OpenMP/target_parallel_codegen.cpp index ad5a9d53bcf65..63535309c6c99 100644 --- a/clang/test/OpenMP/target_parallel_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_codegen.cpp @@ -2484,10 +2484,13 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined) // CHECK9-NEXT: ret void // @@ -2503,17 +2506,22 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK9-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i64 [[TMP1]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 2 +// CHECK9-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 +// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i64 [[TMP4]]) // CHECK9-NEXT: ret void // // @@ -2544,23 +2552,30 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK9-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined, i64 [[TMP6]], i64 [[TMP8]]) // CHECK9-NEXT: ret void // // @@ -2587,41 +2602,38 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 -// CHECK9-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 5 +// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 6 +// CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 7 +// CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 8 +// CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP19]], ptr [[A_CASTED]], align 4 +// CHECK9-NEXT: [[TMP20:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined, i64 [[TMP20]], ptr [[TMP4]], i64 [[TMP6]], ptr [[TMP8]], ptr [[TMP10]], i64 [[TMP12]], i64 [[TMP14]], ptr [[TMP16]], ptr [[TMP18]]) // CHECK9-NEXT: ret void // // @@ -2698,32 +2710,40 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[AAA:%.*]] = alloca i8, align 1 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 -// CHECK9-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 2 +// CHECK9-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP9]], ptr [[A_CASTED]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP11]], ptr [[AA_CASTED]], align 2 +// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = load i8, ptr [[AAA]], align 1 +// CHECK9-NEXT: store i8 [[TMP13]], ptr [[AAA_CASTED]], align 1 +// CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined, i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP14]], ptr [[TMP8]]) // CHECK9-NEXT: ret void // // @@ -2764,29 +2784,30 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8 +// CHECK9-NEXT: store i32 [[TMP4]], ptr [[B]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[B]], align 4 +// CHECK9-NEXT: store i32 [[TMP11]], ptr [[B_CASTED]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[B_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP2]], i64 [[TMP12]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP10]]) // CHECK9-NEXT: ret void // // @@ -2829,26 +2850,32 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP7]], ptr [[A_CASTED]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP9]], ptr [[AA_CASTED]], align 2 +// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined, i64 [[TMP8]], i64 [[TMP10]], ptr [[TMP6]]) // CHECK9-NEXT: ret void // // @@ -2882,10 +2909,13 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined) // CHECK11-NEXT: ret void // @@ -2901,17 +2931,22 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK11-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i32 [[TMP1]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 2 +// CHECK11-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i32 [[TMP4]]) // CHECK11-NEXT: ret void // // @@ -2942,23 +2977,30 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK11-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined, i32 [[TMP1]], i32 [[TMP3]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined, i32 [[TMP6]], i32 [[TMP8]]) // CHECK11-NEXT: ret void // // @@ -2985,41 +3027,38 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 -// CHECK11-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 5 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 6 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 7 +// CHECK11-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 8 +// CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP19]], ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined, i32 [[TMP20]], ptr [[TMP4]], i32 [[TMP6]], ptr [[TMP8]], ptr [[TMP10]], i32 [[TMP12]], i32 [[TMP14]], ptr [[TMP16]], ptr [[TMP18]]) // CHECK11-NEXT: ret void // // @@ -3096,32 +3135,40 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[AAA:%.*]] = alloca i8, align 1 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 -// CHECK11-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 2 +// CHECK11-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP9]], ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP11]], ptr [[AA_CASTED]], align 2 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i8, ptr [[AAA]], align 1 +// CHECK11-NEXT: store i8 [[TMP13]], ptr [[AAA_CASTED]], align 1 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined, i32 [[TMP10]], i32 [[TMP12]], i32 [[TMP14]], ptr [[TMP8]]) // CHECK11-NEXT: ret void // // @@ -3162,29 +3209,30 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], ptr [[B]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[B]], align 4 +// CHECK11-NEXT: store i32 [[TMP11]], ptr [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP2]], i32 [[TMP12]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP10]]) // CHECK11-NEXT: ret void // // @@ -3227,26 +3275,32 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP9]], ptr [[AA_CASTED]], align 2 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined, i32 [[TMP8]], i32 [[TMP10]], ptr [[TMP6]]) // CHECK11-NEXT: ret void // // diff --git a/clang/test/OpenMP/target_parallel_for_codegen.cpp b/clang/test/OpenMP/target_parallel_for_codegen.cpp index 73504cf7a8024..64c14108021ff 100644 --- a/clang/test/OpenMP/target_parallel_for_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_for_codegen.cpp @@ -3639,10 +3639,13 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined) // CHECK9-NEXT: ret void // @@ -3725,29 +3728,38 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[LIN:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK9-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4 +// CHECK9-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK9-NEXT: store i32 [[TMP4]], ptr [[LIN]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK9-NEXT: store i32 [[TMP6]], ptr [[A]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[LIN]], align 4 +// CHECK9-NEXT: store i32 [[TMP9]], ptr [[LIN_CASTED]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[LIN_CASTED]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined, i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]) // CHECK9-NEXT: ret void // // @@ -3867,23 +3879,30 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK9-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i64 [[TMP6]], i64 [[TMP8]]) // CHECK9-NEXT: ret void // // @@ -3961,47 +3980,46 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 -// CHECK9-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 5 +// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 6 +// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 7 +// CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 8 +// CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 9 +// CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 10 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 8 +// CHECK9-NEXT: store i32 [[TMP20]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, ptr [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP21]], ptr [[A_CASTED]], align 4 +// CHECK9-NEXT: [[TMP22:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: store i32 [[TMP23]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK9-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i64 [[TMP22]], ptr [[TMP4]], i64 [[TMP6]], ptr [[TMP8]], ptr [[TMP10]], i64 [[TMP12]], i64 [[TMP14]], ptr [[TMP16]], ptr [[TMP18]], i64 [[TMP24]]) // CHECK9-NEXT: ret void // // @@ -4149,32 +4167,40 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[AAA:%.*]] = alloca i8, align 1 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 -// CHECK9-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 2 +// CHECK9-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP9]], ptr [[A_CASTED]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP11]], ptr [[AA_CASTED]], align 2 +// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = load i8, ptr [[AAA]], align 1 +// CHECK9-NEXT: store i8 [[TMP13]], ptr [[AAA_CASTED]], align 1 +// CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined, i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP14]], ptr [[TMP8]]) // CHECK9-NEXT: ret void // // @@ -4200,29 +4226,30 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8 +// CHECK9-NEXT: store i32 [[TMP4]], ptr [[B]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[B]], align 4 +// CHECK9-NEXT: store i32 [[TMP11]], ptr [[B_CASTED]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[B_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined, ptr [[TMP2]], i64 [[TMP12]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP10]]) // CHECK9-NEXT: ret void // // @@ -4315,26 +4342,32 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_6:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], ptr [[TMP0]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], ptr [[TMP0]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP7]], ptr [[A_CASTED]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP9]], ptr [[AA_CASTED]], align 2 +// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined, i64 [[TMP8]], i64 [[TMP10]], ptr [[TMP6]]) // CHECK9-NEXT: ret void // // @@ -4418,10 +4451,13 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined) // CHECK11-NEXT: ret void // @@ -4504,29 +4540,38 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[LIN:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK11-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4 +// CHECK11-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], ptr [[LIN]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK11-NEXT: store i32 [[TMP6]], ptr [[A]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[LIN]], align 4 +// CHECK11-NEXT: store i32 [[TMP9]], ptr [[LIN_CASTED]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[LIN_CASTED]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined, i32 [[TMP8]], i32 [[TMP10]], i32 [[TMP12]]) // CHECK11-NEXT: ret void // // @@ -4646,23 +4691,30 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK11-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i32 [[TMP1]], i32 [[TMP3]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i32 [[TMP6]], i32 [[TMP8]]) // CHECK11-NEXT: ret void // // @@ -4740,47 +4792,46 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 -// CHECK11-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 5 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 6 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 7 +// CHECK11-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 8 +// CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 9 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 +// CHECK11-NEXT: store i32 [[TMP20]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP21]], ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: store i32 [[TMP23]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i32 [[TMP22]], ptr [[TMP4]], i32 [[TMP6]], ptr [[TMP8]], ptr [[TMP10]], i32 [[TMP12]], i32 [[TMP14]], ptr [[TMP16]], ptr [[TMP18]], i32 [[TMP24]]) // CHECK11-NEXT: ret void // // @@ -4928,32 +4979,40 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[AAA:%.*]] = alloca i8, align 1 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 -// CHECK11-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 2 +// CHECK11-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP9]], ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP11]], ptr [[AA_CASTED]], align 2 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i8, ptr [[AAA]], align 1 +// CHECK11-NEXT: store i8 [[TMP13]], ptr [[AAA_CASTED]], align 1 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined, i32 [[TMP10]], i32 [[TMP12]], i32 [[TMP14]], ptr [[TMP8]]) // CHECK11-NEXT: ret void // // @@ -4979,29 +5038,30 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], ptr [[B]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[B]], align 4 +// CHECK11-NEXT: store i32 [[TMP11]], ptr [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined, ptr [[TMP2]], i32 [[TMP12]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP10]]) // CHECK11-NEXT: ret void // // @@ -5094,26 +5154,32 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP9]], ptr [[AA_CASTED]], align 2 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined, i32 [[TMP8]], i32 [[TMP10]], ptr [[TMP6]]) // CHECK11-NEXT: ret void // // diff --git a/clang/test/OpenMP/target_parallel_for_simd_codegen.cpp b/clang/test/OpenMP/target_parallel_for_simd_codegen.cpp index 8009e06666c82..307e0d073c815 100644 --- a/clang/test/OpenMP/target_parallel_for_simd_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_for_simd_codegen.cpp @@ -8996,10 +8996,13 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined) // CHECK17-NEXT: ret void // @@ -9072,29 +9075,38 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK17-NEXT: [[LIN:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK17-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 -// CHECK17-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK17-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4 +// CHECK17-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK17-NEXT: store i32 [[TMP4]], ptr [[LIN]], align 4 +// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK17-NEXT: store i32 [[TMP6]], ptr [[A]], align 4 +// CHECK17-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK17-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2 +// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[LIN]], align 4 +// CHECK17-NEXT: store i32 [[TMP9]], ptr [[LIN_CASTED]], align 4 +// CHECK17-NEXT: [[TMP10:%.*]] = load i64, ptr [[LIN_CASTED]], align 8 +// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[A]], align 4 +// CHECK17-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4 +// CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]) // CHECK17-NEXT: ret void // // @@ -9221,23 +9233,30 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK17-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK17-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK17-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK17-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 +// CHECK17-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4 +// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK17-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2 +// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i64 [[TMP6]], i64 [[TMP8]]) // CHECK17-NEXT: ret void // // @@ -9322,47 +9341,46 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 -// CHECK17-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK17-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK17-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK17-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 4 +// CHECK17-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8 +// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 5 +// CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 6 +// CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8 +// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 7 +// CHECK17-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8 +// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 8 +// CHECK17-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 9 +// CHECK17-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 +// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 10 +// CHECK17-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 8 +// CHECK17-NEXT: store i32 [[TMP20]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[TMP21:%.*]] = load i32, ptr [[A]], align 4 +// CHECK17-NEXT: store i32 [[TMP21]], ptr [[A_CASTED]], align 4 +// CHECK17-NEXT: [[TMP22:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: store i32 [[TMP23]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK17-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i64 [[TMP22]], ptr [[TMP4]], i64 [[TMP6]], ptr [[TMP8]], ptr [[TMP10]], i64 [[TMP12]], i64 [[TMP14]], ptr [[TMP16]], ptr [[TMP18]], i64 [[TMP24]]) // CHECK17-NEXT: ret void // // @@ -9517,32 +9535,40 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK17-NEXT: [[AAA:%.*]] = alloca i8, align 1 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK17-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 -// CHECK17-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK17-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK17-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 2 +// CHECK17-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1 +// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8 +// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4 +// CHECK17-NEXT: store i32 [[TMP9]], ptr [[A_CASTED]], align 4 +// CHECK17-NEXT: [[TMP10:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP11:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK17-NEXT: store i16 [[TMP11]], ptr [[AA_CASTED]], align 2 +// CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK17-NEXT: [[TMP13:%.*]] = load i8, ptr [[AAA]], align 1 +// CHECK17-NEXT: store i8 [[TMP13]], ptr [[AAA_CASTED]], align 1 +// CHECK17-NEXT: [[TMP14:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP14]], ptr [[TMP8]]) // CHECK17-NEXT: ret void // // @@ -9568,29 +9594,30 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK17-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8 +// CHECK17-NEXT: store i32 [[TMP4]], ptr [[B]], align 4 +// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8 +// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 4 +// CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[B]], align 4 +// CHECK17-NEXT: store i32 [[TMP11]], ptr [[B_CASTED]], align 4 +// CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[B_CASTED]], align 8 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP2]], i64 [[TMP12]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP10]]) // CHECK17-NEXT: ret void // // @@ -9690,26 +9717,32 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK17-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_6:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK17-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], ptr [[TMP0]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK17-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], ptr [[TMP0]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 +// CHECK17-NEXT: store i32 [[TMP7]], ptr [[A_CASTED]], align 4 +// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK17-NEXT: store i16 [[TMP9]], ptr [[AA_CASTED]], align 2 +// CHECK17-NEXT: [[TMP10:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i64 [[TMP8]], i64 [[TMP10]], ptr [[TMP6]]) // CHECK17-NEXT: ret void // // @@ -9800,10 +9833,13 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 -// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined) // CHECK19-NEXT: ret void // @@ -9876,29 +9912,38 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 -// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK19-NEXT: [[LIN:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK19-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) +// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4 +// CHECK19-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK19-NEXT: store i32 [[TMP4]], ptr [[LIN]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK19-NEXT: store i32 [[TMP6]], ptr [[A]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK19-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[LIN]], align 4 +// CHECK19-NEXT: store i32 [[TMP9]], ptr [[LIN_CASTED]], align 4 +// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[LIN_CASTED]], align 4 +// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i32 [[TMP8]], i32 [[TMP10]], i32 [[TMP12]]) // CHECK19-NEXT: ret void // // @@ -10025,23 +10070,30 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 -// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK19-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i32 [[TMP1]], i32 [[TMP3]]) +// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK19-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK19-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK19-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i32 [[TMP6]], i32 [[TMP8]]) // CHECK19-NEXT: ret void // // @@ -10126,47 +10178,46 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 -// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 -// CHECK19-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]]) +// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK19-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 4 +// CHECK19-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4 +// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 5 +// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 +// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 6 +// CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 +// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 7 +// CHECK19-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 4 +// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 8 +// CHECK19-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 4 +// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 9 +// CHECK19-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 +// CHECK19-NEXT: store i32 [[TMP20]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: [[TMP21:%.*]] = load i32, ptr [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP21]], ptr [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP22:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: store i32 [[TMP23]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i32 [[TMP22]], ptr [[TMP4]], i32 [[TMP6]], ptr [[TMP8]], ptr [[TMP10]], i32 [[TMP12]], i32 [[TMP14]], ptr [[TMP16]], ptr [[TMP18]], i32 [[TMP24]]) // CHECK19-NEXT: ret void // // @@ -10321,32 +10372,40 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 -// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK19-NEXT: [[AAA:%.*]] = alloca i8, align 1 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 -// CHECK19-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]]) +// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK19-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK19-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 2 +// CHECK19-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1 +// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP9]], ptr [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP11:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK19-NEXT: store i16 [[TMP11]], ptr [[AA_CASTED]], align 2 +// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK19-NEXT: [[TMP13:%.*]] = load i8, ptr [[AAA]], align 1 +// CHECK19-NEXT: store i8 [[TMP13]], ptr [[AAA_CASTED]], align 1 +// CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 +// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i32 [[TMP10]], i32 [[TMP12]], i32 [[TMP14]], ptr [[TMP8]]) // CHECK19-NEXT: ret void // // @@ -10372,29 +10431,30 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]]) +// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK19-NEXT: store i32 [[TMP4]], ptr [[B]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 4 +// CHECK19-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4 +// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[B]], align 4 +// CHECK19-NEXT: store i32 [[TMP11]], ptr [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_CASTED]], align 4 +// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP2]], i32 [[TMP12]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP10]]) // CHECK19-NEXT: ret void // // @@ -10494,26 +10554,32 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 -// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]]) +// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK19-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK19-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP7]], ptr [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK19-NEXT: store i16 [[TMP9]], ptr [[AA_CASTED]], align 2 +// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i32 [[TMP8]], i32 [[TMP10]], ptr [[TMP6]]) // CHECK19-NEXT: ret void // // @@ -10604,10 +10670,13 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 -// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK21-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 // CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined) // CHECK21-NEXT: ret void // @@ -10680,29 +10749,38 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 -// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK21-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK21-NEXT: [[LIN:%.*]] = alloca i32, align 4 +// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK21-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 -// CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 8 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 -// CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) +// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK21-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4 +// CHECK21-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK21-NEXT: store i32 [[TMP4]], ptr [[LIN]], align 4 +// CHECK21-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK21-NEXT: store i32 [[TMP6]], ptr [[A]], align 4 +// CHECK21-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK21-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2 +// CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[LIN]], align 4 +// CHECK21-NEXT: store i32 [[TMP9]], ptr [[LIN_CASTED]], align 4 +// CHECK21-NEXT: [[TMP10:%.*]] = load i64, ptr [[LIN_CASTED]], align 8 +// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[A]], align 4 +// CHECK21-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4 +// CHECK21-NEXT: [[TMP12:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]) // CHECK21-NEXT: ret void // // @@ -10829,23 +10907,30 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 -// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK21-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK21-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK21-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 -// CHECK21-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) +// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK21-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK21-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK21-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 +// CHECK21-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4 +// CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK21-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK21-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2 +// CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i64 [[TMP6]], i64 [[TMP8]]) // CHECK21-NEXT: ret void // // @@ -10930,47 +11015,46 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 -// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK21-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 -// CHECK21-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 -// CHECK21-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 -// CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 -// CHECK21-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 -// CHECK21-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 -// CHECK21-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK21-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK21-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]]) +// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK21-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 2 +// CHECK21-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// CHECK21-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 3 +// CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8 +// CHECK21-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 4 +// CHECK21-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8 +// CHECK21-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 5 +// CHECK21-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK21-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 6 +// CHECK21-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8 +// CHECK21-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 7 +// CHECK21-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8 +// CHECK21-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 8 +// CHECK21-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK21-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 9 +// CHECK21-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 +// CHECK21-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 10 +// CHECK21-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 8 +// CHECK21-NEXT: store i32 [[TMP20]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK21-NEXT: [[TMP21:%.*]] = load i32, ptr [[A]], align 4 +// CHECK21-NEXT: store i32 [[TMP21]], ptr [[A_CASTED]], align 4 +// CHECK21-NEXT: [[TMP22:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK21-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK21-NEXT: store i32 [[TMP23]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK21-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i64 [[TMP22]], ptr [[TMP4]], i64 [[TMP6]], ptr [[TMP8]], ptr [[TMP10]], i64 [[TMP12]], i64 [[TMP14]], ptr [[TMP16]], ptr [[TMP18]], i64 [[TMP24]]) // CHECK21-NEXT: ret void // // @@ -11125,32 +11209,40 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 -// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// CHECK21-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK21-NEXT: [[AAA:%.*]] = alloca i8, align 1 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK21-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK21-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK21-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 -// CHECK21-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 -// CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 -// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]]) +// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK21-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 1 +// CHECK21-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK21-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK21-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 2 +// CHECK21-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 2 +// CHECK21-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1 +// CHECK21-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 3 +// CHECK21-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8 +// CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4 +// CHECK21-NEXT: store i32 [[TMP9]], ptr [[A_CASTED]], align 4 +// CHECK21-NEXT: [[TMP10:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK21-NEXT: [[TMP11:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK21-NEXT: store i16 [[TMP11]], ptr [[AA_CASTED]], align 2 +// CHECK21-NEXT: [[TMP12:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK21-NEXT: [[TMP13:%.*]] = load i8, ptr [[AAA]], align 1 +// CHECK21-NEXT: store i8 [[TMP13]], ptr [[AAA_CASTED]], align 1 +// CHECK21-NEXT: [[TMP14:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 +// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP14]], ptr [[TMP8]]) // CHECK21-NEXT: ret void // // @@ -11176,50 +11268,55 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 -// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK21-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK21-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK21-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 -// CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK21-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK21-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// CHECK21-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 -// CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 -// CHECK21-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 -// CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 +// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 +// CHECK21-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP1]], i32 0, i32 1 +// CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8 +// CHECK21-NEXT: store i32 [[TMP5]], ptr [[B]], align 4 +// CHECK21-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP1]], i32 0, i32 3 +// CHECK21-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP6]], align 8 +// CHECK21-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP1]], i32 0, i32 4 +// CHECK21-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8 +// CHECK21-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP1]], i32 0, i32 5 +// CHECK21-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8 +// CHECK21-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP1]], i32 0, i32 6 +// CHECK21-NEXT: [[TMP13:%.*]] = load i8, ptr [[TMP12]], align 8 +// CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP13]] to i1 // CHECK21-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK21-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 -// CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK21-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 -// CHECK21-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP9]] to i1 +// CHECK21-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK21-NEXT: [[TMP14:%.*]] = load i32, ptr [[B]], align 4 +// CHECK21-NEXT: store i32 [[TMP14]], ptr [[B_CASTED]], align 4 +// CHECK21-NEXT: [[TMP15:%.*]] = load i64, ptr [[B_CASTED]], align 8 +// CHECK21-NEXT: [[TMP16:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK21-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP16]] to i1 +// CHECK21-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL1]] to i8 +// CHECK21-NEXT: store i8 [[FROMBOOL2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 +// CHECK21-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK21-NEXT: [[TMP18:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK21-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP18]] to i1 // CHECK21-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK21: omp_if.then: -// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined, ptr [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], ptr [[TMP4]], i64 [[TMP8]]) +// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined, ptr [[TMP3]], i64 [[TMP15]], i64 [[TMP7]], i64 [[TMP9]], ptr [[TMP11]], i64 [[TMP17]]) // CHECK21-NEXT: br label [[OMP_IF_END:%.*]] // CHECK21: omp_if.else: // CHECK21-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) // CHECK21-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4 // CHECK21-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK21-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], ptr [[TMP4]], i64 [[TMP8]]) #[[ATTR1:[0-9]+]] +// CHECK21-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP3]], i64 [[TMP15]], i64 [[TMP7]], i64 [[TMP9]], ptr [[TMP11]], i64 [[TMP17]]) #[[ATTR1:[0-9]+]] // CHECK21-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) // CHECK21-NEXT: br label [[OMP_IF_END]] // CHECK21: omp_if.end: @@ -11384,26 +11481,32 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 -// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// CHECK21-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK21-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK21-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]]) +// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_7:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK21-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], ptr [[TMP0]], i32 0, i32 1 +// CHECK21-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK21-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK21-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], ptr [[TMP0]], i32 0, i32 2 +// CHECK21-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 +// CHECK21-NEXT: store i32 [[TMP7]], ptr [[A_CASTED]], align 4 +// CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK21-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK21-NEXT: store i16 [[TMP9]], ptr [[AA_CASTED]], align 2 +// CHECK21-NEXT: [[TMP10:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i64 [[TMP8]], i64 [[TMP10]], ptr [[TMP6]]) // CHECK21-NEXT: ret void // // @@ -11494,10 +11597,13 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 -// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK23-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 // CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined) // CHECK23-NEXT: ret void // @@ -11570,29 +11676,38 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 -// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK23-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK23-NEXT: [[LIN:%.*]] = alloca i32, align 4 +// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK23-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) +// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK23-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4 +// CHECK23-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK23-NEXT: store i32 [[TMP4]], ptr [[LIN]], align 4 +// CHECK23-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK23-NEXT: store i32 [[TMP6]], ptr [[A]], align 4 +// CHECK23-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK23-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2 +// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[LIN]], align 4 +// CHECK23-NEXT: store i32 [[TMP9]], ptr [[LIN_CASTED]], align 4 +// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[LIN_CASTED]], align 4 +// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[A]], align 4 +// CHECK23-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4 +// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i32 [[TMP8]], i32 [[TMP10]], i32 [[TMP12]]) // CHECK23-NEXT: ret void // // @@ -11719,23 +11834,30 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 -// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK23-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK23-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i32 [[TMP1]], i32 [[TMP3]]) +// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK23-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK23-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK23-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 +// CHECK23-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4 +// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK23-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK23-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2 +// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i32 [[TMP6]], i32 [[TMP8]]) // CHECK23-NEXT: ret void // // @@ -11820,47 +11942,46 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 -// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK23-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 -// CHECK23-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 -// CHECK23-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 -// CHECK23-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 -// CHECK23-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 -// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK23-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]]) +// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK23-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 1 +// CHECK23-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4 +// CHECK23-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 2 +// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK23-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 3 +// CHECK23-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4 +// CHECK23-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 4 +// CHECK23-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4 +// CHECK23-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 5 +// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 +// CHECK23-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 6 +// CHECK23-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 +// CHECK23-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 7 +// CHECK23-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 4 +// CHECK23-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 8 +// CHECK23-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 4 +// CHECK23-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 9 +// CHECK23-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 +// CHECK23-NEXT: store i32 [[TMP20]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK23-NEXT: [[TMP21:%.*]] = load i32, ptr [[A]], align 4 +// CHECK23-NEXT: store i32 [[TMP21]], ptr [[A_CASTED]], align 4 +// CHECK23-NEXT: [[TMP22:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK23-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK23-NEXT: store i32 [[TMP23]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK23-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i32 [[TMP22]], ptr [[TMP4]], i32 [[TMP6]], ptr [[TMP8]], ptr [[TMP10]], i32 [[TMP12]], i32 [[TMP14]], ptr [[TMP16]], ptr [[TMP18]], i32 [[TMP24]]) // CHECK23-NEXT: ret void // // @@ -12015,32 +12136,40 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 -// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 +// CHECK23-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK23-NEXT: [[AAA:%.*]] = alloca i8, align 1 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK23-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK23-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 -// CHECK23-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 -// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]]) +// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK23-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 1 +// CHECK23-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK23-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK23-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 2 +// CHECK23-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 2 +// CHECK23-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1 +// CHECK23-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 3 +// CHECK23-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4 +// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4 +// CHECK23-NEXT: store i32 [[TMP9]], ptr [[A_CASTED]], align 4 +// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK23-NEXT: [[TMP11:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK23-NEXT: store i16 [[TMP11]], ptr [[AA_CASTED]], align 2 +// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK23-NEXT: [[TMP13:%.*]] = load i8, ptr [[AAA]], align 1 +// CHECK23-NEXT: store i8 [[TMP13]], ptr [[AAA_CASTED]], align 1 +// CHECK23-NEXT: [[TMP14:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 +// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i32 [[TMP10]], i32 [[TMP12]], i32 [[TMP14]], ptr [[TMP8]]) // CHECK23-NEXT: ret void // // @@ -12066,50 +12195,55 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 -// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK23-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK23-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK23-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 -// CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 4 -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4 -// CHECK23-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 -// CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 +// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4 +// CHECK23-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP1]], i32 0, i32 1 +// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK23-NEXT: store i32 [[TMP5]], ptr [[B]], align 4 +// CHECK23-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP1]], i32 0, i32 2 +// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK23-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP1]], i32 0, i32 3 +// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 +// CHECK23-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP1]], i32 0, i32 4 +// CHECK23-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 4 +// CHECK23-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP1]], i32 0, i32 5 +// CHECK23-NEXT: [[TMP13:%.*]] = load i8, ptr [[TMP12]], align 4 +// CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP13]] to i1 // CHECK23-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK23-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK23-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 -// CHECK23-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP9]] to i1 +// CHECK23-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK23-NEXT: [[TMP14:%.*]] = load i32, ptr [[B]], align 4 +// CHECK23-NEXT: store i32 [[TMP14]], ptr [[B_CASTED]], align 4 +// CHECK23-NEXT: [[TMP15:%.*]] = load i32, ptr [[B_CASTED]], align 4 +// CHECK23-NEXT: [[TMP16:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK23-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP16]] to i1 +// CHECK23-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL1]] to i8 +// CHECK23-NEXT: store i8 [[FROMBOOL2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 +// CHECK23-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK23-NEXT: [[TMP18:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK23-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP18]] to i1 // CHECK23-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK23: omp_if.then: -// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined, ptr [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], ptr [[TMP4]], i32 [[TMP8]]) +// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined, ptr [[TMP3]], i32 [[TMP15]], i32 [[TMP7]], i32 [[TMP9]], ptr [[TMP11]], i32 [[TMP17]]) // CHECK23-NEXT: br label [[OMP_IF_END:%.*]] // CHECK23: omp_if.else: // CHECK23-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) // CHECK23-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4 // CHECK23-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK23-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], ptr [[TMP4]], i32 [[TMP8]]) #[[ATTR1:[0-9]+]] +// CHECK23-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP3]], i32 [[TMP15]], i32 [[TMP7]], i32 [[TMP9]], ptr [[TMP11]], i32 [[TMP17]]) #[[ATTR1:[0-9]+]] // CHECK23-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]]) // CHECK23-NEXT: br label [[OMP_IF_END]] // CHECK23: omp_if.end: @@ -12274,26 +12408,32 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 -// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 +// CHECK23-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK23-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]]) +// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_6:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK23-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], ptr [[TMP0]], i32 0, i32 1 +// CHECK23-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK23-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK23-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], ptr [[TMP0]], i32 0, i32 2 +// CHECK23-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4 +// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 +// CHECK23-NEXT: store i32 [[TMP7]], ptr [[A_CASTED]], align 4 +// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK23-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK23-NEXT: store i16 [[TMP9]], ptr [[AA_CASTED]], align 2 +// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i32 [[TMP8]], i32 [[TMP10]], ptr [[TMP6]]) // CHECK23-NEXT: ret void // // diff --git a/clang/test/OpenMP/target_parallel_generic_loop_codegen-2.cpp b/clang/test/OpenMP/target_parallel_generic_loop_codegen-2.cpp index a92f052085c74..41a0e94620914 100644 --- a/clang/test/OpenMP/target_parallel_generic_loop_codegen-2.cpp +++ b/clang/test/OpenMP/target_parallel_generic_loop_codegen-2.cpp @@ -564,17 +564,22 @@ int nested(int a){ // // // TCHECK-TARGET-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42 -// TCHECK-TARGET-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// TCHECK-TARGET-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // TCHECK-TARGET-NEXT: entry: // TCHECK-TARGET-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK-TARGET-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// TCHECK-TARGET-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-TARGET-NEXT: [[A:%.*]] = alloca i32, align 4 // TCHECK-TARGET-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // TCHECK-TARGET-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// TCHECK-TARGET-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// TCHECK-TARGET-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// TCHECK-TARGET-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 -// TCHECK-TARGET-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// TCHECK-TARGET-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined, i64 [[TMP1]]) +// TCHECK-TARGET-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-TARGET-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-TARGET-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-TARGET-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// TCHECK-TARGET-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// TCHECK-TARGET-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 +// TCHECK-TARGET-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 +// TCHECK-TARGET-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// TCHECK-TARGET-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined, i64 [[TMP4]]) // TCHECK-TARGET-NEXT: ret void // // @@ -644,17 +649,22 @@ int nested(int a){ // // // TCHECK-TARGET-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49 -// TCHECK-TARGET-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// TCHECK-TARGET-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // TCHECK-TARGET-NEXT: entry: // TCHECK-TARGET-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// TCHECK-TARGET-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// TCHECK-TARGET-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-TARGET-NEXT: [[A:%.*]] = alloca i32, align 4 // TCHECK-TARGET-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // TCHECK-TARGET-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// TCHECK-TARGET-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// TCHECK-TARGET-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// TCHECK-TARGET-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 -// TCHECK-TARGET-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// TCHECK-TARGET-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined, i64 [[TMP1]]) +// TCHECK-TARGET-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-TARGET-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-TARGET-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-TARGET-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// TCHECK-TARGET-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// TCHECK-TARGET-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 +// TCHECK-TARGET-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 +// TCHECK-TARGET-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// TCHECK-TARGET-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined, i64 [[TMP4]]) // TCHECK-TARGET-NEXT: ret void // // @@ -724,17 +734,22 @@ int nested(int a){ // // // TCHECK-TARGET-X86-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42 -// TCHECK-TARGET-X86-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// TCHECK-TARGET-X86-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // TCHECK-TARGET-X86-NEXT: entry: // TCHECK-TARGET-X86-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK-TARGET-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// TCHECK-TARGET-X86-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-TARGET-X86-NEXT: [[A:%.*]] = alloca i32, align 4 // TCHECK-TARGET-X86-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // TCHECK-TARGET-X86-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// TCHECK-TARGET-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// TCHECK-TARGET-X86-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// TCHECK-TARGET-X86-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 -// TCHECK-TARGET-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// TCHECK-TARGET-X86-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined, i32 [[TMP1]]) +// TCHECK-TARGET-X86-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-TARGET-X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-TARGET-X86-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-TARGET-X86-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// TCHECK-TARGET-X86-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// TCHECK-TARGET-X86-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 +// TCHECK-TARGET-X86-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 +// TCHECK-TARGET-X86-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// TCHECK-TARGET-X86-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined, i32 [[TMP4]]) // TCHECK-TARGET-X86-NEXT: ret void // // @@ -804,17 +819,22 @@ int nested(int a){ // // // TCHECK-TARGET-X86-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49 -// TCHECK-TARGET-X86-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// TCHECK-TARGET-X86-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // TCHECK-TARGET-X86-NEXT: entry: // TCHECK-TARGET-X86-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// TCHECK-TARGET-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// TCHECK-TARGET-X86-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-TARGET-X86-NEXT: [[A:%.*]] = alloca i32, align 4 // TCHECK-TARGET-X86-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // TCHECK-TARGET-X86-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// TCHECK-TARGET-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// TCHECK-TARGET-X86-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// TCHECK-TARGET-X86-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 -// TCHECK-TARGET-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// TCHECK-TARGET-X86-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined, i32 [[TMP1]]) +// TCHECK-TARGET-X86-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-TARGET-X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-TARGET-X86-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-TARGET-X86-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// TCHECK-TARGET-X86-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// TCHECK-TARGET-X86-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 +// TCHECK-TARGET-X86-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 +// TCHECK-TARGET-X86-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// TCHECK-TARGET-X86-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined, i32 [[TMP4]]) // TCHECK-TARGET-X86-NEXT: ret void // // diff --git a/clang/test/OpenMP/target_parallel_if_codegen.cpp b/clang/test/OpenMP/target_parallel_if_codegen.cpp index 6447a76dd467c..5f30bdd0a9ffd 100644 --- a/clang/test/OpenMP/target_parallel_if_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_if_codegen.cpp @@ -1507,18 +1507,25 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK9-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 -// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load i8, ptr [[TMP2]], align 1 +// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK9-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK9-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP4]] to i1 +// CHECK9-NEXT: br i1 [[TOBOOL1]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK9: omp_if.then: // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined) // CHECK9-NEXT: br label [[OMP_IF_END:%.*]] @@ -1544,10 +1551,13 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined) // CHECK9-NEXT: ret void // @@ -1563,35 +1573,43 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP2]], ptr [[B_CASTED]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[B_CASTED]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 -// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 -// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8 +// CHECK9-NEXT: store i32 [[TMP5]], ptr [[B]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP1]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 4 +// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 +// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK9-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4 +// CHECK9-NEXT: store i32 [[TMP8]], ptr [[B_CASTED]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[B_CASTED]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK9-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP10]] to i1 +// CHECK9-NEXT: br i1 [[TOBOOL1]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK9: omp_if.then: -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP1]], i64 [[TMP3]]) +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP3]], i64 [[TMP9]]) // CHECK9-NEXT: br label [[OMP_IF_END:%.*]] // CHECK9: omp_if.else: // CHECK9-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i64 [[TMP3]]) #[[ATTR1]] +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP3]], i64 [[TMP9]]) #[[ATTR1]] // CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK9-NEXT: br label [[OMP_IF_END]] // CHECK9: omp_if.end: @@ -1619,29 +1637,35 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK9-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 -// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 -// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 8 +// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1 +// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK9-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK9-NEXT: [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK9-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP6]] to i1 +// CHECK9-NEXT: br i1 [[TOBOOL1]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK9: omp_if.then: -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[TMP1]]) +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[TMP3]]) // CHECK9-NEXT: br label [[OMP_IF_END:%.*]] // CHECK9: omp_if.else: // CHECK9-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]]) #[[ATTR1]] +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP3]]) #[[ATTR1]] // CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK9-NEXT: br label [[OMP_IF_END]] // CHECK9: omp_if.end: @@ -1664,23 +1688,28 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8 // CHECK9-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR1]] +// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], i64 [[TMP5]]) #[[ATTR1]] // CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK9-NEXT: ret void // @@ -1701,23 +1730,30 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[B:%.*]] = alloca i16, align 2 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[B_ADDR]], align 2 -// CHECK9-NEXT: store i16 [[TMP2]], ptr [[B_CASTED]], align 2 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[B_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK9-NEXT: store i16 [[TMP4]], ptr [[B]], align 2 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[B]], align 2 +// CHECK9-NEXT: store i16 [[TMP7]], ptr [[B_CASTED]], align 2 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[B_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP6]], i64 [[TMP8]]) // CHECK9-NEXT: ret void // // @@ -1741,18 +1777,25 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK11-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 -// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 -// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load i8, ptr [[TMP2]], align 1 +// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK11-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK11-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP4]] to i1 +// CHECK11-NEXT: br i1 [[TOBOOL1]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK11: omp_if.then: // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined) // CHECK11-NEXT: br label [[OMP_IF_END:%.*]] @@ -1778,10 +1821,13 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined) // CHECK11-NEXT: ret void // @@ -1797,35 +1843,43 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], ptr [[B_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 -// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 -// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP1]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], ptr [[B]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP1]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 4 +// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 +// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK11-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4 +// CHECK11-NEXT: store i32 [[TMP8]], ptr [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK11-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP10]] to i1 +// CHECK11-NEXT: br i1 [[TOBOOL1]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK11: omp_if.then: -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP1]], i32 [[TMP3]]) +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP3]], i32 [[TMP9]]) // CHECK11-NEXT: br label [[OMP_IF_END:%.*]] // CHECK11: omp_if.else: // CHECK11-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK11-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i32 [[TMP3]]) #[[ATTR1]] +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP3]], i32 [[TMP9]]) #[[ATTR1]] // CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK11-NEXT: br label [[OMP_IF_END]] // CHECK11: omp_if.end: @@ -1853,29 +1907,35 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK11-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 -// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 -// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP1]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 4 +// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1 +// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK11-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK11-NEXT: [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK11-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP6]] to i1 +// CHECK11-NEXT: br i1 [[TOBOOL1]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK11: omp_if.then: -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[TMP1]]) +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[TMP3]]) // CHECK11-NEXT: br label [[OMP_IF_END:%.*]] // CHECK11: omp_if.else: // CHECK11-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK11-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]]) #[[ATTR1]] +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP3]]) #[[ATTR1]] // CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK11-NEXT: br label [[OMP_IF_END]] // CHECK11: omp_if.end: @@ -1898,23 +1958,28 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4 // CHECK11-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK11-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR1]] +// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], i32 [[TMP5]]) #[[ATTR1]] // CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK11-NEXT: ret void // @@ -1935,23 +2000,30 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i16, align 2 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[B_ADDR]], align 2 -// CHECK11-NEXT: store i16 [[TMP2]], ptr [[B_CASTED]], align 2 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP1]], i32 [[TMP3]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK11-NEXT: store i16 [[TMP4]], ptr [[B]], align 2 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[B]], align 2 +// CHECK11-NEXT: store i16 [[TMP7]], ptr [[B_CASTED]], align 2 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP6]], i32 [[TMP8]]) // CHECK11-NEXT: ret void // // diff --git a/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp b/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp index a14518286dc91..06bd42099fa3a 100644 --- a/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp @@ -1346,15 +1346,20 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]]) // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined) // CHECK9-NEXT: ret void // @@ -1370,15 +1375,20 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]]) // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined) // CHECK9-NEXT: ret void // @@ -1394,25 +1404,31 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP3]], ptr [[B_CASTED]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[B_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP1]], i64 [[TMP4]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8 +// CHECK9-NEXT: store i32 [[TMP5]], ptr [[B]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP1]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK9-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP8]]) +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4 +// CHECK9-NEXT: store i32 [[TMP9]], ptr [[B_CASTED]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[B_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP3]], i64 [[TMP10]]) // CHECK9-NEXT: ret void // // @@ -1437,16 +1453,18 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 // CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 1024) -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[TMP1]]) +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[TMP3]]) // CHECK9-NEXT: ret void // // @@ -1466,11 +1484,14 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 // CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 20) // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.omp_outlined) // CHECK9-NEXT: ret void @@ -1487,29 +1508,38 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR__ADDR]], align 2 -// CHECK9-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[B_ADDR]], align 2 -// CHECK9-NEXT: store i16 [[TMP5]], ptr [[B_CASTED]], align 2 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP4]], i64 [[TMP6]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 4 +// CHECK9-NEXT: store i16 [[TMP5]], ptr [[B]], align 2 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP1]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 2 +// CHECK9-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2 +// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2 +// CHECK9-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP9]]) +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2 +// CHECK9-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2 +// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[B_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP11]], i64 [[TMP13]]) // CHECK9-NEXT: ret void // // @@ -1533,15 +1563,20 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]]) // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined) // CHECK11-NEXT: ret void // @@ -1557,15 +1592,20 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]]) // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined) // CHECK11-NEXT: ret void // @@ -1581,25 +1621,31 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], ptr [[B_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP1]], i32 [[TMP4]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP1]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], ptr [[B]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP1]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP8]]) +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4 +// CHECK11-NEXT: store i32 [[TMP9]], ptr [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[B_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP3]], i32 [[TMP10]]) // CHECK11-NEXT: ret void // // @@ -1624,16 +1670,18 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4 // CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 1024) -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[TMP1]]) +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[TMP3]]) // CHECK11-NEXT: ret void // // @@ -1653,11 +1701,14 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 // CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 20) // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.omp_outlined) // CHECK11-NEXT: ret void @@ -1674,29 +1725,38 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR__ADDR]], align 2 -// CHECK11-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[B_ADDR]], align 2 -// CHECK11-NEXT: store i16 [[TMP5]], ptr [[B_CASTED]], align 2 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP4]], i32 [[TMP6]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP1]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 4 +// CHECK11-NEXT: store i16 [[TMP5]], ptr [[B]], align 2 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP1]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 2 +// CHECK11-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2 +// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2 +// CHECK11-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP9]]) +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2 +// CHECK11-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP11]], i32 [[TMP13]]) // CHECK11-NEXT: ret void // // diff --git a/clang/test/OpenMP/target_private_codegen.cpp b/clang/test/OpenMP/target_private_codegen.cpp index 483e40f85f19a..4ab9fc8cc1540 100644 --- a/clang/test/OpenMP/target_private_codegen.cpp +++ b/clang/test/OpenMP/target_private_codegen.cpp @@ -1,3 +1,4 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ --version 4 // Only test codegen on target side, as private clause does not require any action on the host side // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc @@ -17,7 +18,6 @@ // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics #ifndef HEADER @@ -29,8 +29,6 @@ struct TT{ ty Y; }; -// TCHECK: [[TT:%.+]] = type { i64, i8 } -// TCHECK: [[S1:%.+]] = type { double } int foo(int n) { int a = 0; @@ -45,22 +43,12 @@ int foo(int n) { { } - // TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(ptr {{[^,]+}}) - // TCHECK: [[DYN_PTR:%.+]] = alloca ptr - // TCHECK: [[A:%.+]] = alloca i{{[0-9]+}}, - // TCHECK-NOT: store {{.+}}, {{.+}} [[A]], - // TCHECK: ret void #pragma omp target private(a) { a = 1; } - // TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(ptr {{[^,]+}}) - // TCHECK: [[DYN_PTR:%.+]] = alloca ptr - // TCHECK: [[A:%.+]] = alloca i{{[0-9]+}}, - // TCHECK: store i{{[0-9]+}} 1, ptr [[A]], - // TCHECK: ret void #pragma omp target private(a, aa) { @@ -68,13 +56,6 @@ int foo(int n) { aa = 1; } - // TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(ptr {{[^,]+}}) - // TCHECK: [[DYN_PTR:%.+]] = alloca ptr - // TCHECK: [[A:%.+]] = alloca i{{[0-9]+}}, - // TCHECK: [[A2:%.+]] = alloca i{{[0-9]+}}, - // TCHECK: store i{{[0-9]+}} 1, ptr [[A]], - // TCHECK: store i{{[0-9]+}} 1, ptr [[A2]], - // TCHECK: ret void #pragma omp target private(a, b, bn, c, cn, d) { @@ -88,49 +69,16 @@ int foo(int n) { } // make sure that private variables are generated in all cases and that we use those instances for operations inside the // target region - // TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(ptr {{[^,]+}}, i{{[0-9]+}} noundef [[VLA:%.+]], i{{[0-9]+}} noundef [[VLA1:%.+]], i{{[0-9]+}} noundef [[VLA3:%.+]]) - // TCHECK: [[DYN_PTR:%.+]] = alloca ptr - // TCHECK: [[VLA_ADDR:%.+]] = alloca i{{[0-9]+}}, - // TCHECK: [[VLA_ADDR2:%.+]] = alloca i{{[0-9]+}}, - // TCHECK: [[VLA_ADDR4:%.+]] = alloca i{{[0-9]+}}, - // TCHECK: [[A:%.+]] = alloca i{{[0-9]+}}, - // TCHECK: [[B:%.+]] = alloca [10 x float], - // TCHECK: [[SSTACK:%.+]] = alloca ptr, - // TCHECK: [[C:%.+]] = alloca [5 x [10 x double]], - // TCHECK: [[D:%.+]] = alloca [[TT]], - // TCHECK: store i{{[0-9]+}} [[VLA]], ptr [[VLA_ADDR]], - // TCHECK: store i{{[0-9]+}} [[VLA1]], ptr [[VLA_ADDR2]], - // TCHECK: store i{{[0-9]+}} [[VLA3]], ptr [[VLA_ADDR4]], - // TCHECK: [[VLA_ADDR_REF:%.+]] = load i{{[0-9]+}}, ptr [[VLA_ADDR]], - // TCHECK: [[VLA_ADDR_REF2:%.+]] = load i{{[0-9]+}}, ptr [[VLA_ADDR2]], - // TCHECK: [[VLA_ADDR_REF4:%.+]] = load i{{[0-9]+}}, ptr [[VLA_ADDR4]], - // TCHECK: [[RET_STACK:%.+]] = call ptr @llvm.stacksave.p0() - // TCHECK: store ptr [[RET_STACK]], ptr [[SSTACK]], - // TCHECK: [[VLA5:%.+]] = alloca float, i{{[0-9]+}} [[VLA_ADDR_REF]], - // TCHECK: [[VLA6_SIZE:%.+]] = mul{{.+}} i{{[0-9]+}} [[VLA_ADDR_REF2]], [[VLA_ADDR_REF4]] - // TCHECK: [[VLA6:%.+]] = alloca double, i{{[0-9]+}} [[VLA6_SIZE]], // a = 1 - // TCHECK: store i{{[0-9]+}} 1, ptr [[A]], // b[2] = 1.0 - // TCHECK: [[B_GEP:%.+]] = getelementptr inbounds [10 x float], ptr [[B]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 - // TCHECK: store float 1.0{{.*}}, ptr [[B_GEP]], // bn[3] = 1.0 - // TCHECK: [[BN_GEP:%.+]] = getelementptr inbounds float, ptr [[VLA5]], i{{[0-9]+}} 3 - // TCHECK: store float 1.0{{.*}}, ptr [[BN_GEP]], // c[1][2] = 1.0 - // TCHECK: [[C_GEP1:%.+]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // TCHECK: [[C_GEP2:%.+]] = getelementptr inbounds [10 x double], ptr [[C_GEP1]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 - // TCHECK: store double 1.0{{.*}}, ptr [[C_GEP2]], // cn[1][3] = 1.0 - // TCHECK: [[CN_IND:%.+]] = mul{{.+}} i{{[0-9]+}} 1, [[VLA_ADDR_REF4]] - // TCHECK: [[CN_GEP_IND:%.+]] = getelementptr inbounds double, ptr [[VLA6]], i{{[0-9]+}} [[CN_IND]] - // TCHECK: [[CN_GEP_3:%.+]] = getelementptr inbounds double, ptr [[CN_GEP_IND]], i{{[0-9]+}} 3 - // TCHECK: store double 1.0{{.*}}, ptr [[CN_GEP_3]], // d.X = 1 // [[X_FIELD:%.+]] = getelementptr inbounds [[TT]] ptr [[D]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 @@ -183,18 +131,6 @@ int fstatic(int n) { return a; } -// TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(ptr {{[^,]+}}) -// TCHECK: [[DYN_PTR:%.+]] = alloca ptr -// TCHECK: [[A:%.+]] = alloca i{{[0-9]+}}, -// TCHECK: [[A2:%.+]] = alloca i{{[0-9]+}}, -// TCHECK: [[A3:%.+]] = alloca i{{[0-9]+}}, -// TCHECK: [[B:%.+]] = alloca [10 x i{{[0-9]+}}], -// TCHECK: store i{{[0-9]+}} 1, ptr [[A]], -// TCHECK: store i{{[0-9]+}} 1, ptr [[A2]], -// TCHECK: store i{{[0-9]+}} 1, ptr [[A3]], -// TCHECK: [[B_GEP:%.+]] = getelementptr inbounds [10 x i{{[0-9]+}}], ptr [[B]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 -// TCHECK: store i{{[0-9]+}} 1, ptr [[B_GEP]], -// TCHECK: ret void struct S1 { double a; @@ -211,47 +147,6 @@ struct S1 { return c[1][1] + (int)b; } - - // TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(ptr {{[^,]+}}, ptr noundef [[TH:%.+]], i{{[0-9]+}} noundef [[VLA:%.+]], i{{[0-9]+}} noundef [[VLA1:%.+]]) - // TCHECK: [[DYN_PTR:%.+]] = alloca ptr - // TCHECK: [[TH_ADDR:%.+]] = alloca ptr, - // TCHECK: [[VLA_ADDR:%.+]] = alloca i{{[0-9]+}}, - // TCHECK: [[VLA_ADDR2:%.+]] = alloca i{{[0-9]+}}, - // TCHECK: [[B:%.+]] = alloca i{{[0-9]+}}, - // TCHECK: [[SSTACK:%.+]] = alloca ptr, - // TCHECK: store ptr [[TH]], ptr [[TH_ADDR]], - // TCHECK: store i{{[0-9]+}} [[VLA]], ptr [[VLA_ADDR]], - // TCHECK: store i{{[0-9]+}} [[VLA1]], ptr [[VLA_ADDR2]], - // TCHECK: [[TH_ADDR_REF:%.+]] = load ptr, ptr [[TH_ADDR]], - // TCHECK: [[VLA_ADDR_REF:%.+]] = load i{{[0-9]+}}, ptr [[VLA_ADDR]], - // TCHECK: [[VLA_ADDR_REF2:%.+]] = load i{{[0-9]+}}, ptr [[VLA_ADDR2]], - // TCHECK: [[RET_STACK:%.+]] = call ptr @llvm.stacksave.p0() - // TCHECK: store ptr [[RET_STACK:%.+]], ptr [[SSTACK]], - - // this->a = (double)b + 1.5; - // TCHECK: [[VLA_IND:%.+]] = mul{{.+}} i{{[0-9]+}} [[VLA_ADDR_REF]], [[VLA_ADDR_REF2]] - // TCHECK: [[VLA3:%.+]] = alloca i{{[0-9]+}}, i{{[0-9]+}} [[VLA_IND]], - // TCHECK: [[B_VAL:%.+]] = load i{{[0-9]+}}, ptr [[B]], - // TCHECK: [[B_CONV:%.+]] = sitofp i{{[0-9]+}} [[B_VAL]] to double - // TCHECK: [[NEW_A_VAL:%.+]] = fadd double [[B_CONV]], 1.5{{.+}}+00 - // TCHECK: [[A_FIELD:%.+]] = getelementptr inbounds [[S1]], ptr [[TH_ADDR_REF]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // TCHECK: store double [[NEW_A_VAL]], ptr [[A_FIELD]], - - // c[1][1] = ++a; - // TCHECK: [[A_FIELD4:%.+]] = getelementptr inbounds [[S1]], ptr [[TH_ADDR_REF]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // TCHECK: [[A_FIELD4_VAL:%.+]] = load double, ptr [[A_FIELD4]], - // TCHECK: [[A_FIELD_INC:%.+]] = fadd double [[A_FIELD4_VAL]], 1.0{{.+}}+00 - // TCHECK: store double [[A_FIELD_INC]], ptr [[A_FIELD4]], - // TCHECK: [[A_FIELD_INC_CONV:%.+]] = fptosi double [[A_FIELD_INC]] to i{{[0-9]+}} - // TCHECK: [[C_IND:%.+]] = mul{{.+}} i{{[0-9]+}} 1, [[VLA_ADDR_REF2]] - // TCHECK: [[C_1_REF:%.+]] = getelementptr inbounds i{{[0-9]+}}, ptr [[VLA3]], i{{[0-9]+}} [[C_IND]] - // TCHECK: [[C_1_1_REF:%.+]] = getelementptr inbounds i{{[0-9]+}}, ptr [[C_1_REF]], i{{[0-9]+}} 1 - // TCHECK: store i{{[0-9]+}} [[A_FIELD_INC_CONV]], ptr [[C_1_1_REF]], - - // finish - // TCHECK: [[RELOAD_SSTACK:%.+]] = load ptr, ptr [[SSTACK]], - // TCHECK: call void @llvm.stackrestore.p0(ptr [[RELOAD_SSTACK]]) - // TCHECK: ret void }; @@ -267,15 +162,365 @@ int bar(int n){ } // template -// TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(ptr {{[^,]+}}) -// TCHECK: [[DYN_PTR:%.+]] = alloca ptr -// TCHECK: [[A:%.+]] = alloca i{{[0-9]+}}, -// TCHECK: [[A2:%.+]] = alloca i{{[0-9]+}}, -// TCHECK: [[B:%.+]] = alloca [10 x i{{[0-9]+}}], -// TCHECK: store i{{[0-9]+}} 1, ptr [[A]], -// TCHECK: store i{{[0-9]+}} 1, ptr [[A2]], -// TCHECK: [[B_GEP:%.+]] = getelementptr inbounds [10 x i{{[0-9]+}}], ptr [[B]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 -// TCHECK: store i{{[0-9]+}} 1, ptr [[B_GEP]], -// TCHECK: ret void #endif +// TCHECK-64-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l42( +// TCHECK-64-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { +// TCHECK-64-NEXT: entry: +// TCHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: [[A:%.*]] = alloca i32, align 4 +// TCHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// TCHECK-64-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: ret void +// +// +// TCHECK-64-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47( +// TCHECK-64-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { +// TCHECK-64-NEXT: entry: +// TCHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: [[A:%.*]] = alloca i32, align 4 +// TCHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// TCHECK-64-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: store i32 1, ptr [[A]], align 4 +// TCHECK-64-NEXT: ret void +// +// +// TCHECK-64-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53( +// TCHECK-64-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { +// TCHECK-64-NEXT: entry: +// TCHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: [[A:%.*]] = alloca i32, align 4 +// TCHECK-64-NEXT: [[AA:%.*]] = alloca i16, align 2 +// TCHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// TCHECK-64-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: store i32 1, ptr [[A]], align 4 +// TCHECK-64-NEXT: store i16 1, ptr [[AA]], align 2 +// TCHECK-64-NEXT: ret void +// +// +// TCHECK-64-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l60( +// TCHECK-64-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { +// TCHECK-64-NEXT: entry: +// TCHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: [[A:%.*]] = alloca i32, align 4 +// TCHECK-64-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// TCHECK-64-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// TCHECK-64-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// TCHECK-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// TCHECK-64-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 8 +// TCHECK-64-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 +// TCHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// TCHECK-64-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-64-NEXT: [[TMP2:%.*]] = load i64, ptr [[TMP1]], align 8 +// TCHECK-64-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK-64-NEXT: [[TMP4:%.*]] = load i64, ptr [[TMP3]], align 8 +// TCHECK-64-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK-64-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8 +// TCHECK-64-NEXT: [[TMP7:%.*]] = call ptr @llvm.stacksave.p0() +// TCHECK-64-NEXT: store ptr [[TMP7]], ptr [[SAVED_STACK]], align 8 +// TCHECK-64-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 +// TCHECK-64-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 +// TCHECK-64-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP4]], [[TMP6]] +// TCHECK-64-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP8]], align 8 +// TCHECK-64-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 +// TCHECK-64-NEXT: store i64 [[TMP6]], ptr [[__VLA_EXPR2]], align 8 +// TCHECK-64-NEXT: store i32 1, ptr [[A]], align 4 +// TCHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 2 +// TCHECK-64-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 +// TCHECK-64-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 3 +// TCHECK-64-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX2]], align 4 +// TCHECK-64-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 1 +// TCHECK-64-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX3]], i64 0, i64 2 +// TCHECK-64-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX4]], align 8 +// TCHECK-64-NEXT: [[TMP9:%.*]] = mul nsw i64 1, [[TMP6]] +// TCHECK-64-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i64 [[TMP9]] +// TCHECK-64-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX5]], i64 3 +// TCHECK-64-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX6]], align 8 +// TCHECK-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 +// TCHECK-64-NEXT: store i64 1, ptr [[X]], align 8 +// TCHECK-64-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 +// TCHECK-64-NEXT: store i8 1, ptr [[Y]], align 8 +// TCHECK-64-NEXT: [[TMP10:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// TCHECK-64-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP10]]) +// TCHECK-64-NEXT: ret void +// +// +// TCHECK-64-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l123( +// TCHECK-64-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { +// TCHECK-64-NEXT: entry: +// TCHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: [[A:%.*]] = alloca i32, align 4 +// TCHECK-64-NEXT: [[AA:%.*]] = alloca i16, align 2 +// TCHECK-64-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// TCHECK-64-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// TCHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// TCHECK-64-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: store i32 1, ptr [[A]], align 4 +// TCHECK-64-NEXT: store i16 1, ptr [[AA]], align 2 +// TCHECK-64-NEXT: store i8 1, ptr [[AAA]], align 1 +// TCHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 +// TCHECK-64-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4 +// TCHECK-64-NEXT: ret void +// +// +// TCHECK-64-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l142( +// TCHECK-64-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { +// TCHECK-64-NEXT: entry: +// TCHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: [[B:%.*]] = alloca i32, align 4 +// TCHECK-64-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// TCHECK-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// TCHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// TCHECK-64-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// TCHECK-64-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK-64-NEXT: [[TMP4:%.*]] = load i64, ptr [[TMP3]], align 8 +// TCHECK-64-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK-64-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8 +// TCHECK-64-NEXT: [[TMP7:%.*]] = call ptr @llvm.stacksave.p0() +// TCHECK-64-NEXT: store ptr [[TMP7]], ptr [[SAVED_STACK]], align 8 +// TCHECK-64-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP4]], [[TMP6]] +// TCHECK-64-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP8]], align 2 +// TCHECK-64-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR0]], align 8 +// TCHECK-64-NEXT: store i64 [[TMP6]], ptr [[__VLA_EXPR1]], align 8 +// TCHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4 +// TCHECK-64-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double +// TCHECK-64-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// TCHECK-64-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP2]], i32 0, i32 0 +// TCHECK-64-NEXT: store double [[ADD]], ptr [[A]], align 8 +// TCHECK-64-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP2]], i32 0, i32 0 +// TCHECK-64-NEXT: [[TMP10:%.*]] = load double, ptr [[A1]], align 8 +// TCHECK-64-NEXT: [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00 +// TCHECK-64-NEXT: store double [[INC]], ptr [[A1]], align 8 +// TCHECK-64-NEXT: [[CONV2:%.*]] = fptosi double [[INC]] to i16 +// TCHECK-64-NEXT: [[TMP11:%.*]] = mul nsw i64 1, [[TMP6]] +// TCHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP11]] +// TCHECK-64-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 +// TCHECK-64-NEXT: store i16 [[CONV2]], ptr [[ARRAYIDX3]], align 2 +// TCHECK-64-NEXT: [[TMP12:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// TCHECK-64-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP12]]) +// TCHECK-64-NEXT: ret void +// +// +// TCHECK-64-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l106( +// TCHECK-64-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { +// TCHECK-64-NEXT: entry: +// TCHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: [[A:%.*]] = alloca i32, align 4 +// TCHECK-64-NEXT: [[AA:%.*]] = alloca i16, align 2 +// TCHECK-64-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// TCHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// TCHECK-64-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: store i32 1, ptr [[A]], align 4 +// TCHECK-64-NEXT: store i16 1, ptr [[AA]], align 2 +// TCHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 +// TCHECK-64-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4 +// TCHECK-64-NEXT: ret void +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// TCHECK-32-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l42( +// TCHECK-32-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { +// TCHECK-32-NEXT: entry: +// TCHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: [[A:%.*]] = alloca i32, align 4 +// TCHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// TCHECK-32-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: ret void +// +// +// TCHECK-32-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47( +// TCHECK-32-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { +// TCHECK-32-NEXT: entry: +// TCHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: [[A:%.*]] = alloca i32, align 4 +// TCHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// TCHECK-32-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: store i32 1, ptr [[A]], align 4 +// TCHECK-32-NEXT: ret void +// +// +// TCHECK-32-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53( +// TCHECK-32-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { +// TCHECK-32-NEXT: entry: +// TCHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: [[A:%.*]] = alloca i32, align 4 +// TCHECK-32-NEXT: [[AA:%.*]] = alloca i16, align 2 +// TCHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// TCHECK-32-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: store i32 1, ptr [[A]], align 4 +// TCHECK-32-NEXT: store i16 1, ptr [[AA]], align 2 +// TCHECK-32-NEXT: ret void +// +// +// TCHECK-32-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l60( +// TCHECK-32-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { +// TCHECK-32-NEXT: entry: +// TCHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: [[A:%.*]] = alloca i32, align 4 +// TCHECK-32-NEXT: [[B:%.*]] = alloca [10 x float], align 4 +// TCHECK-32-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// TCHECK-32-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 +// TCHECK-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// TCHECK-32-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 4 +// TCHECK-32-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 +// TCHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// TCHECK-32-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// TCHECK-32-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// TCHECK-32-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// TCHECK-32-NEXT: [[TMP7:%.*]] = call ptr @llvm.stacksave.p0() +// TCHECK-32-NEXT: store ptr [[TMP7]], ptr [[SAVED_STACK]], align 4 +// TCHECK-32-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP2]], align 4 +// TCHECK-32-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR0]], align 4 +// TCHECK-32-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP4]], [[TMP6]] +// TCHECK-32-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP8]], align 8 +// TCHECK-32-NEXT: store i32 [[TMP4]], ptr [[__VLA_EXPR1]], align 4 +// TCHECK-32-NEXT: store i32 [[TMP6]], ptr [[__VLA_EXPR2]], align 4 +// TCHECK-32-NEXT: store i32 1, ptr [[A]], align 4 +// TCHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 2 +// TCHECK-32-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 +// TCHECK-32-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[VLA]], i32 3 +// TCHECK-32-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX2]], align 4 +// TCHECK-32-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 1 +// TCHECK-32-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX3]], i32 0, i32 2 +// TCHECK-32-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX4]], align 8 +// TCHECK-32-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP6]] +// TCHECK-32-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i32 [[TMP9]] +// TCHECK-32-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX5]], i32 3 +// TCHECK-32-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX6]], align 8 +// TCHECK-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 +// TCHECK-32-NEXT: store i64 1, ptr [[X]], align 4 +// TCHECK-32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 +// TCHECK-32-NEXT: store i8 1, ptr [[Y]], align 4 +// TCHECK-32-NEXT: [[TMP10:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// TCHECK-32-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP10]]) +// TCHECK-32-NEXT: ret void +// +// +// TCHECK-32-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l123( +// TCHECK-32-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { +// TCHECK-32-NEXT: entry: +// TCHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: [[A:%.*]] = alloca i32, align 4 +// TCHECK-32-NEXT: [[AA:%.*]] = alloca i16, align 2 +// TCHECK-32-NEXT: [[AAA:%.*]] = alloca i8, align 1 +// TCHECK-32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// TCHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// TCHECK-32-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: store i32 1, ptr [[A]], align 4 +// TCHECK-32-NEXT: store i16 1, ptr [[AA]], align 2 +// TCHECK-32-NEXT: store i8 1, ptr [[AAA]], align 1 +// TCHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 +// TCHECK-32-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4 +// TCHECK-32-NEXT: ret void +// +// +// TCHECK-32-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l142( +// TCHECK-32-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { +// TCHECK-32-NEXT: entry: +// TCHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: [[B:%.*]] = alloca i32, align 4 +// TCHECK-32-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 +// TCHECK-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 +// TCHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// TCHECK-32-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-32-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// TCHECK-32-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// TCHECK-32-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// TCHECK-32-NEXT: [[TMP7:%.*]] = call ptr @llvm.stacksave.p0() +// TCHECK-32-NEXT: store ptr [[TMP7]], ptr [[SAVED_STACK]], align 4 +// TCHECK-32-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP4]], [[TMP6]] +// TCHECK-32-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP8]], align 2 +// TCHECK-32-NEXT: store i32 [[TMP4]], ptr [[__VLA_EXPR0]], align 4 +// TCHECK-32-NEXT: store i32 [[TMP6]], ptr [[__VLA_EXPR1]], align 4 +// TCHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4 +// TCHECK-32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double +// TCHECK-32-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// TCHECK-32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP2]], i32 0, i32 0 +// TCHECK-32-NEXT: store double [[ADD]], ptr [[A]], align 4 +// TCHECK-32-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP2]], i32 0, i32 0 +// TCHECK-32-NEXT: [[TMP10:%.*]] = load double, ptr [[A1]], align 4 +// TCHECK-32-NEXT: [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00 +// TCHECK-32-NEXT: store double [[INC]], ptr [[A1]], align 4 +// TCHECK-32-NEXT: [[CONV2:%.*]] = fptosi double [[INC]] to i16 +// TCHECK-32-NEXT: [[TMP11:%.*]] = mul nsw i32 1, [[TMP6]] +// TCHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP11]] +// TCHECK-32-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 +// TCHECK-32-NEXT: store i16 [[CONV2]], ptr [[ARRAYIDX3]], align 2 +// TCHECK-32-NEXT: [[TMP12:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// TCHECK-32-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP12]]) +// TCHECK-32-NEXT: ret void +// +// +// TCHECK-32-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l106( +// TCHECK-32-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { +// TCHECK-32-NEXT: entry: +// TCHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: [[A:%.*]] = alloca i32, align 4 +// TCHECK-32-NEXT: [[AA:%.*]] = alloca i16, align 2 +// TCHECK-32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 +// TCHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// TCHECK-32-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: store i32 1, ptr [[A]], align 4 +// TCHECK-32-NEXT: store i16 1, ptr [[AA]], align 2 +// TCHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 +// TCHECK-32-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4 +// TCHECK-32-NEXT: ret void + +// NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +// SIMD-ONLY0: {{.*}} +// TCHECK: {{.*}} diff --git a/clang/test/OpenMP/target_reduction_codegen.cpp b/clang/test/OpenMP/target_reduction_codegen.cpp index 9f113be62beb5..d9bfc6679205d 100644 --- a/clang/test/OpenMP/target_reduction_codegen.cpp +++ b/clang/test/OpenMP/target_reduction_codegen.cpp @@ -1,3 +1,4 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ --version 4 // Only test codegen on target side, as private clause does not require any action on the host side // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc @@ -17,7 +18,6 @@ // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics #ifndef HEADER @@ -30,8 +30,6 @@ struct TT{ TT operator*(const TT &) { return *this; } }; -// TCHECK: [[S1:%.+]] = type { double } - int foo(int n) { int a = 0; short aa = 0; @@ -45,48 +43,21 @@ int foo(int n) { { } - // TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(ptr {{[^,]+}}, ptr{{.+}} %{{.+}}) - // TCHECK: [[DYN_PTR:%.+]] = alloca ptr, - // TCHECK: [[A:%.+]] = alloca ptr, - // TCHECK: store {{.+}}, {{.+}} [[A]], - // TCHECK: load ptr, ptr [[A]], - // TCHECK: ret void - #pragma omp target reduction(+:a) { a = 1; } - // TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(ptr {{[^,]+}}, ptr{{.+}} %{{.+}}) - // TCHECK: [[DYN_PTR:%.+]] = alloca ptr, - // TCHECK: [[A:%.+]] = alloca ptr, - // TCHECK: store {{.+}}, {{.+}} [[A]], - // TCHECK: [[REF:%.+]] = load ptr, ptr [[A]], - // TCHECK: store i{{[0-9]+}} 1, ptr [[REF]], - // TCHECK: ret void - #pragma omp target reduction(-:a, aa) { a = 1; aa = 1; } - // TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(ptr {{[^,]+}}, ptr{{.+}} [[A:%.+]], ptr{{.+}} [[AA:%.+]]) - // TCHECK: [[DYN_PTR:%.+]] = alloca ptr, - // TCHECK: [[A:%.+]] = alloca ptr, - // TCHECK: [[AA:%.+]] = alloca ptr, - // TCHECK: store {{.+}}, {{.+}} [[A]], - // TCHECK: store {{.+}}, {{.+}} [[AA]], - // TCHECK: [[A_REF:%.+]] = load ptr, ptr [[A]], - // TCHECK: [[AA_REF:%.+]] = load ptr, ptr [[AA]], - // TCHECK: store i{{[0-9]+}} 1, ptr [[A_REF]], - // TCHECK: store i{{[0-9]+}} 1, ptr [[AA_REF]], - // TCHECK: ret void return a; } - template tx ftemplate(int n) { tx a = 0; @@ -121,26 +92,6 @@ int fstatic(int n) { return a; } -// TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(ptr {{[^,]+}}, ptr{{.+}}, ptr{{.+}}, ptr{{.+}}, ptr{{.+}}) -// TCHECK: [[DYN_PTR:%.+]] = alloca ptr, -// TCHECK: [[A:%.+]] = alloca ptr, -// TCHECK: [[A2:%.+]] = alloca ptr, -// TCHECK: [[A3:%.+]] = alloca ptr, -// TCHECK: [[B:%.+]] = alloca ptr, -// TCHECK: store {{.+}}, {{.+}} [[A]], -// TCHECK: store {{.+}}, {{.+}} [[A2]], -// TCHECK: store {{.+}}, {{.+}} [[A3]], -// TCHECK: store {{.+}}, {{.+}} [[B]], -// TCHECK: [[A_REF:%.+]] = load ptr, ptr [[A]], -// TCHECK: [[AA_REF:%.+]] = load ptr, ptr [[AA]], -// TCHECK: [[A3_REF:%.+]] = load ptr, ptr [[A3]], -// TCHECK: [[B_REF:%.+]] = load ptr, ptr [[B]], -// TCHECK: store i{{[0-9]+}} 1, ptr [[A_REF]], -// TCHECK: store i{{[0-9]+}} 1, ptr [[AA_REF]], -// TCHECK: store i{{[0-9]+}} 1, ptr [[A3_REF]], -// TCHECK: [[B_GEP:%.+]] = getelementptr inbounds [10 x i{{[0-9]+}}], ptr [[B_REF]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 -// TCHECK: store i{{[0-9]+}} 1, ptr [[B_GEP]], -// TCHECK: ret void struct S1 { double a; @@ -157,48 +108,8 @@ struct S1 { return c[1][1] + (int)b; } - - // TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(ptr {{[^,]+}}, ptr noundef [[TH:%.+]], ptr{{.+}}, i{{[0-9]+}} noundef [[VLA:%.+]], i{{[0-9]+}} noundef [[VLA1:%.+]], ptr{{.+}}) - // TCHECK: [[DYN_PTR:%.+]] = alloca ptr, - // TCHECK: [[TH_ADDR:%.+]] = alloca ptr, - // TCHECK: [[B_ADDR:%.+]] = alloca ptr, - // TCHECK: [[VLA_ADDR:%.+]] = alloca i{{[0-9]+}}, - // TCHECK: [[VLA_ADDR2:%.+]] = alloca i{{[0-9]+}}, - // TCHECK: [[C_ADDR:%.+]] = alloca ptr, - // TCHECK: store ptr [[TH]], ptr [[TH_ADDR]], - // TCHECK: store ptr {{.+}}, ptr [[B_ADDR]], - // TCHECK: store i{{[0-9]+}} [[VLA]], ptr [[VLA_ADDR]], - // TCHECK: store i{{[0-9]+}} [[VLA1]], ptr [[VLA_ADDR2]], - // TCHECK: store ptr {{.+}}, ptr [[C_ADDR]], - // TCHECK: [[TH_ADDR_REF:%.+]] = load ptr, ptr [[TH_ADDR]], - // TCHECK: [[B_REF:%.+]] = load ptr, ptr [[B_ADDR]], - // TCHECK: [[VLA_ADDR_REF:%.+]] = load i{{[0-9]+}}, ptr [[VLA_ADDR]], - // TCHECK: [[VLA_ADDR_REF2:%.+]] = load i{{[0-9]+}}, ptr [[VLA_ADDR2]], - // TCHECK: [[C_REF:%.+]] = load ptr, ptr [[C_ADDR]], - - // this->a = (double)b + 1.5; - // TCHECK: [[B_VAL:%.+]] = load i{{[0-9]+}}, ptr [[B_REF]], - // TCHECK: [[B_CONV:%.+]] = sitofp i{{[0-9]+}} [[B_VAL]] to double - // TCHECK: [[NEW_A_VAL:%.+]] = fadd double [[B_CONV]], 1.5{{.+}}+00 - // TCHECK: [[A_FIELD:%.+]] = getelementptr inbounds [[S1]], ptr [[TH_ADDR_REF]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // TCHECK: store double [[NEW_A_VAL]], ptr [[A_FIELD]], - - // c[1][1] = ++a; - // TCHECK: [[A_FIELD4:%.+]] = getelementptr inbounds [[S1]], ptr [[TH_ADDR_REF]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // TCHECK: [[A_FIELD4_VAL:%.+]] = load double, ptr [[A_FIELD4]], - // TCHECK: [[A_FIELD_INC:%.+]] = fadd double [[A_FIELD4_VAL]], 1.0{{.+}}+00 - // TCHECK: store double [[A_FIELD_INC]], ptr [[A_FIELD4]], - // TCHECK: [[A_FIELD_INC_CONV:%.+]] = fptosi double [[A_FIELD_INC]] to i{{[0-9]+}} - // TCHECK: [[C_IND:%.+]] = mul{{.+}} i{{[0-9]+}} 1, [[VLA_ADDR_REF2]] - // TCHECK: [[C_1_REF:%.+]] = getelementptr inbounds i{{[0-9]+}}, ptr [[C_REF]], i{{[0-9]+}} [[C_IND]] - // TCHECK: [[C_1_1_REF:%.+]] = getelementptr inbounds i{{[0-9]+}}, ptr [[C_1_REF]], i{{[0-9]+}} 1 - // TCHECK: store i{{[0-9]+}} [[A_FIELD_INC_CONV]], ptr [[C_1_1_REF]], - - // finish - // TCHECK: ret void }; - int bar(int n){ int a = 0; a += foo(n); @@ -211,21 +122,294 @@ int bar(int n){ } // template -// TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(ptr {{[^,]+}}, ptr{{.+}}, ptr{{.+}}, ptr{{.+}}) -// TCHECK: [[DYN_PTR:%.+]] = alloca ptr, -// TCHECK: [[A:%.+]] = alloca ptr, -// TCHECK: [[A2:%.+]] = alloca ptr, -// TCHECK: [[B:%.+]] = alloca ptr, -// TCHECK: store {{.+}}, {{.+}} [[A]], -// TCHECK: store {{.+}}, {{.+}} [[A2]], -// TCHECK: store {{.+}}, {{.+}} [[B]], -// TCHECK: [[A_REF:%.+]] = load ptr, ptr [[A]], -// TCHECK: [[AA_REF:%.+]] = load ptr, ptr [[AA]], -// TCHECK: [[B_REF:%.+]] = load ptr, ptr [[B]], -// TCHECK: store i{{[0-9]+}} 1, ptr [[A_REF]], -// TCHECK: store i{{[0-9]+}} 1, ptr [[AA_REF]], -// TCHECK: [[B_GEP:%.+]] = getelementptr inbounds [10 x i{{[0-9]+}}], ptr [[B_REF]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 -// TCHECK: store i{{[0-9]+}} 1, ptr [[B_GEP]], -// TCHECK: ret void #endif + +// TCHECK-64-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l42( +// TCHECK-64-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { +// TCHECK-64-NEXT: entry: +// TCHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// TCHECK-64-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// TCHECK-64-NEXT: ret void +// +// +// TCHECK-64-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l46( +// TCHECK-64-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { +// TCHECK-64-NEXT: entry: +// TCHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// TCHECK-64-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// TCHECK-64-NEXT: store i32 1, ptr [[TMP2]], align 4 +// TCHECK-64-NEXT: ret void +// +// +// TCHECK-64-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l51( +// TCHECK-64-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { +// TCHECK-64-NEXT: entry: +// TCHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// TCHECK-64-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// TCHECK-64-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK-64-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// TCHECK-64-NEXT: store i32 1, ptr [[TMP2]], align 4 +// TCHECK-64-NEXT: store i16 1, ptr [[TMP4]], align 2 +// TCHECK-64-NEXT: ret void +// +// +// TCHECK-64-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l84( +// TCHECK-64-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { +// TCHECK-64-NEXT: entry: +// TCHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// TCHECK-64-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// TCHECK-64-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK-64-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// TCHECK-64-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK-64-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// TCHECK-64-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 3 +// TCHECK-64-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8 +// TCHECK-64-NEXT: store i32 1, ptr [[TMP2]], align 4 +// TCHECK-64-NEXT: store i16 1, ptr [[TMP4]], align 2 +// TCHECK-64-NEXT: store i8 1, ptr [[TMP6]], align 1 +// TCHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP8]], i64 0, i64 2 +// TCHECK-64-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4 +// TCHECK-64-NEXT: ret void +// +// +// TCHECK-64-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l103( +// TCHECK-64-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { +// TCHECK-64-NEXT: entry: +// TCHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// TCHECK-64-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// TCHECK-64-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK-64-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// TCHECK-64-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK-64-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8 +// TCHECK-64-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 3 +// TCHECK-64-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8 +// TCHECK-64-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 4 +// TCHECK-64-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// TCHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP4]], align 4 +// TCHECK-64-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP11]] to double +// TCHECK-64-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// TCHECK-64-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP2]], i32 0, i32 0 +// TCHECK-64-NEXT: store double [[ADD]], ptr [[A]], align 8 +// TCHECK-64-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP2]], i32 0, i32 0 +// TCHECK-64-NEXT: [[TMP12:%.*]] = load double, ptr [[A1]], align 8 +// TCHECK-64-NEXT: [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00 +// TCHECK-64-NEXT: store double [[INC]], ptr [[A1]], align 8 +// TCHECK-64-NEXT: [[CONV2:%.*]] = fptosi double [[INC]] to i16 +// TCHECK-64-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP8]] +// TCHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP10]], i64 [[TMP13]] +// TCHECK-64-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 +// TCHECK-64-NEXT: store i16 [[CONV2]], ptr [[ARRAYIDX3]], align 2 +// TCHECK-64-NEXT: ret void +// +// +// TCHECK-64-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l67( +// TCHECK-64-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { +// TCHECK-64-NEXT: entry: +// TCHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// TCHECK-64-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// TCHECK-64-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// TCHECK-64-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK-64-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// TCHECK-64-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK-64-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// TCHECK-64-NEXT: store i32 1, ptr [[TMP2]], align 4 +// TCHECK-64-NEXT: store i16 1, ptr [[TMP4]], align 2 +// TCHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP6]], i64 0, i64 2 +// TCHECK-64-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4 +// TCHECK-64-NEXT: ret void +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// TCHECK-32-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l42( +// TCHECK-32-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { +// TCHECK-32-NEXT: entry: +// TCHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// TCHECK-32-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-32-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// TCHECK-32-NEXT: ret void +// +// +// TCHECK-32-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l46( +// TCHECK-32-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { +// TCHECK-32-NEXT: entry: +// TCHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// TCHECK-32-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-32-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// TCHECK-32-NEXT: store i32 1, ptr [[TMP2]], align 4 +// TCHECK-32-NEXT: ret void +// +// +// TCHECK-32-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l51( +// TCHECK-32-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { +// TCHECK-32-NEXT: entry: +// TCHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// TCHECK-32-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-32-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// TCHECK-32-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK-32-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4 +// TCHECK-32-NEXT: store i32 1, ptr [[TMP2]], align 4 +// TCHECK-32-NEXT: store i16 1, ptr [[TMP4]], align 2 +// TCHECK-32-NEXT: ret void +// +// +// TCHECK-32-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l84( +// TCHECK-32-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { +// TCHECK-32-NEXT: entry: +// TCHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// TCHECK-32-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-32-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// TCHECK-32-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK-32-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4 +// TCHECK-32-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK-32-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4 +// TCHECK-32-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 3 +// TCHECK-32-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4 +// TCHECK-32-NEXT: store i32 1, ptr [[TMP2]], align 4 +// TCHECK-32-NEXT: store i16 1, ptr [[TMP4]], align 2 +// TCHECK-32-NEXT: store i8 1, ptr [[TMP6]], align 1 +// TCHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP8]], i32 0, i32 2 +// TCHECK-32-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4 +// TCHECK-32-NEXT: ret void +// +// +// TCHECK-32-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l103( +// TCHECK-32-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { +// TCHECK-32-NEXT: entry: +// TCHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// TCHECK-32-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-32-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// TCHECK-32-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK-32-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4 +// TCHECK-32-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// TCHECK-32-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 3 +// TCHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 +// TCHECK-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 4 +// TCHECK-32-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4 +// TCHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP4]], align 4 +// TCHECK-32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP11]] to double +// TCHECK-32-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// TCHECK-32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP2]], i32 0, i32 0 +// TCHECK-32-NEXT: store double [[ADD]], ptr [[A]], align 4 +// TCHECK-32-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP2]], i32 0, i32 0 +// TCHECK-32-NEXT: [[TMP12:%.*]] = load double, ptr [[A1]], align 4 +// TCHECK-32-NEXT: [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00 +// TCHECK-32-NEXT: store double [[INC]], ptr [[A1]], align 4 +// TCHECK-32-NEXT: [[CONV2:%.*]] = fptosi double [[INC]] to i16 +// TCHECK-32-NEXT: [[TMP13:%.*]] = mul nsw i32 1, [[TMP8]] +// TCHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP10]], i32 [[TMP13]] +// TCHECK-32-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 +// TCHECK-32-NEXT: store i16 [[CONV2]], ptr [[ARRAYIDX3]], align 2 +// TCHECK-32-NEXT: ret void +// +// +// TCHECK-32-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l67( +// TCHECK-32-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { +// TCHECK-32-NEXT: entry: +// TCHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// TCHECK-32-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// TCHECK-32-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-32-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// TCHECK-32-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 1 +// TCHECK-32-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4 +// TCHECK-32-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 2 +// TCHECK-32-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4 +// TCHECK-32-NEXT: store i32 1, ptr [[TMP2]], align 4 +// TCHECK-32-NEXT: store i16 1, ptr [[TMP4]], align 2 +// TCHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP6]], i32 0, i32 2 +// TCHECK-32-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4 +// TCHECK-32-NEXT: ret void +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +//// NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +// SIMD-ONLY0: {{.*}} +// TCHECK: {{.*}} diff --git a/clang/test/OpenMP/target_task_affinity_codegen.cpp b/clang/test/OpenMP/target_task_affinity_codegen.cpp index 2ef6e5a2f7a3d..37dd4e6748219 100644 --- a/clang/test/OpenMP/target_task_affinity_codegen.cpp +++ b/clang/test/OpenMP/target_task_affinity_codegen.cpp @@ -571,46 +571,47 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[B:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 8 // CHECK9-NEXT: [[DOTAFFS_ARR_ADDR:%.*]] = alloca [1 x %struct.kmp_task_affinity_info_t], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0 -// CHECK9-NEXT: store ptr [[B_ADDR]], ptr [[TMP1]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 48, i64 8, ptr @.omp_task_entry.) -// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x %struct.kmp_task_affinity_info_t], ptr [[DOTAFFS_ARR_ADDR]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 0 -// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i64 1023 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[ARRAYIDX1]], i32 1 -// CHECK9-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64 -// CHECK9-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP6]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = sub nuw i64 [[TMP8]], [[TMP7]] -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr [[STRUCT_KMP_TASK_AFFINITY_INFO_T:%.*]], ptr [[TMP3]], i64 0 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP10]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64 -// CHECK9-NEXT: store i64 [[TMP12]], ptr [[TMP11]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP10]], i32 0, i32 1 -// CHECK9-NEXT: store i64 [[TMP9]], ptr [[TMP13]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_omp_reg_task_with_affinity(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP2]], i32 1, ptr [[TMP3]]) -// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP2]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP15]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8 -// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP17]], ptr align 8 [[AGG_CAPTURED]], i64 8, i1 false) -// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP2]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP18]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP20:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[TMP20]], ptr [[TMP19]], align 8 -// CHECK9-NEXT: [[TMP21:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP2]]) -// CHECK9-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_omp_taskwait(ptr @[[GLOB1]], i32 [[TMP0]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK9-NEXT: store ptr [[TMP2]], ptr [[TMP4]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 48, i64 8, ptr @.omp_task_entry.) +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x %struct.kmp_task_affinity_info_t], ptr [[DOTAFFS_ARR_ADDR]], i64 0, i64 0 +// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP3]], align 8 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP7]], i64 0 +// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP3]], align 8 +// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[TMP8]], i64 1023 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[ARRAYIDX1]], i32 1 +// CHECK9-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64 +// CHECK9-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP9]] to i64 +// CHECK9-NEXT: [[TMP12:%.*]] = sub nuw i64 [[TMP11]], [[TMP10]] +// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr [[STRUCT_KMP_TASK_AFFINITY_INFO_T:%.*]], ptr [[TMP6]], i64 0 +// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP13]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64 +// CHECK9-NEXT: store i64 [[TMP15]], ptr [[TMP14]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP13]], i32 0, i32 1 +// CHECK9-NEXT: store i64 [[TMP12]], ptr [[TMP16]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_omp_reg_task_with_affinity(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP5]], i32 1, ptr [[TMP6]]) +// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP18]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8 +// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP20]], ptr align 8 [[AGG_CAPTURED]], i64 8, i1 false) +// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP5]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP21]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP3]], align 8 +// CHECK9-NEXT: store ptr [[TMP23]], ptr [[TMP22]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP5]]) +// CHECK9-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_omp_taskwait(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK9-NEXT: ret void // // @@ -693,46 +694,47 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[B:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 4 // CHECK11-NEXT: [[DOTAFFS_ARR_ADDR:%.*]] = alloca [1 x %struct.kmp_task_affinity_info_t], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0 -// CHECK11-NEXT: store ptr [[B_ADDR]], ptr [[TMP1]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 24, i32 4, ptr @.omp_task_entry.) -// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x %struct.kmp_task_affinity_info_t], ptr [[DOTAFFS_ARR_ADDR]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i32 0 -// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i32 1023 -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[ARRAYIDX1]], i32 1 -// CHECK11-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i32 -// CHECK11-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP6]] to i32 -// CHECK11-NEXT: [[TMP9:%.*]] = sub nuw i32 [[TMP8]], [[TMP7]] -// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr [[STRUCT_KMP_TASK_AFFINITY_INFO_T:%.*]], ptr [[TMP3]], i32 0 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP10]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i32 -// CHECK11-NEXT: store i32 [[TMP12]], ptr [[TMP11]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP10]], i32 0, i32 1 -// CHECK11-NEXT: store i32 [[TMP9]], ptr [[TMP13]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_omp_reg_task_with_affinity(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP2]], i32 1, ptr [[TMP3]]) -// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP2]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP15]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 4 -// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP17]], ptr align 4 [[AGG_CAPTURED]], i32 4, i1 false) -// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP2]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP18]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP20:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[TMP20]], ptr [[TMP19]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP2]]) -// CHECK11-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_omp_taskwait(ptr @[[GLOB1]], i32 [[TMP0]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK11-NEXT: store ptr [[TMP2]], ptr [[TMP4]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 24, i32 4, ptr @.omp_task_entry.) +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x %struct.kmp_task_affinity_info_t], ptr [[DOTAFFS_ARR_ADDR]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP3]], align 4 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP7]], i32 0 +// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP3]], align 4 +// CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[TMP8]], i32 1023 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[ARRAYIDX1]], i32 1 +// CHECK11-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i32 +// CHECK11-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP9]] to i32 +// CHECK11-NEXT: [[TMP12:%.*]] = sub nuw i32 [[TMP11]], [[TMP10]] +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr [[STRUCT_KMP_TASK_AFFINITY_INFO_T:%.*]], ptr [[TMP6]], i32 0 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP13]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i32 +// CHECK11-NEXT: store i32 [[TMP15]], ptr [[TMP14]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP13]], i32 0, i32 1 +// CHECK11-NEXT: store i32 [[TMP12]], ptr [[TMP16]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_omp_reg_task_with_affinity(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP5]], i32 1, ptr [[TMP6]]) +// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP5]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP18]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 4 +// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP20]], ptr align 4 [[AGG_CAPTURED]], i32 4, i1 false) +// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP5]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP21]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP3]], align 4 +// CHECK11-NEXT: store ptr [[TMP23]], ptr [[TMP22]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP5]]) +// CHECK11-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_omp_taskwait(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK11-NEXT: ret void // // diff --git a/clang/test/OpenMP/target_teams_codegen.cpp b/clang/test/OpenMP/target_teams_codegen.cpp index 24dc2fd2e49f4..21977b88e94e5 100644 --- a/clang/test/OpenMP/target_teams_codegen.cpp +++ b/clang/test/OpenMP/target_teams_codegen.cpp @@ -3486,25 +3486,34 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i64 [[TMP4]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4 +// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK9-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP8]], i32 [[TMP9]]) +// CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2 +// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i64 [[TMP11]]) // CHECK9-NEXT: ret void // // @@ -3521,17 +3530,22 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK9-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP1]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 2 +// CHECK9-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 +// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP4]]) // CHECK9-NEXT: ret void // // @@ -3553,23 +3567,30 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK9-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP6]], i64 [[TMP8]]) // CHECK9-NEXT: ret void // // @@ -3596,25 +3617,32 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 4 +// CHECK9-NEXT: store i16 [[TMP5]], ptr [[AA]], align 2 // CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined, i64 [[TMP2]], i64 [[TMP4]]) +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2 +// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined, i64 [[TMP7]], i64 [[TMP9]]) // CHECK9-NEXT: ret void // // @@ -3641,41 +3669,38 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l148 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 -// CHECK9-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l148.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 5 +// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 6 +// CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 7 +// CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 8 +// CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP19]], ptr [[A_CASTED]], align 4 +// CHECK9-NEXT: [[TMP20:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l148.omp_outlined, i64 [[TMP20]], ptr [[TMP4]], i64 [[TMP6]], ptr [[TMP8]], ptr [[TMP10]], i64 [[TMP12]], i64 [[TMP14]], ptr [[TMP16]], ptr [[TMP18]]) // CHECK9-NEXT: ret void // // @@ -3752,17 +3777,22 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[NN:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[NN]], ptr [[NN_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP0]], ptr [[NN_CASTED]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[NN_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i64 [[TMP1]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[NN]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[NN]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], ptr [[NN_CASTED]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[NN_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i64 [[TMP4]]) // CHECK9-NEXT: ret void // // @@ -3796,17 +3826,22 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[NN:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[NN]], ptr [[NN_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP0]], ptr [[NN_CASTED]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[NN_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163.omp_outlined, i64 [[TMP1]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_6:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[NN]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[NN]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], ptr [[NN_CASTED]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[NN_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163.omp_outlined, i64 [[TMP4]]) // CHECK9-NEXT: ret void // // @@ -3837,14 +3872,16 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l188 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l188.omp_outlined, i64 [[TMP0]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_7:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[TMP1]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l188.omp_outlined, i64 [[TMP2]]) // CHECK9-NEXT: ret void // // @@ -3863,32 +3900,40 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l215 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[AAA:%.*]] = alloca i8, align 1 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 -// CHECK9-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l215.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_8:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_8]], ptr [[TMP0]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_8]], ptr [[TMP0]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 2 +// CHECK9-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_8]], ptr [[TMP0]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP9]], ptr [[A_CASTED]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP11]], ptr [[AA_CASTED]], align 2 +// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = load i8, ptr [[AAA]], align 1 +// CHECK9-NEXT: store i8 [[TMP13]], ptr [[AAA_CASTED]], align 1 +// CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l215.omp_outlined, i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP14]], ptr [[TMP8]]) // CHECK9-NEXT: ret void // // @@ -3929,29 +3974,30 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l233 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l233.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_9:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_9]], ptr [[TMP0]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8 +// CHECK9-NEXT: store i32 [[TMP4]], ptr [[B]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_9]], ptr [[TMP0]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_9]], ptr [[TMP0]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_9]], ptr [[TMP0]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[B]], align 4 +// CHECK9-NEXT: store i32 [[TMP11]], ptr [[B_CASTED]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[B_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l233.omp_outlined, ptr [[TMP2]], i64 [[TMP12]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP10]]) // CHECK9-NEXT: ret void // // @@ -3994,26 +4040,32 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l198 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l198.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_10:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_10]], ptr [[TMP0]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_10]], ptr [[TMP0]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP7]], ptr [[A_CASTED]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP9]], ptr [[AA_CASTED]], align 2 +// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l198.omp_outlined, i64 [[TMP8]], i64 [[TMP10]], ptr [[TMP6]]) // CHECK9-NEXT: ret void // // @@ -4047,25 +4099,34 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i32 [[TMP4]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4 +// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP8]], i32 [[TMP9]]) +// CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i32 [[TMP11]]) // CHECK11-NEXT: ret void // // @@ -4082,17 +4143,22 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK11-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP1]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 2 +// CHECK11-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP4]]) // CHECK11-NEXT: ret void // // @@ -4114,23 +4180,30 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK11-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP1]], i32 [[TMP3]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP6]], i32 [[TMP8]]) // CHECK11-NEXT: ret void // // @@ -4157,25 +4230,32 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP1]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 4 +// CHECK11-NEXT: store i16 [[TMP5]], ptr [[AA]], align 2 // CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined, i32 [[TMP2]], i32 [[TMP4]]) +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined, i32 [[TMP7]], i32 [[TMP9]]) // CHECK11-NEXT: ret void // // @@ -4202,41 +4282,38 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l148 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 -// CHECK11-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l148.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 5 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 6 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 7 +// CHECK11-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 8 +// CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP19]], ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l148.omp_outlined, i32 [[TMP20]], ptr [[TMP4]], i32 [[TMP6]], ptr [[TMP8]], ptr [[TMP10]], i32 [[TMP12]], i32 [[TMP14]], ptr [[TMP16]], ptr [[TMP18]]) // CHECK11-NEXT: ret void // // @@ -4313,17 +4390,22 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[NN:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[NN]], ptr [[NN_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], ptr [[NN_CASTED]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[NN_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i32 [[TMP1]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[NN]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[NN]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], ptr [[NN_CASTED]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[NN_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i32 [[TMP4]]) // CHECK11-NEXT: ret void // // @@ -4357,17 +4439,22 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[NN:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[NN]], ptr [[NN_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], ptr [[NN_CASTED]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[NN_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163.omp_outlined, i32 [[TMP1]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_6:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[NN]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[NN]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], ptr [[NN_CASTED]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[NN_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163.omp_outlined, i32 [[TMP4]]) // CHECK11-NEXT: ret void // // @@ -4398,14 +4485,16 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l188 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l188.omp_outlined, i32 [[TMP0]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_7:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l188.omp_outlined, i32 [[TMP2]]) // CHECK11-NEXT: ret void // // @@ -4424,32 +4513,40 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l215 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[AAA:%.*]] = alloca i8, align 1 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 -// CHECK11-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l215.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_8:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_8]], ptr [[TMP0]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_8]], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 2 +// CHECK11-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_8]], ptr [[TMP0]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP9]], ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP11]], ptr [[AA_CASTED]], align 2 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i8, ptr [[AAA]], align 1 +// CHECK11-NEXT: store i8 [[TMP13]], ptr [[AAA_CASTED]], align 1 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l215.omp_outlined, i32 [[TMP10]], i32 [[TMP12]], i32 [[TMP14]], ptr [[TMP8]]) // CHECK11-NEXT: ret void // // @@ -4490,29 +4587,30 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l233 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l233.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_9:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_9]], ptr [[TMP0]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], ptr [[B]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_9]], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_9]], ptr [[TMP0]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_9]], ptr [[TMP0]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[B]], align 4 +// CHECK11-NEXT: store i32 [[TMP11]], ptr [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l233.omp_outlined, ptr [[TMP2]], i32 [[TMP12]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP10]]) // CHECK11-NEXT: ret void // // @@ -4555,26 +4653,32 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l198 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l198.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_10:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_10]], ptr [[TMP0]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_10]], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP9]], ptr [[AA_CASTED]], align 2 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l198.omp_outlined, i32 [[TMP8]], i32 [[TMP10]], ptr [[TMP6]]) // CHECK11-NEXT: ret void // // diff --git a/clang/test/OpenMP/target_teams_distribute_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_codegen.cpp index bd33e52ca3ef0..5bbdf96c59d20 100644 --- a/clang/test/OpenMP/target_teams_distribute_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_codegen.cpp @@ -3771,25 +3771,34 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined, i64 [[TMP4]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4 +// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK9-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP8]], i32 [[TMP9]]) +// CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2 +// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined, i64 [[TMP11]]) // CHECK9-NEXT: ret void // // @@ -3856,17 +3865,22 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK9-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined, i64 [[TMP1]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 2 +// CHECK9-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 +// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined, i64 [[TMP4]]) // CHECK9-NEXT: ret void // // @@ -3938,23 +3952,30 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK9-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined, i64 [[TMP6]], i64 [[TMP8]]) // CHECK9-NEXT: ret void // // @@ -4031,47 +4052,46 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 -// CHECK9-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 5 +// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 6 +// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 7 +// CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 8 +// CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 9 +// CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 10 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 8 +// CHECK9-NEXT: store i32 [[TMP20]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, ptr [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP21]], ptr [[A_CASTED]], align 4 +// CHECK9-NEXT: [[TMP22:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: store i32 [[TMP23]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK9-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined, i64 [[TMP22]], ptr [[TMP4]], i64 [[TMP6]], ptr [[TMP8]], ptr [[TMP10]], i64 [[TMP12]], i64 [[TMP14]], ptr [[TMP16]], ptr [[TMP18]], i64 [[TMP24]]) // CHECK9-NEXT: ret void // // @@ -4218,38 +4238,48 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[AAA:%.*]] = alloca i8, align 1 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[N_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK9-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 -// CHECK9-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 1 -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP0]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[N]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK9-NEXT: store i32 [[TMP4]], ptr [[A]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8 +// CHECK9-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 2 +// CHECK9-NEXT: store i8 [[TMP8]], ptr [[AAA]], align 1 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[N]], align 4 +// CHECK9-NEXT: store i32 [[TMP11]], ptr [[N_CASTED]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP13]], ptr [[A_CASTED]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP15]], ptr [[AA_CASTED]], align 2 +// CHECK9-NEXT: [[TMP16:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = load i8, ptr [[AAA]], align 1 +// CHECK9-NEXT: store i8 [[TMP17]], ptr [[AAA_CASTED]], align 1 +// CHECK9-NEXT: [[TMP18:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined, i64 [[TMP12]], i64 [[TMP14]], i64 [[TMP16]], i64 [[TMP18]], ptr [[TMP10]]) // CHECK9-NEXT: ret void // // @@ -4374,29 +4404,30 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8 +// CHECK9-NEXT: store i32 [[TMP4]], ptr [[B]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[B]], align 4 +// CHECK9-NEXT: store i32 [[TMP11]], ptr [[B_CASTED]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[B_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined, ptr [[TMP2]], i64 [[TMP12]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP10]]) // CHECK9-NEXT: ret void // // @@ -4489,26 +4520,32 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_6:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], ptr [[TMP0]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], ptr [[TMP0]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP7]], ptr [[A_CASTED]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK9-NEXT: store i16 [[TMP9]], ptr [[AA_CASTED]], align 2 +// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined, i64 [[TMP8]], i64 [[TMP10]], ptr [[TMP6]]) // CHECK9-NEXT: ret void // // @@ -4592,25 +4629,34 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined, i32 [[TMP4]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4 +// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP8]], i32 [[TMP9]]) +// CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined, i32 [[TMP11]]) // CHECK11-NEXT: ret void // // @@ -4677,17 +4723,22 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK11-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined, i32 [[TMP1]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 2 +// CHECK11-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined, i32 [[TMP4]]) // CHECK11-NEXT: ret void // // @@ -4759,23 +4810,30 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK11-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined, i32 [[TMP1]], i32 [[TMP3]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined, i32 [[TMP6]], i32 [[TMP8]]) // CHECK11-NEXT: ret void // // @@ -4852,47 +4910,46 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 -// CHECK11-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 5 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 6 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 7 +// CHECK11-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 8 +// CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 9 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 +// CHECK11-NEXT: store i32 [[TMP20]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP21]], ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: store i32 [[TMP23]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined, i32 [[TMP22]], ptr [[TMP4]], i32 [[TMP6]], ptr [[TMP8]], ptr [[TMP10]], i32 [[TMP12]], i32 [[TMP14]], ptr [[TMP16]], ptr [[TMP18]], i32 [[TMP24]]) // CHECK11-NEXT: ret void // // @@ -5039,38 +5096,48 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[AAA:%.*]] = alloca i8, align 1 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK11-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 -// CHECK11-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 1 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP0]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[N]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], ptr [[A]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4 +// CHECK11-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 2 +// CHECK11-NEXT: store i8 [[TMP8]], ptr [[AAA]], align 1 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[N]], align 4 +// CHECK11-NEXT: store i32 [[TMP11]], ptr [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP13]], ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP15]], ptr [[AA_CASTED]], align 2 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i8, ptr [[AAA]], align 1 +// CHECK11-NEXT: store i8 [[TMP17]], ptr [[AAA_CASTED]], align 1 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined, i32 [[TMP12]], i32 [[TMP14]], i32 [[TMP16]], i32 [[TMP18]], ptr [[TMP10]]) // CHECK11-NEXT: ret void // // @@ -5195,29 +5262,30 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK11-NEXT: store i32 [[TMP4]], ptr [[B]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[B]], align 4 +// CHECK11-NEXT: store i32 [[TMP11]], ptr [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined, ptr [[TMP2]], i32 [[TMP12]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP10]]) // CHECK11-NEXT: ret void // // @@ -5310,26 +5378,32 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK11-NEXT: store i16 [[TMP9]], ptr [[AA_CASTED]], align 2 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined, i32 [[TMP8]], i32 [[TMP10]], ptr [[TMP6]]) // CHECK11-NEXT: ret void // // diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp index 0d0d996747214..51f8ee8b50b2e 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp @@ -1840,28 +1840,36 @@ int target_teams_fun(int *g){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 -// CHECK10-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]) // CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 -// CHECK10-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK10-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i64, ptr [[N_CASTED]], align 8 -// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.omp_outlined, i64 [[TMP5]], ptr [[TMP1]]) +// CHECK10-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8 +// CHECK10-NEXT: store i32 [[TMP3]], ptr [[N]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8 +// CHECK10-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 +// CHECK10-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP10]], i32 [[TMP11]]) +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, ptr [[N]], align 4 +// CHECK10-NEXT: store i32 [[TMP12]], ptr [[N_CASTED]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.omp_outlined, i64 [[TMP13]], ptr [[TMP5]]) // CHECK10-NEXT: ret void // // @@ -2073,23 +2081,26 @@ int target_teams_fun(int *g){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 -// CHECK10-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK10-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 8 +// CHECK10-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 -// CHECK10-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK10-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, ptr [[N_CASTED]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[G_ADDR]], align 8 -// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58.omp_outlined, i64 [[TMP2]], ptr [[TMP0]], ptr [[TMP3]]) +// CHECK10-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK10-NEXT: store i32 [[TMP2]], ptr [[N]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4 +// CHECK10-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58.omp_outlined, i64 [[TMP7]], ptr [[TMP4]], ptr [[TMP8]]) // CHECK10-NEXT: ret void // // @@ -2294,28 +2305,36 @@ int target_teams_fun(int *g){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 -// CHECK12-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]) // CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 -// CHECK12-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK12-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4 -// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.omp_outlined, i32 [[TMP5]], ptr [[TMP1]]) +// CHECK12-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], ptr [[N]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK12-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 +// CHECK12-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP10]], i32 [[TMP11]]) +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, ptr [[N]], align 4 +// CHECK12-NEXT: store i32 [[TMP12]], ptr [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, ptr [[N_CASTED]], align 4 +// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.omp_outlined, i32 [[TMP13]], ptr [[TMP5]]) // CHECK12-NEXT: ret void // // @@ -2522,23 +2541,26 @@ int target_teams_fun(int *g){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 -// CHECK12-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK12-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4 +// CHECK12-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 -// CHECK12-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 -// CHECK12-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load ptr, ptr [[G_ADDR]], align 4 -// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58.omp_outlined, i32 [[TMP2]], ptr [[TMP0]], ptr [[TMP3]]) +// CHECK12-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], ptr [[N]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4 +// CHECK12-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP5]], align 4 +// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58.omp_outlined, i32 [[TMP7]], ptr [[TMP4]], ptr [[TMP8]]) // CHECK12-NEXT: ret void // // diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp index bf1fc1d7cbae5..cf83ebde940a2 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp @@ -2645,32 +2645,36 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 -// CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK13-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK13-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 -// CHECK13-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 -// CHECK13-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 -// CHECK13-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK13-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 -// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP6]]) +// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 1 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8 +// CHECK13-NEXT: store i32 [[TMP4]], ptr [[T_VAR]], align 4 +// CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 3 +// CHECK13-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK13-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 4 +// CHECK13-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8 +// CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 5 +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 8 +// CHECK13-NEXT: store i32 [[TMP10]], ptr [[SIVAR]], align 4 +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK13-NEXT: store i32 [[TMP11]], ptr [[T_VAR_CASTED]], align 4 +// CHECK13-NEXT: [[TMP12:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[SIVAR]], align 4 +// CHECK13-NEXT: store i32 [[TMP13]], ptr [[SIVAR_CASTED]], align 4 +// CHECK13-NEXT: [[TMP14:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 +// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[TMP2]], i64 [[TMP12]], ptr [[TMP6]], ptr [[TMP8]], i64 [[TMP14]]) // CHECK13-NEXT: ret void // // @@ -2975,29 +2979,31 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 -// CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK13-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 -// CHECK13-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 -// CHECK13-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 -// CHECK13-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 -// CHECK13-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 -// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) +// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8 +// CHECK13-NEXT: store i32 [[TMP4]], ptr [[T_VAR]], align 4 +// CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// CHECK13-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK13-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 3 +// CHECK13-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8 +// CHECK13-NEXT: store ptr [[TMP8]], ptr [[TMP]], align 8 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK13-NEXT: store i32 [[TMP9]], ptr [[T_VAR_CASTED]], align 4 +// CHECK13-NEXT: [[TMP10:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 +// CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[TMP2]], i64 [[TMP10]], ptr [[TMP6]], ptr [[TMP11]]) // CHECK13-NEXT: ret void // // @@ -3018,9 +3024,9 @@ int main() { // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.1], align 4 // CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_1:%.*]], align 4 // CHECK13-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK13-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -3040,8 +3046,8 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK13: omp.arraycpy.body: @@ -3050,8 +3056,8 @@ int main() { // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] -// CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_1]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_1]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK13: omp.arraycpy.done4: @@ -3108,12 +3114,12 @@ int main() { // CHECK13-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]]) // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i64 2 +// CHECK13-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN9]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] @@ -3155,9 +3161,9 @@ int main() { // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.1], align 4 // CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK13-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK13-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_1:%.*]], align 4 // CHECK13-NEXT: [[AGG_TMP7:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK13-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -3184,8 +3190,8 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK13: omp.arraycpy.body: @@ -3194,8 +3200,8 @@ int main() { // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] -// CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_1]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_1]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]] // CHECK13: omp.arraycpy.done5: @@ -3241,7 +3247,7 @@ int main() { // CHECK13-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP8]], align 8 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK13-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] +// CHECK13-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false) // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -3258,12 +3264,12 @@ int main() { // CHECK13-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2 +// CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] @@ -3353,9 +3359,9 @@ int main() { // CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 -// CHECK13-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 +// CHECK13-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[TMP0]], i32 0, i32 0 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 // CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 @@ -3365,32 +3371,36 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 -// CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK15-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK15-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 -// CHECK15-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 -// CHECK15-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 -// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i32 [[TMP6]]) +// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 1 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK15-NEXT: store i32 [[TMP4]], ptr [[T_VAR]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4 +// CHECK15-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 3 +// CHECK15-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4 +// CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 4 +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 +// CHECK15-NEXT: store i32 [[TMP10]], ptr [[SIVAR]], align 4 +// CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK15-NEXT: store i32 [[TMP11]], ptr [[T_VAR_CASTED]], align 4 +// CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 +// CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[SIVAR]], align 4 +// CHECK15-NEXT: store i32 [[TMP13]], ptr [[SIVAR_CASTED]], align 4 +// CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 +// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[TMP2]], i32 [[TMP12]], ptr [[TMP6]], ptr [[TMP8]], i32 [[TMP14]]) // CHECK15-NEXT: ret void // // @@ -3689,29 +3699,31 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 -// CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK15-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 -// CHECK15-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 -// CHECK15-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 -// CHECK15-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 -// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) +// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK15-NEXT: store i32 [[TMP4]], ptr [[T_VAR]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4 +// CHECK15-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 3 +// CHECK15-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4 +// CHECK15-NEXT: store ptr [[TMP8]], ptr [[TMP]], align 4 +// CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK15-NEXT: store i32 [[TMP9]], ptr [[T_VAR_CASTED]], align 4 +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 +// CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[TMP2]], i32 [[TMP10]], ptr [[TMP6]], ptr [[TMP11]]) // CHECK15-NEXT: ret void // // @@ -3732,9 +3744,9 @@ int main() { // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.1], align 4 // CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_1:%.*]], align 4 // CHECK15-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK15-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -3754,8 +3766,8 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK15: omp.arraycpy.body: @@ -3764,8 +3776,8 @@ int main() { // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] // CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) #[[ATTR4]] // CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] -// CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_1]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_1]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK15: omp.arraycpy.done4: @@ -3820,12 +3832,12 @@ int main() { // CHECK15-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 +// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP21]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] @@ -3867,9 +3879,9 @@ int main() { // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.1], align 4 // CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_1:%.*]], align 4 // CHECK15-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK15-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -3894,8 +3906,8 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK15: omp.arraycpy.body: @@ -3904,8 +3916,8 @@ int main() { // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] // CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) #[[ATTR4]] // CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] -// CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_1]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_1]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK15: omp.arraycpy.done4: @@ -3949,7 +3961,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 // CHECK15-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] +// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP17]], i32 4, i1 false) // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -3966,12 +3978,12 @@ int main() { // CHECK15-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 +// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] @@ -4061,9 +4073,9 @@ int main() { // CHECK15-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 // CHECK15-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 -// CHECK15-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 +// CHECK15-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[TMP0]], i32 0, i32 0 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 // CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 @@ -4073,32 +4085,41 @@ int main() { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[G:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[G1:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[G_ADDR]], align 4 -// CHECK17-NEXT: store i32 [[TMP0]], ptr [[G_CASTED]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load volatile i32, ptr [[TMP2]], align 4 -// CHECK17-NEXT: store i32 [[TMP3]], ptr [[G1_CASTED]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[G1_CASTED]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined, i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK17-NEXT: store i32 [[TMP2]], ptr [[G]], align 4 +// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK17-NEXT: store i32 [[TMP4]], ptr [[G1]], align 4 +// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK17-NEXT: store i32 [[TMP6]], ptr [[SIVAR]], align 4 +// CHECK17-NEXT: store ptr [[G1]], ptr [[TMP]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[G]], align 4 +// CHECK17-NEXT: store i32 [[TMP7]], ptr [[G_CASTED]], align 4 +// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[G_CASTED]], align 8 +// CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK17-NEXT: [[TMP10:%.*]] = load volatile i32, ptr [[TMP9]], align 4 +// CHECK17-NEXT: store i32 [[TMP10]], ptr [[G1_CASTED]], align 4 +// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[G1_CASTED]], align 8 +// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 +// CHECK17-NEXT: store i32 [[TMP12]], ptr [[SIVAR_CASTED]], align 4 +// CHECK17-NEXT: [[TMP13:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined, i64 [[TMP8]], i64 [[TMP11]], i64 [[TMP13]]) // CHECK17-NEXT: ret void // // diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp index 49e4681c05153..201a539e92e7c 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp @@ -1931,10 +1931,13 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 -// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined) // CHECK13-NEXT: ret void // @@ -2165,10 +2168,13 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 -// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined) // CHECK13-NEXT: ret void // @@ -2187,8 +2193,8 @@ int main() { // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.1], align 4 +// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_1:%.*]], align 4 // CHECK13-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -2198,13 +2204,13 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 +// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: @@ -2254,12 +2260,12 @@ int main() { // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i64 2 +// CHECK13-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN4]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] @@ -2293,8 +2299,8 @@ int main() { // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.1], align 4 +// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_1:%.*]], align 4 // CHECK13-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -2312,13 +2318,13 @@ int main() { // CHECK13-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 +// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: @@ -2361,7 +2367,7 @@ int main() { // CHECK13-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false) // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2378,12 +2384,12 @@ int main() { // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 +// CHECK13-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN8]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] @@ -2429,7 +2435,7 @@ int main() { // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK13-NEXT: ret void @@ -2445,10 +2451,13 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 -// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 // CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined) // CHECK15-NEXT: ret void // @@ -2673,10 +2682,13 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 -// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 // CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined) // CHECK15-NEXT: ret void // @@ -2695,8 +2707,8 @@ int main() { // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.1], align 4 +// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_1:%.*]], align 4 // CHECK15-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2706,13 +2718,13 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 +// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: @@ -2760,12 +2772,12 @@ int main() { // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i32 2 +// CHECK15-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN4]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] @@ -2799,8 +2811,8 @@ int main() { // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.1], align 4 +// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_1:%.*]], align 4 // CHECK15-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2816,13 +2828,13 @@ int main() { // CHECK15-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 +// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: @@ -2863,7 +2875,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK15-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i32 0, i32 [[TMP13]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false) // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -2880,12 +2892,12 @@ int main() { // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 +// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] @@ -2931,7 +2943,7 @@ int main() { // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK15-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK15-NEXT: ret void @@ -2947,10 +2959,13 @@ int main() { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined) // CHECK17-NEXT: ret void // diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp index a4119a07f61f2..6ee82803fa870 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp @@ -2323,34 +2323,44 @@ void test_target_teams_atomic() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[I:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB4:[0-9]+]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[I]], ptr [[I_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[I_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP4]], ptr [[I_CASTED]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[I_CASTED]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50.omp_outlined, i64 [[TMP5]], i64 [[TMP7]], ptr [[TMP1]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8 +// CHECK9-NEXT: store i32 [[TMP3]], ptr [[I]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], ptr [[N]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 8 +// CHECK9-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 +// CHECK9-NEXT: store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB4]], i32 [[TMP0]], i32 [[TMP12]], i32 [[TMP13]]) +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 +// CHECK9-NEXT: store i32 [[TMP14]], ptr [[I_CASTED]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[I_CASTED]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[N]], align 4 +// CHECK9-NEXT: store i32 [[TMP16]], ptr [[N_CASTED]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50.omp_outlined, i64 [[TMP15]], i64 [[TMP17]], ptr [[TMP7]]) // CHECK9-NEXT: ret void // // @@ -2599,23 +2609,26 @@ void test_target_teams_atomic() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[N_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[G_ADDR]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56.omp_outlined, i64 [[TMP2]], ptr [[TMP0]], ptr [[TMP3]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[N]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4 +// CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56.omp_outlined, i64 [[TMP7]], ptr [[TMP4]], ptr [[TMP8]]) // CHECK9-NEXT: ret void // // @@ -2844,14 +2857,16 @@ void test_target_teams_atomic() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z24test_target_teams_atomicv_l72 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z24test_target_teams_atomicv_l72.omp_outlined, ptr [[TMP0]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z24test_target_teams_atomicv_l72.omp_outlined, ptr [[TMP2]]) // CHECK9-NEXT: ret void // // @@ -3007,34 +3022,44 @@ void test_target_teams_atomic() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[I:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB4:[0-9]+]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[I_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP4]], ptr [[I_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[I_CASTED]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50.omp_outlined, i32 [[TMP5]], i32 [[TMP7]], ptr [[TMP1]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], ptr [[I]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], ptr [[N]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 +// CHECK11-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 +// CHECK11-NEXT: store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB4]], i32 [[TMP0]], i32 [[TMP12]], i32 [[TMP13]]) +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 +// CHECK11-NEXT: store i32 [[TMP14]], ptr [[I_CASTED]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[I_CASTED]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[N]], align 4 +// CHECK11-NEXT: store i32 [[TMP16]], ptr [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[N_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50.omp_outlined, i32 [[TMP15]], i32 [[TMP17]], ptr [[TMP7]]) // CHECK11-NEXT: ret void // // @@ -3278,23 +3303,26 @@ void test_target_teams_atomic() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[G_ADDR]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56.omp_outlined, i32 [[TMP2]], ptr [[TMP0]], ptr [[TMP3]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[N]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4 +// CHECK11-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP5]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56.omp_outlined, i32 [[TMP7]], ptr [[TMP4]], ptr [[TMP8]]) // CHECK11-NEXT: ret void // // @@ -3518,14 +3546,16 @@ void test_target_teams_atomic() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z24test_target_teams_atomicv_l72 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z24test_target_teams_atomicv_l72.omp_outlined, ptr [[TMP0]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z24test_target_teams_atomicv_l72.omp_outlined, ptr [[TMP2]]) // CHECK11-NEXT: ret void // // diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp index ea05aecebf371..13751aca11b12 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp @@ -3487,32 +3487,36 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 -// CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK13-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK13-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 -// CHECK13-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 -// CHECK13-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 -// CHECK13-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK13-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 -// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP6]]) +// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 1 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8 +// CHECK13-NEXT: store i32 [[TMP4]], ptr [[T_VAR]], align 4 +// CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 3 +// CHECK13-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK13-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 4 +// CHECK13-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8 +// CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 5 +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 8 +// CHECK13-NEXT: store i32 [[TMP10]], ptr [[SIVAR]], align 4 +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK13-NEXT: store i32 [[TMP11]], ptr [[T_VAR_CASTED]], align 4 +// CHECK13-NEXT: [[TMP12:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[SIVAR]], align 4 +// CHECK13-NEXT: store i32 [[TMP13]], ptr [[SIVAR_CASTED]], align 4 +// CHECK13-NEXT: [[TMP14:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 +// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[TMP2]], i64 [[TMP12]], ptr [[TMP6]], ptr [[TMP8]], i64 [[TMP14]]) // CHECK13-NEXT: ret void // // @@ -3831,29 +3835,31 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 -// CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK13-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 -// CHECK13-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 -// CHECK13-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 -// CHECK13-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 -// CHECK13-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 -// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) +// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK13-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK13-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8 +// CHECK13-NEXT: store i32 [[TMP4]], ptr [[T_VAR]], align 4 +// CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// CHECK13-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK13-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 3 +// CHECK13-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8 +// CHECK13-NEXT: store ptr [[TMP8]], ptr [[TMP]], align 8 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK13-NEXT: store i32 [[TMP9]], ptr [[T_VAR_CASTED]], align 4 +// CHECK13-NEXT: [[TMP10:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 +// CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[TMP2]], i64 [[TMP10]], ptr [[TMP6]], ptr [[TMP11]]) // CHECK13-NEXT: ret void // // @@ -3874,9 +3880,9 @@ int main() { // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.1], align 4 // CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_1:%.*]], align 4 // CHECK13-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK13-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -3896,8 +3902,8 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK13: omp.arraycpy.body: @@ -3906,8 +3912,8 @@ int main() { // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] -// CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_1]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_1]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK13: omp.arraycpy.done4: @@ -3971,12 +3977,12 @@ int main() { // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i64 2 +// CHECK13-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN9]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] @@ -4018,9 +4024,9 @@ int main() { // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.1], align 4 // CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK13-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK13-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_1:%.*]], align 4 // CHECK13-NEXT: [[AGG_TMP7:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK13-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -4047,8 +4053,8 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK13: omp.arraycpy.body: @@ -4057,8 +4063,8 @@ int main() { // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] -// CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_1]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_1]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]] // CHECK13: omp.arraycpy.done5: @@ -4104,7 +4110,7 @@ int main() { // CHECK13-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP8]], align 8, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK13-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] +// CHECK13-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -4128,12 +4134,12 @@ int main() { // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2 +// CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] @@ -4223,9 +4229,9 @@ int main() { // CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 -// CHECK13-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 +// CHECK13-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[TMP0]], i32 0, i32 0 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 // CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 @@ -4235,32 +4241,36 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 -// CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK15-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK15-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 -// CHECK15-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 -// CHECK15-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 -// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i32 [[TMP6]]) +// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 1 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK15-NEXT: store i32 [[TMP4]], ptr [[T_VAR]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4 +// CHECK15-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 3 +// CHECK15-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4 +// CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 4 +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 +// CHECK15-NEXT: store i32 [[TMP10]], ptr [[SIVAR]], align 4 +// CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK15-NEXT: store i32 [[TMP11]], ptr [[T_VAR_CASTED]], align 4 +// CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 +// CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[SIVAR]], align 4 +// CHECK15-NEXT: store i32 [[TMP13]], ptr [[SIVAR_CASTED]], align 4 +// CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 +// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[TMP2]], i32 [[TMP12]], ptr [[TMP6]], ptr [[TMP8]], i32 [[TMP14]]) // CHECK15-NEXT: ret void // // @@ -4573,29 +4583,31 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 -// CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK15-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 -// CHECK15-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 -// CHECK15-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 -// CHECK15-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 -// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) +// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK15-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// CHECK15-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK15-NEXT: store i32 [[TMP4]], ptr [[T_VAR]], align 4 +// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// CHECK15-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4 +// CHECK15-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 3 +// CHECK15-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4 +// CHECK15-NEXT: store ptr [[TMP8]], ptr [[TMP]], align 4 +// CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK15-NEXT: store i32 [[TMP9]], ptr [[T_VAR_CASTED]], align 4 +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 +// CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[TMP2]], i32 [[TMP10]], ptr [[TMP6]], ptr [[TMP11]]) // CHECK15-NEXT: ret void // // @@ -4616,9 +4628,9 @@ int main() { // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.1], align 4 // CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_1:%.*]], align 4 // CHECK15-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK15-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -4638,8 +4650,8 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK15: omp.arraycpy.body: @@ -4648,8 +4660,8 @@ int main() { // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] // CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) #[[ATTR4]] // CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] -// CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_1]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_1]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK15: omp.arraycpy.done4: @@ -4711,12 +4723,12 @@ int main() { // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 +// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] @@ -4758,9 +4770,9 @@ int main() { // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.1], align 4 // CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_1:%.*]], align 4 // CHECK15-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK15-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -4785,8 +4797,8 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK15: omp.arraycpy.body: @@ -4795,8 +4807,8 @@ int main() { // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] // CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) #[[ATTR4]] // CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] -// CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_1]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_1]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK15: omp.arraycpy.done4: @@ -4840,7 +4852,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK15-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] +// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP19]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -4864,12 +4876,12 @@ int main() { // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 +// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] @@ -4959,9 +4971,9 @@ int main() { // CHECK15-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 // CHECK15-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 -// CHECK15-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 +// CHECK15-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[TMP0]], i32 0, i32 0 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 // CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 @@ -4971,32 +4983,41 @@ int main() { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[G:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[G1:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[G_ADDR]], align 4 -// CHECK17-NEXT: store i32 [[TMP0]], ptr [[G_CASTED]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load volatile i32, ptr [[TMP2]], align 4 -// CHECK17-NEXT: store i32 [[TMP3]], ptr [[G1_CASTED]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[G1_CASTED]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined, i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK17-NEXT: store i32 [[TMP2]], ptr [[G]], align 4 +// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK17-NEXT: store i32 [[TMP4]], ptr [[G1]], align 4 +// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP0]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK17-NEXT: store i32 [[TMP6]], ptr [[SIVAR]], align 4 +// CHECK17-NEXT: store ptr [[G1]], ptr [[TMP]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[G]], align 4 +// CHECK17-NEXT: store i32 [[TMP7]], ptr [[G_CASTED]], align 4 +// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[G_CASTED]], align 8 +// CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK17-NEXT: [[TMP10:%.*]] = load volatile i32, ptr [[TMP9]], align 4 +// CHECK17-NEXT: store i32 [[TMP10]], ptr [[G1_CASTED]], align 4 +// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[G1_CASTED]], align 8 +// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 +// CHECK17-NEXT: store i32 [[TMP12]], ptr [[SIVAR_CASTED]], align 4 +// CHECK17-NEXT: [[TMP13:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined, i64 [[TMP8]], i64 [[TMP11]], i64 [[TMP13]]) // CHECK17-NEXT: ret void // // diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp index 0cc07c86aaea7..3d941b0b05549 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp @@ -2885,10 +2885,13 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 -// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined) // CHECK13-NEXT: ret void // @@ -3133,10 +3136,13 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 -// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined) // CHECK13-NEXT: ret void // @@ -3155,8 +3161,8 @@ int main() { // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.1], align 4 +// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_1:%.*]], align 4 // CHECK13-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -3166,13 +3172,13 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 +// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: @@ -3229,12 +3235,12 @@ int main() { // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i64 2 +// CHECK13-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN4]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] @@ -3268,8 +3274,8 @@ int main() { // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.1], align 4 +// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_1:%.*]], align 4 // CHECK13-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -3287,13 +3293,13 @@ int main() { // CHECK13-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 +// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: @@ -3336,7 +3342,7 @@ int main() { // CHECK13-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false), !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -3360,12 +3366,12 @@ int main() { // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 +// CHECK13-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN8]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] @@ -3411,7 +3417,7 @@ int main() { // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK13-NEXT: ret void @@ -3427,10 +3433,13 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 -// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 // CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined) // CHECK15-NEXT: ret void // @@ -3669,10 +3678,13 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 -// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 // CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined) // CHECK15-NEXT: ret void // @@ -3691,8 +3703,8 @@ int main() { // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.1], align 4 +// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_1:%.*]], align 4 // CHECK15-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -3702,13 +3714,13 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 +// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: @@ -3763,12 +3775,12 @@ int main() { // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i32 2 +// CHECK15-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN4]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] @@ -3802,8 +3814,8 @@ int main() { // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.1], align 4 +// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_1:%.*]], align 4 // CHECK15-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -3819,13 +3831,13 @@ int main() { // CHECK15-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 +// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: @@ -3866,7 +3878,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK15-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i32 0, i32 [[TMP13]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false), !llvm.access.group [[ACC_GRP19]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -3890,12 +3902,12 @@ int main() { // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 +// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] @@ -3941,7 +3953,7 @@ int main() { // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK15-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK15-NEXT: ret void @@ -3957,10 +3969,13 @@ int main() { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined) // CHECK17-NEXT: ret void // diff --git a/clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp index d2a5d1f62a8b9..dd251d083556e 100644 --- a/clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp @@ -9620,25 +9620,34 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK17-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i64 [[TMP4]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4 +// CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2 +// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK17-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK17-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK17-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP8]], i32 [[TMP9]]) +// CHECK17-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK17-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2 +// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i64 [[TMP11]]) // CHECK17-NEXT: ret void // // @@ -9712,17 +9721,22 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK17-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP1]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 2 +// CHECK17-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 +// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP4]]) // CHECK17-NEXT: ret void // // @@ -9801,23 +9815,30 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK17-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK17-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 -// CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK17-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK17-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 +// CHECK17-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4 +// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK17-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2 +// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP6]], i64 [[TMP8]]) // CHECK17-NEXT: ret void // // @@ -9901,41 +9922,38 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 -// CHECK17-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 -// CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK17-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK17-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8 +// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 4 +// CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 5 +// CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8 +// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 6 +// CHECK17-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8 +// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 7 +// CHECK17-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 8 +// CHECK17-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 +// CHECK17-NEXT: [[TMP19:%.*]] = load i32, ptr [[A]], align 4 +// CHECK17-NEXT: store i32 [[TMP19]], ptr [[A_CASTED]], align 4 +// CHECK17-NEXT: [[TMP20:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i64 [[TMP20]], ptr [[TMP4]], i64 [[TMP6]], ptr [[TMP8]], ptr [[TMP10]], i64 [[TMP12]], i64 [[TMP14]], ptr [[TMP16]], ptr [[TMP18]]) // CHECK17-NEXT: ret void // // @@ -10071,38 +10089,48 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK17-NEXT: [[AAA:%.*]] = alloca i8, align 1 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK17-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 -// CHECK17-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 -// CHECK17-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK17-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2 -// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK17-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 -// CHECK17-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 1 -// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP0]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK17-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK17-NEXT: store i32 [[TMP4]], ptr [[N]], align 4 +// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8 +// CHECK17-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2 +// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 2 +// CHECK17-NEXT: store i8 [[TMP8]], ptr [[AAA]], align 1 +// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 4 +// CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[A]], align 4 +// CHECK17-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4 +// CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[N]], align 4 +// CHECK17-NEXT: store i32 [[TMP13]], ptr [[N_CASTED]], align 4 +// CHECK17-NEXT: [[TMP14:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// CHECK17-NEXT: [[TMP15:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK17-NEXT: store i16 [[TMP15]], ptr [[AA_CASTED]], align 2 +// CHECK17-NEXT: [[TMP16:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK17-NEXT: [[TMP17:%.*]] = load i8, ptr [[AAA]], align 1 +// CHECK17-NEXT: store i8 [[TMP17]], ptr [[AAA_CASTED]], align 1 +// CHECK17-NEXT: [[TMP18:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i64 [[TMP12]], i64 [[TMP14]], i64 [[TMP16]], i64 [[TMP18]], ptr [[TMP10]]) // CHECK17-NEXT: ret void // // @@ -10243,29 +10271,30 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK17-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8 +// CHECK17-NEXT: store i32 [[TMP4]], ptr [[B]], align 4 +// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 3 +// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8 +// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 4 +// CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[B]], align 4 +// CHECK17-NEXT: store i32 [[TMP11]], ptr [[B_CASTED]], align 4 +// CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[B_CASTED]], align 8 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[TMP2]], i64 [[TMP12]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP10]]) // CHECK17-NEXT: ret void // // @@ -10365,26 +10394,32 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK17-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]]) +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK17-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK17-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 2 +// CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 +// CHECK17-NEXT: store i32 [[TMP7]], ptr [[A_CASTED]], align 4 +// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK17-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK17-NEXT: store i16 [[TMP9]], ptr [[AA_CASTED]], align 2 +// CHECK17-NEXT: [[TMP10:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i64 [[TMP8]], i64 [[TMP10]], ptr [[TMP6]]) // CHECK17-NEXT: ret void // // @@ -10475,25 +10510,34 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 -// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK19-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i32 [[TMP4]]) +// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4 +// CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2 +// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK19-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK19-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK19-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP8]], i32 [[TMP9]]) +// CHECK19-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK19-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2 +// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i32 [[TMP11]]) // CHECK19-NEXT: ret void // // @@ -10567,17 +10611,22 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK19-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP1]]) +// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 2 +// CHECK19-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP4]]) // CHECK19-NEXT: ret void // // @@ -10656,23 +10705,30 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK19-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP1]], i32 [[TMP3]]) +// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK19-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK19-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK19-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP6]], i32 [[TMP8]]) // CHECK19-NEXT: ret void // // @@ -10756,41 +10812,38 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 -// CHECK19-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]]) +// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK19-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 4 +// CHECK19-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4 +// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 5 +// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 +// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 6 +// CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 +// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 7 +// CHECK19-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 4 +// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 8 +// CHECK19-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 4 +// CHECK19-NEXT: [[TMP19:%.*]] = load i32, ptr [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP19]], ptr [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i32 [[TMP20]], ptr [[TMP4]], i32 [[TMP6]], ptr [[TMP8]], ptr [[TMP10]], i32 [[TMP12]], i32 [[TMP14]], ptr [[TMP16]], ptr [[TMP18]]) // CHECK19-NEXT: ret void // // @@ -10926,38 +10979,48 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 -// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK19-NEXT: [[AAA:%.*]] = alloca i8, align 1 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK19-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 -// CHECK19-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 1 -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP0]]) +// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK19-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK19-NEXT: store i32 [[TMP4]], ptr [[N]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4 +// CHECK19-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2 +// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 2 +// CHECK19-NEXT: store i8 [[TMP8]], ptr [[AAA]], align 1 +// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 4 +// CHECK19-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4 +// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[N]], align 4 +// CHECK19-NEXT: store i32 [[TMP13]], ptr [[N_CASTED]], align 4 +// CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[N_CASTED]], align 4 +// CHECK19-NEXT: [[TMP15:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK19-NEXT: store i16 [[TMP15]], ptr [[AA_CASTED]], align 2 +// CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK19-NEXT: [[TMP17:%.*]] = load i8, ptr [[AAA]], align 1 +// CHECK19-NEXT: store i8 [[TMP17]], ptr [[AAA_CASTED]], align 1 +// CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 +// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i32 [[TMP12]], i32 [[TMP14]], i32 [[TMP16]], i32 [[TMP18]], ptr [[TMP10]]) // CHECK19-NEXT: ret void // // @@ -11098,29 +11161,30 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 -// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]]) +// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK19-NEXT: store i32 [[TMP4]], ptr [[B]], align 4 +// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 3 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 4 +// CHECK19-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4 +// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[B]], align 4 +// CHECK19-NEXT: store i32 [[TMP11]], ptr [[B_CASTED]], align 4 +// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_CASTED]], align 4 +// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[TMP2]], i32 [[TMP12]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP10]]) // CHECK19-NEXT: ret void // // @@ -11220,26 +11284,32 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 -// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]]) +// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK19-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 1 +// CHECK19-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK19-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4 +// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 +// CHECK19-NEXT: store i32 [[TMP7]], ptr [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK19-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK19-NEXT: store i16 [[TMP9]], ptr [[AA_CASTED]], align 2 +// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i32 [[TMP8]], i32 [[TMP10]], ptr [[TMP6]]) // CHECK19-NEXT: ret void // // @@ -11330,25 +11400,34 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 -// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK21-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK21-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK21-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK21-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK21-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i64 [[TMP4]]) +// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK21-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4 +// CHECK21-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2 +// CHECK21-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 1 +// CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK21-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK21-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 2 +// CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK21-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK21-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP8]], i32 [[TMP9]]) +// CHECK21-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK21-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2 +// CHECK21-NEXT: [[TMP11:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i64 [[TMP11]]) // CHECK21-NEXT: ret void // // @@ -11422,17 +11501,22 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK21-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK21-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 -// CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP1]]) +// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK21-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 2 +// CHECK21-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// CHECK21-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK21-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 +// CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP4]]) // CHECK21-NEXT: ret void // // @@ -11511,23 +11595,30 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 +// CHECK21-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK21-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK21-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 -// CHECK21-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) +// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK21-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK21-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK21-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 +// CHECK21-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4 +// CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK21-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK21-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2 +// CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP6]], i64 [[TMP8]]) // CHECK21-NEXT: ret void // // @@ -11611,41 +11702,38 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 +// CHECK21-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 -// CHECK21-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 -// CHECK21-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 -// CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 -// CHECK21-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 -// CHECK21-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 -// CHECK21-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]]) +// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK21-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 1 +// CHECK21-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// CHECK21-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 2 +// CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8 +// CHECK21-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 3 +// CHECK21-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8 +// CHECK21-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 4 +// CHECK21-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK21-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 5 +// CHECK21-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8 +// CHECK21-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 6 +// CHECK21-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8 +// CHECK21-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 7 +// CHECK21-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK21-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 8 +// CHECK21-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 +// CHECK21-NEXT: [[TMP19:%.*]] = load i32, ptr [[A]], align 4 +// CHECK21-NEXT: store i32 [[TMP19]], ptr [[A_CASTED]], align 4 +// CHECK21-NEXT: [[TMP20:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i64 [[TMP20]], ptr [[TMP4]], i64 [[TMP6]], ptr [[TMP8]], ptr [[TMP10]], i64 [[TMP12]], i64 [[TMP14]], ptr [[TMP16]], ptr [[TMP18]]) // CHECK21-NEXT: ret void // // @@ -11781,38 +11869,48 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 -// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// CHECK21-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK21-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK21-NEXT: [[AAA:%.*]] = alloca i8, align 1 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 -// CHECK21-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK21-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2 -// CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK21-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 -// CHECK21-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 1 -// CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 -// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP0]]) +// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK21-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 1 +// CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK21-NEXT: store i32 [[TMP4]], ptr [[N]], align 4 +// CHECK21-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 2 +// CHECK21-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8 +// CHECK21-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2 +// CHECK21-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 3 +// CHECK21-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 2 +// CHECK21-NEXT: store i8 [[TMP8]], ptr [[AAA]], align 1 +// CHECK21-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 4 +// CHECK21-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[A]], align 4 +// CHECK21-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4 +// CHECK21-NEXT: [[TMP12:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[N]], align 4 +// CHECK21-NEXT: store i32 [[TMP13]], ptr [[N_CASTED]], align 4 +// CHECK21-NEXT: [[TMP14:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// CHECK21-NEXT: [[TMP15:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK21-NEXT: store i16 [[TMP15]], ptr [[AA_CASTED]], align 2 +// CHECK21-NEXT: [[TMP16:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK21-NEXT: [[TMP17:%.*]] = load i8, ptr [[AAA]], align 1 +// CHECK21-NEXT: store i8 [[TMP17]], ptr [[AAA_CASTED]], align 1 +// CHECK21-NEXT: [[TMP18:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 +// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i64 [[TMP12]], i64 [[TMP14]], i64 [[TMP16]], i64 [[TMP18]], ptr [[TMP10]]) // CHECK21-NEXT: ret void // // @@ -11953,37 +12051,42 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 -// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK21-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK21-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK21-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 -// CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 -// CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8 -// CHECK21-NEXT: [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 -// CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 +// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 1 +// CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8 +// CHECK21-NEXT: store i32 [[TMP4]], ptr [[B]], align 4 +// CHECK21-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 3 +// CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8 +// CHECK21-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 4 +// CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8 +// CHECK21-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 5 +// CHECK21-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK21-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 6 +// CHECK21-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 8 +// CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP12]] to i1 // CHECK21-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK21-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 -// CHECK21-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 -// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]], i64 [[TMP7]]) +// CHECK21-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[B]], align 4 +// CHECK21-NEXT: store i32 [[TMP13]], ptr [[B_CASTED]], align 4 +// CHECK21-NEXT: [[TMP14:%.*]] = load i64, ptr [[B_CASTED]], align 8 +// CHECK21-NEXT: [[TMP15:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK21-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP15]] to i1 +// CHECK21-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL1]] to i8 +// CHECK21-NEXT: store i8 [[FROMBOOL2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 +// CHECK21-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[TMP2]], i64 [[TMP14]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP10]], i64 [[TMP16]]) // CHECK21-NEXT: ret void // // @@ -12127,26 +12230,32 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 -// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// CHECK21-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK21-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK21-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 -// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]]) +// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_6:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK21-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], ptr [[TMP0]], i32 0, i32 1 +// CHECK21-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK21-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK21-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], ptr [[TMP0]], i32 0, i32 2 +// CHECK21-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 +// CHECK21-NEXT: store i32 [[TMP7]], ptr [[A_CASTED]], align 4 +// CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK21-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK21-NEXT: store i16 [[TMP9]], ptr [[AA_CASTED]], align 2 +// CHECK21-NEXT: [[TMP10:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i64 [[TMP8]], i64 [[TMP10]], ptr [[TMP6]]) // CHECK21-NEXT: ret void // // @@ -12237,25 +12346,34 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 -// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK23-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK23-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK23-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK23-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK23-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i32 [[TMP4]]) +// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK23-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4 +// CHECK23-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2 +// CHECK23-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 1 +// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK23-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK23-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 2 +// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK23-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK23-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP8]], i32 [[TMP9]]) +// CHECK23-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK23-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2 +// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i32 [[TMP11]]) // CHECK23-NEXT: ret void // // @@ -12329,17 +12447,22 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK23-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK23-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP1]]) +// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK23-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 2 +// CHECK23-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2 +// CHECK23-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK23-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 +// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP4]]) // CHECK23-NEXT: ret void // // @@ -12418,23 +12541,30 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 +// CHECK23-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK23-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP1]], i32 [[TMP3]]) +// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK23-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK23-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK23-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 +// CHECK23-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4 +// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK23-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK23-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2 +// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP6]], i32 [[TMP8]]) // CHECK23-NEXT: ret void // // @@ -12518,41 +12648,38 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 +// CHECK23-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 -// CHECK23-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 -// CHECK23-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 -// CHECK23-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 -// CHECK23-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 -// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]]) +// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK23-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 1 +// CHECK23-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4 +// CHECK23-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 2 +// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK23-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 3 +// CHECK23-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4 +// CHECK23-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 4 +// CHECK23-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4 +// CHECK23-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 5 +// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 +// CHECK23-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 6 +// CHECK23-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 +// CHECK23-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 7 +// CHECK23-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 4 +// CHECK23-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], ptr [[TMP0]], i32 0, i32 8 +// CHECK23-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 4 +// CHECK23-NEXT: [[TMP19:%.*]] = load i32, ptr [[A]], align 4 +// CHECK23-NEXT: store i32 [[TMP19]], ptr [[A_CASTED]], align 4 +// CHECK23-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i32 [[TMP20]], ptr [[TMP4]], i32 [[TMP6]], ptr [[TMP8]], ptr [[TMP10]], i32 [[TMP12]], i32 [[TMP14]], ptr [[TMP16]], ptr [[TMP18]]) // CHECK23-NEXT: ret void // // @@ -12688,38 +12815,48 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 -// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 +// CHECK23-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK23-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 +// CHECK23-NEXT: [[AAA:%.*]] = alloca i8, align 1 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4 -// CHECK23-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK23-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK23-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 -// CHECK23-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 1 -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 -// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP0]]) +// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK23-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 1 +// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK23-NEXT: store i32 [[TMP4]], ptr [[N]], align 4 +// CHECK23-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 2 +// CHECK23-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4 +// CHECK23-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2 +// CHECK23-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 3 +// CHECK23-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 2 +// CHECK23-NEXT: store i8 [[TMP8]], ptr [[AAA]], align 1 +// CHECK23-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], ptr [[TMP0]], i32 0, i32 4 +// CHECK23-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4 +// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[A]], align 4 +// CHECK23-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4 +// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[N]], align 4 +// CHECK23-NEXT: store i32 [[TMP13]], ptr [[N_CASTED]], align 4 +// CHECK23-NEXT: [[TMP14:%.*]] = load i32, ptr [[N_CASTED]], align 4 +// CHECK23-NEXT: [[TMP15:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK23-NEXT: store i16 [[TMP15]], ptr [[AA_CASTED]], align 2 +// CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK23-NEXT: [[TMP17:%.*]] = load i8, ptr [[AAA]], align 1 +// CHECK23-NEXT: store i8 [[TMP17]], ptr [[AAA_CASTED]], align 1 +// CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 +// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i32 [[TMP12]], i32 [[TMP14]], i32 [[TMP16]], i32 [[TMP18]], ptr [[TMP10]]) // CHECK23-NEXT: ret void // // @@ -12860,37 +12997,42 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 -// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK23-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK23-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK23-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 -// CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 -// CHECK23-NEXT: [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 -// CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 +// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 1 +// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK23-NEXT: store i32 [[TMP4]], ptr [[B]], align 4 +// CHECK23-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 2 +// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK23-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 3 +// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 +// CHECK23-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 4 +// CHECK23-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4 +// CHECK23-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP0]], i32 0, i32 5 +// CHECK23-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 4 +// CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP12]] to i1 // CHECK23-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK23-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 -// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]], i32 [[TMP7]]) +// CHECK23-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[B]], align 4 +// CHECK23-NEXT: store i32 [[TMP13]], ptr [[B_CASTED]], align 4 +// CHECK23-NEXT: [[TMP14:%.*]] = load i32, ptr [[B_CASTED]], align 4 +// CHECK23-NEXT: [[TMP15:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK23-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP15]] to i1 +// CHECK23-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL1]] to i8 +// CHECK23-NEXT: store i8 [[FROMBOOL2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 +// CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[TMP2]], i32 [[TMP14]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP10]], i32 [[TMP16]]) // CHECK23-NEXT: ret void // // @@ -13034,26 +13176,32 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 -// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 +// CHECK23-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 -// CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 -// CHECK23-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 -// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]]) +// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_6:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK23-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 +// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], ptr [[TMP0]], i32 0, i32 1 +// CHECK23-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4 +// CHECK23-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2 +// CHECK23-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], ptr [[TMP0]], i32 0, i32 2 +// CHECK23-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4 +// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 +// CHECK23-NEXT: store i32 [[TMP7]], ptr [[A_CASTED]], align 4 +// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK23-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK23-NEXT: store i16 [[TMP9]], ptr [[AA_CASTED]], align 2 +// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i32 [[TMP8]], i32 [[TMP10]], ptr [[TMP6]]) // CHECK23-NEXT: ret void // // diff --git a/clang/test/OpenMP/target_teams_generic_loop_codegen-1.cpp b/clang/test/OpenMP/target_teams_generic_loop_codegen-1.cpp index ec806081a3e44..f23875c1f4feb 100644 --- a/clang/test/OpenMP/target_teams_generic_loop_codegen-1.cpp +++ b/clang/test/OpenMP/target_teams_generic_loop_codegen-1.cpp @@ -1790,28 +1790,36 @@ int target_teams_fun(int *g){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 -// CHECK10-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK10-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]) // CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 -// CHECK10-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK10-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i64, ptr [[N_CASTED]], align 8 -// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.omp_outlined, i64 [[TMP5]], ptr [[TMP1]]) +// CHECK10-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8 +// CHECK10-NEXT: store i32 [[TMP3]], ptr [[N]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 +// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8 +// CHECK10-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 3 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 +// CHECK10-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK10-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP10]], i32 [[TMP11]]) +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, ptr [[N]], align 4 +// CHECK10-NEXT: store i32 [[TMP12]], ptr [[N_CASTED]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.omp_outlined, i64 [[TMP13]], ptr [[TMP5]]) // CHECK10-NEXT: ret void // // @@ -2008,23 +2016,26 @@ int target_teams_fun(int *g){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l57 -// CHECK10-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK10-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 8 +// CHECK10-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK10-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 -// CHECK10-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK10-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, ptr [[N_CASTED]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[G_ADDR]], align 8 -// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l57.omp_outlined, i64 [[TMP2]], ptr [[TMP0]], ptr [[TMP3]]) +// CHECK10-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK10-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8 +// CHECK10-NEXT: store i32 [[TMP2]], ptr [[N]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// CHECK10-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4 +// CHECK10-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l57.omp_outlined, i64 [[TMP7]], ptr [[TMP4]], ptr [[TMP8]]) // CHECK10-NEXT: ret void // // @@ -2229,28 +2240,36 @@ int target_teams_fun(int *g){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 -// CHECK12-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]) // CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 -// CHECK12-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK12-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4 -// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.omp_outlined, i32 [[TMP5]], ptr [[TMP1]]) +// CHECK12-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK12-NEXT: store i32 [[TMP3]], ptr [[N]], align 4 +// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK12-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 3 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 +// CHECK12-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK12-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP10]], i32 [[TMP11]]) +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, ptr [[N]], align 4 +// CHECK12-NEXT: store i32 [[TMP12]], ptr [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, ptr [[N_CASTED]], align 4 +// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.omp_outlined, i32 [[TMP13]], ptr [[TMP5]]) // CHECK12-NEXT: ret void // // @@ -2442,23 +2461,26 @@ int target_teams_fun(int *g){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l57 -// CHECK12-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK12-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4 +// CHECK12-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 -// CHECK12-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 -// CHECK12-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_CASTED]], align 4 -// CHECK12-NEXT: [[TMP3:%.*]] = load ptr, ptr [[G_ADDR]], align 4 -// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l57.omp_outlined, i32 [[TMP2]], ptr [[TMP0]], ptr [[TMP3]]) +// CHECK12-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK12-NEXT: store i32 [[TMP2]], ptr [[N]], align 4 +// CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// CHECK12-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4 +// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 2 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4 +// CHECK12-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP5]], align 4 +// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l57.omp_outlined, i32 [[TMP7]], ptr [[TMP4]], ptr [[TMP8]]) // CHECK12-NEXT: ret void // // diff --git a/clang/test/OpenMP/target_teams_generic_loop_private_codegen.cpp b/clang/test/OpenMP/target_teams_generic_loop_private_codegen.cpp index 9b3d77f5b0adc..24ebaaa9355cb 100644 --- a/clang/test/OpenMP/target_teams_generic_loop_private_codegen.cpp +++ b/clang/test/OpenMP/target_teams_generic_loop_private_codegen.cpp @@ -1452,10 +1452,13 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 -// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined) // CHECK13-NEXT: ret void // @@ -1585,10 +1588,13 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 -// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined) // CHECK13-NEXT: ret void // @@ -1607,8 +1613,8 @@ int main() { // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.1], align 4 +// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_1:%.*]], align 4 // CHECK13-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1618,13 +1624,13 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 +// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: @@ -1667,7 +1673,7 @@ int main() { // CHECK13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -1684,12 +1690,12 @@ int main() { // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 +// CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] @@ -1745,7 +1751,7 @@ int main() { // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK13-NEXT: ret void @@ -1761,10 +1767,13 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 -// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 // CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined) // CHECK15-NEXT: ret void // @@ -1892,10 +1901,13 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 -// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 // CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined) // CHECK15-NEXT: ret void // @@ -1914,8 +1926,8 @@ int main() { // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.1], align 4 +// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_1:%.*]], align 4 // CHECK15-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1925,13 +1937,13 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 +// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: @@ -1972,7 +1984,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK15-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i32 0, i32 [[TMP11]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false) // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -1989,12 +2001,12 @@ int main() { // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 +// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.1], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] @@ -2050,7 +2062,7 @@ int main() { // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK15-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK15-NEXT: ret void @@ -2066,10 +2078,13 @@ int main() { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 -// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined) // CHECK17-NEXT: ret void // diff --git a/clang/test/OpenMP/target_teams_map_codegen.cpp b/clang/test/OpenMP/target_teams_map_codegen.cpp index 974ba36e6bb0d..b8ce1f20b7a1c 100644 --- a/clang/test/OpenMP/target_teams_map_codegen.cpp +++ b/clang/test/OpenMP/target_teams_map_codegen.cpp @@ -2224,10 +2224,13 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27 -// CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27.omp_outlined) // CHECK5-NEXT: ret void // @@ -2245,25 +2248,26 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33 -// CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK5-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8 -// CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 +// CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[Y_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK5-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8 -// CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK5-NEXT: store i32 [[TMP2]], ptr [[X_CASTED]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[X_CASTED]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK5-NEXT: store i32 [[TMP4]], ptr [[Y_CASTED]], align 4 -// CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[Y_CASTED]], align 8 -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33.omp_outlined, i64 [[TMP3]], i64 [[TMP5]]) +// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK5-NEXT: store i32 [[TMP5]], ptr [[X_CASTED]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[X_CASTED]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK5-NEXT: store i32 [[TMP7]], ptr [[Y_CASTED]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[Y_CASTED]], align 8 +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33.omp_outlined, i64 [[TMP6]], i64 [[TMP8]]) // CHECK5-NEXT: ret void // // @@ -2282,17 +2286,18 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39 -// CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK5-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8 -// CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 +// CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK5-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8 -// CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]) +// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined, ptr [[TMP2]], ptr [[TMP4]]) // CHECK5-NEXT: ret void // // @@ -2376,18 +2381,20 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45 -// CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK5-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8 +// CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK5-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK5-NEXT: store i32 [[TMP1]], ptr [[X_CASTED]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[X_CASTED]], align 8 -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45.omp_outlined, i64 [[TMP2]]) +// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK5-NEXT: store i32 [[TMP3]], ptr [[X_CASTED]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[X_CASTED]], align 8 +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45.omp_outlined, i64 [[TMP4]]) // CHECK5-NEXT: ret void // // @@ -2404,18 +2411,20 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51 -// CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK5-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8 +// CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK5-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK5-NEXT: store i32 [[TMP1]], ptr [[X_CASTED]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[X_CASTED]], align 8 -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51.omp_outlined, i64 [[TMP2]]) +// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK5-NEXT: store i32 [[TMP3]], ptr [[X_CASTED]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[X_CASTED]], align 8 +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51.omp_outlined, i64 [[TMP4]]) // CHECK5-NEXT: ret void // // @@ -2432,18 +2441,20 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57 -// CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK5-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8 +// CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK5-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK5-NEXT: store i32 [[TMP1]], ptr [[X_CASTED]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[X_CASTED]], align 8 -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57.omp_outlined, i64 [[TMP2]]) +// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK5-NEXT: store i32 [[TMP3]], ptr [[X_CASTED]], align 4 +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[X_CASTED]], align 8 +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57.omp_outlined, i64 [[TMP4]]) // CHECK5-NEXT: ret void // // @@ -2460,17 +2471,18 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63 -// CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], ptr noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 -// CHECK5-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8 +// CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 -// CHECK5-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8 -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]) +// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined, ptr [[TMP2]], ptr [[TMP4]]) // CHECK5-NEXT: ret void // // @@ -2582,17 +2594,18 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65 -// CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], ptr noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 -// CHECK5-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8 +// CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 -// CHECK5-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8 -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]) +// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_6:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], ptr [[TMP0]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined, ptr [[TMP2]], ptr [[TMP4]]) // CHECK5-NEXT: ret void // // @@ -2704,17 +2717,18 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72 -// CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], ptr noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 -// CHECK5-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8 +// CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 -// CHECK5-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8 -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]) +// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_7:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], ptr [[TMP0]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72.omp_outlined, ptr [[TMP2]], ptr [[TMP4]]) // CHECK5-NEXT: ret void // // @@ -2798,17 +2812,18 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74 -// CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], ptr noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 -// CHECK5-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8 +// CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 -// CHECK5-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8 -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]) +// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_8:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_8]], ptr [[TMP0]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74.omp_outlined, ptr [[TMP2]], ptr [[TMP4]]) // CHECK5-NEXT: ret void // // @@ -2892,10 +2907,13 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27 -// CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK7-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// CHECK7-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27.omp_outlined) // CHECK7-NEXT: ret void // @@ -2913,25 +2931,26 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33 -// CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK7-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 4 -// CHECK7-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 4 +// CHECK7-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[Y_CASTED:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK7-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4 -// CHECK7-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Y_ADDR]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK7-NEXT: store i32 [[TMP2]], ptr [[X_CASTED]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[X_CASTED]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK7-NEXT: store i32 [[TMP4]], ptr [[Y_CASTED]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[Y_CASTED]], align 4 -// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33.omp_outlined, i32 [[TMP3]], i32 [[TMP5]]) +// CHECK7-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP0]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK7-NEXT: store i32 [[TMP5]], ptr [[X_CASTED]], align 4 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[X_CASTED]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK7-NEXT: store i32 [[TMP7]], ptr [[Y_CASTED]], align 4 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[Y_CASTED]], align 4 +// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33.omp_outlined, i32 [[TMP6]], i32 [[TMP8]]) // CHECK7-NEXT: ret void // // @@ -2950,17 +2969,18 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39 -// CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK7-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 4 -// CHECK7-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 4 +// CHECK7-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK7-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4 -// CHECK7-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Y_ADDR]], align 4 -// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]) +// CHECK7-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP0]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4 +// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined, ptr [[TMP2]], ptr [[TMP4]]) // CHECK7-NEXT: ret void // // @@ -3044,18 +3064,20 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45 -// CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK7-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 4 +// CHECK7-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK7-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK7-NEXT: store i32 [[TMP1]], ptr [[X_CASTED]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[X_CASTED]], align 4 -// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45.omp_outlined, i32 [[TMP2]]) +// CHECK7-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], ptr [[X_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[X_CASTED]], align 4 +// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45.omp_outlined, i32 [[TMP4]]) // CHECK7-NEXT: ret void // // @@ -3072,18 +3094,20 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51 -// CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK7-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 4 +// CHECK7-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK7-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK7-NEXT: store i32 [[TMP1]], ptr [[X_CASTED]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[X_CASTED]], align 4 -// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51.omp_outlined, i32 [[TMP2]]) +// CHECK7-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], ptr [[X_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[X_CASTED]], align 4 +// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51.omp_outlined, i32 [[TMP4]]) // CHECK7-NEXT: ret void // // @@ -3100,18 +3124,20 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57 -// CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK7-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 4 +// CHECK7-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK7-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK7-NEXT: store i32 [[TMP1]], ptr [[X_CASTED]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[X_CASTED]], align 4 -// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57.omp_outlined, i32 [[TMP2]]) +// CHECK7-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK7-NEXT: store i32 [[TMP3]], ptr [[X_CASTED]], align 4 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[X_CASTED]], align 4 +// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57.omp_outlined, i32 [[TMP4]]) // CHECK7-NEXT: ret void // // @@ -3128,17 +3154,18 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63 -// CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], ptr noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK7-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 4 -// CHECK7-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 4 +// CHECK7-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK7-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 4 -// CHECK7-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 4 -// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]) +// CHECK7-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], ptr [[TMP0]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4 +// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined, ptr [[TMP2]], ptr [[TMP4]]) // CHECK7-NEXT: ret void // // @@ -3250,17 +3277,18 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65 -// CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], ptr noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK7-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 4 -// CHECK7-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 4 +// CHECK7-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK7-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 4 -// CHECK7-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 4 -// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]) +// CHECK7-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_6:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], ptr [[TMP0]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4 +// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined, ptr [[TMP2]], ptr [[TMP4]]) // CHECK7-NEXT: ret void // // diff --git a/clang/test/OpenMP/target_teams_num_teams_codegen.cpp b/clang/test/OpenMP/target_teams_num_teams_codegen.cpp index ba01a411670ce..f87a03f354c13 100644 --- a/clang/test/OpenMP/target_teams_num_teams_codegen.cpp +++ b/clang/test/OpenMP/target_teams_num_teams_codegen.cpp @@ -1331,15 +1331,20 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 0) // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined) // CHECK9-NEXT: ret void // @@ -1355,15 +1360,20 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 0) // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined) // CHECK9-NEXT: ret void // @@ -1379,25 +1389,31 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP3]], ptr [[B_CASTED]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[B_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP1]], i64 [[TMP4]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8 +// CHECK9-NEXT: store i32 [[TMP5]], ptr [[B]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP1]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK9-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP8]], i32 0) +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4 +// CHECK9-NEXT: store i32 [[TMP9]], ptr [[B_CASTED]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[B_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP3]], i64 [[TMP10]]) // CHECK9-NEXT: ret void // // @@ -1422,16 +1438,18 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 // CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[TMP1]]) +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[TMP3]]) // CHECK9-NEXT: ret void // // @@ -1451,11 +1469,14 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 // CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.omp_outlined) // CHECK9-NEXT: ret void @@ -1472,29 +1493,38 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR__ADDR]], align 2 -// CHECK9-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[B_ADDR]], align 2 -// CHECK9-NEXT: store i16 [[TMP5]], ptr [[B_CASTED]], align 2 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP4]], i64 [[TMP6]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 4 +// CHECK9-NEXT: store i16 [[TMP5]], ptr [[B]], align 2 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP1]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 2 +// CHECK9-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2 +// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2 +// CHECK9-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP9]], i32 0) +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2 +// CHECK9-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2 +// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[B_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP11]], i64 [[TMP13]]) // CHECK9-NEXT: ret void // // @@ -1518,15 +1548,20 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 0) // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined) // CHECK11-NEXT: ret void // @@ -1542,15 +1577,20 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 0) // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined) // CHECK11-NEXT: ret void // @@ -1566,25 +1606,31 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], ptr [[B_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP1]], i32 [[TMP4]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP1]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], ptr [[B]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP1]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP8]], i32 0) +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4 +// CHECK11-NEXT: store i32 [[TMP9]], ptr [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[B_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP3]], i32 [[TMP10]]) // CHECK11-NEXT: ret void // // @@ -1609,16 +1655,18 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4 // CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[TMP1]]) +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[TMP3]]) // CHECK11-NEXT: ret void // // @@ -1638,11 +1686,14 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 // CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.omp_outlined) // CHECK11-NEXT: ret void @@ -1659,29 +1710,38 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR__ADDR]], align 2 -// CHECK11-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[B_ADDR]], align 2 -// CHECK11-NEXT: store i16 [[TMP5]], ptr [[B_CASTED]], align 2 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP4]], i32 [[TMP6]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP1]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 4 +// CHECK11-NEXT: store i16 [[TMP5]], ptr [[B]], align 2 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP1]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 2 +// CHECK11-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2 +// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2 +// CHECK11-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP9]], i32 0) +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2 +// CHECK11-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP11]], i32 [[TMP13]]) // CHECK11-NEXT: ret void // // diff --git a/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp b/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp index c081f6e52d7af..4feca0f936561 100644 --- a/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp +++ b/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp @@ -1369,18 +1369,25 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP6]], i32 [[TMP7]]) // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined) // CHECK9-NEXT: ret void // @@ -1396,15 +1403,20 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP4]]) // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined) // CHECK9-NEXT: ret void // @@ -1420,25 +1432,31 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP3]], ptr [[B_CASTED]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[B_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP1]], i64 [[TMP4]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8 +// CHECK9-NEXT: store i32 [[TMP5]], ptr [[B]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP1]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK9-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP8]]) +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4 +// CHECK9-NEXT: store i32 [[TMP9]], ptr [[B_CASTED]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[B_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP3]], i64 [[TMP10]]) // CHECK9-NEXT: ret void // // @@ -1463,16 +1481,18 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 // CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[TMP1]]) +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[TMP3]]) // CHECK9-NEXT: ret void // // @@ -1492,11 +1512,14 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 // CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.omp_outlined) // CHECK9-NEXT: ret void @@ -1513,29 +1536,38 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR__ADDR]], align 2 -// CHECK9-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[B_ADDR]], align 2 -// CHECK9-NEXT: store i16 [[TMP5]], ptr [[B_CASTED]], align 2 -// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP4]], i64 [[TMP6]]) +// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 4 +// CHECK9-NEXT: store i16 [[TMP5]], ptr [[B]], align 2 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP1]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 2 +// CHECK9-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2 +// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2 +// CHECK9-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP9]], i32 1024) +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4 +// CHECK9-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2 +// CHECK9-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2 +// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[B_CASTED]], align 8 +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP11]], i64 [[TMP13]]) // CHECK9-NEXT: ret void // // @@ -1559,18 +1591,25 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 -// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP6]], i32 [[TMP7]]) // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined) // CHECK11-NEXT: ret void // @@ -1586,15 +1625,20 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP4]]) // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined) // CHECK11-NEXT: ret void // @@ -1610,25 +1654,31 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], ptr [[B_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP1]], i32 [[TMP4]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP1]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK11-NEXT: store i32 [[TMP5]], ptr [[B]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP1]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK11-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP8]]) +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4 +// CHECK11-NEXT: store i32 [[TMP9]], ptr [[B_CASTED]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[B_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP3]], i32 [[TMP10]]) // CHECK11-NEXT: ret void // // @@ -1653,16 +1703,18 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4 // CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024) -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[TMP1]]) +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[TMP3]]) // CHECK11-NEXT: ret void // // @@ -1682,11 +1734,14 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 // CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20) // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.omp_outlined) // CHECK11-NEXT: ret void @@ -1703,29 +1758,38 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[B:%.*]] = alloca i16, align 2 +// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR__ADDR]], align 2 -// CHECK11-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[B_ADDR]], align 2 -// CHECK11-NEXT: store i16 [[TMP5]], ptr [[B_CASTED]], align 2 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP4]], i32 [[TMP6]]) +// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP1]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 4 +// CHECK11-NEXT: store i16 [[TMP5]], ptr [[B]], align 2 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], ptr [[TMP1]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 2 +// CHECK11-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2 +// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2 +// CHECK11-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32 +// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP9]], i32 1024) +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4 +// CHECK11-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2 +// CHECK11-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_CASTED]], align 4 +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP11]], i32 [[TMP13]]) // CHECK11-NEXT: ret void // // diff --git a/clang/test/OpenMP/teams_codegen.cpp b/clang/test/OpenMP/teams_codegen.cpp index 91702fb47af73..b2ed0372e31ae 100644 --- a/clang/test/OpenMP/teams_codegen.cpp +++ b/clang/test/OpenMP/teams_codegen.cpp @@ -2371,13 +2371,18 @@ void foo() { // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216 -// CHECK25-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK25-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 +// CHECK25-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK25-NEXT: [[ARGC:%.*]] = alloca i32, align 4 // CHECK25-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 8 -// CHECK25-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216.omp_outlined, ptr [[ARGC_ADDR]]) +// CHECK25-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK25-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK25-NEXT: store i32 [[TMP2]], ptr [[ARGC]], align 4 +// CHECK25-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216.omp_outlined, ptr [[ARGC]]) // CHECK25-NEXT: ret void // // @@ -2396,13 +2401,15 @@ void foo() { // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209 -// CHECK25-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8 +// CHECK25-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 // CHECK25-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK25-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8 -// CHECK25-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209.omp_outlined, ptr [[ARGC_ADDR]]) +// CHECK25-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK25-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK25-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK25-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209.omp_outlined, ptr [[TMP1]]) // CHECK25-NEXT: ret void // // @@ -2421,13 +2428,18 @@ void foo() { // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216 -// CHECK27-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK27-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK27-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK27-NEXT: [[ARGC:%.*]] = alloca i32, align 4 // CHECK27-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 -// CHECK27-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216.omp_outlined, ptr [[ARGC_ADDR]]) +// CHECK27-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK27-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK27-NEXT: store i32 [[TMP2]], ptr [[ARGC]], align 4 +// CHECK27-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216.omp_outlined, ptr [[ARGC]]) // CHECK27-NEXT: ret void // // @@ -2446,13 +2458,15 @@ void foo() { // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209 -// CHECK27-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 4 +// CHECK27-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 // CHECK27-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK27-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 4 -// CHECK27-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209.omp_outlined, ptr [[ARGC_ADDR]]) +// CHECK27-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK27-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK27-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK27-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209.omp_outlined, ptr [[TMP1]]) // CHECK27-NEXT: ret void // // @@ -2471,21 +2485,30 @@ void foo() { // // // CHECK33-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265 -// CHECK33-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK33-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK33-NEXT: entry: // CHECK33-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK33-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK33-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK33-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 +// CHECK33-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK33-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK33-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK33-NEXT: [[ARGC:%.*]] = alloca i32, align 4 // CHECK33-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK33-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK33-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK33-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 -// CHECK33-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 8 -// CHECK33-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK33-NEXT: [[TMP2:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK33-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK33-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265.omp_outlined, ptr [[ARGC_ADDR]]) +// CHECK33-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK33-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK33-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK33-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK33-NEXT: store i32 [[TMP3]], ptr [[A]], align 4 +// CHECK33-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 1 +// CHECK33-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK33-NEXT: store i32 [[TMP5]], ptr [[B]], align 4 +// CHECK33-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 2 +// CHECK33-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK33-NEXT: store i32 [[TMP7]], ptr [[ARGC]], align 4 +// CHECK33-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 +// CHECK33-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4 +// CHECK33-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP8]], i32 [[TMP9]]) +// CHECK33-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265.omp_outlined, ptr [[ARGC]]) // CHECK33-NEXT: ret void // // @@ -2504,21 +2527,27 @@ void foo() { // // // CHECK33-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254 -// CHECK33-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], ptr noundef [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK33-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK33-NEXT: entry: // CHECK33-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK33-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK33-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 -// CHECK33-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8 +// CHECK33-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8 +// CHECK33-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK33-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK33-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK33-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK33-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK33-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 -// CHECK33-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8 -// CHECK33-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK33-NEXT: [[TMP2:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK33-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK33-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254.omp_outlined, ptr [[ARGC_ADDR]]) +// CHECK33-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 +// CHECK33-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 +// CHECK33-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK33-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8 +// CHECK33-NEXT: store i32 [[TMP3]], ptr [[A]], align 4 +// CHECK33-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP1]], i32 0, i32 1 +// CHECK33-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK33-NEXT: store i32 [[TMP5]], ptr [[B]], align 4 +// CHECK33-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP1]], i32 0, i32 2 +// CHECK33-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 +// CHECK33-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4 +// CHECK33-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP7]], i32 [[TMP8]]) +// CHECK33-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254.omp_outlined, ptr [[TMP6]]) // CHECK33-NEXT: ret void // // @@ -2537,21 +2566,30 @@ void foo() { // // // CHECK35-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265 -// CHECK35-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK35-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK35-NEXT: entry: // CHECK35-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK35-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK35-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK35-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 +// CHECK35-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK35-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK35-NEXT: [[B:%.*]] = alloca i32, align 4 +// CHECK35-NEXT: [[ARGC:%.*]] = alloca i32, align 4 // CHECK35-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK35-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK35-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK35-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 -// CHECK35-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 -// CHECK35-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK35-NEXT: [[TMP2:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK35-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK35-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265.omp_outlined, ptr [[ARGC_ADDR]]) +// CHECK35-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK35-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK35-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK35-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK35-NEXT: store i32 [[TMP3]], ptr [[A]], align 4 +// CHECK35-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 1 +// CHECK35-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK35-NEXT: store i32 [[TMP5]], ptr [[B]], align 4 +// CHECK35-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP1]], i32 0, i32 2 +// CHECK35-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK35-NEXT: store i32 [[TMP7]], ptr [[ARGC]], align 4 +// CHECK35-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 +// CHECK35-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4 +// CHECK35-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP8]], i32 [[TMP9]]) +// CHECK35-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265.omp_outlined, ptr [[ARGC]]) // CHECK35-NEXT: ret void // // @@ -2570,21 +2608,27 @@ void foo() { // // // CHECK35-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254 -// CHECK35-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], ptr noundef [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK35-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] { // CHECK35-NEXT: entry: // CHECK35-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK35-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK35-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK35-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 4 +// CHECK35-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4 +// CHECK35-NEXT: [[A:%.*]] = alloca i32, align 4 +// CHECK35-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK35-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK35-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK35-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK35-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 -// CHECK35-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 4 -// CHECK35-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK35-NEXT: [[TMP2:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK35-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) -// CHECK35-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254.omp_outlined, ptr [[ARGC_ADDR]]) +// CHECK35-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4 +// CHECK35-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4 +// CHECK35-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK35-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK35-NEXT: store i32 [[TMP3]], ptr [[A]], align 4 +// CHECK35-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP1]], i32 0, i32 1 +// CHECK35-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK35-NEXT: store i32 [[TMP5]], ptr [[B]], align 4 +// CHECK35-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], ptr [[TMP1]], i32 0, i32 2 +// CHECK35-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 +// CHECK35-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4 +// CHECK35-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP7]], i32 [[TMP8]]) +// CHECK35-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254.omp_outlined, ptr [[TMP6]]) // CHECK35-NEXT: ret void // // diff --git a/offload/plugins-nextgen/common/include/PluginInterface.h b/offload/plugins-nextgen/common/include/PluginInterface.h index eda6a4fd541e9..57f9966fba636 100644 --- a/offload/plugins-nextgen/common/include/PluginInterface.h +++ b/offload/plugins-nextgen/common/include/PluginInterface.h @@ -271,6 +271,10 @@ struct GenericKernelTy { /// Get the kernel name. const char *getName() const { return Name; } + /// Indicate if the target needs to use the kernel environment. This is only + /// necessary for GPU targets currently. + virtual bool shouldSetupKernelEnvironment() const { return true; } + /// Get the kernel image. DeviceImageTy &getImage() const { assert(ImagePtr && "Kernel is not initialized!"); diff --git a/offload/plugins-nextgen/common/src/PluginInterface.cpp b/offload/plugins-nextgen/common/src/PluginInterface.cpp index 913721a15d713..800f960887009 100644 --- a/offload/plugins-nextgen/common/src/PluginInterface.cpp +++ b/offload/plugins-nextgen/common/src/PluginInterface.cpp @@ -472,6 +472,7 @@ GenericKernelTy::getKernelLaunchEnvironment( // environment. Older versions of the compiler do not generate a kernel // launch environment. if (GenericDevice.Plugin.getRecordReplay().isReplaying() || + !shouldSetupKernelEnvironment() || Version < OMP_KERNEL_ARG_MIN_VERSION_WITH_DYN_PTR) return nullptr; diff --git a/offload/plugins-nextgen/host/CMakeLists.txt b/offload/plugins-nextgen/host/CMakeLists.txt index 817d128f92410..93898a6bba3dd 100644 --- a/offload/plugins-nextgen/host/CMakeLists.txt +++ b/offload/plugins-nextgen/host/CMakeLists.txt @@ -13,30 +13,12 @@ endif() add_target_library(omptarget.rtl.host ${machine}) target_sources(omptarget.rtl.host PRIVATE src/rtl.cpp) - -if(LIBOMPTARGET_DEP_LIBFFI_FOUND) - message(STATUS "Building ${machine} plugin linked with libffi") - if(FFI_STATIC_LIBRARIES) - target_link_libraries(omptarget.rtl.host PRIVATE FFI::ffi_static) - else() - target_link_libraries(omptarget.rtl.host PRIVATE FFI::ffi) - endif() -else() - message(STATUS "Building ${machine} plugin for dlopened libffi") - target_sources(omptarget.rtl.host PRIVATE dynamic_ffi/ffi.cpp) - target_include_directories(omptarget.rtl.host PRIVATE dynamic_ffi) -endif() - target_include_directories(omptarget.rtl.host PRIVATE ${LIBOMPTARGET_INCLUDE_DIR}) -if(LIBOMPTARGET_DEP_LIBFFI_FOUND) - list(APPEND LIBOMPTARGET_TESTED_PLUGINS omptarget.rtl.host) - set(LIBOMPTARGET_TESTED_PLUGINS - "${LIBOMPTARGET_TESTED_PLUGINS}" PARENT_SCOPE) -else() - message(STATUS "Not generating ${tmachine_name} tests. LibFFI not found.") -endif() +list(APPEND LIBOMPTARGET_TESTED_PLUGINS omptarget.rtl.host) +set(LIBOMPTARGET_TESTED_PLUGINS + "${LIBOMPTARGET_TESTED_PLUGINS}" PARENT_SCOPE) # Define the target specific triples and ELF machine values. if(CMAKE_SYSTEM_PROCESSOR MATCHES "ppc64le$") diff --git a/offload/plugins-nextgen/host/dynamic_ffi/ffi.cpp b/offload/plugins-nextgen/host/dynamic_ffi/ffi.cpp deleted file mode 100644 index c586ad1c1969b..0000000000000 --- a/offload/plugins-nextgen/host/dynamic_ffi/ffi.cpp +++ /dev/null @@ -1,75 +0,0 @@ -//===--- generic-elf-64bit/dynamic_ffi/ffi.cpp -------------------- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// Implement subset of the FFI api by calling into the FFI library via dlopen -// -//===----------------------------------------------------------------------===// - -#include "llvm/Support/DynamicLibrary.h" - -#include "Shared/Debug.h" -#include - -#include "DLWrap.h" -#include "ffi.h" - -DLWRAP_INITIALIZE() - -DLWRAP(ffi_call, 4); -DLWRAP(ffi_prep_cif, 5); - -DLWRAP_FINALIZE() - -ffi_type ffi_type_void; -ffi_type ffi_type_pointer; - -// Name of the FFI shared library. -constexpr const char *FFI_PATH = "libffi.so"; - -#define DYNAMIC_FFI_SUCCESS 0 -#define DYNAMIC_FFI_FAIL 1 - -// Initializes the dynamic FFI wrapper. -uint32_t ffi_init() { - std::string ErrMsg; - auto DynlibHandle = std::make_unique( - llvm::sys::DynamicLibrary::getPermanentLibrary(FFI_PATH, &ErrMsg)); - - if (!DynlibHandle->isValid()) { - DP("Unable to load library '%s': %s!\n", FFI_PATH, ErrMsg.c_str()); - return DYNAMIC_FFI_FAIL; - } - - for (size_t I = 0; I < dlwrap::size(); I++) { - const char *Sym = dlwrap::symbol(I); - - void *P = DynlibHandle->getAddressOfSymbol(Sym); - if (P == nullptr) { - DP("Unable to find '%s' in '%s'!\n", Sym, FFI_PATH); - return DYNAMIC_FFI_FAIL; - } - DP("Implementing %s with dlsym(%s) -> %p\n", Sym, Sym, P); - - *dlwrap::pointer(I) = P; - } - -#define DYNAMIC_INIT(SYMBOL) \ - { \ - void *SymbolPtr = DynlibHandle->getAddressOfSymbol(#SYMBOL); \ - if (!SymbolPtr) { \ - DP("Unable to find '%s' in '%s'!\n", #SYMBOL, FFI_PATH); \ - return DYNAMIC_FFI_FAIL; \ - } \ - SYMBOL = *reinterpret_cast(SymbolPtr); \ - } - DYNAMIC_INIT(ffi_type_void); - DYNAMIC_INIT(ffi_type_pointer); -#undef DYNAMIC_INIT - - return DYNAMIC_FFI_SUCCESS; -} diff --git a/offload/plugins-nextgen/host/dynamic_ffi/ffi.h b/offload/plugins-nextgen/host/dynamic_ffi/ffi.h deleted file mode 100644 index 0ae025805e1d4..0000000000000 --- a/offload/plugins-nextgen/host/dynamic_ffi/ffi.h +++ /dev/null @@ -1,78 +0,0 @@ -//===--- generic-elf-64bit/dynamic_ffi/ffi.cpp -------------------- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// Provides a mirror to the parts of the FFI interface that the plugins require. -// -// libffi -// - Copyright (c) 2011, 2014, 2019, 2021, 2022 Anthony Green -// - Copyright (c) 1996-2003, 2007, 2008 Red Hat, Inc. -// -//===----------------------------------------------------------------------===// - -#ifndef DYNAMIC_FFI_FFI_H -#define DYNAMIC_FFI_FFI_H - -#include -#include - -#define USES_DYNAMIC_FFI - -uint32_t ffi_init(); - -typedef struct _ffi_type { - size_t size; - unsigned short alignment; - unsigned short type; - struct _ffi_type **elements; -} ffi_type; - -typedef enum { - FFI_OK = 0, - FFI_BAD_TYPEDEF, - FFI_BAD_ABI, - FFI_BAD_ARGTYPE -} ffi_status; - -// These are target depenent so we set them manually for each ABI by referencing -// the FFI source. -typedef enum ffi_abi { -#if (defined(_M_X64) || defined(__x86_64__)) - FFI_DEFAULT_ABI = 2, // FFI_UNIX64. -#elif defined(__aarch64__) || defined(__arm64__) || defined(_M_ARM64) - FFI_DEFAULT_ABI = 1, // FFI_SYSV. -#elif defined(__powerpc64__) - FFI_DEFAULT_ABI = 8, // FFI_LINUX. -#elif defined(__s390x__) - FFI_DEFAULT_ABI = 1, // FFI_SYSV. -#else -#error "Unknown ABI" -#endif -} ffi_cif; - -#ifdef __cplusplus -extern "C" { -#endif - -#define FFI_EXTERN extern -#define FFI_API - -FFI_EXTERN ffi_type ffi_type_void; -FFI_EXTERN ffi_type ffi_type_pointer; - -FFI_API -void ffi_call(ffi_cif *cif, void (*fn)(void), void *rvalue, void **avalue); - -FFI_API -ffi_status ffi_prep_cif(ffi_cif *cif, ffi_abi abi, unsigned int nargs, - ffi_type *rtype, ffi_type **atypes); - -#ifdef __cplusplus -} -#endif - -#endif // DYNAMIC_FFI_FFI_H diff --git a/offload/plugins-nextgen/host/src/rtl.cpp b/offload/plugins-nextgen/host/src/rtl.cpp index ef84cbaf54588..50a5c97493138 100644 --- a/offload/plugins-nextgen/host/src/rtl.cpp +++ b/offload/plugins-nextgen/host/src/rtl.cpp @@ -18,6 +18,7 @@ #include "Shared/Debug.h" #include "Shared/Environment.h" +#include "Shared/Utils.h" #include "Utils/ELF.h" #include "GlobalHandler.h" @@ -62,6 +63,9 @@ struct GenELF64KernelTy : public GenericKernelTy { /// Construct the kernel with a name and an execution mode. GenELF64KernelTy(const char *Name) : GenericKernelTy(Name), Func(nullptr) {} + /// This plugin doesn't use the kernel environment. + virtual bool shouldSetupKernelEnvironment() const override { return false; }; + /// Initialize the kernel. Error initImpl(GenericDeviceTy &Device, DeviceImageTy &Image) override { // Functions have zero size. @@ -77,7 +81,7 @@ struct GenELF64KernelTy : public GenericKernelTy { return Plugin::error("Invalid function for kernel %s", getName()); // Save the function pointer. - Func = (void (*)())Global.getPtr(); + Func = (void (*)(void *, void *))Global.getPtr(); KernelEnvironment.Configuration.ExecMode = OMP_TGT_EXEC_MODE_GENERIC; KernelEnvironment.Configuration.MayUseNestedParallelism = /*Unknown=*/2; @@ -88,31 +92,61 @@ struct GenELF64KernelTy : public GenericKernelTy { return Plugin::success(); } - /// Launch the kernel using the libffi. + /// Launch the kernel by copying the arguments to a new struct. Error launchImpl(GenericDeviceTy &GenericDevice, uint32_t NumThreads, uint64_t NumBlocks, KernelArgsTy &KernelArgs, void *Args, AsyncInfoWrapperTy &AsyncInfoWrapper) const override { - // Create a vector of ffi_types, one per argument. - SmallVector ArgTypes(KernelArgs.NumArgs, &ffi_type_pointer); - ffi_type **ArgTypesPtr = (ArgTypes.size()) ? &ArgTypes[0] : nullptr; - - // Prepare the cif structure before running the kernel function. - ffi_cif Cif; - ffi_status Status = ffi_prep_cif(&Cif, FFI_DEFAULT_ABI, KernelArgs.NumArgs, - &ffi_type_void, ArgTypesPtr); - if (Status != FFI_OK) - return Plugin::error("Error in ffi_prep_cif: %d", Status); - - // Call the kernel function through libffi. - long Return; - ffi_call(&Cif, Func, &Return, (void **)Args); + // The CPU uses a packed struct as its native argument format. We need to + // get the appropriate size with alignment according to the OpenMP + // interface. + void *AllArgs = nullptr; + if (KernelArgs.NumArgs) { + uint64_t Size = 0; + for (int I = 0; I < KernelArgs.NumArgs; ++I) { + // The reported size is only accurate if it is a literal being copied, + // otherwise it is always an i64 pointer or promoted value. + uint64_t Width = KernelArgs.ArgTypes[I] & OMP_TGT_MAPTYPE_LITERAL + ? KernelArgs.ArgSizes[I] + : sizeof(void *); + if (Size % Width != 0) + Size = align_up(Size, Width); + Size += Width; + } + + auto AllocOrErr = GenericDevice.dataAlloc( + Size, /*HstPtr=*/nullptr, TargetAllocTy::TARGET_ALLOC_DEVICE); + if (!AllocOrErr) + return AllocOrErr.takeError(); + AllArgs = *AllocOrErr; + + uint64_t Offset = 0; + for (int I = 0; I < KernelArgs.NumArgs; ++I) { + uint64_t Width = KernelArgs.ArgTypes[I] & OMP_TGT_MAPTYPE_LITERAL + ? KernelArgs.ArgSizes[I] + : sizeof(void *); + Offset = align_up(Offset, Width); + std::memcpy(advanceVoidPtr(AllArgs, Offset), + static_cast(Args)[I], Width); + Offset += Width; + } + AsyncInfoWrapper.freeAllocationAfterSynchronization(AllArgs); + } + // We do not use the kernel environment pointer, but the Clang codegen emits + // it anyway. It is easier to simply ignore it here. + Func(nullptr, AllArgs); return Plugin::success(); } private: - /// The kernel function to execute. - void (*Func)(void); + template static Ty1 align_up(Ty1 V, Ty2 Align) { + return ((V + Ty1(Align) - 1) / Ty1(Align)) * Ty1(Align); + } + + /// The kernel function to execute. The function signature is always expected + /// to be the following interface. + /// void kernel(void *KernelEnv, void *Args[NumArgs]); + void (*Func)(void *, void *); }; /// Class implementing the GenELF64 device images properties.