diff --git a/llvm/lib/Target/RISCV/RISCVProfiles.td b/llvm/lib/Target/RISCV/RISCVProfiles.td index 5c13710faf65b9..e56df33bd8cb07 100644 --- a/llvm/lib/Target/RISCV/RISCVProfiles.td +++ b/llvm/lib/Target/RISCV/RISCVProfiles.td @@ -8,7 +8,11 @@ class RISCVProfile features> : SubtargetFeature; + "RISC-V " # name # " profile", features> { + // Indicates if the profile is not yet ratified, so should be treated as + // experimental. + bit Experimental = false; +} defvar RVI20U32Features = [Feature32Bit, FeatureStdExtI]; defvar RVI20U64Features = [Feature64Bit, FeatureStdExtI]; diff --git a/llvm/test/TableGen/riscv-target-def.td b/llvm/test/TableGen/riscv-target-def.td index 7f3d9bdb278ca3..e328a6e3b58349 100644 --- a/llvm/test/TableGen/riscv-target-def.td +++ b/llvm/test/TableGen/riscv-target-def.td @@ -53,12 +53,19 @@ def FeatureDummy class RISCVProfile features> : SubtargetFeature; + "RISC-V " # name # " profile", features> { + bit Experimental = false; +} +class RISCVExperimentalProfile features> + : RISCVProfile<"experimental-"#name, features> { + let Experimental = true; +} def RVI20U32 : RISCVProfile<"rvi20u32", [Feature32Bit, FeatureStdExtI]>; def RVI20U64 : RISCVProfile<"rvi20u64", [Feature64Bit, FeatureStdExtI]>; def ProfileDummy : RISCVProfile<"dummy", [Feature64Bit, FeatureStdExtI, FeatureStdExtF, FeatureStdExtZidummy]>; +def RVI99U64 : RISCVExperimentalProfile<"rvi99u64", [Feature64Bit, FeatureStdExtI]>; class RISCVProcessorModel &Features) { OS << LS << Ext.first << Ext.second.Major << 'p' << Ext.second.Minor; } +static void printProfileTable(raw_ostream &OS, + const std::vector &Profiles, + bool Experimental) { + OS << "static constexpr RISCVProfile Supported"; + if (Experimental) + OS << "Experimental"; + OS << "Profiles[] = {\n"; + + for (const Record *Rec : Profiles) { + if (Rec->getValueAsBit("Experimental") != Experimental) + continue; + + OS.indent(4) << "{\"" << Rec->getValueAsString("Name") << "\",\""; + printMArch(OS, Rec->getValueAsListOfDefs("Implies")); + OS << "\"},\n"; + } + + OS << "};\n\n"; +} + static void emitRISCVProfiles(RecordKeeper &Records, raw_ostream &OS) { OS << "#ifdef GET_SUPPORTED_PROFILES\n"; OS << "#undef GET_SUPPORTED_PROFILES\n\n"; @@ -129,15 +149,12 @@ static void emitRISCVProfiles(RecordKeeper &Records, raw_ostream &OS) { auto Profiles = Records.getAllDerivedDefinitionsIfDefined("RISCVProfile"); if (!Profiles.empty()) { - llvm::sort(Profiles, LessRecordFieldName()); - OS << "static constexpr RISCVProfile SupportedProfiles[] = {\n"; - for (const Record *Rec : Profiles) { - OS.indent(4) << "{\"" << Rec->getValueAsString("Name") << "\",\""; - printMArch(OS, Rec->getValueAsListOfDefs("Implies")); - OS << "\"},\n"; - } - - OS << "};\n\n"; + printProfileTable(OS, Profiles, /*Experimental=*/false); + bool HasExperimentalProfiles = any_of(Profiles, [&](auto &Rec) { + return Rec->getValueAsBit("Experimental"); + }); + if (HasExperimentalProfiles) + printProfileTable(OS, Profiles, /*Experimental=*/true); } OS << "#endif // GET_SUPPORTED_PROFILES\n\n";