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Add support for displaying all segments (ie. RAM and registers) as we…

…ll as physical (ROM) address space.
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1 parent cea9838 commit c676cab5895f22f19972e53a7b4c8541347337d9 @logic committed Sep 21, 2010
Showing with 13 additions and 3 deletions.
  1. +11 −3 dis.py
  2. +2 −0 sh2.py
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14 dis.py
@@ -202,11 +202,17 @@ def mitsu_fixups(model):
output_separator = ' ! ' + '-' * 60
-def final_output(model, outfile=sys.stdout):
+def final_output(model, outfile=sys.stdout, output_ram=False):
# Output a moderately-useful disassembly.
countdown = 0
code = False
- for start, end in model.get_phys_ranges():
+ ranges = [ ]
+ if output_ram:
+ for segment in model.segments:
+ ranges.append((segment.start, segment.end))
+ else:
+ ranges = model.get_phys_ranges()
+ for start, end in ranges:
for i in range(start, end):
if countdown > 0:
countdown -= 1
@@ -237,6 +243,8 @@ def main():
help='specify a destination file (default is standard output)')
parser.add_option('-m', '--mitsu', action='store_true', dest='mitsu',
help='perform fixups specific to Mitsubishi ECUs')
+ parser.add_option('-r', '--ram', action='store_true', dest='output_ram',
+ help='include RAM addresses in output')
options, args = parser.parse_args()
if len(args) != 1:
@@ -262,7 +270,7 @@ def main():
output = sys.stdout
else:
output = open(options.file, 'w')
- final_output(model, output)
+ final_output(model, output, options.output_ram)
if __name__ == '__main__':
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2 sh2.py
@@ -30,6 +30,8 @@ def get_instruction(self):
"""A GAS-compatible string representation for this data type."""
name = self.__class__.__name__.lower().replace('field', '')
val = '.%s 0x%%0%dX' % (name, (self.width * 2))
+ if self.extra is None:
+ self.extra = 0
return val % self.extra

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