From 8f7ae504944c882f1dc227f950ff16b9c4a1100d Mon Sep 17 00:00:00 2001 From: Greg Chadwick Date: Wed, 21 Jun 2023 12:25:50 +0100 Subject: [PATCH] [dv, fcov] Increase iterations of riscv_mem_intg_error_test This helps hit more coverage more reliably in particular for the priv_mode_irq_cross cross coverage. A better fix would adjust riscv_mem_intg_error_test to utilize U mode more but it's a quick test for run so this suffices for now. --- dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml b/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml index e8b7b82e8..824ba7ff7 100644 --- a/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml +++ b/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml @@ -606,7 +606,7 @@ - test: riscv_mem_intg_error_test description: > Normal random instruction test, but randomly insert memory load/store integrity errors - iterations: 15 + iterations: 50 gen_test: riscv_rand_instr_test gen_opts: > +require_signature_addr=1