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Provide simulation to run RISC-V Compliance test #209

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merged 2 commits into from Aug 5, 2019

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@imphil
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commented Aug 3, 2019

This adds a Verilator simulation of Ibex for use in RISC-V Compliance
Testing. In addition to ibex itself, the simulation contains a RAM and
a memory-mapped helper module for the test software to interact with the
outside world. The test framework uses this to dump a "test signature",
which is written to a certain part of the memory, and to end the
simulation. (In the future, this could be extended to include printf()
like functionality.)

Fixes #99

Note that this requires changes to the compliance test suite itself, please see #99 for more discussion.

@vogelpi
vogelpi approved these changes Aug 5, 2019
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Thanks @imphil for implementing all this including the howto and documentation! I tested it and it works like a charm. I have just minor comments like missing newlines at the end of some files, and some indentation issues.

I noted that we have 3 identical copies of prim_clock_gating.sv in the repo now. And this is not good. I think we should at some point change this and have only one...

end
end
end
endmodule

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vogelpi Aug 5, 2019

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Add newline


assign clk_o = clk_i & clk_en;

endmodule

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vogelpi Aug 5, 2019

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Add newline

.host_rdata_i (host_rdata[TestUtilHost])
);

endmodule

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Add newline

end
host_gnt_o[host_sel_req] = host_req_i[host_sel_req];
end
endmodule

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Add terminating newline.

module ibex_riscv_compliance (
input IO_CLK,
input IO_RST_N
);

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vogelpi Aug 5, 2019

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Remove spaces before ");"

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imphil Aug 5, 2019

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Fixed, thanks

@@ -0,0 +1,24 @@
// Copyright lowRISC contributors.

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We now got four copies of prim_clock_gating.sv inside the repo:

  • examples/sim/rtl/prim_clock_gating.sv
  • dv/riscv_compliance/rtl/prim_clock_gating.sv
  • dv/uvm/tb/prim_clock_gating.sv

They are all the same, except for an unused parameter. A fourth copy with a Xilinx implementation is in examples/fpga/artya7-100/rtl/prim_clock_gating.sv. Should we reorganize this at some point?

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imphil Aug 5, 2019

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I've opened #213 to track progress on that.

imphil added 2 commits Aug 2, 2019
Add simulation for RISC-V compliance testing
This adds a Verilator simulation of Ibex for use in RISC-V Compliance
Testing. In addition to ibex itself, the simulation contains a RAM and
a memory-mapped helper module for the test software to interact with the
outside world. The test framework uses this to dump a "test signature",
which is written to a certain part of the memory, and to end the
simulation. (In the future, this could be extended to include printf()
like functionality.)

@imphil imphil force-pushed the imphil:riscv-compliance branch from 1ea9dc0 to e4086d3 Aug 5, 2019

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commented Aug 5, 2019

As discussed in person, the newlines are there. I implemented all other suggestions. Thanks for the review Pirmin!

@imphil imphil merged commit 24a9c64 into lowRISC:master Aug 5, 2019

@imphil imphil deleted the imphil:riscv-compliance branch Aug 5, 2019

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