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[test-triage] chip_sw_pwrmgr_main_power_glitch_reset
#23961
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chip_sw_pwrmgr_main_power_glitch_reset
Asked @matutem whether he could look into this and he accepted :-) |
This is an SVA issue: the assertion is missing the por_n_i rstmgr input. Bit 0 of por_n_i will cause a POR, but bit 1 indicates a glitch in the main power, and it will trigger a Domain0 reset. The SVA fix is easy. One interesting and disturbing issue is that bit 1 of por_n_i is set to the ast's ast)pwst.main_pok signal, which will be active when there is a power glitch in the |
Are you sure opentitan/hw/top_earlgrey/ip_autogen/rstmgr/rtl/rstmgr.sv Lines 92 to 98 in 3921170
opentitan/hw/top_earlgrey/ip_autogen/rstmgr/rtl/rstmgr.sv Lines 111 to 120 in 3921170
and I this reset is asynchronous, thus not sampled with clk_aon_i .
Am I missing something? If so, could you please point to the code you're referring to? |
My concern is about u_por_domain_sync in line 114 show above. The clock used for the flops is clk_aon_i, so por_n_i is only captured once every 5 micros. |
The assertions pwrmgr_rstmgr_sva_if need to be disabled when either aon or main_pok are inactive. It is more reliable to bind them to rstmgr for top-level simulations. This PR does that and connects rst_slow_ni to &rst_por_aon_n, since rst_por_aon_n is 2-bit wide (one per domain), and captures the rstmgr behavior more accurately. Fixes lowRISC#23961 Signed-off-by: Guillermo Maturana <maturana@opentitan.org>
The assertions pwrmgr_rstmgr_sva_if need to be disabled when either aon or main_pok are inactive. It is more reliable to bind them to rstmgr for top-level simulations. This PR does that and connects rst_slow_ni to &rst_por_aon_n, since rst_por_aon_n is 2-bit wide (one per domain), and captures the rstmgr behavior more accurately. Fixes lowRISC#23961 Signed-off-by: Guillermo Maturana <maturana@opentitan.org>
The assertions pwrmgr_rstmgr_sva_if need to be disabled when either aon or main_pok are inactive. It is more reliable to bind them to rstmgr for top-level simulations. This PR does that and connects rst_slow_ni to &rst_por_aon_n, since rst_por_aon_n is 2-bit wide (one per domain), and captures the rstmgr behavior more accurately. This also removes the rstmgr_unit_only* files for simplicity. Fixes lowRISC#23961 Signed-off-by: Guillermo Maturana <maturana@opentitan.org>
The assertions pwrmgr_rstmgr_sva_if need to be disabled when either aon or main_pok are inactive. It is more reliable to bind them to rstmgr for top-level simulations. This PR does that and connects rst_slow_ni to &rst_por_aon_n, since rst_por_aon_n is 2-bit wide (one per domain), and captures the rstmgr behavior more accurately. This also removes the rstmgr_unit_only* files for simplicity. Fixes lowRISC#23961 Signed-off-by: Guillermo Maturana <maturana@opentitan.org>
The assertions pwrmgr_rstmgr_sva_if need to be disabled when either aon or main_pok are inactive. It is more reliable to bind them to rstmgr for top-level simulations. This PR does that and connects rst_slow_ni to &rst_por_aon_n, since rst_por_aon_n is 2-bit wide (one per domain), and captures the rstmgr behavior more accurately. This also removes the rstmgr_unit_only* files for simplicity. Fixes lowRISC#23961 Signed-off-by: Guillermo Maturana <maturana@opentitan.org>
The assertions pwrmgr_rstmgr_sva_if need to be disabled when either aon or main_pok are inactive. It is more reliable to bind them to rstmgr for top-level simulations. This PR does that and connects rst_slow_ni to &rst_por_aon_n, since rst_por_aon_n is 2-bit wide (one per domain), and captures the rstmgr behavior more accurately. This also removes the rstmgr_unit_only* files for simplicity. Fixes lowRISC#23961 Signed-off-by: Guillermo Maturana <maturana@opentitan.org>
The assertions pwrmgr_rstmgr_sva_if need to be disabled when either aon or main_pok are inactive. It is more reliable to bind them to rstmgr for top-level simulations. This PR does that and connects rst_slow_ni to &rst_por_aon_n, since rst_por_aon_n is 2-bit wide (one per domain), and captures the rstmgr behavior more accurately. This also removes the rstmgr_unit_only* files for simplicity. Fixes lowRISC#23961 Signed-off-by: Guillermo Maturana <maturana@opentitan.org>
The assertions pwrmgr_rstmgr_sva_if need to be disabled when either aon or main_pok are inactive. It is more reliable to bind them to rstmgr for top-level simulations. This PR does that and connects rst_slow_ni to &rst_por_aon_n, since rst_por_aon_n is 2-bit wide (one per domain), and captures the rstmgr behavior more accurately. This also removes the rstmgr_unit_only* files for simplicity. Fixes lowRISC#23961 Signed-off-by: Guillermo Maturana <maturana@opentitan.org>
The assertions pwrmgr_rstmgr_sva_if need to be disabled when either aon or main_pok are inactive. It is more reliable to bind them to rstmgr for top-level simulations. This PR does that and connects rst_slow_ni to &rst_por_aon_n, since rst_por_aon_n is 2-bit wide (one per domain), and captures the rstmgr behavior more accurately. This also removes the rstmgr_unit_only* files for simplicity. Fixes lowRISC#23961 Signed-off-by: Guillermo Maturana <maturana@opentitan.org>
Hierarchy of regression failure
Chip Level
Failure Description
Steps to Reproduce
./util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson -i chip_sw_pwrmgr_main_power_glitch_reset --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676 --fixed-seed 19739929326588231339427436212387352319943555198022910986496607969950925791351 --waves fsdb
Tests with similar or related failures
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