diff --git a/hw/top_earlgrey/clkgen_xil7series.core b/hw/top_earlgrey/clkgen_xil7series.core deleted file mode 100644 index 9bc8eb30dfe73..0000000000000 --- a/hw/top_earlgrey/clkgen_xil7series.core +++ /dev/null @@ -1,21 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -# TODO: long term this should be merged into AST. - -name: "lowrisc:systems:clkgen_xil7series" -description: "Clock generation infrastructure for Xilinx 7-Series FPGAs." -filesets: - files_rtl: - files: - - rtl/clkgen_xil7series.sv - # piggy-back here for now - - rtl/usr_access_xil7series.sv - file_type: systemVerilogSource - -targets: - default: - filesets: - - files_rtl diff --git a/hw/top_earlgrey/data/clocks.xdc b/hw/top_earlgrey/data/clocks.xdc index e111068c35338..074548bf593b5 100644 --- a/hw/top_earlgrey/data/clocks.xdc +++ b/hw/top_earlgrey/data/clocks.xdc @@ -231,14 +231,29 @@ set_input_delay -clock clk_spi_pt -clock_fall -max ${spi_host_in_delay_max} \ # SPI Host clock origin buffer set spi_host_0_peri [get_pins top_earlgrey/u_clkmgr_aon/u_clk_io_peri_cg/gen_xilinx.u_impl_xilinx/gen_gate.gen_bufgce.u_bufgce/O] -# Even though it's 2x the max possible frequency, keep the peripheral clock -# frequency for the output. This will enable shifting the latch edge for hold -# analysis by the proper amount to effect "half-cycle sampling" of SPI. -create_generated_clock -name clk_spi_host0 -divide_by 1 -add \ +create_generated_clock -name clk_spi_host0 -divide_by 2 -add \ -source ${spi_host_0_peri} \ -master_clock [get_clocks -of_objects ${spi_host_0_peri}] \ [get_ports SPI_HOST_CLK] +# Multi-cycle path to adjust the hold edge, since launch and capture edges are +# opposite in the SPI_HOST_CLK domain. +set_multicycle_path -setup 1 -start \ + -from [get_clocks -of_objects ${spi_host_0_peri}] \ + -to [get_clocks clk_spi_host0] +set_multicycle_path -hold 1 -start \ + -from [get_clocks -of_objects ${spi_host_0_peri}] \ + -to [get_clocks clk_spi_host0] + +# set multicycle path for data going from SPI_HOST_CLK to logic +# the SPI host logic will read these paths at "full cycle" +set_multicycle_path -setup -end 2 \ + -from [get_clocks clk_spi_host0] \ + -to [get_clocks -of_objects ${spi_host_0_peri}] +set_multicycle_path -hold -end 2 \ + -from [get_clocks clk_spi_host0] \ + -to [get_clocks -of_objects ${spi_host_0_peri}] + set spi_host_0_data [get_ports {SPI_HOST_D0 SPI_HOST_D1 SPI_HOST_D2 SPI_HOST_D3 SPI_HOST_CS_L}] set_output_delay -clock clk_spi_host0 -min ${spi_host_out_hold} \ ${spi_host_0_data} -add_delay @@ -249,17 +264,6 @@ set_input_delay -clock clk_spi_host0 -clock_fall -min ${spi_host_in_delay_min} set_input_delay -clock clk_spi_host0 -clock_fall -max ${spi_host_in_delay_max} \ ${spi_host_0_data} -add_delay -# The setup analysis is already correct for half-cycle sampling: If the first -# posedge of the peripheral clock represents the negedge of SPI_HOST_CLK, then -# the next posedge of the peripheral clock is when data should be latched, the -# posedge of SPI_HOST_CLK. -# However, the latch edge for hold analysis represents the same edge and needs -# to be advanced by one cycle of the peripheral clock (half a cycle of -# SPI_HOST_CLK). -set_multicycle_path -hold -end \ - -from [get_clocks -of_objects ${spi_host_0_peri}] \ - -to [get_clocks clk_spi_host0] 1 - ## Set asynchronous clock groups set_clock_groups -asynchronous \ -group {clk_main clk_spi_host0} \ diff --git a/hw/top_earlgrey/rtl/clkgen_xil7series.sv b/hw/top_earlgrey/rtl/clkgen_xil7series.sv index 9687d8fd807ab..e2ce7d761f449 100644 --- a/hw/top_earlgrey/rtl/clkgen_xil7series.sv +++ b/hw/top_earlgrey/rtl/clkgen_xil7series.sv @@ -17,8 +17,8 @@ module clkgen_xil7series # ( logic locked_pll; logic io_clk_buf; logic io_rst_buf_n; - logic clk_10_buf; - logic clk_10_unbuf; + logic clk_main_buf; + logic clk_main_unbuf; logic clk_fb_buf; logic clk_fb_unbuf; logic clk_48_buf; @@ -30,10 +30,11 @@ module clkgen_xil7series # ( .BANDWIDTH ("OPTIMIZED"), .COMPENSATION ("ZHOLD"), .STARTUP_WAIT ("FALSE"), - .DIVCLK_DIVIDE (1), - .CLKFBOUT_MULT_F (12.000), + .CLKIN1_PERIOD (10.000), // f_CLKIN = 100 MHz + .DIVCLK_DIVIDE (1), // f_PFD = 100 MHz + .CLKFBOUT_MULT_F (12.000), // f_VCO = 1200 MHz .CLKFBOUT_PHASE (0.000), - .CLKOUT0_DIVIDE_F (120.0), + .CLKOUT0_DIVIDE_F (50.0), // f_main = 24 MHz .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT1_DIVIDE (25), @@ -45,12 +46,11 @@ module clkgen_xil7series # ( .CLKOUT4_PHASE (0.000), .CLKOUT4_DUTY_CYCLE (0.500), .CLKOUT4_CASCADE ("TRUE"), - .CLKOUT6_DIVIDE (120), - .CLKIN1_PERIOD (10.000) + .CLKOUT6_DIVIDE (120) ) pll ( .CLKFBOUT (clk_fb_unbuf), .CLKFBOUTB (), - .CLKOUT0 (clk_10_unbuf), + .CLKOUT0 (clk_main_unbuf), .CLKOUT0B (), .CLKOUT1 (clk_48_unbuf), .CLKOUT1B (), @@ -100,9 +100,9 @@ module clkgen_xil7series # ( ); if (AddClkBuf == 1) begin : gen_clk_bufs - BUFG clk_10_bufg ( - .I (clk_10_unbuf), - .O (clk_10_buf) + BUFG clk_main_bufg ( + .I (clk_main_unbuf), + .O (clk_main_buf) ); BUFG clk_48_bufg ( @@ -111,13 +111,13 @@ module clkgen_xil7series # ( ); end else begin : gen_no_clk_bufs // BUFGs added by downstream modules, no need to add here - assign clk_10_buf = clk_10_unbuf; + assign clk_main_buf = clk_main_unbuf; assign clk_48_buf = clk_48_unbuf; end // outputs // clock - assign clk_main_o = clk_10_buf; + assign clk_main_o = clk_main_buf; assign clk_48MHz_o = clk_48_buf; assign clk_aon_o = clk_aon_buf; diff --git a/hw/top_englishbreakfast/clkgen_xil7series.core b/hw/top_englishbreakfast/clkgen_xil7series.core deleted file mode 120000 index c098f061e6e34..0000000000000 --- a/hw/top_englishbreakfast/clkgen_xil7series.core +++ /dev/null @@ -1 +0,0 @@ -../top_earlgrey/clkgen_xil7series.core \ No newline at end of file diff --git a/hw/top_englishbreakfast/clkgen_xil7series.core b/hw/top_englishbreakfast/clkgen_xil7series.core new file mode 100644 index 0000000000000..9bc8eb30dfe73 --- /dev/null +++ b/hw/top_englishbreakfast/clkgen_xil7series.core @@ -0,0 +1,21 @@ +CAPI=2: +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# TODO: long term this should be merged into AST. + +name: "lowrisc:systems:clkgen_xil7series" +description: "Clock generation infrastructure for Xilinx 7-Series FPGAs." +filesets: + files_rtl: + files: + - rtl/clkgen_xil7series.sv + # piggy-back here for now + - rtl/usr_access_xil7series.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl diff --git a/hw/top_englishbreakfast/rtl/clkgen_xil7series.sv b/hw/top_englishbreakfast/rtl/clkgen_xil7series.sv deleted file mode 120000 index 3a2bbbbd37503..0000000000000 --- a/hw/top_englishbreakfast/rtl/clkgen_xil7series.sv +++ /dev/null @@ -1 +0,0 @@ -../../top_earlgrey/rtl/clkgen_xil7series.sv \ No newline at end of file diff --git a/hw/top_englishbreakfast/rtl/clkgen_xil7series.sv b/hw/top_englishbreakfast/rtl/clkgen_xil7series.sv new file mode 100644 index 0000000000000..28299e0cd9826 --- /dev/null +++ b/hw/top_englishbreakfast/rtl/clkgen_xil7series.sv @@ -0,0 +1,126 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module clkgen_xil7series # ( + // Add BUFG if not done by downstream logic + parameter bit AddClkBuf = 1 +) ( + input clk_i, + input rst_ni, + input srst_ni, + output clk_main_o, + output clk_48MHz_o, + output clk_aon_o, + output rst_no +); + logic locked_pll; + logic io_clk_buf; + logic io_rst_buf_n; + logic clk_main_buf; + logic clk_main_unbuf; + logic clk_fb_buf; + logic clk_fb_unbuf; + logic clk_48_buf; + logic clk_48_unbuf; + logic clk_aon_buf; + logic clk_aon_unbuf; + + MMCME2_ADV #( + .BANDWIDTH ("OPTIMIZED"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .CLKIN1_PERIOD (10.000), // f_CLKIN = 100 MHz + .DIVCLK_DIVIDE (1), // f_PFD = 100 MHz + .CLKFBOUT_MULT_F (12.000), // f_VCO = 1200 MHz + .CLKFBOUT_PHASE (0.000), + .CLKOUT0_DIVIDE_F (120.0), // f_main = 10 MHz + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT1_DIVIDE (25), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.500), + // With CLKOUT4_CASCADE, CLKOUT6's divider is an input to CLKOUT4's + // divider. The effective ratio is a multiplication of the two. + .CLKOUT4_DIVIDE (40), + .CLKOUT4_PHASE (0.000), + .CLKOUT4_DUTY_CYCLE (0.500), + .CLKOUT4_CASCADE ("TRUE"), + .CLKOUT6_DIVIDE (120) + ) pll ( + .CLKFBOUT (clk_fb_unbuf), + .CLKFBOUTB (), + .CLKOUT0 (clk_main_unbuf), + .CLKOUT0B (), + .CLKOUT1 (clk_48_unbuf), + .CLKOUT1B (), + .CLKOUT2 (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (clk_aon_unbuf), + .CLKOUT5 (), + .CLKOUT6 (), + // Input clock control + .CLKFBIN (clk_fb_buf), + .CLKIN1 (clk_i), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (), + .DRDY (), + .DWE (1'b0), + // Phase shift signals + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + // Other control and status signals + .CLKFBSTOPPED (), + .CLKINSTOPPED (), + .LOCKED (locked_pll), + .PWRDWN (1'b0), + // Do not reset MMCM on external reset, otherwise ILA disconnects at a reset + .RST (1'b0)); + + // output buffering + BUFG clk_fb_bufg ( + .I (clk_fb_unbuf), + .O (clk_fb_buf) + ); + + BUFG clk_aon_bufg ( + .I (clk_aon_unbuf), + .O (clk_aon_buf) + ); + + if (AddClkBuf == 1) begin : gen_clk_bufs + BUFG clk_main_bufg ( + .I (clk_main_unbuf), + .O (clk_main_buf) + ); + + BUFG clk_48_bufg ( + .I (clk_48_unbuf), + .O (clk_48_buf) + ); + end else begin : gen_no_clk_bufs + // BUFGs added by downstream modules, no need to add here + assign clk_main_buf = clk_main_unbuf; + assign clk_48_buf = clk_48_unbuf; + end + + // outputs + // clock + assign clk_main_o = clk_main_buf; + assign clk_48MHz_o = clk_48_buf; + assign clk_aon_o = clk_aon_buf; + + // reset + assign rst_no = locked_pll & rst_ni & srst_ni; +endmodule diff --git a/signing/rom_tests/signatures/empty_test_sigverify_spx_fpga_cw310.rsa.sig b/signing/rom_tests/signatures/empty_test_sigverify_spx_fpga_cw310.rsa.sig index 17f8a80994a50..a9642b4b9d52f 100644 Binary files a/signing/rom_tests/signatures/empty_test_sigverify_spx_fpga_cw310.rsa.sig and b/signing/rom_tests/signatures/empty_test_sigverify_spx_fpga_cw310.rsa.sig differ diff --git a/signing/rom_tests/signatures/empty_test_sigverify_spx_fpga_cw310.spx.sig b/signing/rom_tests/signatures/empty_test_sigverify_spx_fpga_cw310.spx.sig index fc7c4251852c3..e2df34930807d 100644 Binary files a/signing/rom_tests/signatures/empty_test_sigverify_spx_fpga_cw310.spx.sig and b/signing/rom_tests/signatures/empty_test_sigverify_spx_fpga_cw310.spx.sig differ diff --git a/signing/rom_tests/signatures/empty_test_sigverify_spx_sim_dv.rsa.sig b/signing/rom_tests/signatures/empty_test_sigverify_spx_sim_dv.rsa.sig index fcabcc1155816..42af71ebeb0a7 100644 Binary files a/signing/rom_tests/signatures/empty_test_sigverify_spx_sim_dv.rsa.sig and b/signing/rom_tests/signatures/empty_test_sigverify_spx_sim_dv.rsa.sig differ diff --git a/signing/rom_tests/signatures/empty_test_sigverify_spx_sim_dv.spx.sig b/signing/rom_tests/signatures/empty_test_sigverify_spx_sim_dv.spx.sig index e7a33b0b04283..ba31d91393b2b 100644 Binary files a/signing/rom_tests/signatures/empty_test_sigverify_spx_sim_dv.spx.sig and b/signing/rom_tests/signatures/empty_test_sigverify_spx_sim_dv.spx.sig differ diff --git a/signing/rom_tests/signatures/empty_test_sigverify_spx_sim_verilator.rsa.sig b/signing/rom_tests/signatures/empty_test_sigverify_spx_sim_verilator.rsa.sig index df66e3bda60d4..d280674a05cb5 100644 Binary files a/signing/rom_tests/signatures/empty_test_sigverify_spx_sim_verilator.rsa.sig and b/signing/rom_tests/signatures/empty_test_sigverify_spx_sim_verilator.rsa.sig differ diff --git a/signing/rom_tests/signatures/empty_test_sigverify_spx_sim_verilator.spx.sig b/signing/rom_tests/signatures/empty_test_sigverify_spx_sim_verilator.spx.sig index 9ac02830f9657..fc06956228ea1 100644 Binary files a/signing/rom_tests/signatures/empty_test_sigverify_spx_sim_verilator.spx.sig and b/signing/rom_tests/signatures/empty_test_sigverify_spx_sim_verilator.spx.sig differ diff --git a/signing/rom_tests/signatures/rom_e2e_self_hash_fpga_cw310.rsa.sig b/signing/rom_tests/signatures/rom_e2e_self_hash_fpga_cw310.rsa.sig index 07b19e0879907..f95b03e533ac2 100644 Binary files a/signing/rom_tests/signatures/rom_e2e_self_hash_fpga_cw310.rsa.sig and b/signing/rom_tests/signatures/rom_e2e_self_hash_fpga_cw310.rsa.sig differ diff --git a/sw/device/lib/arch/device_fpga_cw310.c b/sw/device/lib/arch/device_fpga_cw310.c index 35f51b59cf054..60acfd85121cb 100644 --- a/sw/device/lib/arch/device_fpga_cw310.c +++ b/sw/device/lib/arch/device_fpga_cw310.c @@ -16,15 +16,15 @@ const device_type_t kDeviceType = kDeviceFpgaCw310; -const uint64_t kClockFreqCpuMhz = 10; +const uint64_t kClockFreqCpuMhz = 24; const uint64_t kClockFreqCpuHz = kClockFreqCpuMhz * 1000 * 1000; uint64_t to_cpu_cycles(uint64_t usec) { return usec * kClockFreqCpuMhz; } -const uint64_t kClockFreqHiSpeedPeripheralHz = 10 * 1000 * 1000; // 10MHz +const uint64_t kClockFreqHiSpeedPeripheralHz = 24 * 1000 * 1000; // 24MHz -const uint64_t kClockFreqPeripheralHz = 25 * 100 * 1000; // 2.5MHz +const uint64_t kClockFreqPeripheralHz = 6 * 1000 * 1000; // 6MHz const uint64_t kClockFreqUsbHz = 48 * 1000 * 1000; // 48MHz diff --git a/sw/device/silicon_creator/rom/e2e/presigned_images/empty_test_sigverify_spx_fpga_cw310.signed.bin b/sw/device/silicon_creator/rom/e2e/presigned_images/empty_test_sigverify_spx_fpga_cw310.signed.bin index 67d30cfc7f9a0..309ac5cca5b94 100644 Binary files a/sw/device/silicon_creator/rom/e2e/presigned_images/empty_test_sigverify_spx_fpga_cw310.signed.bin and b/sw/device/silicon_creator/rom/e2e/presigned_images/empty_test_sigverify_spx_fpga_cw310.signed.bin differ diff --git a/sw/device/silicon_creator/rom/e2e/presigned_images/empty_test_sigverify_spx_sim_dv.signed.bin b/sw/device/silicon_creator/rom/e2e/presigned_images/empty_test_sigverify_spx_sim_dv.signed.bin index f9755d4a3b6c4..f2034e6eb0659 100644 Binary files a/sw/device/silicon_creator/rom/e2e/presigned_images/empty_test_sigverify_spx_sim_dv.signed.bin and b/sw/device/silicon_creator/rom/e2e/presigned_images/empty_test_sigverify_spx_sim_dv.signed.bin differ diff --git a/sw/device/silicon_creator/rom/e2e/presigned_images/empty_test_sigverify_spx_sim_verilator.signed.bin b/sw/device/silicon_creator/rom/e2e/presigned_images/empty_test_sigverify_spx_sim_verilator.signed.bin index 78a5fe66297af..49d20f5d55fb2 100644 Binary files a/sw/device/silicon_creator/rom/e2e/presigned_images/empty_test_sigverify_spx_sim_verilator.signed.bin and b/sw/device/silicon_creator/rom/e2e/presigned_images/empty_test_sigverify_spx_sim_verilator.signed.bin differ diff --git a/sw/device/silicon_creator/rom/e2e/presigned_images/rom_e2e_self_hash_fpga_cw310.signed.bin b/sw/device/silicon_creator/rom/e2e/presigned_images/rom_e2e_self_hash_fpga_cw310.signed.bin index 55e8c3950dca7..37fddbfc1848a 100644 Binary files a/sw/device/silicon_creator/rom/e2e/presigned_images/rom_e2e_self_hash_fpga_cw310.signed.bin and b/sw/device/silicon_creator/rom/e2e/presigned_images/rom_e2e_self_hash_fpga_cw310.signed.bin differ diff --git a/sw/device/tests/BUILD b/sw/device/tests/BUILD index f25ecd8562fb9..cf93b1ad0997e 100644 --- a/sw/device/tests/BUILD +++ b/sw/device/tests/BUILD @@ -1256,6 +1256,7 @@ opentitan_functest( "//sw/device/lib/runtime:hart", "//sw/device/lib/runtime:log", "//sw/device/lib/runtime:print", + "//sw/device/lib/testing:entropy_testutils", "//sw/device/lib/testing:keymgr_testutils", "//sw/device/lib/testing:otbn_testutils", "//sw/device/lib/testing/test_framework:ottf_main", diff --git a/sw/device/tests/crypto/BUILD b/sw/device/tests/crypto/BUILD index eaaf5e4613d12..e8f7feb0eae3a 100644 --- a/sw/device/tests/crypto/BUILD +++ b/sw/device/tests/crypto/BUILD @@ -177,8 +177,7 @@ opentitan_functest( name = "rsa_3072_verify_functest_wycheproof", srcs = ["rsa_3072_verify_functest.c"], cw310 = cw310_params( - timeout = "long", - tags = ["broken"], # FIXME #16805 hangs at vector 170 + timeout = "moderate", ), targets = [ "cw310_test_rom", @@ -187,10 +186,10 @@ opentitan_functest( ], verilator = verilator_params( timeout = "eternal", - tags = ["broken"], # FIXME #16805 hangs at vector 165 after ~3h ), deps = [ ":rsa_3072_verify_testvectors_wycheproof_header", + "//sw/device/lib/crypto/drivers:entropy", "//sw/device/lib/crypto/drivers:hmac", "//sw/device/lib/crypto/drivers:otbn", "//sw/device/lib/crypto/impl/rsa:rsa_3072_verify", @@ -214,6 +213,7 @@ opentitan_functest( ), deps = [ ":rsa_3072_verify_testvectors_hardcoded_header", + "//sw/device/lib/crypto/drivers:entropy", "//sw/device/lib/crypto/drivers:hmac", "//sw/device/lib/crypto/drivers:otbn", "//sw/device/lib/crypto/impl/rsa:rsa_3072_verify", diff --git a/sw/device/tests/crypto/rsa_3072_verify_functest.c b/sw/device/tests/crypto/rsa_3072_verify_functest.c index 7c607a42e2aa7..d35119e342d85 100644 --- a/sw/device/tests/crypto/rsa_3072_verify_functest.c +++ b/sw/device/tests/crypto/rsa_3072_verify_functest.c @@ -3,6 +3,7 @@ // SPDX-License-Identifier: Apache-2.0 #include "sw/device/lib/base/memory.h" +#include "sw/device/lib/crypto/drivers/entropy.h" #include "sw/device/lib/crypto/drivers/otbn.h" #include "sw/device/lib/crypto/impl/rsa/rsa_3072_verify.h" #include "sw/device/lib/runtime/log.h" @@ -60,6 +61,9 @@ bool test_main(void) { // Stays true only if all tests pass. bool result = true; + // Set entropy complex to auto mode. + CHECK_STATUS_OK(entropy_complex_init()); + // The definition of `RULE_NAME` comes from the autogen Bazel rule. LOG_INFO("Starting rsa_3072_verify_test:%s", RULE_NAME); for (uint32_t i = 0; i < RSA_3072_VERIFY_NUM_TESTS; i++) { diff --git a/sw/device/tests/keymgr_sideload_otbn_test.c b/sw/device/tests/keymgr_sideload_otbn_test.c index d6bb4d39b1b0a..65dd9ebdf6466 100644 --- a/sw/device/tests/keymgr_sideload_otbn_test.c +++ b/sw/device/tests/keymgr_sideload_otbn_test.c @@ -12,6 +12,7 @@ #include "sw/device/lib/runtime/hart.h" #include "sw/device/lib/runtime/log.h" #include "sw/device/lib/runtime/print.h" +#include "sw/device/lib/testing/entropy_testutils.h" #include "sw/device/lib/testing/keymgr_testutils.h" #include "sw/device/lib/testing/otbn_testutils.h" #include "sw/device/lib/testing/test_framework/check.h" @@ -160,6 +161,12 @@ bool test_main(void) { dif_otbn_t otbn; CHECK_DIF_OK( dif_otbn_init(mmio_region_from_addr(TOP_EARLGREY_OTBN_BASE_ADDR), &otbn)); + + // Put entropy source into auto mode. If the entropy source was merely left + // with the entropy it generated at boot, this test may exhaust the supply + // with no renewal. + CHECK_STATUS_OK(entropy_testutils_auto_mode_init()); + // Test OTBN sideloading. test_otbn_with_sideloaded_key(&keymgr, &otbn);