diff --git a/hw/opentitan/ot_otp_dj.c b/hw/opentitan/ot_otp_dj.c index 28def4bbb9242..968d21d03cb89 100644 --- a/hw/opentitan/ot_otp_dj.c +++ b/hw/opentitan/ot_otp_dj.c @@ -24,6 +24,8 @@ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. + * + * Based on OpenTitan 5fe6fe8605 */ #include "qemu/osdep.h" @@ -55,30 +57,31 @@ #define NUM_IRQS 2u #define NUM_ALERTS 5u -#define NUM_SRAM_KEY_REQ_SLOTS 4u -#define NUM_ERROR_ENTRIES 24u #define NUM_DAI_WORDS 2u #define NUM_DIGEST_WORDS 2u -#define NUM_SW_CFG_WINDOW_WORDS 4096u +#define NUM_ERROR_ENTRIES 24u #define NUM_PART 22u -#define NUM_PART_UNBUF 15u #define NUM_PART_BUF 7u -#define OTP_BYTE_ADDR_WIDTH 14u +#define NUM_PART_UNBUF 15u +#define NUM_SRAM_KEY_REQ_SLOTS 4u +#define NUM_SW_CFG_WINDOW_WORDS 4096u +#define NUM_ZER_WORDS 2u + +#define OTP_BYTE_ADDR_WIDTH 14u /* clang-format off */ -/* Core registers */ -REG32(INTR_STATE, 0x0u) +REG32(INTR_STATE, 0x000u) SHARED_FIELD(INTR_OTP_OPERATION_DONE, 0u, 1u) SHARED_FIELD(INTR_OTP_ERROR, 1u, 1u) -REG32(INTR_ENABLE, 0x4u) -REG32(INTR_TEST, 0x8u) -REG32(ALERT_TEST, 0xcu) +REG32(INTR_ENABLE, 0x004u) +REG32(INTR_TEST, 0x008u) +REG32(ALERT_TEST, 0x00cu) SHARED_FIELD(ALERT_FATAL_MACRO_ERROR, 0u, 1u) SHARED_FIELD(ALERT_FATAL_CHECK_ERROR, 1u, 1u) SHARED_FIELD(ALERT_FATAL_BUS_INTEG_ERROR, 2u, 1u) SHARED_FIELD(ALERT_FATAL_PRIM_OTP_ALERT, 3u, 1u) SHARED_FIELD(ALERT_RECOV_PRIM_OTP_ALERT, 4u, 1u) -REG32(STATUS, 0x10u) +REG32(STATUS, 0x010u) FIELD(STATUS, VENDOR_TEST_ERROR, 0u, 1u) FIELD(STATUS, CREATOR_SW_CFG_ERROR, 1u, 1u) FIELD(STATUS, OWNER_SW_CFG_ERROR, 2u, 1u) @@ -110,78 +113,79 @@ REG32(STATUS, 0x10u) FIELD(STATUS, BUS_INTEG_ERROR, 28u, 1u) FIELD(STATUS, DAI_IDLE, 29u, 1u) FIELD(STATUS, CHECK_PENDING, 30u, 1u) -REG32(ERR_CODE_0, 0x14u) +REG32(ERR_CODE_0, 0x014u) SHARED_FIELD(ERR_CODE, 0u, 3u) -REG32(ERR_CODE_1, 0x18u) -REG32(ERR_CODE_2, 0x1cu) -REG32(ERR_CODE_3, 0x20u) -REG32(ERR_CODE_4, 0x24u) -REG32(ERR_CODE_5, 0x28u) -REG32(ERR_CODE_6, 0x2cu) -REG32(ERR_CODE_7, 0x30u) -REG32(ERR_CODE_8, 0x34u) -REG32(ERR_CODE_9, 0x38u) -REG32(ERR_CODE_10, 0x3cu) -REG32(ERR_CODE_11, 0x40u) -REG32(ERR_CODE_12, 0x44u) -REG32(ERR_CODE_13, 0x48u) -REG32(ERR_CODE_14, 0x4cu) -REG32(ERR_CODE_15, 0x50u) -REG32(ERR_CODE_16, 0x54u) -REG32(ERR_CODE_17, 0x58u) -REG32(ERR_CODE_18, 0x5cu) -REG32(ERR_CODE_19, 0x60u) -REG32(ERR_CODE_20, 0x64u) -REG32(ERR_CODE_21, 0x68u) -REG32(ERR_CODE_22, 0x6cu) -REG32(ERR_CODE_23, 0x70u) -REG32(DIRECT_ACCESS_REGWEN, 0x74u) +REG32(ERR_CODE_1, 0x018u) +REG32(ERR_CODE_2, 0x01cu) +REG32(ERR_CODE_3, 0x020u) +REG32(ERR_CODE_4, 0x024u) +REG32(ERR_CODE_5, 0x028u) +REG32(ERR_CODE_6, 0x02cu) +REG32(ERR_CODE_7, 0x030u) +REG32(ERR_CODE_8, 0x034u) +REG32(ERR_CODE_9, 0x038u) +REG32(ERR_CODE_10, 0x03cu) +REG32(ERR_CODE_11, 0x040u) +REG32(ERR_CODE_12, 0x044u) +REG32(ERR_CODE_13, 0x048u) +REG32(ERR_CODE_14, 0x04cu) +REG32(ERR_CODE_15, 0x050u) +REG32(ERR_CODE_16, 0x054u) +REG32(ERR_CODE_17, 0x058u) +REG32(ERR_CODE_18, 0x05cu) +REG32(ERR_CODE_19, 0x060u) +REG32(ERR_CODE_20, 0x064u) +REG32(ERR_CODE_21, 0x068u) +REG32(ERR_CODE_22, 0x06cu) +REG32(ERR_CODE_23, 0x070u) +REG32(DIRECT_ACCESS_REGWEN, 0x074u) FIELD(DIRECT_ACCESS_REGWEN, REGWEN, 0u, 1u) -REG32(DIRECT_ACCESS_CMD, 0x78u) +REG32(DIRECT_ACCESS_CMD, 0x078u) FIELD(DIRECT_ACCESS_CMD, RD, 0u, 1u) FIELD(DIRECT_ACCESS_CMD, WR, 1u, 1u) FIELD(DIRECT_ACCESS_CMD, DIGEST, 2u, 1u) -REG32(DIRECT_ACCESS_ADDRESS, 0x7cu) - FIELD(DIRECT_ACCESS_ADDRESS, ADDRESS, 0, 14u) -REG32(DIRECT_ACCESS_WDATA_0, 0x80u) -REG32(DIRECT_ACCESS_WDATA_1, 0x84u) -REG32(DIRECT_ACCESS_RDATA_0, 0x88u) -REG32(DIRECT_ACCESS_RDATA_1, 0x8cu) -REG32(CHECK_TRIGGER_REGWEN, 0x90u) + FIELD(DIRECT_ACCESS_CMD, ZEROIZE, 3u, 1u) +REG32(DIRECT_ACCESS_ADDRESS, 0x07cu) + FIELD(DIRECT_ACCESS_ADDRESS, ADDRESS, 0u, 14u) +REG32(DIRECT_ACCESS_WDATA_0, 0x080u) +REG32(DIRECT_ACCESS_WDATA_1, 0x084u) +REG32(DIRECT_ACCESS_RDATA_0, 0x088u) +REG32(DIRECT_ACCESS_RDATA_1, 0x08cu) +REG32(CHECK_TRIGGER_REGWEN, 0x090u) FIELD(CHECK_TRIGGER_REGWEN, REGWEN, 0u, 1u) -REG32(CHECK_TRIGGER, 0x94u) +REG32(CHECK_TRIGGER, 0x094u) FIELD(CHECK_TRIGGER, INTEGRITY, 0u, 1u) FIELD(CHECK_TRIGGER, CONSISTENCY, 1u, 1u) -REG32(CHECK_REGWEN, 0x98u) +REG32(CHECK_REGWEN, 0x098u) FIELD(CHECK_REGWEN, REGWEN, 0u, 1u) -REG32(CHECK_TIMEOUT, 0x9cu) -REG32(INTEGRITY_CHECK_PERIOD, 0xa0u) -REG32(CONSISTENCY_CHECK_PERIOD, 0xa4u) -REG32(VENDOR_TEST_READ_LOCK, 0xa8u) - SHARED_FIELD(READ_LOCK, 0u, 1u) -REG32(CREATOR_SW_CFG_READ_LOCK, 0xacu) -REG32(OWNER_SW_CFG_READ_LOCK, 0xb0u) -REG32(OWNERSHIP_SLOT_STATE_READ_LOCK, 0xb4u) -REG32(ROT_CREATOR_AUTH_READ_LOCK, 0xb8u) -REG32(ROT_OWNER_AUTH_SLOT0_READ_LOCK, 0xbcu) -REG32(ROT_OWNER_AUTH_SLOT1_READ_LOCK, 0xc0u) -REG32(PLAT_INTEG_AUTH_SLOT0_READ_LOCK, 0xc4u) -REG32(PLAT_INTEG_AUTH_SLOT1_READ_LOCK, 0xc8u) -REG32(PLAT_OWNER_AUTH_SLOT0_READ_LOCK, 0xccu) -REG32(PLAT_OWNER_AUTH_SLOT1_READ_LOCK, 0xd0u) -REG32(PLAT_OWNER_AUTH_SLOT2_READ_LOCK, 0xd4u) -REG32(PLAT_OWNER_AUTH_SLOT3_READ_LOCK, 0xd8u) -REG32(EXT_NVM_READ_LOCK, 0xdcu) -REG32(ROM_PATCH_READ_LOCK, 0xe0u) -REG32(VENDOR_TEST_DIGEST_0, 0xe4u) -REG32(VENDOR_TEST_DIGEST_1, 0xe8u) -REG32(CREATOR_SW_CFG_DIGEST_0, 0xecu) -REG32(CREATOR_SW_CFG_DIGEST_1, 0xf0u) -REG32(OWNER_SW_CFG_DIGEST_0, 0xf4u) -REG32(OWNER_SW_CFG_DIGEST_1, 0xf8u) -REG32(ROT_CREATOR_AUTH_DIGEST_0, 0xfcu) +REG32(CHECK_TIMEOUT, 0x09cu) +REG32(INTEGRITY_CHECK_PERIOD, 0x0a0u) +REG32(CONSISTENCY_CHECK_PERIOD, 0x0a4u) +REG32(VENDOR_TEST_READ_LOCK, 0x0a8u) + SHARED_FIELD(READ_LOCK, 0u, 1u) +REG32(CREATOR_SW_CFG_READ_LOCK, 0x0acu) +REG32(OWNER_SW_CFG_READ_LOCK, 0x0b0u) +REG32(OWNERSHIP_SLOT_STATE_READ_LOCK, 0x0b4u) +REG32(ROT_CREATOR_AUTH_READ_LOCK, 0x0b8u) +REG32(ROT_OWNER_AUTH_SLOT0_READ_LOCK, 0x0bcu) +REG32(ROT_OWNER_AUTH_SLOT1_READ_LOCK, 0x0c0u) +REG32(PLAT_INTEG_AUTH_SLOT0_READ_LOCK, 0x0c4u) +REG32(PLAT_INTEG_AUTH_SLOT1_READ_LOCK, 0x0c8u) +REG32(PLAT_OWNER_AUTH_SLOT0_READ_LOCK, 0x0ccu) +REG32(PLAT_OWNER_AUTH_SLOT1_READ_LOCK, 0x0d0u) +REG32(PLAT_OWNER_AUTH_SLOT2_READ_LOCK, 0x0d4u) +REG32(PLAT_OWNER_AUTH_SLOT3_READ_LOCK, 0x0d8u) +REG32(EXT_NVM_READ_LOCK, 0x0dcu) +REG32(ROM_PATCH_READ_LOCK, 0x0e0u) +REG32(VENDOR_TEST_DIGEST_0, 0x0e4u) +REG32(VENDOR_TEST_DIGEST_1, 0x0e8u) +REG32(CREATOR_SW_CFG_DIGEST_0, 0x0ecu) +REG32(CREATOR_SW_CFG_DIGEST_1, 0x0f0u) +REG32(OWNER_SW_CFG_DIGEST_0, 0x0f4u) +REG32(OWNER_SW_CFG_DIGEST_1, 0x0f8u) +REG32(ROT_CREATOR_AUTH_DIGEST_0, 0x0fcu) REG32(ROT_CREATOR_AUTH_DIGEST_1, 0x100u) -REG32(ROT_OWNER_AUTH_SLOT0_DIGEST_0, 0x104) +REG32(ROT_OWNER_AUTH_SLOT0_DIGEST_0, 0x104u) REG32(ROT_OWNER_AUTH_SLOT0_DIGEST_1, 0x108u) REG32(ROT_OWNER_AUTH_SLOT1_DIGEST_0, 0x10cu) REG32(ROT_OWNER_AUTH_SLOT1_DIGEST_1, 0x110u) @@ -215,189 +219,129 @@ REG32(SECRET3_DIGEST_1, 0x178u) /* Software Config Window registers (at offset SW_CFG_WINDOW = +0x4000) */ REG32(VENDOR_TEST_SCRATCH, 0u) REG32(VENDOR_TEST_DIGEST, 56u) -REG32(CREATOR_SW_CFG_DIO_ATTR, 64u) -REG32(CREATOR_SW_CFG_AST, 140u) -REG32(CREATOR_SW_CFG_AST_CFG, 140u) -REG32(CREATOR_SW_CFG_AST_SPARES, 160u) -REG32(CREATOR_SW_CFG_AST_AVGSFUSECTL, 174u) -REG32(CREATOR_SW_CFG_AST_AVGSHDRCFG, 178u) -REG32(CREATOR_SW_CFG_AST_RINGOSC_TRIM_CTL, 181u) -REG32(CREATOR_SW_CFG_AST_RINGOSC_FREQ_COUNT_CTL, 182u) -REG32(CREATOR_SW_CFG_AST_RINGOSC_FREQ_TH_SLOW, 184u) -REG32(CREATOR_SW_CFG_AST_RINGOSC_FREQ_TH_FAST, 186u) +REG32(CREATOR_SW_CFG_AST_CFG, 64u) REG32(CREATOR_SW_CFG_AST_INIT_EN, 188u) REG32(CREATOR_SW_CFG_OVERRIDES, 192u) -REG32(CREATOR_SW_CFG_ROM_PERMISSIVE_SECURITY, 224u) -REG32(CREATOR_SW_CFG_BOOTSTRAP_FW_OWNERS_MASK, 228u) -REG32(CREATOR_SW_CFG_ROM_EXT_OWNERS_MASK, 232u) -REG32(CREATOR_SW_CFG_ROM_EXT_SKU, 236u) -REG32(CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN, 240u) -REG32(CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN, 244u) -REG32(CREATOR_SW_CFG_SIGVERIFY_SPX_EN, 252u) -REG32(CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN, 256u) -REG32(CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG, 264u) -REG32(CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG, 268u) -REG32(CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE, 272u) -REG32(CREATOR_SW_CFG_RNG_EN, 276u) -REG32(CREATOR_SW_CFG_JITTER_EN, 280u) -REG32(CREATOR_SW_CFG_RET_RAM_RESET_MASK, 284u) -REG32(CREATOR_SW_CFG_MANUF_STATE, 288u) -REG32(CREATOR_SW_CFG_ROM_EXEC_EN, 292u) -REG32(CREATOR_SW_CFG_CPUCTRL, 296u) -REG32(CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT, 300u) -REG32(CREATOR_SW_CFG_MIN_SEC_VER_BL0, 304u) -REG32(CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN, 308u) -REG32(CREATOR_SW_CFG_RMA_SPIN_EN, 312u) -REG32(CREATOR_SW_CFG_RMA_SPIN_CYCLES, 316u) -REG32(CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS, 320u) -REG32(CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS, 324u) -REG32(CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS, 328u) -REG32(CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS, 332u) -REG32(CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS, 336u) -REG32(CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS, 340u) -REG32(CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS, 344u) -REG32(CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS, 348u) -REG32(CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS, 352u) -REG32(CREATOR_SW_CFG_RNG_ALERT_THRESHOLD, 356u) -REG32(CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST, 360u) -REG32(CREATOR_SW_CFG_SRAM_KEY_RENEW_EN, 364u) -REG32(CREATOR_SW_CFG_DIGEST, 392u) -REG32(OWNER_SW_CFG_ROM_ERROR_REPORTING, 400u) -REG32(OWNER_SW_CFG_ROM_BOOTSTRAP_DIS, 404u) -REG32(OWNER_SW_CFG_ROM_ALERT_CLASS_EN, 408u) -REG32(OWNER_SW_CFG_ROM_ALERT_ESCALATION, 412u) -REG32(OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION, 416u) -REG32(OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION, 816u) -REG32(OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH, 880u) -REG32(OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES, 896u) -REG32(OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES, 912u) -REG32(OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD, 976u) -REG32(OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END, 980u) -REG32(OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV, 984u) -REG32(OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA, 988u) -REG32(OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES, 992u) -REG32(OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN, 996u) -REG32(OWNER_SW_CFG_MANUF_STATE, 1000u) -REG32(OWNER_SW_CFG_ROM_RSTMGR_INFO_EN, 1004u) -REG32(OWNER_SW_CFG_DIGEST, 1024u) -REG32(OWNERSHIP_SLOT_STATE_ROT_OWNER_AUTH, 1032u) -REG32(OWNERSHIP_SLOT_STATE_PLAT_INTEG_AUTH, 1048u) -REG32(OWNERSHIP_SLOT_STATE_PLAT_OWNER_AUTH, 1064u) -REG32(ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY_TYPE, 1080u) -REG32(ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY_ROLE, 1084u) -REG32(ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY, 1088u) -REG32(ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY_TYPE, 1152u) -REG32(ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY_ROLE, 1156u) -REG32(ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY, 1160u) -REG32(ROT_CREATOR_AUTH_KEYMANIFEST_KEY_TYPE, 1224u) -REG32(ROT_CREATOR_AUTH_KEYMANIFEST_KEY_ROLE, 1228u) -REG32(ROT_CREATOR_AUTH_KEYMANIFEST_KEY, 1232u) -REG32(ROT_CREATOR_AUTH_KEY_DEVICE_ID, 1296u) -REG32(ROT_CREATOR_AUTH_KEY_METADATA, 1328u) -REG32(ROT_CREATOR_AUTH_KEY_SIGNATURE, 1344u) -REG32(ROT_CREATOR_AUTH_IDENTITY_CERT, 1408u) -REG32(ROT_CREATOR_AUTH_IDENTITY_CERT_CMAC, 2176u) -REG32(ROT_CREATOR_AUTH_DIGEST, 2496u) -REG32(ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_TYPE, 2504u) -REG32(ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_ROLE, 2508u) -REG32(ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY, 2512u) -REG32(ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_TYPE, 2576u) -REG32(ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_ROLE, 2580u) -REG32(ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY, 2584u) -REG32(ROT_OWNER_AUTH_SLOT0_DIGEST, 2824u) -REG32(ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_TYPE, 2832u) -REG32(ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_ROLE, 2836u) -REG32(ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY, 2840u) -REG32(ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_TYPE, 2904u) -REG32(ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_ROLE, 2908u) -REG32(ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY, 2912u) -REG32(ROT_OWNER_AUTH_SLOT1_DIGEST, 3152u) -REG32(PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY_TYPE, 3160u) -REG32(PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY_ROLE, 3164u) -REG32(PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY, 3168u) -REG32(PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY_TYPE, 3232u) -REG32(PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY_ROLE, 3236u) -REG32(PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY, 3240u) -REG32(PLAT_INTEG_AUTH_SLOT0_DIGEST, 3480u) -REG32(PLAT_INTEG_AUTH_SLOT1, 3488u) -REG32(PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY_TYPE, 3488u) -REG32(PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY_ROLE, 3492u) -REG32(PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY, 3496u) -REG32(PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY_TYPE, 3560u) -REG32(PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY_ROLE, 3564u) -REG32(PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY, 3568u) -REG32(PLAT_INTEG_AUTH_SLOT1_DIGEST, 3808u) -REG32(PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_TYPE, 3816u) -REG32(PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_ROLE, 3820u) -REG32(PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY, 3824u) -REG32(PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_TYPE, 3888u) -REG32(PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_ROLE, 3892u) -REG32(PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY, 3896u) -REG32(PLAT_OWNER_AUTH_SLOT0_DIGEST, 4136u) -REG32(PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_TYPE, 4144u) -REG32(PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_ROLE, 4148u) -REG32(PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY, 4152u) -REG32(PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_TYPE, 4216u) -REG32(PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_ROLE, 4220u) -REG32(PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY, 4224u) -REG32(PLAT_OWNER_AUTH_SLOT1_DIGEST, 4464u) -REG32(PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY_TYPE, 4472u) -REG32(PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY_ROLE, 4476u) -REG32(PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY, 4480u) -REG32(PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY_TYPE, 4544u) -REG32(PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY_ROLE, 4548u) -REG32(PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY, 4552u) -REG32(PLAT_OWNER_AUTH_SLOT2_DIGEST, 4792u) -REG32(PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY_TYPE, 4800u) -REG32(PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY_ROLE, 4804u) -REG32(PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY, 4808u) -REG32(PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY_TYPE, 4872u) -REG32(PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY_ROLE, 4876u) -REG32(PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY, 4880u) -REG32(PLAT_OWNER_AUTH_SLOT3_DIGEST, 5120u) -REG32(EXT_NVM_ANTIREPLAY_FRESHNESS_CNT, 5128u) -REG32(ROM_PATCH_DATA, 6152u) -REG32(ROM_PATCH_DIGEST, 15912u) -REG32(HW_CFG0_DEVICE_ID, 15920u) -REG32(HW_CFG0_MANUF_STATE, 15952u) -REG32(HW_CFG0_DIGEST, 15984u) -REG32(HW_CFG1_SOC_DBG_STATE, 15992u) -REG32(HW_CFG1_EN_SRAM_IFETCH, 15996u) -REG32(HW_CFG1_DIGEST, 16000u) -REG32(SECRET0_TEST_UNLOCK_TOKEN, 16008u) -REG32(SECRET0_TEST_EXIT_TOKEN, 16024u) -REG32(SECRET0_DIGEST, 16040u) -REG32(SECRET1_FLASH_ADDR_KEY_SEED, 16048u) -REG32(SECRET1_FLASH_DATA_KEY_SEED, 16080u) -REG32(SECRET1_SRAM_DATA_KEY_SEED, 16112u) -REG32(SECRET1_DIGEST, 16128u) -REG32(SECRET2_RMA_TOKEN, 16136u) -REG32(SECRET2_CREATOR_ROOT_KEY_SHARE0, 16152u) -REG32(SECRET2_CREATOR_ROOT_KEY_SHARE1, 16184u) -REG32(SECRET2_CREATOR_SEED, 16216u) -REG32(SECRET2_DIGEST, 16248u) -REG32(SECRET3_OWNER_SEED, 16256u) -REG32(SECRET3_DIGEST, 16288u) +REG32(CREATOR_SW_CFG_ROM_EXT_SKU, 224u) +REG32(CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN, 228u) +REG32(CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN, 232u) +REG32(CREATOR_SW_CFG_SIGVERIFY_SPX_EN, 240u) +REG32(CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN, 244u) +REG32(CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG, 252u) +REG32(CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG, 256u) +REG32(CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE, 260u) +REG32(CREATOR_SW_CFG_RNG_EN, 264u) +REG32(CREATOR_SW_CFG_JITTER_EN, 268u) +REG32(CREATOR_SW_CFG_RET_RAM_RESET_MASK, 272u) +REG32(CREATOR_SW_CFG_MANUF_STATE, 276u) +REG32(CREATOR_SW_CFG_ROM_EXEC_EN, 280u) +REG32(CREATOR_SW_CFG_CPUCTRL, 284u) +REG32(CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT, 288u) +REG32(CREATOR_SW_CFG_MIN_SEC_VER_BL0, 292u) +REG32(CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN, 296u) +REG32(CREATOR_SW_CFG_RMA_SPIN_EN, 300u) +REG32(CREATOR_SW_CFG_RMA_SPIN_CYCLES, 304u) +REG32(CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS, 308u) +REG32(CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS, 312u) +REG32(CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS, 316u) +REG32(CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS, 320u) +REG32(CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS, 324u) +REG32(CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS, 328u) +REG32(CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS, 332u) +REG32(CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS, 336u) +REG32(CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS, 340u) +REG32(CREATOR_SW_CFG_RNG_ALERT_THRESHOLD, 344u) +REG32(CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST, 348u) +REG32(CREATOR_SW_CFG_SRAM_KEY_RENEW_EN, 352u) +REG32(CREATOR_SW_CFG_DIGEST, 360u) +REG32(OWNER_SW_CFG_ROM_ERROR_REPORTING, 368u) +REG32(OWNER_SW_CFG_ROM_BOOTSTRAP_DIS, 372u) +REG32(OWNER_SW_CFG_ROM_ALERT_CLASS_EN, 376u) +REG32(OWNER_SW_CFG_ROM_ALERT_ESCALATION, 380u) +REG32(OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION, 384u) +REG32(OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION, 804u) +REG32(OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH, 832u) +REG32(OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES, 848u) +REG32(OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES, 864u) +REG32(OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD, 928u) +REG32(OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END, 932u) +REG32(OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV, 936u) +REG32(OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA, 940u) +REG32(OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES, 944u) +REG32(OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN, 948u) +REG32(OWNER_SW_CFG_MANUF_STATE, 952u) +REG32(OWNER_SW_CFG_ROM_RSTMGR_INFO_EN, 956u) +REG32(OWNER_SW_CFG_DIGEST, 960u) +REG32(OWNERSHIP_SLOT_STATE_ROT_OWNER_AUTH, 968u) +REG32(OWNERSHIP_SLOT_STATE_PLAT_INTEG_AUTH, 984u) +REG32(OWNERSHIP_SLOT_STATE_PLAT_OWNER_AUTH, 1000u) +REG32(ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY, 1016u) +REG32(ROT_CREATOR_AUTH_OWNERSHIP_STATE, 1176u) +REG32(ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY, 1180u) +REG32(ROT_CREATOR_AUTH_KEYMANIFEST_KEY, 1340u) +REG32(ROT_CREATOR_AUTH_UNLOCK4XFER_KEY, 1500u) +REG32(ROT_CREATOR_AUTH_IDENTITY_CERT, 1660u) +REG32(ROT_CREATOR_AUTH_DIGEST, 2432u) +REG32(ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY, 2440u) +REG32(ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY, 2600u) +REG32(ROT_OWNER_AUTH_SLOT0_DIGEST, 2760u) +REG32(ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY, 2768u) +REG32(ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY, 2928u) +REG32(ROT_OWNER_AUTH_SLOT1_DIGEST, 3088u) +REG32(PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY, 3096u) +REG32(PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY, 3256u) +REG32(PLAT_INTEG_AUTH_SLOT0_DIGEST, 3416u) +REG32(PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY, 3424u) +REG32(PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY, 3584u) +REG32(PLAT_INTEG_AUTH_SLOT1_DIGEST, 3744u) +REG32(PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY, 3752u) +REG32(PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY, 3912u) +REG32(PLAT_OWNER_AUTH_SLOT0_DIGEST, 4072u) +REG32(PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY, 4080u) +REG32(PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY, 4240u) +REG32(PLAT_OWNER_AUTH_SLOT1_DIGEST, 4400u) +REG32(PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY, 4408u) +REG32(PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY, 4568u) +REG32(PLAT_OWNER_AUTH_SLOT2_DIGEST, 4728u) +REG32(PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY, 4736u) +REG32(PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY, 4896u) +REG32(PLAT_OWNER_AUTH_SLOT3_DIGEST, 5056u) +REG32(EXT_NVM_ANTIREPLAY_FRESHNESS_CNT, 5064u) +REG32(ROM_PATCH_DATA, 6088u) +REG32(ROM_PATCH_DIGEST, 15944u) +REG32(HW_CFG0_DEVICE_ID, 15952u) +REG32(HW_CFG0_MANUF_STATE, 15984u) +REG32(HW_CFG0_DIGEST, 16016u) +REG32(HW_CFG1_SOC_DBG_STATE, 16024u) +REG32(HW_CFG1_EN_CSRNG_SW_APP_READ, 16028u) +REG32(HW_CFG1_EN_SRAM_IFETCH, 16029u) +REG32(HW_CFG1_DIGEST, 16032u) +REG32(SECRET0_TEST_UNLOCK_TOKEN, 16040u) +REG32(SECRET0_TEST_EXIT_TOKEN, 16056u) +REG32(SECRET0_DIGEST, 16072u) +REG32(SECRET0_ZER, 16080u) +REG32(SECRET1_SRAM_DATA_KEY_SEED, 16088u) +REG32(SECRET1_DIGEST, 16104u) +REG32(SECRET1_ZER, 16112u) +REG32(SECRET2_RMA_TOKEN, 16120u) +REG32(SECRET2_CREATOR_ROOT_KEY_SHARE0, 16136u) +REG32(SECRET2_CREATOR_ROOT_KEY_SHARE1, 16168u) +REG32(SECRET2_CREATOR_SEED, 16200u) +REG32(SECRET2_DIGEST, 16232u) +REG32(SECRET2_ZER, 16240u) +REG32(SECRET3_OWNER_SEED, 16248u) +REG32(SECRET3_DIGEST, 16280u) +REG32(SECRET3_ZER, 16288u) REG32(LC_TRANSITION_CNT, 16296u) REG32(LC_STATE, 16344u) /* clang-format on */ +#define VENDOR_TEST_SIZE 64u #define VENDOR_TEST_SCRATCH_SIZE 56u -#define CREATOR_SW_CFG_DIO_ATTR_SIZE 76u -#define CREATOR_SW_CFG_AST_SIZE 52u -#define CREATOR_SW_CFG_AST_CFG_SIZE 20u -#define CREATOR_SW_CFG_AST_SPARES_SIZE 14u -#define CREATOR_SW_CFG_AST_AVGSFUSECTL_SIZE 4u -#define CREATOR_SW_CFG_AST_AVGSHDRCFG_SIZE 3u -#define CREATOR_SW_CFG_AST_RINGOSC_TRIM_CTL_SIZE 1u -#define CREATOR_SW_CFG_AST_RINGOSC_FREQ_COUNT_CTL_SIZE 2u -#define CREATOR_SW_CFG_AST_RINGOSC_FREQ_TH_SLOW_SIZE 2u -#define CREATOR_SW_CFG_AST_RINGOSC_FREQ_TH_FAST_SIZE 2u +#define CREATOR_SW_CFG_SIZE 304u +#define CREATOR_SW_CFG_AST_CFG_SIZE 124u #define CREATOR_SW_CFG_AST_INIT_EN_SIZE 4u #define CREATOR_SW_CFG_OVERRIDES_SIZE 32u -#define CREATOR_SW_CFG_ROM_PERMISSIVE_SECURITY_SIZE 4u -#define CREATOR_SW_CFG_BOOTSTRAP_FW_OWNERS_MASK_SIZE 4u -#define CREATOR_SW_CFG_ROM_EXT_OWNERS_MASK_SIZE 4u #define CREATOR_SW_CFG_ROM_EXT_SKU_SIZE 4u #define CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN_SIZE 4u #define CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN_SIZE 8u @@ -427,13 +371,15 @@ REG32(LC_STATE, 16344u) #define CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS_SIZE 4u #define CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS_SIZE 4u #define CREATOR_SW_CFG_RNG_ALERT_THRESHOLD_SIZE 4u +#define CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST_SIZE 4u #define CREATOR_SW_CFG_SRAM_KEY_RENEW_EN_SIZE 4u +#define OWNER_SW_CFG_SIZE 600u #define OWNER_SW_CFG_ROM_ERROR_REPORTING_SIZE 4u #define OWNER_SW_CFG_ROM_BOOTSTRAP_DIS_SIZE 4u #define OWNER_SW_CFG_ROM_ALERT_CLASS_EN_SIZE 4u #define OWNER_SW_CFG_ROM_ALERT_ESCALATION_SIZE 4u -#define OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION_SIZE 400u -#define OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION_SIZE 64u +#define OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION_SIZE 420u +#define OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION_SIZE 28u #define OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH_SIZE 16u #define OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES_SIZE 16u #define OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES_SIZE 64u @@ -445,96 +391,82 @@ REG32(LC_STATE, 16344u) #define OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN_SIZE 4u #define OWNER_SW_CFG_MANUF_STATE_SIZE 4u #define OWNER_SW_CFG_ROM_RSTMGR_INFO_EN_SIZE 4u +#define OWNERSHIP_SLOT_STATE_SIZE 48u #define OWNERSHIP_SLOT_STATE_ROT_OWNER_AUTH_SIZE 16u #define OWNERSHIP_SLOT_STATE_PLAT_INTEG_AUTH_SIZE 16u #define OWNERSHIP_SLOT_STATE_PLAT_OWNER_AUTH_SIZE 16u -#define ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY_TYPE_SIZE 4u -#define ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY_ROLE_SIZE 4u -#define ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY_SIZE 64u -#define ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY_TYPE_SIZE 4u -#define ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY_ROLE_SIZE 4u -#define ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY_SIZE 64u -#define ROT_CREATOR_AUTH_KEYMANIFEST_KEY_TYPE_SIZE 4u -#define ROT_CREATOR_AUTH_KEYMANIFEST_KEY_ROLE_SIZE 4u -#define ROT_CREATOR_AUTH_KEYMANIFEST_KEY_SIZE 64u -#define ROT_CREATOR_AUTH_KEY_DEVICE_ID_SIZE 32u -#define ROT_CREATOR_AUTH_KEY_METADATA_SIZE 16u -#define ROT_CREATOR_AUTH_KEY_SIGNATURE_SIZE 64u +#define ROT_CREATOR_AUTH_SIZE 1424u +#define ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY_SIZE 160u +#define ROT_CREATOR_AUTH_OWNERSHIP_STATE_SIZE 4u +#define ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY_SIZE 160u +#define ROT_CREATOR_AUTH_KEYMANIFEST_KEY_SIZE 160u +#define ROT_CREATOR_AUTH_UNLOCK4XFER_KEY_SIZE 160u #define ROT_CREATOR_AUTH_IDENTITY_CERT_SIZE 768u -#define ROT_CREATOR_AUTH_IDENTITY_CERT_CMAC_SIZE 16u -#define ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_TYPE_SIZE 4u -#define ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_ROLE_SIZE 4u -#define ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_SIZE 64u -#define ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_TYPE_SIZE 4u -#define ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_ROLE_SIZE 4u -#define ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_SIZE 64u -#define ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_TYPE_SIZE 4u -#define ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_ROLE_SIZE 4u -#define ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_SIZE 64u -#define ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_TYPE_SIZE 4u -#define ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_ROLE_SIZE 4u -#define ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_SIZE 64u -#define PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY_TYPE_SIZE 4u -#define PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY_ROLE_SIZE 4u -#define PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY_SIZE 64u -#define PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY_TYPE_SIZE 4u -#define PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY_ROLE_SIZE 4u -#define PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY_SIZE 64u -#define PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY_TYPE_SIZE 4u -#define PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY_ROLE_SIZE 4u -#define PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY_SIZE 64u -#define PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY_TYPE_SIZE 4u -#define PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY_ROLE_SIZE 4u -#define PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY_SIZE 64u -#define PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_TYPE_SIZE 4u -#define PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_ROLE_SIZE 4u -#define PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_SIZE 64u -#define PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_TYPE_SIZE 4u -#define PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_ROLE_SIZE 4u -#define PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_SIZE 64u -#define PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_TYPE_SIZE 4u -#define PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_ROLE_SIZE 4u -#define PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_SIZE 64u -#define PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_TYPE_SIZE 4u -#define PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_ROLE_SIZE 4u -#define PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_SIZE 64u -#define PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY_TYPE_SIZE 4u -#define PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY_ROLE_SIZE 4u -#define PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY_SIZE 64u -#define PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY_TYPE_SIZE 4u -#define PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY_ROLE_SIZE 4u -#define PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY_SIZE 64u -#define PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY_TYPE_SIZE 4u -#define PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY_ROLE_SIZE 4u -#define PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY_SIZE 64u -#define PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY_TYPE_SIZE 4u -#define PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY_ROLE_SIZE 4u -#define PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY_SIZE 64u +#define ROT_OWNER_AUTH_SLOT0_SIZE 328u +#define ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_SIZE 160u +#define ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_SIZE 160u +#define ROT_OWNER_AUTH_SLOT1_SIZE 328u +#define ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_SIZE 160u +#define ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_SIZE 160u +#define PLAT_INTEG_AUTH_SLOT0_SIZE 328u +#define PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY_SIZE 160u +#define PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY_SIZE 160u +#define PLAT_INTEG_AUTH_SLOT1_SIZE 328u +#define PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY_SIZE 160u +#define PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY_SIZE 160u +#define PLAT_OWNER_AUTH_SLOT0_SIZE 328u +#define PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_SIZE 160u +#define PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_SIZE 160u +#define PLAT_OWNER_AUTH_SLOT1_SIZE 328u +#define PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_SIZE 160u +#define PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_SIZE 160u +#define PLAT_OWNER_AUTH_SLOT2_SIZE 328u +#define PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY_SIZE 160u +#define PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY_SIZE 160u +#define PLAT_OWNER_AUTH_SLOT3_SIZE 328u +#define PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY_SIZE 160u +#define PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY_SIZE 160u +#define EXT_NVM_SIZE 1024u #define EXT_NVM_ANTIREPLAY_FRESHNESS_CNT_SIZE 1024u +#define ROM_PATCH_SIZE 9864u #define ROM_PATCH_DATA_SIZE 9192u +#define HW_CFG0_SIZE 72u #define HW_CFG0_DEVICE_ID_SIZE 32u #define HW_CFG0_MANUF_STATE_SIZE 32u +#define HW_CFG1_SIZE 16u #define HW_CFG1_SOC_DBG_STATE_SIZE 4u +#define HW_CFG1_EN_CSRNG_SW_APP_READ_SIZE 1u #define HW_CFG1_EN_SRAM_IFETCH_SIZE 1u +#define SECRET0_SIZE 48u #define SECRET0_TEST_UNLOCK_TOKEN_SIZE 16u #define SECRET0_TEST_EXIT_TOKEN_SIZE 16u -#define SECRET1_FLASH_ADDR_KEY_SEED_SIZE 32u -#define SECRET1_FLASH_DATA_KEY_SEED_SIZE 32u +#define SECRET1_SIZE 32u #define SECRET1_SRAM_DATA_KEY_SEED_SIZE 16u +#define SECRET2_SIZE 128u #define SECRET2_RMA_TOKEN_SIZE 16u #define SECRET2_CREATOR_ROOT_KEY_SHARE0_SIZE 32u #define SECRET2_CREATOR_ROOT_KEY_SHARE1_SIZE 32u #define SECRET2_CREATOR_SEED_SIZE 32u +#define SECRET3_SIZE 48u #define SECRET3_OWNER_SEED_SIZE 32u +#define LIFE_CYCLE_SIZE 88u #define LC_TRANSITION_CNT_SIZE 48u #define LC_STATE_SIZE 40u -#define INTR_MASK (INTR_OTP_OPERATION_DONE_MASK | INTR_OTP_ERROR_MASK) -#define ALERT_TEST_MASK \ +#define INTR_WMASK (INTR_OTP_OPERATION_DONE_MASK | INTR_OTP_ERROR_MASK) + +#define ALERT_WMASK \ (ALERT_FATAL_MACRO_ERROR_MASK | ALERT_FATAL_CHECK_ERROR_MASK | \ ALERT_FATAL_BUS_INTEG_ERROR_MASK | ALERT_FATAL_PRIM_OTP_ALERT_MASK | \ ALERT_RECOV_PRIM_OTP_ALERT_MASK) +#define DIRECT_ACCESS_CMD_WMASK \ + (R_DIRECT_ACCESS_CMD_RD_MASK | R_DIRECT_ACCESS_CMD_WR_MASK | \ + R_DIRECT_ACCESS_CMD_DIGEST_MASK | R_DIRECT_ACCESS_CMD_ZEROIZE_MASK) + +#define CHECK_TRIGGER_WMASK \ + (R_CHECK_TRIGGER_INTEGRITY_MASK | R_CHECK_TRIGGER_CONSISTENCY_MASK) + #define SW_CFG_WINDOW 0x4000u #define SW_CFG_WINDOW_SIZE (NUM_SW_CFG_WINDOW_WORDS * sizeof(uint32_t)) @@ -603,12 +535,14 @@ typedef enum { OTP_PART_SECRET2, OTP_PART_SECRET3, OTP_PART_LIFE_CYCLE, - OTP_PART_COUNT, - OTP_ENTRY_DAI = OTP_PART_COUNT, /* Fake partitions for error (...) */ + OTP_PART_OTP_COUNT, /* count of "real" OTP partitions */ + OTP_ENTRY_DAI = OTP_PART_OTP_COUNT, /* Fake partitions for error (...) */ OTP_ENTRY_KDI, /* Key derivation issue, not really OTP */ OTP_ENTRY_COUNT, } OtOTPPartitionType; +static_assert(OTP_PART_OTP_COUNT == NUM_PART, "Invalid partition count"); + /* Error code (compliant with ERR_CODE registers) */ typedef enum { OTP_NO_ERROR, @@ -689,6 +623,7 @@ typedef struct { uint16_t size; uint16_t offset; uint16_t digest_offset; + uint16_t zer_offset; uint16_t hw_digest:1; uint16_t sw_digest:1; uint16_t secret:1; @@ -697,6 +632,7 @@ typedef struct { uint16_t read_lock:1; uint16_t read_lock_csr:1; uint16_t integrity:1; + uint16_t zeroizable:1; uint16_t iskeymgr_creator:1; uint16_t iskeymgr_owner:1; } OtOTPPartDesc; @@ -708,14 +644,11 @@ typedef struct { /* NOLINTNEXTLINE */ #include "ot_otp_dj_parts.c" -static_assert(OTP_PART_COUNT == NUM_PART, "Invalid partition definitions"); -static_assert(OTP_PART_COUNT == OTP_PART_COUNT, - "Invalid partition definitions"); -static_assert(NUM_PART_UNBUF + NUM_PART_BUF == NUM_PART, "Invalid partitions"); -static_assert(NUM_ERROR_ENTRIES == OTP_ENTRY_COUNT, "Invalid entries"); -static_assert(NUM_PART <= 64, "Maximum part count reached"); +static_assert(OTP_PART_COUNT <= 64, "Maximum part count reached"); +static_assert(OTP_PART_OTP_COUNT == OTP_PART_COUNT, "Invalid partition count"); #define OTP_DIGEST_ADDR_MASK (sizeof(uint64_t) - 1u) +#define OTP_ZER_ADDR_MASK (sizeof(uint64_t) - 1u) static_assert(OTP_BYTE_ADDR_WIDTH == R_DIRECT_ACCESS_ADDRESS_ADDRESS_LENGTH, "OTP byte address width mismatch"); @@ -1072,12 +1005,6 @@ ot_otp_dj_lci_change_state_line(OtOTPDjState *s, OtOTPLCIState state, int line); #define LCI_CHANGE_STATE(_s_, _st_) \ ot_otp_dj_lci_change_state_line(_s_, _st_, __LINE__) -#define OT_OTP_PART_DATA_OFFSET(_pix_) \ - ((unsigned)(OtOTPPartDescs[(_pix_)].offset)) -#define OT_OTP_PART_DATA_BYTE_SIZE(_pix_) \ - ((unsigned)(OtOTPPartDescs[(_pix_)].size - \ - sizeof(uint32_t) * NUM_DIGEST_WORDS)) - #ifdef OT_OTP_DEBUG #define OT_OTP_HEXSTR_SIZE 256u #define TRACE_OTP(msg, ...) qemu_log("%s: " msg "\n", __func__, ##__VA_ARGS__); @@ -1089,6 +1016,26 @@ ot_otp_dj_lci_change_state_line(OtOTPDjState *s, OtOTPLCIState state, int line); #define ot_otp_hexdump(_s_, _b_, _l_) #endif +static inline unsigned ot_otp_dj_part_data_offset(unsigned pix) +{ + return (unsigned)(OtOTPPartDescs[pix].offset); +} + +static inline unsigned ot_otp_dj_part_data_byte_size(unsigned pix) +{ + size_t size = OtOTPPartDescs[pix].size; + + if (OtOTPPartDescs[pix].hw_digest || OtOTPPartDescs[pix].sw_digest) { + size -= sizeof(uint32_t) * NUM_DIGEST_WORDS; + } + + if (OtOTPPartDescs[pix].zeroizable) { + size -= sizeof(uint32_t) * NUM_ZER_WORDS; + } + + return (unsigned)size; +} + static void ot_otp_dj_update_irqs(OtOTPDjState *s) { uint32_t levels = s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE]; @@ -1196,8 +1143,7 @@ static void ot_otp_dj_disable_all_partitions(OtOTPDjState *s) static void ot_otp_dj_set_error(OtOTPDjState *s, unsigned part, OtOTPError err) { - /* This is in NUM_ERROR_ENTRIES */ - g_assert(part < NUM_ERROR_ENTRIES); + g_assert(part < OTP_ENTRY_COUNT); uint32_t errval = ((uint32_t)err) & ERR_CODE_MASK; if (errval || errval != s->regs[R_ERR_CODE_0 + part]) { @@ -1275,37 +1221,6 @@ static int ot_otp_dj_get_part_from_address(const OtOTPDjState *s, hwaddr addr) return -1; } -static uint16_t ot_otp_dj_get_part_digest_offset(int part) -{ - switch (part) { - case OTP_PART_VENDOR_TEST: - case OTP_PART_CREATOR_SW_CFG: - case OTP_PART_OWNER_SW_CFG: - case OTP_PART_OWNERSHIP_SLOT_STATE: - case OTP_PART_ROT_CREATOR_AUTH: - case OTP_PART_ROT_OWNER_AUTH_SLOT0: - case OTP_PART_ROT_OWNER_AUTH_SLOT1: - case OTP_PART_PLAT_INTEG_AUTH_SLOT0: - case OTP_PART_PLAT_INTEG_AUTH_SLOT1: - case OTP_PART_PLAT_OWNER_AUTH_SLOT0: - case OTP_PART_PLAT_OWNER_AUTH_SLOT1: - case OTP_PART_PLAT_OWNER_AUTH_SLOT2: - case OTP_PART_PLAT_OWNER_AUTH_SLOT3: - case OTP_PART_EXT_NVM: - case OTP_PART_ROM_PATCH: - case OTP_PART_HW_CFG0: - case OTP_PART_HW_CFG1: - case OTP_PART_SECRET0: - case OTP_PART_SECRET1: - case OTP_PART_SECRET2: - case OTP_PART_SECRET3: - case OTP_PART_LIFE_CYCLE: - return OtOTPPartDescs[part].digest_offset; - default: - return UINT16_MAX; - } -} - static uint8_t ot_otp_dj_compute_ecc_u16(uint16_t data) { uint32_t data_o = (uint32_t)data; @@ -1491,7 +1406,7 @@ static uint64_t ot_otp_dj_get_part_digest(OtOTPDjState *s, int part) { g_assert(!ot_otp_dj_is_buffered(part)); - uint16_t offset = ot_otp_dj_get_part_digest_offset(part); + uint16_t offset = OtOTPPartDescs[part].digest_offset; if (offset == UINT16_MAX) { return 0u; @@ -1522,11 +1437,85 @@ static uint64_t ot_otp_dj_get_buffered_part_digest(OtOTPDjState *s, int part) static bool ot_otp_dj_is_part_digest_offset(int part, hwaddr addr) { - uint16_t offset = ot_otp_dj_get_part_digest_offset(part); + uint16_t offset = OtOTPPartDescs[part].digest_offset; return (offset != UINT16_MAX) && ((addr & ~OTP_DIGEST_ADDR_MASK) == offset); } +static bool ot_otp_dj_is_part_zer_offset(int part, hwaddr addr) +{ + uint16_t offset = OtOTPPartDescs[part].zer_offset; + + return (offset != UINT16_MAX) && ((addr & ~OTP_ZER_ADDR_MASK) == offset); +} + +static uint32_t ot_otp_dj_get_part_digest_reg(OtOTPDjState *s, uint32_t offset) +{ + /* + * Offset is the register offset from the first read 32-bit digest register. + * All digests are 64-bits, which means each partition have two 32-bit + * registers to expose their digest. + * + * Not all partitions have digests, which means the offset argument is the + * relative partition offset for those partitions that features a digest, as + * there is no defined digest access registers defined for partitions that + * do not have a digest. + * + * Need to traverse the partition table to only account for those partitions + * with a digest to match the proper offset. + */ + + /* + * part_look_ix is the index of the partition in the contiguous array of + * digest registers, which would be equivalent as the index of the partition + * that would exist in a virtual partition-with-digest array. + */ + unsigned part_look_ix = (int)(offset / NUM_DIGEST_WORDS); + /* whether to retrieve the top most 32-bit of the digest or not */ + bool hi = (bool)(offset & 0x1u); + + /* part_ix: the partition number in the global partition array */ + unsigned part_ix = 0; + /* traverse the partition array and count each partition with a digest */ + for (unsigned part_dig_ix = 0; part_ix < OTP_PART_COUNT; part_ix++) { + if (ot_otp_dj_has_digest(part_ix)) { + /* + * stop searching if we've found the part-with-digest defined from + * the offset argument. Otherwise, increment the part-with-digest + * index and continue. + */ + if (part_dig_ix == part_look_ix) { + break; + } + part_dig_ix++; + } + } + + /* + * If the part_ix as reached the latest partition, there is something wrong + * with the partition table or the register definitions, as it is assumed + * that LifeCycle partition is the last partition. + */ + static_assert(OTP_PART_LIFE_CYCLE == NUM_PART - 1, + "LC is expected to be the last partition"); + g_assert(part_ix < OTP_PART_COUNT); + + const OtOTPPartDesc *part = &OtOTPPartDescs[part_ix]; + uint64_t digest; + + if (part->buffered) { + digest = ot_otp_dj_get_buffered_part_digest(s, (int)part_ix); + } else { + digest = ot_otp_dj_get_part_digest(s, (int)part_ix); + } + + if (hi) { + digest >>= 32u; + } + + return (uint32_t)digest; +} + static bool ot_otp_dj_is_readable(OtOTPDjState *s, int partition) { if (OtOTPPartDescs[partition].secret) { @@ -1534,88 +1523,47 @@ static bool ot_otp_dj_is_readable(OtOTPDjState *s, int partition) return ot_otp_dj_get_buffered_part_digest(s, partition) == 0u; } - uint32_t reg; + if (!OtOTPPartDescs[partition].read_lock_csr) { + if (!OtOTPPartDescs[partition].read_lock) { + /* read lock is not supported for this partition */ + return true; + } - switch (partition) { - case OTP_PART_VENDOR_TEST: - reg = R_VENDOR_TEST_READ_LOCK; - break; - case OTP_PART_CREATOR_SW_CFG: - reg = R_CREATOR_SW_CFG_READ_LOCK; - break; - case OTP_PART_OWNER_SW_CFG: - reg = R_OWNER_SW_CFG_READ_LOCK; - break; - case OTP_PART_OWNERSHIP_SLOT_STATE: - reg = R_OWNERSHIP_SLOT_STATE_READ_LOCK; - break; - case OTP_PART_ROT_CREATOR_AUTH: - reg = R_ROT_CREATOR_AUTH_READ_LOCK; - break; - case OTP_PART_ROT_OWNER_AUTH_SLOT0: - reg = R_ROT_OWNER_AUTH_SLOT0_READ_LOCK; - break; - case OTP_PART_ROT_OWNER_AUTH_SLOT1: - reg = R_ROT_OWNER_AUTH_SLOT1_READ_LOCK; - break; - case OTP_PART_PLAT_INTEG_AUTH_SLOT0: - reg = R_PLAT_INTEG_AUTH_SLOT0_READ_LOCK; - break; - case OTP_PART_PLAT_INTEG_AUTH_SLOT1: - reg = R_PLAT_INTEG_AUTH_SLOT1_READ_LOCK; - break; - case OTP_PART_PLAT_OWNER_AUTH_SLOT0: - reg = R_PLAT_OWNER_AUTH_SLOT0_READ_LOCK; - break; - case OTP_PART_PLAT_OWNER_AUTH_SLOT1: - reg = R_PLAT_OWNER_AUTH_SLOT1_READ_LOCK; - break; - case OTP_PART_PLAT_OWNER_AUTH_SLOT2: - reg = R_PLAT_OWNER_AUTH_SLOT2_READ_LOCK; - break; - case OTP_PART_PLAT_OWNER_AUTH_SLOT3: - reg = R_PLAT_OWNER_AUTH_SLOT3_READ_LOCK; - break; - case OTP_PART_EXT_NVM: - reg = R_EXT_NVM_READ_LOCK; - break; - case OTP_PART_ROM_PATCH: - reg = R_ROM_PATCH_READ_LOCK; - break; - case OTP_PART_HW_CFG0: - case OTP_PART_HW_CFG1: - case OTP_PART_SECRET0: - case OTP_PART_SECRET1: - case OTP_PART_SECRET2: - case OTP_PART_SECRET3: - reg = UINT32_MAX; - break; - default: - qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: invalid partition: %d\n", - __func__, s->ot_id, partition); - return false; + /* hw read lock, not locked */ + return !s->partctrls[partition].read_lock; } - if (OtOTPPartDescs[partition].read_lock_csr) { - if (reg == UINT32_MAX) { - error_setg(&error_fatal, "CSR register not defined"); - g_assert_not_reached(); + unsigned roffset = 0; + unsigned pix; + for (pix = 0; pix < OTP_PART_COUNT; pix++) { + if (pix == partition) { + break; + } + if (OtOTPPartDescs[partition].read_lock_csr) { + roffset++; } - return (bool)SHARED_FIELD_EX32(s->regs[reg], READ_LOCK); } + /* + * know for sure last partition is the life cycle one, which never + * support a read_lock_csr. Ideally this g_assert should be a + * static_assert, but C being C, constants are not defined as such + * at build time... + */ + g_assert(!OtOTPPartDescs[OTP_PART_LIFE_CYCLE].read_lock_csr); - if (reg != UINT32_MAX) { - error_setg(&error_fatal, "Unexpected CSR register"); - g_assert_not_reached(); - } + /* + * If the previous loop reached the last partition, something + * seriously wrong occured. Use this feature as a sanity check + */ + g_assert(pix < OTP_PART_LIFE_CYCLE); - if (!OtOTPPartDescs[partition].read_lock) { - /* read lock is not supported for this partition */ - return true; - } + /* + * now that the count of read_lock_csr is known, use it to access + * the register for the selected partition + */ + uint32_t reg = R_VENDOR_TEST_READ_LOCK + roffset; - /* hw read lock, not locked */ - return !s->partctrls[partition].read_lock; + return (bool)SHARED_FIELD_EX32(s->regs[reg], READ_LOCK); } static void @@ -1798,7 +1746,7 @@ static void ot_otp_dj_bufferize_partition(OtOTPDjState *s, unsigned ix) } unsigned offset = (unsigned)OtOTPPartDescs[ix].offset; - unsigned part_size = OT_OTP_PART_DATA_BYTE_SIZE(ix); + unsigned part_size = ot_otp_dj_part_data_byte_size(ix); const uint8_t *base = (const uint8_t *)s->otp->data; base += offset; @@ -1818,7 +1766,7 @@ static void ot_otp_dj_check_partition_integrity(OtOTPDjState *s, unsigned ix) pctrl->locked = true; - unsigned part_size = OT_OTP_PART_DATA_BYTE_SIZE(ix); + unsigned part_size = ot_otp_dj_part_data_byte_size(ix); uint64_t digest = ot_otp_dj_compute_partition_digest(s, (const uint8_t *)pctrl->buffer.data, @@ -1930,11 +1878,15 @@ static void ot_otp_dj_dai_read(OtOTPDjState *s) } bool is_digest = ot_otp_dj_is_part_digest_offset(partition, address); + bool is_zer = ot_otp_dj_is_part_zer_offset(partition, address); bool is_readable = ot_otp_dj_is_readable(s, partition); bool is_wide = ot_otp_dj_is_wide_granule(partition, address); /* "in all partitions, the digest itself is ALWAYS readable." */ - if (!is_digest && !is_readable) { + if (!is_digest && !is_zer && !is_readable) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: %s: partition %s @ 0x%04x not readable\n", __func__, + s->ot_id, PART_NAME(partition), address); ot_otp_dj_dai_set_error(s, OTP_ACCESS_ERROR); return; } @@ -2309,11 +2261,11 @@ static void ot_otp_dj_dai_digest(OtOTPDjState *s) if (OtOTPPartDescs[partition].buffered) { data = ((const uint8_t *)s->otp->data) + - OT_OTP_PART_DATA_OFFSET(partition); + ot_otp_dj_part_data_offset(partition); } else { data = (const uint8_t *)pctrl->buffer.data; } - unsigned part_size = OT_OTP_PART_DATA_BYTE_SIZE(partition); + unsigned part_size = ot_otp_dj_part_data_byte_size(partition); DAI_CHANGE_STATE(s, OTP_DAI_DIG); @@ -2443,50 +2395,13 @@ static uint64_t ot_otp_dj_reg_read(void *opaque, hwaddr addr, unsigned size) switch (reg) { case R_INTR_STATE: case R_INTR_ENABLE: - case R_ERR_CODE_0: - case R_ERR_CODE_1: - case R_ERR_CODE_2: - case R_ERR_CODE_3: - case R_ERR_CODE_4: - case R_ERR_CODE_5: - case R_ERR_CODE_6: - case R_ERR_CODE_7: - case R_ERR_CODE_8: - case R_ERR_CODE_9: - case R_ERR_CODE_10: - case R_ERR_CODE_11: - case R_ERR_CODE_12: - case R_ERR_CODE_13: - case R_ERR_CODE_14: - case R_ERR_CODE_15: - case R_ERR_CODE_16: - case R_ERR_CODE_17: - case R_ERR_CODE_18: - case R_ERR_CODE_19: - case R_ERR_CODE_20: - case R_ERR_CODE_21: - case R_ERR_CODE_22: - case R_ERR_CODE_23: + case R_ERR_CODE_0 ... R_ERR_CODE_23: case R_DIRECT_ACCESS_WDATA_0: case R_DIRECT_ACCESS_WDATA_1: case R_DIRECT_ACCESS_RDATA_0: case R_DIRECT_ACCESS_RDATA_1: case R_DIRECT_ACCESS_ADDRESS: - case R_VENDOR_TEST_READ_LOCK: - case R_CREATOR_SW_CFG_READ_LOCK: - case R_OWNER_SW_CFG_READ_LOCK: - case R_OWNERSHIP_SLOT_STATE_READ_LOCK: - case R_ROT_CREATOR_AUTH_READ_LOCK: - case R_ROT_OWNER_AUTH_SLOT0_READ_LOCK: - case R_ROT_OWNER_AUTH_SLOT1_READ_LOCK: - case R_PLAT_INTEG_AUTH_SLOT0_READ_LOCK: - case R_PLAT_INTEG_AUTH_SLOT1_READ_LOCK: - case R_PLAT_OWNER_AUTH_SLOT0_READ_LOCK: - case R_PLAT_OWNER_AUTH_SLOT1_READ_LOCK: - case R_PLAT_OWNER_AUTH_SLOT2_READ_LOCK: - case R_PLAT_OWNER_AUTH_SLOT3_READ_LOCK: - case R_EXT_NVM_READ_LOCK: - case R_ROM_PATCH_READ_LOCK: + case R_VENDOR_TEST_READ_LOCK ... R_ROM_PATCH_READ_LOCK: val32 = s->regs[reg]; break; case R_STATUS: @@ -2506,189 +2421,15 @@ static uint64_t ot_otp_dj_reg_read(void *opaque, hwaddr addr, unsigned size) case R_CHECK_TIMEOUT: case R_INTEGRITY_CHECK_PERIOD: case R_CONSISTENCY_CHECK_PERIOD: - /* TODO: not yet implemented */ + /* @todo not yet implemented */ val32 = 0; break; - /* in all partitions, the digest itself is ALWAYS readable."*/ - case R_VENDOR_TEST_DIGEST_0: - val32 = (uint32_t)ot_otp_dj_get_part_digest(s, OTP_PART_VENDOR_TEST); - break; - case R_VENDOR_TEST_DIGEST_1: - val32 = (uint32_t)(ot_otp_dj_get_part_digest(s, OTP_PART_VENDOR_TEST) >> - 32u); - break; - case R_CREATOR_SW_CFG_DIGEST_0: - val32 = (uint32_t)ot_otp_dj_get_part_digest(s, OTP_PART_CREATOR_SW_CFG); - break; - case R_CREATOR_SW_CFG_DIGEST_1: - val32 = - (uint32_t)(ot_otp_dj_get_part_digest(s, OTP_PART_CREATOR_SW_CFG) >> - 32u); - break; - case R_OWNER_SW_CFG_DIGEST_0: - val32 = (uint32_t)ot_otp_dj_get_part_digest(s, OTP_PART_OWNER_SW_CFG); - break; - case R_OWNER_SW_CFG_DIGEST_1: - val32 = - (uint32_t)(ot_otp_dj_get_part_digest(s, OTP_PART_OWNER_SW_CFG) >> - 32u); - break; - case R_ROT_CREATOR_AUTH_DIGEST_0: - val32 = - (uint32_t)ot_otp_dj_get_part_digest(s, OTP_PART_ROT_CREATOR_AUTH); - break; - case R_ROT_CREATOR_AUTH_DIGEST_1: - val32 = - (uint32_t)(ot_otp_dj_get_part_digest(s, - OTP_PART_ROT_CREATOR_AUTH) >> - 32u); - break; - case R_ROT_OWNER_AUTH_SLOT0_DIGEST_0: - val32 = - (uint32_t)ot_otp_dj_get_part_digest(s, - OTP_PART_ROT_OWNER_AUTH_SLOT0); - break; - case R_ROT_OWNER_AUTH_SLOT0_DIGEST_1: - val32 = (uint32_t)(ot_otp_dj_get_part_digest( - s, OTP_PART_ROT_OWNER_AUTH_SLOT0) >> - 32u); - break; - case R_ROT_OWNER_AUTH_SLOT1_DIGEST_0: - val32 = - (uint32_t)ot_otp_dj_get_part_digest(s, - OTP_PART_ROT_OWNER_AUTH_SLOT1); - break; - case R_ROT_OWNER_AUTH_SLOT1_DIGEST_1: - val32 = (uint32_t)(ot_otp_dj_get_part_digest( - s, OTP_PART_ROT_OWNER_AUTH_SLOT1) >> - 32u); - break; - case R_PLAT_INTEG_AUTH_SLOT0_DIGEST_0: - val32 = - (uint32_t)ot_otp_dj_get_part_digest(s, - OTP_PART_PLAT_INTEG_AUTH_SLOT0); - break; - case R_PLAT_INTEG_AUTH_SLOT0_DIGEST_1: - val32 = (uint32_t)(ot_otp_dj_get_part_digest( - s, OTP_PART_PLAT_INTEG_AUTH_SLOT0) >> - 32u); - break; - case R_PLAT_INTEG_AUTH_SLOT1_DIGEST_0: - val32 = - (uint32_t)ot_otp_dj_get_part_digest(s, - OTP_PART_PLAT_INTEG_AUTH_SLOT1); - break; - case R_PLAT_INTEG_AUTH_SLOT1_DIGEST_1: - val32 = (uint32_t)(ot_otp_dj_get_part_digest( - s, OTP_PART_PLAT_INTEG_AUTH_SLOT1) >> - 32u); - break; - case R_PLAT_OWNER_AUTH_SLOT0_DIGEST_0: - val32 = - (uint32_t)ot_otp_dj_get_part_digest(s, - OTP_PART_PLAT_OWNER_AUTH_SLOT0); - break; - case R_PLAT_OWNER_AUTH_SLOT0_DIGEST_1: - val32 = (uint32_t)(ot_otp_dj_get_part_digest( - s, OTP_PART_PLAT_OWNER_AUTH_SLOT0) >> - 32u); - break; - case R_PLAT_OWNER_AUTH_SLOT1_DIGEST_0: - val32 = - (uint32_t)ot_otp_dj_get_part_digest(s, - OTP_PART_PLAT_OWNER_AUTH_SLOT1); - break; - case R_PLAT_OWNER_AUTH_SLOT1_DIGEST_1: - val32 = (uint32_t)(ot_otp_dj_get_part_digest( - s, OTP_PART_PLAT_OWNER_AUTH_SLOT1) >> - 32u); - break; - case R_PLAT_OWNER_AUTH_SLOT2_DIGEST_0: - val32 = - (uint32_t)ot_otp_dj_get_part_digest(s, - OTP_PART_PLAT_OWNER_AUTH_SLOT2); - break; - case R_PLAT_OWNER_AUTH_SLOT2_DIGEST_1: - val32 = (uint32_t)(ot_otp_dj_get_part_digest( - s, OTP_PART_PLAT_OWNER_AUTH_SLOT2) >> - 32u); - break; - case R_PLAT_OWNER_AUTH_SLOT3_DIGEST_0: - val32 = - (uint32_t)ot_otp_dj_get_part_digest(s, - OTP_PART_PLAT_OWNER_AUTH_SLOT3); - break; - case R_PLAT_OWNER_AUTH_SLOT3_DIGEST_1: - val32 = (uint32_t)(ot_otp_dj_get_part_digest( - s, OTP_PART_PLAT_OWNER_AUTH_SLOT3) >> - 32u); - break; - case R_ROM_PATCH_DIGEST_0: - val32 = (uint32_t)ot_otp_dj_get_part_digest(s, OTP_PART_ROM_PATCH); - break; - case R_ROM_PATCH_DIGEST_1: - val32 = - (uint32_t)(ot_otp_dj_get_part_digest(s, OTP_PART_ROM_PATCH) >> 32u); - break; - case R_HW_CFG0_DIGEST_0: - val32 = - (uint32_t)ot_otp_dj_get_buffered_part_digest(s, OTP_PART_HW_CFG0); - break; - case R_HW_CFG0_DIGEST_1: - val32 = - (uint32_t)(ot_otp_dj_get_buffered_part_digest(s, - OTP_PART_HW_CFG0) >> - 32u); - break; - case R_HW_CFG1_DIGEST_0: - val32 = - (uint32_t)ot_otp_dj_get_buffered_part_digest(s, OTP_PART_HW_CFG1); - break; - case R_HW_CFG1_DIGEST_1: - val32 = - (uint32_t)(ot_otp_dj_get_buffered_part_digest(s, - OTP_PART_HW_CFG1) >> - 32u); - break; - case R_SECRET0_DIGEST_0: - val32 = - (uint32_t)ot_otp_dj_get_buffered_part_digest(s, OTP_PART_SECRET0); - break; - case R_SECRET0_DIGEST_1: - val32 = - (uint32_t)(ot_otp_dj_get_buffered_part_digest(s, - OTP_PART_SECRET0) >> - 32u); - break; - case R_SECRET1_DIGEST_0: - val32 = - (uint32_t)ot_otp_dj_get_buffered_part_digest(s, OTP_PART_SECRET1); - break; - case R_SECRET1_DIGEST_1: - val32 = - (uint32_t)(ot_otp_dj_get_buffered_part_digest(s, - OTP_PART_SECRET1) >> - 32u); - break; - case R_SECRET2_DIGEST_0: - val32 = - (uint32_t)ot_otp_dj_get_buffered_part_digest(s, OTP_PART_SECRET2); - break; - case R_SECRET2_DIGEST_1: - val32 = - (uint32_t)(ot_otp_dj_get_buffered_part_digest(s, - OTP_PART_SECRET2) >> - 32u); - break; - case R_SECRET3_DIGEST_0: - val32 = - (uint32_t)ot_otp_dj_get_buffered_part_digest(s, OTP_PART_SECRET3); - break; - case R_SECRET3_DIGEST_1: - val32 = - (uint32_t)(ot_otp_dj_get_buffered_part_digest(s, - OTP_PART_SECRET3) >> - 32u); + case R_VENDOR_TEST_DIGEST_0 ... R_SECRET3_DIGEST_1: + /* + * In all partitions with a digest, the digest itself is ALWAYS + * readable. + */ + val32 = ot_otp_dj_get_part_digest_reg(s, reg - R_VENDOR_TEST_DIGEST_0); break; case R_INTR_TEST: case R_ALERT_TEST: @@ -2731,21 +2472,7 @@ static void ot_otp_dj_reg_write(void *opaque, hwaddr addr, uint64_t value, case R_DIRECT_ACCESS_ADDRESS: case R_DIRECT_ACCESS_WDATA_0: case R_DIRECT_ACCESS_WDATA_1: - case R_VENDOR_TEST_READ_LOCK: - case R_CREATOR_SW_CFG_READ_LOCK: - case R_OWNER_SW_CFG_READ_LOCK: - case R_OWNERSHIP_SLOT_STATE_READ_LOCK: - case R_ROT_CREATOR_AUTH_READ_LOCK: - case R_ROT_OWNER_AUTH_SLOT0_READ_LOCK: - case R_ROT_OWNER_AUTH_SLOT1_READ_LOCK: - case R_PLAT_INTEG_AUTH_SLOT0_READ_LOCK: - case R_PLAT_INTEG_AUTH_SLOT1_READ_LOCK: - case R_PLAT_OWNER_AUTH_SLOT0_READ_LOCK: - case R_PLAT_OWNER_AUTH_SLOT1_READ_LOCK: - case R_PLAT_OWNER_AUTH_SLOT2_READ_LOCK: - case R_PLAT_OWNER_AUTH_SLOT3_READ_LOCK: - case R_EXT_NVM_READ_LOCK: - case R_ROM_PATCH_READ_LOCK: + case R_VENDOR_TEST_READ_LOCK ... R_ROM_PATCH_READ_LOCK: if (!(s->regs[R_DIRECT_ACCESS_REGWEN] & R_DIRECT_ACCESS_REGWEN_REGWEN_MASK)) { qemu_log_mask(LOG_GUEST_ERROR, @@ -2777,71 +2504,11 @@ static void ot_otp_dj_reg_write(void *opaque, hwaddr addr, uint64_t value, } break; case R_STATUS: - case R_ERR_CODE_0: - case R_ERR_CODE_1: - case R_ERR_CODE_2: - case R_ERR_CODE_3: - case R_ERR_CODE_4: - case R_ERR_CODE_5: - case R_ERR_CODE_6: - case R_ERR_CODE_7: - case R_ERR_CODE_8: - case R_ERR_CODE_9: - case R_ERR_CODE_10: - case R_ERR_CODE_11: - case R_ERR_CODE_12: - case R_ERR_CODE_13: - case R_ERR_CODE_14: - case R_ERR_CODE_15: - case R_ERR_CODE_16: - case R_ERR_CODE_17: - case R_ERR_CODE_18: - case R_ERR_CODE_19: - case R_ERR_CODE_20: - case R_ERR_CODE_21: - case R_ERR_CODE_22: - case R_ERR_CODE_23: + case R_ERR_CODE_0 ... R_ERR_CODE_23: case R_DIRECT_ACCESS_REGWEN: case R_DIRECT_ACCESS_RDATA_0: case R_DIRECT_ACCESS_RDATA_1: - case R_VENDOR_TEST_DIGEST_0: - case R_VENDOR_TEST_DIGEST_1: - case R_CREATOR_SW_CFG_DIGEST_0: - case R_CREATOR_SW_CFG_DIGEST_1: - case R_OWNER_SW_CFG_DIGEST_0: - case R_OWNER_SW_CFG_DIGEST_1: - case R_ROT_CREATOR_AUTH_DIGEST_0: - case R_ROT_CREATOR_AUTH_DIGEST_1: - case R_ROT_OWNER_AUTH_SLOT0_DIGEST_0: - case R_ROT_OWNER_AUTH_SLOT0_DIGEST_1: - case R_ROT_OWNER_AUTH_SLOT1_DIGEST_0: - case R_ROT_OWNER_AUTH_SLOT1_DIGEST_1: - case R_PLAT_INTEG_AUTH_SLOT0_DIGEST_0: - case R_PLAT_INTEG_AUTH_SLOT0_DIGEST_1: - case R_PLAT_INTEG_AUTH_SLOT1_DIGEST_0: - case R_PLAT_INTEG_AUTH_SLOT1_DIGEST_1: - case R_PLAT_OWNER_AUTH_SLOT0_DIGEST_0: - case R_PLAT_OWNER_AUTH_SLOT0_DIGEST_1: - case R_PLAT_OWNER_AUTH_SLOT1_DIGEST_0: - case R_PLAT_OWNER_AUTH_SLOT1_DIGEST_1: - case R_PLAT_OWNER_AUTH_SLOT2_DIGEST_0: - case R_PLAT_OWNER_AUTH_SLOT2_DIGEST_1: - case R_PLAT_OWNER_AUTH_SLOT3_DIGEST_0: - case R_PLAT_OWNER_AUTH_SLOT3_DIGEST_1: - case R_ROM_PATCH_DIGEST_0: - case R_ROM_PATCH_DIGEST_1: - case R_HW_CFG0_DIGEST_0: - case R_HW_CFG0_DIGEST_1: - case R_HW_CFG1_DIGEST_0: - case R_HW_CFG1_DIGEST_1: - case R_SECRET0_DIGEST_0: - case R_SECRET0_DIGEST_1: - case R_SECRET1_DIGEST_0: - case R_SECRET1_DIGEST_1: - case R_SECRET2_DIGEST_0: - case R_SECRET2_DIGEST_1: - case R_SECRET3_DIGEST_0: - case R_SECRET3_DIGEST_1: + case R_VENDOR_TEST_DIGEST_0 ... R_SECRET3_DIGEST_1: qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%03" HWADDR_PRIx " (%s)\n", __func__, s->ot_id, addr, REG_NAME(reg)); @@ -2852,22 +2519,22 @@ static void ot_otp_dj_reg_write(void *opaque, hwaddr addr, uint64_t value, switch (reg) { case R_INTR_STATE: - val32 &= INTR_MASK; + val32 &= INTR_WMASK; s->regs[R_INTR_STATE] &= ~val32; /* RW1C */ ot_otp_dj_update_irqs(s); break; case R_INTR_ENABLE: - val32 &= INTR_MASK; + val32 &= INTR_WMASK; s->regs[R_INTR_ENABLE] = val32; ot_otp_dj_update_irqs(s); break; case R_INTR_TEST: - val32 &= INTR_MASK; + val32 &= INTR_WMASK; s->regs[R_INTR_STATE] = val32; ot_otp_dj_update_irqs(s); break; case R_ALERT_TEST: - val32 &= ALERT_TEST_MASK; + val32 &= ALERT_WMASK; s->regs[reg] = val32; ot_otp_dj_update_alerts(s); break; @@ -2888,21 +2555,7 @@ static void ot_otp_dj_reg_write(void *opaque, hwaddr addr, uint64_t value, case R_DIRECT_ACCESS_WDATA_1: s->regs[reg] = val32; break; - case R_VENDOR_TEST_READ_LOCK: - case R_CREATOR_SW_CFG_READ_LOCK: - case R_OWNER_SW_CFG_READ_LOCK: - case R_OWNERSHIP_SLOT_STATE_READ_LOCK: - case R_ROT_CREATOR_AUTH_READ_LOCK: - case R_ROT_OWNER_AUTH_SLOT0_READ_LOCK: - case R_ROT_OWNER_AUTH_SLOT1_READ_LOCK: - case R_PLAT_INTEG_AUTH_SLOT0_READ_LOCK: - case R_PLAT_INTEG_AUTH_SLOT1_READ_LOCK: - case R_PLAT_OWNER_AUTH_SLOT0_READ_LOCK: - case R_PLAT_OWNER_AUTH_SLOT1_READ_LOCK: - case R_PLAT_OWNER_AUTH_SLOT2_READ_LOCK: - case R_PLAT_OWNER_AUTH_SLOT3_READ_LOCK: - case R_EXT_NVM_READ_LOCK: - case R_ROM_PATCH_READ_LOCK: + case R_VENDOR_TEST_READ_LOCK ... R_ROM_PATCH_READ_LOCK: val32 &= READ_LOCK_MASK; s->regs[reg] &= val32; /* RW0C */ break; @@ -2925,174 +2578,147 @@ static void ot_otp_dj_reg_write(void *opaque, hwaddr addr, uint64_t value, static const char *ot_otp_dj_swcfg_reg_name(unsigned swreg) { -#define CASE_SCALAR(_reg_) \ +#define CASE_BYTE(_reg_) \ + case A_##_reg_: \ + return stringify(_reg_) +#define CASE_SUB(_reg_, _sz_) \ + case A_##_reg_...(A_##_reg_ + (_sz_)): \ + return stringify(_reg_) +#define CASE_REG(_reg_) \ case A_##_reg_...(A_##_reg_ + 3u): \ return stringify(_reg_) +#define CASE_WIDE(_reg_) \ + case A_##_reg_...(A_##_reg_ + 7u): \ + return stringify(_reg_) #define CASE_RANGE(_reg_) \ case A_##_reg_...(A_##_reg_ + (_reg_##_SIZE) - 1u): \ return stringify(_reg_) -#define CASE_SUB_WORD CASE_RANGE -#define CASE_DIGEST(_reg_) \ - case A_##_reg_...(A_##_reg_ + 7u): \ - return stringify(_reg_) switch (swreg) { CASE_RANGE(VENDOR_TEST_SCRATCH); - CASE_DIGEST(VENDOR_TEST_DIGEST); - CASE_RANGE(CREATOR_SW_CFG_DIO_ATTR); - CASE_RANGE(CREATOR_SW_CFG_AST); + CASE_WIDE(VENDOR_TEST_DIGEST); + CASE_RANGE(CREATOR_SW_CFG_AST_CFG); + CASE_REG(CREATOR_SW_CFG_AST_INIT_EN); CASE_RANGE(CREATOR_SW_CFG_OVERRIDES); - CASE_SCALAR(CREATOR_SW_CFG_ROM_PERMISSIVE_SECURITY); - CASE_SCALAR(CREATOR_SW_CFG_BOOTSTRAP_FW_OWNERS_MASK); - CASE_SCALAR(CREATOR_SW_CFG_ROM_EXT_OWNERS_MASK); - CASE_SCALAR(CREATOR_SW_CFG_ROM_EXT_SKU); - CASE_SCALAR(CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN); + CASE_REG(CREATOR_SW_CFG_ROM_EXT_SKU); + CASE_REG(CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN); CASE_RANGE(CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN); - CASE_SCALAR(CREATOR_SW_CFG_SIGVERIFY_SPX_EN); + CASE_REG(CREATOR_SW_CFG_SIGVERIFY_SPX_EN); CASE_RANGE(CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN); - CASE_SCALAR(CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG); - CASE_SCALAR(CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG); - CASE_SCALAR(CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE); - CASE_SCALAR(CREATOR_SW_CFG_RNG_EN); - CASE_SCALAR(CREATOR_SW_CFG_JITTER_EN); - CASE_SCALAR(CREATOR_SW_CFG_RET_RAM_RESET_MASK); - CASE_SCALAR(CREATOR_SW_CFG_MANUF_STATE); - CASE_SCALAR(CREATOR_SW_CFG_ROM_EXEC_EN); - CASE_SCALAR(CREATOR_SW_CFG_CPUCTRL); - CASE_SCALAR(CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT); - CASE_SCALAR(CREATOR_SW_CFG_MIN_SEC_VER_BL0); - CASE_SCALAR(CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN); - CASE_SCALAR(CREATOR_SW_CFG_RMA_SPIN_EN); - CASE_SCALAR(CREATOR_SW_CFG_RMA_SPIN_CYCLES); - CASE_SCALAR(CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS); - CASE_SCALAR(CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS); - CASE_SCALAR(CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS); - CASE_SCALAR(CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS); - CASE_SCALAR(CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS); - CASE_SCALAR(CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS); - CASE_SCALAR(CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS); - CASE_SCALAR(CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS); - CASE_SCALAR(CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS); - CASE_SCALAR(CREATOR_SW_CFG_RNG_ALERT_THRESHOLD); - CASE_SCALAR(CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST); - CASE_SCALAR(CREATOR_SW_CFG_SRAM_KEY_RENEW_EN); - CASE_DIGEST(CREATOR_SW_CFG_DIGEST); - CASE_SCALAR(OWNER_SW_CFG_ROM_ERROR_REPORTING); - CASE_SCALAR(OWNER_SW_CFG_ROM_BOOTSTRAP_DIS); - CASE_SCALAR(OWNER_SW_CFG_ROM_ALERT_CLASS_EN); - CASE_SCALAR(OWNER_SW_CFG_ROM_ALERT_ESCALATION); + CASE_REG(CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG); + CASE_REG(CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG); + CASE_REG(CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE); + CASE_REG(CREATOR_SW_CFG_RNG_EN); + CASE_REG(CREATOR_SW_CFG_JITTER_EN); + CASE_REG(CREATOR_SW_CFG_RET_RAM_RESET_MASK); + CASE_REG(CREATOR_SW_CFG_MANUF_STATE); + CASE_REG(CREATOR_SW_CFG_ROM_EXEC_EN); + CASE_REG(CREATOR_SW_CFG_CPUCTRL); + CASE_REG(CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT); + CASE_REG(CREATOR_SW_CFG_MIN_SEC_VER_BL0); + CASE_REG(CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN); + CASE_REG(CREATOR_SW_CFG_RMA_SPIN_EN); + CASE_REG(CREATOR_SW_CFG_RMA_SPIN_CYCLES); + CASE_REG(CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS); + CASE_REG(CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS); + CASE_REG(CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS); + CASE_REG(CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS); + CASE_REG(CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS); + CASE_REG(CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS); + CASE_REG(CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS); + CASE_REG(CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS); + CASE_REG(CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS); + CASE_REG(CREATOR_SW_CFG_RNG_ALERT_THRESHOLD); + CASE_REG(CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST); + CASE_REG(CREATOR_SW_CFG_SRAM_KEY_RENEW_EN); + CASE_WIDE(CREATOR_SW_CFG_DIGEST); + CASE_REG(OWNER_SW_CFG_ROM_ERROR_REPORTING); + CASE_REG(OWNER_SW_CFG_ROM_BOOTSTRAP_DIS); + CASE_REG(OWNER_SW_CFG_ROM_ALERT_CLASS_EN); + CASE_REG(OWNER_SW_CFG_ROM_ALERT_ESCALATION); CASE_RANGE(OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION); CASE_RANGE(OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION); CASE_RANGE(OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH); CASE_RANGE(OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES); CASE_RANGE(OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES); - CASE_SCALAR(OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD); - CASE_SCALAR(OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END); - CASE_SCALAR(OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV); - CASE_SCALAR(OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA); - CASE_SCALAR(OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES); - CASE_SCALAR(OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN); - CASE_SCALAR(OWNER_SW_CFG_MANUF_STATE); - CASE_SCALAR(OWNER_SW_CFG_ROM_RSTMGR_INFO_EN); - CASE_DIGEST(OWNER_SW_CFG_DIGEST); + CASE_REG(OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD); + CASE_REG(OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END); + CASE_REG(OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV); + CASE_REG(OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA); + CASE_REG(OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES); + CASE_REG(OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN); + CASE_REG(OWNER_SW_CFG_MANUF_STATE); + CASE_REG(OWNER_SW_CFG_ROM_RSTMGR_INFO_EN); + CASE_WIDE(OWNER_SW_CFG_DIGEST); CASE_RANGE(OWNERSHIP_SLOT_STATE_ROT_OWNER_AUTH); CASE_RANGE(OWNERSHIP_SLOT_STATE_PLAT_INTEG_AUTH); CASE_RANGE(OWNERSHIP_SLOT_STATE_PLAT_OWNER_AUTH); - CASE_SCALAR(ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY_TYPE); - CASE_SCALAR(ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY_ROLE); CASE_RANGE(ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY); - CASE_SCALAR(ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY_TYPE); - CASE_SCALAR(ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY_ROLE); + CASE_REG(ROT_CREATOR_AUTH_OWNERSHIP_STATE); CASE_RANGE(ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY); CASE_RANGE(ROT_CREATOR_AUTH_KEYMANIFEST_KEY); - CASE_RANGE(ROT_CREATOR_AUTH_KEY_DEVICE_ID); - CASE_RANGE(ROT_CREATOR_AUTH_KEY_METADATA); - CASE_RANGE(ROT_CREATOR_AUTH_KEY_SIGNATURE); + CASE_RANGE(ROT_CREATOR_AUTH_UNLOCK4XFER_KEY); CASE_RANGE(ROT_CREATOR_AUTH_IDENTITY_CERT); - CASE_RANGE(ROT_CREATOR_AUTH_IDENTITY_CERT_CMAC); - CASE_DIGEST(ROT_CREATOR_AUTH_DIGEST); - CASE_SCALAR(ROT_CREATOR_AUTH_KEYMANIFEST_KEY_TYPE); - CASE_SCALAR(ROT_CREATOR_AUTH_KEYMANIFEST_KEY_ROLE); - CASE_SCALAR(ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_TYPE); - CASE_SCALAR(ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_ROLE); + CASE_WIDE(ROT_CREATOR_AUTH_DIGEST); CASE_RANGE(ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY); CASE_RANGE(ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY); - CASE_DIGEST(ROT_OWNER_AUTH_SLOT0_DIGEST); - CASE_RANGE(ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_TYPE); - CASE_RANGE(ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_ROLE); + CASE_WIDE(ROT_OWNER_AUTH_SLOT0_DIGEST); CASE_RANGE(ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY); CASE_RANGE(ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY); - CASE_DIGEST(ROT_OWNER_AUTH_SLOT1_DIGEST); - CASE_RANGE(PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY_TYPE); - CASE_RANGE(PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY_ROLE); + CASE_WIDE(ROT_OWNER_AUTH_SLOT1_DIGEST); CASE_RANGE(PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY); - CASE_SCALAR(PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY_TYPE); - CASE_SCALAR(PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY_ROLE); CASE_RANGE(PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY); - CASE_DIGEST(PLAT_INTEG_AUTH_SLOT0_DIGEST); + CASE_WIDE(PLAT_INTEG_AUTH_SLOT0_DIGEST); CASE_RANGE(PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY); - CASE_SCALAR(PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY_TYPE); - CASE_SCALAR(PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY_ROLE); CASE_RANGE(PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY); - CASE_DIGEST(PLAT_INTEG_AUTH_SLOT1_DIGEST); - CASE_SCALAR(PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_TYPE); - CASE_SCALAR(PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_ROLE); + CASE_WIDE(PLAT_INTEG_AUTH_SLOT1_DIGEST); CASE_RANGE(PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY); - CASE_SCALAR(PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_TYPE); - CASE_SCALAR(PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_ROLE); CASE_RANGE(PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY); - CASE_DIGEST(PLAT_OWNER_AUTH_SLOT0_DIGEST); - CASE_SCALAR(PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_TYPE); - CASE_SCALAR(PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_ROLE); + CASE_WIDE(PLAT_OWNER_AUTH_SLOT0_DIGEST); CASE_RANGE(PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY); - CASE_SCALAR(PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_TYPE); - CASE_SCALAR(PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_ROLE); CASE_RANGE(PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY); - CASE_DIGEST(PLAT_OWNER_AUTH_SLOT1_DIGEST); - CASE_SCALAR(PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY_TYPE); - CASE_SCALAR(PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY_ROLE); + CASE_WIDE(PLAT_OWNER_AUTH_SLOT1_DIGEST); CASE_RANGE(PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY); - CASE_SCALAR(PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY_TYPE); - CASE_SCALAR(PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY_ROLE); CASE_RANGE(PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY); - CASE_DIGEST(PLAT_OWNER_AUTH_SLOT2_DIGEST); - CASE_SCALAR(PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY_TYPE); - CASE_SCALAR(PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY_ROLE); + CASE_WIDE(PLAT_OWNER_AUTH_SLOT2_DIGEST); CASE_RANGE(PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY); - CASE_SCALAR(PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY_TYPE); - CASE_SCALAR(PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY_ROLE); CASE_RANGE(PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY); - CASE_DIGEST(PLAT_OWNER_AUTH_SLOT3_DIGEST); + CASE_WIDE(PLAT_OWNER_AUTH_SLOT3_DIGEST); CASE_RANGE(EXT_NVM_ANTIREPLAY_FRESHNESS_CNT); CASE_RANGE(ROM_PATCH_DATA); - CASE_DIGEST(ROM_PATCH_DIGEST); + CASE_WIDE(ROM_PATCH_DIGEST); CASE_RANGE(HW_CFG0_DEVICE_ID); CASE_RANGE(HW_CFG0_MANUF_STATE); - CASE_DIGEST(HW_CFG0_DIGEST); - CASE_SCALAR(HW_CFG1_SOC_DBG_STATE); - CASE_SCALAR(HW_CFG1_EN_SRAM_IFETCH); - CASE_DIGEST(HW_CFG1_DIGEST); + CASE_WIDE(HW_CFG0_DIGEST); + CASE_REG(HW_CFG1_SOC_DBG_STATE); + CASE_BYTE(HW_CFG1_EN_CSRNG_SW_APP_READ); + CASE_BYTE(HW_CFG1_EN_SRAM_IFETCH); + CASE_WIDE(HW_CFG1_DIGEST); CASE_RANGE(SECRET0_TEST_UNLOCK_TOKEN); CASE_RANGE(SECRET0_TEST_EXIT_TOKEN); - CASE_DIGEST(SECRET0_DIGEST); - CASE_RANGE(SECRET1_FLASH_ADDR_KEY_SEED); - CASE_RANGE(SECRET1_FLASH_DATA_KEY_SEED); + CASE_WIDE(SECRET0_DIGEST); + CASE_WIDE(SECRET0_ZER); CASE_RANGE(SECRET1_SRAM_DATA_KEY_SEED); - CASE_DIGEST(SECRET1_DIGEST); + CASE_WIDE(SECRET1_DIGEST); + CASE_WIDE(SECRET1_ZER); CASE_RANGE(SECRET2_RMA_TOKEN); CASE_RANGE(SECRET2_CREATOR_ROOT_KEY_SHARE0); CASE_RANGE(SECRET2_CREATOR_ROOT_KEY_SHARE1); CASE_RANGE(SECRET2_CREATOR_SEED); - CASE_DIGEST(SECRET2_DIGEST); + CASE_WIDE(SECRET2_DIGEST); + CASE_WIDE(SECRET2_ZER); CASE_RANGE(SECRET3_OWNER_SEED); - CASE_DIGEST(SECRET3_DIGEST); + CASE_WIDE(SECRET3_DIGEST); + CASE_WIDE(SECRET3_ZER); CASE_RANGE(LC_TRANSITION_CNT); CASE_RANGE(LC_STATE); default: return ""; } -#undef CASE_SCALAR +#undef CASE_BYTE +#undef CASE_SUB +#undef CASE_REG #undef CASE_RANGE #undef CASE_SUB_WORD #undef CASE_DIGEST @@ -3124,9 +2750,10 @@ static MemTxResult ot_otp_dj_swcfg_read_with_attrs( } bool is_digest = ot_otp_dj_is_part_digest_offset(partition, addr); + bool is_zer = ot_otp_dj_is_part_zer_offset(partition, addr); bool is_readable = ot_otp_dj_is_readable(s, partition); - if (!is_digest && !is_readable) { + if (!is_digest && !is_zer && !is_readable) { trace_ot_otp_access_error_on(s->ot_id, partition, addr, "not readable"); ot_otp_dj_set_error(s, (unsigned)partition, OTP_ACCESS_ERROR); @@ -3734,8 +3361,9 @@ static void ot_otp_dj_pwr_load(OtOTPDjState *s) int rc = blk_pread(s->blk, 0, (int64_t)otp_size, otp->storage, 0); if (rc < 0) { error_setg(&error_fatal, - "%s: failed to read the initial OTP content: %d", - s->ot_id, rc); + "%s: failed to read the initial OTP content %zu bytes: " + "%d", + s->ot_id, otp_size, rc); return; } @@ -4168,24 +3796,24 @@ static void ot_otp_dj_reset_enter(Object *obj, ResetType type) memset(s->regs, 0, REGS_COUNT * sizeof(uint32_t)); - s->regs[R_DIRECT_ACCESS_REGWEN] = 0x1u; - s->regs[R_CHECK_TRIGGER_REGWEN] = 0x1u; - s->regs[R_CHECK_REGWEN] = 0x1u; - s->regs[R_VENDOR_TEST_READ_LOCK] = 0x1u; - s->regs[R_CREATOR_SW_CFG_READ_LOCK] = 0x1u; - s->regs[R_OWNER_SW_CFG_READ_LOCK] = 0x1u; - s->regs[R_OWNERSHIP_SLOT_STATE_READ_LOCK] = 0x1u; - s->regs[R_ROT_CREATOR_AUTH_READ_LOCK] = 0x1u; - s->regs[R_ROT_OWNER_AUTH_SLOT0_READ_LOCK] = 0x1u; - s->regs[R_ROT_OWNER_AUTH_SLOT1_READ_LOCK] = 0x1u; - s->regs[R_PLAT_INTEG_AUTH_SLOT0_READ_LOCK] = 0x1u; - s->regs[R_PLAT_INTEG_AUTH_SLOT1_READ_LOCK] = 0x1u; - s->regs[R_PLAT_OWNER_AUTH_SLOT0_READ_LOCK] = 0x1u; - s->regs[R_PLAT_OWNER_AUTH_SLOT1_READ_LOCK] = 0x1u; - s->regs[R_PLAT_OWNER_AUTH_SLOT2_READ_LOCK] = 0x1u; - s->regs[R_PLAT_OWNER_AUTH_SLOT3_READ_LOCK] = 0x1u; - s->regs[R_EXT_NVM_READ_LOCK] = 0x1u; - s->regs[R_ROM_PATCH_READ_LOCK] = 0x1u; + s->regs[R_DIRECT_ACCESS_REGWEN] = 0x00000001u; + s->regs[R_CHECK_TRIGGER_REGWEN] = 0x00000001u; + s->regs[R_CHECK_REGWEN] = 0x00000001u; + s->regs[R_VENDOR_TEST_READ_LOCK] = 0x00000001u; + s->regs[R_CREATOR_SW_CFG_READ_LOCK] = 0x00000001u; + s->regs[R_OWNER_SW_CFG_READ_LOCK] = 0x00000001u; + s->regs[R_OWNERSHIP_SLOT_STATE_READ_LOCK] = 0x00000001u; + s->regs[R_ROT_CREATOR_AUTH_READ_LOCK] = 0x00000001u; + s->regs[R_ROT_OWNER_AUTH_SLOT0_READ_LOCK] = 0x00000001u; + s->regs[R_ROT_OWNER_AUTH_SLOT1_READ_LOCK] = 0x00000001u; + s->regs[R_PLAT_INTEG_AUTH_SLOT0_READ_LOCK] = 0x00000001u; + s->regs[R_PLAT_INTEG_AUTH_SLOT1_READ_LOCK] = 0x00000001u; + s->regs[R_PLAT_OWNER_AUTH_SLOT0_READ_LOCK] = 0x00000001u; + s->regs[R_PLAT_OWNER_AUTH_SLOT1_READ_LOCK] = 0x00000001u; + s->regs[R_PLAT_OWNER_AUTH_SLOT2_READ_LOCK] = 0x00000001u; + s->regs[R_PLAT_OWNER_AUTH_SLOT3_READ_LOCK] = 0x00000001u; + s->regs[R_EXT_NVM_READ_LOCK] = 0x00000001u; + s->regs[R_ROM_PATCH_READ_LOCK] = 0x00000001u; s->alert_bm = 0u; @@ -4205,7 +3833,7 @@ static void ot_otp_dj_reset_enter(Object *obj, ResetType type) s->partctrls[ix].state.u = OTP_UNBUF_IDLE; continue; } - unsigned part_size = OT_OTP_PART_DATA_BYTE_SIZE(ix); + unsigned part_size = ot_otp_dj_part_data_byte_size(ix); memset(s->partctrls[ix].buffer.data, 0, part_size); s->partctrls[ix].buffer.digest = 0; if (OtOTPPartDescs[ix].iskeymgr_creator || @@ -4320,7 +3948,8 @@ static void ot_otp_dj_init(Object *obj) if (!OtOTPPartDescs[ix].buffered) { continue; } - size_t part_words = OT_OTP_PART_DATA_BYTE_SIZE(ix) / sizeof(uint32_t); + size_t part_words = + ot_otp_dj_part_data_byte_size(ix) / sizeof(uint32_t); s->partctrls[ix].buffer.data = g_new0(uint32_t, part_words); } diff --git a/hw/opentitan/ot_otp_dj_parts.c b/hw/opentitan/ot_otp_dj_parts.c index e4d503c6d917d..411802ead16f5 100644 --- a/hw/opentitan/ot_otp_dj_parts.c +++ b/hw/opentitan/ot_otp_dj_parts.c @@ -1,4 +1,7 @@ -/* Generated from otp_ctrl_mmap.hjson with otptool.py */ +/* + * Generated from otp_ctrl_mmap.hjson with otptool.py + * Top version: 5fe6fe8605 + */ /* this prevents linters from checking this file without its parent file */ #ifdef OT_OTP_DJ_PARTS @@ -9,6 +12,7 @@ static const OtOTPPartDesc OtOTPPartDescs[] = { [OTP_PART_VENDOR_TEST] = { .size = 64u, .offset = 0u, + .zer_offset = UINT16_MAX, .digest_offset = 56u, .hw_digest = false, .sw_digest = true, @@ -18,11 +22,13 @@ static const OtOTPPartDesc OtOTPPartDescs[] = { .read_lock_csr = true, .read_lock = true, .integrity = false, + .zeroizable = false, }, [OTP_PART_CREATOR_SW_CFG] = { - .size = 336u, + .size = 304u, .offset = 64u, - .digest_offset = 392u, + .zer_offset = UINT16_MAX, + .digest_offset = 360u, .hw_digest = false, .sw_digest = true, .secret = false, @@ -31,11 +37,13 @@ static const OtOTPPartDesc OtOTPPartDescs[] = { .read_lock_csr = true, .read_lock = true, .integrity = true, + .zeroizable = false, }, [OTP_PART_OWNER_SW_CFG] = { - .size = 632u, - .offset = 400u, - .digest_offset = 1024u, + .size = 600u, + .offset = 368u, + .zer_offset = UINT16_MAX, + .digest_offset = 960u, .hw_digest = false, .sw_digest = true, .secret = false, @@ -44,10 +52,12 @@ static const OtOTPPartDesc OtOTPPartDescs[] = { .read_lock_csr = true, .read_lock = true, .integrity = true, + .zeroizable = false, }, [OTP_PART_OWNERSHIP_SLOT_STATE] = { .size = 48u, - .offset = 1032u, + .offset = 968u, + .zer_offset = UINT16_MAX, .digest_offset = UINT16_MAX, .hw_digest = false, .sw_digest = false, @@ -57,11 +67,13 @@ static const OtOTPPartDesc OtOTPPartDescs[] = { .read_lock_csr = true, .read_lock = true, .integrity = true, + .zeroizable = false, }, [OTP_PART_ROT_CREATOR_AUTH] = { .size = 1424u, - .offset = 1080u, - .digest_offset = 2496u, + .offset = 1016u, + .zer_offset = UINT16_MAX, + .digest_offset = 2432u, .hw_digest = false, .sw_digest = true, .secret = false, @@ -70,11 +82,13 @@ static const OtOTPPartDesc OtOTPPartDescs[] = { .read_lock_csr = true, .read_lock = true, .integrity = true, + .zeroizable = false, }, [OTP_PART_ROT_OWNER_AUTH_SLOT0] = { .size = 328u, - .offset = 2504u, - .digest_offset = 2824u, + .offset = 2440u, + .zer_offset = UINT16_MAX, + .digest_offset = 2760u, .hw_digest = false, .sw_digest = true, .secret = false, @@ -83,11 +97,13 @@ static const OtOTPPartDesc OtOTPPartDescs[] = { .read_lock_csr = true, .read_lock = true, .integrity = true, + .zeroizable = false, }, [OTP_PART_ROT_OWNER_AUTH_SLOT1] = { .size = 328u, - .offset = 2832u, - .digest_offset = 3152u, + .offset = 2768u, + .zer_offset = UINT16_MAX, + .digest_offset = 3088u, .hw_digest = false, .sw_digest = true, .secret = false, @@ -96,11 +112,13 @@ static const OtOTPPartDesc OtOTPPartDescs[] = { .read_lock_csr = true, .read_lock = true, .integrity = true, + .zeroizable = false, }, [OTP_PART_PLAT_INTEG_AUTH_SLOT0] = { .size = 328u, - .offset = 3160u, - .digest_offset = 3480u, + .offset = 3096u, + .zer_offset = UINT16_MAX, + .digest_offset = 3416u, .hw_digest = false, .sw_digest = true, .secret = false, @@ -109,11 +127,13 @@ static const OtOTPPartDesc OtOTPPartDescs[] = { .read_lock_csr = true, .read_lock = true, .integrity = true, + .zeroizable = false, }, [OTP_PART_PLAT_INTEG_AUTH_SLOT1] = { .size = 328u, - .offset = 3488u, - .digest_offset = 3808u, + .offset = 3424u, + .zer_offset = UINT16_MAX, + .digest_offset = 3744u, .hw_digest = false, .sw_digest = true, .secret = false, @@ -122,11 +142,13 @@ static const OtOTPPartDesc OtOTPPartDescs[] = { .read_lock_csr = true, .read_lock = true, .integrity = true, + .zeroizable = false, }, [OTP_PART_PLAT_OWNER_AUTH_SLOT0] = { .size = 328u, - .offset = 3816u, - .digest_offset = 4136u, + .offset = 3752u, + .zer_offset = UINT16_MAX, + .digest_offset = 4072u, .hw_digest = false, .sw_digest = true, .secret = false, @@ -135,11 +157,13 @@ static const OtOTPPartDesc OtOTPPartDescs[] = { .read_lock_csr = true, .read_lock = true, .integrity = true, + .zeroizable = false, }, [OTP_PART_PLAT_OWNER_AUTH_SLOT1] = { .size = 328u, - .offset = 4144u, - .digest_offset = 4464u, + .offset = 4080u, + .zer_offset = UINT16_MAX, + .digest_offset = 4400u, .hw_digest = false, .sw_digest = true, .secret = false, @@ -148,11 +172,13 @@ static const OtOTPPartDesc OtOTPPartDescs[] = { .read_lock_csr = true, .read_lock = true, .integrity = true, + .zeroizable = false, }, [OTP_PART_PLAT_OWNER_AUTH_SLOT2] = { .size = 328u, - .offset = 4472u, - .digest_offset = 4792u, + .offset = 4408u, + .zer_offset = UINT16_MAX, + .digest_offset = 4728u, .hw_digest = false, .sw_digest = true, .secret = false, @@ -161,11 +187,13 @@ static const OtOTPPartDesc OtOTPPartDescs[] = { .read_lock_csr = true, .read_lock = true, .integrity = true, + .zeroizable = false, }, [OTP_PART_PLAT_OWNER_AUTH_SLOT3] = { .size = 328u, - .offset = 4800u, - .digest_offset = 5120u, + .offset = 4736u, + .zer_offset = UINT16_MAX, + .digest_offset = 5056u, .hw_digest = false, .sw_digest = true, .secret = false, @@ -174,10 +202,12 @@ static const OtOTPPartDesc OtOTPPartDescs[] = { .read_lock_csr = true, .read_lock = true, .integrity = true, + .zeroizable = false, }, [OTP_PART_EXT_NVM] = { .size = 1024u, - .offset = 5128u, + .offset = 5064u, + .zer_offset = UINT16_MAX, .digest_offset = UINT16_MAX, .hw_digest = false, .sw_digest = false, @@ -187,11 +217,13 @@ static const OtOTPPartDesc OtOTPPartDescs[] = { .read_lock_csr = true, .read_lock = true, .integrity = false, + .zeroizable = false, }, [OTP_PART_ROM_PATCH] = { - .size = 9768u, - .offset = 6152u, - .digest_offset = 15912u, + .size = 9864u, + .offset = 6088u, + .zer_offset = UINT16_MAX, + .digest_offset = 15944u, .hw_digest = false, .sw_digest = true, .secret = false, @@ -200,11 +232,13 @@ static const OtOTPPartDesc OtOTPPartDescs[] = { .read_lock_csr = true, .read_lock = true, .integrity = true, + .zeroizable = false, }, [OTP_PART_HW_CFG0] = { .size = 72u, - .offset = 15920u, - .digest_offset = 15984u, + .offset = 15952u, + .zer_offset = UINT16_MAX, + .digest_offset = 16016u, .hw_digest = true, .sw_digest = false, .secret = false, @@ -212,11 +246,13 @@ static const OtOTPPartDesc OtOTPPartDescs[] = { .write_lock = false, .read_lock = false, .integrity = true, + .zeroizable = false, }, [OTP_PART_HW_CFG1] = { .size = 16u, - .offset = 15992u, - .digest_offset = 16000u, + .offset = 16024u, + .zer_offset = UINT16_MAX, + .digest_offset = 16032u, .hw_digest = true, .sw_digest = false, .secret = false, @@ -224,11 +260,13 @@ static const OtOTPPartDesc OtOTPPartDescs[] = { .write_lock = false, .read_lock = false, .integrity = true, + .zeroizable = false, }, [OTP_PART_SECRET0] = { - .size = 40u, - .offset = 16008u, - .digest_offset = 16040u, + .size = 48u, + .offset = 16040u, + .zer_offset = 16080u, + .digest_offset = 16072u, .hw_digest = true, .sw_digest = false, .secret = true, @@ -236,11 +274,13 @@ static const OtOTPPartDesc OtOTPPartDescs[] = { .write_lock = false, .read_lock = true, .integrity = true, + .zeroizable = true, }, [OTP_PART_SECRET1] = { - .size = 88u, - .offset = 16048u, - .digest_offset = 16128u, + .size = 32u, + .offset = 16088u, + .zer_offset = 16112u, + .digest_offset = 16104u, .hw_digest = true, .sw_digest = false, .secret = true, @@ -248,11 +288,13 @@ static const OtOTPPartDesc OtOTPPartDescs[] = { .write_lock = false, .read_lock = true, .integrity = true, + .zeroizable = true, }, [OTP_PART_SECRET2] = { - .size = 120u, - .offset = 16136u, - .digest_offset = 16248u, + .size = 128u, + .offset = 16120u, + .zer_offset = 16240u, + .digest_offset = 16232u, .hw_digest = true, .sw_digest = false, .secret = true, @@ -260,12 +302,14 @@ static const OtOTPPartDesc OtOTPPartDescs[] = { .write_lock = false, .read_lock = true, .integrity = true, + .zeroizable = true, .iskeymgr_creator = true, }, [OTP_PART_SECRET3] = { - .size = 40u, - .offset = 16256u, - .digest_offset = 16288u, + .size = 48u, + .offset = 16248u, + .zer_offset = 16288u, + .digest_offset = 16280u, .hw_digest = true, .sw_digest = false, .secret = true, @@ -273,11 +317,13 @@ static const OtOTPPartDesc OtOTPPartDescs[] = { .write_lock = false, .read_lock = true, .integrity = true, + .zeroizable = true, .iskeymgr_owner = true, }, [OTP_PART_LIFE_CYCLE] = { .size = 88u, .offset = 16296u, + .zer_offset = UINT16_MAX, .digest_offset = UINT16_MAX, .hw_digest = false, .sw_digest = false,