diff --git a/hw/opentitan/ot_spi_device.c b/hw/opentitan/ot_spi_device.c
index 9ce321cb9d7f..a6b79432e592 100644
--- a/hw/opentitan/ot_spi_device.c
+++ b/hw/opentitan/ot_spi_device.c
@@ -574,17 +574,19 @@ static const char *TPM_REG_NAMES[TPM_REGS_COUNT] = {
 #define INTERCEPT_EN_MASK \
     (R_INTERCEPT_EN_STATUS_MASK | R_INTERCEPT_EN_JEDEC_MASK | \
      R_INTERCEPT_EN_SFDP_MASK | R_INTERCEPT_EN_MBX_MASK)
-#define FLASH_STATUS_STATUS_MASK \
-    (R_FLASH_STATUS_WEL_MASK | R_FLASH_STATUS_BP0_MASK | \
-     R_FLASH_STATUS_BP1_MASK | R_FLASH_STATUS_BP2_MASK | \
-     R_FLASH_STATUS_TB_MASK | R_FLASH_STATUS_SEC_MASK | \
-     R_FLASH_STATUS_SRP0_MASK | R_FLASH_STATUS_SRP1_MASK | \
-     R_FLASH_STATUS_QE_MASK | R_FLASH_STATUS_LB1_MASK | \
-     R_FLASH_STATUS_LB2_MASK | R_FLASH_STATUS_LB3_MASK | \
-     R_FLASH_STATUS_CMP_MASK | R_FLASH_STATUS_SUS_MASK | \
-     R_FLASH_STATUS_WPS_MASK | R_FLASH_STATUS_DRV0_MASK | \
-     R_FLASH_STATUS_DRV1_MASK | R_FLASH_STATUS_HOLD_NRST_MASK)
-#define FLASH_STATUS_MASK (R_FLASH_STATUS_BUSY_MASK | FLASH_STATUS_STATUS_MASK)
+#define FLASH_STATUS_RW0C_MASK \
+    (R_FLASH_STATUS_BUSY_MASK | R_FLASH_STATUS_WEL_MASK)
+#define FLASH_STATUS_RW_MASK \
+    (R_FLASH_STATUS_BP0_MASK | R_FLASH_STATUS_BP1_MASK | \
+     R_FLASH_STATUS_BP2_MASK | R_FLASH_STATUS_TB_MASK | \
+     R_FLASH_STATUS_SEC_MASK | R_FLASH_STATUS_SRP0_MASK | \
+     R_FLASH_STATUS_SRP1_MASK | R_FLASH_STATUS_QE_MASK | \
+     R_FLASH_STATUS_LB1_MASK | R_FLASH_STATUS_LB2_MASK | \
+     R_FLASH_STATUS_LB3_MASK | R_FLASH_STATUS_CMP_MASK | \
+     R_FLASH_STATUS_SUS_MASK | R_FLASH_STATUS_WPS_MASK | \
+     R_FLASH_STATUS_DRV0_MASK | R_FLASH_STATUS_DRV1_MASK | \
+     R_FLASH_STATUS_HOLD_NRST_MASK)
+#define FLASH_STATUS_MASK (FLASH_STATUS_RW0C_MASK | FLASH_STATUS_RW_MASK)
 #define JEDEC_CC_MASK     (R_JEDEC_CC_CC_MASK | R_JEDEC_CC_NUM_CC_MASK)
 #define JEDEC_ID_MASK     (R_JEDEC_ID_DEVICE_MASK | R_JEDEC_ID_MF_MASK)
 
@@ -1633,9 +1635,14 @@ static void ot_spi_device_spi_regs_write(void *opaque, hwaddr addr,
         val32 &= INTERCEPT_EN_MASK;
         s->spi_regs[reg] = val32;
         break;
+    case R_ADDR_MODE:
+        s->spi_regs[reg] &= ~R_ADDR_MODE_ADDR_4B_EN_MASK;
+        s->spi_regs[reg] |= val32 & R_ADDR_MODE_ADDR_4B_EN_MASK; /* RW */
+        break;
     case R_FLASH_STATUS:
-        s->spi_regs[reg] &= val32 & R_FLASH_STATUS_BUSY_MASK; /* RW0C */
-        s->spi_regs[reg] |= val32 & FLASH_STATUS_STATUS_MASK; /* RW */
+        s->spi_regs[reg] &= val32 & FLASH_STATUS_RW0C_MASK; /* RW0C */
+        s->spi_regs[reg] &= ~FLASH_STATUS_RW_MASK;
+        s->spi_regs[reg] |= val32 & FLASH_STATUS_RW_MASK; /* RW */
         break;
     case R_JEDEC_CC:
         val32 &= JEDEC_CC_MASK;
diff --git a/tests/opentitan/data/earlgrey-tests.txt b/tests/opentitan/data/earlgrey-tests.txt
index 32e5c9ca79a8..d1e331509b44 100644
--- a/tests/opentitan/data/earlgrey-tests.txt
+++ b/tests/opentitan/data/earlgrey-tests.txt
@@ -86,8 +86,8 @@ pass: //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_qemu_rom_with_fa
 pass: //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_qemu_sival_rom_ext
 pass: //sw/device/tests:alert_handler_ping_ok_test_sim_qemu_rom_with_fake_keys
 pass: //sw/device/tests:alert_handler_ping_ok_test_sim_qemu_sival_rom_ext
-pass: //sw/device/tests:aon_timer_irq_test_sim_qemu_rom_with_fake_keys
-pass: //sw/device/tests:aon_timer_irq_test_sim_qemu_sival_rom_ext
+flaky: //sw/device/tests:aon_timer_irq_test_sim_qemu_rom_with_fake_keys # Test checks IRQ timing which may be slightly inaccurate on QEMU, and so rarely fails
+flaky: //sw/device/tests:aon_timer_irq_test_sim_qemu_sival_rom_ext # Test checks IRQ timing which may be slightly inaccurate on QEMU, and so rarely fails
 flaky: //sw/device/tests/autogen:alert_test_sim_qemu_rom_with_fake_keys  # Fails rarely when running in parallel on CI runners, likely due to timing issues.
 flaky: //sw/device/tests/autogen:alert_test_sim_qemu_sival_rom_ext  # Fails rarely when running in parallel on CI runners, likely due to timing issues.
 pass: //sw/device/tests:clkmgr_jitter_frequency_test_sim_qemu_rom_with_fake_keys
@@ -106,10 +106,10 @@ pass: //sw/device/tests:clkmgr_smoketest_sim_qemu_rom_with_fake_keys
 pass: //sw/device/tests:clkmgr_smoketest_sim_qemu_sival_rom_ext
 pass: //sw/device/tests:crt_test_sim_qemu_rom_with_fake_keys
 pass: //sw/device/tests:crt_test_sim_qemu_sival_rom_ext
-pass: //sw/device/tests/crypto:aes_functest_sim_qemu_rom_with_fake_keys
-pass: //sw/device/tests/crypto:aes_functest_sim_qemu_sival_rom_ext
-pass: //sw/device/tests/crypto:aes_gcm_functest_sim_qemu_rom_with_fake_keys
-pass: //sw/device/tests/crypto:aes_gcm_functest_sim_qemu_sival_rom_ext
+flaky: //sw/device/tests/crypto:aes_functest_sim_qemu_rom_with_fake_keys  # Test fails sometimes due to incorrect encrypted data when it didn't before, need to root cause
+flaky: //sw/device/tests/crypto:aes_functest_sim_qemu_sival_rom_ext  # Test fails sometimes due to incorrect encrypted data when it didn't before, need to root cause
+flaky: //sw/device/tests/crypto:aes_gcm_functest_sim_qemu_rom_with_fake_keys  # Test fails ~1% of the time due to an illegal instruction exception, need to root cause
+flaky: //sw/device/tests/crypto:aes_gcm_functest_sim_qemu_sival_rom_ext  # Test fails ~1% of the time due to an illegal instruction exception, need to root cause
 flaky: //sw/device/tests/crypto:aes_gcm_timing_test_sim_qemu_rom_with_fake_keys  # Passes < 5% of the time. This test checks for constant time crypto operations.
 flaky: //sw/device/tests/crypto:aes_gcm_timing_test_sim_qemu_sival_rom_ext  # Passes < 5% of the time. This test checks for constant time crypto operations.
 pass: //sw/device/tests/crypto:aes_kwp_functest_sim_qemu_rom_with_fake_keys
@@ -120,8 +120,8 @@ pass: //sw/device/tests/crypto:aes_kwp_sideload_functest_sim_qemu_rom_with_fake_
 pass: //sw/device/tests/crypto:aes_kwp_sideload_functest_sim_qemu_sival_rom_ext
 pass: //sw/device/tests/crypto:aes_sideload_functest_sim_qemu_rom_with_fake_keys
 pass: //sw/device/tests/crypto:aes_sideload_functest_sim_qemu_sival_rom_ext
-pass: //sw/device/tests/crypto:drbg_functest_sim_qemu_rom_with_fake_keys
-pass: //sw/device/tests/crypto:drbg_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:drbg_functest_sim_qemu_rom_with_fake_keys  # Rarely fails entropy randomness check due to lack of key masking
+pass: //sw/device/tests/crypto:drbg_functest_sim_qemu_sival_rom_ext  # Rarely fails entropy randomness check due to lack of key masking
 pass: //sw/device/tests/crypto:ecdh_p256_functest_sim_qemu_rom_with_fake_keys
 pass: //sw/device/tests/crypto:ecdh_p256_functest_sim_qemu_sival_rom_ext
 pass: //sw/device/tests/crypto:ecdh_p256_sideload_functest_sim_qemu_rom_with_fake_keys
@@ -182,8 +182,8 @@ pass: //sw/device/tests/crypto:sha384_functest_sim_qemu_rom_with_fake_keys
 pass: //sw/device/tests/crypto:sha384_functest_sim_qemu_sival_rom_ext
 pass: //sw/device/tests/crypto:sha512_functest_sim_qemu_rom_with_fake_keys
 pass: //sw/device/tests/crypto:sha512_functest_sim_qemu_sival_rom_ext
-pass: //sw/device/tests/crypto:symmetric_keygen_functest_sim_qemu_rom_with_fake_keys
-pass: //sw/device/tests/crypto:symmetric_keygen_functest_sim_qemu_sival_rom_ext
+flaky: //sw/device/tests/crypto:symmetric_keygen_functest_sim_qemu_rom_with_fake_keys  # Rarely fails entropy randomness check due to lack of key masking
+flaky: //sw/device/tests/crypto:symmetric_keygen_functest_sim_qemu_sival_rom_ext  # Rarely fails entropy randomness check due to lack of key masking
 pass: //sw/device/tests:csrng_kat_test_sim_qemu_rom_with_fake_keys
 pass: //sw/device/tests:csrng_kat_test_sim_qemu_sival_rom_ext
 pass: //sw/device/tests:csrng_smoketest_sim_qemu_rom_with_fake_keys