From 7b0dfd16729d10a8c6c83086e39ac8fa773ce6b6 Mon Sep 17 00:00:00 2001 From: Alex Jones Date: Wed, 29 Oct 2025 17:59:37 +0000 Subject: [PATCH 1/2] [ot] target/riscv: ibex_csr: Fix Ibex `mtvec` WARL writes This fixes the behaviour of mtvec writes on Ibex to allow writes in non-vectored mtvec encode modes, but always tie the written mode to vectored (mtvec is WARL). This is required for the ECALL RISC-V compliance test to pass in QEMU (as it currently does on FPGA and Silicon targets). Signed-off-by: Alex Jones --- target/riscv/ibex_csr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/ibex_csr.c b/target/riscv/ibex_csr.c index 39a8849e3fb2..4d38a1b8298e 100644 --- a/target/riscv/ibex_csr.c +++ b/target/riscv/ibex_csr.c @@ -113,8 +113,9 @@ static RISCVException write_mtvec(CPURISCVState *env, int csrno, "CSR_MTVEC: reserved mode not supported 0x" TARGET_FMT_lx "\n", val); - /* WARL */ - return RISCV_EXCP_NONE; + /* WARL, Ibex will tie any invalid mode writes to 0b01 (vectored) */ + val &= ~3u; + val |= 1u; } /* bits [7:2] are always 0, address should be aligned in 256 bytes */ From 0a962dbdb085668c03cbf4d07b51d71bb87502ed Mon Sep 17 00:00:00 2001 From: Alex Jones Date: Thu, 30 Oct 2025 11:29:36 +0000 Subject: [PATCH 2/2] [ot] tests/opentitan: earlgrey-tests: Add passing ECALL compliance test Signed-off-by: Alex Jones --- tests/opentitan/data/earlgrey-tests.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/opentitan/data/earlgrey-tests.txt b/tests/opentitan/data/earlgrey-tests.txt index c5bbee7e38c9..b81902ec0d98 100644 --- a/tests/opentitan/data/earlgrey-tests.txt +++ b/tests/opentitan/data/earlgrey-tests.txt @@ -640,6 +640,8 @@ pass: //third_party/riscv-compliance:I-CSRRWI-01_sim_qemu_rom_with_fake_keys pass: //third_party/riscv-compliance:I-CSRRWI-01_sim_qemu_sival_rom_ext pass: //third_party/riscv-compliance:I-DELAY_SLOTS-01_sim_qemu_rom_with_fake_keys pass: //third_party/riscv-compliance:I-DELAY_SLOTS-01_sim_qemu_sival_rom_ext +pass: //third_party/riscv-compliance:I-ECALL-01_sim_qemu_rom_with_fake_keys +pass: //third_party/riscv-compliance:I-ECALL-01_sim_qemu_sival_rom_ext pass: //third_party/riscv-compliance:I-ENDIANESS-01_sim_qemu_rom_with_fake_keys pass: //third_party/riscv-compliance:I-ENDIANESS-01_sim_qemu_sival_rom_ext pass: //third_party/riscv-compliance:I-IO-01_sim_qemu_rom_with_fake_keys