From d6909036f427506cde8316cb0fe187092561ac3c Mon Sep 17 00:00:00 2001 From: Alex Jones Date: Wed, 29 Oct 2025 22:59:44 +0000 Subject: [PATCH] [ot] hw/riscv: ot_earlgrey: Leave hart disabled on reset The hart should be disabled on soc reset, and should instead be enabled by the PowerManager when the reset sequence has been properly handled, as the comment suggests. This is already being done correctly on Darjeeling, but is not being done on Earlgrey. Signed-off-by: Alex Jones --- hw/riscv/ot_earlgrey.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/ot_earlgrey.c b/hw/riscv/ot_earlgrey.c index 0fdfc591cefbb..a4197d355d85e 100644 --- a/hw/riscv/ot_earlgrey.c +++ b/hw/riscv/ot_earlgrey.c @@ -1720,7 +1720,7 @@ static void ot_eg_soc_reset_hold(Object *obj, ResetType type) * PowerManager takes care of managing Ibex reset when ready */ CPUState *cs = CPU(s->devices[OT_EG_SOC_DEV_HART]); - cs->disabled = false; + cs->disabled = true; } static void ot_eg_soc_reset_exit(Object *obj, ResetType type)