From 2f814ecc32cb2d0ce4522ea17644ad8fb01cab20 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lo=C3=AFc=20Lefort?= Date: Wed, 6 Sep 2023 16:37:10 +0200 Subject: [PATCH 01/12] [ot] use proper capitalization for EarlGrey MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Loïc Lefort --- MAINTAINERS | 2 +- docs/opentitan/checkregs.md | 2 +- docs/opentitan/earlgrey.md | 2 +- docs/opentitan/index.md | 2 +- hw/opentitan/ot_csrng.c | 2 +- hw/opentitan/ot_otp_earlgrey.c | 4 ++-- hw/opentitan/ot_otp_earlgrey_lcvalues.c | 2 +- hw/opentitan/ot_ref.log | 2 +- hw/riscv/ot_earlgrey.c | 4 ++-- include/hw/opentitan/ot_otp_earlgrey.h | 4 ++-- target/riscv/ibex_csr.c | 7 ++++--- 11 files changed, 17 insertions(+), 16 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 676303e3eef44..3ce2685c5c9cc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1495,7 +1495,7 @@ F: pc-bios/vof* RISC-V Machines --------------- -Earlgrey OpenTitan platform +EarlGrey OpenTitan platform M: Emmanuel Blot M: Loïc Lefort S: Supported diff --git a/docs/opentitan/checkregs.md b/docs/opentitan/checkregs.md index 3e0b7e423e855..d16fcf5a86ab6 100644 --- a/docs/opentitan/checkregs.md +++ b/docs/opentitan/checkregs.md @@ -42,7 +42,7 @@ options: ### Examples -* All Earlgrey register files have been copied into `opentitan/regs-251rc1` +* All EarlGrey register files have been copied into `opentitan/regs-251rc1` ````sh scripts/opentitan/checkregs.py -k -q hw/opentitan ~/opentitan/regs-251rc1/*.h diff --git a/docs/opentitan/earlgrey.md b/docs/opentitan/earlgrey.md index fe94dab09eb50..e004a37ef127b 100644 --- a/docs/opentitan/earlgrey.md +++ b/docs/opentitan/earlgrey.md @@ -1,4 +1,4 @@ -# Earlgrey CW310 +# EarlGrey CW310 ## Supported version diff --git a/docs/opentitan/index.md b/docs/opentitan/index.md index 5ce3932d1b17b..51b5e8798bff9 100644 --- a/docs/opentitan/index.md +++ b/docs/opentitan/index.md @@ -32,4 +32,4 @@ ninja qemu-img ## Supported platforms * [IbexDemo](ibexdemo.md) built for Digilent Arty7 board - * [Earlgrey](earlgrey.md) build for CW310 "Bergen" board + * [EarlGrey](earlgrey.md) build for CW310 "Bergen" board diff --git a/hw/opentitan/ot_csrng.c b/hw/opentitan/ot_csrng.c index d74d03c08c71b..749d1213b52be 100644 --- a/hw/opentitan/ot_csrng.c +++ b/hw/opentitan/ot_csrng.c @@ -830,7 +830,7 @@ static bool ot_csrng_expedite_uninstantiation(OtCSRNGInstance *inst) static void ot_csrng_handle_enable(OtCSRNGState *s) { /* - * As per Earlgrey 2.5.2-rc0: + * As per EarlGrey 2.5.2-rc0: * "CSRNG may only be enabled if ENTROPY_SRC is enabled. CSRNG may only be * disabled if all EDNs are disabled. Once disabled, CSRNG may only be * re-enabled after ENTROPY_SRC has been disabled and re-enabled." diff --git a/hw/opentitan/ot_otp_earlgrey.c b/hw/opentitan/ot_otp_earlgrey.c index e31206f353d5f..08301b261cbc4 100644 --- a/hw/opentitan/ot_otp_earlgrey.c +++ b/hw/opentitan/ot_otp_earlgrey.c @@ -1,5 +1,5 @@ /* - * QEMU OpenTitan Earlgrey One Time Programmable (OTP) memory controller + * QEMU OpenTitan EarlGrey One Time Programmable (OTP) memory controller * * Copyright (c) 2023 Rivos, Inc. * @@ -401,7 +401,7 @@ typedef struct { unsigned ecc_granule; /* size of a granule in bytes */ } OtOTPStorage; -#define OtOTPEgState OtOTPEarlgreyState +#define OtOTPEgState OtOTPEarlGreyState struct OtOTPEgState { OtOTPState parent_obj; diff --git a/hw/opentitan/ot_otp_earlgrey_lcvalues.c b/hw/opentitan/ot_otp_earlgrey_lcvalues.c index 34620310f175f..78e2e7349259f 100644 --- a/hw/opentitan/ot_otp_earlgrey_lcvalues.c +++ b/hw/opentitan/ot_otp_earlgrey_lcvalues.c @@ -1,5 +1,5 @@ /* - * QEMU OpenTitan Earlgrey One Time Programmable (OTP) life cycle values + * QEMU OpenTitan EarlGrey One Time Programmable (OTP) life cycle values * * Copyright (c) 2023 Rivos, Inc. * diff --git a/hw/opentitan/ot_ref.log b/hw/opentitan/ot_ref.log index f7db1244fe419..208365564e1a4 100644 --- a/hw/opentitan/ot_ref.log +++ b/hw/opentitan/ot_ref.log @@ -1,5 +1,5 @@ # This implementation is based on the following OpenTitan RTL version: GIT_REPOS="https://github.com/lowRISC/opentitan" -# This is Earlgrey-M2.5.2-RC0 +# This is EarlGrey-M2.5.2-RC0 GIT_COMMIT="21ce4e9761abdf5c919b46e5ae64a5a8e24992f7" diff --git a/hw/riscv/ot_earlgrey.c b/hw/riscv/ot_earlgrey.c index 5cbb8383d53b5..c2b04bcb041ed 100644 --- a/hw/riscv/ot_earlgrey.c +++ b/hw/riscv/ot_earlgrey.c @@ -87,7 +87,7 @@ static void ot_earlgrey_soc_uart_configure( /* EarlGrey/CW310 AON clock is 250 kHz */ #define OT_EARLGREY_AON_CLK_HZ 250000u -enum OtEarlgreySocDevice { +enum OtEarlGreySocDevice { OT_EARLGREY_SOC_DEV_ADC_CTRL, OT_EARLGREY_SOC_DEV_AES, OT_EARLGREY_SOC_DEV_ALERT_HANDLER, @@ -851,7 +851,7 @@ static const uint32_t ot_earlgrey_pmp_addrs[] = { #define OT_EARLGREY_MSECCFG MSECCFG(1, 1, 0) -enum OtEarlgreyBoardDevice { +enum OtEarlGreyBoardDevice { OT_EARLGREY_BOARD_DEV_SOC, OT_EARLGREY_BOARD_DEV_FLASH, _OT_EARLGREY_BOARD_DEV_COUNT, diff --git a/include/hw/opentitan/ot_otp_earlgrey.h b/include/hw/opentitan/ot_otp_earlgrey.h index 3bf696e3d632c..87a5365a84be8 100644 --- a/include/hw/opentitan/ot_otp_earlgrey.h +++ b/include/hw/opentitan/ot_otp_earlgrey.h @@ -1,5 +1,5 @@ /* - * QEMU OpenTitan Earlgrey One Time Programmable (OTP) memory controller + * QEMU OpenTitan EarlGrey One Time Programmable (OTP) memory controller * * Copyright (c) 2023 Rivos, Inc. * @@ -28,6 +28,6 @@ #include "hw/opentitan/ot_otp.h" #define TYPE_OT_OTP_EARLGREY "ot-otp-earlgrey" -OBJECT_DECLARE_TYPE(OtOTPEarlgreyState, OtOTPStateClass, OT_OTP_EARLGREY) +OBJECT_DECLARE_TYPE(OtOTPEarlGreyState, OtOTPStateClass, OT_OTP_EARLGREY) #endif /* HW_OPENTITAN_OT_OTP_EARLGREY_H */ diff --git a/target/riscv/ibex_csr.c b/target/riscv/ibex_csr.c index b6032b6567fd6..1469d788eb4f7 100644 --- a/target/riscv/ibex_csr.c +++ b/target/riscv/ibex_csr.c @@ -98,8 +98,9 @@ static RISCVException write_mtvec(CPURISCVState *env, int csrno, /* bits [1:0] encode mode; Ibex only supports 1 = vectored */ if ((val & 3u) != 1u) { qemu_log_mask(LOG_UNIMP, - "CSR_MTVEC: reserved mode not supported 0x" TARGET_FMT_lx "\n", - val); + "CSR_MTVEC: reserved mode not supported 0x" TARGET_FMT_lx + "\n", + val); /* WARL */ return RISCV_EXCP_NONE; } @@ -141,7 +142,7 @@ void riscv_add_ibex_csr_ops(RISCVCPU *cpu) /* * Since the CSR operations table is global, we only need to do * this once, regardless of where it's called from. Currently, the - * call is coming from the Ibex/Earlgrey CPU instance init function, + * call is coming from the Ibex/EarlGrey CPU instance init function, * which happens before all CPU properties are set. Therefore all * Ibex extension CSRs are added unconditionally, and the * predicate functions will filter out illegal requests based on From 25b76ef1248a18f8c9e261cbe03e38490c0d7022 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lo=C3=AFc=20Lefort?= Date: Tue, 12 Sep 2023 11:14:35 +0200 Subject: [PATCH 02/12] [ot] hw/opentitan: ot_kmac: turn some logs into asserts MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Calling ot_kmac_connect_app or ot_kmac_start_pending_app with an invalid app_idx is not a guest error. Use an assert instead. Also improve num_app checks in ot_kmac_realize. Signed-off-by: Loïc Lefort --- hw/opentitan/ot_kmac.c | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/hw/opentitan/ot_kmac.c b/hw/opentitan/ot_kmac.c index 3ea0f7c4da0e8..2aa9a6e6c48f2 100644 --- a/hw/opentitan/ot_kmac.c +++ b/hw/opentitan/ot_kmac.c @@ -1444,12 +1444,7 @@ void ot_kmac_connect_app(OtKMACState *s, unsigned app_idx, const OtKMACAppCfg *cfg, ot_kmac_response_fn fn, void *opaque) { - if (app_idx >= s->num_app) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Ignoring connection to invalid app index %u\n", - __func__, app_idx); - return; - } + g_assert(app_idx < s->num_app); OtKMACApp *app = &s->apps[app_idx]; @@ -1515,12 +1510,7 @@ static void ot_kmac_start_pending_app(OtKMACState *s) void ot_kmac_app_request(OtKMACState *s, unsigned app_idx, const OtKMACAppReq *req) { - if (app_idx >= s->num_app) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Ignoring connection to invalid app index %u\n", - __func__, app_idx); - return; - } + g_assert(app_idx < s->num_app); OtKMACApp *app = &s->apps[app_idx]; @@ -1609,8 +1599,11 @@ static void ot_kmac_realize(DeviceState *dev, Error **errp) { OtKMACState *s = OT_KMAC(dev); + /* make sure num-app property is set */ + g_assert(s->num_app > 0); + /* make sure we don't overflow pending_apps bitmask */ - g_assert(s->num_app < 32); + g_assert(s->num_app <= 32); s->apps = g_new0(OtKMACApp, s->num_app); } From b9bc0deebcefe22310597cf1a9269d7bcaea50da Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lo=C3=AFc=20Lefort?= Date: Wed, 13 Sep 2023 09:32:34 +0200 Subject: [PATCH 03/12] [ot] hw/opentitan: ot_flash: fix some register masks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Loïc Lefort --- hw/opentitan/ot_flash.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/hw/opentitan/ot_flash.c b/hw/opentitan/ot_flash.c index e2827f6866c9e..24af406020a28 100644 --- a/hw/opentitan/ot_flash.c +++ b/hw/opentitan/ot_flash.c @@ -297,6 +297,16 @@ REG32(RD_FIFO, 0x1b4u) BANK_INFO_PAGE_CFG_SCRAMBLE_EN_MASK | \ BANK_INFO_PAGE_CFG_ECC_EN_MASK | \ BANK_INFO_PAGE_CFG_HE_EN_MASK) +#define MP_REGION_CFG_MASK \ + (MP_REGION_CFG_RD_EN_MASK | \ + MP_REGION_CFG_PROG_EN_MASK | \ + MP_REGION_CFG_ERASE_EN_MASK | \ + MP_REGION_CFG_SCRAMBLE_EN_MASK | \ + MP_REGION_CFG_ECC_EN_MASK | \ + MP_REGION_CFG_HE_EN_MASK) +#define MP_REGION_MASK \ + (MP_REGION_BASE_MASK | \ + MP_REGION_SIZE_MASK) #define CONTROL_MASK \ (R_CONTROL_START_MASK | \ R_CONTROL_OP_MASK | \ @@ -1157,7 +1167,7 @@ static void ot_flash_regs_write(void *opaque, hwaddr addr, uint64_t val64, case R_MP_REGION_CFG_7: if (ot_flash_regs_is_wr_enabled(s, reg - R_MP_REGION_CFG_0 + R_REGION_CFG_REGWEN_0)) { - val32 &= BANK_INFO_PAGE_CFG_MASK; + val32 &= MP_REGION_CFG_MASK; s->regs[reg] = val32; } break; @@ -1171,12 +1181,12 @@ static void ot_flash_regs_write(void *opaque, hwaddr addr, uint64_t val64, case R_MP_REGION_7: if (ot_flash_regs_is_wr_enabled(s, reg - R_MP_REGION_0 + R_REGION_CFG_REGWEN_0)) { - val32 &= BANK_INFO_PAGE_CFG_MASK; + val32 &= MP_REGION_MASK; s->regs[reg] = val32; } break; case R_DEFAULT_REGION: - val32 &= BANK_INFO_PAGE_CFG_MASK; + val32 &= MP_REGION_CFG_MASK; s->regs[reg] = val32; break; case R_BANK0_INFO0_PAGE_CFG_0: From e2d1e860115298ed40dd668ddc8453dd35eb60ea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lo=C3=AFc=20Lefort?= Date: Fri, 15 Sep 2023 19:26:52 +0200 Subject: [PATCH 04/12] [ot] hw/opentitan: ot_otp_earlgrey: fix some traces MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Loïc Lefort --- hw/opentitan/ot_otp_earlgrey.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/hw/opentitan/ot_otp_earlgrey.c b/hw/opentitan/ot_otp_earlgrey.c index 08301b261cbc4..35d10502216d6 100644 --- a/hw/opentitan/ot_otp_earlgrey.c +++ b/hw/opentitan/ot_otp_earlgrey.c @@ -865,8 +865,8 @@ static uint64_t ot_otp_eg_regs_read(void *opaque, hwaddr addr, unsigned size) case R_INTR_TEST: case R_ALERT_TEST: qemu_log_mask(LOG_GUEST_ERROR, - "W/O register 0x%03" HWADDR_PRIx " (%s)\n", addr, - REG_NAME(reg)); + "%s: W/O register 0x%03" HWADDR_PRIx " (%s)\n", __func__, + addr, REG_NAME(reg)); val32 = 0; break; default: @@ -963,8 +963,8 @@ static void ot_otp_eg_regs_write(void *opaque, hwaddr addr, uint64_t value, case R_SECRET2_DIGEST_0: case R_SECRET2_DIGEST_1: qemu_log_mask(LOG_GUEST_ERROR, - "R/O register 0x%03" HWADDR_PRIx " (%s)\n", addr, - REG_NAME(reg)); + "%s: R/O register 0x%03" HWADDR_PRIx " (%s)\n", __func__, + addr, REG_NAME(reg)); break; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", @@ -1103,7 +1103,8 @@ static void ot_otp_eg_swcfg_write(void *opaque, hwaddr addr, uint64_t value, hwaddr reg = R32_OFF(addr); - qemu_log_mask(LOG_GUEST_ERROR, "R/O register 0x%03" HWADDR_PRIx " (%s)\n", + qemu_log_mask(LOG_GUEST_ERROR, + "%s: R/O register 0x%03" HWADDR_PRIx " (%s)\n", __func__, addr, ot_otp_eg_swcfg_reg_name(reg)); } @@ -1159,8 +1160,8 @@ static void ot_otp_eg_csrs_write(void *opaque, hwaddr addr, uint64_t value, break; case R_CSR7: qemu_log_mask(LOG_GUEST_ERROR, - "R/O register 0x%01" HWADDR_PRIx " (%s)\n", addr, - CSR_NAME(reg)); + "%s: R/O register 0x%01" HWADDR_PRIx " (%s)\n", __func__, + addr, CSR_NAME(reg)); break; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", From 0123039a7e7639bd7220739c2171c0c2a27e5e3a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lo=C3=AFc=20Lefort?= Date: Fri, 15 Sep 2023 19:19:32 +0200 Subject: [PATCH 05/12] [ot] hw/opentitan: ot_otp_earlgrey: update names for some constants MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update constant names to match names from otp_ctrl_mmap.hjson Signed-off-by: Loïc Lefort --- hw/opentitan/ot_otp_earlgrey.c | 68 ++++++++++++++++------------------ 1 file changed, 32 insertions(+), 36 deletions(-) diff --git a/hw/opentitan/ot_otp_earlgrey.c b/hw/opentitan/ot_otp_earlgrey.c index 35d10502216d6..bf280d012634c 100644 --- a/hw/opentitan/ot_otp_earlgrey.c +++ b/hw/opentitan/ot_otp_earlgrey.c @@ -124,7 +124,9 @@ REG32(SECRET1_DIGEST_0, 0x80u) REG32(SECRET1_DIGEST_1, 0x84u) REG32(SECRET2_DIGEST_0, 0x88u) REG32(SECRET2_DIGEST_1, 0x8cu) -/* Software Config Window registers (at offset +0x1000) */ +/* Software Config Window registers (at offset SW_CFG_WINDOW = +0x1000) */ +REG32(SCRATCH, 0u) +REG32(VENDOR_TEST_DIGEST, 56u) REG32(CREATOR_SW_CFG_AST_CFG, 64u) REG32(CREATOR_SW_CFG_AST_INIT_EN, 220u) REG32(CREATOR_SW_CFG_ROM_EXT_SKU, 224u) @@ -175,7 +177,7 @@ REG32(OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA, 1372u) REG32(OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES, 1376u) REG32(OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN, 1380u) REG32(OWNER_SW_CFG_MANUF_STATE, 1384u) -REG32(OWNER_SW_CFG_ROM_RSTMGR_INFO_EN_OFFSET, 1388u) +REG32(OWNER_SW_CFG_ROM_RSTMGR_INFO_EN, 1388u) REG32(OWNER_SW_CFG_DIGEST, 1656u) REG32(DEVICE_ID, 1664u) REG32(MANUF_STATE, 1696u) @@ -185,21 +187,23 @@ REG32(HW_CFG_ENABLE, 1728u) FIELD(HW_CFG_ENABLE, EN_ENTROPY_SRC_FW_READ, 16u, 8u) FIELD(HW_CFG_ENABLE, EN_ENTROPY_SRC_FW_OVER, 24u, 8u) REG32(HW_CFG_DIGEST, 1736u) -REG32(SECRET0_TEST_UNLOCK_TOKEN, 1744u) -REG32(SECRET0_TEST_EXIT_TOKEN, 1760u) +REG32(TEST_UNLOCK_TOKEN, 1744u) +REG32(TEST_EXIT_TOKEN, 1760u) REG32(SECRET0_DIGEST, 1776u) -REG32(SECRET1_FLASH_ADDR_KEY_SEED, 1784u) -REG32(SECRET1_FLASH_DATA_KEY_SEED, 1816u) -REG32(SECRET1_SRAM_DATA_KEY_SEED, 1848u) +REG32(FLASH_ADDR_KEY_SEED, 1784u) +REG32(FLASH_DATA_KEY_SEED, 1816u) +REG32(SRAM_DATA_KEY_SEED, 1848u) REG32(SECRET1_DIGEST, 1864u) -REG32(SECRET2_RMA_TOKEN, 1872u) -REG32(SECRET2_CREATOR_ROOT_KEY_SHARE0, 1888u) -REG32(SECRET2_CREATOR_ROOT_KEY_SHARE1, 1920u) +REG32(RMA_TOKEN, 1872u) +REG32(CREATOR_ROOT_KEY_SHARE0, 1888u) +REG32(CREATOR_ROOT_KEY_SHARE1, 1920u) REG32(SECRET2_DIGEST, 1952u) REG32(LC_TRANSITION_CNT, 1960u) REG32(LC_STATE, 2008u) /* clang-format on */ +#define SCRATCH_SIZE 56u +#define VENDOR_TEST_DIGEST_SIZE 8u #define CREATOR_SW_CFG_AST_CFG_SIZE 156u #define CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN_SIZE 8u #define CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN_SIZE 8u @@ -210,20 +214,19 @@ REG32(LC_STATE, 2008u) #define OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES_SIZE 16u #define OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES_SIZE 64u #define OWNER_SW_CFG_DIGEST_SIZE 8u -#define OWNER_SW_CFG_DIGEST_SIZE 8u #define DEVICE_ID_SIZE 32u #define MANUF_STATE_SIZE 32u #define HW_CFG_DIGEST_SIZE 8u -#define SECRET0_TEST_UNLOCK_TOKEN_SIZE 16u -#define SECRET0_TEST_EXIT_TOKEN_SIZE 16u +#define TEST_UNLOCK_TOKEN_SIZE 16u +#define TEST_EXIT_TOKEN_SIZE 16u #define SECRET0_DIGEST_SIZE 8u -#define SECRET1_FLASH_ADDR_KEY_SEED_SIZE 32u -#define SECRET1_FLASH_DATA_KEY_SEED_SIZE 32u -#define SECRET1_SRAM_DATA_KEY_SEED_SIZE 16u +#define FLASH_ADDR_KEY_SEED_SIZE 32u +#define FLASH_DATA_KEY_SEED_SIZE 32u +#define SRAM_DATA_KEY_SEED_SIZE 16u #define SECRET1_DIGEST_SIZE 8u -#define SECRET2_RMA_TOKEN_SIZE 16u -#define SECRET2_CREATOR_ROOT_KEY_SHARE0_SIZE 32u -#define SECRET2_CREATOR_ROOT_KEY_SHARE1_SIZE 32u +#define RMA_TOKEN_SIZE 16u +#define CREATOR_ROOT_KEY_SHARE0_SIZE 32u +#define CREATOR_ROOT_KEY_SHARE1_SIZE 32u #define SECRET2_DIGEST_SIZE 8u #define LC_TRANSITION_CNT_SIZE 48u #define LC_STATE_SIZE 40u @@ -672,16 +675,9 @@ static bool ot_otp_eg_is_readable(OtOTPEgState *s, int partition, unsigned addr) READ_LOCK); break; case OTP_PART_SECRET0: - rdaccess = - ot_otp_eg_swcfg_get_part_digest(s, OTP_PART_SECRET0) == 0u; - break; case OTP_PART_SECRET1: - rdaccess = - ot_otp_eg_swcfg_get_part_digest(s, OTP_PART_SECRET1) == 0u; - break; case OTP_PART_SECRET2: - rdaccess = - ot_otp_eg_swcfg_get_part_digest(s, OTP_PART_SECRET2) == 0u; + rdaccess = ot_otp_eg_swcfg_get_part_digest(s, partition) == 0u; break; default: break; @@ -1033,21 +1029,21 @@ static const char *ot_otp_eg_swcfg_reg_name(unsigned swreg) CASE_SCALAR(OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES); CASE_SCALAR(OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN); CASE_SCALAR(OWNER_SW_CFG_MANUF_STATE); - CASE_SCALAR(OWNER_SW_CFG_ROM_RSTMGR_INFO_EN_OFFSET); + CASE_SCALAR(OWNER_SW_CFG_ROM_RSTMGR_INFO_EN); CASE_RANGE(OWNER_SW_CFG_DIGEST); CASE_RANGE(DEVICE_ID); CASE_RANGE(MANUF_STATE); CASE_RANGE(HW_CFG_DIGEST); - CASE_RANGE(SECRET0_TEST_UNLOCK_TOKEN); - CASE_RANGE(SECRET0_TEST_EXIT_TOKEN); + CASE_RANGE(TEST_UNLOCK_TOKEN); + CASE_RANGE(TEST_EXIT_TOKEN); CASE_RANGE(SECRET0_DIGEST); - CASE_RANGE(SECRET1_FLASH_ADDR_KEY_SEED); - CASE_RANGE(SECRET1_FLASH_DATA_KEY_SEED); - CASE_RANGE(SECRET1_SRAM_DATA_KEY_SEED); + CASE_RANGE(FLASH_ADDR_KEY_SEED); + CASE_RANGE(FLASH_DATA_KEY_SEED); + CASE_RANGE(SRAM_DATA_KEY_SEED); CASE_RANGE(SECRET1_DIGEST); - CASE_RANGE(SECRET2_RMA_TOKEN); - CASE_RANGE(SECRET2_CREATOR_ROOT_KEY_SHARE0); - CASE_RANGE(SECRET2_CREATOR_ROOT_KEY_SHARE1); + CASE_RANGE(RMA_TOKEN); + CASE_RANGE(CREATOR_ROOT_KEY_SHARE0); + CASE_RANGE(CREATOR_ROOT_KEY_SHARE1); CASE_RANGE(SECRET2_DIGEST); CASE_RANGE(LC_TRANSITION_CNT); CASE_RANGE(LC_STATE); From ade71727c5d9aeba2771bbf1489751bd6eb14c22 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lo=C3=AFc=20Lefort?= Date: Fri, 15 Sep 2023 19:54:02 +0200 Subject: [PATCH 06/12] [ot] hw/opentitan: ot_otp_earlgrey: use constants for partition offsets/sizes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Loïc Lefort --- hw/opentitan/ot_otp_earlgrey.c | 63 +++++++++++++++++++++------------- 1 file changed, 40 insertions(+), 23 deletions(-) diff --git a/hw/opentitan/ot_otp_earlgrey.c b/hw/opentitan/ot_otp_earlgrey.c index bf280d012634c..4f5f10e1a5662 100644 --- a/hw/opentitan/ot_otp_earlgrey.c +++ b/hw/opentitan/ot_otp_earlgrey.c @@ -357,6 +357,23 @@ static const char CSR_NAMES[CSRS_COUNT][6u] = { }; #undef CSR_NAME_ENTRY +#define OTP_PART_VENDOR_TEST_OFFSET 0u +#define OTP_PART_VENDOR_TEST_SIZE 64u +#define OTP_PART_CREATOR_SW_CFG_OFFSET 64u +#define OTP_PART_CREATOR_SW_CFG_SIZE 800u +#define OTP_PART_OWNER_SW_CFG_OFFSET 864u +#define OTP_PART_OWNER_SW_CFG_SIZE 800u +#define OTP_PART_HW_CFG_OFFSET 1664u +#define OTP_PART_HW_CFG_SIZE 80u +#define OTP_PART_SECRET0_OFFSET 1744u +#define OTP_PART_SECRET0_SIZE 40u +#define OTP_PART_SECRET1_OFFSET 1784u +#define OTP_PART_SECRET1_SIZE 88u +#define OTP_PART_SECRET2_OFFSET 1872u +#define OTP_PART_SECRET2_SIZE 88u +#define OTP_PART_LIFE_CYCLE_OFFSET 1960u +#define OTP_PART_LIFE_CYCLE_SIZE 88u + typedef enum { OTP_PART_VENDOR_TEST, OTP_PART_CREATOR_SW_CFG, @@ -442,9 +459,9 @@ struct OtOTPEgState { static const OtOTPPartition OtOTPPartitions[] = { [OTP_PART_VENDOR_TEST] = { - .size = 0x40u, /* 64 */ - .offset = 0u, - .digest_offset = 56u, + .size = OTP_PART_VENDOR_TEST_SIZE, + .offset = OTP_PART_VENDOR_TEST_OFFSET, + .digest_offset = R_VENDOR_TEST_DIGEST, .hw_digest = false, .secret = false, .buffered = false, @@ -454,9 +471,9 @@ static const OtOTPPartition OtOTPPartitions[] = { .wide = false, }, [OTP_PART_CREATOR_SW_CFG] = { - .size = 0x320u, /* 800u */ - .offset = 0x40u, - .digest_offset = 64u, + .size = OTP_PART_CREATOR_SW_CFG_SIZE, + .offset = OTP_PART_CREATOR_SW_CFG_OFFSET, + .digest_offset = R_CREATOR_SW_CFG_DIGEST, .hw_digest = false, .secret = false, .buffered = false, @@ -466,9 +483,9 @@ static const OtOTPPartition OtOTPPartitions[] = { .wide = false, }, [OTP_PART_OWNER_SW_CFG] = { - .size = 0x320u, /* 800u */ - .offset = 0x360u, - .digest_offset = 864u, + .size = OTP_PART_OWNER_SW_CFG_SIZE, + .offset = OTP_PART_OWNER_SW_CFG_OFFSET, + .digest_offset = R_OWNER_SW_CFG_DIGEST, .hw_digest = false, .secret = false, .buffered = false, @@ -478,9 +495,9 @@ static const OtOTPPartition OtOTPPartitions[] = { .wide = false, }, [OTP_PART_HW_CFG] = { - .size = 80u, - .offset = 0x680u, - .digest_offset = 1736u, + .size = OTP_PART_HW_CFG_SIZE, + .offset = OTP_PART_HW_CFG_OFFSET, + .digest_offset = R_HW_CFG_DIGEST, .hw_digest = true, .secret = false, .buffered = true, @@ -490,9 +507,9 @@ static const OtOTPPartition OtOTPPartitions[] = { .wide = false, }, [OTP_PART_SECRET0] = { - .size = 40u, - .offset = 0x6d0u, - .digest_offset = 1776u, + .size = OTP_PART_SECRET0_SIZE, + .offset = OTP_PART_SECRET0_OFFSET, + .digest_offset = R_SECRET0_DIGEST, .hw_digest = true, .secret = true, .buffered = true, @@ -502,9 +519,9 @@ static const OtOTPPartition OtOTPPartitions[] = { .wide = true, }, [OTP_PART_SECRET1] = { - .size = 88u, - .offset = 0x6f8u, - .digest_offset = 1864u, + .size = OTP_PART_SECRET1_SIZE, + .offset = OTP_PART_SECRET1_OFFSET, + .digest_offset = R_SECRET1_DIGEST, .hw_digest = true, .secret = true, .buffered = true, @@ -514,9 +531,9 @@ static const OtOTPPartition OtOTPPartitions[] = { .wide = true, }, [OTP_PART_SECRET2] = { - .size = 88u, - .offset = 0x750u, - .digest_offset = 1952u, + .size = OTP_PART_SECRET2_SIZE, + .offset = OTP_PART_SECRET2_OFFSET, + .digest_offset = R_SECRET2_DIGEST, .hw_digest = true, .secret = true, .buffered = true, @@ -526,8 +543,8 @@ static const OtOTPPartition OtOTPPartitions[] = { .wide = true, }, [OTP_PART_LIFE_CYCLE] = { - .size = 88u, - .offset = 0x7a8u, + .size = OTP_PART_LIFE_CYCLE_SIZE, + .offset = OTP_PART_LIFE_CYCLE_OFFSET, .digest_offset = UINT16_MAX, .hw_digest = false, .secret = false, From 94f404f01e75b884dcf9a9ddd9171f8536694de9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lo=C3=AFc=20Lefort?= Date: Fri, 15 Sep 2023 19:25:06 +0200 Subject: [PATCH 07/12] [ot] hw/opentitan: ot_otp_earlgrey: implement read locks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Loïc Lefort --- hw/opentitan/ot_otp_earlgrey.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/hw/opentitan/ot_otp_earlgrey.c b/hw/opentitan/ot_otp_earlgrey.c index 4f5f10e1a5662..9c792a20ae895 100644 --- a/hw/opentitan/ot_otp_earlgrey.c +++ b/hw/opentitan/ot_otp_earlgrey.c @@ -789,6 +789,9 @@ static uint64_t ot_otp_eg_regs_read(void *opaque, hwaddr addr, unsigned size) case R_DIRECT_ACCESS_RDATA_0: case R_DIRECT_ACCESS_RDATA_1: case R_DIRECT_ACCESS_ADDRESS: + case R_VENDOR_TEST_READ_LOCK: + case R_CREATOR_SW_CFG_READ_LOCK: + case R_OWNER_SW_CFG_READ_LOCK: val32 = s->regs[reg]; break; case R_STATUS: @@ -807,9 +810,6 @@ static uint64_t ot_otp_eg_regs_read(void *opaque, hwaddr addr, unsigned size) case R_CHECK_TIMEOUT: case R_INTEGRITY_CHECK_PERIOD: case R_CONSISTENCY_CHECK_PERIOD: - case R_VENDOR_TEST_READ_LOCK: - case R_CREATOR_SW_CFG_READ_LOCK: - case R_OWNER_SW_CFG_READ_LOCK: /* TODO: not yet implemented */ val32 = 0; break; @@ -945,15 +945,18 @@ static void ot_otp_eg_regs_write(void *opaque, hwaddr addr, uint64_t value, case R_DIRECT_ACCESS_WDATA_1: s->regs[reg] = val32; break; + case R_VENDOR_TEST_READ_LOCK: + case R_CREATOR_SW_CFG_READ_LOCK: + case R_OWNER_SW_CFG_READ_LOCK: + val32 &= READ_LOCK_MASK; + s->regs[reg] &= val32; /* RW0C */ + break; case R_CHECK_TRIGGER_REGWEN: case R_CHECK_TRIGGER: case R_CHECK_REGWEN: case R_CHECK_TIMEOUT: case R_INTEGRITY_CHECK_PERIOD: case R_CONSISTENCY_CHECK_PERIOD: - case R_VENDOR_TEST_READ_LOCK: - case R_CREATOR_SW_CFG_READ_LOCK: - case R_OWNER_SW_CFG_READ_LOCK: /* TODO: not yet implemented */ break; case R_STATUS: From c96460189f3c2ce4cb20af18cd9c572064e40306 Mon Sep 17 00:00:00 2001 From: Emmanuel Blot Date: Tue, 12 Sep 2023 18:29:19 +0200 Subject: [PATCH 08/12] [ot] hw/opentitan: ot_aes: fix missing func name in log guest error msgs Signed-off-by: Emmanuel Blot --- hw/opentitan/ot_aes.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/opentitan/ot_aes.c b/hw/opentitan/ot_aes.c index 058dc57c2d773..bbc014934e73f 100644 --- a/hw/opentitan/ot_aes.c +++ b/hw/opentitan/ot_aes.c @@ -1003,8 +1003,8 @@ static uint64_t ot_aes_read(void *opaque, hwaddr addr, unsigned size) case R_DATA_IN_3: case R_TRIGGER: qemu_log_mask(LOG_GUEST_ERROR, - "W/O register 0x%02" HWADDR_PRIx " (%s)\n", addr, - REG_NAME(reg)); + "%s: W/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__, + addr, REG_NAME(reg)); val32 = 0u; break; case R_IV_0: @@ -1085,8 +1085,8 @@ static void ot_aes_write(void *opaque, hwaddr addr, uint64_t val64, case R_DATA_OUT_3: case R_STATUS: qemu_log_mask(LOG_GUEST_ERROR, - "R/O register 0x%02" HWADDR_PRIx " (%s)\n", addr, - REG_NAME(reg)); + "%s: R/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__, + addr, REG_NAME(reg)); break; case R_KEY_SHARE0_0: case R_KEY_SHARE0_1: From 17f46d90791d72602ac1306284d157157d2d9ac8 Mon Sep 17 00:00:00 2001 From: Emmanuel Blot Date: Thu, 14 Sep 2023 11:03:55 +0200 Subject: [PATCH 09/12] [ot] hw/opentitan: ot_pwrmgr: fix invalid syntax Signed-off-by: Emmanuel Blot --- hw/opentitan/ot_pwrmgr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/opentitan/ot_pwrmgr.c b/hw/opentitan/ot_pwrmgr.c index 7a419bd608b07..1492065a55c84 100644 --- a/hw/opentitan/ot_pwrmgr.c +++ b/hw/opentitan/ot_pwrmgr.c @@ -282,10 +282,11 @@ static void ot_pwrmgr_rst_req(void *opaque, int irq, int level) switch (irq) { case OT_PWRMGR_RST_REQ_SYSRST: - s->reset_req.req = OT_RSTMGR_RESET_SYSCTRL, s->reset_req.domain = false; + s->reset_req.req = OT_RSTMGR_RESET_SYSCTRL; + s->reset_req.domain = false; break; case OT_PWRMGR_RST_REQ_AON_TIMER: - s->reset_req.req = OT_RSTMGR_RESET_AON_TIMER, + s->reset_req.req = OT_RSTMGR_RESET_AON_TIMER; s->reset_req.domain = false; break; default: From 9d57f12f393d1780395628891a7ffe17b93a955d Mon Sep 17 00:00:00 2001 From: Emmanuel Blot Date: Fri, 15 Sep 2023 19:15:08 +0200 Subject: [PATCH 10/12] [ot] hw/opentitan: ot_pwrmgr: accept no rom Signed-off-by: Emmanuel Blot --- hw/opentitan/ot_pwrmgr.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/hw/opentitan/ot_pwrmgr.c b/hw/opentitan/ot_pwrmgr.c index 1492065a55c84..ed05928aaef95 100644 --- a/hw/opentitan/ot_pwrmgr.c +++ b/hw/opentitan/ot_pwrmgr.c @@ -515,14 +515,16 @@ static void ot_pwrmgr_realize(DeviceState *dev, Error **errp) { OtPwrMgrState *s = OT_PWRMGR(dev); - g_assert(s->num_rom); - - s->roms = g_new0(OtPwrMgrRomStatus, s->num_rom); - - qdev_init_gpio_in_named(dev, &ot_pwrmgr_rom_good, OPENTITAN_PWRMGR_ROM_GOOD, - s->num_rom); - qdev_init_gpio_in_named(dev, &ot_pwrmgr_rom_done, OPENTITAN_PWRMGR_ROM_DONE, - s->num_rom); + if (s->num_rom) { + s->roms = g_new0(OtPwrMgrRomStatus, s->num_rom); + + qdev_init_gpio_in_named(dev, &ot_pwrmgr_rom_good, + OPENTITAN_PWRMGR_ROM_GOOD, s->num_rom); + qdev_init_gpio_in_named(dev, &ot_pwrmgr_rom_done, + OPENTITAN_PWRMGR_ROM_DONE, s->num_rom); + } else { + s->roms = NULL; + } } static void ot_pwrmgr_init(Object *obj) From c61909a9d4acb8587178b5df6a8d490bb160cc9d Mon Sep 17 00:00:00 2001 From: Emmanuel Blot Date: Fri, 15 Sep 2023 19:15:28 +0200 Subject: [PATCH 11/12] [ot] hw/opentitan: ot_sram_ctrl: make OTP link optional Signed-off-by: Emmanuel Blot --- hw/opentitan/ot_sram_ctrl.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/hw/opentitan/ot_sram_ctrl.c b/hw/opentitan/ot_sram_ctrl.c index 76505bfcacf13..98220bcf83d42 100644 --- a/hw/opentitan/ot_sram_ctrl.c +++ b/hw/opentitan/ot_sram_ctrl.c @@ -100,8 +100,9 @@ struct OtSramCtrlState { bool otp_ifetch; bool cfg_ifetch; - OtOTPState *otp_ctrl; + OtOTPState *otp_ctrl; /* optional */ uint32_t size; + bool ifetch; /* only used when no otp_ctrl is defined */ }; static uint64_t ot_sram_ctrl_regs_read(void *opaque, hwaddr addr, unsigned size) @@ -203,6 +204,7 @@ static Property ot_sram_ctrl_properties[] = { DEFINE_PROP_LINK("otp_ctrl", OtSramCtrlState, otp_ctrl, TYPE_OT_OTP, OtOTPState *), DEFINE_PROP_UINT32("size", OtSramCtrlState, size, 0u), + DEFINE_PROP_BOOL("ifetch", OtSramCtrlState, ifetch, false), DEFINE_PROP_END_OF_LIST(), }; @@ -226,9 +228,13 @@ static void ot_sram_ctrl_reset(DeviceState *dev) s->regs[R_EXEC] = 0x9u; s->regs[R_CTRL_REGWEN] = 0x1u; - OtOTPStateClass *oc = - OBJECT_GET_CLASS(OtOTPStateClass, s->otp_ctrl, TYPE_OT_OTP); - s->otp_ifetch = oc->get_hw_cfg(s->otp_ctrl)->en_sram_ifetch; + if (s->otp_ctrl) { + OtOTPStateClass *oc = + OBJECT_GET_CLASS(OtOTPStateClass, s->otp_ctrl, TYPE_OT_OTP); + s->otp_ifetch = oc->get_hw_cfg(s->otp_ctrl)->en_sram_ifetch; + } else { + s->otp_ifetch = s->ifetch; + } s->cfg_ifetch = 0u; /* not used for now */ } @@ -236,7 +242,6 @@ static void ot_sram_ctrl_realize(DeviceState *dev, Error **errp) { OtSramCtrlState *s = OT_SRAM_CTRL(dev); - g_assert(s->otp_ctrl); g_assert(s->size); MemoryRegion *mr = &s->mem; From 39cfee681b0c1d4e98f3412b77ab6dfc3600d21a Mon Sep 17 00:00:00 2001 From: Emmanuel Blot Date: Fri, 15 Sep 2023 17:13:03 +0200 Subject: [PATCH 12/12] [ot] hw/riscv: move PMP macros from ot_earlgrey to ibex_common Signed-off-by: Emmanuel Blot --- hw/riscv/ot_earlgrey.c | 76 +++++++++++++++------------------- include/hw/riscv/ibex_common.h | 24 +++++++++++ 2 files changed, 57 insertions(+), 43 deletions(-) diff --git a/hw/riscv/ot_earlgrey.c b/hw/riscv/ot_earlgrey.c index c2b04bcb041ed..d10463e9ee4f7 100644 --- a/hw/riscv/ot_earlgrey.c +++ b/hw/riscv/ot_earlgrey.c @@ -797,59 +797,49 @@ static const IbexDeviceDef ot_earlgrey_soc_devices[] = { /* clang-format on */ }; -#define PMP_CFG(_l_, _a_, _x_, _w_, _r_) \ - ((uint8_t)(((_l_) << 7u) | ((_a_) << 3u) | ((_x_) << 2u) | ((_w_) << 1u) | \ - ((_r_)))) -#define PMP_ADDR(_a_) ((_a_) >> 2u) - -#define MSECCFG(_rlb_, _mmwp_, _mml_) \ - (((_rlb_) << 2u) | ((_mmwp_) << 1u) | ((_mml_))) - -enum { PMP_MODE_OFF, PMP_MODE_TOR, PMP_MODE_NA4, PMP_MODE_NAPOT }; - static const uint8_t ot_earlgrey_pmp_cfgs[] = { /* clang-format off */ - PMP_CFG(0, PMP_MODE_OFF, 0, 0, 0), - PMP_CFG(0, PMP_MODE_OFF, 0, 0, 0), - PMP_CFG(1, PMP_MODE_NAPOT, 1, 0, 1), /* rgn 2 [ROM: LRX] */ - PMP_CFG(0, PMP_MODE_OFF, 0, 0, 0), - PMP_CFG(0, PMP_MODE_OFF, 0, 0, 0), - PMP_CFG(0, PMP_MODE_OFF, 0, 0, 0), - PMP_CFG(0, PMP_MODE_OFF, 0, 0, 0), - PMP_CFG(0, PMP_MODE_OFF, 0, 0, 0), - PMP_CFG(0, PMP_MODE_OFF, 0, 0, 0), - PMP_CFG(0, PMP_MODE_OFF, 0, 0, 0), - PMP_CFG(0, PMP_MODE_OFF, 0, 0, 0), - PMP_CFG(1, PMP_MODE_TOR, 0, 1, 1), /* rgn 11 [MMIO: LRW] */ - PMP_CFG(0, PMP_MODE_OFF, 0, 0, 0), - PMP_CFG(1, PMP_MODE_NAPOT, 1, 1, 1), /* rgn 13 [DV_ROM: LRWX] */ - PMP_CFG(0, PMP_MODE_OFF, 0, 0, 0), - PMP_CFG(0, PMP_MODE_OFF, 0, 0, 0) + IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0), + IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0), + IBEX_PMP_CFG(1, IBEX_PMP_MODE_NAPOT, 1, 0, 1), /* rgn 2 [ROM: LRX] */ + IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0), + IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0), + IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0), + IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0), + IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0), + IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0), + IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0), + IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0), + IBEX_PMP_CFG(1, IBEX_PMP_MODE_TOR, 0, 1, 1), /* rgn 11 [MMIO: LRW] */ + IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0), + IBEX_PMP_CFG(1, IBEX_PMP_MODE_NAPOT, 1, 1, 1), /* rgn 13 [DV_ROM: LRWX] */ + IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0), + IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0) /* clang-format on */ }; static const uint32_t ot_earlgrey_pmp_addrs[] = { /* clang-format off */ - PMP_ADDR(0x00000000), - PMP_ADDR(0x00000000), - PMP_ADDR(0x000083fc), /* rgn 2 [ROM: base=0x0000_8000 size (2KiB)] */ - PMP_ADDR(0x00000000), - PMP_ADDR(0x00000000), - PMP_ADDR(0x00000000), - PMP_ADDR(0x00000000), - PMP_ADDR(0x00000000), - PMP_ADDR(0x00000000), - PMP_ADDR(0x00000000), - PMP_ADDR(0x40000000), /* rgn 10 [MMIO: lo=0x4000_0000] */ - PMP_ADDR(0x42010000), /* rgn 11 [MMIO: hi=0x4201_0000] */ - PMP_ADDR(0x00000000), - PMP_ADDR(0x000107fc), /* rgn 13 [DV_ROM: base=0x0001_0000 size (4KiB)] */ - PMP_ADDR(0x00000000), - PMP_ADDR(0x00000000) + IBEX_PMP_ADDR(0x00000000), + IBEX_PMP_ADDR(0x00000000), + IBEX_PMP_ADDR(0x000083fc), /* rgn 2 [ROM: base=0x0000_8000 sz (2KiB)] */ + IBEX_PMP_ADDR(0x00000000), + IBEX_PMP_ADDR(0x00000000), + IBEX_PMP_ADDR(0x00000000), + IBEX_PMP_ADDR(0x00000000), + IBEX_PMP_ADDR(0x00000000), + IBEX_PMP_ADDR(0x00000000), + IBEX_PMP_ADDR(0x00000000), + IBEX_PMP_ADDR(0x40000000), /* rgn 10 [MMIO: lo=0x4000_0000] */ + IBEX_PMP_ADDR(0x42010000), /* rgn 11 [MMIO: hi=0x4201_0000] */ + IBEX_PMP_ADDR(0x00000000), + IBEX_PMP_ADDR(0x000107fc), /* rgn 13 [DV_ROM: base=0x0001_0000 sz (4KiB)] */ + IBEX_PMP_ADDR(0x00000000), + IBEX_PMP_ADDR(0x00000000) /* clang-format on */ }; -#define OT_EARLGREY_MSECCFG MSECCFG(1, 1, 0) +#define OT_EARLGREY_MSECCFG IBEX_MSECCFG(1, 1, 0) enum OtEarlGreyBoardDevice { OT_EARLGREY_BOARD_DEV_SOC, diff --git a/include/hw/riscv/ibex_common.h b/include/hw/riscv/ibex_common.h index 7dee302a4bb64..2a070baaa9d3c 100644 --- a/include/hw/riscv/ibex_common.h +++ b/include/hw/riscv/ibex_common.h @@ -29,6 +29,30 @@ #include "hw/qdev-core.h" +/* ------------------------------------------------------------------------ */ +/* PMP configuration */ +/* ------------------------------------------------------------------------ */ + +#define IBEX_PMP_CFG(_l_, _a_, _x_, _w_, _r_) \ + ((uint8_t)(((_l_) << 7u) | ((_a_) << 3u) | ((_x_) << 2u) | ((_w_) << 1u) | \ + ((_r_)))) +#define IBEX_PMP_ADDR(_a_) ((_a_) >> 2u) + +#define IBEX_MSECCFG(_rlb_, _mmwp_, _mml_) \ + (((_rlb_) << 2u) | ((_mmwp_) << 1u) | ((_mml_))) + + +/* clang-format off */ + +enum { + IBEX_PMP_MODE_OFF, + IBEX_PMP_MODE_TOR, + IBEX_PMP_MODE_NA4, + IBEX_PMP_MODE_NAPOT +}; + +/* clang-format on */ + /* ------------------------------------------------------------------------ */ /* Devices & GPIOs */ /* ------------------------------------------------------------------------ */