Pinned repositories

  1. lowrisc-chip

    The root repo for lowRISC project and FPGA demos.

    SystemVerilog 309 63

  2. lowrisc.github.io

    Generated html for the lowRISC site. PRs should go to the source repo https://github.com/lowrisc/lowrisc-site

    HTML 10 5

  3. riscv-llvm

    RISC-V support for LLVM projects (LLVM, Clang, ...)

    Shell 66 19

  4. lowrisc-docker

    Docker files to generate development environment for multiple releases.

    Shell 7

  5. lowrisc-fpga

    Untethered (stand-alone) FPGA implementation of the lowRISC SoC

    C 39 7

  • Generated html for the lowRISC site. PRs should go to the source repo https://github.com/lowrisc/lowrisc-site

    HTML 10 5 Updated Oct 19, 2018
  • CSS 1 13 Updated Oct 19, 2018
  • The root repo for lowRISC project and FPGA demos.

    SystemVerilog 309 63 Updated Oct 19, 2018
  • Minimised environment for bandwidth limited sites

    Makefile Updated Oct 18, 2018
  • FreeBSD/RISC-V development

    C 1 Updated Oct 18, 2018
  • RISC-V support for LLVM projects (LLVM, Clang, ...)

    Shell 66 19 Updated Oct 18, 2018
  • Untethered (stand-alone) FPGA implementation of the lowRISC SoC

    C 39 7 Updated Oct 17, 2018
  • Rocket Chip Generator

    Scala 2 355 Updated Oct 12, 2018
  • RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)

    Shell 2 230 Updated Oct 12, 2018
  • RISC-V Proxy Kernel

    C 97 Updated Oct 12, 2018
  • FPGA demo for Digilent NEXYS 4 board

    Tcl 5 9 Updated Oct 12, 2018
  • RISC-V Linux Port

    C 5 143 Updated Oct 5, 2018
  • Port of u-boot to RISCV based ariane core

    C 1 Updated Oct 3, 2018
  • Shell 1 Updated Sep 23, 2018
  • Local version of qemu for riscv emulation use

    C 1 Updated Aug 29, 2018
  • Buildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at http://git.buildroot.net/buildroot/. Do not open issues or file pull requests here.

    Makefile 1 656 Updated Aug 24, 2018
  • KC705 implementation of the lowRISC unthethered SoC

    C 1 1 Updated Aug 20, 2018
  • Fork of OpenOCD that has RISC-V support

    C 57 GPL-2.0 Updated Aug 13, 2018
  • C 24 Updated Jul 26, 2018
  • Ariane is a 6-stage RISC-V CPU

    SystemVerilog 3 41 Updated Jul 25, 2018
  • Collection of IP cores usable to lowRISC SoC

    SystemVerilog 4 4 Updated Jul 25, 2018
  • C 78 Updated Jul 20, 2018
  • Port of lowrisc to low cost artya7-100 FPGA

    Makefile 1 Updated Jul 20, 2018
  • Simple single-port AXI memory interface

    SystemVerilog 5 Updated May 22, 2018
  • Contains commonly used UVM components (agents, environments and tests).

    SystemVerilog 1 6 Updated May 22, 2018
  • l3riscv

    Forked from jrrk/l3riscv

    An executable specification of the RISCV ISA in L3.

    Ruby 6 Updated Apr 6, 2018
  • Scala 4 3 Updated Jan 21, 2018
  • C 2 Updated Jan 20, 2018
  • SystemVerilog Updated Jan 16, 2018
  • Port of the Yocto Project to the RISC-V ISA

    Python 39 Updated Jan 9, 2018