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Generated html for the lowRISC site. PRs should go to the source repo https://github.com/lowrisc/lowrisc-site
The root repo for lowRISC project and FPGA demos.
Minimised environment for bandwidth limited sites
RISC-V support for LLVM projects (LLVM, Clang, ...)
Untethered (stand-alone) FPGA implementation of the lowRISC SoC
Rocket Chip Generator
RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)
RISC-V Proxy Kernel
FPGA demo for Digilent NEXYS 4 board
RISC-V Linux Port
Port of u-boot to RISCV based ariane core
Local version of qemu for riscv emulation use
Buildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at http://git.buildroot.net/buildroot/. Do not open issues or file pull requests here.
KC705 implementation of the lowRISC unthethered SoC
Fork of OpenOCD that has RISC-V support
Ariane is a 6-stage RISC-V CPU
Collection of IP cores usable to lowRISC SoC
Port of lowrisc to low cost artya7-100 FPGA
Simple single-port AXI memory interface
Contains commonly used UVM components (agents, environments and tests).
An executable specification of the RISCV ISA in L3.
Port of the Yocto Project to the RISC-V ISA