• Scala 9 3 Updated Feb 17, 2017
  • The root repo for lowRISC project and FPGA demos.

    SystemVerilog 91 22 Updated Feb 17, 2017
  • RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)

    Shell 1 72 Updated Feb 17, 2017
  • C 27 Updated Feb 17, 2017
  • C 11 Updated Feb 17, 2017
  • Demonstration of SD card controller using Pulpino and Nexys4-ddr board. Work in progress.

    Verilog 1 Updated Feb 15, 2017
  • Untethered (stand-alone) FPGA implementation of the lowRISC SoC

    C 13 6 Updated Feb 14, 2017
  • FPGA demo for Digilent NEXYS 4 board

    Tcl 2 5 Updated Feb 14, 2017
  • Docker files to generate development environment for multiple releases.

    Shell 1 Updated Feb 14, 2017
  • RISC-V Functional ISA Simulator

    C 67 Updated Feb 14, 2017
  • 4 1 Updated Feb 14, 2017
  • GNU toolchain for RISC-V, including GCC 4.9.2

    C 57 Updated Feb 13, 2017
  • RISC-V Opcodes

    Python 29 Updated Feb 10, 2017
  • RISC-V Proxy Kernel

    C 33 Updated Feb 10, 2017
  • RISC-V Frontend Server

    C++ 34 Updated Feb 10, 2017
  • Generated html for the lowRISC site. PRs should go to the source repo https://github.com/lowrisc/lowrisc-site

    HTML 6 5 Updated Feb 9, 2017
  • CSS 8 Updated Feb 9, 2017
  • Scala 3 2 Updated Feb 6, 2017
  • Collection of IP cores usable to lowRISC SoC

    SystemVerilog 1 4 Updated Jan 25, 2017
  • C 1 Updated Dec 14, 2016
  • A Python script to generate a Gantt chart from a (H)JSON input

    Python 17 1 Updated Oct 15, 2016
  • A Scala library for Context-Dependent Evironments

    Scala 6 Updated Oct 10, 2016
  • RISC-V Linux Port

    C 3 34 Updated Oct 6, 2016
  • glip

    Forked from TUM-LIS/glip

    Generic Logic Interfacing Project

    C 4 Updated Aug 12, 2016
  • A debugging transport based on greth 10/100Mbit and riscv_vhdl

    Verilog 1 Updated Aug 12, 2016
  • Tcl Updated Aug 12, 2016
  • KC705 implementation of the lowRISC unthethered SoC

    C Updated Aug 12, 2016
  • A repo to store all document files other than the website itself.

    Makefile 1 Updated Jul 29, 2016
  • A repository for peripheral components and IO devices associated with the RocketChip project

    Scala 9 Updated Jul 8, 2016
  • Verilog 11 Updated Mar 25, 2016