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The root repo for lowRISC project and FPGA demos.
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bootrom Try to make bootrom more intelligent Nov 16, 2017
csrc add csrc files from rocket-chip [ci skip] Oct 11, 2017
debian-riscv64 @ e7d18e1 Update signing keys and paths to Debian unstable(sid) Jan 4, 2019
fpga @ 19015db Update LICENSE.Cambridge and README.md Oct 22, 2018
jenkins Experiment with larger cache Aug 29, 2018
project initially can generate Verilog using the example configuration [ci skip] Aug 18, 2017
qemu @ 7ae23bc Add new version of qemu Aug 29, 2018
riscv-linux @ c81ff0d Make clear screen functional, detect scrolling direction, clean up an… Oct 5, 2018
rocket-chip @ 84f6ac1 Update riscv-pk for FreeBSD booter compatibility Oct 12, 2018
scripts add scripts from rocket-chip and generate behavioural sram blocks [ci… Oct 5, 2017
src Clean up Vivado warnings, correct palette logic Oct 12, 2018
unitest tag cache unitest finished Jul 6, 2017
vcs Revise hierarchy to keep all chisel code inside rocket-chip Jan 23, 2018
vsim Revise hierarchy to keep all chisel code inside rocket-chip Jan 23, 2018
vsrc Hack for hello world with new AXI ports Jan 18, 2018
.gitignore initially can generate Verilog using the example configuration [ci skip] Aug 18, 2017
.gitmodules
.travis.yml Revise repo list in .travis.yml Jan 23, 2018
CONTRIBUTORS update Alex's email. Apr 12, 2017
Jenkinsfile Relocate jenkins Makefile Aug 15, 2018
LICENSE.Berkeley copy tag related code to tagpipe [ci skip] Jan 27, 2017
LICENSE.Cambridge Update LICENSE.Cambridge and README.md Oct 22, 2018
LICENSE.SiFive check in code from upstream and new Chisel3 compilation flow [ci skip] Aug 15, 2017
LICENSE.jtag check in code from upstream and new Chisel3 compilation flow [ci skip] Aug 15, 2017
Makefrag Adapt for 64-bit I/O bus and newer Rocket release May 31, 2018
Makefrag-build Hack for hello world with new AXI ports Jan 18, 2018
README.md Restructure README.md Nov 15, 2018
sbt-launch.jar update code for untethered code release Nov 18, 2015
set_env.sh use $RISCV in set_env.sh rather than $TOP/riscv Apr 3, 2017

README.md

lowRISC chip

The root git repo for lowRISC development and FPGA demos.

See LICENSE.Cambridge for license details.

See the documentation for build instructions.

master status: master build status

update status: update build status

dev status: dev build status

Current version: Release version 0.6 (10-2018) --- lowRISC technical refresh with RV64GC, Debian+FreeBSD capable

To download the repo:

git clone -b refresh-v0.6 --recursive https://github.com/lowrisc/lowrisc-chip.git

For the previous release:

################
# Version 0.5: lowRISC with 100MHz Ethernet and Network filing system access (01-2018)
################
git clone -b ethernet-v0.5 --recursive https://github.com/lowrisc/lowrisc-chip.git

################
# Version 0.4: lowRISC with with tagged memory and minion core (06-2017)
################
git clone -b minion-v0.4 --recursive https://github.com/lowrisc/lowrisc-chip.git

################
# Version 0.3: lowRISC with a trace debugger (07-2016)
################
git clone -b debug-v0.3 --recursive https://github.com/lowrisc/lowrisc-chip.git

################
# Version 0.2: untethered lowRISC (12-2015)
################
git clone -b untether-v0.2 --recursive https://github.com/lowrisc/lowrisc-chip.git

################
# Version 0.1: tagged memory (04-2015)
################
git clone -b tagged-memory-v0.1 --recursive https://github.com/lowrisc/lowrisc-chip.git

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