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SPI Interface for DepthAI API #140
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We have an initial version running here: https://discuss.luxonis.com/d/56-initial-bw1092-esp32-proof-of-concept-code |
Our first real implementation and example is here: And more background is here: |
And our pull request for joining this into the Gen2 pipeline builder is here: |
The Gen2 implementation of SPI is here: https://github.com/luxonis/esp32-spi-message-demo. As of this writing it includes MobileNetv2-SSD, tiny-YOLOv3, and thumbnail output examples. But a whole slew of other permutations are possible as it is based on the node/graph system of the Gen2 pipeline builder. |
Release v2.4.0
Start with the
why
:In many cases using a micro-controller can be advantages compared to a full-out Linux system:
linux tax
in terms of additional onboard storage needed for Linux)So one advantage of DepthAI is it is such a system... booting over eMMC it can be fully up/running in under 100 milliseconds, and ~400 milliseconds from NOR flash.
So using DepthAI with such micro-controller applications is valuable. And a popular/easy way to interface between microcontrollers is SPI (COPI/CIPO).
Move to the
how
:We have initially implemented a SPI protocol w/ CRC capability for DepthAI to act as a SPI
peripheral
. So then a microcontroller is the SPIcontroller
and can pull data off of DepthAI when it sees fit.At the physical layer (see luxonis/depthai-hardware#10), there will be a GPIO output so that DepthAI can interrupt the microcontroller when new/pertinent data is available. (This pin can also be ignored/not-connected if desired and the microcontroller can simply poll or request data when it wants to.)
Initially we will implement support tensor outputs from the salient neural networks (upon request from the SPI controller), but will expand to allow all the pertinent functionality from #136 to be included, both as input and output.
Move to the
what
:SPI communication support for DepthAI.
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