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The reverse-engineered AY-3-8910 chip. Transistor-level schematics, verilog model and a testbench with tools, that can render register dump files into .flac soundtrack.
Verilog Python Shell
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Latest commit cf8d14d Nov 26, 2019
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pdf First commit Nov 17, 2019
rtl First commit Nov 17, 2019
sch Added links to schematics README Nov 26, 2019
LICENSE Initial commit Nov 17, 2019
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