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usb_halinit.c
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usb_halinit.c
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _HCI_HAL_INIT_C_
#include <osdep_service.h>
#include <drv_types.h>
#include <rtw_efuse.h>
#include <rtl8188e_hal.h>
#include <rtl8188e_led.h>
#include <rtw_iol.h>
#include <usb_ops.h>
#include <usb_hal.h>
#include <usb_osintf.h>
#define HAL_MAC_ENABLE 1
#define HAL_BB_ENABLE 1
#define HAL_RF_ENABLE 1
static void _ConfigNormalChipOutEP_8188E(struct adapter *adapt, u8 NumOutPipe)
{
struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
switch (NumOutPipe) {
case 3:
haldata->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ;
haldata->OutEpNumber = 3;
break;
case 2:
haldata->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ;
haldata->OutEpNumber = 2;
break;
case 1:
haldata->OutEpQueueSel = TX_SELE_HQ;
haldata->OutEpNumber = 1;
break;
default:
break;
}
DBG_88E("%s OutEpQueueSel(0x%02x), OutEpNumber(%d)\n", __func__, haldata->OutEpQueueSel, haldata->OutEpNumber);
}
static bool HalUsbSetQueuePipeMapping8188EUsb(struct adapter *adapt, u8 NumInPipe, u8 NumOutPipe)
{
struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
bool result = false;
_ConfigNormalChipOutEP_8188E(adapt, NumOutPipe);
/* Normal chip with one IN and one OUT doesn't have interrupt IN EP. */
if (1 == haldata->OutEpNumber) {
if (1 != NumInPipe)
return result;
}
/* All config other than above support one Bulk IN and one Interrupt IN. */
result = Hal_MappingOutPipe(adapt, NumOutPipe);
return result;
}
static void rtl8188eu_interface_configure(struct adapter *adapt)
{
struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapt);
if (pdvobjpriv->ishighspeed)
haldata->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;/* 512 bytes */
else
haldata->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;/* 64 bytes */
haldata->interfaceIndex = pdvobjpriv->InterfaceNumber;
haldata->UsbTxAggMode = 1;
haldata->UsbTxAggDescNum = 0x6; /* only 4 bits */
haldata->UsbRxAggMode = USB_RX_AGG_DMA;/* USB_RX_AGG_DMA; */
haldata->UsbRxAggBlockCount = 8; /* unit : 512b */
haldata->UsbRxAggBlockTimeout = 0x6;
haldata->UsbRxAggPageCount = 48; /* uint :128 b 0x0A; 10 = MAX_RX_DMA_BUFFER_SIZE/2/haldata->UsbBulkOutSize */
haldata->UsbRxAggPageTimeout = 0x4; /* 6, absolute time = 34ms/(2^6) */
HalUsbSetQueuePipeMapping8188EUsb(adapt,
pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes);
}
static u32 rtl8188eu_InitPowerOn(struct adapter *adapt)
{
u16 value16;
/* HW Power on sequence */
struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
if (haldata->bMacPwrCtrlOn)
return _SUCCESS;
if (!HalPwrSeqCmdParsing(adapt, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_PWR_ON_FLOW)) {
DBG_88E(KERN_ERR "%s: run power on flow fail\n", __func__);
return _FAIL;
}
/* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
/* Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. */
rtw_write16(adapt, REG_CR, 0x00); /* suggseted by zhouzhou, by page, 20111230 */
/* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
value16 = rtw_read16(adapt, REG_CR);
value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
| PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
/* for SDIO - Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. */
rtw_write16(adapt, REG_CR, value16);
haldata->bMacPwrCtrlOn = true;
return _SUCCESS;
}
/* Shall USB interface init this? */
static void _InitInterrupt(struct adapter *Adapter)
{
u32 imr, imr_ex;
u8 usb_opt;
struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
/* HISR write one to clear */
rtw_write32(Adapter, REG_HISR_88E, 0xFFFFFFFF);
/* HIMR - */
imr = IMR_PSTIMEOUT_88E | IMR_TBDER_88E | IMR_CPWM_88E | IMR_CPWM2_88E;
rtw_write32(Adapter, REG_HIMR_88E, imr);
haldata->IntrMask[0] = imr;
imr_ex = IMR_TXERR_88E | IMR_RXERR_88E | IMR_TXFOVW_88E | IMR_RXFOVW_88E;
rtw_write32(Adapter, REG_HIMRE_88E, imr_ex);
haldata->IntrMask[1] = imr_ex;
/* REG_USB_SPECIAL_OPTION - BIT(4) */
/* 0; Use interrupt endpoint to upload interrupt pkt */
/* 1; Use bulk endpoint to upload interrupt pkt, */
usb_opt = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION);
if (!adapter_to_dvobj(Adapter)->ishighspeed)
usb_opt = usb_opt & (~INT_BULK_SEL);
else
usb_opt = usb_opt | (INT_BULK_SEL);
rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, usb_opt);
}
static void _InitQueueReservedPage(struct adapter *Adapter)
{
struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
struct registry_priv *pregistrypriv = &Adapter->registrypriv;
u32 numHQ = 0;
u32 numLQ = 0;
u32 numNQ = 0;
u32 numPubQ;
u32 value32;
u8 value8;
bool bWiFiConfig = pregistrypriv->wifi_spec;
if (bWiFiConfig) {
if (haldata->OutEpQueueSel & TX_SELE_HQ)
numHQ = 0x29;
if (haldata->OutEpQueueSel & TX_SELE_LQ)
numLQ = 0x1C;
/* NOTE: This step shall be proceed before writting REG_RQPN. */
if (haldata->OutEpQueueSel & TX_SELE_NQ)
numNQ = 0x1C;
value8 = (u8)_NPQ(numNQ);
rtw_write8(Adapter, REG_RQPN_NPQ, value8);
numPubQ = 0xA8 - numHQ - numLQ - numNQ;
/* TX DMA */
value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
rtw_write32(Adapter, REG_RQPN, value32);
} else {
rtw_write16(Adapter, REG_RQPN_NPQ, 0x0000);/* Just follow MP Team,??? Georgia 03/28 */
rtw_write16(Adapter, REG_RQPN_NPQ, 0x0d);
rtw_write32(Adapter, REG_RQPN, 0x808E000d);/* reserve 7 page for LPS */
}
}
static void _InitTxBufferBoundary(struct adapter *Adapter, u8 txpktbuf_bndy)
{
rtw_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
rtw_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
rtw_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
rtw_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
rtw_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy);
}
static void _InitPageBoundary(struct adapter *Adapter)
{
/* RX Page Boundary */
/* */
u16 rxff_bndy = MAX_RX_DMA_BUFFER_SIZE_88E-1;
rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
}
static void _InitNormalChipRegPriority(struct adapter *Adapter, u16 beQ,
u16 bkQ, u16 viQ, u16 voQ, u16 mgtQ,
u16 hiQ)
{
u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
_TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
_TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
}
static void _InitNormalChipOneOutEpPriority(struct adapter *Adapter)
{
struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
u16 value = 0;
switch (haldata->OutEpQueueSel) {
case TX_SELE_HQ:
value = QUEUE_HIGH;
break;
case TX_SELE_LQ:
value = QUEUE_LOW;
break;
case TX_SELE_NQ:
value = QUEUE_NORMAL;
break;
default:
break;
}
_InitNormalChipRegPriority(Adapter, value, value, value, value,
value, value);
}
static void _InitNormalChipTwoOutEpPriority(struct adapter *Adapter)
{
struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
struct registry_priv *pregistrypriv = &Adapter->registrypriv;
u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
u16 valueHi = 0;
u16 valueLow = 0;
switch (haldata->OutEpQueueSel) {
case (TX_SELE_HQ | TX_SELE_LQ):
valueHi = QUEUE_HIGH;
valueLow = QUEUE_LOW;
break;
case (TX_SELE_NQ | TX_SELE_LQ):
valueHi = QUEUE_NORMAL;
valueLow = QUEUE_LOW;
break;
case (TX_SELE_HQ | TX_SELE_NQ):
valueHi = QUEUE_HIGH;
valueLow = QUEUE_NORMAL;
break;
default:
break;
}
if (!pregistrypriv->wifi_spec) {
beQ = valueLow;
bkQ = valueLow;
viQ = valueHi;
voQ = valueHi;
mgtQ = valueHi;
hiQ = valueHi;
} else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
beQ = valueLow;
bkQ = valueHi;
viQ = valueHi;
voQ = valueLow;
mgtQ = valueHi;
hiQ = valueHi;
}
_InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
}
static void _InitNormalChipThreeOutEpPriority(struct adapter *Adapter)
{
struct registry_priv *pregistrypriv = &Adapter->registrypriv;
u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
if (!pregistrypriv->wifi_spec) {/* typical setting */
beQ = QUEUE_LOW;
bkQ = QUEUE_LOW;
viQ = QUEUE_NORMAL;
voQ = QUEUE_HIGH;
mgtQ = QUEUE_HIGH;
hiQ = QUEUE_HIGH;
} else {/* for WMM */
beQ = QUEUE_LOW;
bkQ = QUEUE_NORMAL;
viQ = QUEUE_NORMAL;
voQ = QUEUE_HIGH;
mgtQ = QUEUE_HIGH;
hiQ = QUEUE_HIGH;
}
_InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
}
static void _InitQueuePriority(struct adapter *Adapter)
{
struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
switch (haldata->OutEpNumber) {
case 1:
_InitNormalChipOneOutEpPriority(Adapter);
break;
case 2:
_InitNormalChipTwoOutEpPriority(Adapter);
break;
case 3:
_InitNormalChipThreeOutEpPriority(Adapter);
break;
default:
break;
}
}
static void _InitNetworkType(struct adapter *Adapter)
{
u32 value32;
value32 = rtw_read32(Adapter, REG_CR);
/* TODO: use the other function to set network type */
value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
rtw_write32(Adapter, REG_CR, value32);
}
static void _InitTransferPageSize(struct adapter *Adapter)
{
/* Tx page size is always 128. */
u8 value8;
value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
rtw_write8(Adapter, REG_PBP, value8);
}
static void _InitDriverInfoSize(struct adapter *Adapter, u8 drvInfoSize)
{
rtw_write8(Adapter, REG_RX_DRVINFO_SZ, drvInfoSize);
}
static void _InitWMACSetting(struct adapter *Adapter)
{
struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
haldata->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AB |
RCR_CBSSID_DATA | RCR_CBSSID_BCN |
RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
RCR_APP_MIC | RCR_APP_PHYSTS;
/* some REG_RCR will be modified later by phy_ConfigMACWithHeaderFile() */
rtw_write32(Adapter, REG_RCR, haldata->ReceiveConfig);
/* Accept all multicast address */
rtw_write32(Adapter, REG_MAR, 0xFFFFFFFF);
rtw_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
}
static void _InitAdaptiveCtrl(struct adapter *Adapter)
{
u16 value16;
u32 value32;
/* Response Rate Set */
value32 = rtw_read32(Adapter, REG_RRSR);
value32 &= ~RATE_BITMAP_ALL;
value32 |= RATE_RRSR_CCK_ONLY_1M;
rtw_write32(Adapter, REG_RRSR, value32);
/* CF-END Threshold */
/* SIFS (used in NAV) */
value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
rtw_write16(Adapter, REG_SPEC_SIFS, value16);
/* Retry Limit */
value16 = _LRL(0x30) | _SRL(0x30);
rtw_write16(Adapter, REG_RL, value16);
}
static void _InitEDCA(struct adapter *Adapter)
{
/* Set Spec SIFS (used in NAV) */
rtw_write16(Adapter, REG_SPEC_SIFS, 0x100a);
rtw_write16(Adapter, REG_MAC_SPEC_SIFS, 0x100a);
/* Set SIFS for CCK */
rtw_write16(Adapter, REG_SIFS_CTX, 0x100a);
/* Set SIFS for OFDM */
rtw_write16(Adapter, REG_SIFS_TRX, 0x100a);
/* TXOP */
rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
}
static void _InitBeaconMaxError(struct adapter *Adapter, bool InfraMode)
{
}
static void _InitHWLed(struct adapter *Adapter)
{
struct led_priv *pledpriv = &(Adapter->ledpriv);
if (pledpriv->LedStrategy != HW_LED)
return;
/* HW led control */
/* to do .... */
/* must consider cases of antenna diversity/ commbo card/solo card/mini card */
}
static void _InitRDGSetting(struct adapter *Adapter)
{
rtw_write8(Adapter, REG_RD_CTRL, 0xFF);
rtw_write16(Adapter, REG_RD_NAV_NXT, 0x200);
rtw_write8(Adapter, REG_RD_RESP_PKT_TH, 0x05);
}
static void _InitRxSetting(struct adapter *Adapter)
{
rtw_write32(Adapter, REG_MACID, 0x87654321);
rtw_write32(Adapter, 0x0700, 0x87654321);
}
static void _InitRetryFunction(struct adapter *Adapter)
{
u8 value8;
value8 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL);
value8 |= EN_AMPDU_RTY_NEW;
rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
/* Set ACK timeout */
rtw_write8(Adapter, REG_ACKTO, 0x40);
}
/*-----------------------------------------------------------------------------
* Function: usb_AggSettingTxUpdate()
*
* Overview: Separate TX/RX parameters update independent for TP detection and
* dynamic TX/RX aggreagtion parameters update.
*
* Input: struct adapter *
*
* Output/Return: NONE
*
* Revised History:
* When Who Remark
* 12/10/2010 MHC Separate to smaller function.
*
*---------------------------------------------------------------------------*/
static void usb_AggSettingTxUpdate(struct adapter *Adapter)
{
struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
u32 value32;
if (Adapter->registrypriv.wifi_spec)
haldata->UsbTxAggMode = false;
if (haldata->UsbTxAggMode) {
value32 = rtw_read32(Adapter, REG_TDECTRL);
value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT);
value32 |= ((haldata->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT);
rtw_write32(Adapter, REG_TDECTRL, value32);
}
} /* usb_AggSettingTxUpdate */
/*-----------------------------------------------------------------------------
* Function: usb_AggSettingRxUpdate()
*
* Overview: Separate TX/RX parameters update independent for TP detection and
* dynamic TX/RX aggreagtion parameters update.
*
* Input: struct adapter *
*
* Output/Return: NONE
*
* Revised History:
* When Who Remark
* 12/10/2010 MHC Separate to smaller function.
*
*---------------------------------------------------------------------------*/
static void
usb_AggSettingRxUpdate(
struct adapter *Adapter
)
{
struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
u8 valueDMA;
u8 valueUSB;
valueDMA = rtw_read8(Adapter, REG_TRXDMA_CTRL);
valueUSB = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION);
switch (haldata->UsbRxAggMode) {
case USB_RX_AGG_DMA:
valueDMA |= RXDMA_AGG_EN;
valueUSB &= ~USB_AGG_EN;
break;
case USB_RX_AGG_USB:
valueDMA &= ~RXDMA_AGG_EN;
valueUSB |= USB_AGG_EN;
break;
case USB_RX_AGG_MIX:
valueDMA |= RXDMA_AGG_EN;
valueUSB |= USB_AGG_EN;
break;
case USB_RX_AGG_DISABLE:
default:
valueDMA &= ~RXDMA_AGG_EN;
valueUSB &= ~USB_AGG_EN;
break;
}
rtw_write8(Adapter, REG_TRXDMA_CTRL, valueDMA);
rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, valueUSB);
switch (haldata->UsbRxAggMode) {
case USB_RX_AGG_DMA:
rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, haldata->UsbRxAggPageCount);
rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, haldata->UsbRxAggPageTimeout);
break;
case USB_RX_AGG_USB:
rtw_write8(Adapter, REG_USB_AGG_TH, haldata->UsbRxAggBlockCount);
rtw_write8(Adapter, REG_USB_AGG_TO, haldata->UsbRxAggBlockTimeout);
break;
case USB_RX_AGG_MIX:
rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, haldata->UsbRxAggPageCount);
rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, (haldata->UsbRxAggPageTimeout & 0x1F));/* 0x280[12:8] */
rtw_write8(Adapter, REG_USB_AGG_TH, haldata->UsbRxAggBlockCount);
rtw_write8(Adapter, REG_USB_AGG_TO, haldata->UsbRxAggBlockTimeout);
break;
case USB_RX_AGG_DISABLE:
default:
/* TODO: */
break;
}
switch (PBP_128) {
case PBP_128:
haldata->HwRxPageSize = 128;
break;
case PBP_64:
haldata->HwRxPageSize = 64;
break;
case PBP_256:
haldata->HwRxPageSize = 256;
break;
case PBP_512:
haldata->HwRxPageSize = 512;
break;
case PBP_1024:
haldata->HwRxPageSize = 1024;
break;
default:
break;
}
} /* usb_AggSettingRxUpdate */
static void InitUsbAggregationSetting(struct adapter *Adapter)
{
struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
/* Tx aggregation setting */
usb_AggSettingTxUpdate(Adapter);
/* Rx aggregation setting */
usb_AggSettingRxUpdate(Adapter);
/* 201/12/10 MH Add for USB agg mode dynamic switch. */
haldata->UsbRxHighSpeedMode = false;
}
static void _InitOperationMode(struct adapter *Adapter)
{
}
static void _InitBeaconParameters(struct adapter *Adapter)
{
struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
rtw_write16(Adapter, REG_BCN_CTRL, 0x1010);
/* TODO: Remove these magic number */
rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0x6404);/* ms */
rtw_write8(Adapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);/* 5ms */
rtw_write8(Adapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME); /* 2ms */
/* Suggested by designer timchen. Change beacon AIFS to the largest number */
/* beacause test chip does not contension before sending beacon. by tynli. 2009.11.03 */
rtw_write16(Adapter, REG_BCNTCFG, 0x660F);
haldata->RegBcnCtrlVal = rtw_read8(Adapter, REG_BCN_CTRL);
haldata->RegTxPause = rtw_read8(Adapter, REG_TXPAUSE);
haldata->RegFwHwTxQCtrl = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL+2);
haldata->RegReg542 = rtw_read8(Adapter, REG_TBTT_PROHIBIT+2);
haldata->RegCR_1 = rtw_read8(Adapter, REG_CR+1);
}
static void _BeaconFunctionEnable(struct adapter *Adapter,
bool Enable, bool Linked)
{
rtw_write8(Adapter, REG_BCN_CTRL, (BIT4 | BIT3 | BIT1));
rtw_write8(Adapter, REG_RD_CTRL+1, 0x6F);
}
/* Set CCK and OFDM Block "ON" */
static void _BBTurnOnBlock(struct adapter *Adapter)
{
PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
}
enum {
Antenna_Lfet = 1,
Antenna_Right = 2,
};
static void _InitAntenna_Selection(struct adapter *Adapter)
{
struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
if (haldata->AntDivCfg == 0)
return;
DBG_88E("==> %s ....\n", __func__);
rtw_write32(Adapter, REG_LEDCFG0, rtw_read32(Adapter, REG_LEDCFG0)|BIT23);
PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
if (PHY_QueryBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == Antenna_A)
haldata->CurAntenna = Antenna_A;
else
haldata->CurAntenna = Antenna_B;
DBG_88E("%s,Cur_ant:(%x)%s\n", __func__, haldata->CurAntenna, (haldata->CurAntenna == Antenna_A) ? "Antenna_A" : "Antenna_B");
}
/*-----------------------------------------------------------------------------
* Function: HwSuspendModeEnable92Cu()
*
* Overview: HW suspend mode switch.
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 08/23/2010 MHC HW suspend mode switch test..
*---------------------------------------------------------------------------*/
enum rt_rf_power_state RfOnOffDetect(struct adapter *adapt)
{
u8 val8;
enum rt_rf_power_state rfpowerstate = rf_off;
if (adapt->pwrctrlpriv.bHWPowerdown) {
val8 = rtw_read8(adapt, REG_HSISR);
DBG_88E("pwrdown, 0x5c(BIT7)=%02x\n", val8);
rfpowerstate = (val8 & BIT7) ? rf_off : rf_on;
} else { /* rf on/off */
rtw_write8(adapt, REG_MAC_PINMUX_CFG, rtw_read8(adapt, REG_MAC_PINMUX_CFG)&~(BIT3));
val8 = rtw_read8(adapt, REG_GPIO_IO_SEL);
DBG_88E("GPIO_IN=%02x\n", val8);
rfpowerstate = (val8 & BIT3) ? rf_on : rf_off;
}
return rfpowerstate;
} /* HalDetectPwrDownMode */
static u32 rtl8188eu_hal_init(struct adapter *Adapter)
{
u8 value8 = 0;
u16 value16;
u8 txpktbuf_bndy;
u32 status = _SUCCESS;
struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv;
struct registry_priv *pregistrypriv = &Adapter->registrypriv;
u32 init_start_time = jiffies;
#define HAL_INIT_PROFILE_TAG(stage) do {} while (0)
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
if (Adapter->pwrctrlpriv.bkeepfwalive) {
_ps_open_RF(Adapter);
if (haldata->odmpriv.RFCalibrateInfo.bIQKInitialized) {
PHY_IQCalibrate_8188E(Adapter, true);
} else {
PHY_IQCalibrate_8188E(Adapter, false);
haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
}
ODM_TXPowerTrackingCheck(&haldata->odmpriv);
PHY_LCCalibrate_8188E(Adapter);
goto exit;
}
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
status = rtl8188eu_InitPowerOn(Adapter);
if (status == _FAIL) {
RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init power on!\n"));
goto exit;
}
/* Save target channel */
haldata->CurrentChannel = 6;/* default set to 6 */
if (pwrctrlpriv->reg_rfoff) {
pwrctrlpriv->rf_pwrstate = rf_off;
}
/* 2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
/* HW GPIO pin. Before PHY_RFConfig8192C. */
/* 2010/08/26 MH If Efuse does not support sective suspend then disable the function. */
if (!pregistrypriv->wifi_spec) {
txpktbuf_bndy = TX_PAGE_BOUNDARY_88E;
} else {
/* for WMM */
txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_88E;
}
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
_InitQueueReservedPage(Adapter);
_InitQueuePriority(Adapter);
_InitPageBoundary(Adapter);
_InitTransferPageSize(Adapter);
_InitTxBufferBoundary(Adapter, 0);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
if (Adapter->registrypriv.mp_mode == 1) {
_InitRxSetting(Adapter);
Adapter->bFWReady = false;
haldata->fw_ractrl = false;
} else {
status = rtl8188e_FirmwareDownload(Adapter);
if (status != _SUCCESS) {
DBG_88E("%s: Download Firmware failed!!\n", __func__);
Adapter->bFWReady = false;
haldata->fw_ractrl = false;
return status;
} else {
RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializeadapt8192CSdio(): Download Firmware Success!!\n"));
Adapter->bFWReady = true;
haldata->fw_ractrl = false;
}
}
rtl8188e_InitializeFirmwareVars(Adapter);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
#if (HAL_MAC_ENABLE == 1)
status = PHY_MACConfig8188E(Adapter);
if (status == _FAIL) {
DBG_88E(" ### Failed to init MAC ......\n ");
goto exit;
}
#endif
/* */
/* d. Initialize BB related configurations. */
/* */
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
#if (HAL_BB_ENABLE == 1)
status = PHY_BBConfig8188E(Adapter);
if (status == _FAIL) {
DBG_88E(" ### Failed to init BB ......\n ");
goto exit;
}
#endif
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
#if (HAL_RF_ENABLE == 1)
status = PHY_RFConfig8188E(Adapter);
if (status == _FAIL) {
DBG_88E(" ### Failed to init RF ......\n ");
goto exit;
}
#endif
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_EFUSE_PATCH);
status = rtl8188e_iol_efuse_patch(Adapter);
if (status == _FAIL) {
DBG_88E("%s rtl8188e_iol_efuse_patch failed\n", __func__);
goto exit;
}
_InitTxBufferBoundary(Adapter, txpktbuf_bndy);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
status = InitLLTTable(Adapter, txpktbuf_bndy);
if (status == _FAIL) {
RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT table\n"));
goto exit;
}
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
/* Get Rx PHY status in order to report RSSI and others. */
_InitDriverInfoSize(Adapter, DRVINFO_SZ);
_InitInterrupt(Adapter);
hal_init_macaddr(Adapter);/* set mac_address */
_InitNetworkType(Adapter);/* set msr */
_InitWMACSetting(Adapter);
_InitAdaptiveCtrl(Adapter);
_InitEDCA(Adapter);
_InitRetryFunction(Adapter);
InitUsbAggregationSetting(Adapter);
_InitOperationMode(Adapter);/* todo */
_InitBeaconParameters(Adapter);
_InitBeaconMaxError(Adapter, true);
/* */
/* Init CR MACTXEN, MACRXEN after setting RxFF boundary REG_TRXFF_BNDY to patch */
/* Hw bug which Hw initials RxFF boundary size to a value which is larger than the real Rx buffer size in 88E. */
/* */
/* Enable MACTXEN/MACRXEN block */
value16 = rtw_read16(Adapter, REG_CR);
value16 |= (MACTXEN | MACRXEN);
rtw_write8(Adapter, REG_CR, value16);
if (haldata->bRDGEnable)
_InitRDGSetting(Adapter);
/* Enable TX Report */
/* Enable Tx Report Timer */
value8 = rtw_read8(Adapter, REG_TX_RPT_CTRL);
rtw_write8(Adapter, REG_TX_RPT_CTRL, (value8|BIT1|BIT0));
/* Set MAX RPT MACID */
rtw_write8(Adapter, REG_TX_RPT_CTRL+1, 2);/* FOR sta mode ,0: bc/mc ,1:AP */
/* Tx RPT Timer. Unit: 32us */
rtw_write16(Adapter, REG_TX_RPT_TIME, 0xCdf0);
rtw_write8(Adapter, REG_EARLY_MODE_CONTROL, 0);
rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
_InitHWLed(Adapter);
/* Keep RfRegChnlVal for later use. */
haldata->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (enum rf_radio_path)0, RF_CHNLBW, bRFRegOffsetMask);
haldata->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (enum rf_radio_path)1, RF_CHNLBW, bRFRegOffsetMask);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
_BBTurnOnBlock(Adapter);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
invalidate_cam_all(Adapter);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
/* 2010/12/17 MH We need to set TX power according to EFUSE content at first. */
PHY_SetTxPowerLevel8188E(Adapter, haldata->CurrentChannel);
/* Move by Neo for USB SS to below setp */
/* _RfPowerSave(Adapter); */
_InitAntenna_Selection(Adapter);
/* */
/* Disable BAR, suggested by Scott */
/* 2010.04.09 add by hpfan */
/* */
rtw_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
/* HW SEQ CTRL */
/* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
rtw_write8(Adapter, REG_HWSEQ_CTRL, 0xFF);
if (pregistrypriv->wifi_spec)
rtw_write16(Adapter, REG_FAST_EDCA_CTRL, 0);
/* Nav limit , suggest by scott */
rtw_write8(Adapter, 0x652, 0x0);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
rtl8188e_InitHalDm(Adapter);
if (Adapter->registrypriv.mp_mode == 1) {
Adapter->mppriv.channel = haldata->CurrentChannel;
MPT_InitializeAdapter(Adapter, Adapter->mppriv.channel);
} else {
/* 2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status */
/* and then decide to enable RF or not.!!!??? For Selective suspend mode. We may not */
/* call initstruct adapter. May cause some problem?? */
/* Fix the bug that Hw/Sw radio off before S3/S4, the RF off action will not be executed */
/* in MgntActSet_RF_State() after wake up, because the value of haldata->eRFPowerState */
/* is the same as eRfOff, we should change it to eRfOn after we config RF parameters. */
/* Added by tynli. 2010.03.30. */
pwrctrlpriv->rf_pwrstate = rf_on;
/* enable Tx report. */
rtw_write8(Adapter, REG_FWHW_TXQ_CTRL+1, 0x0F);
/* Suggested by SD1 pisa. Added by tynli. 2011.10.21. */
rtw_write8(Adapter, REG_EARLY_MODE_CONTROL+3, 0x01);/* Pretx_en, for WEP/TKIP SEC */
/* tynli_test_tx_report. */
rtw_write16(Adapter, REG_TX_RPT_TIME, 0x3DF0);
/* enable tx DMA to drop the redundate data of packet */
rtw_write16(Adapter, REG_TXDMA_OFFSET_CHK, (rtw_read16(Adapter, REG_TXDMA_OFFSET_CHK) | DROP_DATA_EN));
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK);
/* 2010/08/26 MH Merge from 8192CE. */
if (pwrctrlpriv->rf_pwrstate == rf_on) {
if (haldata->odmpriv.RFCalibrateInfo.bIQKInitialized) {
PHY_IQCalibrate_8188E(Adapter, true);
} else {
PHY_IQCalibrate_8188E(Adapter, false);
haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
}
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK);
ODM_TXPowerTrackingCheck(&haldata->odmpriv);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
PHY_LCCalibrate_8188E(Adapter);
}
}
/* HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS); */
/* _InitPABias(Adapter); */
rtw_write8(Adapter, REG_USB_HRPWM, 0);
/* ack for xmit mgmt frames. */
rtw_write32(Adapter, REG_FWHW_TXQ_CTRL, rtw_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12));
exit:
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
DBG_88E("%s in %dms\n", __func__, rtw_get_passing_time_ms(init_start_time));
return status;
}
void _ps_open_RF(struct adapter *adapt)
{
/* here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified */
/* phy_SsPwrSwitch92CU(adapt, rf_on, 1); */
}
static void _ps_close_RF(struct adapter *adapt)
{
/* here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified */
/* phy_SsPwrSwitch92CU(adapt, rf_off, 1); */
}
static void CardDisableRTL8188EU(struct adapter *Adapter)
{
u8 val8;
struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("CardDisableRTL8188EU\n"));
/* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */
val8 = rtw_read8(Adapter, REG_TX_RPT_CTRL);
rtw_write8(Adapter, REG_TX_RPT_CTRL, val8&(~BIT1));
/* stop rx */
rtw_write8(Adapter, REG_CR, 0x0);
/* Run LPS WL RFOFF flow */
HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_LPS_ENTER_FLOW);
/* 2. 0x1F[7:0] = 0 turn off RF */