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pll + por

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lynxis committed Oct 29, 2017
1 parent 42c939f commit 9aab1b3c46e411c6b1eb0cfeb6f641b582a9b786
Showing with 28 additions and 13 deletions.
  1. +1 −1 Makefile
  2. +7 −3 lpc.v
  3. +5 −2 power_on_reset.v
  4. +15 −7 top.v
@@ -1,6 +1,6 @@

NAME=top
DEPS=buffer.v bufferdomain.v lpc.v mem2serial.v ringbuffer.v uart_tx.v power_on_reset.v trigger_led.v
DEPS=buffer.v bufferdomain.v lpc.v mem2serial.v ringbuffer.v uart_tx.v power_on_reset.v trigger_led.v pll.v

$(NAME).bin: $(NAME).pcf $(NAME).v $(DEPS)
yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v $(DEPS)
10 lpc.v
@@ -76,6 +76,7 @@ module lpc(
idle: begin end

cycle_dir: begin
out_clock_enable <= 0;
if (lpc_ad[3:2] == 2'b00) begin /* i/o */
state <= address;
counter <= 4;
@@ -100,16 +101,20 @@ module lpc(

tar: state <= sync;

sync:
sync: begin
if (lpc_ad == 4'b0000)
if (cyctype_dir[3] == 0) begin /* i/o or memory */
state <= read_data;
data <= 0;
counter <= 2;
end else
state <= idle; /* unsupported dma or reserved */
end

read_data: state <= idle;
read_data: begin
out_clock_enable <= 1;
state <= idle;
end

/* todo: missing TAR after read_data */

@@ -123,5 +128,4 @@ module lpc(
assign out_cyctype_dir = cyctype_dir;
assign out_data = data;
assign out_addr = addr;
assign out_clock_enable = reset && state == read_data && counter == 0;
endmodule
@@ -1,4 +1,7 @@
module power_on_reset(input clock, output reg reset);
module power_on_reset(
input pll_locked,
input clock,
output reg reset);

reg [31:0] counter = 32'h2;

@@ -10,7 +13,7 @@ always @(*) begin
end

always @(negedge clock) begin
if (counter != 0)
if (counter != 0 && pll_locked)
counter <= counter - 1;
end

22 top.v
@@ -1,4 +1,4 @@
module top #(parameter CLOCK_FREQ = 12_000_000, parameter BAUD_RATE = 921600)
module top #(parameter CLOCK_FREQ = 33_000_000, parameter BAUD_RATE = 921600)
(
input [3:0] lpc_ad,
input lpc_clock,
@@ -46,8 +46,16 @@ module top #(parameter CLOCK_FREQ = 12_000_000, parameter BAUD_RATE = 921600)
wire trigger_port;
wire no_lpc_reset;

wire main_clock;
wire pll_locked;

pll PLL(.clock_in(ext_clock),
.clock_out(main_clock),
.locked(pll_locked));

power_on_reset POR(
.clock(ext_clock),
.pll_locked(pll_locked),
.clock(main_clock),
.reset(reset));

lpc LPC(
@@ -66,7 +74,7 @@ module top #(parameter CLOCK_FREQ = 12_000_000, parameter BAUD_RATE = 921600)
.input_data(lpc_data),
.input_enable(lpc_data_enable),
.reset(reset),
.clock(ext_clock),
.clock(main_clock),
.output_data(write_data),
.output_enable(write_clock_enable));

@@ -78,7 +86,7 @@ module top #(parameter CLOCK_FREQ = 12_000_000, parameter BAUD_RATE = 921600)
ringbuffer #(.AW(10), .DW(48))
RINGBUFFER (
.reset(reset),
.clock(ext_clock),
.clock(main_clock),
.write_clock_enable(write_clock_enable),
.read_clock_enable(read_clock_enable),
.read_data(read_data),
@@ -88,7 +96,7 @@ module top #(parameter CLOCK_FREQ = 12_000_000, parameter BAUD_RATE = 921600)

mem2serial MEM_SERIAL(
.reset(reset),
.clock(ext_clock),
.clock(main_clock),
.read_empty(empty),
.read_clock_enable(read_clock_enable),
.read_data(read_data),
@@ -103,12 +111,12 @@ module top #(parameter CLOCK_FREQ = 12_000_000, parameter BAUD_RATE = 921600)
.reset(reset),
.ready(uart_ready),
.tx(uart_tx_pin),
.clock(ext_clock),
.clock(main_clock),
.uart_clock(uart_clock));

trigger_led TRIGGERLPC(
.reset(reset),
.clock(ext_clock),
.clock(main_clock),
.led(valid_lpc_output_led),
.trigger(trigger_port));

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