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this commit is to free warnings as:

http://downloads.qi-hardware.com/people/adam/m1/tmp/kicad/20120424_3494_6-warnings.png

reasons/steps on editing:
Used a KiCad Version: (2012-04-08 BZR 3494)-testing Application: Eeschema

Build: wxWidgets 2.8.10 (no debug,Unicode,compiler with C++ ABI 1002,GCC 4.4.3,wx containers,compatible with 2.6)
Platform: Linux 2.6.32-40-generic i686, 32 bit, Little endian, wxGTK
Options:          KICAD_GOST=OFF
         USE_WX_GRAPHICS_CONTEXT=OFF
         USE_WX_OVERLAY=OFF
         USE_BOOST_POLYGON_LIBRARY

1. Previous last history about splitted manually[scaled down] FPGA.sch(A2) into two A3 of FPGA_P1.sch, and FPGA_P2.sch;
   But there DRAM_A[12..0] bus and DRAM_DQ[31..0] bus are too long, so after dragged those blocks, saved, do DRC,
   a 6-warnings unconnected.

2. If you have ever dragged a 'block' contains bus entry, bus, wires, global lable AFTER DRC without any Err.
   then will get 6 warnings as above.

3. then removed all those blocks, and edited them in eeschema again. Do DRC then get 0 Err.
3. Possible reason: from A2 to A3, the coordinate axis are changed and not meet A3 scale, or others. Don't know the real root cause.
  • Loading branch information...
commit 5c3e30e756c2cb9c962a60c1efa66a7d7bf3f499 1 parent b0e64e7
@adamwang adamwang authored
Showing with 17 additions and 17 deletions.
  1. +17 −17 r4/FPGA_P1.sch
View
34 r4/FPGA_P1.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2 date 2012年04月24日 (週二) 17時12分31秒
+EESchema Schematic File Version 2 date 2012年04月24日 (週二) 19時01分55秒
LIBS:js28f256j3f105
LIBS:8_10-card
LIBS:74x1g00_5
@@ -64,10 +64,6 @@ Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
-Text Label 7500 750 0 60 ~ 0
-SDRAM_A[12..0]
-Text Label 13600 4500 0 60 ~ 0
-SDRAM_DQ[31..0]
Text Notes 13800 9750 2 60 ~ 0
H/W Control: R4 Version
Text Label 12700 8550 0 60 ~ 0
@@ -165,8 +161,6 @@ Entry Wire Line
7250 3250 7350 3350
Entry Wire Line
7250 3150 7350 3250
-Text GLabel 8350 750 2 60 Output ~ 0
-SDRAM_A[12..0]
Entry Wire Line
7400 2950 7500 3050
Entry Wire Line
@@ -259,8 +253,6 @@ Text GLabel 8000 1150 0 50 Output ~ 0
SDRAM_BA0
Text Label 8100 1050 0 60 ~ 0
FPGA_VREF
-Text GLabel 14450 4500 2 60 BiDi ~ 0
-SDRAM_DQ[31..0]
Entry Wire Line
13400 1250 13500 1350
Entry Wire Line
@@ -716,6 +708,10 @@ F 1 "XC6SLX45-2FGG484C" H 10350 3800 60 0000 C CNN
4 10350 3750
1 0 0 -1
$EndComp
+Text GLabel 8550 800 2 60 Output ~ 0
+SDRAM_A[12..0]
+Text Label 7550 800 0 60 ~ 0
+SDRAM_A[12..0]
Wire Wire Line
13400 9350 12700 9350
Wire Wire Line
@@ -741,10 +737,6 @@ Wire Bus Line
Wire Wire Line
8750 2450 8100 2450
Wire Bus Line
- 8350 750 7400 750
-Wire Bus Line
- 7400 750 7400 3050
-Wire Bus Line
8950 7550 8950 8300
Wire Bus Line
2750 8550 2750 9350
@@ -1256,10 +1248,6 @@ Wire Wire Line
12700 1150 11950 1150
Wire Wire Line
13400 1250 11950 1250
-Wire Bus Line
- 13500 1150 13500 4500
-Wire Bus Line
- 13500 4500 14450 4500
Wire Wire Line
8750 1050 8100 1050
Wire Wire Line
@@ -1360,4 +1348,16 @@ Wire Wire Line
Connection ~ 14200 8950
Wire Wire Line
13400 8950 12700 8950
+Wire Bus Line
+ 7400 3050 7400 800
+Wire Bus Line
+ 7400 800 8550 800
+Wire Bus Line
+ 13500 1150 13500 4600
+Wire Bus Line
+ 13500 4600 14850 4600
+Text GLabel 14850 4600 2 60 BiDi ~ 0
+SDRAM_DQ[31..0]
+Text Label 14500 4600 2 60 ~ 0
+SDRAM_DQ[31..0]
$EndSCHEMATC
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