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0  boards/milkymist-one/synthesis/build/.keep_me
No changes.
66  boards/mixxeo/rtl/system.v
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+/*
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+ * Milkymist VJ SoC fjmem flasher
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+ * Copyright (C) 2010 Michael Walle
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+ *
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+ * This program is free software: you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation, version 3 of the License.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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+ */
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+
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+module system(
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+    input clk50,
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+    
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+    /* flash */
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+    output [23:0] flash_adr,
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+    inout [15:0] flash_d,
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+    output flash_oe_n,
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+    output flash_we_n,
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+    output flash_ce_n,
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+    output flash_rst_n,
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+    input flash_sts,
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+
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+	/* debug */
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+	output led
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+);
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+
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+/* clock and reset */
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+wire sys_rst;
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+wire sys_clk;
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+assign sys_clk = clk50;
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+assign sys_rst = 1'b0;
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+
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+/* flash control pins */
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+assign flash_ce_n = 1'b0;
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+assign flash_rst_n = 1'b1;
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+
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+/* debug */
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+wire fjmem_update;
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+reg [25:0] counter;
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+always @(posedge sys_clk)
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+	counter <= counter + 1'd1;
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+
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+assign led = counter[25] ^ fjmem_update;
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+
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+fjmem #(
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+    .adr_width(24)
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+) fjmem (
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+    .sys_clk(sys_clk),
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+    .sys_rst(sys_rst),
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+
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+    .flash_adr(flash_adr),
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+    .flash_d(flash_d),
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+    .flash_oe_n(flash_oe_n),
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+    .flash_we_n(flash_we_n),
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+
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+	.fjmem_update(fjmem_update)
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+);
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+
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+endmodule
26  boards/mixxeo/synthesis/Makefile.xst
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+BOARD_DIR=../rtl
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+FJMEM_DIR=../../../fjmem/rtl
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+
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+SRC = $(wildcard $(BOARD_DIR)/*.v)
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+SRC += $(wildcard $(FJMEM_DIR)/*.v)
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+SRC += $(wildcard $(FJMEM_DIR)/spartan6/*.v)
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+
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+all: build/system.bit
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+
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+build/system.ucf: system.ucf
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+	cp system.ucf build/system.ucf
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+
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+build/system.prj: $(SRC)
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+	rm -f build/system.prj
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+	for i in `echo $^`; do \
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+	    echo "verilog work ../$$i" >> build/system.prj; \
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+	done
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+
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+build/system.ngc: build/system.prj
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+	cd build && xst -ifn ../system.xst
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+
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+build/system.ngd: build/system.ngc build/system.ucf
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+	cd build && ngdbuild -uc system.ucf system.ngc
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+
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+include common.mak
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+
0  boards/mixxeo/synthesis/build/.keep_me
No changes.
27  boards/mixxeo/synthesis/common.mak
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+timing: build/system-routed.twr
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+
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+usage: build/system-routed.xdl
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+	../../../tools/xdlanalyze.pl build/system-routed.xdl 0
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+
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+load: build/system.bit
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+	cd build && impact -batch ../load.cmd
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+
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+build/system.ncd: build/system.ngd
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+	cd build && map -ol high -w system.ngd
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+
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+build/system-routed.ncd: build/system.ncd
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+	cd build && par -ol high -w system.ncd system-routed.ncd
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+
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+build/system.bit: build/system-routed.ncd
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+	cd build && bitgen -g LCK_cycle:6 -w system-routed.ncd system.bit
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+
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+build/system-routed.xdl: build/system-routed.ncd
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+	cd build && xdl -ncd2xdl system-routed.ncd system-routed.xdl
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+
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+build/system-routed.twr: build/system-routed.ncd
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+	cd build && trce -e 100 system-routed.ncd system.pcf
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+
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+clean:
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+	rm -rf build/*
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+
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+.PHONY: timing usage load clean
59  boards/mixxeo/synthesis/system.ucf
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+# ==== Clock input ====
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+NET "clk50" LOC = AB13 | IOSTANDARD = LVCMOS33;
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+
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+NET "clk50" TNM_NET = "GRPclk50";
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+TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
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+
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+# ==== Flash ====
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+NET "flash_adr(0)" LOC = L22;
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+NET "flash_adr(1)" LOC = L20;
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+NET "flash_adr(2)" LOC = K22;
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+NET "flash_adr(3)" LOC = K21;
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+NET "flash_adr(4)" LOC = J19;
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+NET "flash_adr(5)" LOC = H20;
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+NET "flash_adr(6)" LOC = F22;
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+NET "flash_adr(7)" LOC = F21;
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+NET "flash_adr(8)" LOC = K17;
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+NET "flash_adr(9)" LOC = J17;
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+NET "flash_adr(10)" LOC = E22;
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+NET "flash_adr(11)" LOC = E20;
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+NET "flash_adr(12)" LOC = H18;
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+NET "flash_adr(13)" LOC = H19;
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+NET "flash_adr(14)" LOC = F20;
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+NET "flash_adr(15)" LOC = G19;
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+NET "flash_adr(16)" LOC = C22;
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+NET "flash_adr(17)" LOC = C20;
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+NET "flash_adr(18)" LOC = D22;
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+NET "flash_adr(19)" LOC = D21;
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+NET "flash_adr(20)" LOC = F19;
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+NET "flash_adr(21)" LOC = F18;
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+NET "flash_adr(22)" LOC = D20;
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+NET "flash_adr(23)" LOC = D19;
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+NET "flash_d(0)" LOC = AA20;
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+NET "flash_d(1)" LOC = U14;
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+NET "flash_d(2)" LOC = U13;
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+NET "flash_d(3)" LOC = AA6;
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+NET "flash_d(4)" LOC = AB6;
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+NET "flash_d(5)" LOC = W4;
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+NET "flash_d(6)" LOC = Y4;
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+NET "flash_d(7)" LOC = Y7;
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+NET "flash_d(8)" LOC = AA2;
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+NET "flash_d(9)" LOC = AB2;
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+NET "flash_d(10)" LOC = V15;
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+NET "flash_d(11)" LOC = AA18;
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+NET "flash_d(12)" LOC = AB18;
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+NET "flash_d(13)" LOC = Y13;
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+NET "flash_d(14)" LOC = AA12;
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+NET "flash_d(15)" LOC = AB12;
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+
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+NET "flash_adr(*)" IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
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+NET "flash_d(*)" IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 | PULLDOWN;
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+
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+NET "flash_ce_n" LOC = M21 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
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+NET "flash_oe_n" LOC = M22 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
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+NET "flash_we_n" LOC = N20 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
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+NET "flash_rst_n" LOC = P22 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
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+NET "flash_sts" LOC = R20 | IOSTANDARD = LVCMOS33 | PULLUP;
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+
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+# ==== LEDs ====
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+NET "led" LOC = V5 | IOSTANDARD = LVCMOS33 | SLEW = QUIETIO | DRIVE = 24;
8  boards/mixxeo/synthesis/system.xst
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+run
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+-ifn system.prj
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+-top system
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+-ifmt MIXED
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+-opt_mode SPEED
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+-opt_level 2
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+-ofn system.ngc
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+-p xc6slx45-fgg484-2

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