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base fork: m-labs/fjmem-m1
base: b841f4b373dd
...
head fork: m-labs/fjmem-m1
compare: 8c1ea67f0ea1
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  • 2 commits
  • 7 files changed
  • 0 commit comments
  • 1 contributor
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0  boards/milkymist-one/synthesis/build/.keep_me
No changes.
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66 boards/mixxeo/rtl/system.v
@@ -0,0 +1,66 @@
+/*
+ * Milkymist VJ SoC fjmem flasher
+ * Copyright (C) 2010 Michael Walle
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+module system(
+ input clk50,
+
+ /* flash */
+ output [23:0] flash_adr,
+ inout [15:0] flash_d,
+ output flash_oe_n,
+ output flash_we_n,
+ output flash_ce_n,
+ output flash_rst_n,
+ input flash_sts,
+
+ /* debug */
+ output led
+);
+
+/* clock and reset */
+wire sys_rst;
+wire sys_clk;
+assign sys_clk = clk50;
+assign sys_rst = 1'b0;
+
+/* flash control pins */
+assign flash_ce_n = 1'b0;
+assign flash_rst_n = 1'b1;
+
+/* debug */
+wire fjmem_update;
+reg [25:0] counter;
+always @(posedge sys_clk)
+ counter <= counter + 1'd1;
+
+assign led = counter[25] ^ fjmem_update;
+
+fjmem #(
+ .adr_width(24)
+) fjmem (
+ .sys_clk(sys_clk),
+ .sys_rst(sys_rst),
+
+ .flash_adr(flash_adr),
+ .flash_d(flash_d),
+ .flash_oe_n(flash_oe_n),
+ .flash_we_n(flash_we_n),
+
+ .fjmem_update(fjmem_update)
+);
+
+endmodule
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26 boards/mixxeo/synthesis/Makefile.xst
@@ -0,0 +1,26 @@
+BOARD_DIR=../rtl
+FJMEM_DIR=../../../fjmem/rtl
+
+SRC = $(wildcard $(BOARD_DIR)/*.v)
+SRC += $(wildcard $(FJMEM_DIR)/*.v)
+SRC += $(wildcard $(FJMEM_DIR)/spartan6/*.v)
+
+all: build/system.bit
+
+build/system.ucf: system.ucf
+ cp system.ucf build/system.ucf
+
+build/system.prj: $(SRC)
+ rm -f build/system.prj
+ for i in `echo $^`; do \
+ echo "verilog work ../$$i" >> build/system.prj; \
+ done
+
+build/system.ngc: build/system.prj
+ cd build && xst -ifn ../system.xst
+
+build/system.ngd: build/system.ngc build/system.ucf
+ cd build && ngdbuild -uc system.ucf system.ngc
+
+include common.mak
+
View
0  boards/mixxeo/synthesis/build/.keep_me
No changes.
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27 boards/mixxeo/synthesis/common.mak
@@ -0,0 +1,27 @@
+timing: build/system-routed.twr
+
+usage: build/system-routed.xdl
+ ../../../tools/xdlanalyze.pl build/system-routed.xdl 0
+
+load: build/system.bit
+ cd build && impact -batch ../load.cmd
+
+build/system.ncd: build/system.ngd
+ cd build && map -ol high -w system.ngd
+
+build/system-routed.ncd: build/system.ncd
+ cd build && par -ol high -w system.ncd system-routed.ncd
+
+build/system.bit: build/system-routed.ncd
+ cd build && bitgen -g LCK_cycle:6 -w system-routed.ncd system.bit
+
+build/system-routed.xdl: build/system-routed.ncd
+ cd build && xdl -ncd2xdl system-routed.ncd system-routed.xdl
+
+build/system-routed.twr: build/system-routed.ncd
+ cd build && trce -e 100 system-routed.ncd system.pcf
+
+clean:
+ rm -rf build/*
+
+.PHONY: timing usage load clean
View
59 boards/mixxeo/synthesis/system.ucf
@@ -0,0 +1,59 @@
+# ==== Clock input ====
+NET "clk50" LOC = AB13 | IOSTANDARD = LVCMOS33;
+
+NET "clk50" TNM_NET = "GRPclk50";
+TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
+
+# ==== Flash ====
+NET "flash_adr(0)" LOC = L22;
+NET "flash_adr(1)" LOC = L20;
+NET "flash_adr(2)" LOC = K22;
+NET "flash_adr(3)" LOC = K21;
+NET "flash_adr(4)" LOC = J19;
+NET "flash_adr(5)" LOC = H20;
+NET "flash_adr(6)" LOC = F22;
+NET "flash_adr(7)" LOC = F21;
+NET "flash_adr(8)" LOC = K17;
+NET "flash_adr(9)" LOC = J17;
+NET "flash_adr(10)" LOC = E22;
+NET "flash_adr(11)" LOC = E20;
+NET "flash_adr(12)" LOC = H18;
+NET "flash_adr(13)" LOC = H19;
+NET "flash_adr(14)" LOC = F20;
+NET "flash_adr(15)" LOC = G19;
+NET "flash_adr(16)" LOC = C22;
+NET "flash_adr(17)" LOC = C20;
+NET "flash_adr(18)" LOC = D22;
+NET "flash_adr(19)" LOC = D21;
+NET "flash_adr(20)" LOC = F19;
+NET "flash_adr(21)" LOC = F18;
+NET "flash_adr(22)" LOC = D20;
+NET "flash_adr(23)" LOC = D19;
+NET "flash_d(0)" LOC = AA20;
+NET "flash_d(1)" LOC = U14;
+NET "flash_d(2)" LOC = U13;
+NET "flash_d(3)" LOC = AA6;
+NET "flash_d(4)" LOC = AB6;
+NET "flash_d(5)" LOC = W4;
+NET "flash_d(6)" LOC = Y4;
+NET "flash_d(7)" LOC = Y7;
+NET "flash_d(8)" LOC = AA2;
+NET "flash_d(9)" LOC = AB2;
+NET "flash_d(10)" LOC = V15;
+NET "flash_d(11)" LOC = AA18;
+NET "flash_d(12)" LOC = AB18;
+NET "flash_d(13)" LOC = Y13;
+NET "flash_d(14)" LOC = AA12;
+NET "flash_d(15)" LOC = AB12;
+
+NET "flash_adr(*)" IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
+NET "flash_d(*)" IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 | PULLDOWN;
+
+NET "flash_ce_n" LOC = M21 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
+NET "flash_oe_n" LOC = M22 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
+NET "flash_we_n" LOC = N20 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
+NET "flash_rst_n" LOC = P22 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
+NET "flash_sts" LOC = R20 | IOSTANDARD = LVCMOS33 | PULLUP;
+
+# ==== LEDs ====
+NET "led" LOC = V5 | IOSTANDARD = LVCMOS33 | SLEW = QUIETIO | DRIVE = 24;
View
8 boards/mixxeo/synthesis/system.xst
@@ -0,0 +1,8 @@
+run
+-ifn system.prj
+-top system
+-ifmt MIXED
+-opt_mode SPEED
+-opt_level 2
+-ofn system.ngc
+-p xc6slx45-fgg484-2

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