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Copyright 2016-2017 / EnjoyDigital Copyright 2016-2017 / M-Labs Ltd A small footprint and configurable JESD204B core [> Features ----------- PHY: - PRBS7/PRBS15/PRBS31 to check link integrity. - 8B/10B encoding - 32 bits interface - Kintex7 support (CPLL up to 5Gbps, QPLL for higher linerates) - Kintex Ultrascale support (CPLL up to 6.25Gbps, QPLL for higher linerates) Core: Link: - Scrambling to reduce EMI - Special characters insertion - CGS/ILAS Transport: - converters <--> lanes mapping [> Possible improvements ------------------------ - add support for RX (ADC) - add support for non scrambled mode - add support for Altera PHYs - add support for Lattice PHYs - add support for others Xilinx transceivers [> Tests -------- Unit tests are available in ./test/. To run all the unit tests: setup.py test Tests can also be run individually: python3 -m unittest test.test_name