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new time/early_printk/uart drivers compiling, untested

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commit 3faaf7ade0ff5ef6355bdb3e68c001634ec5c71f 1 parent aa07145
Sébastien Bourdeauducq authored May 22, 2012
6  arch/lm32/Kconfig.cpu
@@ -20,6 +20,7 @@ config CPU_MICO32
20 20
 	bool "mico32"
21 21
 	help
22 22
 	  LatticeMico32 processor.
  23
+
23 24
 endchoice
24 25
 
25 26
 choice
@@ -29,15 +30,12 @@ choice
29 30
 config	BOARD_MILKYMIST_ONE
30 31
 	bool "Milkymist One"
31 32
 
32  
-config	BOARD_MILKYMIST_SOC
33  
-	bool "Milkymist SoC"
34 33
 endchoice
35 34
 endif
36 35
 
37 36
 config CPU_CLOCK
38 37
 	int "CPU Clock [Hz] (integer)"
39  
-	default "80000000" if BOARD_MILKYMIST_ONE
40  
-	default "100000000" if BOARD_MILKYMIST_SOC
  38
+	default "83333333" if BOARD_MILKYMIST_ONE
41 39
 
42 40
 config KERNEL_BASE_ADDR
43 41
 	hex "Physical address where Linux Kernel is"
42  arch/lm32/boot/dts/milkymist_one.dts
@@ -23,7 +23,7 @@
23 23
 			device_type = "cpu";
24 24
 			compatible = "lattice,mico32";
25 25
 			reg = <0>;
26  
-			clock-frequency = <80000000>;	/* 80 MHz */
  26
+			clock-frequency = <83333333>;
27 27
 			i-cache-line-size = <16>;
28 28
 			d-cache-line-size = <16>;
29 29
 			i-cache-size = <4096>;
@@ -43,46 +43,34 @@
43 43
 		reg = <0x40000000 0x08000000>;	/* 128MB */
44 44
 	};
45 45
 
46  
-	flash@0 {
47  
-		compatible = "cfi-flash";
48  
-		reg = <0x80000000 0x02000000>;	/* 32MB */
49  
-		bank-width = <4>;
50  
-		device-width = <1>;
51  
-		#address-cells = <1>;
52  
-		#size-cells = <1>;
53  
-		partition@0 {
54  
-			label = "bitstream";
55  
-			reg = <0x00000000 0x00180000>;
56  
-			read-only;
57  
-		};
58  
-		partition@180000 {
59  
-			label = "unused";
60  
-			reg = <0x000a0000 0x02360000>;
61  
-			read-only;
62  
-		};
63  
-	};
64  
-
65 46
 	csr-bus@e0000000 {
66 47
 		#address-cells = <1>;
67 48
 		#size-cells = <1>;
68 49
 		ranges = <0x0 0xe0000000 0x100000>;
69 50
 		compatible = "milkymist,csr-bus";
70 51
 
71  
-		uart@0 {
  52
+		uart@0000 {
72 53
 			device_type = "serial";
73 54
 			compatible = "milkymist,uart";
74  
-			clock-frequency = <80000000>;
75  
-			reg = <0x0 0x1000>;
  55
+			clock-frequency = <83333333>;
  56
+			reg = <0x0000 0x800>;
76 57
 			interrupts = <0>;
77 58
 			interrupt-parent = <&pic>;
78 59
 		};
  60
+		
  61
+		timer@1800 {
  62
+			compatible = "milkymist,timer";
  63
+			reg = <0x1800 0x800>;
  64
+			interrupts = <1>;
  65
+			interrupt-parent = <&pic>;
  66
+		};
79 67
 
80  
-		ethernet@8000 {
  68
+		ethernet@2000 {
81 69
 			#address-cells = <1>;
82 70
 			#size-cells = <0>;
83  
-			compatible = "milkymist,minimac2";
84  
-			reg = <0x8000 0x1000>;
85  
-			interrupts = <10 11>;
  71
+			compatible = "milkymist,minimac3";
  72
+			reg = <0x2000 0x800>;
  73
+			interrupts = <2>;
86 74
 			interrupt-parent = <&pic>;
87 75
 
88 76
 			phy0: ethernet-phy@0 {
85  arch/lm32/defconfig
@@ -161,19 +161,18 @@ CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
161 161
 CONFIG_PLAT_MILKYMIST=y
162 162
 CONFIG_CPU_MICO32=y
163 163
 CONFIG_BOARD_MILKYMIST_ONE=y
164  
-# CONFIG_BOARD_MILKYMIST_SOC is not set
165  
-CONFIG_CPU_CLOCK=80000000
  164
+CONFIG_CPU_CLOCK=83333333
166 165
 CONFIG_KERNEL_BASE_ADDR=0x40000000
167  
-# CONFIG_EARLY_PRINTK is not set
  166
+CONFIG_EARLY_PRINTK=y
168 167
 # CONFIG_LM32_HW_JTAG is not set
169 168
 # CONFIG_NO_HZ is not set
170 169
 # CONFIG_HIGH_RES_TIMERS is not set
171 170
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
172  
-# CONFIG_HZ_100 is not set
173  
-CONFIG_HZ_250=y
  171
+CONFIG_HZ_100=y
  172
+# CONFIG_HZ_250 is not set
174 173
 # CONFIG_HZ_300 is not set
175 174
 # CONFIG_HZ_1000 is not set
176  
-CONFIG_HZ=250
  175
+CONFIG_HZ=100
177 176
 # CONFIG_SCHED_HRTICK is not set
178 177
 CONFIG_FLATMEM_MANUAL=y
179 178
 CONFIG_HAVE_MEMBLOCK=y
@@ -250,7 +249,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
250 249
 # CONFIG_ATM is not set
251 250
 # CONFIG_L2TP is not set
252 251
 # CONFIG_BRIDGE is not set
253  
-# CONFIG_NET_DSA is not set
254 252
 # CONFIG_VLAN_8021Q is not set
255 253
 # CONFIG_DECNET is not set
256 254
 # CONFIG_LLC2 is not set
@@ -313,8 +311,6 @@ CONFIG_OF_ADDRESS=y
313 311
 CONFIG_OF_IRQ=y
314 312
 CONFIG_OF_DEVICE=y
315 313
 CONFIG_OF_GPIO=y
316  
-CONFIG_OF_NET=y
317  
-CONFIG_OF_MDIO=y
318 314
 # CONFIG_PARPORT is not set
319 315
 CONFIG_BLK_DEV=y
320 316
 # CONFIG_BLK_DEV_COW_COMMON is not set
@@ -346,66 +342,7 @@ CONFIG_SCSI_MOD=y
346 342
 # CONFIG_SCSI_NETLINK is not set
347 343
 # CONFIG_ATA is not set
348 344
 # CONFIG_MD is not set
349  
-CONFIG_NETDEVICES=y
350  
-# CONFIG_DUMMY is not set
351  
-# CONFIG_BONDING is not set
352  
-# CONFIG_MACVLAN is not set
353  
-# CONFIG_EQUALIZER is not set
354  
-# CONFIG_TUN is not set
355  
-# CONFIG_VETH is not set
356  
-# CONFIG_MII is not set
357  
-CONFIG_PHYLIB=y
358  
-
359  
-#
360  
-# MII PHY device drivers
361  
-#
362  
-CONFIG_MARVELL_PHY=y
363  
-# CONFIG_DAVICOM_PHY is not set
364  
-# CONFIG_QSEMI_PHY is not set
365  
-# CONFIG_LXT_PHY is not set
366  
-# CONFIG_CICADA_PHY is not set
367  
-# CONFIG_VITESSE_PHY is not set
368  
-# CONFIG_SMSC_PHY is not set
369  
-# CONFIG_BROADCOM_PHY is not set
370  
-# CONFIG_ICPLUS_PHY is not set
371  
-# CONFIG_REALTEK_PHY is not set
372  
-# CONFIG_NATIONAL_PHY is not set
373  
-# CONFIG_STE10XP is not set
374  
-# CONFIG_LSI_ET1011C_PHY is not set
375  
-CONFIG_MICREL_PHY=y
376  
-# CONFIG_FIXED_PHY is not set
377  
-CONFIG_MDIO_BITBANG=y
378  
-# CONFIG_MDIO_GPIO is not set
379  
-# CONFIG_NET_ETHERNET is not set
380  
-# CONFIG_NETDEV_1000 is not set
381  
-# CONFIG_NETDEV_10000 is not set
382  
-# CONFIG_WLAN is not set
383  
-
384  
-#
385  
-# Enable WiMAX (Networking options) to see the WiMAX drivers
386  
-#
387  
-# CONFIG_WAN is not set
388  
-
389  
-#
390  
-# CAIF transport drivers
391  
-#
392  
-CONFIG_PPP=y
393  
-# CONFIG_PPP_MULTILINK is not set
394  
-# CONFIG_PPP_FILTER is not set
395  
-CONFIG_PPP_ASYNC=y
396  
-CONFIG_PPP_SYNC_TTY=y
397  
-CONFIG_PPP_DEFLATE=y
398  
-CONFIG_PPP_BSDCOMP=y
399  
-# CONFIG_PPP_MPPE is not set
400  
-# CONFIG_PPPOE is not set
401  
-CONFIG_SLIP=y
402  
-CONFIG_SLIP_COMPRESSED=y
403  
-CONFIG_SLHC=y
404  
-# CONFIG_SLIP_SMART is not set
405  
-# CONFIG_SLIP_MODE_SLIP6 is not set
406  
-# CONFIG_NETCONSOLE is not set
407  
-# CONFIG_NETPOLL is not set
408  
-# CONFIG_NET_POLL_CONTROLLER is not set
  345
+# CONFIG_NETDEVICES is not set
409 346
 # CONFIG_ISDN is not set
410 347
 # CONFIG_PHONE is not set
411 348
 
@@ -555,12 +492,7 @@ CONFIG_GPIOLIB=y
555 492
 # CONFIG_HWMON is not set
556 493
 # CONFIG_THERMAL is not set
557 494
 # CONFIG_WATCHDOG is not set
558  
-CONFIG_MFD_SUPPORT=y
559  
-# CONFIG_MFD_CORE is not set
560  
-# CONFIG_MFD_SM501 is not set
561  
-# CONFIG_HTC_PASIC3 is not set
562  
-# CONFIG_MFD_TMIO is not set
563  
-# CONFIG_ABX500_CORE is not set
  495
+# CONFIG_MFD_SUPPORT is not set
564 496
 # CONFIG_REGULATOR is not set
565 497
 # CONFIG_MEDIA_SUPPORT is not set
566 498
 
@@ -597,7 +529,7 @@ CONFIG_DUMMY_CONSOLE=y
597 529
 #
598 530
 # CONFIG_VIRTIO_BALLOON is not set
599 531
 # CONFIG_STAGING is not set
600  
-CONFIG_IOMMU_SUPPORT=y
  532
+# CONFIG_IOMMU_SUPPORT is not set
601 533
 # CONFIG_VIRT_DRIVERS is not set
602 534
 
603 535
 #
@@ -893,7 +825,6 @@ CONFIG_CRC32=y
893 825
 # CONFIG_LIBCRC32C is not set
894 826
 # CONFIG_CRC8 is not set
895 827
 CONFIG_ZLIB_INFLATE=y
896  
-CONFIG_ZLIB_DEFLATE=y
897 828
 # CONFIG_XZ_DEC is not set
898 829
 # CONFIG_XZ_DEC_BCJ is not set
899 830
 CONFIG_DECOMPRESS_GZIP=y
8  arch/lm32/kernel/process.c
@@ -46,7 +46,6 @@
46 46
 #include <asm/traps.h>
47 47
 #include <asm/setup.h>
48 48
 #include <asm/pgtable.h>
49  
-#include <asm/hw/milkymist.h>
50 49
 
51 50
 asmlinkage void ret_from_fork(void);
52 51
 asmlinkage void syscall_tail(void);
@@ -93,9 +92,9 @@ void cpu_idle(void)
93 92
 
94 93
 void machine_restart(char * __unused)
95 94
 {
96  
-	/* Writing to CSR_SYSTEM_ID causes a system reset */
97  
-	iowrite32be(1, CSR_SYSTEM_ID);
98  
-	while(1);
  95
+	printk("%s:%d: machine_restart() is not possible on lm32\n", __FILE__, __LINE__);
  96
+	for (;;)
  97
+		cpu_relax();
99 98
 }
100 99
 
101 100
 void machine_halt(void)
@@ -259,4 +258,3 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long usp)
259 258
 
260 259
 	/*printk("start_thread: current=%lx usp=%lx\n", current, usp);*/
261 260
 }
262  
-
19  arch/lm32/platforms/milkymist/early_printk.c
@@ -36,26 +36,15 @@
36 36
 #include <asm/irq.h>
37 37
 #include <linux/io.h>
38 38
 
39  
-#define UART_RXTX     (void*)0xe0000000
40  
-#define UART_DIVISOR  (void*)0xe0000004
41  
-#define UART_STAT     (void*)0xe0000008
42  
-#define UART_CTRL     (void*)0xe000000c
43  
-#define UART_DEBUG    (void*)0xe000000c
  39
+#define UART_RXTX		((void *)0xe0000000)
  40
+#define UART_STAT		((void *)0xe000000c)
44 41
 
45  
-#define UART_STAT_THRE   (1<<0)
46  
-#define UART_STAT_RX_EVT (1<<1)
47  
-#define UART_STAT_TX_EVT (1<<2)
  42
+#define UART_STAT_TXING		(1)
48 43
 
49 44
 static void __init early_console_putc(char c)
50 45
 {
51  
-	unsigned int timeout = 1000;
52  
-	uint32_t stat;
53  
-
54 46
 	iowrite32be(c, UART_RXTX);
55  
-
56  
-	do {
57  
-		stat = ioread32be(UART_STAT);
58  
-	} while (!(stat & UART_STAT_THRE) && --timeout);
  47
+	while(ioread32be(UART_STAT) & UART_STAT_TXING);
59 48
 }
60 49
 
61 50
 static void __init early_console_write(struct console *con, const char *s,
1  arch/lm32/platforms/milkymist/setup.c
@@ -8,4 +8,3 @@ void __init plat_setup_arch(void)
8 8
     milkymist_setup_early_printk();
9 9
 #endif
10 10
 }
11  
-
118  arch/lm32/platforms/milkymist/time.c
@@ -21,74 +21,73 @@
21 21
 #include <linux/timex.h>
22 22
 #include <linux/io.h>
23 23
 
24  
-#include <asm/hw/interrupts.h>
25  
-#include <asm/hw/sysctl.h>
  24
+// TODO: use the DTS?
  25
+#define TIMER0_BASE		0xe0001800
26 26
 
27  
-#define TIMER_CLOCKEVENT 0
28  
-#define TIMER_CLOCKSOURCE 1
  27
+#define TIMER0_CSR(x)		((void *)(TIMER0_BASE+(x)))
29 28
 
30  
-static uint32_t milkymist_ticks_per_jiffy;
  29
+#define CSR_TIMER0_EN		TIMER0_CSR(0x00)
31 30
 
32  
-static inline uint32_t milkymist_timer_get_counter(unsigned int timer)
33  
-{
34  
-	return ioread32be(CSR_TIMER_COUNTER(timer));
35  
-}
  31
+#define CSR_TIMER0_COUNT3	TIMER0_CSR(0x04)
  32
+#define CSR_TIMER0_COUNT2	TIMER0_CSR(0x08)
  33
+#define CSR_TIMER0_COUNT1	TIMER0_CSR(0x0C)
  34
+#define CSR_TIMER0_COUNT0	TIMER0_CSR(0x10)
36 35
 
37  
-static inline void milkymist_timer_set_counter(unsigned int timer, uint32_t value)
38  
-{
39  
-	iowrite32be(value, CSR_TIMER_COUNTER(timer));
40  
-}
  36
+#define CSR_TIMER0_RELOAD3	TIMER0_CSR(0x14)
  37
+#define CSR_TIMER0_RELOAD2	TIMER0_CSR(0x18)
  38
+#define CSR_TIMER0_RELOAD1	TIMER0_CSR(0x1C)
  39
+#define CSR_TIMER0_RELOAD0	TIMER0_CSR(0x20)
41 40
 
42  
-static inline uint32_t milkymist_timer_get_compare(unsigned int timer)
43  
-{
44  
-	return ioread32be(CSR_TIMER_COMPARE(timer));
45  
-}
  41
+#define CSR_TIMER0_EV_STAT	TIMER0_CSR(0x24)
  42
+#define CSR_TIMER0_EV_PENDING	TIMER0_CSR(0x28)
  43
+#define CSR_TIMER0_EV_ENABLE	TIMER0_CSR(0x2C)
46 44
 
47  
-static inline void milkymist_timer_set_compare(unsigned int timer, uint32_t value)
  45
+#define TIMER0_INTERRUPT	1
  46
+
  47
+
  48
+static uint32_t milkymist_ticks_per_jiffy;
  49
+
  50
+static inline void milkymist_timer_set_counter(uint32_t value)
48 51
 {
49  
-	iowrite32be(value, CSR_TIMER_COMPARE(timer));
  52
+	iowrite32be((value & 0xff000000) >> 24, CSR_TIMER0_COUNT3);
  53
+	iowrite32be((value & 0x00ff0000) >> 16, CSR_TIMER0_COUNT2);
  54
+	iowrite32be((value & 0x0000ff00) >> 8, CSR_TIMER0_COUNT1);
  55
+	iowrite32be(value & 0x000000ff, CSR_TIMER0_COUNT0);
50 56
 }
51 57
 
52  
-static inline void milkymist_timer_disable(unsigned int timer)
  58
+static inline void milkymist_timer_set_reload(uint32_t value)
53 59
 {
54  
-	iowrite32be(0, CSR_TIMER_CONTROL(timer));
  60
+	iowrite32be((value & 0xff000000) >> 24, CSR_TIMER0_RELOAD3);
  61
+	iowrite32be((value & 0x00ff0000) >> 16, CSR_TIMER0_RELOAD2);
  62
+	iowrite32be((value & 0x0000ff00) >> 8, CSR_TIMER0_RELOAD1);
  63
+	iowrite32be(value & 0x000000ff, CSR_TIMER0_RELOAD0);
55 64
 }
56 65
 
57  
-static inline void milkymist_timer_enable(unsigned int timer, bool periodic)
  66
+static inline void milkymist_timer_disable(void)
58 67
 {
59  
-	uint32_t val = TIMER_ENABLE;
60  
-	if (periodic);
61  
-		val |= TIMER_AUTORESTART;
62  
-	iowrite32be(val, CSR_TIMER_CONTROL(timer));
  68
+	iowrite32be(0, CSR_TIMER0_EN);
63 69
 }
64 70
 
65  
-cycles_t get_cycles(void)
  71
+static inline void milkymist_timer_enable(void)
66 72
 {
67  
-	return milkymist_timer_get_counter(TIMER_CLOCKSOURCE);
  73
+	iowrite32be(1, CSR_TIMER0_EN);
68 74
 }
69 75
 
70  
-static cycle_t milkymist_clocksource_read(struct clocksource *cs)
  76
+cycles_t get_cycles(void)
71 77
 {
72  
-	return get_cycles();
  78
+	return 0;
73 79
 }
74 80
 
75  
-static struct clocksource milkymist_clocksource = {
76  
-	.name = "milkymist-timer",
77  
-	.rating = 200,
78  
-	.read = milkymist_clocksource_read,
79  
-	.mask = CLOCKSOURCE_MASK(32),
80  
-	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
81  
-};
82  
-
83 81
 static irqreturn_t milkymist_clockevent_irq(int irq, void *devid)
84 82
 {
85 83
 	struct clock_event_device *cd = devid;
86 84
 
87 85
 	if (cd->mode != CLOCK_EVT_MODE_PERIODIC)
88  
-		milkymist_timer_disable(TIMER_CLOCKEVENT);
  86
+		milkymist_timer_disable();
89 87
 
90 88
 	cd->event_handler(cd);
91  
-
  89
+	
  90
+	iowrite32be(1, CSR_TIMER0_EV_PENDING);
92 91
 	return IRQ_HANDLED;
93 92
 }
94 93
 
@@ -97,15 +96,22 @@ static void milkymist_clockevent_set_mode(enum clock_event_mode mode,
97 96
 {
98 97
 	switch (mode) {
99 98
 	case CLOCK_EVT_MODE_PERIODIC:
100  
-		milkymist_timer_disable(TIMER_CLOCKEVENT);
101  
-		milkymist_timer_set_counter(TIMER_CLOCKEVENT, 0);
102  
-		milkymist_timer_set_compare(TIMER_CLOCKEVENT, milkymist_ticks_per_jiffy);
  99
+		milkymist_timer_disable();
  100
+		milkymist_timer_set_counter(milkymist_ticks_per_jiffy);
  101
+		milkymist_timer_set_reload(milkymist_ticks_per_jiffy);
  102
+		milkymist_timer_enable();
  103
+		break;
103 104
 	case CLOCK_EVT_MODE_RESUME:
104  
-		milkymist_timer_enable(TIMER_CLOCKEVENT, true);
  105
+		milkymist_timer_enable();
105 106
 		break;
106 107
 	case CLOCK_EVT_MODE_ONESHOT:
  108
+		milkymist_timer_disable();
  109
+		milkymist_timer_set_counter(milkymist_ticks_per_jiffy);
  110
+		milkymist_timer_set_reload(0);
  111
+		milkymist_timer_enable();
  112
+		break;
107 113
 	case CLOCK_EVT_MODE_SHUTDOWN:
108  
-		milkymist_timer_disable(TIMER_CLOCKEVENT);
  114
+		milkymist_timer_disable();
109 115
 		break;
110 116
 	default:
111 117
 		break;
@@ -115,9 +121,9 @@ static void milkymist_clockevent_set_mode(enum clock_event_mode mode,
115 121
 static int milkymist_clockevent_set_next(unsigned long evt,
116 122
 	struct clock_event_device *cd)
117 123
 {
118  
-	milkymist_timer_set_counter(TIMER_CLOCKEVENT, 0);
119  
-	milkymist_timer_set_compare(TIMER_CLOCKEVENT, evt);
120  
-	milkymist_timer_enable(TIMER_CLOCKEVENT, false);
  124
+	milkymist_timer_disable();
  125
+	milkymist_timer_set_counter(evt);
  126
+	milkymist_timer_enable();
121 127
 
122 128
 	return 0;
123 129
 }
@@ -128,7 +134,7 @@ static struct clock_event_device milkymist_clockevent = {
128 134
 	.set_next_event = milkymist_clockevent_set_next,
129 135
 	.set_mode = milkymist_clockevent_set_mode,
130 136
 	.rating = 200,
131  
-	.irq = IRQ_TIMER0,
  137
+	.irq = TIMER0_INTERRUPT,
132 138
 };
133 139
 
134 140
 static struct irqaction timer_irqaction = {
@@ -140,8 +146,6 @@ static struct irqaction timer_irqaction = {
140 146
 
141 147
 void __init plat_time_init(void)
142 148
 {
143  
-	int ret;
144  
-
145 149
 	milkymist_ticks_per_jiffy = DIV_ROUND_CLOSEST(CONFIG_CPU_CLOCK, HZ);
146 150
 
147 151
 	clockevents_calc_mult_shift(&milkymist_clockevent, CONFIG_CPU_CLOCK, 5);
@@ -149,17 +153,7 @@ void __init plat_time_init(void)
149 153
 	milkymist_clockevent.max_delta_ns = clockevent_delta2ns(0xffff, &milkymist_clockevent);
150 154
 	milkymist_clockevent.cpumask = cpumask_of(0);
151 155
 
152  
-	milkymist_timer_disable(TIMER_CLOCKSOURCE);
153  
-	milkymist_timer_set_compare(TIMER_CLOCKSOURCE, 0xffffffff);
154  
-	milkymist_timer_set_counter(TIMER_CLOCKSOURCE, 0);
155  
-	milkymist_timer_enable(TIMER_CLOCKSOURCE, true);
156  
-
157 156
 	clockevents_register_device(&milkymist_clockevent);
158 157
 
159  
-	ret = clocksource_register_hz(&milkymist_clocksource, CONFIG_CPU_CLOCK);
160  
-
161  
-	if (ret)
162  
-		printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
163  
-
164  
-	setup_irq(IRQ_TIMER0, &timer_irqaction);
  158
+	setup_irq(TIMER0_INTERRUPT, &timer_irqaction);
165 159
 }
81  drivers/tty/serial/milkymist_uart.c
@@ -48,21 +48,17 @@
48 48
 
49 49
 #define MILKYMIST_NR_UARTS CONFIG_SERIAL_MILKYMIST_NR_UARTS
50 50
 
51  
-#define UART_RXTX  0x00
52  
-#define UART_DIV   0x04
53  
-#define UART_STAT  0x08
54  
-#define UART_CTRL  0x0c
55  
-#define UART_DEBUG 0x10
  51
+#define CSR_UART_RXTX		0x00
  52
+#define CSR_UART_DIVISORH	0x04
  53
+#define CSR_UART_DIVISORL	0x08
56 54
 
57  
-#define UART_STAT_THRE    0x01
58  
-#define UART_STAT_RX_EVT  0x02
59  
-#define UART_STAT_TX_EVT  0x04
  55
+#define CSR_UART_EV_STAT	0x0C
  56
+#define CSR_UART_EV_PENDING	0x10
  57
+#define CSR_UART_EV_ENABLE	0x14
60 58
 
61  
-#define UART_CTRL_RX_INT  0x01
62  
-#define UART_CTRL_TX_INT  0x02
63  
-#define UART_CTRL_THRU    0x04
  59
+#define UART_EV_TX		0x1
  60
+#define UART_EV_RX		0x2
64 61
 
65  
-#define UART_DEBUG_BREAK  0x01
66 62
 
67 63
 static struct uart_port milkymist_uart_ports[MILKYMIST_NR_UARTS];
68 64
 
@@ -71,7 +67,7 @@ static void milkymist_uart_tx_char(struct uart_port *port)
71 67
 	struct circ_buf *xmit = &port->state->xmit;
72 68
 
73 69
 	if (port->x_char) {
74  
-		iowrite32be(port->x_char, port->membase + UART_RXTX);
  70
+		iowrite32be(port->x_char, port->membase + CSR_UART_RXTX);
75 71
 		port->x_char = 0;
76 72
 		port->icount.tx++;
77 73
 		return;
@@ -80,7 +76,7 @@ static void milkymist_uart_tx_char(struct uart_port *port)
80 76
 	if (uart_circ_empty(xmit) || uart_tx_stopped(port))
81 77
 		return;
82 78
 
83  
-	iowrite32be(xmit->buf[xmit->tail], port->membase + UART_RXTX);
  79
+	iowrite32be(xmit->buf[xmit->tail], port->membase + CSR_UART_RXTX);
84 80
 	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
85 81
 	port->icount.tx++;
86 82
 
@@ -93,7 +89,7 @@ static void milkymist_uart_rx_char(struct uart_port *port)
93 89
 	struct tty_struct *tty = port->state->port.tty;
94 90
 	unsigned char ch;
95 91
 
96  
-	ch = ioread32be(port->membase + UART_RXTX) & 0xff;
  92
+	ch = ioread32be(port->membase + CSR_UART_RXTX) & 0xff;
97 93
 	port->icount.rx++;
98 94
 
99 95
 	if (uart_handle_sysrq_char(port, ch))
@@ -113,12 +109,12 @@ static irqreturn_t milkymist_uart_isr(int irq, void *data)
113 109
 	spin_lock(&port->lock);
114 110
 
115 111
 	/* read and ack events */
116  
-	stat = ioread32be(port->membase + UART_STAT) & 0xff;
117  
-	iowrite32be(stat, port->membase + UART_STAT);
  112
+	stat = ioread32be(port->membase + CSR_UART_EV_PENDING);
  113
+	iowrite32be(stat, port->membase + CSR_UART_EV_PENDING);
118 114
 
119  
-	if (stat & UART_STAT_RX_EVT)
  115
+	if (stat & UART_EV_RX)
120 116
 		milkymist_uart_rx_char(port);
121  
-	if (stat & UART_STAT_TX_EVT)
  117
+	if (stat & UART_EV_TX)
122 118
 		milkymist_uart_tx_char(port);
123 119
 
124 120
 	spin_unlock(&port->lock);
@@ -129,10 +125,10 @@ static irqreturn_t milkymist_uart_isr(int irq, void *data)
129 125
 static void milkymist_uart_start_tx(struct uart_port *port)
130 126
 {
131 127
 	u8 stat;
132  
-	stat = ioread32be(port->membase + UART_STAT) & 0xff;
  128
+	stat = ioread32be(port->membase + CSR_UART_EV_STAT);
133 129
 
134 130
 	/* transmission is still in progress */
135  
-	if (!(stat & UART_STAT_THRE))
  131
+	if (stat & UART_EV_TX)
136 132
 		return;
137 133
 
138 134
 	milkymist_uart_tx_char(port);
@@ -176,12 +172,10 @@ static int milkymist_uart_startup(struct uart_port *port)
176 172
 	ret = request_irq(port->irq, milkymist_uart_isr,
177 173
 			IRQF_DISABLED, "milkymist_uart", port);
178 174
 
179  
-	/* ack events */
180  
-	iowrite32be(UART_STAT_TX_EVT | UART_STAT_RX_EVT,
181  
-			port->membase + UART_STAT);
182  
-
183  
-	iowrite32be(UART_CTRL_RX_INT | UART_CTRL_TX_INT,
184  
-			port->membase + UART_CTRL);
  175
+	iowrite32be(UART_EV_TX | UART_EV_RX,
  176
+			port->membase + CSR_UART_EV_PENDING);
  177
+	iowrite32be(UART_EV_TX | UART_EV_RX,
  178
+			port->membase + CSR_UART_EV_ENABLE);
185 179
 
186 180
 	if (ret) {
187 181
 		pr_err("milkymist_uart: unable to attach interrupt\n");
@@ -193,7 +187,7 @@ static int milkymist_uart_startup(struct uart_port *port)
193 187
 
194 188
 static void milkymist_uart_shutdown(struct uart_port *port)
195 189
 {
196  
-	iowrite32be(0, port->membase + UART_CTRL);
  190
+	iowrite32be(0, port->membase + CSR_UART_EV_ENABLE);
197 191
 	free_irq(port->irq, port);
198 192
 }
199 193
 
@@ -252,7 +246,8 @@ static void milkymist_uart_set_termios(struct uart_port *port,
252 246
 
253 247
 	spin_lock_irqsave(&port->lock, flags);
254 248
 	uart_update_timeout(port, termios->c_cflag, baud);
255  
-	iowrite32be(quot, port->membase + UART_DIV);
  249
+	iowrite32be((quot & 0xff00) >> 8, port->membase + CSR_UART_DIVISORH);
  250
+	iowrite32be(quot & 0x00ff, port->membase + CSR_UART_DIVISORL);
256 251
 	spin_unlock_irqrestore(&port->lock, flags);
257 252
 
258 253
 	if (tty_termios_baud_rate(termios))
@@ -287,12 +282,11 @@ static struct uart_ops milkymist_uart_ops = {
287 282
 #ifdef CONFIG_SERIAL_MILKYMIST_CONSOLE
288 283
 static void milkymist_uart_console_wait_tx(struct uart_port *port)
289 284
 {
290  
-	int i;
291 285
 	u8 stat;
292 286
 
293  
-	for (i = 0; i < 100000; i++) {
294  
-		stat = ioread32be(port->membase + UART_STAT) & 0xff;
295  
-		if (stat & UART_STAT_THRE)
  287
+	while (true) {
  288
+		stat = ioread32be(port->membase + CSR_UART_EV_STAT);
  289
+		if (!(stat & UART_EV_TX))
296 290
 			break;
297 291
 		cpu_relax();
298 292
 	}
@@ -301,14 +295,14 @@ static void milkymist_uart_console_wait_tx(struct uart_port *port)
301 295
 static void milkymist_uart_console_putchar(struct uart_port *port, int ch)
302 296
 {
303 297
 	milkymist_uart_console_wait_tx(port);
304  
-	iowrite32be(ch, port->membase + UART_RXTX);
  298
+	iowrite32be(ch, port->membase + CSR_UART_RXTX);
305 299
 }
306 300
 
307 301
 static void milkymist_uart_console_write(struct console *co, const char *s,
308 302
 		unsigned int count)
309 303
 {
310 304
 	struct uart_port *port = &milkymist_uart_ports[co->index];
311  
-	u32 ctrl;
  305
+	u32 enabled;
312 306
 	unsigned long flags;
313 307
 	int locked = 1;
314 308
 
@@ -320,21 +314,14 @@ static void milkymist_uart_console_write(struct console *co, const char *s,
320 314
 	/* wait until current transmission is finished */
321 315
 	milkymist_uart_console_wait_tx(port);
322 316
 
323  
-	/* save ctrl and stat */
324  
-	ctrl = ioread32be(port->membase + UART_CTRL);
325  
-
326  
-	/* disable irqs */
327  
-	iowrite32be(ctrl & ~(UART_CTRL_RX_INT | UART_CTRL_TX_INT),
328  
-			port->membase + UART_CTRL);
  317
+	enabled = ioread32be(port->membase + CSR_UART_EV_ENABLE);
  318
+	iowrite32be(0, port->membase + CSR_UART_EV_ENABLE);
329 319
 
330 320
 	uart_console_write(port, s, count, milkymist_uart_console_putchar);
331 321
 	milkymist_uart_console_wait_tx(port);
  322
+	iowrite32be(UART_EV_TX, port->membase + CSR_UART_EV_PENDING);
332 323
 
333  
-	/* ack write event */
334  
-	iowrite32be(UART_STAT_TX_EVT, port->membase + UART_STAT);
335  
-
336  
-	/* restore control register */
337  
-	iowrite32be(ctrl, port->membase + UART_CTRL);
  324
+	iowrite32be(enabled, port->membase + CSR_UART_EV_ENABLE);
338 325
 
339 326
 	if (locked)
340 327
 		spin_unlock_irqrestore(&port->lock, flags);
@@ -520,6 +507,6 @@ static void __exit milkymist_uart_exit(void)
520 507
 module_init(milkymist_uart_init);
521 508
 module_exit(milkymist_uart_exit);
522 509
 
523  
-MODULE_AUTHOR("Milkymist Project");
  510
+MODULE_AUTHOR("RTCM");
524 511
 MODULE_DESCRIPTION("Milkymist UART driver");
525 512
 MODULE_LICENSE("GPL");

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