From 78affc9ea1978d707b376180ec559b62fbf9ea05 Mon Sep 17 00:00:00 2001
From: Owen Anderson <resistor@mac.com>
Date: Thu, 18 Aug 2011 22:47:44 +0000
Subject: [PATCH] STC2L_POST and STC2L_POST should be handled the same as
 STCL_POST/LDC_POST for the purposes of decoding all operands except the
 predicate. Found by randomized testing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138003 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 4 ++++
 test/MC/Disassembler/ARM/arm-tests.txt          | 3 +++
 2 files changed, 7 insertions(+)

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 40a7936cfe..a57102c6e1 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -927,6 +927,8 @@ static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
     case ARM::STC2L_OPTION:
     case ARM::LDCL_POST:
     case ARM::STCL_POST:
+    case ARM::LDC2L_POST:
+    case ARM::STC2L_POST:
       break;
     default:
       Inst.addOperand(MCOperand::CreateReg(0));
@@ -946,6 +948,8 @@ static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
   switch (Inst.getOpcode()) {
     case ARM::LDCL_POST:
     case ARM::STCL_POST:
+    case ARM::LDC2L_POST:
+    case ARM::STC2L_POST:
       imm |= U << 8;
     case ARM::LDC_OPTION:
     case ARM::LDCL_OPTION:
diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt
index cf25875937..66bec91c31 100644
--- a/test/MC/Disassembler/ARM/arm-tests.txt
+++ b/test/MC/Disassembler/ARM/arm-tests.txt
@@ -314,3 +314,6 @@
 
 # CHECK: rfedb	#4!
 0x14 0x0 0x32 0xf9
+
+# CHECK: stc2l	p0, cr0, [r2], #-96
+0x18 0x0 0x62 0xfc