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  • 82 commits
  • 167 files changed
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  • 21 contributors
Oct 05, 2011
Update InstCombine worklist after instruction transform is complete.
When updating the worklist for InstCombine, the Add/AddUsersToWorklist
functions may access the instruction(s) being added, for debug output for
example. If the instructions aren't yet added to the basic block, this
can result in a crash. Finish the instruction transformation before
adjusting the worklist instead.

rdar://10238555


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141203 91177308-0d34-0410-b5e6-96231b3b80d8
30c1ff2
Rafael Ávila de Espíndola Check for the returns_twice attribute in callsFunctionThatReturnsTwic…
…e. This

fixes PR11038, but there are still some cleanups to be done.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141204 91177308-0d34-0410-b5e6-96231b3b80d8
11f1a83
Override TRI::getSubClassWithSubReg for X86.
There are fewer registers with sub_8bit sub-registers in 32-bit mode
than in 64-bit mode.  In 32-bit mode, sub_8bit behaves the same as
sub_8bit_hi.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141206 91177308-0d34-0410-b5e6-96231b3b80d8
9bb272c
Simplify EXTRACT_SUBREG emission.
EXTRACT_SUBREG is emitted as %dst = COPY %src:sub, so there is no need to
constrain the %dst register class.  RegisterCoalescer will apply the
necessary constraints if it decides to eliminate the COPY.

The %src register class does need to be constrained to something with
the right sub-registers, though.  This is currently done manually with
COPY_TO_REGCLASS nodes.  They can possibly be removed after this patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141207 91177308-0d34-0410-b5e6-96231b3b80d8
d2ed2d7
Revert 141203. InstCombine is looping on unit tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141209 91177308-0d34-0410-b5e6-96231b3b80d8
e2999b4
Re-commit 141203, but much more conservative.
Just pull the instruction name, but don't change the order of anything
else. That keeps --debug happy and non-crashing, but doesn't change
how the worklist gets built.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141210 91177308-0d34-0410-b5e6-96231b3b80d8
35d9da3
Remove unused DstSubIdx argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141214 91177308-0d34-0410-b5e6-96231b3b80d8
6e39290
Bill Wendling Fix comment to reflect the new EH stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141218 91177308-0d34-0410-b5e6-96231b3b80d8
2130ab0
Fixes PR11070 - assert in SCEV getConstantEvolvingPHIOperands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141219 91177308-0d34-0410-b5e6-96231b3b80d8
ef8a4c2
Fix sub-register operand verification.
PhysReg operands are not allowed to have sub-register indices at all.

For virtual registers with sub-reg indices, check that all registers in
the register class support the sub-reg index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141220 91177308-0d34-0410-b5e6-96231b3b80d8
b4a0221
Bill Wendling Small refactoring. Cache the FunctionInfo->MBB into a local variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141221 91177308-0d34-0410-b5e6-96231b3b80d8
6f50054
Bill Wendling Add an ivar that maps a landing pad's EH symbol to the call sites tha…
…t may jump

to the landing pad. This will be used by the back-end to generate the jump
tables for dispatching the arriving longjmp in sjlj eh.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141224 91177308-0d34-0410-b5e6-96231b3b80d8
84fb7dd
Bill Wendling Modify the mapping from landing pad to call sites to accept more than…
… one call

site.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141226 91177308-0d34-0410-b5e6-96231b3b80d8
30e6740
PR11061: Make simplifylibcalls fold strcmp("", x) correctly.
While I'm here, fix the related issue with strncmp, add some actual tests for strcmp and strncmp, and start using StringRef::compare for constant folding instead of using strcmp/strncmp so that the optimized IR isn't dependent on the host's implementation of strcmp.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141227 91177308-0d34-0410-b5e6-96231b3b80d8
7928608
greened Refactor Multiclass Def Processing
Move the code to instantiate a multiclass def, bind its arguments and
resolve its members into three helper functions.  These will be reused
to support a new kind of multiclass def: a multidef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141229 91177308-0d34-0410-b5e6-96231b3b80d8
e499a2d
greened Add Multidef Data Structures
Add a set of data structures and members analogous to those used for
multiclass defs.  These will represent a new kind of multiclass def: a
multidef.  The idea behind the multidef is to process a list of items
and create a def record for each one inside the enclosing multiclass.
This allows the user to dynamically create a set of defs based on the
contents of a list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141230 91177308-0d34-0410-b5e6-96231b3b80d8
bda579b
greened Lexer Support for Multidefs
Add keyword support for multidefs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141231 91177308-0d34-0410-b5e6-96231b3b80d8
b9c29ea
greened Parser Multidef Support
Add parser support to recognize multidefs.  No processing on the
multidef is done at this point.  The grammar is:

MultiDef = MULTIDEF ObjectName < Value, Declaration, Value > ObjectBody

The first Value must be resolveable to a list and the second Value
must be resolveable to an integer.  The Declaration is a temporary
value used as an iterator to refer to list items during processing.
It may be passed into the ObjectBody where it will be substituted with
the list value used to instantiate each def.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141232 91177308-0d34-0410-b5e6-96231b3b80d8
6da674c
greened Process Multidefs
Process each multidef declared in a multiclass.  Iterate through the
list and instantiate a def in the multiclass for each item, resolving
the list item to the temporary iterator (possibly) used in the
multidef ObjectBody.  We then process each generated def in the normal
way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141233 91177308-0d34-0410-b5e6-96231b3b80d8
a6d442e
greened Add a Multidef Test
Add a simple test for multidefs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141234 91177308-0d34-0410-b5e6-96231b3b80d8
e5d5cdf
greened Update Test for Multidefs
Update the MultiPat.td test to create some defs via multidefs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141235 91177308-0d34-0410-b5e6-96231b3b80d8
fd56d75
greened Document Multidefs
Provide documentation for multidefs, explaining in detail how they
work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141236 91177308-0d34-0410-b5e6-96231b3b80d8
112d959
greened Emacs Support for Multidefs
Add Emacs font-lock keyword support for multidefs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141237 91177308-0d34-0410-b5e6-96231b3b80d8
45e7266
greened Vim Support for Multidefs
Add vim highlighting support for multidefs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141238 91177308-0d34-0410-b5e6-96231b3b80d8
6494af4
greened Prefix Template Arg Names with Multiclass Name
For consistency, prefix multiclass template arg names with the
multiclass name followed by "::" to avoid name clashes among
multiclass arguments and other entities in the multiclass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141239 91177308-0d34-0410-b5e6-96231b3b80d8
caa25c8
greened Fix a typo.
Fix the argument passed in the multidef example.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141243 91177308-0d34-0410-b5e6-96231b3b80d8
4413b50
Bill Wendling Add accessor method to check if the landing pad symbol has call site …
…information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141244 91177308-0d34-0410-b5e6-96231b3b80d8
d3b56cb
Bill Wendling Get the proper call site numbers for the landing pads. Also remove a …
…magic

number (18) for the proper addressing mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141245 91177308-0d34-0410-b5e6-96231b3b80d8
5cbef19
Remove a check from ARM shifted operand isel helper methods, which we…
…re blocking

merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141247 91177308-0d34-0410-b5e6-96231b3b80d8
d78ebe1
Always merge profitable shifts on A9, not just when they have a singl…
…e use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141248 91177308-0d34-0410-b5e6-96231b3b80d8
8f8aa81
Oct 06, 2011
Remove the TRI::getSubRegisterRegClass() hook.
This restores my karma after I added TRI::getSubClassWithSubReg().

Register constraints are applied 'backwards'.  Starting from the
register class required by an instruction operand, the correct question
is: 'How can I constrain the super-register register class so all its
sub-registers satisfy the instruction constraint?' The
getMatchingSuperRegClass() hook answers that.

We never need to go 'forwards': Starting from a super-register register
class, what register class are the sub-registers in?  The
getSubRegisterRegClass() hook did that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141258 91177308-0d34-0410-b5e6-96231b3b80d8
d9c1fa5
Bill Wendling Add the MBBs before inserting the instructions. Doing it afterwards c…
…ould lead

to an infinite loop because of the def-use chains.

Also use a frame load instead of store for the LD instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141263 91177308-0d34-0410-b5e6-96231b3b80d8
930193c
pcc Build system infrastructure for multiple tblgens.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141266 91177308-0d34-0410-b5e6-96231b3b80d8
de8f33c
Cosmetic change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141269 91177308-0d34-0410-b5e6-96231b3b80d8
cf2adb9
Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90…
…. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8
7ea16b0
add more tests for the OCaml bindings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141283 91177308-0d34-0410-b5e6-96231b3b80d8
0e68e90
ocaml bindings: add llvm_ipo based on IPO.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141284 91177308-0d34-0410-b5e6-96231b3b80d8
624c5ed
C/OCaml API to retrieve struct name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141285 91177308-0d34-0410-b5e6-96231b3b80d8
c44943e
ocaml/C bindings: getmdstring, add num_op, get_op should work on meta…
…data too

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141286 91177308-0d34-0410-b5e6-96231b3b80d8
4f661ab
add binding to read icmp predicate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141287 91177308-0d34-0410-b5e6-96231b3b80d8
4917ec9
ocaml/C bindings: type->isSized()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141288 91177308-0d34-0410-b5e6-96231b3b80d8
ff12c99
Add uwtable, returnstwice and nonlazybind to the C bindings also.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141289 91177308-0d34-0410-b5e6-96231b3b80d8
6831b7c
Don't require C bindings opcode numbers to be kept in sync.
They are not in sync now, for example Bitcast would show up as LLVMCall.
So instead introduce 2 functions that map to and from the opcodes in the C
bindings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141290 91177308-0d34-0410-b5e6-96231b3b80d8
4df1557
pcc Remove the Clang tblgen backends from LLVM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141293 91177308-0d34-0410-b5e6-96231b3b80d8
6d1409d
pcc s/tblgen/llvm-tblgen/g in a few missed places, including the tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141294 91177308-0d34-0410-b5e6-96231b3b80d8
5d5c062
greened Fix Typo
Compare the entire keyword string.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141295 91177308-0d34-0410-b5e6-96231b3b80d8
c2d18f8
Benjamin Kramer Simplify code. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141299 91177308-0d34-0410-b5e6-96231b3b80d8
37d42af
Benjamin Kramer Use StringSwitch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141305 91177308-0d34-0410-b5e6-96231b3b80d8
ee57318
Justin Holewinski PTX: Implement signed division
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141306 91177308-0d34-0410-b5e6-96231b3b80d8
9a6eba6
Fix -asserts build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141313 91177308-0d34-0410-b5e6-96231b3b80d8
3ef1234
greened Make Test More Thorough
Check that all ADD patters are processed.

Add a SUB test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141314 91177308-0d34-0410-b5e6-96231b3b80d8
2f0722c
greened Fix List-of-List Processing
Fix VarListElementInit::resolveListElementReference to return a
partially resolved VarListElementInint in the case where full
resolution is not possible.  This allows TableGen to make forward
progress resolving certain complex list expressions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141315 91177308-0d34-0410-b5e6-96231b3b80d8
d2b9f20
Fix and clean up tests. Un-XFAIL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141316 91177308-0d34-0410-b5e6-96231b3b80d8
d6f8509
Bill Wendling * Set the low bit of the return address when we are in thumb mode.
* Some code cleanup.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141317 91177308-0d34-0410-b5e6-96231b3b80d8
04f15b4
Fix and clean up tests. Un-XFAIL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141318 91177308-0d34-0410-b5e6-96231b3b80d8
7abb795
Bill Wendling Use a thumb ORR instead of thumb2 ORR when in thumb-only mode. (Picky…
…! Picky!)

Place the immediate to OR into a register so that it works.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141319 91177308-0d34-0410-b5e6-96231b3b80d8
5e2cbc1
Tidy up tests. Un-XFAIL file and mark individual tests as FIXME instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141321 91177308-0d34-0410-b5e6-96231b3b80d8
bee5d2f
Bill Wendling Refactor some of the code that sets up the entry block for SjLj EH. N…
…o functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141323 91177308-0d34-0410-b5e6-96231b3b80d8
e29fa1d
Bill Wendling Generate the dispatch table for ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141327 91177308-0d34-0410-b5e6-96231b3b80d8
95ce2e9
Remove the old atomic instrinsics. autoupgrade functionality is inclu…
…ded with this patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141333 91177308-0d34-0410-b5e6-96231b3b80d8
8540101
resistor Fix the check for nested IT instructions in the disassembler. We need…
… to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141339 91177308-0d34-0410-b5e6-96231b3b80d8
7011eee
Bill Wendling Generate the dispatch code for a 'thumb' function. This is very simil…
…ar to the

others. They take the call site value. Determine if it's a proper value. And
then jumps to the correct call site via a jump table.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141341 91177308-0d34-0410-b5e6-96231b3b80d8
083a8eb
Bill Wendling Use the correct vreg here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141342 91177308-0d34-0410-b5e6-96231b3b80d8
217f0e9
Oct 07, 2011
Revert part of r141274. Only need to change encoding for xchg %eax, %…
…eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141353 91177308-0d34-0410-b5e6-96231b3b80d8
25f6dfd
Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141354 91177308-0d34-0410-b5e6-96231b3b80d8
1b526a9
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141356 91177308-0d34-0410-b5e6-96231b3b80d8
4563bba
PostRA scheduler fix. Clear stale loop dependencies.
Fixes <rdar://problem/10235725>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141357 91177308-0d34-0410-b5e6-96231b3b80d8
e8deca8
Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WR…
…GSBASE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141358 91177308-0d34-0410-b5e6-96231b3b80d8
75fe5f3
CunningBaldrick Teach GVN to also propagate switch cases. For example, in this code
  switch (n) {
    case 27:
      do_something(x);
    ...
  }
the call do_something(x) will be replaced with do_something(27).  In
gcc-as-one-big-file this results in the removal of about 500 lines of
bitcode (about 0.02%), so has about 1/10 of the effect of propagating
branch conditions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141360 91177308-0d34-0410-b5e6-96231b3b80d8
3f329cb
Anton Korobeynikov Peephole optimization for ABS on ARM.
Patch by Ana Pazos!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141365 91177308-0d34-0410-b5e6-96231b3b80d8
244455e
Move default to top of switch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141366 91177308-0d34-0410-b5e6-96231b3b80d8
7761948
Reenable use of divmod compiler_rt functions for iOS 5.0 and later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141368 91177308-0d34-0410-b5e6-96231b3b80d8
2fef457
Reenable tail calls for iOS 5.0 and later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141370 91177308-0d34-0410-b5e6-96231b3b80d8
6d2f9ce
High bits of movmskp{s|d} and pmovmskb are known zero. rdar://10247336
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141371 91177308-0d34-0410-b5e6-96231b3b80d8
7c1780c
Jakob is the code owner of register allocation and TableGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141372 91177308-0d34-0410-b5e6-96231b3b80d8
b767613
Michael Spencer Change relocation API to be per section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141376 91177308-0d34-0410-b5e6-96231b3b80d8
f1164a2
Michael Spencer Fix spelling in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141377 91177308-0d34-0410-b5e6-96231b3b80d8
67370ef
greened Remove Multidefs
Multidefs are a bit unwieldy and incomplete.  Remove them in favor of
another mechanism, probably for loops.

Revert "Make Test More Thorough"
Revert "Fix a typo."
Revert "Vim Support for Multidefs"
Revert "Emacs Support for Multidefs"
Revert "Document Multidefs"
Revert "Add a Multidef Test"
Revert "Update Test for Multidefs"
Revert "Process Multidefs"
Revert "Parser Multidef Support"
Revert "Lexer Support for Multidefs"
Revert "Add Multidef Data Structures"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141378 91177308-0d34-0410-b5e6-96231b3b80d8
a1b1b79
Bill Wendling Revert 141376 and 141377 due to breaking the build.
--- Reverse-merging r141377 into '.':
U    tools/llvm-objdump/MachODump.cpp
--- Reverse-merging r141376 into '.':
U    include/llvm/Object/COFF.h
U    include/llvm/Object/ObjectFile.h
U    include/llvm-c/Object.h
U    tools/llvm-objdump/llvm-objdump.cpp
U    lib/Object/MachOObjectFile.cpp
U    lib/Object/COFFObjectFile.cpp
U    lib/Object/Object.cpp
U    lib/Object/ELFObjectFile.cpp



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141379 91177308-0d34-0410-b5e6-96231b3b80d8
a48ad13
Improve ARM assembly parser diagnostic for unexpected tokens.
Consider:
  mov r8, r11 fred

Previously, we issued the not very informative:
x.s:6:1: error: unexpected token in argument list

^

Now we generate:
x.s:5:14: error: unexpected token in argument list
  mov r8, r11 fred
              ^


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141380 91177308-0d34-0410-b5e6-96231b3b80d8
186ffac
jpbonn Merge branch 'master' of http://llvm.org/git/llvm c3b0a3f
jpbonn Updated CMakeList to match latest LLVM. d1600ca