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base fork: m-labs/llvm-lm32
base: 5b9fac4
...
head fork: m-labs/llvm-lm32
compare: f1db207
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Commits on Jul 28, 2011
Jakub Staszak Add InEdges (edges from header to the loop) in Loop Branch Heuristics…
…, so

there is no frequency difference whether condition is in the header or in
the latch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136398 91177308-0d34-0410-b5e6-96231b3b80d8
fa44725
Jim Grosbach ARM assembly parsing and encoding for BFC and BFI.
Add parsing support that handles converting the lsb+width source into the
odd way we represent the instruction (an inverted bitfield mask).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136399 91177308-0d34-0410-b5e6-96231b3b80d8
293a2ee
Jim Grosbach Remove obsolete FIXME reference in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136400 91177308-0d34-0410-b5e6-96231b3b80d8
43afb6f
Jakob Stoklund Olesen Handle REG_SEQUENCE with implicitly defined operands.
Code like that would only be produced by bugpoint, but we should still
handle it correctly.

When a register is defined by a REG_SEQUENCE of undefs, the register
itself is undef. Previously, we would create a register with uses but no
defs.

Fixes part of PR10520.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136401 91177308-0d34-0410-b5e6-96231b3b80d8
f6c6900
Jakub Staszak Heuristics are in descending priority now. If we use one of them, ski…
…p the rest.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136402 91177308-0d34-0410-b5e6-96231b3b80d8
7241caf
Jakub Staszak If run with -debug give more information about Cyclic Probability.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136403 91177308-0d34-0410-b5e6-96231b3b80d8
7f1cce5
Eli Friedman LangRef and basic memory-representation/reading/writing for 'cmpxchg'…
… and

'atomicrmw' instructions, which allow representing all the current atomic
rmw intrinsics.

The allowed operands for these instructions are heavily restricted at the
moment; we can probably loosen it a bit, but supporting general
first-class types (where it makes sense) might get a bit complicated,
given how SelectionDAG works.

As an initial cut, these operations do not support specifying an alignment,
but it would be possible to add if we think it's useful. Specifying an
alignment lower than the natural alignment would be essentially
impossible to support on anything other than x86, but specifying a greater
alignment would be possible.  I can't think of any useful optimizations which
would use that information, but maybe someone else has ideas.

Optimizer/codegen support coming soon.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136404 91177308-0d34-0410-b5e6-96231b3b80d8
ff03048
@resistor resistor Enhance the fixed-length decoder emitter to support parsing scattered…
… fields.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136405 91177308-0d34-0410-b5e6-96231b3b80d8
d1e38df
Jim Grosbach ARM assembly parsing and encoding for BLX (immediate).
Add parsing support for BLX (immediate). Since the register operand version is
predicated and the label operand version is not, we have to use some special
handling to get the operand list right for matching.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136406 91177308-0d34-0410-b5e6-96231b3b80d8
cf121c3
Jim Grosbach CBZ/CBNZ are Thumb2 only. No need for ARM mode tests for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136408 91177308-0d34-0410-b5e6-96231b3b80d8
c5b3c58
Jim Grosbach PLD and PLI are not predicable in ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136427 91177308-0d34-0410-b5e6-96231b3b80d8
48c693f
Jakub Staszak Change LBH_TAKEN_WEIGHT to 124 (from 128). Right now, sum of
LBH_TAKEN_WEIGHT + LBH_NONTAKEN_WEIGHT = 128 which in _most_ cases reduce
number of rounding errors.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136428 91177308-0d34-0410-b5e6-96231b3b80d8
3d8b15e
@isanbard isanbard Add the AddLandingPadInfo function.
AddLandingPadInfo takes a landingpad instruction and grabs all of the
information from it that it needs for EH table generation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136429 91177308-0d34-0410-b5e6-96231b3b80d8
e963a38
@isanbard isanbard Visit the landingpad instruction.
This generates the correct SDNodes for the landingpad instruction. It makes an
assumption that the result of the landingpad instruction has at least two
values. And that the first value is a pointer to the exception object and the
second value is the "selector."


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136430 91177308-0d34-0410-b5e6-96231b3b80d8
3678537
@resistor resistor Enhance the fixed-length decoder emitter to support tied operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136431 91177308-0d34-0410-b5e6-96231b3b80d8
00ef6e3
Commits on Jul 29, 2011
Jakub Staszak Remove extra semicolon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136432 91177308-0d34-0410-b5e6-96231b3b80d8
00eab6c
@chandlerc chandlerc Rewrite the CMake build to use explicit dependencies between libraries,
specified in the same file that the library itself is created. This is
more idiomatic for CMake builds, and also allows us to correctly specify
dependencies that are missed due to bugs in the GenLibDeps perl script,
or change from compiler to compiler. On Linux, this returns CMake to
a place where it can relably rebuild several targets of LLVM.

I have tried not to change the dependencies from the ones in the current
auto-generated file. The only places I've really diverged are in places
where I was seeing link failures, and added a dependency. The goal of
this patch is not to start changing the dependencies, merely to move
them into the correct location, and an explicit form that we can control
and change when necessary.

This also removes a serialization point in the build because we don't
have to scan all the libraries before we begin building various tools.
We no longer have a step of the build that regenerates a file inside the
source tree. A few other associated cleanups fall out of this.

This isn't really finished yet though. After talking to dgregor he urged
switching to a single CMake macro to construct libraries with both
sources and dependencies in the arguments. Migrating from the two macros
to that style will be a follow-up patch.

Also, llvm-config is still generated with GenLibDeps.pl, which means it
still has slightly buggy dependencies. The internal CMake
'llvm-config-like' macro uses the correct explicitly specified
dependencies however. A future patch will switch llvm-config generation
(when using CMake) to be based on these deps as well.

This may well break Windows. I'm getting a machine set up now to dig
into any failures there. If anyone can chime in with problems they see
or ideas of how to solve them for Windows, much appreciated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136433 91177308-0d34-0410-b5e6-96231b3b80d8
ac03e73
Eli Friedman Make sure to correctly clear the exact/nuw/nsw flags off of shifts wh…
…en they are combined together. <rdar://problem/9859829>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136435 91177308-0d34-0410-b5e6-96231b3b80d8
ef71597
Jakob Stoklund Olesen Add -verify-arm-pseudo-expand.
This hidden llc option runs the machine code verifier after expanding
ARM pseudo-instructions, but before if-conversion.

The machine code verifier is much better at pointing out liveness errors
that can trip up the register scavenger.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136439 91177308-0d34-0410-b5e6-96231b3b80d8
e69438f
Jakob Stoklund Olesen Transfer implicit operands in NEONMoveFixPass.
Later passes /are/ using this information when running the register
scavenger.

This fixes the second problem in PR10520.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136440 91177308-0d34-0410-b5e6-96231b3b80d8
fe42808
@isanbard isanbard Make sure to sext or trunc the result from the register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136444 91177308-0d34-0410-b5e6-96231b3b80d8
744b4bd
@isanbard isanbard And now something that compiles...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136445 91177308-0d34-0410-b5e6-96231b3b80d8
7d44c45
@isanbard isanbard Use the pointer type size.
With this, we can now compile a simple EH program.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136446 91177308-0d34-0410-b5e6-96231b3b80d8
741bf79
@bcardosolopes bcardosolopes Cleanup PALIGNR handling and remove the old palign pattern fragment.
Also make PALIGNR masks to don't match 256-bits, which isn't supported
It's also a step to solve PR10489

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136448 91177308-0d34-0410-b5e6-96231b3b80d8
9065d4b
@bcardosolopes bcardosolopes Enable usage of SSE4 extracts and inserts in their 128-bit AVX forms.
Also tidy up code a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136449 91177308-0d34-0410-b5e6-96231b3b80d8
0b0a09f
@bcardosolopes bcardosolopes Fix a bug while generating target specific VPERMIL masks: skip
undef mask elements. This fixes PR10529.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136450 91177308-0d34-0410-b5e6-96231b3b80d8
377baa5
@bcardosolopes bcardosolopes Add v8i32 and v4i64 vpermil patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136451 91177308-0d34-0410-b5e6-96231b3b80d8
e89c7d4
@bcardosolopes bcardosolopes Add DecodeShuffle shuffle support for VPERMIPD variantes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136452 91177308-0d34-0410-b5e6-96231b3b80d8
2eb4c2b
@bcardosolopes bcardosolopes Match VPERMIL masks more strictly and update the target specific mask
generation to always catch the weird cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136453 91177308-0d34-0410-b5e6-96231b3b80d8
dd63530
@bcardosolopes bcardosolopes Fix two tests that I crashed in the previous commits. The mask elts
on the second half must be reindexed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136454 91177308-0d34-0410-b5e6-96231b3b80d8
6126005
@chandlerc chandlerc Fix the MCDisassembler dependencies. These were just absurdly wrong.
First off, only depend on the actual MC-ized disassemblers in the
targets, not all of the libraries those in turn depend on.

Second off, only depend on those MC-ized disassemblers for targets we're
building.

This should fix builds of fewer than all targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136455 91177308-0d34-0410-b5e6-96231b3b80d8
7ad75f6
Jakub Staszak Remove incEdgeWeight and decEdgeWeight. Set edge weight directly to a…
…void

rounding errors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136456 91177308-0d34-0410-b5e6-96231b3b80d8
e0058b4
Eli Friedman Misc optimizer+codegen work for 'cmpxchg' and 'atomicrmw'. They appea…
…r to be

working on x86 (at least for trivial testcases); other architectures will
need more work so that they actually emit the appropriate instructions for
orderings stricter than 'monotonic'. (As far as I can tell, the ARM, PPC,
Mips, and Alpha backends need such changes.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136457 91177308-0d34-0410-b5e6-96231b3b80d8
55ba816
@nlewycky nlewycky Fix a lot of typos, improve (but not necessarily fix) grammaros and r…
…eflow some

lines. No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136458 91177308-0d34-0410-b5e6-96231b3b80d8
3bbb6f7
@nlewycky nlewycky Teach Path::GetCurrentDirectory to use $PWD, to support users who lik…
…e to do

screwy things by setting PWD != getcwd(). For example, some developers I know
will use this to control the value in gcc's DW_AT_comp_dir value in debug
output. With this patch, that trick will now work on clang too.

The only other effect of this change is that the static analysis will now
respect $PWD when reporting the directory of the files in its HTML output. I
think that's fine.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136459 91177308-0d34-0410-b5e6-96231b3b80d8
3c036e5
@CunningBaldrick CunningBaldrick Avoid undefined behaviour if somehow NUM_GRAPHS equals 2^32 (or
whatever the size of unsigned is), though this can't actually
occur for any integer value of NUM_NODES.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136460 91177308-0d34-0410-b5e6-96231b3b80d8
6815ff0
Douglas Gregor Switch the CMake edis build over to add_llvm_library_dependencies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136463 91177308-0d34-0410-b5e6-96231b3b80d8
3401a90
@resistor resistor Fix a case where, when trying to track tied operands, we'd accidental…
…ly overwrite our mapping.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136467 91177308-0d34-0410-b5e6-96231b3b80d8
d217da1
Jim Grosbach Tweak comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136468 91177308-0d34-0410-b5e6-96231b3b80d8
bd4562e
Jim Grosbach Update FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136470 91177308-0d34-0410-b5e6-96231b3b80d8
96e24fa
Jim Grosbach ARM update tests for CPS instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136472 91177308-0d34-0410-b5e6-96231b3b80d8
71d3d67
Jim Grosbach ARM range checking for mode on CPS instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136473 91177308-0d34-0410-b5e6-96231b3b80d8
b48ce90
Jim Grosbach ARM SRS and RFE instructions are not code-gen only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136475 91177308-0d34-0410-b5e6-96231b3b80d8
5a28748
@nlewycky nlewycky Don't look at $PWD in GetCurrentDirectory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136477 91177308-0d34-0410-b5e6-96231b3b80d8
2b9c507
@resistor resistor Third time's the charm for implementing tied operand decoding properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136478 91177308-0d34-0410-b5e6-96231b3b80d8
ea24298
Jim Grosbach ARM assembly parsing and encoding for RFE instruction.
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136479 91177308-0d34-0410-b5e6-96231b3b80d8
2c6363a
Devang Patel Clean up debug info after reassociation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136480 91177308-0d34-0410-b5e6-96231b3b80d8
1619560
@greened greened Add a std::string Wrapper for TableGen
Create a std::string wrapper for use as a DenseMap key.  DenseMap is
not safe in generate with strings, so this wrapper indicates that only
strings guaranteed not to have certain values should be used in the
DenseMap.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136481 91177308-0d34-0410-b5e6-96231b3b80d8
cd0bc90
@greened greened Add ListInit::getValues
Add a getValues ListInit method to return the sequence of values in
the list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136482 91177308-0d34-0410-b5e6-96231b3b80d8
c45a2ca
@greened greened [AVX] Remove Mutating Members from Inits
Get rid of all Init members that modify internal state.  This is in
preparation for making references to Inits const.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136483 91177308-0d34-0410-b5e6-96231b3b80d8
ca7fd3d
@greened greened [AVX] Remove non-const Iterators
Remove all non-const iterators from Init classes.  This is another
step toward constifying Inits and ultimately turning them into
FoldingSetNodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136484 91177308-0d34-0410-b5e6-96231b3b80d8
60c04af
@greened greened [AVX] Constify Inits
Make references to Inits const everywhere.  This is the final step
before making them unique.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136485 91177308-0d34-0410-b5e6-96231b3b80d8
f37dd02
@greened greened [AVX] Create Inits Via Factory Method
Replace uses of new *Init with *Init::get.  This hides the allocation
implementation so that we can unique Inits in various ways.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136486 91177308-0d34-0410-b5e6-96231b3b80d8
dcd35c7
@greened greened [AVX] Unique UnsetInit
Keep only one UnsetInit around.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136487 91177308-0d34-0410-b5e6-96231b3b80d8
ba1ae18
@greened greened [AVX] Unique BitInit
Keep only two copies of BitInit: one for true and one for false.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136488 91177308-0d34-0410-b5e6-96231b3b80d8
0ffd167
@greened greened [AVX] Make BitsInit Unique
Make BitsInit a FoldingSetNode so we can unique it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136489 91177308-0d34-0410-b5e6-96231b3b80d8
726bbde
@greened greened [AVX] Make IntInit Unique
Use a DenseMap to make sure only one IntInit of any value exists.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136490 91177308-0d34-0410-b5e6-96231b3b80d8
2855b0f
@greened greened [AVX] Make StringInit Unique
Use a StringMap to ensure the StringInits are unique.  This is
especially important for AVX where we will have many smallish
strings representing instruction prefixes, suffixes and the like.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136491 91177308-0d34-0410-b5e6-96231b3b80d8
d0e9d04
@greened greened [AVX] Make CodeInit Unique
Use a StringMap to ensure CodeInits are unique and created only
once.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136492 91177308-0d34-0410-b5e6-96231b3b80d8
637b4ff
@greened greened [AVX] Make ListInits Unique
Ensure ListInits are unique and only created once.  This will be
important for AVX as lists will be used extensively to pass generic
patterns, prefix information and other things to lower-level
pattern-generation classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136493 91177308-0d34-0410-b5e6-96231b3b80d8
aad4c9f
@greened greened [AVX] Make UnOpInit Unique
Make sure UnOpInits are unique and created only once.  This will be
important for AVX/SIMD as many operators will be used to generate
patterns and other relevant data.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136494 91177308-0d34-0410-b5e6-96231b3b80d8
6f03b63
@greened greened [AVX] Make BinOpInit Unique
Make sure BinOpInits are unique and created only once.  This will be
important for AVX/SIMD as many operators will be used to generate
patterns and other relevant data.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136495 91177308-0d34-0410-b5e6-96231b3b80d8
65a5b8c
@greened greened [AVX] Make TernOpInit Unique
Make sure TernOpInits are unique and created only once.  This will be
important for AVX/SIMD as many operators will be used to generate
patterns and other relevant data.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136496 91177308-0d34-0410-b5e6-96231b3b80d8
b76a1e6
@greened greened [AVX] Make VarInit Unique
Make sure VarInits are unique and created only once.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136497 91177308-0d34-0410-b5e6-96231b3b80d8
e0be0e3
@greened greened [AVX] Make VarBitInit Unique
Make sure VarBitInits are unique and created only once.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136498 91177308-0d34-0410-b5e6-96231b3b80d8
aa839b8
@greened greened [AVX] Make VarListElementInit Unique
Make sure VarListElementInits are unique and created only once.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136499 91177308-0d34-0410-b5e6-96231b3b80d8
08f71e3
@greened greened [AVX] Make FieldInit Unique
Make sure FieldInits are unique and created only once.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136500 91177308-0d34-0410-b5e6-96231b3b80d8
65bf3ca
@greened greened [AVX] Make DagInits Unique
Make sure DagInits are unique and created only once.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136501 91177308-0d34-0410-b5e6-96231b3b80d8
78621a8
Jakub Staszak Add more constantness in BranchProbabilityInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136502 91177308-0d34-0410-b5e6-96231b3b80d8
6f6baf1
Devang Patel Clear DbgValues in the end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136503 91177308-0d34-0410-b5e6-96231b3b80d8
6e8bb8a
Jim Grosbach ARM CPS mode immediate is 5 bits, not 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136505 91177308-0d34-0410-b5e6-96231b3b80d8
33768db
Jakub Staszak Remove unneeded const_cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136506 91177308-0d34-0410-b5e6-96231b3b80d8
95ece8e
@chandlerc chandlerc On mac, it seems the MC disassembler is actually using the targetinfo
for targets that don't have an MC-ized disassembler. I'm suspicious that
this shouldn't actually be happening, but hoping to fix the CMake build
on macs first, and investigate why second.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136508 91177308-0d34-0410-b5e6-96231b3b80d8
c91d626
Jim Grosbach ARM SRS instruction parsing, diassembly and encoding support.
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136509 91177308-0d34-0410-b5e6-96231b3b80d8
e1cf590
Chris Lattner have the verifier catch gep's into opaque struct types. PR10473
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136510 91177308-0d34-0410-b5e6-96231b3b80d8
4cea5ba
@greened greened Remove a blank line from the top.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136511 91177308-0d34-0410-b5e6-96231b3b80d8
b4f4cbd
Eric Christopher Add support for the 'Q' constraint.
Fixes rdar://9866494


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136523 91177308-0d34-0410-b5e6-96231b3b80d8
ef7f1e7
Jakob Stoklund Olesen Enable compact region splitting by default.
This helps generate better code in functions with high register
pressure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136528 91177308-0d34-0410-b5e6-96231b3b80d8
9162abb
Jakub Staszak Do not lose branch weights when lowering SwitchInst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136529 91177308-0d34-0410-b5e6-96231b3b80d8
c8f34de
@greened greened Unconstify Inits
Remove const qualifiers from Init references, per Chris' request.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136531 91177308-0d34-0410-b5e6-96231b3b80d8
05bce0b
Jakob Stoklund Olesen Add an isSSA() flag to MachineRegisterInfo.
This flag is true from isel to register allocation when the machine
function is required to be in SSA form.  The TwoAddressInstructionPass
and PHIElimination passes clear the flag.

The SSA flag wil be used by the machine code verifier to check for SSA
form, and eventually an assertion can enforce it in +Asserts builds.
This will catch the common target error of creating machine code with
multiple defs of a virtual register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136532 91177308-0d34-0410-b5e6-96231b3b80d8
73e7dce
@resistor resistor Correctly handle scattered operands where the bits of the operand are…
… contiguous, but out of order.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136534 91177308-0d34-0410-b5e6-96231b3b80d8
eb809f5
Jakob Stoklund Olesen Check for multiple defs in the machine code verifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136535 91177308-0d34-0410-b5e6-96231b3b80d8
93e6f02
Jakob Stoklund Olesen Don't check liveness of unallocatable registers.
This includes registers like EFLAGS and ST0-ST7. We don't check for
liveness issues in the verifier and scavenger because registers will
never be allocated from these classes.

While in SSA form, we do care about the liveness of unallocatable
unreserved registers. Liveness of EFLAGS and ST0 neds to be correct for
MachineDCE and MachineSinking.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136541 91177308-0d34-0410-b5e6-96231b3b80d8
eeb57c7
@chandlerc chandlerc Make my attempt to build up global deps variables actually utilize
globally scoped constructs. Also, round-trip these dependencies through
the LLVMConfig.cmake.in file thata is used by CMake-based clients of
"installed" (or built) LLVM trees.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136543 91177308-0d34-0410-b5e6-96231b3b80d8
2e1513d
Commits on Jul 30, 2011
Jakob Stoklund Olesen Revert "Don't check liveness of unallocatable registers."
The ARM target depends on CPSR liveness being tracked after register
allocation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136548 91177308-0d34-0410-b5e6-96231b3b80d8
4af0f5f
Sean Callanan Added several architecture names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136552 91177308-0d34-0410-b5e6-96231b3b80d8
efd7919
@isanbard isanbard Revert r136253, r136263, r136269, r136313, r136325, r136326, r136329,…
… r136338,

r136339, r136341, r136369, r136387, r136392, r136396, r136429, r136430, r136444,
r136445, r136446, r136253 pending review.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136556 91177308-0d34-0410-b5e6-96231b3b80d8
10c6d12
@chandlerc chandlerc Remove yet another buried and hidden implicit dependency: every single
sub-library for the targets depended on the core target CodeGen library.
This completely undermined the careful work to separate the those
libraries, especially the MC-layer ones. This surfaced as circular
dependencies when the libraries were built as shared libraries where
CMake doesn't allow cycles.

This should fix PR10537. I'll watch the bots to see if there is fallout
on other platforms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136565 91177308-0d34-0410-b5e6-96231b3b80d8
c58247d
@chandlerc chandlerc Switch another of the old dependencies on implicitly produced synthetic
rules to the new explicitly listed TableGen rules. Somehow I missed this
in my original sweep.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136567 91177308-0d34-0410-b5e6-96231b3b80d8
61377a1
Jakob Stoklund Olesen Revert r136528 "Enable compact region splitting by default."
While this generally helped x86-64, there was some large regressions
for i386.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136571 91177308-0d34-0410-b5e6-96231b3b80d8
21384c4
Commits on Jul 31, 2011
@d0k d0k Remove InvalidateStructLayoutInfo from the ocaml bindings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136582 91177308-0d34-0410-b5e6-96231b3b80d8
e2721f7
Jakub Staszak Add Zero Heurestics to BranchProbabilityInfo. If we compare value to …
…zero we

decide whether condition is likely to be true this way:

x == 0  ->  false
x <  0  ->  false
x <= 0  ->  false
x != 0  ->  true
x >  0  ->  true
x >= 0  ->  true


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136583 91177308-0d34-0410-b5e6-96231b3b80d8
a5dd550
Jakob Stoklund Olesen Time the emission of debug values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136584 91177308-0d34-0410-b5e6-96231b3b80d8
c476902
@espindola espindola Add a small gep optimization I noticed was missing while reading some…
… IL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136585 91177308-0d34-0410-b5e6-96231b3b80d8
592ad6a
Jakub Staszak Do not handle case where LHS is equal to zero, because InstCombiner a…
…lways moves

it to RHS anyway.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136586 91177308-0d34-0410-b5e6-96231b3b80d8
a385c20
Jakub Staszak Remove untrue comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136587 91177308-0d34-0410-b5e6-96231b3b80d8
4faf553
Jakub Staszak Do not handle cases with >= and <= predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136588 91177308-0d34-0410-b5e6-96231b3b80d8
6762dc1
@isanbard isanbard Add the 'resume' instruction for the new EH rewrite.
This adds the 'resume' instruction class, IR parsing, and bitcode reading and
writing. The 'resume' instruction resumes propagation of an existing (in-flight)
exception whose unwinding was interrupted with a 'landingpad' instruction (to be
added later).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136589 91177308-0d34-0410-b5e6-96231b3b80d8
dccc03b
@isanbard isanbard Fix some validation errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136590 91177308-0d34-0410-b5e6-96231b3b80d8
0246bb7
@isanbard isanbard Fix some validation errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136591 91177308-0d34-0410-b5e6-96231b3b80d8
af75f0c
@chandlerc chandlerc I mis-interpreted the MCDisassembler's intended dependencies. Now to fix
them properly. Specifically, the disassembler clearly attempts to
initialiaze all TargetInfo, MCTargeDesc, AsmParser, and Disassembler
sublibraries of registered targets. This makes the CMakeLists accurately
reflect this intent in the code.

This should fix the last of the link errors that I have gotten reports
of on OS X, but if anyone continues to see link errors, continue to
pester me and I'll look into it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136603 91177308-0d34-0410-b5e6-96231b3b80d8
8733409
Commits on Aug 01, 2011
@jayfoad jayfoad The operands of a GlobalAlias are always Constants. Simplify things
accordingly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136608 91177308-0d34-0410-b5e6-96231b3b80d8
4f2d695
@jayfoad jayfoad Remove an unnecessary cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136609 91177308-0d34-0410-b5e6-96231b3b80d8
b899d95
@jayfoad jayfoad Micro-optimisation in getAliasedGlobal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136610 91177308-0d34-0410-b5e6-96231b3b80d8
4255274
@jayfoad jayfoad Simplify printAlias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136611 91177308-0d34-0410-b5e6-96231b3b80d8
8d94865
@jayfoad jayfoad Add braces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136612 91177308-0d34-0410-b5e6-96231b3b80d8
5cd8ea2
Jakub Staszak Add BlockFrequency::getEntryFrequency()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136618 91177308-0d34-0410-b5e6-96231b3b80d8
e2481ff
Douglas Gregor Update CMake target names for tablegen-generated data in the X86 and …
…ARM targets. This should fix the CMake build with MSVC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136621 91177308-0d34-0410-b5e6-96231b3b80d8
32ab312
@rlsosborne rlsosborne Fix crash with varargs function with no named parameters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136623 91177308-0d34-0410-b5e6-96231b3b80d8
965b891
@resistor resistor Add a clear() operation to MCInst, to drop all of its operands. Usefu…
…l for the disassembler, where we may realize fairly late into decoding that something is wrong and need to reset.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136634 91177308-0d34-0410-b5e6-96231b3b80d8
423b81e
@resistor resistor Enhance the fixed length disassembler to better handle operand decodi…
…ng failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136635 91177308-0d34-0410-b5e6-96231b3b80d8
7f76bae
Jakub Staszak Change SmallVector to SmallPtrSet in BranchProbabilityInfo. Handle ca…
…ses where

one than one successor goes to the same block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136638 91177308-0d34-0410-b5e6-96231b3b80d8
b137f16
Evan Cheng Set endianess and pointer size for PPC Linux. Bug noticed by Roman Di…
…vacky.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136639 91177308-0d34-0410-b5e6-96231b3b80d8
8ead80d
@bcardosolopes bcardosolopes Since vectors with all ones can't be created with a 256-bit instruction,
avoid returning early for v8i32 types, which would only be valid for
vector with all zeros. Also split the handling of zeros and ones into separate
checking logic since they are handled differently. This fixes PR10547

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136642 91177308-0d34-0410-b5e6-96231b3b80d8
531f19f
@chandlerc chandlerc Actually finish switching to the new system for Target sublibrary
TableGen deps introduced in r136023. This completes the fixing that
dgregor started in r136621. Sorry for missing these the first time
around.

This should fix some of the random race-condition failures people are
still seeing with CMake.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136643 91177308-0d34-0410-b5e6-96231b3b80d8
81fd0ba
@resistor resistor The FixedLenDecoder needs to gracefully handle failing per-instructio…
…n decoder hooks in addition to per-operand decoder hooks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136645 91177308-0d34-0410-b5e6-96231b3b80d8
5f801ba
@rdivacky rdivacky Fix a typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136646 91177308-0d34-0410-b5e6-96231b3b80d8
4d7ce32
@bcardosolopes bcardosolopes Lower CONCAT_VECTORS to use two VINSERTF128 instructions instead of
using a stack store.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136652 91177308-0d34-0410-b5e6-96231b3b80d8
8af2451
@bcardosolopes bcardosolopes Teach PreprocessISelDAG to be aware of vector types and to not proces…
…s them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136653 91177308-0d34-0410-b5e6-96231b3b80d8
aed890b
@bcardosolopes bcardosolopes Add v4f64 -> v2f32 fp_round support. Also add a testcase to exercise
the legalizer. This commit together with the two previous ones fixes
PR10495.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136654 91177308-0d34-0410-b5e6-96231b3b80d8
55244ce
Jim Grosbach Fix comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136655 91177308-0d34-0410-b5e6-96231b3b80d8
b2756af
Jim Grosbach Move imm0_255 to ARMInstrInfo.td with the other immediate predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136656 91177308-0d34-0410-b5e6-96231b3b80d8
02c8460
@resistor resistor Make the FixedLengthDecoderEmitter smart enough to autogenerate decod…
…ers for encodings like "let Inst{11-7} = foo;", where the RHS has no bitwidth specifiers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136660 91177308-0d34-0410-b5e6-96231b3b80d8
cf60395
Commits on Aug 02, 2011
@nlewycky nlewycky Bail from FastISel when we encounter a volatile memset intrinsic. Pat…
…ch by Ivan

Krasin!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136663 91177308-0d34-0410-b5e6-96231b3b80d8
3207c9a
Eli Friedman Fix a couple silly typos in IRBuilder in the new atomic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136665 91177308-0d34-0410-b5e6-96231b3b80d8
9b0a479
Eli Friedman Minor wording tweak for memory model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136668 91177308-0d34-0410-b5e6-96231b3b80d8
101c81d
@rjmccall rjmccall I am the code owner for Clang's IR generation; this has been true
for awhile, but it's good to make this official.  

Just to be clear, Doug and Ted "elected" me to this position.

Might as well add myself to the credits list while I'm at it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136673 91177308-0d34-0410-b5e6-96231b3b80d8
74699fd
@resistor resistor Revert r136503 and r136480 in an effort to fix non-determinism in the…
… llvm-gcc buildbots on i386. Devang is looking into the root cause.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136674 91177308-0d34-0410-b5e6-96231b3b80d8
9b7fdc7
@d0k d0k Remove empty test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136675 91177308-0d34-0410-b5e6-96231b3b80d8
7a3824b
Andrew Trick Use consistent terminology for loop exit/exiting blocks. Name change …
…only.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136677 91177308-0d34-0410-b5e6-96231b3b80d8
fcb4356
@isanbard isanbard Remove the LLVMBuildUnwind C API function.
The 'unwind' function is going away with the new EH rewrite. This is step 0 in
keeping front-ends from using it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136683 91177308-0d34-0410-b5e6-96231b3b80d8
1600525
@isanbard isanbard Duncan's english is better than mine. :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136684 91177308-0d34-0410-b5e6-96231b3b80d8
086da7e
@rdivacky rdivacky Sketch out PowerPC ELF writer. This is enough to get clang -integrate…
…d-as

to compile a working hello world on FreeBSD/PPC32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136689 91177308-0d34-0410-b5e6-96231b3b80d8
2c0d69f
@rdivacky rdivacky Remove trailing semicolon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136690 91177308-0d34-0410-b5e6-96231b3b80d8
29630ff
@bcardosolopes bcardosolopes Make this kind of lowering to be supported by 256-bit instructions:
  shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
To:
  shuffle (vload ptr)), undef, <1, 1, 1, 1>
Fix PR10494

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136691 91177308-0d34-0410-b5e6-96231b3b80d8
ac5f13f
@rdivacky rdivacky Comment out the PPC relocation offset adjustment. It must be done dif…
…ferently.

This unbreaks some tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136692 91177308-0d34-0410-b5e6-96231b3b80d8
c9c0cc1
Jim Grosbach ARM: rename addrmode7 to addr_offset_none.
Use a more descriptive name so the code is more self-documenting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136704 91177308-0d34-0410-b5e6-96231b3b80d8
e39389a
Jim Grosbach Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136705 91177308-0d34-0410-b5e6-96231b3b80d8
b93509d
@resistor resistor Fix the broken encodings for the VFP vmov.f32 and vmov.f64 instructio…
…ns, as well as the comments that explain them incorrectly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136707 91177308-0d34-0410-b5e6-96231b3b80d8
96279d0
Eli Friedman Don't create a ridiculous EXTRACT_ELEMENT. PR10563.
The testcase looks extremely fragile, so I'm adding an assertion which should catch any cases like this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136711 91177308-0d34-0410-b5e6-96231b3b80d8
6cdc1f4
@espindola espindola Assume .cfi_startproc is the first thing in a function. If the functi…
…on is

externally visable, create a local symbol to use in the CFE. If not, use the
function label itself.

Fixes PR10420.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136716 91177308-0d34-0410-b5e6-96231b3b80d8
49cb9b8
Chris Lattner no need to count the terminators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136718 91177308-0d34-0410-b5e6-96231b3b80d8
6445ecb
Chad Rosier Update the default bug report url in autoconf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136721 91177308-0d34-0410-b5e6-96231b3b80d8
11066fb
@nlewycky nlewycky Lifetime intrinsics on undef are dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136722 91177308-0d34-0410-b5e6-96231b3b80d8
3e69c13
Eli Friedman Add new atomic instructions to SCCP. No functional change, but stops …
…debug spam.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136723 91177308-0d34-0410-b5e6-96231b3b80d8
fe1926e
@espindola espindola move PassManagerBuilder.h to IPO. This is a non intuitive place to pu…
…t it,

but it solves a layering violation since things in Support are not supposed to
use things in Transforms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136726 91177308-0d34-0410-b5e6-96231b3b80d8
3d453ac
@espindola espindola Move methods in PassManagerBuilder offline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136727 91177308-0d34-0410-b5e6-96231b3b80d8
c684e83
@isanbard isanbard Add the documentation for the 'landingpad' instruction. Improve the '…
…invoke'

instruction's documentation to reference the landingpad and resume instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136729 91177308-0d34-0410-b5e6-96231b3b80d8
f78faf8
Jakob Stoklund Olesen Extend the SpillPlacement interface with two new features.
The PrefBoth constraint is used for blocks that ideally want a live-in
value both on the stack and in a register. This would be used by a block
that has a use before interference forces a spill.

Secondly, add the ChangesValue flag to BlockConstraint. This tells
SpillPlacement if a live-in value on the stack can be reused as a
live-out stack value for free. If the block redefines the virtual
register, a spill would be required for that.

This extra information will be used by SpillPlacement to more accurately
calculate spill costs when a value can exist both on the stack and in a
register.

The simplest example is a basic block that reads the virtual register,
but doesn't change its value. Spilling around such a block requires a
reload, but no spill in the block.

The spiller already knows this, but the spill placer doesn't. That can
sometimes lead to suboptimal regions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136731 91177308-0d34-0410-b5e6-96231b3b80d8
0e0a880
@nlewycky nlewycky Teach InstCombine that lifetime intrincs aren't a real user on the re…
…sult of a

malloc call.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136732 91177308-0d34-0410-b5e6-96231b3b80d8
d8030c7
Jakob Stoklund Olesen Delete BlockInfo::LiveThrough. It wasn't used any more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136735 91177308-0d34-0410-b5e6-96231b3b80d8
4751eb7
Jakob Stoklund Olesen Add a BlockInfo::FirstDef field.
This is either an invalid SlotIndex, or valno->def for the first value
defined inside the block. PHI values are not counted as defined inside
the block.

The FirstDef field will be used when estimating the cost of spilling
around a block.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136736 91177308-0d34-0410-b5e6-96231b3b80d8
77ee114
Eli Friedman ARM backend support for atomicrmw and cmpxchg with non-monotonic orde…
…ring. Not especially pretty, but seems to work well enough. If this looks okay, I'll put together similar patches for Mips, PPC, and Alpha.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136737 91177308-0d34-0410-b5e6-96231b3b80d8
989f61e
Evan Cheng lldb doesn't need the edis dylib any more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136738 91177308-0d34-0410-b5e6-96231b3b80d8
779fa1b
Jakob Stoklund Olesen Rename {First,Last}Use to {First,Last}Instr.
With a 'FirstDef' field right there, it is very confusing that FirstUse
refers to an instruction that may be a def.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136739 91177308-0d34-0410-b5e6-96231b3b80d8
fe62d92
Jakob Stoklund Olesen Inform SpillPlacement about blocks with defs.
This information is not used for anything yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136741 91177308-0d34-0410-b5e6-96231b3b80d8
5ebca79
Jakob Stoklund Olesen Use the precomputed def presence in RAGreedy::calcSpillCost.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136742 91177308-0d34-0410-b5e6-96231b3b80d8
3f5beed
Commits on Aug 03, 2011
@isanbard isanbard Replace the 'UnwindInst' check with a check for 'ResumeInst', which a…
…lso exits

the function, because the UnwindInst is going away.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136751 91177308-0d34-0410-b5e6-96231b3b80d8
19308a1
@nlewycky nlewycky Fix logical error when detecting lifetime intrinsics.
Don't replace a gep/bitcast with 'undef' because that will form a "free(undef)"
which in turn means "unreachable". What we wanted was a no-op. Instead, analyze
the whole tree and look for all the instructions we need to delete first, then
delete them second, not relying on the use_list to stay consistent.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136752 91177308-0d34-0410-b5e6-96231b3b80d8
d5061a9
@isanbard isanbard Add this back in for now. There are still a few passes which create u…
…nwind instructions at the moment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136756 91177308-0d34-0410-b5e6-96231b3b80d8
d0c0d44
@nlewycky nlewycky Small cleanups:
  - use SmallVectorImpl& for the function argument.
  - ignore the operands on the GEP, even if they aren't constant! Much as we
    pretend the malloc succeeds, we pretend that malloc + whatever-you-GEP'd-by
    is not null. It's magic!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136757 91177308-0d34-0410-b5e6-96231b3b80d8
dbd2255
Devang Patel Use byte offset, instead of element number, to access merged global.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136759 91177308-0d34-0410-b5e6-96231b3b80d8
027cbf9
Chris Lattner fix PR10286, a problem with the .ll printer handling block addresses …
…that are out-of-scope.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136768 91177308-0d34-0410-b5e6-96231b3b80d8
fb5179a
@jayfoad jayfoad Use cast<> instead of a C-style cast to get some free assertions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136771 91177308-0d34-0410-b5e6-96231b3b80d8
e3fbe6c
Jakob Stoklund Olesen Handle IMPLICIT_DEF instructions in X86FloatingPoint.
This fixes PR10575.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136787 91177308-0d34-0410-b5e6-96231b3b80d8
56e3232
@isanbard isanbard Explain how clauses are applied.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136790 91177308-0d34-0410-b5e6-96231b3b80d8
b7a0135
Andrew Trick whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136795 91177308-0d34-0410-b5e6-96231b3b80d8
1c3ff65
Andrew Trick SCEV: Use AssertingVH to catch dangling BasicBlock* when passes forget
to notify SCEV of a change. Add forgetLoop in a couple of those places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136797 91177308-0d34-0410-b5e6-96231b3b80d8
1009c32
@isanbard isanbard Go back to the old definition. It's not clear that a 'resume' can be …
…'outlined' from the function with the landing pad for all platforms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136799 91177308-0d34-0410-b5e6-96231b3b80d8
e4ad50b
Bob Wilson Some revisions to Devang's change r136759 for merged global debug info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136802 91177308-0d34-0410-b5e6-96231b3b80d8
cfc55c2
@d0k d0k Remove unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136803 91177308-0d34-0410-b5e6-96231b3b80d8
1488f76
@isanbard isanbard Remove CreateUnwind from the IRBuillder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136811 91177308-0d34-0410-b5e6-96231b3b80d8
866ec86
Eli Friedman New approach to r136737: insert the necessary fences for atomic ops i…
…n platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing.

I think this completes the basic CodeGen for atomicrmw and cmpxchg.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136813 91177308-0d34-0410-b5e6-96231b3b80d8
26689ac
Evan Cheng Kill the export list as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136814 91177308-0d34-0410-b5e6-96231b3b80d8
a9362ca
Jakub Staszak Add more constantness in BlockFrequencyInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136816 91177308-0d34-0410-b5e6-96231b3b80d8
8ea4523
@resistor resistor Add accessors for manipulating an MCInst's operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136818 91177308-0d34-0410-b5e6-96231b3b80d8
56cb3e3
@isanbard isanbard Remove the LowerSetJmp pass. It wasn't used effectively by any of the…
… targets.

This is some of my original LLVM code. *wipes tear*


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136821 91177308-0d34-0410-b5e6-96231b3b80d8
2626dba
Jakub Staszak Use MachineBranchProbabilityInfo in If-Conversion instead of its own …
…heuristics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136826 91177308-0d34-0410-b5e6-96231b3b80d8
990f78d
Jakub Staszak Fix typo in #include which revealed in the case-sensitive filesystem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136828 91177308-0d34-0410-b5e6-96231b3b80d8
0767267
@chandlerc chandlerc Fix some warnings from Clang in release builds:
lib/CodeGen/RegAllocGreedy.cpp:1176:18: warning: unused variable 'B' [-Wunused-variable]
    if (unsigned B = Cand.getBundles(BundleCand, BestCand)) {
                 ^
lib/CodeGen/RegAllocGreedy.cpp:1188:18: warning: unused variable 'B' [-Wunused-variable]
    if (unsigned B = Cand.getBundles(BundleCand, 0)) {
                 ^

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136831 91177308-0d34-0410-b5e6-96231b3b80d8
32668ea
Jakob Stoklund Olesen Be more conservative when forming compact regions.
Apply twice the negative bias on transparent blocks when computing the
compact regions. This excludes loop backedges from the region when only
one of the loop blocks uses the register.

Previously, we would include the backedge in the region if the loop
preheader and the loop latch both used the register, but the loop header
didn't.

When both the header and latch blocks use the register, we still keep it
live on the backedge.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136832 91177308-0d34-0410-b5e6-96231b3b80d8
b87f91b
@d0k d0k Remove underscore that's breaking linux buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136833 91177308-0d34-0410-b5e6-96231b3b80d8
9dbd0a8
Devang Patel Do not drop undef debug values. These are used as range termination m…
…arker by live debug variable pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136834 91177308-0d34-0410-b5e6-96231b3b80d8
5787124
Jakob Stoklund Olesen Enable compact region splitting by default.
This helps generate better code in functions with high register
pressure.

The previous version of compact region splitting caused regressions
because the regions were a bit too large. A stronger negative bias
applied in r136832 fixed this problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136836 91177308-0d34-0410-b5e6-96231b3b80d8
a92afc1
@resistor resistor Fix broken encoding of tCBNZ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136837 91177308-0d34-0410-b5e6-96231b3b80d8
0bc8bbb
Andrew Trick An interface for iterating over a loop's blocks in DFS order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136838 91177308-0d34-0410-b5e6-96231b3b80d8
5207936
Andrew Trick whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136840 91177308-0d34-0410-b5e6-96231b3b80d8
fbfb806
Jakob Stoklund Olesen Correctly handle multiple DBG_VALUE instructions at the same SlotIndex.
It is possible to have multiple DBG_VALUEs for the same variable:

32L TEST32rr %vreg0<kill>, %vreg0, %EFLAGS<imp-def>; GR32:%vreg0
    DBG_VALUE 2, 0, !"i"
    DBG_VALUE %noreg, %0, !"i"

When that happens, keep the last one instead of the first.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136842 91177308-0d34-0410-b5e6-96231b3b80d8
79513ed
Andrew Trick whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136843 91177308-0d34-0410-b5e6-96231b3b80d8
882bcc6
Andrew Trick An algorithm for incrementally updating LoopInfo within a
LoopPassManager. The incremental update should be extremely cheap in
most cases and can be used in places where it's not feasible to
regenerate the entire loop forest.

- "Unloop" is a node in the loop tree whose last backedge has been removed.
- Perform reverse dataflow on the block inside Unloop to propagate the
  nearest loop from the block's successors.
- For reducible CFG, each block in unloop is visited exactly
  once. This is because unloop no longer has a backedge and blocks
  within subloops don't change parents.
- Immediate subloops are summarized by the nearest loop reachable from
  their exits or exits within nested subloops.
- At completion the unloop blocks each have a new parent loop, and
  each immediate subloop has a new parent.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136844 91177308-0d34-0410-b5e6-96231b3b80d8
762797d
Jim Grosbach ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
7ce0579
Commits on Aug 04, 2011
@isanbard isanbard Only access both operands of an INSERT_SUBVECTOR if it is an INSERT_S…
…UBVECTOR.

Fixes PR10527.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136853 91177308-0d34-0410-b5e6-96231b3b80d8
456a925
Jason W Kim Fix http://llvm.org/bugs/show_bug.cgi?id=10568
Move the reloc size assert into AsmBackend - where it is more apropos.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136855 91177308-0d34-0410-b5e6-96231b3b80d8
e651983
Andrew Trick Reverting r136884 updateUnloop, which crashed a linux builder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136857 91177308-0d34-0410-b5e6-96231b3b80d8
0712108
@CunningBaldrick CunningBaldrick Fix what seems an obvious typo. Patch by Ivan Krasin. Problem
reported at http://habrahabr.ru/blogs/compilers/125626/.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136865 91177308-0d34-0410-b5e6-96231b3b80d8
c9d904e
@jayfoad jayfoad Reword.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136866 91177308-0d34-0410-b5e6-96231b3b80d8
f42e9b2
@espindola espindola Print all the bits in the addend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136867 91177308-0d34-0410-b5e6-96231b3b80d8
d7c9b63
@espindola espindola Add an assert to check that the Addend fits the file format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136868 91177308-0d34-0410-b5e6-96231b3b80d8
bbf9c4a
@espindola espindola Don't print a counter in hex.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136869 91177308-0d34-0410-b5e6-96231b3b80d8
014180d
@espindola espindola Change anther counter to decimal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136870 91177308-0d34-0410-b5e6-96231b3b80d8
f7179de
@espindola espindola Another counter goes decimal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136871 91177308-0d34-0410-b5e6-96231b3b80d8
65ad8dc
@espindola espindola Print r_type with the correct number of bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136872 91177308-0d34-0410-b5e6-96231b3b80d8
f81f675
@espindola espindola Print r_sym with the correct number of bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136873 91177308-0d34-0410-b5e6-96231b3b80d8
a83f8ef
@espindola espindola Print st_bind with the correct number of bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136874 91177308-0d34-0410-b5e6-96231b3b80d8
d7c2783
@espindola espindola print st_type with the correct number of bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136875 91177308-0d34-0410-b5e6-96231b3b80d8
71a8f5c
@espindola espindola print st_other with the correct number of bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136877 91177308-0d34-0410-b5e6-96231b3b80d8
67ac0c0
@CunningBaldrick CunningBaldrick Add obviously missing "break". Noticed by Andrey Karpov with
the PVS-studio tool.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136878 91177308-0d34-0410-b5e6-96231b3b80d8
8036586
@espindola espindola print st_shndx with the correct number of bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136880 91177308-0d34-0410-b5e6-96231b3b80d8
251a2bb
@CunningBaldrick CunningBaldrick Fix a place that was clearly forgotten when the type legalization
logic moved over to its own enum.  Noticed by Andrey Karpov with
the PVS-studio tool.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136881 91177308-0d34-0410-b5e6-96231b3b80d8
1203486
@espindola espindola Fix the bitwidth of the remaining fields.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136884 91177308-0d34-0410-b5e6-96231b3b80d8
5c4e52e
@resistor resistor LDCL_POST and STCL_POST need one's-complement offsets, rather than tw…
…o's complement offsets. Add an appropriate immediate type for them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136896 91177308-0d34-0410-b5e6-96231b3b80d8
154c41d
Evan Cheng Fix an obvious type. Patch by Ivan Krasin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136899 91177308-0d34-0410-b5e6-96231b3b80d8
dd5663c
Evan Cheng Fix an obvious type. Patch by Ivan Krasin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136900 91177308-0d34-0410-b5e6-96231b3b80d8
a81388f
Devang Patel Add counter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136901 91177308-0d34-0410-b5e6-96231b3b80d8
ad90d3a
@rdivacky rdivacky Introduce adjustFixupOffset that adjusts the fixup offset of a reloca…
…tion.

This is meant to be overriden by backends. Implement an override on PowerPC
which adjusts the offset by 2 for ha16/lo16 relocation kinds. This removes
a commented out hack and enables hello world to be compiled on PowerPC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136905 91177308-0d34-0410-b5e6-96231b3b80d8
2a66cea
Chris Lattner allow \r's in .s files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136908 91177308-0d34-0410-b5e6-96231b3b80d8
0ecd825
Devang Patel Linke NamedMDNodes after linking global values as comment suggests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136909 91177308-0d34-0410-b5e6-96231b3b80d8
211da8f
Devang Patel We need to map DebugLoc. It leads to Fuction * (through subprogram en…
…try node) which should be appropriately mapped.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136910 91177308-0d34-0410-b5e6-96231b3b80d8
1f35b17
Devang Patel Increment counter inside insertDebugValue().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136915 91177308-0d34-0410-b5e6-96231b3b80d8
d9f3fc7
Devang Patel Print DBG_VALUE variable's location info as a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136916 91177308-0d34-0410-b5e6-96231b3b80d8
4d3586d
Jakob Stoklund Olesen Count the total amount of stack space used in compiled functions.
Patch by Ivan Krasin!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136921 91177308-0d34-0410-b5e6-96231b3b80d8
c219d19
Jim Grosbach ARM assembly parsing and encoding for LDR instructions.
Enhance support for LDR instruction assembly parsing for post-indexed
addressing with immediate values. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136940 91177308-0d34-0410-b5e6-96231b3b80d8
039c2e1
@resistor resistor Fix broken encodings for the Thumb2 LDRD/STRD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136942 91177308-0d34-0410-b5e6-96231b3b80d8
14c903a
Commits on Aug 05, 2011
@chandlerc chandlerc Temporarily revert r135528 which distinguishes between two copies of one
inlined variable, based on the discussion in PR10542.

This explodes the runtime of several passes down the pipeline due to
a large number of "copies" remaining live across a large function. This
only shows up with both debug and opt, but when it does it creates
a many-minute compile when self-hosting LLVM+Clang. There are several
other cases that show these types of regressions.

All of this is tracked in PR10542, and progress is being made on fixing
the issue. Once its addressed, the re-instated, but until then this
restores the performance for self-hosting and other opt+debug builds.

Devang, let me know if this causes any trouble, or impedes fixing it in
any way, and thanks for working on this!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136953 91177308-0d34-0410-b5e6-96231b3b80d8
4147f39
Jason W Kim Fix http://llvm.org/bugs/show_bug.cgi?id=10583\n - test for 1 and 2 b…
…yte fixups to be added

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136954 91177308-0d34-0410-b5e6-96231b3b80d8
4dd963b
@chandlerc chandlerc Silence unused variable warnings in release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136956 91177308-0d34-0410-b5e6-96231b3b80d8
8d8fa25
Bob Wilson Add missing register constraint for some VLD3/VLD4 pseudo instructions.
<rdar://problem/9878189>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136962 91177308-0d34-0410-b5e6-96231b3b80d8
9a45008
Jim Grosbach ARM use a dedicated printer for postidx_reg operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136968 91177308-0d34-0410-b5e6-96231b3b80d8
ca8c70b
Jim Grosbach ARM simplify the postidx_reg operand encoding.
The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136969 91177308-0d34-0410-b5e6-96231b3b80d8
16578b5
Jakob Stoklund Olesen Fix liveness computations in BranchFolding.
The old code would look at kills and defs in one pass over the
instruction operands, causing problems with this code:

  %R0<def>, %CPSR<def,dead> = tLSLri %R5<kill>, 2, pred:14, pred:%noreg
  %R0<def>, %CPSR<def,dead> = tADDrr %R4<kill>, %R0<kill>, pred:14, %pred:%noreg

The last instruction kills and redefines %R0, so it is still live after
the instruction.

This caused a register scavenger crash when compiling 483.xalancbmk for
armv6. I am not including a test case because it requires too much bad
luck to expose this old bug.

First you need to convince the register allocator to use %R0 twice on
the tADDrr instruction, then you have to convince BranchFolding to do
something that causes it to run the register scavenger on he bad block.

<rdar://problem/9898200>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136973 91177308-0d34-0410-b5e6-96231b3b80d8
54cfeda
Jim Grosbach Add ARM LDR parsing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136977 91177308-0d34-0410-b5e6-96231b3b80d8
6fc1c08
Jim Grosbach ARM refactor indexed store instructions.
Refactor STR[B] pre and post indexed instructions to use addressing modes for
memory operands, which is necessary for assembly parsing and is more consistent
with the rest of the memory instruction definitions. Make some incremental
progress on refactoring away the mega-operand addrmode2 along the way, which
is nice.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136978 91177308-0d34-0410-b5e6-96231b3b80d8
19dec20
Jakob Stoklund Olesen Detect proper register sub-classes.
Some instructions require restricted register classes, but most of the
time that doesn't affect register allocation. For example, some
instructions don't work with the stack pointer, but that is a reserved
register anyway.

Sometimes it matters, GR32_ABCD only has 4 allocatable registers. For
such a proper sub-class, the register allocator should try to enable
register class inflation since that makes more registers available for
allocation.

Make sure only legal super-classes are considered. For example, tGPR is
not a proper sub-class in Thumb mode, but in ARM mode it is.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136981 91177308-0d34-0410-b5e6-96231b3b80d8
f39031b
Jim Grosbach ARM indexed load assembly parsing and encoding.
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136982 91177308-0d34-0410-b5e6-96231b3b80d8
f4fa3d6
Jim Grosbach ARM load instruction shifted register index operands.
Parsing and encoding for shifted index operands for load instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136986 91177308-0d34-0410-b5e6-96231b3b80d8
0d6fac3
Jakob Stoklund Olesen Split around single instructions to enable register class inflation.
Normally, we don't create a live range for a single instruction in a
basic block, the spiller does that anyway. However, when splitting a
live range that belongs to a proper register sub-class, inserting these
extra COPY instructions completely remove the constraints from the
remainder interval, and it may be allocated from the larger super-class.

The spiller will mop up these small live ranges if we end up spilling
anyway. It calls them snippets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136989 91177308-0d34-0410-b5e6-96231b3b80d8
2d6d86b
Jakob Stoklund Olesen Also use shouldSplitSingleBlock() in the fallback splitting mode.
Drop the use of SplitAnalysis::getMultiUseBlocks, there is no need to go
through a SmallPtrSet any more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136992 91177308-0d34-0410-b5e6-96231b3b80d8
b3ef7f6
Jakob Stoklund Olesen Delete getMultiUseBlocks and splitSingleBlocks.
These functions are no longer used, and they are easily replaced with a
loop calling shouldSplitSingleBlock and splitSingleBlock.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136993 91177308-0d34-0410-b5e6-96231b3b80d8
75e28f7
Jakob Stoklund Olesen Extract per-block splitting into its own method.
No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136994 91177308-0d34-0410-b5e6-96231b3b80d8
dab35d3
Jakob Stoklund Olesen Remember to update LiveDebugVariables after per-block splitting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136996 91177308-0d34-0410-b5e6-96231b3b80d8
1f88042
Jakob Stoklund Olesen Only mark remainder intervals as RS_Spill after per-block splitting.
The local ranges created get to stay in the RS_New stage, just like for
local and region splitting.

This gives tryLocalSplit a bit more freedom the first time it sees one
of these new local ranges.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137001 91177308-0d34-0410-b5e6-96231b3b80d8
a9c41d3
Jakob Stoklund Olesen Reject RS_Spill ranges from local splitting as well.
All new local ranges are marked as RS_New now, so there is no need to
attempt splitting of RS_Spill ranges any more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137002 91177308-0d34-0410-b5e6-96231b3b80d8
ccfa446
Commits on Aug 06, 2011
Andrew Trick Made SCEV's UDiv expressions more canonical. When dividing a
recurrence, the initial values low bits can sometimes be ignored.

To take advantage of this, added FoldIVUser to IndVarSimplify to fold
an IV operand into a udiv/lshr if the operator doesn't affect the
result.

-indvars -disable-iv-rewrite now transforms

i = phi i4
i1 = i0 + 1
idx = i1 >> (2 or more)
i4 = i + 4

into

i = phi i4
idx = i0 >> ...
i4 = i + 4


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137013 91177308-0d34-0410-b5e6-96231b3b80d8
06988bc
Jakob Stoklund Olesen Fix typo. Thanks, Andy!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137023 91177308-0d34-0410-b5e6-96231b3b80d8
69145ba
Commits on Aug 07, 2011
Chris Lattner strengthen up an assertion: you can't create a constant struct
with an opaque struct type, it doesn't make sense.  This should
resolve PR10473.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137028 91177308-0d34-0410-b5e6-96231b3b80d8
f4ef8db
Commits on Aug 08, 2011
@jpbonn jpbonn Merge branch 'master' of http://llvm.org/git/llvm
Conflicts:
	autoconf/configure.ac
	cmake/modules/LLVMLibDeps.cmake
	configure
	lib/Support/Triple.cpp
ce427e3
@jpbonn jpbonn Updated to match SVN head - Many MC related changes. dea4593
@jpbonn jpbonn Merge branch 'master' of github.com:milkymist/llvm-lm32 6735653
@jpbonn jpbonn Untested attempt to update for latest MC changes. f1db207