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base fork: m-labs/llvm-lm32
base: 6476535
...
head fork: m-labs/llvm-lm32
compare: 2a1ffcf
  • 6 commits
  • 46 files changed
  • 0 commit comments
  • 3 contributors
Commits on Jun 14, 2011
Jim Grosbach Revert 133010. Self-hosted buildbot unhappy.
Apparently llvm itself generates undefined assembler local labels, causing
self-hosting problems with this patch. Reverting until that's sorted out.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133013 91177308-0d34-0410-b5e6-96231b3b80d8
6c3044d
Stuart Hastings Test case for x86 MMX inline asm. rdar://problem/8886707
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133014 91177308-0d34-0410-b5e6-96231b3b80d8
0ca7338
@jpbonn jpbonn Merge branch 'master' of http://llvm.org/git/llvm into mico32 5434905
Commits on Jun 15, 2011
@jpbonn jpbonn Reenabled disabled tests. Removed some XFAIL flags. 390351c
@jpbonn jpbonn Removed monarch references and corrected cases of march=monarch. 9dca00c
@jpbonn jpbonn Added ADDE/ADDC/SUBE/SUBC, set BR_JT to expand, updated README. 2a1ffcf
Showing with 141 additions and 391 deletions.
  1. +1 −12 include/llvm/MC/MCContext.h
  2. +4 −25 lib/MC/MCParser/AsmParser.cpp
  3. +9 −2 lib/Target/Mico32/Mico32ISelLowering.cpp
  4. +35 −9 lib/Target/Mico32/README
  5. +3 −1 test/CodeGen/Mico32/{2006-08-11-RetVector.ll.xfail → 2006-08-11-RetVector.ll}
  6. +0 −2  test/CodeGen/Mico32/2006-12-07-LargeAlloca.ll
  7. +0 −3  test/CodeGen/Mico32/2007-04-03-PEIBug.ll
  8. +1 −1  test/CodeGen/Mico32/{2007-05-07-tailmerge-1.ll.xfail → 2007-05-07-tailmerge-1.ll}
  9. +1 −1  test/CodeGen/Mico32/{2007-05-09-tailmerge-2.ll.xfail → 2007-05-09-tailmerge-2.ll}
  10. +0 −70 test/CodeGen/Mico32/2007-05-22-tailmerge-3.ll.xfail
  11. +0 −2  test/CodeGen/Mico32/2007-09-08-unaligned.ll
  12. +0 −2  test/CodeGen/Mico32/2007-09-08-unaligned_pass.ll
  13. +1 −1  test/CodeGen/Mico32/{2008-03-06-KillInfo.ll.xfail → 2008-03-06-KillInfo.ll}
  14. +11 −11 test/CodeGen/Mico32/{2008-09-12-CoalescerBug.ll.xfail → 2008-09-12-CoalescerBug.ll}
  15. +1 −1  test/CodeGen/Mico32/{2009-02-22-SoftenFloatVaArg.ll.xfail → 2009-02-22-SoftenFloatVaArg.ll}
  16. +1 −1  test/CodeGen/Mico32/{Frames-large.ll.xfail → Frames-large.ll}
  17. +1 −1  test/CodeGen/Mico32/and_ops.ll
  18. +1 −1  test/CodeGen/Mico32/{bool-vector.ll.xfail → bool-vector.ll}
  19. +1 −1  test/CodeGen/Mico32/{branch-opt.ll.xfail → branch-opt.ll}
  20. +1 −1  test/CodeGen/Mico32/{constindices.ll.xfail → constindices.ll}
  21. +0 −2  test/CodeGen/Mico32/fpcmp_ueq.ll
  22. +0 −2  test/CodeGen/Mico32/fpcmp_xfail.ll
  23. +6 −7 test/CodeGen/Mico32/jmp_table.ll
  24. +1 −1  test/CodeGen/Mico32/{large-stack.ll.xfail → large-stack.ll}
  25. +1 −1  test/CodeGen/Mico32/{mul128.ll.xfail → mul128.ll}
  26. +1 −73 test/CodeGen/Mico32/nand.ll
  27. +1 −115 test/CodeGen/Mico32/or_ops.ll
  28. +1 −3 test/CodeGen/Mico32/or_ops_pass.ll
  29. +0 −2  test/CodeGen/Mico32/ord.ll
  30. +0 −2  test/CodeGen/Mico32/retaddr.ll
  31. +1 −1  test/CodeGen/Mico32/select_bits.ll
  32. +1 −1  test/CodeGen/Mico32/select_bits_pass.ll
  33. +1 −1  test/CodeGen/Mico32/trunc.ll
  34. +1 −1  test/CodeGen/Mico32/trunc_pass.ll
  35. +1 −1  test/CodeGen/Mico32/{truncstore-dag-combine2.ll.xfail → truncstore-dag-combine2.ll}
  36. +0 −18 test/CodeGen/Mico32/unaligned_load_store.ll.xfail
  37. +0 −2  test/CodeGen/Mico32/unord.ll
  38. +1 −1  test/CodeGen/Mico32/{vargs2.ll.xfail → vargs2.ll}
  39. +1 −1  test/CodeGen/Mico32/vec_const.ll
  40. +1 −1  test/CodeGen/Mico32/vec_insert.ll
  41. +1 −3 test/CodeGen/Mico32/{vec_misaligned.ll.xfail → vec_misaligned.ll}
  42. +1 −1  test/CodeGen/Mico32/vec_mul.ll
  43. +1 −1  test/CodeGen/Mico32/vecinsert.ll
  44. +1 −1  test/CodeGen/Mico32/vecinsert_pass.ll
  45. +1 −1  test/CodeGen/Mico32/{vfp.ll.xfail → vfp.ll}
  46. +45 −0 test/CodeGen/X86/2011-06-14-mmx-inlineasm.ll
View
13 include/llvm/MC/MCContext.h
@@ -39,9 +39,6 @@ namespace llvm {
class MCContext {
MCContext(const MCContext&); // DO NOT IMPLEMENT
MCContext &operator=(const MCContext&); // DO NOT IMPLEMENT
- public:
- typedef StringMap<MCSymbol*, BumpPtrAllocator&> SymbolTable;
- private:
/// The MCAsmInfo for this target.
const MCAsmInfo &MAI;
@@ -55,7 +52,7 @@ namespace llvm {
BumpPtrAllocator Allocator;
/// Symbols - Bindings of names to symbols.
- SymbolTable Symbols;
+ StringMap<MCSymbol*, BumpPtrAllocator&> Symbols;
/// UsedNames - Keeps tracks of names that were used both for used declared
/// and artificial symbols.
@@ -145,14 +142,6 @@ namespace llvm {
/// LookupSymbol - Get the symbol for \p Name, or null.
MCSymbol *LookupSymbol(StringRef Name) const;
- /// getSymbols - Get a reference for the symbol table for clients that
- /// want to, for example, iterate over all symbols. 'const' because we
- /// still want any modifications to the table itself to use the MCContext
- /// APIs.
- const SymbolTable &getSymbols() const {
- return Symbols;
- }
-
/// @}
/// @name Section Management
View
29 lib/MC/MCParser/AsmParser.cpp
@@ -84,7 +84,6 @@ class AsmParser : public MCAsmParser {
AsmLexer Lexer;
MCContext &Ctx;
MCStreamer &Out;
- const MCAsmInfo &MAI;
SourceMgr &SrcMgr;
MCAsmParserExtension *GenericParser;
MCAsmParserExtension *PlatformParser;
@@ -136,7 +135,7 @@ class AsmParser : public MCAsmParser {
virtual MCContext &getContext() { return Ctx; }
virtual MCStreamer &getStreamer() { return Out; }
- virtual bool Warning(SMLoc L, const Twine &Msg);
+ virtual bool Warning(SMLoc L, const Twine &Meg);
virtual bool Error(SMLoc L, const Twine &Msg);
const AsmToken &Lex();
@@ -161,9 +160,8 @@ class AsmParser : public MCAsmParser {
void HandleMacroExit();
void PrintMacroInstantiations();
- void PrintMessage(SMLoc Loc, const Twine &Msg, const char *Type,
- bool ShowLine = true) const {
- SrcMgr.PrintMessage(Loc, Msg, Type, ShowLine);
+ void PrintMessage(SMLoc Loc, const Twine &Msg, const char *Type) const {
+ SrcMgr.PrintMessage(Loc, Msg, Type);
}
/// EnterIncludeFile - Enter the specified file. This returns true on failure.
@@ -339,7 +337,7 @@ enum { DEFAULT_ADDRSPACE = 0 };
AsmParser::AsmParser(const Target &T, SourceMgr &_SM, MCContext &_Ctx,
MCStreamer &_Out, const MCAsmInfo &_MAI)
- : Lexer(_MAI), Ctx(_Ctx), Out(_Out), MAI(_MAI), SrcMgr(_SM),
+ : Lexer(_MAI), Ctx(_Ctx), Out(_Out), SrcMgr(_SM),
GenericParser(new GenericAsmParser), PlatformParser(0),
CurBuffer(0), MacrosEnabled(true) {
Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer));
@@ -468,25 +466,6 @@ bool AsmParser::Run(bool NoInitialTextSection, bool NoFinalize) {
TokError("unassigned file number: " + Twine(i) + " for .file directives");
}
- // Check to see that all assembler local symbols were actually defined.
- // Targets that don't do subsections via symbols may not want this, though,
- // so conservatively exclude them.
- if (MAI.hasSubsectionsViaSymbols()) {
- const MCContext::SymbolTable &Symbols = getContext().getSymbols();
- for (MCContext::SymbolTable::const_iterator i = Symbols.begin(),
- e = Symbols.end();
- i != e; ++i) {
- MCSymbol *Sym = i->getValue();
- if (Sym->isTemporary() && !Sym->isDefined())
- // FIXME: We would really like to refer back to where the symbol was
- // first referenced for a source location. We need to add something
- // to track that. Currently, we just point to the end of the file.
- PrintMessage(getLexer().getLoc(), "assembler local symbol '" +
- Sym->getName() + "' not defined", "error", false);
- }
- }
-
-
// Finalize the output stream if there are no errors and if the client wants
// us to.
if (!HadError && !NoFinalize)
View
11 lib/Target/Mico32/Mico32ISelLowering.cpp
@@ -70,6 +70,12 @@ Mico32TargetLowering::Mico32TargetLowering(Mico32TargetMachine &TM)
// setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
// setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
+ // There's no extended adds or subtracts.
+ setOperationAction(ISD::ADDC, MVT::i32, Expand);
+ setOperationAction(ISD::ADDE, MVT::i32, Expand);
+ setOperationAction(ISD::SUBC, MVT::i32, Expand);
+ setOperationAction(ISD::SUBE, MVT::i32, Expand);
+
// Check if unsigned div/mod are enabled.
if (!Subtarget->hasDIV()) {
setOperationAction(ISD::UDIV, MVT::i32, Expand);
@@ -142,8 +148,9 @@ Mico32TargetLowering::Mico32TargetLowering(Mico32TargetMachine &TM)
setOperationAction(ISD::VACOPY, MVT::Other, Expand);
-// FIXME: need to handle branches
-// setOperationAction(ISD::BR_JT, MVT::Other, Expand);
+ // Mico32 does not have jump table branches.
+ setOperationAction(ISD::BR_JT, MVT::Other, Expand);
+ // Expand BR_CC to BRCOND.
setOperationAction(ISD::BR_CC, MVT::Other, Expand);
// Operations not directly supported by Mico32.
View
44 lib/Target/Mico32/README
@@ -60,15 +60,41 @@ After the inital "make check" (which does some initial DejaGnu configuration) yo
--------------------
-Initial results:
-
- Expected Passes : 439
- Expected Failures : 28
- Unexpected Passes : 7
- Unexpected Failures: 37
-
-
-Notes
+Test Results:
+
+Failing Tests (25):
+ LLVM :: CodeGen/mico32/2005-11-30-vastart-crash.ll
+ LLVM :: CodeGen/mico32/2006-04-04-zextload.ll
+ LLVM :: CodeGen/mico32/2006-10-17-ppc64-alloca.ll
+ LLVM :: CodeGen/mico32/2006-12-07-LargeAlloca.ll
+ LLVM :: CodeGen/mico32/2007-03-06-AddR7.ll
+ LLVM :: CodeGen/mico32/2007-04-03-PEIBug.ll
+ LLVM :: CodeGen/mico32/2007-05-03-BadPostIndexedLd.ll
+ LLVM :: CodeGen/mico32/2007-08-15-ReuseBug.ll
+ LLVM :: CodeGen/mico32/2007-11-16-landingpad-split.ll
+ LLVM :: CodeGen/mico32/2008-02-05-LiveIntervalsAssert.ll
+ LLVM :: CodeGen/mico32/2008-04-11-PHIofImpDef.ll
+ LLVM :: CodeGen/mico32/2008-06-23-LiveVariablesCrash.ll
+ LLVM :: CodeGen/mico32/2008-08-06-Alloca.ll
+ LLVM :: CodeGen/mico32/2008-09-12-CoalescerBug.ll
+ LLVM :: CodeGen/mico32/2008-09-17-CoalescerBug.ll
+ LLVM :: CodeGen/mico32/Frames-alloca.ll
+ LLVM :: CodeGen/mico32/alloca.ll
+ LLVM :: CodeGen/mico32/call_adj.ll
+ LLVM :: CodeGen/mico32/dyn-stackalloc.ll
+ LLVM :: CodeGen/mico32/invalid-memcpy.ll
+ LLVM :: CodeGen/mico32/jmp_table.ll
+ LLVM :: CodeGen/mico32/stack-frame.ll
+ LLVM :: CodeGen/mico32/stacksave-restore.ll
+ LLVM :: CodeGen/mico32/switch-lower-feature-2.ll
+ LLVM :: CodeGen/mico32/vargs2.ll
+
+ Expected Passes : 472
+ Expected Failures : 25
+ Unexpected Failures: 25
+
+
+NOTES
Calling conventions
from GCC lm32.c
View
4 ...eGen/Mico32/2006-08-11-RetVector.ll.xfail → test/CodeGen/Mico32/2006-08-11-RetVector.ll
@@ -1,4 +1,6 @@
-; RUN: llvm-as < %s | llc -march=monarch
+; mico32 can only return <2 x i32> at most.
+; XFAIL: *
+; RUN: llvm-as < %s | llc -march=mico32
; END.
; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsldoi
; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep vor
View
2  test/CodeGen/Mico32/2006-12-07-LargeAlloca.ll
@@ -1,5 +1,3 @@
-; monarch stack offset is limited to ~32K.
-; XFAIL: *
; RUN: llvm-as < %s | llc -march=mico32
; END.
; RUN: llvm-as < %s | llc -march=ppc64
View
3  test/CodeGen/Mico32/2007-04-03-PEIBug.ll
@@ -1,6 +1,3 @@
-; monarch stack offset is limited to ~32K.
-; monarch doesn't support varargs.
-; XFAIL: *
; RUN: llvm-as < %s | llc -march=mico32
; END.
; RUN: llvm-as < %s | llc -march=arm | not grep {add.*#0}
View
2  ...en/Mico32/2007-05-07-tailmerge-1.ll.xfail → .../CodeGen/Mico32/2007-05-07-tailmerge-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=monarch
+; RUN: llvm-as < %s | llc -march=mico32
; END.
; RUN: llvm-as < %s | llc -march=arm -enable-tail-merge | grep bl.*baz | count 1
; RUN: llvm-as < %s | llc -march=arm -enable-tail-merge | grep bl.*quux | count 1
View
2  ...en/Mico32/2007-05-09-tailmerge-2.ll.xfail → .../CodeGen/Mico32/2007-05-09-tailmerge-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=monarch
+; RUN: llvm-as < %s | llc -march=mico32
; END.
; RUN: llvm-as < %s | llc -march=arm -enable-tail-merge | grep bl.*baz | count 1
; RUN: llvm-as < %s | llc -march=arm -enable-tail-merge | grep bl.*quux | count 1
View
70 test/CodeGen/Mico32/2007-05-22-tailmerge-3.ll.xfail
@@ -1,70 +0,0 @@
-; RUN: llvm-as < %s | llc -march=monarch
-; END.
-; RUN: llvm-as < %s | llc -march=ppc32 | grep bl.*baz | count 2
-; RUN: llvm-as < %s | llc -march=ppc32 | grep bl.*quux | count 2
-; RUN: llvm-as < %s | llc -march=ppc32 -enable-tail-merge | grep bl.*baz | count 1
-; RUN: llvm-as < %s | llc -march=ppc32 -enable-tail-merge=1 | grep bl.*quux | count 1
-; Check that tail merging is not the default on ppc, and that -enable-tail-merge works.
-
-; ModuleID = 'tail.c'
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
-target triple = "i686-apple-darwin8"
-
-define i32 @f(i32 %i, i32 %q) {
-entry:
- %i_addr = alloca i32 ; <i32*> [#uses=2]
- %q_addr = alloca i32 ; <i32*> [#uses=2]
- %retval = alloca i32, align 4 ; <i32*> [#uses=1]
- "alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
- store i32 %i, i32* %i_addr
- store i32 %q, i32* %q_addr
- %tmp = load i32* %i_addr ; <i32> [#uses=1]
- %tmp1 = icmp ne i32 %tmp, 0 ; <i1> [#uses=1]
- %tmp12 = zext i1 %tmp1 to i8 ; <i8> [#uses=1]
- %toBool = icmp ne i8 %tmp12, 0 ; <i1> [#uses=1]
- br i1 %toBool, label %cond_true, label %cond_false
-
-cond_true: ; preds = %entry
- %tmp3 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
- %tmp4 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
- %tmp7 = load i32* %q_addr ; <i32> [#uses=1]
- %tmp8 = icmp ne i32 %tmp7, 0 ; <i1> [#uses=1]
- %tmp89 = zext i1 %tmp8 to i8 ; <i8> [#uses=1]
- %toBool10 = icmp ne i8 %tmp89, 0 ; <i1> [#uses=1]
- br i1 %toBool10, label %cond_true11, label %cond_false15
-
-cond_false: ; preds = %entry
- %tmp5 = call i32 (...)* @foo( ) ; <i32> [#uses=0]
- %tmp6 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
- %tmp27 = load i32* %q_addr ; <i32> [#uses=1]
- %tmp28 = icmp ne i32 %tmp27, 0 ; <i1> [#uses=1]
- %tmp289 = zext i1 %tmp28 to i8 ; <i8> [#uses=1]
- %toBool210 = icmp ne i8 %tmp289, 0 ; <i1> [#uses=1]
- br i1 %toBool210, label %cond_true11, label %cond_false15
-
-cond_true11: ; preds = %cond_next
- %tmp13 = call i32 (...)* @foo( ) ; <i32> [#uses=0]
- %tmp14 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0]
- br label %cond_next18
-
-cond_false15: ; preds = %cond_next
- %tmp16 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
- %tmp17 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0]
- br label %cond_next18
-
-cond_next18: ; preds = %cond_false15, %cond_true11
- %tmp19 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
- br label %return
-
-return: ; preds = %cond_next18
- %retval20 = load i32* %retval ; <i32> [#uses=1]
- ret i32 %retval20
-}
-
-declare i32 @bar(...)
-
-declare i32 @baz(...)
-
-declare i32 @foo(...)
-
-declare i32 @quux(...)
View
2  test/CodeGen/Mico32/2007-09-08-unaligned.ll
@@ -1,5 +1,3 @@
-; monarch does not support unaligned accesses.
-; XFAIL: *
; RUN: llvm-as < %s | llc -march=mico32
; END.
; RUN: llvm-as < %s | llc | grep stfd | count 3
View
2  test/CodeGen/Mico32/2007-09-08-unaligned_pass.ll
@@ -1,5 +1,3 @@
-; monarch does not support unaligned accesses.
-; XFAIL: *
; RUN: llvm-as < %s | llc -march=mico32
; END.
; RUN: llvm-as < %s | llc | grep stfd | count 3
View
2  ...deGen/Mico32/2008-03-06-KillInfo.ll.xfail → test/CodeGen/Mico32/2008-03-06-KillInfo.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=monarch
+; RUN: llvm-as < %s | llc -march=mico32
; XFAIL: *
; END.
; RUN: llvm-as < %s | llc -march=ppc64 -enable-ppc64-regscavenger
View
22 ...n/Mico32/2008-09-12-CoalescerBug.ll.xfail → ...CodeGen/Mico32/2008-09-12-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=monarch
+; RUN: llvm-as < %s | llc -march=mico32
; END.
; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin
@@ -31,9 +31,9 @@ bb2217: ; preds = %bb2326
%10 = load float* %9, align 4 ; <float> [#uses=1]
%11 = getelementptr float* null, i32 3 ; <float*> [#uses=1]
%12 = load float* %11, align 4 ; <float> [#uses=1]
- %13 = mul float %10, 6.553500e+04 ; <float> [#uses=1]
+ %13 = fmul float %10, 6.553500e+04 ; <float> [#uses=1]
%14 = add float %13, 5.000000e-01 ; <float> [#uses=1]
- %15 = mul float %12, 6.553500e+04 ; <float> [#uses=1]
+ %15 = fmul float %12, 6.553500e+04 ; <float> [#uses=1]
%16 = add float %15, 5.000000e-01 ; <float> [#uses=3]
%17 = fcmp olt float %14, 0.000000e+00 ; <i1> [#uses=0]
%18 = fcmp olt float %16, 0.000000e+00 ; <i1> [#uses=1]
@@ -70,9 +70,9 @@ bb2265: ; preds = %bb2264, %bb2262, %bb2217
%37 = load float* %36, align 4 ; <float> [#uses=1]
%38 = getelementptr float* %36, i32 1 ; <float*> [#uses=1]
%39 = load float* %38, align 4 ; <float> [#uses=1]
- %40 = mul float %37, 6.553500e+04 ; <float> [#uses=1]
+ %40 = fmul float %37, 6.553500e+04 ; <float> [#uses=1]
%41 = add float %40, 5.000000e-01 ; <float> [#uses=1]
- %42 = mul float %39, 6.553500e+04 ; <float> [#uses=1]
+ %42 = fmul float %39, 6.553500e+04 ; <float> [#uses=1]
%43 = add float %42, 5.000000e-01 ; <float> [#uses=3]
%44 = fcmp olt float %41, 0.000000e+00 ; <i1> [#uses=0]
%45 = fcmp olt float %43, 0.000000e+00 ; <i1> [#uses=1]
@@ -90,9 +90,9 @@ bb2277: ; preds = %bb2274, %bb2265
%50 = load float* %49, align 4 ; <float> [#uses=1]
%51 = getelementptr float* %36, i32 3 ; <float*> [#uses=1]
%52 = load float* %51, align 4 ; <float> [#uses=1]
- %53 = mul float %50, 6.553500e+04 ; <float> [#uses=1]
+ %53 = fmul float %50, 6.553500e+04 ; <float> [#uses=1]
%54 = add float %53, 5.000000e-01 ; <float> [#uses=1]
- %55 = mul float %52, 6.553500e+04 ; <float> [#uses=1]
+ %55 = fmul float %52, 6.553500e+04 ; <float> [#uses=1]
%56 = add float %55, 5.000000e-01 ; <float> [#uses=1]
%57 = fcmp olt float %54, 0.000000e+00 ; <i1> [#uses=0]
%58 = fcmp olt float %56, 0.000000e+00 ; <i1> [#uses=0]
@@ -113,9 +113,9 @@ bb2277: ; preds = %bb2274, %bb2265
%73 = load float* %72, align 4 ; <float> [#uses=1]
%74 = getelementptr float* %72, i32 1 ; <float*> [#uses=1]
%75 = load float* %74, align 4 ; <float> [#uses=1]
- %76 = mul float %73, 6.553500e+04 ; <float> [#uses=1]
+ %76 = fmul float %73, 6.553500e+04 ; <float> [#uses=1]
%77 = add float %76, 5.000000e-01 ; <float> [#uses=3]
- %78 = mul float %75, 6.553500e+04 ; <float> [#uses=1]
+ %78 = fmul float %75, 6.553500e+04 ; <float> [#uses=1]
%79 = add float %78, 5.000000e-01 ; <float> [#uses=1]
%80 = fcmp olt float %77, 0.000000e+00 ; <i1> [#uses=1]
br i1 %80, label %bb2295, label %bb2292
@@ -136,9 +136,9 @@ bb2295: ; preds = %bb2294, %bb2292, %bb2277
%86 = load float* %85, align 4 ; <float> [#uses=1]
%87 = getelementptr float* %72, i32 3 ; <float*> [#uses=1]
%88 = load float* %87, align 4 ; <float> [#uses=1]
- %89 = mul float %86, 6.553500e+04 ; <float> [#uses=1]
+ %89 = fmul float %86, 6.553500e+04 ; <float> [#uses=1]
%90 = add float %89, 5.000000e-01 ; <float> [#uses=1]
- %91 = mul float %88, 6.553500e+04 ; <float> [#uses=1]
+ %91 = fmul float %88, 6.553500e+04 ; <float> [#uses=1]
%92 = add float %91, 5.000000e-01 ; <float> [#uses=1]
%93 = fcmp olt float %90, 0.000000e+00 ; <i1> [#uses=0]
%94 = fcmp olt float %92, 0.000000e+00 ; <i1> [#uses=0]
View
2  ...co32/2009-02-22-SoftenFloatVaArg.ll.xfail → ...Gen/Mico32/2009-02-22-SoftenFloatVaArg.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=monarch
+; RUN: llvm-as < %s | llc -march=mico32
; END.
; RUN: llvm-as < %s | llc
; PR3610
View
2  test/CodeGen/Mico32/Frames-large.ll.xfail → test/CodeGen/Mico32/Frames-large.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=monarch
+; RUN: llvm-as < %s | llc -march=mico32
; END.
; RUN: llvm-as < %s | \
; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \
View
2  test/CodeGen/Mico32/and_ops.ll
@@ -1,4 +1,4 @@
-; monarch only supports returning <4 x i32>.
+; mico32 can return < 2 x i32> at most.
; XFAIL: *
; RUN: llvm-as -o - %s | llc -march=mico32
; END.
View
2  test/CodeGen/Mico32/bool-vector.ll.xfail → test/CodeGen/Mico32/bool-vector.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=monarch
+; RUN: llvm-as < %s | llc -march=mico32
; END.
; RUN: llvm-as < %s | llc
; PR1845
View
2  test/CodeGen/Mico32/branch-opt.ll.xfail → test/CodeGen/Mico32/branch-opt.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=monarch
+; RUN: llvm-as < %s | llc -march=mico32
; END.
; RUN: llvm-as < %s | llc -march=ppc32 | \
; RUN: grep {b LBB.*} | count 4
View
2  test/CodeGen/Mico32/constindices.ll.xfail → test/CodeGen/Mico32/constindices.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=monarch
+; RUN: llvm-as < %s | llc -march=mico32
; END.
; RUN: llvm-as < %s | llc
View
2  test/CodeGen/Mico32/fpcmp_ueq.ll
@@ -1,5 +1,3 @@
-; Monarch does not support unordered compares.
-; XFAIL: *
; RUN: llvm-as < %s | llc -march=mico32
; END.
; RUN: llvm-as < %s | llc -march=arm | grep moveq
View
2  test/CodeGen/Mico32/fpcmp_xfail.ll
@@ -1,5 +1,3 @@
-; Monarch does not support unordered compares.
-; XFAIL: *
; RUN: llvm-as < %s | llc -march=mico32
; END.
; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 > %t
View
13 test/CodeGen/Mico32/jmp_table.ll
@@ -1,14 +1,13 @@
; try to check that we have the most important instructions, which shouldn't
; appear otherwise
; RUN: llvm-as < %s | llc -march=mico32
-;# RUN: llvm-as < %s | llc -march=alpha | grep jmp
-;# RUN: llvm-as < %s | llc -march=alpha | grep gprel32
-;# RUN: llvm-as < %s | llc -march=alpha | grep ldl
-;# RUN: llvm-as < %s | llc -march=alpha | grep rodata
-;# END.
+; END.
+; RUN: llvm-as < %s | llc -march=alpha | grep jmp
+; RUN: llvm-as < %s | llc -march=alpha | grep gprel32
+; RUN: llvm-as < %s | llc -march=alpha | grep ldl
+; RUN: llvm-as < %s | llc -march=alpha | grep rodata
+; END.
-; target datalayout = "e-p:64:64"
-; target triple = "alphaev67-unknown-linux-gnu"
@str = internal constant [2 x i8] c"1\00" ; <[2 x i8]*> [#uses=1]
@str1 = internal constant [2 x i8] c"2\00" ; <[2 x i8]*> [#uses=1]
@str2 = internal constant [2 x i8] c"3\00" ; <[2 x i8]*> [#uses=1]
View
2  test/CodeGen/Mico32/large-stack.ll.xfail → test/CodeGen/Mico32/large-stack.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=monarch
+; RUN: llvm-as < %s | llc -march=mico32
; XFAIL: *
; END.
; RUN: llvm-as < %s | llc -march=arm
View
2  test/CodeGen/Mico32/mul128.ll.xfail → test/CodeGen/Mico32/mul128.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=monarch
+; RUN: llvm-as < %s | llc -march=mico32
; XFAIL: *
define i128 @__mulvdi3(i128 %a, i128 %b) nounwind {
View
74 test/CodeGen/Mico32/nand.ll
@@ -1,4 +1,4 @@
-; monarch supports returning <4 x i32> at most.
+; mico32 supports returning <4 x i32> at most.
; nand_pass.ll has supported versions of this test.
; XFAIL: *
; RUN: llvm-as -o - %s | llc -march=mico32
@@ -52,75 +52,3 @@ define <16 x i8> @nand_v16i8_2(<16 x i8> %arg1, <16 x i8> %arg2) {
i8 -1, i8 -1, i8 -1, i8 -1 >
ret <16 x i8> %B
}
-
-define i32 @nand_i32_1(i32 %arg1, i32 %arg2) {
- %A = and i32 %arg2, %arg1 ; <i32> [#uses=1]
- %B = xor i32 %A, -1 ; <i32> [#uses=1]
- ret i32 %B
-}
-
-define i32 @nand_i32_2(i32 %arg1, i32 %arg2) {
- %A = and i32 %arg1, %arg2 ; <i32> [#uses=1]
- %B = xor i32 %A, -1 ; <i32> [#uses=1]
- ret i32 %B
-}
-
-define i16 @nand_i16_1(i16 signext %arg1, i16 signext %arg2) signext {
- %A = and i16 %arg2, %arg1 ; <i16> [#uses=1]
- %B = xor i16 %A, -1 ; <i16> [#uses=1]
- ret i16 %B
-}
-
-define i16 @nand_i16_2(i16 signext %arg1, i16 signext %arg2) signext {
- %A = and i16 %arg1, %arg2 ; <i16> [#uses=1]
- %B = xor i16 %A, -1 ; <i16> [#uses=1]
- ret i16 %B
-}
-
-define i16 @nand_i16u_1(i16 zeroext %arg1, i16 zeroext %arg2) zeroext {
- %A = and i16 %arg2, %arg1 ; <i16> [#uses=1]
- %B = xor i16 %A, -1 ; <i16> [#uses=1]
- ret i16 %B
-}
-
-define i16 @nand_i16u_2(i16 zeroext %arg1, i16 zeroext %arg2) zeroext {
- %A = and i16 %arg1, %arg2 ; <i16> [#uses=1]
- %B = xor i16 %A, -1 ; <i16> [#uses=1]
- ret i16 %B
-}
-
-define i8 @nand_i8u_1(i8 zeroext %arg1, i8 zeroext %arg2) zeroext {
- %A = and i8 %arg2, %arg1 ; <i8> [#uses=1]
- %B = xor i8 %A, -1 ; <i8> [#uses=1]
- ret i8 %B
-}
-
-define i8 @nand_i8u_2(i8 zeroext %arg1, i8 zeroext %arg2) zeroext {
- %A = and i8 %arg1, %arg2 ; <i8> [#uses=1]
- %B = xor i8 %A, -1 ; <i8> [#uses=1]
- ret i8 %B
-}
-
-define i8 @nand_i8_1(i8 signext %arg1, i8 signext %arg2) signext {
- %A = and i8 %arg2, %arg1 ; <i8> [#uses=1]
- %B = xor i8 %A, -1 ; <i8> [#uses=1]
- ret i8 %B
-}
-
-define i8 @nand_i8_2(i8 signext %arg1, i8 signext %arg2) signext {
- %A = and i8 %arg1, %arg2 ; <i8> [#uses=1]
- %B = xor i8 %A, -1 ; <i8> [#uses=1]
- ret i8 %B
-}
-
-define i8 @nand_i8_3(i8 %arg1, i8 %arg2) {
- %A = and i8 %arg2, %arg1 ; <i8> [#uses=1]
- %B = xor i8 %A, -1 ; <i8> [#uses=1]
- ret i8 %B
-}
-
-define i8 @nand_i8_4(i8 %arg1, i8 %arg2) {
- %A = and i8 %arg1, %arg2 ; <i8> [#uses=1]
- %B = xor i8 %A, -1 ; <i8> [#uses=1]
- ret i8 %B
-}
View
116 test/CodeGen/Mico32/or_ops.ll
@@ -1,4 +1,4 @@
-; monarch supports retuning <4 x i32> at most.
+; mico32 supports retuning <2 x i32> at most.
; or_ops_pass.ll has supported versions of this test.
; XFAIL: *
; RUN: llvm-as -o - %s | llc -march=mico32
@@ -43,36 +43,6 @@ define <16 x i8> @or_v16i8_2(<16 x i8> %arg1, <16 x i8> %arg2) {
ret <16 x i8> %A
}
-define i32 @or_i32_1(i32 %arg1, i32 %arg2) {
- %A = or i32 %arg2, %arg1
- ret i32 %A
-}
-
-define i32 @or_i32_2(i32 %arg1, i32 %arg2) {
- %A = or i32 %arg1, %arg2
- ret i32 %A
-}
-
-define i16 @or_i16_1(i16 %arg1, i16 %arg2) {
- %A = or i16 %arg2, %arg1
- ret i16 %A
-}
-
-define i16 @or_i16_2(i16 %arg1, i16 %arg2) {
- %A = or i16 %arg1, %arg2
- ret i16 %A
-}
-
-define i8 @or_i8_1(i8 %arg1, i8 %arg2) {
- %A = or i8 %arg2, %arg1
- ret i8 %A
-}
-
-define i8 @or_i8_2(i8 %arg1, i8 %arg2) {
- %A = or i8 %arg1, %arg2
- ret i8 %A
-}
-
; ORC instruction generation:
define <4 x i32> @orc_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
%A = xor <4 x i32> %arg2, < i32 -1, i32 -1, i32 -1, i32 -1 >
@@ -130,60 +100,6 @@ define <16 x i8> @orc_v16i8_3(<16 x i8> %arg1, <16 x i8> %arg2) {
ret <16 x i8> %B
}
-define i32 @orc_i32_1(i32 %arg1, i32 %arg2) {
- %A = xor i32 %arg2, -1
- %B = or i32 %A, %arg1
- ret i32 %B
-}
-
-define i32 @orc_i32_2(i32 %arg1, i32 %arg2) {
- %A = xor i32 %arg1, -1
- %B = or i32 %A, %arg2
- ret i32 %B
-}
-
-define i32 @orc_i32_3(i32 %arg1, i32 %arg2) {
- %A = xor i32 %arg2, -1
- %B = or i32 %arg1, %A
- ret i32 %B
-}
-
-define i16 @orc_i16_1(i16 %arg1, i16 %arg2) {
- %A = xor i16 %arg2, -1
- %B = or i16 %A, %arg1
- ret i16 %B
-}
-
-define i16 @orc_i16_2(i16 %arg1, i16 %arg2) {
- %A = xor i16 %arg1, -1
- %B = or i16 %A, %arg2
- ret i16 %B
-}
-
-define i16 @orc_i16_3(i16 %arg1, i16 %arg2) {
- %A = xor i16 %arg2, -1
- %B = or i16 %arg1, %A
- ret i16 %B
-}
-
-define i8 @orc_i8_1(i8 %arg1, i8 %arg2) {
- %A = xor i8 %arg2, -1
- %B = or i8 %A, %arg1
- ret i8 %B
-}
-
-define i8 @orc_i8_2(i8 %arg1, i8 %arg2) {
- %A = xor i8 %arg1, -1
- %B = or i8 %A, %arg2
- ret i8 %B
-}
-
-define i8 @orc_i8_3(i8 %arg1, i8 %arg2) {
- %A = xor i8 %arg2, -1
- %B = or i8 %arg1, %A
- ret i8 %B
-}
-
; ORI instruction generation (i32 data type):
define <4 x i32> @ori_v4i32_1(<4 x i32> %in) {
%tmp2 = or <4 x i32> %in, < i32 511, i32 511, i32 511, i32 511 >
@@ -205,16 +121,6 @@ define <4 x i32> @ori_v4i32_4(<4 x i32> %in) {
ret <4 x i32> %tmp2
}
-define i32 @ori_u32(i32 zeroext %in) zeroext {
- %tmp37 = or i32 %in, 37 ; <i32> [#uses=1]
- ret i32 %tmp37
-}
-
-define i32 @ori_i32(i32 signext %in) signext {
- %tmp38 = or i32 %in, 37 ; <i32> [#uses=1]
- ret i32 %tmp38
-}
-
; ORHI instruction generation (i16 data type):
define <8 x i16> @orhi_v8i16_1(<8 x i16> %in) {
%tmp2 = or <8 x i16> %in, < i16 511, i16 511, i16 511, i16 511,
@@ -240,16 +146,6 @@ define <8 x i16> @orhi_v8i16_4(<8 x i16> %in) {
ret <8 x i16> %tmp2
}
-define i16 @orhi_u16(i16 zeroext %in) zeroext {
- %tmp37 = or i16 %in, 37 ; <i16> [#uses=1]
- ret i16 %tmp37
-}
-
-define i16 @orhi_i16(i16 signext %in) signext {
- %tmp38 = or i16 %in, 37 ; <i16> [#uses=1]
- ret i16 %tmp38
-}
-
; ORBI instruction generation (i8 data type):
define <16 x i8> @orbi_v16i8(<16 x i8> %in) {
%tmp2 = or <16 x i8> %in, < i8 42, i8 42, i8 42, i8 42, i8 42, i8 42,
@@ -257,13 +153,3 @@ define <16 x i8> @orbi_v16i8(<16 x i8> %in) {
i8 42, i8 42, i8 42, i8 42 >
ret <16 x i8> %tmp2
}
-
-define i8 @orbi_u8(i8 zeroext %in) zeroext {
- %tmp37 = or i8 %in, 37 ; <i8> [#uses=1]
- ret i8 %tmp37
-}
-
-define i8 @orbi_i8(i8 signext %in) signext {
- %tmp38 = or i8 %in, 37 ; <i8> [#uses=1]
- ret i8 %tmp38
-}
View
4 test/CodeGen/Mico32/or_ops_pass.ll
@@ -1,4 +1,4 @@
-; monarch supports retuning <4 x i32> at most.
+; mico32 supports retuning <2 x i32> at most.
; or_ops.ll has unsupported versions of this test.
; RUN: llvm-as -o - %s | llc -march=mico32
; END.
@@ -8,8 +8,6 @@
; RUN: grep ori %t1.s | count 30
; RUN: grep orhi %t1.s | count 30
; RUN: grep orbi %t1.s | count 15
-target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
-target triple = "spu"
; OR instruction generation:
;define <4 x i32> @or_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
View
2  test/CodeGen/Mico32/ord.ll
@@ -1,5 +1,3 @@
-; Monarch doesn't support unordered compares.
-; XFAIL: *
; RUN: llvm-as < %s | llc -march=mico32
; END.
; RUN: llvm-as < %s | llc -march=arm | grep movne | count 1
View
2  test/CodeGen/Mico32/retaddr.ll
@@ -1,5 +1,3 @@
-; Monarch currently deosn't support the llvm.returnaddress intrinsic.
-; XFAIL: *
; RUN: llvm-as < %s | llc -march=mico32
; END.
; RUN: llvm-as < %s | llc -march=ppc32 | grep mflr
View
2  test/CodeGen/Mico32/select_bits.ll
@@ -1,4 +1,4 @@
-; monarch supports returning <4 x i32> at most.
+; mico32 supports returning <2 x i32> at most.
; select_bits_pass.ll has passing versions of this test.
; XFAIL: *
; RUN: llvm-as -o - %s | llc -march=mico32
View
2  test/CodeGen/Mico32/select_bits_pass.ll
@@ -1,4 +1,4 @@
-; monarch supports returning <4 x i32> at most.
+; mico32 supports returning <2 x i32> at most.
; select_bits.ll has unsupported versions of this test.
; RUN: llvm-as -o - %s | llc -march=mico32
; END.
View
2  test/CodeGen/Mico32/trunc.ll
@@ -1,4 +1,4 @@
-; monarch supports returning <4 x i32> at most.
+; mico32 supports returning <2 x i32> at most.
; trunc_pass.ll has supported versions of this test.
; XFAIL: *
; RUN: llvm-as -o - %s | llc -march=mico32
View
2  test/CodeGen/Mico32/trunc_pass.ll
@@ -1,4 +1,4 @@
-; monarch supports returning <4 x i32> at most.
+; mico32 supports returning <2 x i32> at most.
; trunc.ll has unsupported versions of this test.
; RUN: llvm-as -o - %s | llc -march=mico32
; END.
View
2  ...n/Mico32/truncstore-dag-combine2.ll.xfail → ...CodeGen/Mico32/truncstore-dag-combine2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=monarch
+; RUN: llvm-as < %s | llc -march=mico32
; END.
; RUN: llvm-as < %s | llc -march=arm | not grep orr
; RUN: llvm-as < %s | llc -march=arm | not grep mov
View
18 test/CodeGen/Mico32/unaligned_load_store.ll.xfail
@@ -1,18 +0,0 @@
-; RUN: llvm-as < %s | llc -march=monarch
-; END.
-; RUN: llvm-as < %s | \
-; RUN: llc -march=arm -o %t -f
-; RUN: grep ldrb %t | count 4
-; RUN: grep strb %t | count 4
-
-
- %struct.p = type <{ i8, i32 }>
-@t = global %struct.p <{ i8 1, i32 10 }> ; <%struct.p*> [#uses=1]
-@u = weak global %struct.p zeroinitializer ; <%struct.p*> [#uses=1]
-
-define i32 @main() {
-entry:
- %tmp3 = load i32* getelementptr (%struct.p* @t, i32 0, i32 1), align 1 ; <i32> [#uses=2]
- store i32 %tmp3, i32* getelementptr (%struct.p* @u, i32 0, i32 1), align 1
- ret i32 %tmp3
-}
View
2  test/CodeGen/Mico32/unord.ll
@@ -1,5 +1,3 @@
-; monarch does not support unordered compares.
-; XFAIL: *
; RUN: llvm-as < %s | llc -march=mico32
; END.
; RUN: llvm-as < %s | llc -march=arm | grep movne | count 1
View
2  test/CodeGen/Mico32/vargs2.ll.xfail → test/CodeGen/Mico32/vargs2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=monarch
+; RUN: llvm-as < %s | llc -march=mico32
; END.
; RUN: llvm-as < %s | llc -march=thumb
; RUN: llvm-as < %s | llc -march=thumb | \
View
2  test/CodeGen/Mico32/vec_const.ll
@@ -1,4 +1,4 @@
-; monarch only supports returning <4 x i32> at most.
+; mico32 only supports returning <2 x i32> at most.
; XFAIL: *
; RUN: llvm-as -o - %s | llc -march=mico32
; END.
View
2  test/CodeGen/Mico32/vec_insert.ll
@@ -1,4 +1,4 @@
-; monarch only supports returning <4 x i32> at most.
+; mico32 only supports returning <2 x i32> at most.
; XFAIL: *
; RUN: llvm-as < %s | llc -march=mico32
; END.
View
4 test/CodeGen/Mico32/vec_misaligned.ll.xfail → test/CodeGen/Mico32/vec_misaligned.ll
@@ -1,9 +1,7 @@
-; RUN: llvm-as < %s | llc -march=monarch
+; RUN: llvm-as < %s | llc -march=mico32
; END.
; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5
-target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
-target triple = "powerpc-apple-darwin8"
%struct.S2203 = type { %struct.u16qi }
%struct.u16qi = type { <16 x i8> }
@s = weak global %struct.S2203 zeroinitializer ; <%struct.S2203*> [#uses=1]
View
2  test/CodeGen/Mico32/vec_mul.ll
@@ -1,4 +1,4 @@
-; monarch only supports returning <4 x i16>
+; mico32 only supports returning <2 x i16>
; XFAIL: *
; RUN: llvm-as < %s | llc -march=mico32
; END.
View
2  test/CodeGen/Mico32/vecinsert.ll
@@ -1,4 +1,4 @@
-; monarch only supports returning <4 x i32> at most.
+; mico32 only supports returning <2 x i32> at most.
; vecinster_pass.ll has passing versions of this test.
; XFAIL: *
; RUN: llvm-as -o - %s | llc -march=mico32
View
2  test/CodeGen/Mico32/vecinsert_pass.ll
@@ -1,4 +1,4 @@
-; monarch only supports returning <4 x i32> at most.
+; mico32 only supports returning <2 x i32> at most.
; vecinster.ll has failing versions of this test.
; RUN: llvm-as -o - %s | llc -march=mico32
; END.
View
2  test/CodeGen/Mico32/vfp.ll.xfail → test/CodeGen/Mico32/vfp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=monarch
+; RUN: llvm-as < %s | llc -march=mico32
; END.
; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | \
; RUN: grep fabs | count 2
View
45 test/CodeGen/X86/2011-06-14-mmx-inlineasm.ll
@@ -0,0 +1,45 @@
+; RUN: llc -mcpu=i686 -mattr=+mmx < %s | FileCheck %s
+; ModuleID = 'tq.c'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
+target triple = "i386-apple-macosx10.6.6"
+
+%0 = type { x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx }
+
+define i32 @pixman_fill_mmx(i32* nocapture %bits, i32 %stride, i32 %bpp, i32 %x, i32 %y, i32 %width, i32 %height, i32 %xor) nounwind ssp {
+entry:
+ %conv = zext i32 %xor to i64
+ %shl = shl nuw i64 %conv, 32
+ %or = or i64 %shl, %conv
+ %0 = bitcast i64 %or to x86_mmx
+; CHECK: movq [[MMXR:%mm[0-7],]] {{%mm[0-7]}}
+; CHECK-NEXT: movq [[MMXR]] {{%mm[0-7]}}
+; CHECK-NEXT: movq [[MMXR]] {{%mm[0-7]}}
+; CHECK-NEXT: movq [[MMXR]] {{%mm[0-7]}}
+; CHECK-NEXT: movq [[MMXR]] {{%mm[0-7]}}
+; CHECK-NEXT: movq [[MMXR]] {{%mm[0-7]}}
+; CHECK-NEXT: movq [[MMXR]] {{%mm[0-7]}}
+ %1 = tail call %0 asm "movq\09\09$7,\09$0\0Amovq\09\09$7,\09$1\0Amovq\09\09$7,\09$2\0Amovq\09\09$7,\09$3\0Amovq\09\09$7,\09$4\0Amovq\09\09$7,\09$5\0Amovq\09\09$7,\09$6\0A", "=&y,=&y,=&y,=&y,=&y,=&y,=y,y,~{dirflag},~{fpsr},~{flags}"(x86_mmx %0) nounwind, !srcloc !0
+ %asmresult = extractvalue %0 %1, 0
+ %asmresult6 = extractvalue %0 %1, 1
+ %asmresult7 = extractvalue %0 %1, 2
+ %asmresult8 = extractvalue %0 %1, 3
+ %asmresult9 = extractvalue %0 %1, 4
+ %asmresult10 = extractvalue %0 %1, 5
+ %asmresult11 = extractvalue %0 %1, 6
+; CHECK: movq {{%mm[0-7]}},
+; CHECK-NEXT: movq {{%mm[0-7]}},
+; CHECK-NEXT: movq {{%mm[0-7]}},
+; CHECK-NEXT: movq {{%mm[0-7]}},
+; CHECK-NEXT: movq {{%mm[0-7]}},
+; CHECK-NEXT: movq {{%mm[0-7]}},
+; CHECK-NEXT: movq {{%mm[0-7]}},
+; CHECK-NEXT: movq {{%mm[0-7]}},
+ tail call void asm sideeffect "movq\09$1,\09 ($0)\0Amovq\09$2,\09 8($0)\0Amovq\09$3,\0916($0)\0Amovq\09$4,\0924($0)\0Amovq\09$5,\0932($0)\0Amovq\09$6,\0940($0)\0Amovq\09$7,\0948($0)\0Amovq\09$8,\0956($0)\0A", "r,y,y,y,y,y,y,y,y,~{memory},~{dirflag},~{fpsr},~{flags}"(i8* undef, x86_mmx %0, x86_mmx %asmresult, x86_mmx %asmresult6, x86_mmx %asmresult7, x86_mmx %asmresult8, x86_mmx %asmresult9, x86_mmx %asmresult10, x86_mmx %asmresult11) nounwind, !srcloc !1
+ tail call void @llvm.x86.mmx.emms() nounwind
+ ret i32 1
+}
+
+declare void @llvm.x86.mmx.emms() nounwind
+
+!0 = metadata !{i32 888, i32 917, i32 945, i32 973, i32 1001, i32 1029, i32 1057}
+!1 = metadata !{i32 1390, i32 1430, i32 1469, i32 1508, i32 1547, i32 1586, i32 1625, i32 1664}

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