Skip to content
This repository

HTTPS clone URL

Subversion checkout URL

You can clone with HTTPS or Subversion.

Download ZIP
  • 3 commits
  • 9 files changed
  • 0 comments
  • 1 contributor
4  lib/Target/Mico32/Mico32InstrInfo.td
@@ -509,6 +509,10 @@ def SB      :  StoreM<0x0c, "sb      ", truncstorei8>;
509 509
 def SH      :  StoreM<0x03, "sh      ", truncstorei16>;
510 510
 def SW      :  StoreM<0x16, "sw      ", store>;
511 511
 
  512
+// Convert any extend loads into zero extend loads
  513
+def : Pat<(extloadi8  ADDRri:$addr), (i32 (LBU ADDRri:$addr))>;
  514
+def : Pat<(extloadi16 ADDRri:$addr), (i32 (LHU ADDRri:$addr))>;
  515
+
512 516
 
513 517
 //===----------------------------------------------------------------------===//
514 518
 // Mico32 comparison instructions
78  test/CodeGen/Mico32/or_ops_pass.ll
@@ -12,15 +12,15 @@ target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i
12 12
 target triple = "spu"
13 13
 
14 14
 ; OR instruction generation:
15  
-define <4 x i32> @or_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
16  
-        %A = or <4 x i32> %arg1, %arg2
17  
-        ret <4 x i32> %A
18  
-}
  15
+;define <4 x i32> @or_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
  16
+;        %A = or <4 x i32> %arg1, %arg2
  17
+;        ret <4 x i32> %A
  18
+;}
19 19
 
20  
-define <4 x i32> @or_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
21  
-        %A = or <4 x i32> %arg2, %arg1
22  
-        ret <4 x i32> %A
23  
-}
  20
+;define <4 x i32> @or_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
  21
+;        %A = or <4 x i32> %arg2, %arg1
  22
+;        ret <4 x i32> %A
  23
+;}
24 24
 
25 25
 ;define <8 x i16> @or_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) {
26 26
 ;        %A = or <8 x i16> %arg1, %arg2
@@ -73,23 +73,23 @@ define i8 @or_i8_2(i8 %arg1, i8 %arg2) {
73 73
 }
74 74
 
75 75
 ; ORC instruction generation:
76  
-define <4 x i32> @orc_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
77  
-        %A = xor <4 x i32> %arg2, < i32 -1, i32 -1, i32 -1, i32 -1 >
78  
-        %B = or <4 x i32> %arg1, %A
79  
-        ret <4 x i32> %B
80  
-}
  76
+;define <4 x i32> @orc_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
  77
+;        %A = xor <4 x i32> %arg2, < i32 -1, i32 -1, i32 -1, i32 -1 >
  78
+;        %B = or <4 x i32> %arg1, %A
  79
+;        ret <4 x i32> %B
  80
+;}
81 81
 
82  
-define <4 x i32> @orc_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
83  
-        %A = xor <4 x i32> %arg1, < i32 -1, i32 -1, i32 -1, i32 -1 >
84  
-        %B = or <4 x i32> %arg2, %A
85  
-        ret <4 x i32> %B
86  
-}
  82
+;define <4 x i32> @orc_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
  83
+;        %A = xor <4 x i32> %arg1, < i32 -1, i32 -1, i32 -1, i32 -1 >
  84
+;        %B = or <4 x i32> %arg2, %A
  85
+;        ret <4 x i32> %B
  86
+;}
87 87
 
88  
-define <4 x i32> @orc_v4i32_3(<4 x i32> %arg1, <4 x i32> %arg2) {
89  
-        %A = xor <4 x i32> %arg1, < i32 -1, i32 -1, i32 -1, i32 -1 >
90  
-        %B = or <4 x i32> %A, %arg2
91  
-        ret <4 x i32> %B
92  
-}
  88
+;define <4 x i32> @orc_v4i32_3(<4 x i32> %arg1, <4 x i32> %arg2) {
  89
+;        %A = xor <4 x i32> %arg1, < i32 -1, i32 -1, i32 -1, i32 -1 >
  90
+;        %B = or <4 x i32> %A, %arg2
  91
+;        ret <4 x i32> %B
  92
+;}
93 93
 
94 94
 ;define <8 x i16> @orc_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) {
95 95
 ;        %A = xor <8 x i16> %arg2, < i16 -1, i16 -1, i16 -1, i16 -1,
@@ -184,25 +184,25 @@ define i8 @orc_i8_3(i8 %arg1, i8 %arg2) {
184 184
 }
185 185
 
186 186
 ; ORI instruction generation (i32 data type):
187  
-define <4 x i32> @ori_v4i32_1(<4 x i32> %in) {
188  
-        %tmp2 = or <4 x i32> %in, < i32 511, i32 511, i32 511, i32 511 >
189  
-        ret <4 x i32> %tmp2
190  
-}
  187
+;define <4 x i32> @ori_v4i32_1(<4 x i32> %in) {
  188
+;        %tmp2 = or <4 x i32> %in, < i32 511, i32 511, i32 511, i32 511 >
  189
+;        ret <4 x i32> %tmp2
  190
+;}
191 191
 
192  
-define <4 x i32> @ori_v4i32_2(<4 x i32> %in) {
193  
-        %tmp2 = or <4 x i32> %in, < i32 510, i32 510, i32 510, i32 510 >
194  
-        ret <4 x i32> %tmp2
195  
-}
  192
+;define <4 x i32> @ori_v4i32_2(<4 x i32> %in) {
  193
+;        %tmp2 = or <4 x i32> %in, < i32 510, i32 510, i32 510, i32 510 >
  194
+;        ret <4 x i32> %tmp2
  195
+;}
196 196
 
197  
-define <4 x i32> @ori_v4i32_3(<4 x i32> %in) {
198  
-        %tmp2 = or <4 x i32> %in, < i32 -1, i32 -1, i32 -1, i32 -1 >
199  
-        ret <4 x i32> %tmp2
200  
-}
  197
+;define <4 x i32> @ori_v4i32_3(<4 x i32> %in) {
  198
+;        %tmp2 = or <4 x i32> %in, < i32 -1, i32 -1, i32 -1, i32 -1 >
  199
+;        ret <4 x i32> %tmp2
  200
+;}
201 201
 
202  
-define <4 x i32> @ori_v4i32_4(<4 x i32> %in) {
203  
-        %tmp2 = or <4 x i32> %in, < i32 -512, i32 -512, i32 -512, i32 -512 >
204  
-        ret <4 x i32> %tmp2
205  
-}
  202
+;define <4 x i32> @ori_v4i32_4(<4 x i32> %in) {
  203
+;        %tmp2 = or <4 x i32> %in, < i32 -512, i32 -512, i32 -512, i32 -512 >
  204
+;        ret <4 x i32> %tmp2
  205
+;}
206 206
 
207 207
 define i32 @ori_u32(i32 zeroext  %in) zeroext  {
208 208
         %tmp37 = or i32 %in, 37         ; <i32> [#uses=1]
2  test/CodeGen/Mico32/ret_i128_arg2.ll
... ...
@@ -1,3 +1,5 @@
  1
+; mico32 doesn't support directly returning i128 values.
  2
+; XFAIL: *
1 3
 ; RUN: llvm-as < %s | llc -march=mico32
2 4
 
3 5
 define i128 @test_i128(i128 %a1, i128 %a2, i128 %a3) {
2  test/CodeGen/Mico32/select-cc.ll
... ...
@@ -1,3 +1,5 @@
  1
+; mico32 doesn't support directly returning two doubles.
  2
+; XFAIL: *
1 3
 ; RUN: llvm-as < %s | llc -march=mico32
2 4
 ; END.
3 5
 ; RUN: llvm-as < %s | llc -march=ppc32
336  test/CodeGen/Mico32/select_bits_pass.ll
@@ -6,342 +6,6 @@
6 6
 ; RUN: grep selb   %t1.s | count 56
7 7
 
8 8
 ;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
9  
-; v2i64
10  
-;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
11  
-
12  
-; (or (and rC, rB), (and (not rC), rA))
13  
-define <2 x i64> @selectbits_v2i64_01(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
14  
-        %C = and <2 x i64> %rC, %rB
15  
-        %A = xor <2 x i64> %rC, < i64 -1, i64 -1 >
16  
-        %B = and <2 x i64> %A, %rA
17  
-        %D = or <2 x i64> %C, %B
18  
-        ret <2 x i64> %D
19  
-}
20  
-
21  
-; (or (and rB, rC), (and (not rC), rA))
22  
-define <2 x i64> @selectbits_v2i64_02(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
23  
-        %C = and <2 x i64> %rB, %rC
24  
-        %A = xor <2 x i64> %rC, < i64 -1, i64 -1 >
25  
-        %B = and <2 x i64> %A, %rA
26  
-        %D = or <2 x i64> %C, %B
27  
-        ret <2 x i64> %D
28  
-}
29  
-
30  
-; (or (and (not rC), rA), (and rB, rC))
31  
-define <2 x i64> @selectbits_v2i64_03(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
32  
-        %A = xor <2 x i64> %rC, < i64 -1, i64 -1 >
33  
-        %B = and <2 x i64> %A, %rA
34  
-        %C = and <2 x i64> %rB, %rC
35  
-        %D = or <2 x i64> %C, %B
36  
-        ret <2 x i64> %D
37  
-}
38  
-
39  
-; (or (and (not rC), rA), (and rC, rB))
40  
-define <2 x i64> @selectbits_v2i64_04(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
41  
-        %A = xor <2 x i64> %rC, < i64 -1, i64 -1 >
42  
-        %B = and <2 x i64> %A, %rA
43  
-        %C = and <2 x i64> %rC, %rB
44  
-        %D = or <2 x i64> %C, %B
45  
-        ret <2 x i64> %D
46  
-}
47  
-
48  
-; (or (and rC, rB), (and rA, (not rC)))
49  
-define <2 x i64> @selectbits_v2i64_05(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
50  
-        %C = and <2 x i64> %rC, %rB
51  
-        %A = xor <2 x i64> %rC, < i64 -1, i64 -1 >
52  
-        %B = and <2 x i64> %rA, %A
53  
-        %D = or <2 x i64> %C, %B
54  
-        ret <2 x i64> %D
55  
-}
56  
-
57  
-; (or (and rB, rC), (and rA, (not rC)))
58  
-define <2 x i64> @selectbits_v2i64_06(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
59  
-        %C = and <2 x i64> %rB, %rC
60  
-        %A = xor <2 x i64> %rC, < i64 -1, i64 -1 >
61  
-        %B = and <2 x i64> %rA, %A
62  
-        %D = or <2 x i64> %C, %B
63  
-        ret <2 x i64> %D
64  
-}
65  
-
66  
-; (or (and rA, (not rC)), (and rB, rC))
67  
-define <2 x i64> @selectbits_v2i64_07(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
68  
-        %A = xor <2 x i64> %rC, < i64 -1, i64 -1 >
69  
-        %B = and <2 x i64> %rA, %A
70  
-        %C = and <2 x i64> %rB, %rC
71  
-        %D = or <2 x i64> %C, %B
72  
-        ret <2 x i64> %D
73  
-}
74  
-
75  
-; (or (and rA, (not rC)), (and rC, rB))
76  
-define <2 x i64> @selectbits_v2i64_08(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
77  
-        %A = xor <2 x i64> %rC, < i64 -1, i64 -1 >
78  
-        %B = and <2 x i64> %rA, %A
79  
-        %C = and <2 x i64> %rC, %rB
80  
-        %D = or <2 x i64> %C, %B
81  
-        ret <2 x i64> %D
82  
-}
83  
-
84  
-;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
85  
-; v4i32
86  
-;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
87  
-
88  
-; (or (and rC, rB), (and (not rC), rA))
89  
-define <4 x i32> @selectbits_v4i32_01(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) {
90  
-        %C = and <4 x i32> %rC, %rB
91  
-        %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1 >
92  
-        %B = and <4 x i32> %A, %rA
93  
-        %D = or <4 x i32> %C, %B
94  
-        ret <4 x i32> %D
95  
-}
96  
-
97  
-; (or (and rB, rC), (and (not rC), rA))
98  
-define <4 x i32> @selectbits_v4i32_02(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) {
99  
-        %C = and <4 x i32> %rB, %rC
100  
-        %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1 >
101  
-        %B = and <4 x i32> %A, %rA
102  
-        %D = or <4 x i32> %C, %B
103  
-        ret <4 x i32> %D
104  
-}
105  
-
106  
-; (or (and (not rC), rA), (and rB, rC))
107  
-define <4 x i32> @selectbits_v4i32_03(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) {
108  
-        %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1 >
109  
-        %B = and <4 x i32> %A, %rA
110  
-        %C = and <4 x i32> %rB, %rC
111  
-        %D = or <4 x i32> %C, %B
112  
-        ret <4 x i32> %D
113  
-}
114  
-
115  
-; (or (and (not rC), rA), (and rC, rB))
116  
-define <4 x i32> @selectbits_v4i32_04(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) {
117  
-        %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1>
118  
-        %B = and <4 x i32> %A, %rA
119  
-        %C = and <4 x i32> %rC, %rB
120  
-        %D = or <4 x i32> %C, %B
121  
-        ret <4 x i32> %D
122  
-}
123  
-
124  
-; (or (and rC, rB), (and rA, (not rC)))
125  
-define <4 x i32> @selectbits_v4i32_05(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) {
126  
-        %C = and <4 x i32> %rC, %rB
127  
-        %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1>
128  
-        %B = and <4 x i32> %rA, %A
129  
-        %D = or <4 x i32> %C, %B
130  
-        ret <4 x i32> %D
131  
-}
132  
-
133  
-; (or (and rB, rC), (and rA, (not rC)))
134  
-define <4 x i32> @selectbits_v4i32_06(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) {
135  
-        %C = and <4 x i32> %rB, %rC
136  
-        %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1>
137  
-        %B = and <4 x i32> %rA, %A
138  
-        %D = or <4 x i32> %C, %B
139  
-        ret <4 x i32> %D
140  
-}
141  
-
142  
-; (or (and rA, (not rC)), (and rB, rC))
143  
-define <4 x i32> @selectbits_v4i32_07(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) {
144  
-        %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1>
145  
-        %B = and <4 x i32> %rA, %A
146  
-        %C = and <4 x i32> %rB, %rC
147  
-        %D = or <4 x i32> %C, %B
148  
-        ret <4 x i32> %D
149  
-}
150  
-
151  
-; (or (and rA, (not rC)), (and rC, rB))
152  
-define <4 x i32> @selectbits_v4i32_08(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) {
153  
-        %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1>
154  
-        %B = and <4 x i32> %rA, %A
155  
-        %C = and <4 x i32> %rC, %rB
156  
-        %D = or <4 x i32> %C, %B
157  
-        ret <4 x i32> %D
158  
-}
159  
-
160  
-;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
161  
-; v8i16
162  
-;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
163  
-;
164  
-;; (or (and rC, rB), (and (not rC), rA))
165  
-;define <8 x i16> @selectbits_v8i16_01(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) {
166  
-;        %C = and <8 x i16> %rC, %rB
167  
-;        %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1,
168  
-;                                  i16 -1, i16 -1, i16 -1, i16 -1 >
169  
-;        %B = and <8 x i16> %A, %rA
170  
-;        %D = or <8 x i16> %C, %B
171  
-;        ret <8 x i16> %D
172  
-;}
173  
-;
174  
-;; (or (and rB, rC), (and (not rC), rA))
175  
-;define <8 x i16> @selectbits_v8i16_02(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) {
176  
-;        %C = and <8 x i16> %rB, %rC
177  
-;        %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1,
178  
-;                                  i16 -1, i16 -1, i16 -1, i16 -1 >
179  
-;        %B = and <8 x i16> %A, %rA
180  
-;        %D = or <8 x i16> %C, %B
181  
-;        ret <8 x i16> %D
182  
-;}
183  
-;
184  
-;; (or (and (not rC), rA), (and rB, rC))
185  
-;define <8 x i16> @selectbits_v8i16_03(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) {
186  
-;        %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1,
187  
-;                                  i16 -1, i16 -1, i16 -1, i16 -1 >
188  
-;        %B = and <8 x i16> %A, %rA
189  
-;        %C = and <8 x i16> %rB, %rC
190  
-;        %D = or <8 x i16> %C, %B
191  
-;        ret <8 x i16> %D
192  
-;}
193  
-;
194  
-;; (or (and (not rC), rA), (and rC, rB))
195  
-;define <8 x i16> @selectbits_v8i16_04(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) {
196  
-;        %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1,
197  
-;                                  i16 -1, i16 -1, i16 -1, i16 -1 >
198  
-;        %B = and <8 x i16> %A, %rA
199  
-;        %C = and <8 x i16> %rC, %rB
200  
-;        %D = or <8 x i16> %C, %B
201  
-;        ret <8 x i16> %D
202  
-;}
203  
-;
204  
-;; (or (and rC, rB), (and rA, (not rC)))
205  
-;define <8 x i16> @selectbits_v8i16_05(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) {
206  
-;        %C = and <8 x i16> %rC, %rB
207  
-;        %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1,
208  
-;                                  i16 -1, i16 -1, i16 -1, i16 -1 >
209  
-;        %B = and <8 x i16> %rA, %A
210  
-;        %D = or <8 x i16> %C, %B
211  
-;        ret <8 x i16> %D
212  
-;}
213  
-;
214  
-;; (or (and rB, rC), (and rA, (not rC)))
215  
-;define <8 x i16> @selectbits_v8i16_06(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) {
216  
-;        %C = and <8 x i16> %rB, %rC
217  
-;        %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1,
218  
-;                                  i16 -1, i16 -1, i16 -1, i16 -1 >
219  
-;        %B = and <8 x i16> %rA, %A
220  
-;        %D = or <8 x i16> %C, %B
221  
-;        ret <8 x i16> %D
222  
-;}
223  
-;
224  
-;; (or (and rA, (not rC)), (and rB, rC))
225  
-;define <8 x i16> @selectbits_v8i16_07(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) {
226  
-;        %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1,
227  
-;                                  i16 -1, i16 -1, i16 -1, i16 -1 >
228  
-;        %B = and <8 x i16> %rA, %A
229  
-;        %C = and <8 x i16> %rB, %rC
230  
-;        %D = or <8 x i16> %C, %B
231  
-;        ret <8 x i16> %D
232  
-;}
233  
-;
234  
-;; (or (and rA, (not rC)), (and rC, rB))
235  
-;define <8 x i16> @selectbits_v8i16_08(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) {
236  
-;        %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1,
237  
-;                                  i16 -1, i16 -1, i16 -1, i16 -1 >
238  
-;        %B = and <8 x i16> %rA, %A
239  
-;        %C = and <8 x i16> %rC, %rB
240  
-;        %D = or <8 x i16> %C, %B
241  
-;        ret <8 x i16> %D
242  
-;}
243  
-;
244  
-;;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
245  
-;; v16i8
246  
-;;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
247  
-;
248  
-;; (or (and rC, rB), (and (not rC), rA))
249  
-;define <16 x i8> @selectbits_v16i8_01(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) {
250  
-;        %C = and <16 x i8> %rC, %rB
251  
-;        %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1,
252  
-;                                  i8 -1, i8 -1, i8 -1, i8 -1,
253  
-;                                  i8 -1, i8 -1, i8 -1, i8 -1,
254  
-;                                  i8 -1, i8 -1, i8 -1, i8 -1 >
255  
-;        %B = and <16 x i8> %A, %rA
256  
-;        %D = or <16 x i8> %C, %B
257  
-;        ret <16 x i8> %D
258  
-;}
259  
-;
260  
-;; (or (and rB, rC), (and (not rC), rA))
261  
-;define <16 x i8> @selectbits_v16i8_02(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) {
262  
-;        %C = and <16 x i8> %rB, %rC
263  
-;        %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1,
264  
-;                                  i8 -1, i8 -1, i8 -1, i8 -1,
265  
-;                                  i8 -1, i8 -1, i8 -1, i8 -1,
266  
-;                                  i8 -1, i8 -1, i8 -1, i8 -1 >
267  
-;        %B = and <16 x i8> %A, %rA
268  
-;        %D = or <16 x i8> %C, %B
269  
-;        ret <16 x i8> %D
270  
-;}
271  
-;
272  
-;; (or (and (not rC), rA), (and rB, rC))
273  
-;define <16 x i8> @selectbits_v16i8_03(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) {
274  
-;        %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1,
275  
-;                                  i8 -1, i8 -1, i8 -1, i8 -1,
276  
-;                                  i8 -1, i8 -1, i8 -1, i8 -1,
277  
-;                                  i8 -1, i8 -1, i8 -1, i8 -1 >
278  
-;        %B = and <16 x i8> %A, %rA
279  
-;        %C = and <16 x i8> %rB, %rC
280  
-;        %D = or <16 x i8> %C, %B
281  
-;        ret <16 x i8> %D
282  
-;}
283  
-;
284  
-;; (or (and (not rC), rA), (and rC, rB))
285  
-;define <16 x i8> @selectbits_v16i8_04(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) {
286  
-;        %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1,
287  
-;                                  i8 -1, i8 -1, i8 -1, i8 -1,
288  
-;                                  i8 -1, i8 -1, i8 -1, i8 -1,
289  
-;                                  i8 -1, i8 -1, i8 -1, i8 -1 >
290  
-;        %B = and <16 x i8> %A, %rA
291  
-;        %C = and <16 x i8> %rC, %rB
292  
-;        %D = or <16 x i8> %C, %B
293  
-;        ret <16 x i8> %D
294  
-;}
295  
-;
296  
-;; (or (and rC, rB), (and rA, (not rC)))
297  
-;define <16 x i8> @selectbits_v16i8_05(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) {
298  
-;        %C = and <16 x i8> %rC, %rB
299  
-;        %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1,
300  
-;                                  i8 -1, i8 -1, i8 -1, i8 -1,
301  
-;                                  i8 -1, i8 -1, i8 -1, i8 -1,
302  
-;                                  i8 -1, i8 -1, i8 -1, i8 -1 >
303  
-;        %B = and <16 x i8> %rA, %A
304  
-;        %D = or <16 x i8> %C, %B
305  
-;        ret <16 x i8> %D
306  
-;}
307  
-;
308  
-;; (or (and rB, rC), (and rA, (not rC)))
309  
-;define <16 x i8> @selectbits_v16i8_06(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) {
310  
-;        %C = and <16 x i8> %rB, %rC
311  
-;        %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1,
312  
-;                                  i8 -1, i8 -1, i8 -1, i8 -1,
313  
-;                                  i8 -1, i8 -1, i8 -1, i8 -1,
314  
-;                                  i8 -1, i8 -1, i8 -1, i8 -1 >
315  
-;        %B = and <16 x i8> %rA, %A
316  
-;        %D = or <16 x i8> %C, %B
317  
-;        ret <16 x i8> %D
318  
-;}
319  
-;
320  
-;; (or (and rA, (not rC)), (and rB, rC))
321  
-;define <16 x i8> @selectbits_v16i8_07(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) {
322  
-;        %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1,
323  
-;                                  i8 -1, i8 -1, i8 -1, i8 -1,
324  
-;                                  i8 -1, i8 -1, i8 -1, i8 -1,
325  
-;                                  i8 -1, i8 -1, i8 -1, i8 -1 >
326  
-;        %B = and <16 x i8> %rA, %A
327  
-;        %C = and <16 x i8> %rB, %rC
328  
-;        %D = or <16 x i8> %C, %B
329  
-;        ret <16 x i8> %D
330  
-;}
331  
-;
332  
-;; (or (and rA, (not rC)), (and rC, rB))
333  
-;define <16 x i8> @selectbits_v16i8_08(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) {
334  
-;        %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1,
335  
-;                                  i8 -1, i8 -1, i8 -1, i8 -1,
336  
-;                                  i8 -1, i8 -1, i8 -1, i8 -1,
337  
-;                                  i8 -1, i8 -1, i8 -1, i8 -1 >
338  
-;        %B = and <16 x i8> %rA, %A
339  
-;        %C = and <16 x i8> %rC, %rB
340  
-;        %D = or <16 x i8> %C, %B
341  
-;        ret <16 x i8> %D
342  
-;}
343  
-;
344  
-;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
345 9
 ; i32
346 10
 ;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
347 11
 
2  test/CodeGen/Mico32/shift128.ll
... ...
@@ -1,3 +1,5 @@
  1
+; mico32 cann't directly return i128.
  2
+; XFAIL: *
1 3
 ; RUN: llvm-as < %s | llc -march=mico32
2 4
 ; END.
3 5
 ; RUN: llvm-as < %s | llc -march=ppc64 | grep sld | count 5
36  test/CodeGen/Mico32/sp_farith.ll
@@ -10,63 +10,34 @@
10 10
 ;
11 11
 ; This file includes standard floating point arithmetic instructions
12 12
 ; NOTE fdiv is tested separately since it is a compound operation
13  
-target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
14  
-target triple = "spu"
15 13
 
16 14
 define float @fp_add(float %arg1, float %arg2) {
17 15
         %A = fadd float %arg1, %arg2     ; <float> [#uses=1]
18 16
         ret float %A
19 17
 }
20 18
 
21  
-define <4 x float> @fp_add_vec(<4 x float> %arg1, <4 x float> %arg2) {
22  
-        %A = fadd <4 x float> %arg1, %arg2       ; <<4 x float>> [#uses=1]
23  
-        ret <4 x float> %A
24  
-}
25  
-
26 19
 define float @fp_sub(float %arg1, float %arg2) {
27 20
         %A = fsub float %arg1,  %arg2    ; <float> [#uses=1]
28 21
         ret float %A
29 22
 }
30 23
 
31  
-define <4 x float> @fp_sub_vec(<4 x float> %arg1, <4 x float> %arg2) {
32  
-        %A = fsub <4 x float> %arg1,  %arg2      ; <<4 x float>> [#uses=1]
33  
-        ret <4 x float> %A
34  
-}
35  
-
36 24
 define float @fp_mul(float %arg1, float %arg2) {
37 25
         %A = fmul float %arg1,  %arg2    ; <float> [#uses=1]
38 26
         ret float %A
39 27
 }
40 28
 
41  
-define <4 x float> @fp_mul_vec(<4 x float> %arg1, <4 x float> %arg2) {
42  
-        %A = fmul <4 x float> %arg1,  %arg2      ; <<4 x float>> [#uses=1]
43  
-        ret <4 x float> %A
44  
-}
45  
-
46 29
 define float @fp_mul_add(float %arg1, float %arg2, float %arg3) {
47 30
         %A = fmul float %arg1,  %arg2    ; <float> [#uses=1]
48 31
         %B = fadd float %A, %arg3        ; <float> [#uses=1]
49 32
         ret float %B
50 33
 }
51 34
 
52  
-define <4 x float> @fp_mul_add_vec(<4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3) {
53  
-        %A = fmul <4 x float> %arg1,  %arg2      ; <<4 x float>> [#uses=1]
54  
-        %B = fadd <4 x float> %A, %arg3  ; <<4 x float>> [#uses=1]
55  
-        ret <4 x float> %B
56  
-}
57  
-
58 35
 define float @fp_mul_sub(float %arg1, float %arg2, float %arg3) {
59 36
         %A = fmul float %arg1,  %arg2    ; <float> [#uses=1]
60 37
         %B = fsub float %A, %arg3        ; <float> [#uses=1]
61 38
         ret float %B
62 39
 }
63 40
 
64  
-define <4 x float> @fp_mul_sub_vec(<4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3) {
65  
-        %A = fmul <4 x float> %arg1,  %arg2      ; <<4 x float>> [#uses=1]
66  
-        %B = fsub <4 x float> %A, %arg3  ; <<4 x float>> [#uses=1]
67  
-        ret <4 x float> %B
68  
-}
69  
-
70 41
 ; Test the straightforward way of getting fnms
71 42
 ; c - a * b
72 43
 define float @fp_neg_mul_sub_1(float %arg1, float %arg2, float %arg3) {
@@ -83,10 +54,3 @@ define float @fp_neg_mul_sub_2(float %arg1, float %arg2, float %arg3) {
83 54
         %C = fsub float -0.0, %B
84 55
         ret float %C
85 56
 }
86  
-
87  
-define <4 x float> @fp_neg_mul_sub_vec(<4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3) {
88  
-        %A = fmul <4 x float> %arg1,  %arg2
89  
-        %B = fsub <4 x float> %A, %arg3
90  
-        %D = fsub <4 x float> < float -0.0, float -0.0, float -0.0, float -0.0 >, %B
91  
-        ret <4 x float> %D
92  
-}
10  test/CodeGen/Mico32/vec_vrsave.ll
@@ -5,12 +5,12 @@
5 5
 ; RUN: not grep spr %t
6 6
 ; RUN: not grep vrsave %t
7 7
 
8  
-define <4 x i32> @test_rol() {
9  
-        ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 >
  8
+define <2 x i32> @test_rol() {
  9
+        ret <2 x i32> < i32 -11534337, i32 -11534337 >
10 10
 }
11 11
 
12  
-define <4 x i32> @test_arg(<4 x i32> %A, <4 x i32> %B) {
13  
-        %C = add <4 x i32> %A, %B               ; <<4 x i32>> [#uses=1]
14  
-        ret <4 x i32> %C
  12
+define <2 x i32> @test_arg(<2 x i32> %A, <2 x i32> %B) {
  13
+        %C = add <2 x i32> %A, %B               ; <<2 x i32>> [#uses=1]
  14
+        ret <2 x i32> %C
15 15
 }
16 16
 
44  test/CodeGen/Mico32/vecinsert_pass.ll
@@ -37,21 +37,21 @@
37 37
 ;}
38 38
 
39 39
 ; 1574023 -> 0x180487 (ILHU 24/IOHL 1159)
40  
-define <4 x i32> @test_v4i32_1(<4 x i32> %P, i32 %x) {
  40
+define <2 x i32> @test_v4i32_1(<2 x i32> %P, i32 %x) {
41 41
 entry:
42  
-        %tmp1 = insertelement <4 x i32> %P, i32 %x, i32 2
43  
-        %tmp1.1 = insertelement <4 x i32> %tmp1, i32 1574023, i32 1
44  
-        %tmp1.2 = insertelement <4 x i32> %tmp1.1, i32 %x, i32 3
45  
-        ret <4 x i32> %tmp1.2
  42
+        %tmp1 = insertelement <2 x i32> %P, i32 %x, i32 2
  43
+        %tmp1.1 = insertelement <2 x i32> %tmp1, i32 1574023, i32 1
  44
+        %tmp1.2 = insertelement <2 x i32> %tmp1.1, i32 %x, i32 3
  45
+        ret <2 x i32> %tmp1.2
46 46
 }
47 47
 
48 48
 ; Should generate IL for the load
49  
-define <4 x i32> @test_v4i32_2(<4 x i32> %P, i32 %x) {
  49
+define <2 x i32> @test_v2i32_2(<2 x i32> %P, i32 %x) {
50 50
 entry:
51  
-        %tmp1 = insertelement <4 x i32> %P, i32 %x, i32 2
52  
-        %tmp1.1 = insertelement <4 x i32> %tmp1, i32 -39, i32 1
53  
-        %tmp1.2 = insertelement <4 x i32> %tmp1.1, i32 %x, i32 3
54  
-        ret <4 x i32> %tmp1.2
  51
+        %tmp1 = insertelement <2 x i32> %P, i32 %x, i32 2
  52
+        %tmp1.1 = insertelement <2 x i32> %tmp1, i32 -39, i32 1
  53
+        %tmp1.2 = insertelement <2 x i32> %tmp1.1, i32 %x, i32 3
  54
+        ret <2 x i32> %tmp1.2
55 55
 }
56 56
 
57 57
 define void @variable_v16i8_1(<16 x i8>* %a, i32 %i) nounwind {
@@ -74,23 +74,23 @@ entry:
74 74
 	ret void
75 75
 }
76 76
 
77  
-define void @variable_v4i32_1(<4 x i32>* %a, i32 %i) nounwind {
  77
+define void @variable_v2i32_1(<2 x i32>* %a, i32 %i) nounwind {
78 78
 entry:
79  
-	%arrayidx = getelementptr <4 x i32>* %a, i32 %i
80  
-	%tmp2 = load <4 x i32>* %arrayidx
81  
-	%tmp3 = insertelement <4 x i32> %tmp2, i32 1, i32 1
82  
-	%tmp8 = insertelement <4 x i32> %tmp3, i32 2, i32 2
83  
-	store <4 x i32> %tmp8, <4 x i32>* %arrayidx
  79
+	%arrayidx = getelementptr <2 x i32>* %a, i32 %i
  80
+	%tmp2 = load <2 x i32>* %arrayidx
  81
+	%tmp3 = insertelement <2 x i32> %tmp2, i32 1, i32 1
  82
+	%tmp8 = insertelement <2 x i32> %tmp3, i32 2, i32 2
  83
+	store <2 x i32> %tmp8, <2 x i32>* %arrayidx
84 84
 	ret void
85 85
 }
86 86
 
87  
-define void @variable_v4f32_1(<4 x float>* %a, i32 %i) nounwind {
  87
+define void @variable_v2f32_1(<2 x float>* %a, i32 %i) nounwind {
88 88
 entry:
89  
-	%arrayidx = getelementptr <4 x float>* %a, i32 %i
90  
-	%tmp2 = load <4 x float>* %arrayidx
91  
-	%tmp3 = insertelement <4 x float> %tmp2, float 1.000000e+00, i32 1
92  
-	%tmp8 = insertelement <4 x float> %tmp3, float 2.000000e+00, i32 2
93  
-	store <4 x float> %tmp8, <4 x float>* %arrayidx
  89
+	%arrayidx = getelementptr <2 x float>* %a, i32 %i
  90
+	%tmp2 = load <2 x float>* %arrayidx
  91
+	%tmp3 = insertelement <2 x float> %tmp2, float 1.000000e+00, i32 1
  92
+	%tmp8 = insertelement <2 x float> %tmp3, float 2.000000e+00, i32 2
  93
+	store <2 x float> %tmp8, <2 x float>* %arrayidx
94 94
 	ret void
95 95
 }
96 96
 

No commit comments for this range

Something went wrong with that request. Please try again.