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base fork: m-labs/llvm-lm32
base: e91db4e
...
head fork: m-labs/llvm-lm32
compare: a7c424e
  • 3 commits
  • 9 files changed
  • 0 commit comments
  • 1 contributor
View
4 lib/Target/Mico32/Mico32InstrInfo.td
@@ -509,6 +509,10 @@ def SB : StoreM<0x0c, "sb ", truncstorei8>;
def SH : StoreM<0x03, "sh ", truncstorei16>;
def SW : StoreM<0x16, "sw ", store>;
+// Convert any extend loads into zero extend loads
+def : Pat<(extloadi8 ADDRri:$addr), (i32 (LBU ADDRri:$addr))>;
+def : Pat<(extloadi16 ADDRri:$addr), (i32 (LHU ADDRri:$addr))>;
+
//===----------------------------------------------------------------------===//
// Mico32 comparison instructions
View
78 test/CodeGen/Mico32/or_ops_pass.ll
@@ -12,15 +12,15 @@ target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i
target triple = "spu"
; OR instruction generation:
-define <4 x i32> @or_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
- %A = or <4 x i32> %arg1, %arg2
- ret <4 x i32> %A
-}
+;define <4 x i32> @or_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
+; %A = or <4 x i32> %arg1, %arg2
+; ret <4 x i32> %A
+;}
-define <4 x i32> @or_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
- %A = or <4 x i32> %arg2, %arg1
- ret <4 x i32> %A
-}
+;define <4 x i32> @or_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
+; %A = or <4 x i32> %arg2, %arg1
+; ret <4 x i32> %A
+;}
;define <8 x i16> @or_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) {
; %A = or <8 x i16> %arg1, %arg2
@@ -73,23 +73,23 @@ define i8 @or_i8_2(i8 %arg1, i8 %arg2) {
}
; ORC instruction generation:
-define <4 x i32> @orc_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
- %A = xor <4 x i32> %arg2, < i32 -1, i32 -1, i32 -1, i32 -1 >
- %B = or <4 x i32> %arg1, %A
- ret <4 x i32> %B
-}
+;define <4 x i32> @orc_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
+; %A = xor <4 x i32> %arg2, < i32 -1, i32 -1, i32 -1, i32 -1 >
+; %B = or <4 x i32> %arg1, %A
+; ret <4 x i32> %B
+;}
-define <4 x i32> @orc_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
- %A = xor <4 x i32> %arg1, < i32 -1, i32 -1, i32 -1, i32 -1 >
- %B = or <4 x i32> %arg2, %A
- ret <4 x i32> %B
-}
+;define <4 x i32> @orc_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
+; %A = xor <4 x i32> %arg1, < i32 -1, i32 -1, i32 -1, i32 -1 >
+; %B = or <4 x i32> %arg2, %A
+; ret <4 x i32> %B
+;}
-define <4 x i32> @orc_v4i32_3(<4 x i32> %arg1, <4 x i32> %arg2) {
- %A = xor <4 x i32> %arg1, < i32 -1, i32 -1, i32 -1, i32 -1 >
- %B = or <4 x i32> %A, %arg2
- ret <4 x i32> %B
-}
+;define <4 x i32> @orc_v4i32_3(<4 x i32> %arg1, <4 x i32> %arg2) {
+; %A = xor <4 x i32> %arg1, < i32 -1, i32 -1, i32 -1, i32 -1 >
+; %B = or <4 x i32> %A, %arg2
+; ret <4 x i32> %B
+;}
;define <8 x i16> @orc_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) {
; %A = xor <8 x i16> %arg2, < i16 -1, i16 -1, i16 -1, i16 -1,
@@ -184,25 +184,25 @@ define i8 @orc_i8_3(i8 %arg1, i8 %arg2) {
}
; ORI instruction generation (i32 data type):
-define <4 x i32> @ori_v4i32_1(<4 x i32> %in) {
- %tmp2 = or <4 x i32> %in, < i32 511, i32 511, i32 511, i32 511 >
- ret <4 x i32> %tmp2
-}
+;define <4 x i32> @ori_v4i32_1(<4 x i32> %in) {
+; %tmp2 = or <4 x i32> %in, < i32 511, i32 511, i32 511, i32 511 >
+; ret <4 x i32> %tmp2
+;}
-define <4 x i32> @ori_v4i32_2(<4 x i32> %in) {
- %tmp2 = or <4 x i32> %in, < i32 510, i32 510, i32 510, i32 510 >
- ret <4 x i32> %tmp2
-}
+;define <4 x i32> @ori_v4i32_2(<4 x i32> %in) {
+; %tmp2 = or <4 x i32> %in, < i32 510, i32 510, i32 510, i32 510 >
+; ret <4 x i32> %tmp2
+;}
-define <4 x i32> @ori_v4i32_3(<4 x i32> %in) {
- %tmp2 = or <4 x i32> %in, < i32 -1, i32 -1, i32 -1, i32 -1 >
- ret <4 x i32> %tmp2
-}
+;define <4 x i32> @ori_v4i32_3(<4 x i32> %in) {
+; %tmp2 = or <4 x i32> %in, < i32 -1, i32 -1, i32 -1, i32 -1 >
+; ret <4 x i32> %tmp2
+;}
-define <4 x i32> @ori_v4i32_4(<4 x i32> %in) {
- %tmp2 = or <4 x i32> %in, < i32 -512, i32 -512, i32 -512, i32 -512 >
- ret <4 x i32> %tmp2
-}
+;define <4 x i32> @ori_v4i32_4(<4 x i32> %in) {
+; %tmp2 = or <4 x i32> %in, < i32 -512, i32 -512, i32 -512, i32 -512 >
+; ret <4 x i32> %tmp2
+;}
define i32 @ori_u32(i32 zeroext %in) zeroext {
%tmp37 = or i32 %in, 37 ; <i32> [#uses=1]
View
2  test/CodeGen/Mico32/ret_i128_arg2.ll
@@ -1,3 +1,5 @@
+; mico32 doesn't support directly returning i128 values.
+; XFAIL: *
; RUN: llvm-as < %s | llc -march=mico32
define i128 @test_i128(i128 %a1, i128 %a2, i128 %a3) {
View
2  test/CodeGen/Mico32/select-cc.ll
@@ -1,3 +1,5 @@
+; mico32 doesn't support directly returning two doubles.
+; XFAIL: *
; RUN: llvm-as < %s | llc -march=mico32
; END.
; RUN: llvm-as < %s | llc -march=ppc32
View
336 test/CodeGen/Mico32/select_bits_pass.ll
@@ -6,342 +6,6 @@
; RUN: grep selb %t1.s | count 56
;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
-; v2i64
-;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
-
-; (or (and rC, rB), (and (not rC), rA))
-define <2 x i64> @selectbits_v2i64_01(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
- %C = and <2 x i64> %rC, %rB
- %A = xor <2 x i64> %rC, < i64 -1, i64 -1 >
- %B = and <2 x i64> %A, %rA
- %D = or <2 x i64> %C, %B
- ret <2 x i64> %D
-}
-
-; (or (and rB, rC), (and (not rC), rA))
-define <2 x i64> @selectbits_v2i64_02(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
- %C = and <2 x i64> %rB, %rC
- %A = xor <2 x i64> %rC, < i64 -1, i64 -1 >
- %B = and <2 x i64> %A, %rA
- %D = or <2 x i64> %C, %B
- ret <2 x i64> %D
-}
-
-; (or (and (not rC), rA), (and rB, rC))
-define <2 x i64> @selectbits_v2i64_03(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
- %A = xor <2 x i64> %rC, < i64 -1, i64 -1 >
- %B = and <2 x i64> %A, %rA
- %C = and <2 x i64> %rB, %rC
- %D = or <2 x i64> %C, %B
- ret <2 x i64> %D
-}
-
-; (or (and (not rC), rA), (and rC, rB))
-define <2 x i64> @selectbits_v2i64_04(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
- %A = xor <2 x i64> %rC, < i64 -1, i64 -1 >
- %B = and <2 x i64> %A, %rA
- %C = and <2 x i64> %rC, %rB
- %D = or <2 x i64> %C, %B
- ret <2 x i64> %D
-}
-
-; (or (and rC, rB), (and rA, (not rC)))
-define <2 x i64> @selectbits_v2i64_05(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
- %C = and <2 x i64> %rC, %rB
- %A = xor <2 x i64> %rC, < i64 -1, i64 -1 >
- %B = and <2 x i64> %rA, %A
- %D = or <2 x i64> %C, %B
- ret <2 x i64> %D
-}
-
-; (or (and rB, rC), (and rA, (not rC)))
-define <2 x i64> @selectbits_v2i64_06(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
- %C = and <2 x i64> %rB, %rC
- %A = xor <2 x i64> %rC, < i64 -1, i64 -1 >
- %B = and <2 x i64> %rA, %A
- %D = or <2 x i64> %C, %B
- ret <2 x i64> %D
-}
-
-; (or (and rA, (not rC)), (and rB, rC))
-define <2 x i64> @selectbits_v2i64_07(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
- %A = xor <2 x i64> %rC, < i64 -1, i64 -1 >
- %B = and <2 x i64> %rA, %A
- %C = and <2 x i64> %rB, %rC
- %D = or <2 x i64> %C, %B
- ret <2 x i64> %D
-}
-
-; (or (and rA, (not rC)), (and rC, rB))
-define <2 x i64> @selectbits_v2i64_08(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
- %A = xor <2 x i64> %rC, < i64 -1, i64 -1 >
- %B = and <2 x i64> %rA, %A
- %C = and <2 x i64> %rC, %rB
- %D = or <2 x i64> %C, %B
- ret <2 x i64> %D
-}
-
-;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
-; v4i32
-;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
-
-; (or (and rC, rB), (and (not rC), rA))
-define <4 x i32> @selectbits_v4i32_01(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) {
- %C = and <4 x i32> %rC, %rB
- %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1 >
- %B = and <4 x i32> %A, %rA
- %D = or <4 x i32> %C, %B
- ret <4 x i32> %D
-}
-
-; (or (and rB, rC), (and (not rC), rA))
-define <4 x i32> @selectbits_v4i32_02(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) {
- %C = and <4 x i32> %rB, %rC
- %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1 >
- %B = and <4 x i32> %A, %rA
- %D = or <4 x i32> %C, %B
- ret <4 x i32> %D
-}
-
-; (or (and (not rC), rA), (and rB, rC))
-define <4 x i32> @selectbits_v4i32_03(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) {
- %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1 >
- %B = and <4 x i32> %A, %rA
- %C = and <4 x i32> %rB, %rC
- %D = or <4 x i32> %C, %B
- ret <4 x i32> %D
-}
-
-; (or (and (not rC), rA), (and rC, rB))
-define <4 x i32> @selectbits_v4i32_04(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) {
- %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1>
- %B = and <4 x i32> %A, %rA
- %C = and <4 x i32> %rC, %rB
- %D = or <4 x i32> %C, %B
- ret <4 x i32> %D
-}
-
-; (or (and rC, rB), (and rA, (not rC)))
-define <4 x i32> @selectbits_v4i32_05(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) {
- %C = and <4 x i32> %rC, %rB
- %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1>
- %B = and <4 x i32> %rA, %A
- %D = or <4 x i32> %C, %B
- ret <4 x i32> %D
-}
-
-; (or (and rB, rC), (and rA, (not rC)))
-define <4 x i32> @selectbits_v4i32_06(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) {
- %C = and <4 x i32> %rB, %rC
- %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1>
- %B = and <4 x i32> %rA, %A
- %D = or <4 x i32> %C, %B
- ret <4 x i32> %D
-}
-
-; (or (and rA, (not rC)), (and rB, rC))
-define <4 x i32> @selectbits_v4i32_07(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) {
- %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1>
- %B = and <4 x i32> %rA, %A
- %C = and <4 x i32> %rB, %rC
- %D = or <4 x i32> %C, %B
- ret <4 x i32> %D
-}
-
-; (or (and rA, (not rC)), (and rC, rB))
-define <4 x i32> @selectbits_v4i32_08(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) {
- %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1>
- %B = and <4 x i32> %rA, %A
- %C = and <4 x i32> %rC, %rB
- %D = or <4 x i32> %C, %B
- ret <4 x i32> %D
-}
-
-;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
-; v8i16
-;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
-;
-;; (or (and rC, rB), (and (not rC), rA))
-;define <8 x i16> @selectbits_v8i16_01(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) {
-; %C = and <8 x i16> %rC, %rB
-; %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1,
-; i16 -1, i16 -1, i16 -1, i16 -1 >
-; %B = and <8 x i16> %A, %rA
-; %D = or <8 x i16> %C, %B
-; ret <8 x i16> %D
-;}
-;
-;; (or (and rB, rC), (and (not rC), rA))
-;define <8 x i16> @selectbits_v8i16_02(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) {
-; %C = and <8 x i16> %rB, %rC
-; %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1,
-; i16 -1, i16 -1, i16 -1, i16 -1 >
-; %B = and <8 x i16> %A, %rA
-; %D = or <8 x i16> %C, %B
-; ret <8 x i16> %D
-;}
-;
-;; (or (and (not rC), rA), (and rB, rC))
-;define <8 x i16> @selectbits_v8i16_03(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) {
-; %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1,
-; i16 -1, i16 -1, i16 -1, i16 -1 >
-; %B = and <8 x i16> %A, %rA
-; %C = and <8 x i16> %rB, %rC
-; %D = or <8 x i16> %C, %B
-; ret <8 x i16> %D
-;}
-;
-;; (or (and (not rC), rA), (and rC, rB))
-;define <8 x i16> @selectbits_v8i16_04(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) {
-; %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1,
-; i16 -1, i16 -1, i16 -1, i16 -1 >
-; %B = and <8 x i16> %A, %rA
-; %C = and <8 x i16> %rC, %rB
-; %D = or <8 x i16> %C, %B
-; ret <8 x i16> %D
-;}
-;
-;; (or (and rC, rB), (and rA, (not rC)))
-;define <8 x i16> @selectbits_v8i16_05(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) {
-; %C = and <8 x i16> %rC, %rB
-; %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1,
-; i16 -1, i16 -1, i16 -1, i16 -1 >
-; %B = and <8 x i16> %rA, %A
-; %D = or <8 x i16> %C, %B
-; ret <8 x i16> %D
-;}
-;
-;; (or (and rB, rC), (and rA, (not rC)))
-;define <8 x i16> @selectbits_v8i16_06(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) {
-; %C = and <8 x i16> %rB, %rC
-; %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1,
-; i16 -1, i16 -1, i16 -1, i16 -1 >
-; %B = and <8 x i16> %rA, %A
-; %D = or <8 x i16> %C, %B
-; ret <8 x i16> %D
-;}
-;
-;; (or (and rA, (not rC)), (and rB, rC))
-;define <8 x i16> @selectbits_v8i16_07(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) {
-; %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1,
-; i16 -1, i16 -1, i16 -1, i16 -1 >
-; %B = and <8 x i16> %rA, %A
-; %C = and <8 x i16> %rB, %rC
-; %D = or <8 x i16> %C, %B
-; ret <8 x i16> %D
-;}
-;
-;; (or (and rA, (not rC)), (and rC, rB))
-;define <8 x i16> @selectbits_v8i16_08(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) {
-; %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1,
-; i16 -1, i16 -1, i16 -1, i16 -1 >
-; %B = and <8 x i16> %rA, %A
-; %C = and <8 x i16> %rC, %rB
-; %D = or <8 x i16> %C, %B
-; ret <8 x i16> %D
-;}
-;
-;;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
-;; v16i8
-;;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
-;
-;; (or (and rC, rB), (and (not rC), rA))
-;define <16 x i8> @selectbits_v16i8_01(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) {
-; %C = and <16 x i8> %rC, %rB
-; %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1,
-; i8 -1, i8 -1, i8 -1, i8 -1,
-; i8 -1, i8 -1, i8 -1, i8 -1,
-; i8 -1, i8 -1, i8 -1, i8 -1 >
-; %B = and <16 x i8> %A, %rA
-; %D = or <16 x i8> %C, %B
-; ret <16 x i8> %D
-;}
-;
-;; (or (and rB, rC), (and (not rC), rA))
-;define <16 x i8> @selectbits_v16i8_02(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) {
-; %C = and <16 x i8> %rB, %rC
-; %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1,
-; i8 -1, i8 -1, i8 -1, i8 -1,
-; i8 -1, i8 -1, i8 -1, i8 -1,
-; i8 -1, i8 -1, i8 -1, i8 -1 >
-; %B = and <16 x i8> %A, %rA
-; %D = or <16 x i8> %C, %B
-; ret <16 x i8> %D
-;}
-;
-;; (or (and (not rC), rA), (and rB, rC))
-;define <16 x i8> @selectbits_v16i8_03(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) {
-; %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1,
-; i8 -1, i8 -1, i8 -1, i8 -1,
-; i8 -1, i8 -1, i8 -1, i8 -1,
-; i8 -1, i8 -1, i8 -1, i8 -1 >
-; %B = and <16 x i8> %A, %rA
-; %C = and <16 x i8> %rB, %rC
-; %D = or <16 x i8> %C, %B
-; ret <16 x i8> %D
-;}
-;
-;; (or (and (not rC), rA), (and rC, rB))
-;define <16 x i8> @selectbits_v16i8_04(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) {
-; %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1,
-; i8 -1, i8 -1, i8 -1, i8 -1,
-; i8 -1, i8 -1, i8 -1, i8 -1,
-; i8 -1, i8 -1, i8 -1, i8 -1 >
-; %B = and <16 x i8> %A, %rA
-; %C = and <16 x i8> %rC, %rB
-; %D = or <16 x i8> %C, %B
-; ret <16 x i8> %D
-;}
-;
-;; (or (and rC, rB), (and rA, (not rC)))
-;define <16 x i8> @selectbits_v16i8_05(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) {
-; %C = and <16 x i8> %rC, %rB
-; %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1,
-; i8 -1, i8 -1, i8 -1, i8 -1,
-; i8 -1, i8 -1, i8 -1, i8 -1,
-; i8 -1, i8 -1, i8 -1, i8 -1 >
-; %B = and <16 x i8> %rA, %A
-; %D = or <16 x i8> %C, %B
-; ret <16 x i8> %D
-;}
-;
-;; (or (and rB, rC), (and rA, (not rC)))
-;define <16 x i8> @selectbits_v16i8_06(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) {
-; %C = and <16 x i8> %rB, %rC
-; %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1,
-; i8 -1, i8 -1, i8 -1, i8 -1,
-; i8 -1, i8 -1, i8 -1, i8 -1,
-; i8 -1, i8 -1, i8 -1, i8 -1 >
-; %B = and <16 x i8> %rA, %A
-; %D = or <16 x i8> %C, %B
-; ret <16 x i8> %D
-;}
-;
-;; (or (and rA, (not rC)), (and rB, rC))
-;define <16 x i8> @selectbits_v16i8_07(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) {
-; %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1,
-; i8 -1, i8 -1, i8 -1, i8 -1,
-; i8 -1, i8 -1, i8 -1, i8 -1,
-; i8 -1, i8 -1, i8 -1, i8 -1 >
-; %B = and <16 x i8> %rA, %A
-; %C = and <16 x i8> %rB, %rC
-; %D = or <16 x i8> %C, %B
-; ret <16 x i8> %D
-;}
-;
-;; (or (and rA, (not rC)), (and rC, rB))
-;define <16 x i8> @selectbits_v16i8_08(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) {
-; %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1,
-; i8 -1, i8 -1, i8 -1, i8 -1,
-; i8 -1, i8 -1, i8 -1, i8 -1,
-; i8 -1, i8 -1, i8 -1, i8 -1 >
-; %B = and <16 x i8> %rA, %A
-; %C = and <16 x i8> %rC, %rB
-; %D = or <16 x i8> %C, %B
-; ret <16 x i8> %D
-;}
-;
-;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
; i32
;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
View
2  test/CodeGen/Mico32/shift128.ll
@@ -1,3 +1,5 @@
+; mico32 cann't directly return i128.
+; XFAIL: *
; RUN: llvm-as < %s | llc -march=mico32
; END.
; RUN: llvm-as < %s | llc -march=ppc64 | grep sld | count 5
View
36 test/CodeGen/Mico32/sp_farith.ll
@@ -10,63 +10,34 @@
;
; This file includes standard floating point arithmetic instructions
; NOTE fdiv is tested separately since it is a compound operation
-target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
-target triple = "spu"
define float @fp_add(float %arg1, float %arg2) {
%A = fadd float %arg1, %arg2 ; <float> [#uses=1]
ret float %A
}
-define <4 x float> @fp_add_vec(<4 x float> %arg1, <4 x float> %arg2) {
- %A = fadd <4 x float> %arg1, %arg2 ; <<4 x float>> [#uses=1]
- ret <4 x float> %A
-}
-
define float @fp_sub(float %arg1, float %arg2) {
%A = fsub float %arg1, %arg2 ; <float> [#uses=1]
ret float %A
}
-define <4 x float> @fp_sub_vec(<4 x float> %arg1, <4 x float> %arg2) {
- %A = fsub <4 x float> %arg1, %arg2 ; <<4 x float>> [#uses=1]
- ret <4 x float> %A
-}
-
define float @fp_mul(float %arg1, float %arg2) {
%A = fmul float %arg1, %arg2 ; <float> [#uses=1]
ret float %A
}
-define <4 x float> @fp_mul_vec(<4 x float> %arg1, <4 x float> %arg2) {
- %A = fmul <4 x float> %arg1, %arg2 ; <<4 x float>> [#uses=1]
- ret <4 x float> %A
-}
-
define float @fp_mul_add(float %arg1, float %arg2, float %arg3) {
%A = fmul float %arg1, %arg2 ; <float> [#uses=1]
%B = fadd float %A, %arg3 ; <float> [#uses=1]
ret float %B
}
-define <4 x float> @fp_mul_add_vec(<4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3) {
- %A = fmul <4 x float> %arg1, %arg2 ; <<4 x float>> [#uses=1]
- %B = fadd <4 x float> %A, %arg3 ; <<4 x float>> [#uses=1]
- ret <4 x float> %B
-}
-
define float @fp_mul_sub(float %arg1, float %arg2, float %arg3) {
%A = fmul float %arg1, %arg2 ; <float> [#uses=1]
%B = fsub float %A, %arg3 ; <float> [#uses=1]
ret float %B
}
-define <4 x float> @fp_mul_sub_vec(<4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3) {
- %A = fmul <4 x float> %arg1, %arg2 ; <<4 x float>> [#uses=1]
- %B = fsub <4 x float> %A, %arg3 ; <<4 x float>> [#uses=1]
- ret <4 x float> %B
-}
-
; Test the straightforward way of getting fnms
; c - a * b
define float @fp_neg_mul_sub_1(float %arg1, float %arg2, float %arg3) {
@@ -83,10 +54,3 @@ define float @fp_neg_mul_sub_2(float %arg1, float %arg2, float %arg3) {
%C = fsub float -0.0, %B
ret float %C
}
-
-define <4 x float> @fp_neg_mul_sub_vec(<4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3) {
- %A = fmul <4 x float> %arg1, %arg2
- %B = fsub <4 x float> %A, %arg3
- %D = fsub <4 x float> < float -0.0, float -0.0, float -0.0, float -0.0 >, %B
- ret <4 x float> %D
-}
View
10 test/CodeGen/Mico32/vec_vrsave.ll
@@ -5,12 +5,12 @@
; RUN: not grep spr %t
; RUN: not grep vrsave %t
-define <4 x i32> @test_rol() {
- ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 >
+define <2 x i32> @test_rol() {
+ ret <2 x i32> < i32 -11534337, i32 -11534337 >
}
-define <4 x i32> @test_arg(<4 x i32> %A, <4 x i32> %B) {
- %C = add <4 x i32> %A, %B ; <<4 x i32>> [#uses=1]
- ret <4 x i32> %C
+define <2 x i32> @test_arg(<2 x i32> %A, <2 x i32> %B) {
+ %C = add <2 x i32> %A, %B ; <<2 x i32>> [#uses=1]
+ ret <2 x i32> %C
}
View
44 test/CodeGen/Mico32/vecinsert_pass.ll
@@ -37,21 +37,21 @@
;}
; 1574023 -> 0x180487 (ILHU 24/IOHL 1159)
-define <4 x i32> @test_v4i32_1(<4 x i32> %P, i32 %x) {
+define <2 x i32> @test_v4i32_1(<2 x i32> %P, i32 %x) {
entry:
- %tmp1 = insertelement <4 x i32> %P, i32 %x, i32 2
- %tmp1.1 = insertelement <4 x i32> %tmp1, i32 1574023, i32 1
- %tmp1.2 = insertelement <4 x i32> %tmp1.1, i32 %x, i32 3
- ret <4 x i32> %tmp1.2
+ %tmp1 = insertelement <2 x i32> %P, i32 %x, i32 2
+ %tmp1.1 = insertelement <2 x i32> %tmp1, i32 1574023, i32 1
+ %tmp1.2 = insertelement <2 x i32> %tmp1.1, i32 %x, i32 3
+ ret <2 x i32> %tmp1.2
}
; Should generate IL for the load
-define <4 x i32> @test_v4i32_2(<4 x i32> %P, i32 %x) {
+define <2 x i32> @test_v2i32_2(<2 x i32> %P, i32 %x) {
entry:
- %tmp1 = insertelement <4 x i32> %P, i32 %x, i32 2
- %tmp1.1 = insertelement <4 x i32> %tmp1, i32 -39, i32 1
- %tmp1.2 = insertelement <4 x i32> %tmp1.1, i32 %x, i32 3
- ret <4 x i32> %tmp1.2
+ %tmp1 = insertelement <2 x i32> %P, i32 %x, i32 2
+ %tmp1.1 = insertelement <2 x i32> %tmp1, i32 -39, i32 1
+ %tmp1.2 = insertelement <2 x i32> %tmp1.1, i32 %x, i32 3
+ ret <2 x i32> %tmp1.2
}
define void @variable_v16i8_1(<16 x i8>* %a, i32 %i) nounwind {
@@ -74,23 +74,23 @@ entry:
ret void
}
-define void @variable_v4i32_1(<4 x i32>* %a, i32 %i) nounwind {
+define void @variable_v2i32_1(<2 x i32>* %a, i32 %i) nounwind {
entry:
- %arrayidx = getelementptr <4 x i32>* %a, i32 %i
- %tmp2 = load <4 x i32>* %arrayidx
- %tmp3 = insertelement <4 x i32> %tmp2, i32 1, i32 1
- %tmp8 = insertelement <4 x i32> %tmp3, i32 2, i32 2
- store <4 x i32> %tmp8, <4 x i32>* %arrayidx
+ %arrayidx = getelementptr <2 x i32>* %a, i32 %i
+ %tmp2 = load <2 x i32>* %arrayidx
+ %tmp3 = insertelement <2 x i32> %tmp2, i32 1, i32 1
+ %tmp8 = insertelement <2 x i32> %tmp3, i32 2, i32 2
+ store <2 x i32> %tmp8, <2 x i32>* %arrayidx
ret void
}
-define void @variable_v4f32_1(<4 x float>* %a, i32 %i) nounwind {
+define void @variable_v2f32_1(<2 x float>* %a, i32 %i) nounwind {
entry:
- %arrayidx = getelementptr <4 x float>* %a, i32 %i
- %tmp2 = load <4 x float>* %arrayidx
- %tmp3 = insertelement <4 x float> %tmp2, float 1.000000e+00, i32 1
- %tmp8 = insertelement <4 x float> %tmp3, float 2.000000e+00, i32 2
- store <4 x float> %tmp8, <4 x float>* %arrayidx
+ %arrayidx = getelementptr <2 x float>* %a, i32 %i
+ %tmp2 = load <2 x float>* %arrayidx
+ %tmp3 = insertelement <2 x float> %tmp2, float 1.000000e+00, i32 1
+ %tmp8 = insertelement <2 x float> %tmp3, float 2.000000e+00, i32 2
+ store <2 x float> %tmp8, <2 x float>* %arrayidx
ret void
}

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