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  1. 2  CMakeLists.txt
  2. 2  autoconf/config.sub
  3. 12  autoconf/configure.ac
  4. 10  configure
  5. 2  include/llvm/ADT/Triple.h
  6. 2  include/llvm/Support/ELF.h
  7. 12  lib/Support/Triple.cpp
  8. 2  lib/Target/LLVMBuild.txt
  9. 31  lib/Target/LM32/CMakeLists.txt
  10. 12  lib/Target/{Mico32 → LM32}/LLVMBuild.txt
  11. 20  lib/Target/{Mico32/Mico32.h → LM32/LM32.h}
  12. 26  lib/Target/{Mico32/Mico32.td → LM32/LM32.td}
  13. 38  lib/Target/{Mico32/Mico32AsmPrinter.cpp → LM32/LM32AsmPrinter.cpp}
  14. 12  lib/Target/{Mico32/Mico32CallingConv.td → LM32/LM32CallingConv.td}
  15. 48  lib/Target/{Mico32/Mico32ELFWriterInfo.cpp → LM32/LM32ELFWriterInfo.cpp}
  16. 16  lib/Target/{Mico32/Mico32ELFWriterInfo.h → LM32/LM32ELFWriterInfo.h}
  17. 102  lib/Target/{Mico32/Mico32FrameLowering.cpp → LM32/LM32FrameLowering.cpp}
  18. 22  lib/Target/{Mico32/Mico32FrameLowering.h → LM32/LM32FrameLowering.h}
  19. 72  lib/Target/{Mico32/Mico32ISelDAGToDAG.cpp → LM32/LM32ISelDAGToDAG.cpp}
  20. 228  lib/Target/{Mico32/Mico32ISelLowering.cpp → LM32/LM32ISelLowering.cpp}
  21. 26  lib/Target/{Mico32/Mico32ISelLowering.h → LM32/LM32ISelLowering.h}
  22. 52  lib/Target/{Mico32/Mico32InstrFormats.td → LM32/LM32InstrFormats.td}
  23. 106  lib/Target/{Mico32/Mico32InstrInfo.cpp → LM32/LM32InstrInfo.cpp}
  24. 42  lib/Target/{Mico32/Mico32InstrInfo.h → LM32/LM32InstrInfo.h}
  25. 98  lib/Target/{Mico32/Mico32InstrInfo.td → LM32/LM32InstrInfo.td}
  26. 22  lib/Target/{Mico32/Mico32MachineFunctionInfo.h → LM32/LM32MachineFunctionInfo.h}
  27. 80  lib/Target/{Mico32/Mico32RegisterInfo.cpp → LM32/LM32RegisterInfo.cpp}
  28. 20  lib/Target/{Mico32/Mico32RegisterInfo.h → LM32/LM32RegisterInfo.h}
  29. 20  lib/Target/{Mico32/Mico32RegisterInfo.td → LM32/LM32RegisterInfo.td}
  30. 12  lib/Target/{Mico32/Mico32Relocations.h → LM32/LM32Relocations.h}
  31. 10  lib/Target/{Mico32/Mico32Schedule.td → LM32/LM32Schedule.td}
  32. 12  lib/Target/{Mico32/Mico32SelectionDAGInfo.cpp → LM32/LM32SelectionDAGInfo.cpp}
  33. 16  lib/Target/{Mico32/Mico32SelectionDAGInfo.h → LM32/LM32SelectionDAGInfo.h}
  34. 18  lib/Target/{Mico32/Mico32Subtarget.cpp → LM32/LM32Subtarget.cpp}
  35. 16  lib/Target/{Mico32/Mico32Subtarget.h → LM32/LM32Subtarget.h}
  36. 20  lib/Target/{Mico32/Mico32TargetMachine.cpp → LM32/LM32TargetMachine.cpp}
  37. 48  lib/Target/{Mico32/Mico32TargetMachine.h → LM32/LM32TargetMachine.h}
  38. 14  lib/Target/{Mico32/Mico32TargetObjectFile.cpp → LM32/LM32TargetObjectFile.cpp}
  39. 8  lib/Target/{Mico32/Mico32TargetObjectFile.h → LM32/LM32TargetObjectFile.h}
  40. 0  lib/Target/{Mico32 → LM32}/LM32_opcodes.ods
  41. 7  lib/Target/LM32/MCTargetDesc/CMakeLists.txt
  42. 10  lib/Target/{Mico32 → LM32}/MCTargetDesc/LLVMBuild.txt
  43. 8  lib/Target/{Mico32/MCTargetDesc/Mico32MCAsmInfo.cpp → LM32/MCTargetDesc/LM32MCAsmInfo.cpp}
  44. 12  lib/Target/{Mico32/MCTargetDesc/Mico32MCAsmInfo.h → LM32/MCTargetDesc/LM32MCAsmInfo.h}
  45. 56  lib/Target/{Mico32/MCTargetDesc/Mico32MCTargetDesc.cpp → LM32/MCTargetDesc/LM32MCTargetDesc.cpp}
  46. 22  lib/Target/{Mico32/MCTargetDesc/Mico32MCTargetDesc.h → LM32/MCTargetDesc/LM32MCTargetDesc.h}
  47. 4  lib/Target/{Mico32 → LM32}/MCTargetDesc/Makefile
  48. 12  lib/Target/{Mico32 → LM32}/Makefile
  49. 24  lib/Target/{Mico32 → LM32}/README
  50. 6  lib/Target/{Mico32 → LM32}/TargetInfo/CMakeLists.txt
  51. 8  lib/Target/{Mico32 → LM32}/TargetInfo/LLVMBuild.txt
  52. 10  lib/Target/{Mico32/TargetInfo/Mico32TargetInfo.cpp → LM32/TargetInfo/LM32TargetInfo.cpp}
  53. 4  lib/Target/{Mico32 → LM32}/TargetInfo/Makefile
  54. 31  lib/Target/Mico32/CMakeLists.txt
  55. 7  lib/Target/Mico32/MCTargetDesc/CMakeLists.txt
  56. 2  test/CodeGen/{Mico32 → LM32}/2002-04-14-UnexpectedUnsignedType.ll
  57. 2  test/CodeGen/{Mico32 → LM32}/2004-11-29-ShrCrash.ll
  58. 2  test/CodeGen/{Mico32 → LM32}/2004-11-30-shift-crash.ll
  59. 2  test/CodeGen/{Mico32 → LM32}/2004-11-30-shr-var-crash.ll
  60. 2  test/CodeGen/{Mico32 → LM32}/2004-12-12-ZeroSizeCommon.ll
  61. 2  test/CodeGen/{Mico32 → LM32}/2005-01-14-SetSelectCrash.ll
  62. 2  test/CodeGen/{Mico32 → LM32}/2005-01-14-UndefLong.ll
  63. 2  test/CodeGen/{Mico32 → LM32}/2005-08-12-rlwimi-crash.ll
  64. 2  test/CodeGen/{Mico32 → LM32}/2005-09-02-LegalizeDuplicatesCalls.ll
  65. 2  test/CodeGen/{Mico32 → LM32}/2005-10-08-ArithmeticRotate.ll
  66. 2  test/CodeGen/{Mico32 → LM32}/2005-11-30-vastart-crash.ll
  67. 2  test/CodeGen/{Mico32 → LM32}/2005-12-12-MissingFCMov.ll
  68. 2  test/CodeGen/{Mico32 → LM32}/2006-01-11-darwin-fp-argument.ll
  69. 2  test/CodeGen/{Mico32 → LM32}/2006-01-18-MissedGlobal.ll
  70. 2  test/CodeGen/{Mico32 → LM32}/2006-01-20-ShiftPartsCrash.ll
  71. 2  test/CodeGen/{Mico32 → LM32}/2006-01-26-VaargBreak.ll
  72. 2  test/CodeGen/{Mico32 → LM32}/2006-04-04-zextload.ll
  73. 2  test/CodeGen/{Mico32 → LM32}/2006-04-05-splat-ish.ll
  74. 2  test/CodeGen/{Mico32 → LM32}/2006-05-12-rlwimi-crash.ll
  75. 2  test/CodeGen/{Mico32 → LM32}/2006-07-07-ComputeMaskedBits.ll
  76. 2  test/CodeGen/{Mico32 → LM32}/2006-07-19-stwbrx-crash.ll
  77. 4  test/CodeGen/{Mico32 → LM32}/2006-08-11-RetVector.ll
  78. 2  test/CodeGen/{Mico32 → LM32}/2006-08-15-SelectionCrash.ll
  79. 2  test/CodeGen/{Mico32 → LM32}/2006-09-28-shift_64.ll
  80. 2  test/CodeGen/{Mico32 → LM32}/2006-10-11-combiner-aa-regression.ll
  81. 2  test/CodeGen/{Mico32 → LM32}/2006-10-13-Miscompile.ll
  82. 2  test/CodeGen/{Mico32 → LM32}/2006-10-17-brcc-miscompile.ll
  83. 2  test/CodeGen/{Mico32 → LM32}/2006-10-17-ppc64-alloca.ll
  84. 2  test/CodeGen/{Mico32 → LM32}/2006-11-01-vastart.ll
  85. 2  test/CodeGen/{Mico32 → LM32}/2006-11-10-CycleInDAG.ll
  86. 2  test/CodeGen/{Mico32 → LM32}/2006-11-10-DAGCombineMiscompile.ll
  87. 2  test/CodeGen/{Mico32 → LM32}/2006-11-29-AltivecFPSplat.ll
  88. 2  test/CodeGen/{Mico32 → LM32}/2006-12-07-LargeAlloca.ll
  89. 2  test/CodeGen/{Mico32 → LM32}/2006-12-07-SelectCrash.ll
  90. 2  test/CodeGen/{Mico32 → LM32}/2007-01-04-ArgExtension.ll
  91. 2  test/CodeGen/{Mico32 → LM32}/2007-01-19-InfiniteLoop.ll
  92. 2  test/CodeGen/{Mico32 → LM32}/2007-01-31-RegInfoAssert.ll
  93. 2  test/CodeGen/{Mico32 → LM32}/2007-02-02-JoinIntervalsCrash.ll
  94. 2  test/CodeGen/{Mico32 → LM32}/2007-02-16-AlignPacked.ll
  95. 2  test/CodeGen/{Mico32 → LM32}/2007-02-23-lr-saved-twice.ll
  96. 2  test/CodeGen/{Mico32 → LM32}/2007-03-07-CombinerCrash.ll
  97. 2  test/CodeGen/{Mico32 → LM32}/2007-03-13-InstrSched.ll
  98. 2  test/CodeGen/{Mico32 → LM32}/2007-03-21-JoinIntervalsCrash.ll
  99. 2  test/CodeGen/{Mico32 → LM32}/2007-03-24-cntlzd.ll
  100. 2  test/CodeGen/{Mico32 → LM32}/2007-03-27-RegScavengerAssert.ll
  101. 2  test/CodeGen/{Mico32 → LM32}/2007-03-30-RegScavengerAssert.ll
  102. 2  test/CodeGen/{Mico32 → LM32}/2007-04-02-RegScavengerAssert.ll
  103. 2  test/CodeGen/{Mico32 → LM32}/2007-04-03-PEIBug.ll
  104. 2  test/CodeGen/{Mico32 → LM32}/2007-04-03-UndefinedSymbol.ll
  105. 2  test/CodeGen/{Mico32 → LM32}/2007-04-30-CombinerCrash.ll
  106. 2  test/CodeGen/{Mico32 → LM32}/2007-05-03-BadPostIndexedLd.ll
  107. 2  test/CodeGen/{Mico32 → LM32}/2007-05-05-InvalidPushPop.ll
  108. 2  test/CodeGen/{Mico32 → LM32}/2007-05-07-tailmerge-1.ll
  109. 2  test/CodeGen/{Mico32 → LM32}/2007-05-09-tailmerge-2.ll
  110. 2  test/CodeGen/{Mico32 → LM32}/2007-05-14-RegScavengerAssert.ll
  111. 2  test/CodeGen/{Mico32 → LM32}/2007-05-22-tailmerge-3.ll
  112. 2  test/CodeGen/{Mico32 → LM32}/2007-05-23-BadPreIndexedStore.ll
  113. 2  test/CodeGen/{Mico32 → LM32}/2007-05-30-dagcombine-miscomp.ll
  114. 2  test/CodeGen/{Mico32 → LM32}/2007-08-04-CoalescerAssert.ll
  115. 2  test/CodeGen/{Mico32 → LM32}/2007-08-15-ReuseBug.ll
  116. 2  test/CodeGen/{Mico32 → LM32}/2007-09-07-LoadStoreIdxForms.ll
  117. 2  test/CodeGen/{Mico32 → LM32}/2007-09-08-unaligned.ll
  118. 2  test/CodeGen/{Mico32 → LM32}/2007-09-08-unaligned_pass.ll
  119. 2  test/CodeGen/{Mico32 → LM32}/2007-09-12-LiveIntervalsAssert.ll
  120. 2  test/CodeGen/{Mico32 → LM32}/2007-10-18-PtrArithmetic.ll
  121. 2  test/CodeGen/{Mico32 → LM32}/2007-10-21-LocalRegAllocAssert.ll
  122. 2  test/CodeGen/{Mico32 → LM32}/2007-10-21-LocalRegAllocAssert2.ll
  123. 2  test/CodeGen/{Mico32 → LM32}/2007-11-04-CoalescerCrash.ll
  124. 2  test/CodeGen/{Mico32 → LM32}/2007-11-16-landingpad-split.ll
  125. 2  test/CodeGen/{Mico32 → LM32}/2007-11-19-VectorSplitting.ll
  126. 2  test/CodeGen/{Mico32 → LM32}/2007-11-27-mulneg3.ll
  127. 2  test/CodeGen/{Mico32 → LM32}/2008-01-25-EmptyFunction.ll
  128. 2  test/CodeGen/{Mico32 → LM32}/2008-02-04-LocalRegAllocBug.ll
  129. 2  test/CodeGen/{Mico32 → LM32}/2008-02-05-LiveIntervalsAssert.ll
  130. 2  test/CodeGen/{Mico32 → LM32}/2008-02-09-LocalRegAllocAssert.ll
  131. 2  test/CodeGen/{Mico32 → LM32}/2008-02-29-RegAllocLocal.ll
  132. 2  test/CodeGen/{Mico32 → LM32}/2008-03-05-RegScavengerAssert.ll
  133. 2  test/CodeGen/{Mico32 → LM32}/2008-03-05-SxtInRegBug.ll
  134. 2  test/CodeGen/{Mico32 → LM32}/2008-03-06-KillInfo.ll
  135. 2  test/CodeGen/{Mico32 → LM32}/2008-03-07-RegScavengerAssert.ll
  136. 2  test/CodeGen/{Mico32 → LM32}/2008-03-17-RegScavengerCrash.ll
  137. 2  test/CodeGen/{Mico32 → LM32}/2008-03-24-AddressRegImm.ll
  138. 2  test/CodeGen/{Mico32 → LM32}/2008-03-24-CoalescerBug.ll
  139. 2  test/CodeGen/{Mico32 → LM32}/2008-03-26-CoalescerBug.ll
  140. 2  test/CodeGen/{Mico32 → LM32}/2008-04-04-ScavengerAssert.ll
  141. 2  test/CodeGen/{Mico32 → LM32}/2008-04-10-LiveIntervalCrash.ll
  142. 2  test/CodeGen/{Mico32 → LM32}/2008-04-10-ScavengerAssert.ll
  143. 2  test/CodeGen/{Mico32 → LM32}/2008-04-11-PHIofImpDef.ll
  144. 2  test/CodeGen/{Mico32 → LM32}/2008-04-16-CoalescerBug.ll
  145. 2  test/CodeGen/{Mico32 → LM32}/2008-04-23-CoalescerCrash.ll
  146. 2  test/CodeGen/{Mico32 → LM32}/2008-05-19-LiveIntervalsBug.ll
  147. 2  test/CodeGen/{Mico32 → LM32}/2008-05-19-ScavengerAssert.ll
  148. 2  test/CodeGen/{Mico32 → LM32}/2008-06-05-Carry.ll
  149. 2  test/CodeGen/{Mico32 → LM32}/2008-06-23-LiveVariablesCrash.ll
  150. 2  test/CodeGen/{Mico32 → LM32}/2008-07-03-SRet.ll
  151. 2  test/CodeGen/{Mico32 → LM32}/2008-07-05-ByVal.ll
  152. 2  test/CodeGen/{Mico32 → LM32}/2008-07-06-fadd64.ll
  153. 2  test/CodeGen/{Mico32 → LM32}/2008-07-07-FPExtend.ll
  154. 2  test/CodeGen/{Mico32 → LM32}/2008-07-07-Float2Int.ll
  155. 2  test/CodeGen/{Mico32 → LM32}/2008-07-07-IntDoubleConvertions.ll
  156. 4  test/CodeGen/{Mico32 → LM32}/2008-07-10-SplatMiscompile.ll
  157. 2  test/CodeGen/{Mico32 → LM32}/2008-07-15-InternalConstant.ll
  158. 2  test/CodeGen/{Mico32 → LM32}/2008-07-15-SignExtendInreg.ll
  159. 2  test/CodeGen/{Mico32 → LM32}/2008-07-15-SmallSection.ll
  160. 2  test/CodeGen/{Mico32 → LM32}/2008-07-16-SignExtInReg.ll
  161. 2  test/CodeGen/{Mico32 → LM32}/2008-07-17-Fdiv.ll
  162. 2  test/CodeGen/{Mico32 → LM32}/2008-07-22-Cstpool.ll
  163. 2  test/CodeGen/{Mico32 → LM32}/2008-07-23-fpcmp.ll
  164. 2  test/CodeGen/{Mico32 → LM32}/2008-07-24-CodeGenPrepCrash.ll
  165. 2  test/CodeGen/{Mico32 → LM32}/2008-07-24-PPC64-CCBug.ll
  166. 2  test/CodeGen/{Mico32 → LM32}/2008-07-29-icmp.ll
  167. 2  test/CodeGen/{Mico32 → LM32}/2008-07-31-fcopysign.ll
  168. 2  test/CodeGen/{Mico32 → LM32}/2008-08-03-ReturnDouble.ll
  169. 2  test/CodeGen/{Mico32 → LM32}/2008-08-03-fabs64.ll
  170. 2  test/CodeGen/{Mico32 → LM32}/2008-08-04-Bitconvert.ll
  171. 2  test/CodeGen/{Mico32 → LM32}/2008-08-06-Alloca.ll
  172. 2  test/CodeGen/{Mico32 → LM32}/2008-08-07-AsmPrintBug.ll
  173. 2  test/CodeGen/{Mico32 → LM32}/2008-08-07-CC.ll
  174. 2  test/CodeGen/{Mico32 → LM32}/2008-08-07-FPRound.ll
  175. 2  test/CodeGen/{Mico32 → LM32}/2008-08-08-bswap.ll
  176. 2  test/CodeGen/{Mico32 → LM32}/2008-08-08-ctlz.ll
  177. 2  test/CodeGen/{Mico32 → LM32}/2008-09-12-CoalescerBug.ll
  178. 2  test/CodeGen/{Mico32 → LM32}/2008-09-17-CoalescerBug.ll
  179. 2  test/CodeGen/{Mico32 → LM32}/2008-10-13-LegalizerBug.ll
  180. 2  test/CodeGen/{Mico32 → LM32}/2008-11-10-smul_lohi.ll
  181. 2  test/CodeGen/{Mico32 → LM32}/2008-11-10-xint_to_fp.ll
  182. 2  test/CodeGen/{Mico32 → LM32}/2008-11-12-Add128.ll
  183. 2  test/CodeGen/{Mico32 → LM32}/2008-11-17-Shl64.ll
  184. 2  test/CodeGen/{Mico32 → LM32}/2008-12-12-EH.ll
  185. 2  test/CodeGen/{Mico32 → LM32}/2009-01-01-BrCond.ll
  186. 2  test/CodeGen/{Mico32 → LM32}/2009-01-08-Crash.ll
  187. 2  test/CodeGen/{Mico32 → LM32}/2009-01-14-Remat-Crash.ll
  188. 2  test/CodeGen/{Mico32 → LM32}/2009-01-16-DeclareISelBug.ll
  189. 2  test/CodeGen/{Mico32 → LM32}/2009-02-16-SpillerBug.ll
  190. 2  test/CodeGen/{Mico32 → LM32}/2009-02-22-SoftenFloatVaArg.ll
  191. 2  test/CodeGen/{Mico32 → LM32}/2009-02-27-SpillerBug.ll
  192. 2  test/CodeGen/{Mico32 → LM32}/2009-03-07-SpillerBug.ll
  193. 2  test/CodeGen/{Mico32 → LM32}/2009-03-09-AddrModeBug.ll
  194. 2  test/CodeGen/{Mico32 → LM32}/2009-03-17-LSRBug.ll
  195. 2  test/CodeGen/{Mico32 → LM32}/2009-03-27-v2f64-param.ll
  196. 2  test/CodeGen/{Mico32 → LM32}/2009-04-08-AggregateAddr.ll
  197. 2  test/CodeGen/{Mico32 → LM32}/2009-04-08-FREM.ll
  198. 2  test/CodeGen/{Mico32 → LM32}/2009-04-08-FloatUndef.ll
  199. 2  test/CodeGen/{Mico32 → LM32}/2009-06-15-RegScavengerAssert.ll
  200. 2  test/CodeGen/{Mico32 → LM32}/2009-06-19-RegScavengerAssert.ll
  201. 2  test/CodeGen/{Mico32 → LM32}/2009-06-30-RegScavengerAssert.ll
  202. 2  test/CodeGen/{Mico32 → LM32}/2009-07-22-ScavengerAssert.ll
  203. 2  test/CodeGen/{Mico32 → LM32}/2009-08-15-RegScavengerAssert.ll
  204. 2  test/CodeGen/{Mico32 → LM32}/2009-11-13-ScavengerAssert.ll
  205. 2  test/CodeGen/{Mico32 → LM32}/Frames-alloca.ll
  206. 2  test/CodeGen/{Mico32 → LM32}/Frames-large.ll
  207. 2  test/CodeGen/{Mico32 → LM32}/Frames-leaf.ll
  208. 2  test/CodeGen/{Mico32 → LM32}/Frames-small.ll
  209. 2  test/CodeGen/{Mico32 → LM32}/LargeAbsoluteAddr.ll
  210. 0  test/CodeGen/{Mico32 → LM32}/README.txt
  211. 2  test/CodeGen/{Mico32 → LM32}/SwitchLowering.ll
  212. 2  test/CodeGen/{Mico32 → LM32}/add-with-overflow-24.ll
  213. 4  test/CodeGen/{Mico32 → LM32}/add-with-overflow.ll
  214. 4  test/CodeGen/{Mico32 → LM32}/add.ll
  215. 4  test/CodeGen/{Mico32 → LM32}/add128.ll
  216. 2  test/CodeGen/{Mico32 → LM32}/addc-fold2.ll
  217. 2  test/CodeGen/{Mico32 → LM32}/addc.ll
  218. 2  test/CodeGen/{Mico32 → LM32}/addi-reassoc.ll
  219. 2  test/CodeGen/{Mico32 → LM32}/addrmode.ll
  220. 2  test/CodeGen/{Mico32 → LM32}/addsub64.ll
  221. 2  test/CodeGen/{Mico32 → LM32}/aliases.ll
  222. 2  test/CodeGen/{Mico32 → LM32}/align.ll
  223. 2  test/CodeGen/{Mico32 → LM32}/alloca.ll
  224. 2  test/CodeGen/{Mico32 → LM32}/and-branch.ll
  225. 2  test/CodeGen/{Mico32 → LM32}/and-elim.ll
  226. 2  test/CodeGen/{Mico32 → LM32}/and-imm.ll
  227. 2  test/CodeGen/{Mico32 → LM32}/and_add.ll
  228. 4  test/CodeGen/{Mico32 → LM32}/and_ops.ll
  229. 2  test/CodeGen/{Mico32 → LM32}/and_ops2.ll
  230. 2  test/CodeGen/{Mico32 → LM32}/and_ops_pass.ll
  231. 2  test/CodeGen/{Mico32 → LM32}/and_sext.ll
  232. 2  test/CodeGen/{Mico32 → LM32}/and_sra.ll
  233. 2  test/CodeGen/{Mico32 → LM32}/anyext.ll
  234. 2  test/CodeGen/{Mico32 → LM32}/argaddr.ll
  235. 2  test/CodeGen/{Mico32 → LM32}/arguments.ll
  236. 2  test/CodeGen/{Mico32 → LM32}/arguments2.ll
  237. 2  test/CodeGen/{Mico32 → LM32}/arguments3.ll
  238. 2  test/CodeGen/{Mico32 → LM32}/arguments4.ll
  239. 2  test/CodeGen/{Mico32 → LM32}/arguments5.ll
  240. 4  test/CodeGen/{Mico32 → LM32}/arguments6.ll
  241. 2  test/CodeGen/{Mico32 → LM32}/arguments7.ll
  242. 2  test/CodeGen/{Mico32 → LM32}/arguments8.ll
  243. 2  test/CodeGen/{Mico32 → LM32}/arm-negative-stride.ll
  244. 2  test/CodeGen/{Mico32 → LM32}/badCallArgLRLLVM.ll
  245. 2  test/CodeGen/{Mico32 → LM32}/badFoldGEP.ll
  246. 2  test/CodeGen/{Mico32 → LM32}/badarg6.ll
  247. 2  test/CodeGen/{Mico32 → LM32}/badlive.ll
  248. 2  test/CodeGen/{Mico32 → LM32}/basictest.ll
  249. 4  test/CodeGen/{Mico32 → LM32}/bic.ll
  250. 2  test/CodeGen/{Mico32 → LM32}/big-endian-actual-args.ll
  251. 2  test/CodeGen/{Mico32 → LM32}/big-endian-call-result.ll
  252. 2  test/CodeGen/{Mico32 → LM32}/big-endian-formal-args.ll
  253. 2  test/CodeGen/{Mico32 → LM32}/bits.ll
  254. 2  test/CodeGen/{Mico32 → LM32}/bool-to-double.ll
  255. 2  test/CodeGen/{Mico32 → LM32}/bool-vector.ll
  256. 2  test/CodeGen/{Mico32 → LM32}/branch-opt.ll
  257. 2  test/CodeGen/{Mico32 → LM32}/branch-opt2.ll
  258. 2  test/CodeGen/{Mico32 → LM32}/branch.ll
  259. 4  test/CodeGen/{Mico32 → LM32}/bsr.ll
  260. 2  test/CodeGen/{Mico32 → LM32}/bswap-load-store.ll
  261. 2  test/CodeGen/{Mico32 → LM32}/buildvec_canonicalize.ll
  262. 2  test/CodeGen/{Mico32 → LM32}/bx_fold.ll
  263. 2  test/CodeGen/{Mico32 → LM32}/call-ret0.ll
  264. 2  test/CodeGen/{Mico32 → LM32}/call-ret42.ll
  265. 2  test/CodeGen/{Mico32 → LM32}/call-void.ll
  266. 2  test/CodeGen/{Mico32 → LM32}/call.ll
  267. 2  test/CodeGen/{Mico32 → LM32}/call2-ret0.ll
  268. 2  test/CodeGen/{Mico32 → LM32}/call_adj.ll
  269. 4  test/CodeGen/{Mico32 → LM32}/call_indirect.ll
  270. 2  test/CodeGen/{Mico32 → LM32}/call_nolink.ll
  271. 4  test/CodeGen/{Mico32 → LM32}/calls.ll
  272. 2  test/CodeGen/{Mico32 → LM32}/cast-fp.ll
  273. 2  test/CodeGen/{Mico32 → LM32}/clz.ll
  274. 6  test/CodeGen/{Mico32 → LM32}/cmov.ll
  275. 2  test/CodeGen/{Mico32 → LM32}/cmp-cmp.ll
  276. 2  test/CodeGen/{Mico32 → LM32}/cmpbge.ll
  277. 2  test/CodeGen/{Mico32 → LM32}/compare-call.ll
  278. 2  test/CodeGen/{Mico32 → LM32}/compare-call2.ll
  279. 2  test/CodeGen/{Mico32 → LM32}/compare-duplicate.ll
  280. 2  test/CodeGen/{Mico32 → LM32}/compare-simm.ll
  281. 2  test/CodeGen/{Mico32 → LM32}/constants.ll
  282. 2  test/CodeGen/{Mico32 → LM32}/constindices.ll
  283. 2  test/CodeGen/{Mico32 → LM32}/constindices2.ll
  284. 7  test/CodeGen/LM32/convert.sh
  285. 2  test/CodeGen/{Mico32 → LM32}/cos.ll
  286. 2  test/CodeGen/{Mico32 → LM32}/cr_spilling.ll
  287. 2  test/CodeGen/{Mico32 → LM32}/cr_spilling_pass.ll
  288. 2  test/CodeGen/{Mico32 → LM32}/cse-libcalls.ll
  289. 2  test/CodeGen/{Mico32 → LM32}/ctlz.ll
  290. 2  test/CodeGen/{Mico32 → LM32}/ctlz_e.ll
  291. 2  test/CodeGen/{Mico32 → LM32}/ctors_dtors.ll
  292. 2  test/CodeGen/{Mico32 → LM32}/ctpop.ll
  293. 2  test/CodeGen/{Mico32 → LM32}/cttz.ll
  294. 2  test/CodeGen/{Mico32 → LM32}/darwin-labels.ll
  295. 2  test/CodeGen/{Mico32 → LM32}/debug-info.ll
  296. 2  test/CodeGen/{Mico32 → LM32}/delete-node.ll
  297. 2  test/CodeGen/{Mico32 → LM32}/dg.exp
  298. 2  test/CodeGen/{Mico32 → LM32}/div-2.ll
  299. 2  test/CodeGen/{Mico32 → LM32}/div-neg-power-2.ll
  300. 2  test/CodeGen/{Mico32 → LM32}/div.ll
  301. 2  test/CodeGen/{Mico32 → LM32}/dp_farith.ll
  302. 2  test/CodeGen/{Mico32 → LM32}/dyn-stackalloc.ll
2  CMakeLists.txt
@@ -75,7 +75,7 @@ set(LLVM_ALL_TARGETS
75 75
   Hexagon
76 76
   Mips
77 77
   MBlaze
78  
-  Mico32
  78
+  LM32
79 79
   MSP430
80 80
   PowerPC
81 81
   PTX
2  autoconf/config.sub
@@ -262,7 +262,6 @@ case $basic_machine in
262 262
 	| ip2k | iq2000 \
263 263
 	| le32 | le64 \
264 264
 	| lm32 \
265  
-        | mico32 \
266 265
 	| m32c | m32r | m32rle | m68000 | m68k | m88k \
267 266
 	| maxq | mb | microblaze | mcore | mep | metag \
268 267
 	| mips | mipsbe | mipseb | mipsel | mipsle \
@@ -375,7 +374,6 @@ case $basic_machine in
375 374
 	| ip2k-* | iq2000-* \
376 375
 	| le32-* | le64-* \
377 376
 	| lm32-* \
378  
-	| mico32-* \
379 377
 	| m32c-* | m32r-* | m32rle-* \
380 378
 	| m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \
381 379
 	| m88110-* | m88k-* | maxq-* | mcore-* | metag-* | microblaze-* \
12  autoconf/configure.ac
@@ -354,7 +354,7 @@ AC_CACHE_CHECK([target architecture],[llvm_cv_target_arch],
354 354
   sparc*-*)               llvm_cv_target_arch="Sparc" ;;
355 355
   powerpc*-*)             llvm_cv_target_arch="PowerPC" ;;
356 356
   arm*-*)                 llvm_cv_target_arch="ARM" ;;
357  
-  mico32-*)               llvm_cv_target_arch="Mico32" ;;
  357
+  lm32-*)               llvm_cv_target_arch="LM32" ;;
358 358
   mips-*)                 llvm_cv_target_arch="Mips" ;;
359 359
   xcore-*)                llvm_cv_target_arch="XCore" ;;
360 360
   msp430-*)               llvm_cv_target_arch="MSP430" ;;
@@ -502,7 +502,7 @@ else
502 502
     PowerPC)     AC_SUBST(TARGET_HAS_JIT,1) ;;
503 503
     x86_64)      AC_SUBST(TARGET_HAS_JIT,1) ;;
504 504
     ARM)         AC_SUBST(TARGET_HAS_JIT,1) ;;
505  
-    Mico32)      AC_SUBST(TARGET_HAS_JIT,0) ;;
  505
+    LM32)      AC_SUBST(TARGET_HAS_JIT,0) ;;
506 506
     Mips)        AC_SUBST(TARGET_HAS_JIT,1) ;;
507 507
     XCore)       AC_SUBST(TARGET_HAS_JIT,0) ;;
508 508
     MSP430)      AC_SUBST(TARGET_HAS_JIT,0) ;;
@@ -619,14 +619,14 @@ dnl Allow specific targets to be specified for building (or not)
619 619
 TARGETS_TO_BUILD=""
620 620
 AC_ARG_ENABLE([targets],AS_HELP_STRING([--enable-targets],
621 621
     [Build specific host targets: all or target1,target2,... Valid targets are:
622  
-     host, x86, x86_64, sparc, powerpc, arm, mico32, mips, spu, hexagon,
  622
+     host, x86, x86_64, sparc, powerpc, arm, lm32, mips, spu, hexagon,
623 623
      xcore, msp430, ptx, cbe, and cpp (default=all)]),,
624 624
     enableval=all)
625 625
 if test "$enableval" = host-only ; then
626 626
   enableval=host
627 627
 fi
628 628
 case "$enableval" in
629  
-  all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mico32 Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX Hexagon" ;;
  629
+  all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM LM32 Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX Hexagon" ;;
630 630
   *)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
631 631
       case "$a_target" in
632 632
         x86)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -634,7 +634,7 @@ case "$enableval" in
634 634
         sparc)    TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
635 635
         powerpc)  TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
636 636
         arm)      TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
637  
-        mico32)   TARGETS_TO_BUILD="Mico32 $TARGETS_TO_BUILD" ;;
  637
+        lm32)   TARGETS_TO_BUILD="LM32 $TARGETS_TO_BUILD" ;;
638 638
         mips)     TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
639 639
         spu)      TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
640 640
         xcore)    TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
@@ -650,7 +650,7 @@ case "$enableval" in
650 650
             Sparc)       TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
651 651
             PowerPC)     TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
652 652
             ARM)         TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
653  
-            Mico32)      TARGETS_TO_BUILD="Mico32 $TARGETS_TO_BUILD" ;;
  653
+            LM32)      TARGETS_TO_BUILD="LM32 $TARGETS_TO_BUILD" ;;
654 654
             Mips)        TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
655 655
             MBlaze)      TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
656 656
             CellSPU|SPU) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
10  configure
@@ -3880,7 +3880,7 @@ else
3880 3880
   sparc*-*)               llvm_cv_target_arch="Sparc" ;;
3881 3881
   powerpc*-*)             llvm_cv_target_arch="PowerPC" ;;
3882 3882
   arm*-*)                 llvm_cv_target_arch="ARM" ;;
3883  
-  mico32-*)               llvm_cv_target_arch="Mico32" ;;
  3883
+  lm32-*)               llvm_cv_target_arch="LM32" ;;
3884 3884
   mips-*)                 llvm_cv_target_arch="Mips" ;;
3885 3885
   xcore-*)                llvm_cv_target_arch="XCore" ;;
3886 3886
   msp430-*)               llvm_cv_target_arch="MSP430" ;;
@@ -5099,7 +5099,7 @@ else
5099 5099
  ;;
5100 5100
     ARM)         TARGET_HAS_JIT=1
5101 5101
  ;;
5102  
-    Mico32)      TARGET_HAS_JIT=0
  5102
+    LM32)      TARGET_HAS_JIT=0
5103 5103
  ;;
5104 5104
     Mips)        TARGET_HAS_JIT=1
5105 5105
  ;;
@@ -5297,7 +5297,7 @@ if test "$enableval" = host-only ; then
5297 5297
   enableval=host
5298 5298
 fi
5299 5299
 case "$enableval" in
5300  
-  all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mico32 Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX Hexagon" ;;
  5300
+  all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM LM32 Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX Hexagon" ;;
5301 5301
   *)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
5302 5302
       case "$a_target" in
5303 5303
         x86)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -5305,7 +5305,7 @@ case "$enableval" in
5305 5305
         sparc)    TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
5306 5306
         powerpc)  TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
5307 5307
         arm)      TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
5308  
-        mico32)   TARGETS_TO_BUILD="Mico32 $TARGETS_TO_BUILD" ;;
  5308
+        lm32)   TARGETS_TO_BUILD="LM32 $TARGETS_TO_BUILD" ;;
5309 5309
         mips)     TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
5310 5310
         spu)      TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
5311 5311
         xcore)    TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
@@ -5321,7 +5321,7 @@ case "$enableval" in
5321 5321
             Sparc)       TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
5322 5322
             PowerPC)     TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
5323 5323
             ARM)         TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
5324  
-            Mico32)      TARGETS_TO_BUILD="Mico32 $TARGETS_TO_BUILD" ;;
  5324
+            LM32)      TARGETS_TO_BUILD="LM32 $TARGETS_TO_BUILD" ;;
5325 5325
             Mips)        TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
5326 5326
             MBlaze)      TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
5327 5327
             CellSPU|SPU) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
2  include/llvm/ADT/Triple.h
@@ -45,7 +45,7 @@ class Triple {
45 45
 
46 46
     arm,     // ARM; arm, armv.*, xscale
47 47
     cellspu, // CellSPU: spu, cellspu
48  
-    mico32,  // Mico32: mico32
  48
+    lm32,  // LM32: lm32
49 49
     hexagon, // Hexagon: hexagon
50 50
     mips,    // MIPS: mips, mipsallegrex
51 51
     mipsel,  // MIPSEL: mipsel, mipsallegrexel, psp
2  include/llvm/Support/ELF.h
@@ -239,7 +239,7 @@ enum {
239 239
   EM_SCORE7        = 135, // Sunplus S+core7 RISC processor
240 240
   EM_DSP24         = 136, // New Japan Radio (NJR) 24-bit DSP Processor
241 241
   EM_VIDEOCORE3    = 137, // Broadcom VideoCore III processor
242  
-  EM_LATTICEMICO32 = 138, // RISC processor for Lattice FPGA architecture
  242
+  EM_LM32          = 138, // RISC processor for Lattice FPGA architecture
243 243
   EM_SE_C17        = 139, // Seiko Epson C17 family
244 244
   EM_TI_C6000      = 140, // The Texas Instruments TMS320C6000 DSP family
245 245
   EM_TI_C2000      = 141, // The Texas Instruments TMS320C2000 DSP family
12  lib/Support/Triple.cpp
@@ -20,7 +20,7 @@ const char *Triple::getArchTypeName(ArchType Kind) {
20 20
 
21 21
   case arm:     return "arm";
22 22
   case cellspu: return "cellspu";
23  
-  case mico32:  return "mico32";
  23
+  case lm32:  return "lm32";
24 24
   case hexagon: return "hexagon";
25 25
   case mips:    return "mips";
26 26
   case mipsel:  return "mipsel";
@@ -59,7 +59,7 @@ const char *Triple::getArchTypePrefix(ArchType Kind) {
59 59
   case ppc64:
60 60
   case ppc:     return "ppc";
61 61
 
62  
-  case mico32:  return "mico32";
  62
+  case lm32:  return "lm32";
63 63
 
64 64
   case mblaze:  return "mblaze";
65 65
 
@@ -139,8 +139,8 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
139 139
     return arm;
140 140
   if (Name == "cellspu")
141 141
     return cellspu;
142  
-  if (Name == "mico32")
143  
-    return mico32;
  142
+  if (Name == "lm32")
  143
+    return lm32;
144 144
   if (Name == "mips")
145 145
     return mips;
146 146
   if (Name == "mipsel")
@@ -296,8 +296,8 @@ Triple::ArchType Triple::ParseArch(StringRef ArchName) {
296 296
     return cellspu;
297 297
   else if (ArchName == "msp430")
298 298
     return msp430;
299  
-  else if (ArchName == "mico32") 
300  
-    return mico32;
  299
+  else if (ArchName == "lm32") 
  300
+    return lm32;
301 301
   else if (ArchName == "mips" || ArchName == "mipseb" ||
302 302
            ArchName == "mipsallegrex")
303 303
     return mips;
2  lib/Target/LLVMBuild.txt
@@ -16,7 +16,7 @@
16 16
 ;===------------------------------------------------------------------------===;
17 17
 
18 18
 [common]
19  
-subdirectories = ARM CBackend CellSPU CppBackend Hexagon MBlaze Mico32 MSP430 Mips PTX PowerPC Sparc X86 XCore
  19
+subdirectories = ARM CBackend CellSPU CppBackend Hexagon MBlaze LM32 MSP430 Mips PTX PowerPC Sparc X86 XCore
20 20
 
21 21
 ; This is a special group whose required libraries are extended (by llvm-build)
22 22
 ; with the best execution engine (the native JIT, if available, or the
31  lib/Target/LM32/CMakeLists.txt
... ...
@@ -0,0 +1,31 @@
  1
+set(LLVM_TARGET_DEFINITIONS LM32.td)
  2
+
  3
+tablegen(LLVM LM32GenRegisterInfo.inc -gen-register-info)
  4
+tablegen(LLVM LM32GenInstrInfo.inc -gen-instr-info)
  5
+tablegen(LLVM LM32GenCodeEmitter.inc -gen-emitter)
  6
+tablegen(LLVM LM32GenAsmWriter.inc -gen-asm-writer)
  7
+tablegen(LLVM LM32GenAsmMatcher.inc -gen-asm-matcher)
  8
+tablegen(LLVM LM32GenDAGISel.inc -gen-dag-isel)
  9
+tablegen(LLVM LM32GenCallingConv.inc -gen-callingconv)
  10
+tablegen(LLVM LM32GenSubtargetInfo.inc -gen-subtarget)
  11
+tablegen(LLVM LM32GenIntrinsics.inc -gen-tgt-intrinsic)
  12
+tablegen(LLVM LM32GenEDInfo.inc -gen-enhanced-disassembly-info)
  13
+add_public_tablegen_target(LM32CommonTableGen)
  14
+
  15
+add_llvm_target(LM32CodeGen
  16
+  LM32AsmPrinter.cpp
  17
+  LM32ELFWriterInfo.cpp
  18
+  LM32FrameLowering.cpp
  19
+  LM32InstrInfo.cpp
  20
+  LM32ISelDAGToDAG.cpp
  21
+  LM32ISelLowering.cpp
  22
+  LM32RegisterInfo.cpp
  23
+  LM32SelectionDAGInfo.cpp
  24
+  LM32Subtarget.cpp
  25
+  LM32TargetMachine.cpp
  26
+  LM32TargetObjectFile.cpp
  27
+  )
  28
+
  29
+add_subdirectory(TargetInfo)
  30
+add_subdirectory(MCTargetDesc)
  31
+
12  lib/Target/Mico32/LLVMBuild.txt → lib/Target/LM32/LLVMBuild.txt
... ...
@@ -1,4 +1,4 @@
1  
-;===- ./lib/Target/Mico32/LLVMBuild.txt ------------------------*- Conf -*--===;
  1
+;===- ./lib/Target/LM32/LLVMBuild.txt --------------------------*- Conf -*--===;
2 2
 ;
3 3
 ;                     The LLVM Compiler Infrastructure
4 4
 ;
@@ -20,7 +20,7 @@ subdirectories = MCTargetDesc TargetInfo
20 20
 
21 21
 [component_0]
22 22
 type = TargetGroup
23  
-name = Mico32
  23
+name = LM32
24 24
 parent = Target
25 25
 has_asmparser = 1
26 26
 has_asmprinter = 1
@@ -28,8 +28,8 @@ has_disassembler = 1
28 28
 
29 29
 [component_1]
30 30
 type = Library
31  
-name = Mico32CodeGen
32  
-parent = Mico32
33  
-required_libraries = CodeGen Core Mico32Desc Mico32Info MC SelectionDAG Support Target
34  
-add_to_library_groups = Mico32
  31
+name = LM32CodeGen
  32
+parent = LM32
  33
+required_libraries = CodeGen Core LM32Desc LM32Info MC SelectionDAG Support Target
  34
+add_to_library_groups = LM32
35 35
 
20  lib/Target/Mico32/Mico32.h → lib/Target/LM32/LM32.h
... ...
@@ -1,4 +1,4 @@
1  
-//===-- Mico32.h - Top-level interface for Mico32 ---------------*- C++ -*-===//
  1
+//===-- LM32.h - Top-level interface for LM32 -------------------*- C++ -*-===//
2 2
 //
3 3
 //                     The LLVM Compiler Infrastructure
4 4
 //
@@ -8,33 +8,33 @@
8 8
 //===----------------------------------------------------------------------===//
9 9
 //
10 10
 // This file contains the entry points for global functions defined in
11  
-// the LLVM Mico32 back-end.
  11
+// the LLVM LM32 back-end.
12 12
 //
13 13
 //===----------------------------------------------------------------------===//
14 14
 
15  
-#ifndef TARGET_MICO32_H
16  
-#define TARGET_MICO32_H
  15
+#ifndef TARGET_LM32_H
  16
+#define TARGET_LM32_H
17 17
 
18  
-#include "MCTargetDesc/Mico32MCTargetDesc.h"
  18
+#include "MCTargetDesc/LM32MCTargetDesc.h"
19 19
 #include "llvm/Target/TargetMachine.h"
20 20
 
21 21
 namespace llvm {
22  
-  class Mico32TargetMachine;
  22
+  class LM32TargetMachine;
23 23
   class FunctionPass;
24 24
   class MachineCodeEmitter;
25 25
   class MCCodeEmitter;
26 26
   //class TargetAsmBackend;
27 27
   class formatted_raw_ostream;
28 28
 
29  
-  MCCodeEmitter *createMico32MCCodeEmitter(const Target &,
  29
+  MCCodeEmitter *createLM32MCCodeEmitter(const Target &,
30 30
                                            TargetMachine &TM,
31 31
                                            MCContext &Ctx);
32 32
 
33  
-  //TargetAsmBackend *createMico32AsmBackend(const Target &, const std::string &);
  33
+  //TargetAsmBackend *createLM32AsmBackend(const Target &, const std::string &);
34 34
 
35  
-  FunctionPass *createMico32ISelDag(Mico32TargetMachine &TM);
  35
+  FunctionPass *createLM32ISelDag(LM32TargetMachine &TM);
36 36
 
37  
-  extern Target TheMico32Target;
  37
+  extern Target TheLM32Target;
38 38
 } // end namespace llvm;
39 39
 
40 40
 #endif
26  lib/Target/Mico32/Mico32.td → lib/Target/LM32/LM32.td
... ...
@@ -1,4 +1,4 @@
1  
-//===- Mico32.td - Describe the Mico32 Target Machine ------*- tblgen -*-==//
  1
+//===- LM32.td - Describe the LM32 Target Machine -------------*- tblgen -*-==//
2 2
 //
3 3
 //                     The LLVM Compiler Infrastructure
4 4
 //
@@ -6,7 +6,7 @@
6 6
 // License. See LICENSE.TXT for details.
7 7
 //
8 8
 //===----------------------------------------------------------------------===//
9  
-// This is the top level entry point for the Mico32 target.
  9
+// This is the top level entry point for the LM32 target.
10 10
 //===----------------------------------------------------------------------===//
11 11
 
12 12
 //===----------------------------------------------------------------------===//
@@ -19,12 +19,12 @@ include "llvm/Target/Target.td"
19 19
 // Register File, Calling Conv, Instruction Descriptions
20 20
 //===----------------------------------------------------------------------===//
21 21
 
22  
-include "Mico32RegisterInfo.td"
23  
-include "Mico32Schedule.td"
24  
-include "Mico32InstrInfo.td"
25  
-include "Mico32CallingConv.td"
  22
+include "LM32RegisterInfo.td"
  23
+include "LM32Schedule.td"
  24
+include "LM32InstrInfo.td"
  25
+include "LM32CallingConv.td"
26 26
 
27  
-def Mico32InstrInfo : InstrInfo;
  27
+def LM32InstrInfo : InstrInfo;
28 28
 
29 29
 //===----------------------------------------------------------------------===//
30 30
 // Subtarget Features. 
@@ -51,17 +51,17 @@ def FeatureSPBias :
51 51
                    "SP points to last used 32 bit word on stack (not ABI compilant)">;
52 52
 
53 53
 //===----------------------------------------------------------------------===//
54  
-// Mico32 supported processors.
  54
+// LM32 supported processors.
55 55
 //===----------------------------------------------------------------------===//
56 56
 
57  
-def : Processor< "mico32", Mico32Itineraries, []>;
  57
+def : Processor< "lm32", LM32Itineraries, []>;
58 58
 
59 59
 
60 60
 //===----------------------------------------------------------------------===//
61 61
 // Use an MC assembly printer
62 62
 //===----------------------------------------------------------------------===//
63 63
 
64  
-//def Mico32AsmWriter : AsmWriter {
  64
+//def LM32AsmWriter : AsmWriter {
65 65
 //  string AsmWriterClassName  = "InstPrinter";
66 66
 //  bit isMCAsmWriter = 1;
67 67
 //}
@@ -70,8 +70,8 @@ def : Processor< "mico32", Mico32Itineraries, []>;
70 70
 // Target Declaration
71 71
 //===----------------------------------------------------------------------===//
72 72
 
73  
-def Mico32 : Target {
74  
-  let InstructionSet = Mico32InstrInfo;
75  
-//  let AssemblyWriters = [Mico32AsmWriter];
  73
+def LM32 : Target {
  74
+  let InstructionSet = LM32InstrInfo;
  75
+//  let AssemblyWriters = [LM32AsmWriter];
76 76
 }
77 77
 
38  lib/Target/Mico32/Mico32AsmPrinter.cpp → lib/Target/LM32/LM32AsmPrinter.cpp
... ...
@@ -1,4 +1,4 @@
1  
-//===-- Mico32AsmPrinter.cpp - Mico32 LLVM assembly writer ------------===//
  1
+//===-- LM32AsmPrinter.cpp - LM32 LLVM assembly writer --------------------===//
2 2
 //
3 3
 //                     The LLVM Compiler Infrastructure
4 4
 //
@@ -8,13 +8,13 @@
8 8
 //===----------------------------------------------------------------------===//
9 9
 //
10 10
 // This file contains a printer that converts from our internal representation
11  
-// of machine-dependent LLVM code to GAS-format Mico32 assembly language.
  11
+// of machine-dependent LLVM code to GAS-format LM32 assembly language.
12 12
 //
13 13
 //===----------------------------------------------------------------------===//
14 14
 
15 15
 #define DEBUG_TYPE "asm-printer"
16  
-#include "Mico32.h"
17  
-#include "Mico32InstrInfo.h"
  16
+#include "LM32.h"
  17
+#include "LM32InstrInfo.h"
18 18
 #include "llvm/Constants.h"
19 19
 #include "llvm/DerivedTypes.h"
20 20
 #include "llvm/Module.h"
@@ -37,17 +37,17 @@
37 37
 using namespace llvm;
38 38
 
39 39
 namespace {
40  
-  class Mico32AsmPrinter : public AsmPrinter {
  40
+  class LM32AsmPrinter : public AsmPrinter {
41 41
   public:
42  
-    Mico32AsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
  42
+    LM32AsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
43 43
       : AsmPrinter(TM, Streamer) {}
44 44
 
45 45
     virtual const char *getPassName() const {
46  
-      return "Mico32 Assembly Printer";
  46
+      return "LM32 Assembly Printer";
47 47
     }
48 48
 
49 49
     // The printXXXOperand functions are referenced in the
50  
-    // Mico32InstrInfo.td file.
  50
+    // LM32InstrInfo.td file.
51 51
     void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
52 52
     void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O);
53 53
     void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
@@ -78,13 +78,13 @@ namespace {
78 78
   };
79 79
 } // end of anonymous namespace
80 80
 
81  
-#include "Mico32GenAsmWriter.inc"
  81
+#include "LM32GenAsmWriter.inc"
82 82
 
83  
-extern "C" void LLVMInitializeMico32AsmPrinter() {
84  
-  RegisterAsmPrinter<Mico32AsmPrinter> X(TheMico32Target);
  83
+extern "C" void LLVMInitializeLM32AsmPrinter() {
  84
+  RegisterAsmPrinter<LM32AsmPrinter> X(TheLM32Target);
85 85
 }
86 86
 
87  
-void Mico32AsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
  87
+void LM32AsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
88 88
                                         raw_ostream &O)
89 89
 {
90 90
   const MachineOperand &MO = MI->getOperand(opNum);
@@ -101,7 +101,7 @@ void Mico32AsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
101 101
 //  <..."add ${addr:arith}, $dst", [(set IntRegs:$dst, ADDRri:$addr)..>;
102 102
 // will cause TableGen to pass the modifier "arith" to printMemOperand.
103 103
 // See SPARC for example.
104  
-void Mico32AsmPrinter::
  104
+void LM32AsmPrinter::
105 105
 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
106 106
                 const char *Modifier)
107 107
 {
@@ -113,7 +113,7 @@ printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
113 113
 }
114 114
 
115 115
 
116  
-void Mico32AsmPrinter::
  116
+void LM32AsmPrinter::
117 117
 printOperand(const MachineInstr *MI, int opNum, raw_ostream &O)
118 118
 {
119 119
   const MachineOperand &MO = MI->getOperand(opNum);
@@ -151,7 +151,7 @@ printOperand(const MachineInstr *MI, int opNum, raw_ostream &O)
151 151
   }
152 152
 }
153 153
 
154  
-void Mico32AsmPrinter::
  154
+void LM32AsmPrinter::
155 155
 printS16ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
156 156
 {
157 157
   O << (short) MI->getOperand(OpNo).getImm();
@@ -161,7 +161,7 @@ printS16ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
161 161
 
162 162
 /// PrintAsmOperand - Print out an operand for an inline asm expression.
163 163
 ///
164  
-bool Mico32AsmPrinter::
  164
+bool LM32AsmPrinter::
165 165
 PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant,
166 166
                 const char *ExtraCode, raw_ostream &O)
167 167
 {
@@ -180,7 +180,7 @@ PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant,
180 180
   return false;
181 181
 }
182 182
 
183  
-bool Mico32AsmPrinter::
  183
+bool LM32AsmPrinter::
184 184
 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
185 185
                       unsigned AsmVariant, const char *ExtraCode,
186 186
                       raw_ostream &O)
@@ -195,7 +195,7 @@ PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
195 195
   return false;
196 196
 }
197 197
 
198  
-void Mico32AsmPrinter::
  198
+void LM32AsmPrinter::
199 199
 printSymbolHi(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
200 200
 {
201 201
   if (MI->getOperand(OpNo).isImm()) {
@@ -208,7 +208,7 @@ printSymbolHi(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
208 208
   }
209 209
 }
210 210
 
211  
-void Mico32AsmPrinter::
  211
+void LM32AsmPrinter::
212 212
 printSymbolLo(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
213 213
 {
214 214
   if (MI->getOperand(OpNo).isImm()) {
12  lib/Target/Mico32/Mico32CallingConv.td → lib/Target/LM32/LM32CallingConv.td
... ...
@@ -1,4 +1,4 @@
1  
-//===------- Mico32.td - Calling Conventions for Mico32 --*- C++ --------*-===//
  1
+//===-- LM32CallingConv.td - Calling Conventions for LM32 -------*- C++ -*-===//
2 2
 // 
3 3
 //                     The LLVM Compiler Infrastructure
4 4
 //
@@ -7,12 +7,12 @@
7 7
 // 
8 8
 //===----------------------------------------------------------------------===//
9 9
 //
10  
-// This describes the calling conventions for the Mico32 architecture.
  10
+// This describes the calling conventions for the LM32 architecture.
11 11
 //
12 12
 //===----------------------------------------------------------------------===//
13 13
 
14 14
 //===----------------------------------------------------------------------===//
15  
-// Mico32 Calling Conventions
  15
+// LM32 Calling Conventions
16 16
 //===----------------------------------------------------------------------===//
17 17
 
18 18
 // Note it looks like LLVM supports passing or return stucture arguments
@@ -24,7 +24,7 @@
24 24
 // See also: http://nondot.org/sabre/LLVMNotes/CustomCallingConventions.txt
25 25
 
26 26
 
27  
-def CC_Mico32 : CallingConv<[
  27
+def CC_LM32 : CallingConv<[
28 28
   // Promote i8/i16 arguments to i32.
29 29
   CCIfType<[i8, i16], CCPromoteToType<i32>>,
30 30
 
@@ -42,8 +42,8 @@ def CC_Mico32 : CallingConv<[
42 42
 // dependent codegen should not have to do anything special to handle sret.
43 43
 
44 44
 // Note the return registers (and caller saves) should 
45  
-// be "Defs" in the call instruction in Mico32InstrInfo.td.
46  
-def RetCC_Mico32 : CallingConv<[
  45
+// be "Defs" in the call instruction in LM32InstrInfo.td.
  46
+def RetCC_LM32 : CallingConv<[
47 47
   // i32 and f32 are returned in registers R1, R2.
48 48
   CCIfType<[i32, f32], CCAssignToReg<[R1, R2]>>
49 49
 ]>;
48  lib/Target/Mico32/Mico32ELFWriterInfo.cpp → lib/Target/LM32/LM32ELFWriterInfo.cpp
... ...
@@ -1,4 +1,4 @@
1  
-//===-- Mico32ELFWriterInfo.cpp - ELF Writer Info for the Mico32 backend --===//
  1
+//===-- LM32ELFWriterInfo.cpp - ELF Writer Info for the LM32 backend --===//
2 2
 //
3 3
 //                     The LLVM Compiler Infrastructure
4 4
 //
@@ -7,12 +7,12 @@
7 7
 //
8 8
 //===----------------------------------------------------------------------===//
9 9
 //
10  
-// This file implements ELF writer information for the Mico32 backend.
  10
+// This file implements ELF writer information for the LM32 backend.
11 11
 //
12 12
 //===----------------------------------------------------------------------===//
13 13
 
14  
-#include "Mico32ELFWriterInfo.h"
15  
-#include "Mico32Relocations.h"
  14
+#include "LM32ELFWriterInfo.h"
  15
+#include "LM32Relocations.h"
16 16
 #include "llvm/Function.h"
17 17
 #include "llvm/Support/ELF.h"
18 18
 #include "llvm/Support/ErrorHandling.h"
@@ -22,45 +22,45 @@
22 22
 using namespace llvm;
23 23
 
24 24
 //===----------------------------------------------------------------------===//
25  
-//  Implementation of the Mico32ELFWriterInfo class
  25
+//  Implementation of the LM32ELFWriterInfo class
26 26
 //===----------------------------------------------------------------------===//
27 27
 
28  
-Mico32ELFWriterInfo::Mico32ELFWriterInfo(TargetMachine &TM)
  28
+LM32ELFWriterInfo::LM32ELFWriterInfo(TargetMachine &TM)
29 29
   : TargetELFWriterInfo(TM.getTargetData()->getPointerSizeInBits() == 64,
30 30
                         TM.getTargetData()->isLittleEndian()) {
31 31
 }
32 32
 
33  
-Mico32ELFWriterInfo::~Mico32ELFWriterInfo() {}
  33
+LM32ELFWriterInfo::~LM32ELFWriterInfo() {}
34 34
 
35  
-unsigned Mico32ELFWriterInfo::getRelocationType(unsigned MachineRelTy) const {
36  
-llvm_unreachable("unknown mico32 relocation type");
  35
+unsigned LM32ELFWriterInfo::getRelocationType(unsigned MachineRelTy) const {
  36
+llvm_unreachable("unknown lm32 relocation type");
37 37
   switch (MachineRelTy) {
38  
-  case Mico32::reloc_pcrel_word:
  38
+  case LM32::reloc_pcrel_word:
39 39
     return ELF::R_MICROBLAZE_64_PCREL;
40  
-  case Mico32::reloc_absolute_word:
  40
+  case LM32::reloc_absolute_word:
41 41
     return ELF::R_MICROBLAZE_NONE;
42 42
   default:
43  
-    llvm_unreachable("unknown mico32 machine relocation type");
  43
+    llvm_unreachable("unknown lm32 machine relocation type");
44 44
   }
45 45
   return 0;
46 46
 }
47 47
 
48  
-long int Mico32ELFWriterInfo::getDefaultAddendForRelTy(unsigned RelTy,
  48
+long int LM32ELFWriterInfo::getDefaultAddendForRelTy(unsigned RelTy,
49 49
                                                     long int Modifier) const {
50  
-llvm_unreachable("unknown mico32 relocation type");
  50
+llvm_unreachable("unknown lm32 relocation type");
51 51
   switch (RelTy) {
52 52
   case ELF::R_MICROBLAZE_32_PCREL:
53 53
     return Modifier - 4;
54 54
   case ELF::R_MICROBLAZE_32:
55 55
     return Modifier;
56 56
   default:
57  
-    llvm_unreachable("unknown mico32 relocation type");
  57
+    llvm_unreachable("unknown lm32 relocation type");
58 58
   }
59 59
   return 0;
60 60
 }
61 61
 
62  
-unsigned Mico32ELFWriterInfo::getRelocationTySize(unsigned RelTy) const {
63  
-llvm_unreachable("unknown mico32 relocation type");
  62
+unsigned LM32ELFWriterInfo::getRelocationTySize(unsigned RelTy) const {
  63
+llvm_unreachable("unknown lm32 relocation type");
64 64
   // FIXME: Most of these sizes are guesses based on the name
65 65
   switch (RelTy) {
66 66
   case ELF::R_MICROBLAZE_32:
@@ -85,8 +85,8 @@ llvm_unreachable("unknown mico32 relocation type");
85 85
   return 0;
86 86
 }
87 87
 
88  
-bool Mico32ELFWriterInfo::isPCRelativeRel(unsigned RelTy) const {
89  
-llvm_unreachable("unknown mico32 relocation type");
  88
+bool LM32ELFWriterInfo::isPCRelativeRel(unsigned RelTy) const {
  89
+llvm_unreachable("unknown lm32 relocation type");
90 90
   // FIXME: Most of these are guesses based on the name
91 91
   switch (RelTy) {
92 92
   case ELF::R_MICROBLAZE_32_PCREL:
@@ -99,15 +99,15 @@ llvm_unreachable("unknown mico32 relocation type");
99 99
   return false;
100 100
 }
101 101
 
102  
-unsigned Mico32ELFWriterInfo::getAbsoluteLabelMachineRelTy() const {
103  
-llvm_unreachable("unknown mico32 relocation type");
104  
-  return Mico32::reloc_absolute_word;
  102
+unsigned LM32ELFWriterInfo::getAbsoluteLabelMachineRelTy() const {
  103
+llvm_unreachable("unknown lm32 relocation type");
  104
+  return LM32::reloc_absolute_word;
105 105
 }
106 106
 
107  
-long int Mico32ELFWriterInfo::computeRelocation(unsigned SymOffset,
  107
+long int LM32ELFWriterInfo::computeRelocation(unsigned SymOffset,
108 108
                                                 unsigned RelOffset,
109 109
                                                 unsigned RelTy) const {
110  
-llvm_unreachable("unknown mico32 relocation type");
  110
+llvm_unreachable("unknown lm32 relocation type");
111 111
   if (RelTy == ELF::R_MICROBLAZE_32_PCREL || ELF::R_MICROBLAZE_64_PCREL)
112 112
     return SymOffset - (RelOffset + 4);
113 113
   else
16  lib/Target/Mico32/Mico32ELFWriterInfo.h → lib/Target/LM32/LM32ELFWriterInfo.h
... ...
@@ -1,4 +1,4 @@
1  
-//===-- Mico32ELFWriterInfo.h - ELF Writer Info for Mico32 ------*- C++ -*-===//
  1
+//===-- LM32ELFWriterInfo.h - ELF Writer Info for LM32 ----------*- C++ -*-===//
2 2
 //
3 3
 //                     The LLVM Compiler Infrastructure
4 4
 //
@@ -7,21 +7,21 @@
7 7
 //
8 8
 //===----------------------------------------------------------------------===//
9 9
 //
10  
-// This file implements ELF writer information for the Mico32 backend.
  10
+// This file implements ELF writer information for the LM32 backend.
11 11
 //
12 12
 //===----------------------------------------------------------------------===//
13 13
 
14  
-#ifndef MICO32_ELF_WRITER_INFO_H
15  
-#define MICO32_ELF_WRITER_INFO_H
  14
+#ifndef LM32_ELF_WRITER_INFO_H
  15
+#define LM32_ELF_WRITER_INFO_H
16 16
 
17 17
 #include "llvm/Target/TargetELFWriterInfo.h"
18 18
 
19 19
 namespace llvm {
20 20
 
21  
-  class Mico32ELFWriterInfo : public TargetELFWriterInfo {
  21
+  class LM32ELFWriterInfo : public TargetELFWriterInfo {
22 22
   public:
23  
-    Mico32ELFWriterInfo(TargetMachine &TM);
24  
-    virtual ~Mico32ELFWriterInfo();
  23
+    LM32ELFWriterInfo(TargetMachine &TM);
  24
+    virtual ~LM32ELFWriterInfo();
25 25
 
26 26
     /// getRelocationType - Returns the target specific ELF Relocation type.
27 27
     /// 'MachineRelTy' contains the object code independent relocation type
@@ -55,4 +55,4 @@ namespace llvm {
55 55
 
56 56
 } // end llvm namespace
57 57
 
58  
-#endif // MICO32_ELF_WRITER_INFO_H
  58
+#endif // LM32_ELF_WRITER_INFO_H
102  lib/Target/Mico32/Mico32FrameLowering.cpp → lib/Target/LM32/LM32FrameLowering.cpp
... ...
@@ -1,4 +1,4 @@
1  
-//=====- Mico32FrameLowering.cpp - Mico32 Frame Information ------ C++ -*-====//
  1
+//=====- LM32FrameLowering.cpp - LM32 Frame Information ---------- C++ -*-====//
2 2
 //
3 3
 //                     The LLVM Compiler Infrastructure
4 4
 //
@@ -7,14 +7,14 @@
7 7
 //
8 8
 //===----------------------------------------------------------------------===//
9 9
 //
10  
-// This file contains the Mico32 implementation of TargetFrameLowering class.
  10
+// This file contains the LM32 implementation of TargetFrameLowering class.
11 11
 //
12 12
 //===----------------------------------------------------------------------===//
13 13
 
14  
-#include "Mico32.h"
15  
-#include "Mico32FrameLowering.h"
16  
-#include "Mico32InstrInfo.h"
17  
-#include "Mico32MachineFunctionInfo.h"
  14
+#include "LM32.h"
  15
+#include "LM32FrameLowering.h"
  16
+#include "LM32InstrInfo.h"
  17
+#include "LM32MachineFunctionInfo.h"
18 18
 #include "llvm/Function.h"
19 19
 #include "llvm/CodeGen/MachineFrameInfo.h"
20 20
 #include "llvm/CodeGen/MachineFunction.h"
@@ -26,12 +26,12 @@
26 26
 #include "llvm/Target/TargetOptions.h"
27 27
 #include "llvm/Support/CommandLine.h"
28 28
 #include "llvm/Support/Debug.h"
29  
-#include "Mico32Subtarget.h"
  29
+#include "LM32Subtarget.h"
30 30
 
31 31
 
32 32
 using namespace llvm;
33 33
 
34  
-Mico32FrameLowering::Mico32FrameLowering(const Mico32Subtarget &subtarget)
  34
+LM32FrameLowering::LM32FrameLowering(const LM32Subtarget &subtarget)
35 35
   : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
36 36
                         4 /*StackAlignment*/, 
37 37
                         0 /*LocalAreaOffset*/,
@@ -43,7 +43,7 @@ Mico32FrameLowering::Mico32FrameLowering(const Mico32Subtarget &subtarget)
43 43
 
44 44
 /// determineFrameLayout - Align the frame and maximum call frame and
45 45
 /// updated the sizes. Copied from SPU.
46  
-void Mico32FrameLowering::
  46
+void LM32FrameLowering::
47 47
 determineFrameLayout(MachineFunction &MF) const {
48 48
   MachineFrameInfo *MFI = MF.getFrameInfo();
49 49
 
@@ -83,7 +83,7 @@ determineFrameLayout(MachineFunction &MF) const {
83 83
 /// function has variable sized allocas or frame pointer elimination 
84 84
 /// is disabled or stack alignment is less than requested alignment.
85 85
 ///
86  
-bool Mico32FrameLowering::
  86
+bool LM32FrameLowering::
87 87
 hasFP(const MachineFunction &MF) const {
88 88
   const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
89 89
   const MachineFrameInfo *MFI = MF.getFrameInfo();
@@ -97,16 +97,16 @@ hasFP(const MachineFunction &MF) const {
97 97
 
98 98
 // Generate the function prologue.
99 99
 // This is based on XCore with some SPU influence.
100  
-void Mico32FrameLowering::
  100
+void LM32FrameLowering::
101 101
 emitPrologue(MachineFunction &MF) const {
102 102
   MachineBasicBlock &MBB = MF.front();    // Prolog goes in entry BB
103 103
   MachineBasicBlock::iterator MBBI = MBB.begin();
104 104
   MachineFrameInfo *MFrmInf = MF.getFrameInfo();
105 105
   MachineModuleInfo *MMI = &MF.getMMI();
106 106
 
107  
-  Mico32FunctionInfo *MFuncInf = MF.getInfo<Mico32FunctionInfo>();
108  
-  const Mico32InstrInfo &TII =
109  
-    *static_cast<const Mico32InstrInfo*>(MF.getTarget().getInstrInfo());
  107
+  LM32FunctionInfo *MFuncInf = MF.getInfo<LM32FunctionInfo>();
  108
+  const LM32InstrInfo &TII =
  109
+    *static_cast<const LM32InstrInfo*>(MF.getTarget().getInstrInfo());
110 110
 
111 111
   DebugLoc dl = (MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc());
112 112
 
@@ -124,7 +124,7 @@ emitPrologue(MachineFunction &MF) const {
124 124
   // Get the frame size.
125 125
   int FrameSize = MFrmInf->getStackSize();
126 126
   assert(FrameSize%4 == 0 && 
127  
-         "Mico32FrameLowering::emitPrologue Misaligned frame size");
  127
+         "LM32FrameLowering::emitPrologue Misaligned frame size");
128 128
   
129 129
   
130 130
   bool emitFrameMoves = MMI->hasDebugInfo() ||
@@ -141,8 +141,8 @@ emitPrologue(MachineFunction &MF) const {
141 141
     // so we don't use 32768. See SPU for model of how to implement larger
142 142
     // stack frames.
143 143
     if (FrameSize < 32768) {
144  
-      BuildMI(MBB, MBBI, dl, TII.get(Mico32::ADDI),
145  
-              Mico32::RSP).addReg(Mico32::RSP).addImm(-FrameSize);
  144
+      BuildMI(MBB, MBBI, dl, TII.get(LM32::ADDI),
  145
+              LM32::RSP).addReg(LM32::RSP).addImm(-FrameSize);
146 146
     } else {
147 147
       // We could use multiple instructions to generate the offset.
148 148
       report_fatal_error("Unhandled frame size in function: " + MBB.getParent()->getFunction()->getName() + " size: " + Twine(FrameSize));
@@ -156,7 +156,7 @@ emitPrologue(MachineFunction &MF) const {
156 156
 
157 157
       // Show update of SP.
158 158
       MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol();
159  
-      BuildMI(MBB, MBBI, dl, TII.get(Mico32::PROLOG_LABEL)).addSym(FrameLabel);
  159
+      BuildMI(MBB, MBBI, dl, TII.get(LM32::PROLOG_LABEL)).addSym(FrameLabel);
160 160
 
161 161
   DEBUG(dbgs() << "\nFunction: "
162 162
                << MF.getFunction()->getName() << " SP Frame debug location\n");
@@ -173,20 +173,20 @@ emitPrologue(MachineFunction &MF) const {
173 173
       int LRSpillOffset = MFrmInf->getObjectOffset(MFuncInf->getLRSpillSlot())
174 174
         +FrameSize;
175 175
       LRSpillOffset += Subtarget.hasSPBias()? 4 : 0;
176  
-      BuildMI(MBB, MBBI, dl, TII.get(Mico32::SW))
177  
-        .addReg(Mico32::RRA).addReg(Mico32::RSP).addImm(LRSpillOffset);
178  
-      MBB.addLiveIn(Mico32::RRA);
  176
+      BuildMI(MBB, MBBI, dl, TII.get(LM32::SW))
  177
+        .addReg(LM32::RRA).addReg(LM32::RSP).addImm(LRSpillOffset);
  178
+      MBB.addLiveIn(LM32::RRA);
179 179
       
180 180
       if (emitFrameMoves) {
181 181
         MCSymbol *SaveLRLabel = MMI->getContext().CreateTempSymbol();
182  
-        BuildMI(MBB, MBBI, dl, TII.get(Mico32::PROLOG_LABEL))
  182
+        BuildMI(MBB, MBBI, dl, TII.get(LM32::PROLOG_LABEL))
183 183
                 .addSym(SaveLRLabel);
184 184
   DEBUG(dbgs() << "\nFunction: "
185 185
                << MF.getFunction()->getName() << " LR Frame debug location\n");
186 186
   DEBUG(dbgs() << "Moving %RRA (link register): \n");
187 187
   DEBUG(dbgs() << "VirtualFP[FPSpillOffset] = VirtFP[" << LRSpillOffset << "]\n");
188 188
         MachineLocation CSDst(MachineLocation::VirtualFP, LRSpillOffset);
189  
-        MachineLocation CSSrc(Mico32::RRA);
  189
+        MachineLocation CSSrc(LM32::RRA);
190 190
         MMI->getFrameMoves().push_back(MachineMove(SaveLRLabel, CSDst, CSSrc));
191 191
       }
192 192
     }
@@ -197,11 +197,11 @@ emitPrologue(MachineFunction &MF) const {
197 197
         MFrmInf->getObjectOffset(MFuncInf->getFPSpillSlot())+FrameSize;
198 198
       FPSpillOffset += Subtarget.hasSPBias()? 4 : 0;
199 199
   
200  
-      BuildMI(MBB, MBBI, dl, TII.get(Mico32::SW))
201  
-        .addReg(Mico32::RFP).addReg(Mico32::RSP).addImm(FPSpillOffset);
  200
+      BuildMI(MBB, MBBI, dl, TII.get(LM32::SW))
  201
+        .addReg(LM32::RFP).addReg(LM32::RSP).addImm(FPSpillOffset);
202 202
   
203 203
       // RFP is live-in. It is killed at the spill.
204  
-      MBB.addLiveIn(Mico32::RFP);
  204
+      MBB.addLiveIn(LM32::RFP);
205 205
       if (emitFrameMoves) {
206 206
              DEBUG(dbgs() << "\nFunction: "
207 207
                << MF.getFunction()->getName() << " FP Frame debug location\n");
@@ -209,24 +209,24 @@ emitPrologue(MachineFunction &MF) const {
209 209
                << ((FP) ? "FP" : "SP") << " to \n");
210 210
   DEBUG(dbgs() << "VirtualFP[FPSpillOffset] = VirtFP[" << FPSpillOffset << "]\n");
211 211
         MCSymbol *SaveRFPLabel = MMI->getContext().CreateTempSymbol();
212  
-        BuildMI(MBB, MBBI, dl, TII.get(Mico32::PROLOG_LABEL))
  212
+        BuildMI(MBB, MBBI, dl, TII.get(LM32::PROLOG_LABEL))
213 213
                 .addSym(SaveRFPLabel);
214 214
         MachineLocation CSDst(MachineLocation::VirtualFP, FPSpillOffset);
215  
-        MachineLocation CSSrc(Mico32::RFP);
  215
+        MachineLocation CSSrc(LM32::RFP);
216 216
         MMI->getFrameMoves().push_back(MachineMove(SaveRFPLabel, CSDst, CSSrc));
217 217
       }
218 218
       // Set the FP from the SP.
219  
-      unsigned FramePtr = Mico32::RFP;
  219
+      unsigned FramePtr = LM32::RFP;
220 220
       // The FP points to the beginning of the frame ( = SP on entry), 
221 221
       // hence we add in the FrameSize.
222 222
       FrameSize += Subtarget.hasSPBias()? 4 : 0;
223  
-      BuildMI(MBB, MBBI, dl, TII.get(Mico32::ADDI),FramePtr)
224  
-        .addReg(Mico32::RSP).addImm(FrameSize);
  223
+      BuildMI(MBB, MBBI, dl, TII.get(LM32::ADDI),FramePtr)
  224
+        .addReg(LM32::RSP).addImm(FrameSize);
225 225
       if (emitFrameMoves) {
226 226
         DEBUG(dbgs() << "FRAMEMOVE: FPreg: is now FP \n");
227 227
         // Show FP is now valid.
228 228
         MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol();
229  
-        BuildMI(MBB, MBBI, dl,TII.get(Mico32::PROLOG_LABEL)).addSym(FrameLabel);
  229
+        BuildMI(MBB, MBBI, dl,TII.get(LM32::PROLOG_LABEL)).addSym(FrameLabel);
230 230
         MachineLocation SPDst(FramePtr);
231 231
         MachineLocation SPSrc(MachineLocation::VirtualFP);
232 232
         MMI->getFrameMoves().push_back(MachineMove(FrameLabel, SPDst, SPSrc));
@@ -255,7 +255,7 @@ emitPrologue(MachineFunction &MF) const {
255 255
   // This is from PPC:
256 256
   if (emitFrameMoves) {
257 257
     MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol();
258  
-    BuildMI(MBB, MBBI, dl, TII.get(Mico32::PROLOG_LABEL)).addSym(FrameLabel);
  258
+    BuildMI(MBB, MBBI, dl, TII.get(LM32::PROLOG_LABEL)).addSym(FrameLabel);
259 259
     MCSymbol *ReadyLabel = 0;
260 260
 
261 261
     MCSymbol *Label = FP ? ReadyLabel : FrameLabel;
@@ -289,14 +289,14 @@ emitPrologue(MachineFunction &MF) const {
289 289
 }
290 290
 
291 291
 
292  
-void Mico32FrameLowering::
  292
+void LM32FrameLowering::
293 293
 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
294 294
   MachineFrameInfo *MFrmInf = MF.getFrameInfo();
295 295
   MachineBasicBlock::iterator MBBI = prior(MBB.end());
296  
-  const Mico32InstrInfo &TII =
297  
-    *static_cast<const Mico32InstrInfo*>(MF.getTarget().getInstrInfo());
298  
-  Mico32FunctionInfo *MFuncInf = MF.getInfo<Mico32FunctionInfo>();
299  
-  assert(MBBI->getOpcode() == Mico32::RET &&
  296
+  const LM32InstrInfo &TII =
  297
+    *static_cast<const LM32InstrInfo*>(MF.getTarget().getInstrInfo());
  298
+  LM32FunctionInfo *MFuncInf = MF.getInfo<LM32FunctionInfo>();
  299
+  assert(MBBI->getOpcode() == LM32::RET &&
300 300
          "Can only put epilog before 'ret' instruction!");
301 301
   DebugLoc dl = MBBI->getDebugLoc();
302 302
   
@@ -311,8 +311,8 @@ emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
311 311
       int FPSpillOffset = 
312 312
         MFrmInf->getObjectOffset(MFuncInf->getFPSpillSlot())+FrameSize;
313 313
       FPSpillOffset += Subtarget.hasSPBias()? 4 : 0;
314  
-      BuildMI(MBB, MBBI, dl, TII.get(Mico32::LW))
315  
-        .addReg(Mico32::RFP).addReg(Mico32::RSP).addImm(FPSpillOffset);
  314
+      BuildMI(MBB, MBBI, dl, TII.get(LM32::LW))
  315
+        .addReg(LM32::RFP).addReg(LM32::RSP).addImm(FPSpillOffset);
316 316
     }
317 317
   
318 318
     if (MFuncInf->getUsesLR()) {
@@ -320,14 +320,14 @@ emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
320 320
       int LRSpillOffset = MFrmInf->getObjectOffset(MFuncInf->getLRSpillSlot())
321 321
           +FrameSize;
322 322
       LRSpillOffset += Subtarget.hasSPBias()? 4 : 0;
323  
-      BuildMI(MBB, MBBI, dl, TII.get(Mico32::LW))
324  
-        .addReg(Mico32::RRA).addReg(Mico32::RSP).addImm(LRSpillOffset);
  323
+      BuildMI(MBB, MBBI, dl, TII.get(LM32::LW))
  324
+        .addReg(LM32::RRA).addReg(LM32::RSP).addImm(LRSpillOffset);
325 325
     }
326 326
 
327 327
     // SP +=  MFrmInf->getStackSize()
328 328
     if (FrameSize < 32768) {
329  
-      BuildMI(MBB, MBBI, dl, TII.get(Mico32::ADDI), Mico32::RSP)
330  
-        .addReg(Mico32::RSP).addImm(FrameSize);
  329
+      BuildMI(MBB, MBBI, dl, TII.get(LM32::ADDI), LM32::RSP)
  330
+        .addReg(LM32::RSP).addImm(FrameSize);
331 331
     } else {
332 332
       assert( 0 && "Unimplemented - per function stack size limited to 32767 bytes.");
333 333
     }
@@ -339,7 +339,7 @@ emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
339 339
 /// before the specified functions frame layout (MF.getFrameInfo()) is
340 340
 /// finalized.  Once the frame is finalized, MO_FrameIndex operands are
341 341
 /// replaced with direct constants.  This method is optional.
342  
-void Mico32FrameLowering::
  342
+void LM32FrameLowering::
343 343
 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
344 344
 
345 345
 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
@@ -347,14 +347,14 @@ processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
347 347
 /// what callee saved registers should be spilled. This method is optional.
348 348
 /// ARM provides a complex example of this function.
349 349
 /// The following is based on XCore
350  
-void Mico32FrameLowering::
  350
+void LM32FrameLowering::
351 351
 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
352 352
                                      RegScavenger *RS) const {
353 353
   MachineFrameInfo *MFrmInf = MF.getFrameInfo();
354 354
   const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
355  
-  const TargetRegisterClass *RC = Mico32::GPRRegisterClass;
356  
-  Mico32FunctionInfo *MFuncInf = MF.getInfo<Mico32FunctionInfo>();
357  
-  const bool LRUsed = MF.getRegInfo().isPhysRegUsed(Mico32::RRA);
  355
+  const TargetRegisterClass *RC = LM32::GPRRegisterClass;
  356
+  LM32FunctionInfo *MFuncInf = MF.getInfo<LM32FunctionInfo>();
  357
+  const bool LRUsed = MF.getRegInfo().isPhysRegUsed(LM32::RRA);
358 358
   const bool hasFP = MF.getTarget().getFrameLowering()->hasFP(MF);
359 359
   const bool isVarArg = MF.getFunction()->isVarArg();
360 360
   
@@ -371,7 +371,7 @@ processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
371 371
   // LR can be optimized out prior to now:
372 372
   int FrameIdx;
373 373
   if (LRUsed) {
374  
-    MF.getRegInfo().setPhysRegUnused(Mico32::RRA);
  374
+    MF.getRegInfo().setPhysRegUnused(LM32::RRA);
375 375
     
376 376
     if ( !isVarArg )
377 377
       FrameIdx = MFrmInf->CreateFixedObject(RC->getSize(), offset, true);
@@ -397,7 +397,7 @@ processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
397 397
     // This needs saving / restoring in the epilogue / prologue.
398 398
     // Supposedly FP is marked live-in and is killed at the spill. So
399 399
     // don't bother marking it unused.
400  
-    //MF.getRegInfo().setPhysRegUnused(Mico32::RFP);
  400
+    //MF.getRegInfo().setPhysRegUnused(LM32::RFP);
401 401
     // FIXME: shouldn't isSS be true?  XCore says no...
402 402
     if ( !isVarArg )
403 403
       FrameIdx = MFrmInf->CreateFixedObject(RC->getSize(), offset, true);
22  lib/Target/Mico32/Mico32FrameLowering.h → lib/Target/LM32/LM32FrameLowering.h
... ...
@@ -1,4 +1,4 @@
1  
-//===-- Mico32FrameLowering.h - Frame info for Mico32 Target -----*- C++ -*-==//
  1
+//===-- LM32FrameLowering.h - Frame info for LM32 Target ---------*- C++ -*-==//
2 2
 //
3 3
 //                     The LLVM Compiler Infrastructure
4 4
 //
@@ -7,25 +7,25 @@
7 7
 //
8 8
 //===----------------------------------------------------------------------===//
9 9
 //
10  
-// This file contains Mico32 frame information that doesn't fit anywhere else
  10
+// This file contains LM32 frame information that doesn't fit anywhere else
11 11
 // cleanly...
12 12
 //
13 13
 // Based on XCore.
14 14
 //===----------------------------------------------------------------------===//
15 15
 
16  
-#ifndef MICO32FRAMEINFO_H
17  
-#define MICO32FRAMEINFO_H
  16
+#ifndef LM32FRAMEINFO_H
  17
+#define LM32FRAMEINFO_H
18 18
 
19 19
 #include "llvm/Target/TargetFrameLowering.h"
20 20
 #include "llvm/Target/TargetMachine.h"
21 21
 
22 22
 namespace llvm {
23  
-  class Mico32Subtarget;
  23
+  class LM32Subtarget;
24 24
 
25  
-  class Mico32FrameLowering: public TargetFrameLowering {
26  
-    const Mico32Subtarget &Subtarget;
  25
+  class LM32FrameLowering: public TargetFrameLowering {
  26
+    const LM32Subtarget &Subtarget;
27 27
   public:
28  
-    Mico32FrameLowering(const Mico32Subtarget &subtarget);
  28
+    LM32FrameLowering(const LM32Subtarget &subtarget);
29 29
 
30 30
     /// Determine the frame's layout
31 31
     void determineFrameLayout(MachineFunction &MF) const;
@@ -43,12 +43,12 @@ namespace llvm {
43 43
     /// immediately on entry to the current function. This eliminates the need for
44 44
     /// add/sub sp brackets around call sites. Returns true if the call frame is
45 45
     /// included as part of the stack frame.
46  
-    /// Mico32 always reserves call frames. eliminateCallFramePseudoInstr() may
  46
+    /// LM32 always reserves call frames. eliminateCallFramePseudoInstr() may
47 47
     /// need to change if this does.  See ARM for example.
48 48
     ///
49 49
     /// PEI::calculateFrameObjectOffsets() adds maxCallFrameSize if 
50 50
     /// hasReservedCallFrame() is true.  The stack alignment is set
51  
-    /// in Mico32TargetMachine::Mico32TargetMachine().
  51
+    /// in LM32TargetMachine::LM32TargetMachine().
52 52
     /// Some targets (e.g. SPU, PPC) add in the maxCallFrameSize to the
53 53
     /// stacksize manually due to special alignment requirements or other issues.
54 54
     bool hasReservedCallFrame(const MachineFunction &MF) const {
@@ -82,4 +82,4 @@ namespace llvm {
82 82
   };
83 83
 }
84 84
 
85  
-#endif // MICO32FRAMEINFO_H
  85
+#endif // LM32FRAMEINFO_H
72  lib/Target/Mico32/Mico32ISelDAGToDAG.cpp → lib/Target/LM32/LM32ISelDAGToDAG.cpp
... ...
@@ -1,4 +1,4 @@
1  
-//===-- Mico32ISelDAGToDAG.cpp - A dag to dag inst selector for Mico32 ----===//
  1
+//===-- LM32ISelDAGToDAG.cpp - A dag to dag inst selector for LM32 --------===//
2 2
 //
3 3
 //                     The LLVM Compiler Infrastructure
4 4
 //
@@ -7,16 +7,16 @@
7 7
 //
8 8
 //===----------------------------------------------------------------------===//
9 9
 //
10  
-// This file defines an instruction selector for the Mico32 target.
  10
+// This file defines an instruction selector for the LM32 target.
11 11
 //
12 12
 //===----------------------------------------------------------------------===//
13 13
 
14  
-#define DEBUG_TYPE "mico32-isel"
15  
-#include "Mico32.h"
16  
-#include "Mico32MachineFunctionInfo.h"
17  
-#include "Mico32RegisterInfo.h"
18  
-#include "Mico32Subtarget.h"
19  
-#include "Mico32TargetMachine.h"
  14
+#define DEBUG_TYPE "lm32-isel"
  15
+#include "LM32.h"
  16
+#include "LM32MachineFunctionInfo.h"
  17
+#include "LM32RegisterInfo.h"
  18
+#include "LM32Subtarget.h"
  19
+#include "LM32TargetMachine.h"
20 20
 #include "llvm/GlobalValue.h"
21 21
 #include "llvm/Instructions.h"
22 22
 #include "llvm/Intrinsics.h"
@@ -39,42 +39,42 @@ using namespace llvm;
39 39
 //===----------------------------------------------------------------------===//
40 40
 
41 41
 //===----------------------------------------------------------------------===//
42  
-// Mico32DAGToDAGISel - Mico32 specific code to select Mico32 machine
  42
+// LM32DAGToDAGISel - LM32 specific code to select LM32 machine
43 43
 // instructions for SelectionDAG operations.
44 44
 //===----------------------------------------------------------------------===//
45 45
 namespace {
46 46
 
47  
-class Mico32DAGToDAGISel : public SelectionDAGISel {
  47
+class LM32DAGToDAGISel : public SelectionDAGISel {
48 48
 
49  
-  /// TM - Keep a reference to Mico32TargetMachine.
50  
-  Mico32TargetMachine &TM;
  49
+  /// TM - Keep a reference to LM32TargetMachine.
  50
+  LM32TargetMachine &TM;
51 51
 
52  
-  /// Subtarget - Keep a pointer to the Mico32Subtarget around so that we can
  52
+  /// Subtarget - Keep a pointer to the LM32Subtarget around so that we can
53 53
   /// make the right decision when generating code for different targets.
54  
-  const Mico32Subtarget &Subtarget;
  54
+  const LM32Subtarget &Subtarget;
55 55
 
56 56
 public:
57  
-  explicit Mico32DAGToDAGISel(Mico32TargetMachine &tm) :
  57
+  explicit LM32DAGToDAGISel(LM32TargetMachine &tm) :
58 58
   SelectionDAGISel(tm),
59  
-  TM(tm), Subtarget(tm.getSubtarget<Mico32Subtarget>()) {}
  59
+  TM(tm), Subtarget(tm.getSubtarget<LM32Subtarget>()) {}
60 60
 
61 61
   // Pass Name
62 62
   virtual const char *getPassName() const {
63  
-    return "Mico32 DAG->DAG Pattern Instruction Selection";
  63
+    return "LM32 DAG->DAG Pattern Instruction Selection";
64 64
   }
65 65
 private:
66 66
   // Include the pieces autogenerated from the target description.
67  
-  #include "Mico32GenDAGISel.inc"
  67
+  #include "LM32GenDAGISel.inc"
68 68
 
69 69
   /// getTargetMachine - Return a reference to the TargetMachine, casted
70 70
   /// to the target-specific type.
71  
-  const Mico32TargetMachine &getTargetMachine() {
72  
-    return static_cast<const Mico32TargetMachine &>(TM);
  71
+  const LM32TargetMachine &getTargetMachine() {
  72
+    return static_cast<const LM32TargetMachine &>(TM);
73 73
   }
74 74
 
75 75
   /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
76 76
   /// to the target-specific type.
77  
-  const Mico32InstrInfo *getInstrInfo() {
  77
+  const LM32InstrInfo *getInstrInfo() {
78 78
     return getTargetMachine().getInstrInfo();
79 79
   }
80 80
 
@@ -101,7 +101,7 @@ class Mico32DAGToDAGISel : public SelectionDAGISel {
101 101
 /// XCore has a different approach.  It also matches add and defines
102 102
 /// pseudo-instructions that are eliminated in eliminateFrameIndex.
103 103
 ///
104  
-bool Mico32DAGToDAGISel::
  104
+bool LM32DAGToDAGISel::
105 105
 SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset) {
106 106
 //   errs() << "value type: " <<  Addr.getValueType().getEVTString();
107 107
   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
@@ -166,8 +166,8 @@ SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset) {
166 166
 //FIXME: No PIC support.
167 167
 /// getGlobalBaseReg - Output the instructions required to put the
168 168
 /// GOT address into a register.
169  
-SDNode *Mico32DAGToDAGISel::getGlobalBaseReg() {
170  
-//FIXME: not ported to MICO32
  169
+SDNode *LM32DAGToDAGISel::getGlobalBaseReg() {
  170
+//FIXME: not ported to LM32
171 171
 assert(0 && "getGlobalBaseReg() not supported.");
172 172
   unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
173 173
   return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
@@ -177,8 +177,8 @@ assert(0 && "getGlobalBaseReg() not supported.");
177 177
 /// Select instructions not customized! Used for
178 178
 /// expanded, promoted and normal instructions
179 179
 /// from MBlaze:
180  
-SDNode* Mico32DAGToDAGISel::Select(SDNode *Node) {
181  
-//FIXME: not ported to MICO32
  180
+SDNode* LM32DAGToDAGISel::Select(SDNode *Node) {
  181
+//FIXME: not ported to LM32
182 182
   unsigned Opcode = Node->getOpcode();
183 183
   DebugLoc dl = Node->getDebugLoc();
184 184
 
@@ -209,7 +209,7 @@ SDNode* Mico32DAGToDAGISel::Select(SDNode *Node) {
209 209
         EVT VT = Node->getValueType(0);
210 210
 //   errs() << "ISD::FrameIndex value type: " <<  VT.getEVTString() << "/n";
211 211
         SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
212  
-        unsigned Opc = Mico32::ADDI;
  212
+        unsigned Opc = LM32::ADDI;
213 213
         if (Node->hasOneUse())
214 214
           return CurDAG->SelectNodeTo(Node, Opc, VT, TFI, imm);
215 215
         return CurDAG->getMachineNode(Opc, dl, VT, TFI, imm);
@@ -221,22 +221,22 @@ SDNode* Mico32DAGToDAGISel::Select(SDNode *Node) {
221 221
     /// GOT is smaller than about 64k (small code) the GA target is
222 222
     /// loaded with only one instruction. Otherwise GA's target must
223 223
     /// be loaded with 3 instructions.
224  
-    case Mico32ISD::JmpLink: {
  224
+    case LM32ISD::JmpLink: {
225 225
       if (TM.getRelocationModel() == Reloc::PIC_) {
226 226
         SDValue Chain  = Node->getOperand(0);
227 227
         SDValue Callee = Node->getOperand(1);
228  
-        SDValue R20Reg = CurDAG->getRegister(Mico32::R20, MVT::i32);
  228
+        SDValue R20Reg = CurDAG->getRegister(LM32::R20, MVT::i32);
229 229
         SDValue InFlag(0, 0);
230 230
 
231 231
         if ((isa<GlobalAddressSDNode>(Callee)) ||
232 232
             (isa<ExternalSymbolSDNode>(Callee)))
233 233
         {
234 234
           /// Direct call for global addresses and external symbols
235  
-          SDValue GPReg = CurDAG->getRegister(Mico32::R15, MVT::i32);
  235
+          SDValue GPReg = CurDAG->getRegister(LM32::R15, MVT::i32);
236 236
 
237 237
           // Use load to get GOT target
238 238
           SDValue Ops[] = { Callee, GPReg, Chain };
239  
-          SDValue Load = SDValue(CurDAG->getMachineNode(Mico32::LW, dl,
  239
+          SDValue Load = SDValue(CurDAG->getMachineNode(LM32::LW, dl,
240 240
                                  MVT::i32, MVT::Other, Ops, 3), 0);
241 241
           Chain = Load.getValue(1);
242 242
 
@@ -247,7 +247,7 @@ SDNode* Mico32DAGToDAGISel::Select(SDNode *Node) {
247 247
           Chain = CurDAG->getCopyToReg(Chain, dl, R20Reg, Callee, InFlag);
248 248
 
249 249
         // Emit Jump and Link Register
250  
-        SDNode *ResNode = CurDAG->getMachineNode(Mico32::BRLID, dl, MVT::Other,
  250
+        SDNode *ResNode = CurDAG->getMachineNode(LM32::BRLID, dl, MVT::Other,
251 251
                                                  MVT::Glue, R20Reg, Chain);
252 252
         Chain  = SDValue(ResNode, 0);
253 253
         InFlag = SDValue(ResNode, 1);
@@ -271,8 +271,8 @@ SDNode* Mico32DAGToDAGISel::Select(SDNode *Node) {
271 271
   return ResNode;
272 272
 }
273 273
 
274  
-/// createMico32ISelDag - This pass converts a legalized DAG into a
275  
-/// Mico32-specific DAG, ready for instruction scheduling.
276  
-FunctionPass *llvm::createMico32ISelDag(Mico32TargetMachine &TM) {
277  
-  return new Mico32DAGToDAGISel(TM);
  274
+/// createLM32ISelDag - This pass converts a legalized DAG into a
  275
+/// LM32-specific DAG, ready for instruction scheduling.
  276
+FunctionPass *llvm::createLM32ISelDag(LM32TargetMachine &TM) {
  277
+  return new LM32DAGToDAGISel(TM);
278 278
 }
228  lib/Target/Mico32/Mico32ISelLowering.cpp → lib/Target/LM32/LM32ISelLowering.cpp
... ...
@@ -1,4 +1,4 @@
1  
-//===-- Mico32ISelLowering.cpp - Mico32 DAG Lowering Implementation -------===//
  1
+//===-- LM32ISelLowering.cpp - LM32 DAG Lowering Implementation -----------===//
2 2
 //
3 3
 //                     The LLVM Compiler Infrastructure
4 4
 //
@@ -7,17 +7,17 @@
7 7
 //
8 8
 //===----------------------------------------------------------------------===//
9 9
 //
10  
-// This file defines the interfaces that Mico32 uses to lower LLVM code into a
  10
+// This file defines the interfaces that LM32 uses to lower LLVM code into a
11 11
 // selection DAG.
12 12
 //
13 13
 //===----------------------------------------------------------------------===//
14 14
 
15  
-#define DEBUG_TYPE "mico32-lower"
16  
-#include "Mico32ISelLowering.h"
17  
-#include "Mico32MachineFunctionInfo.h"
18  
-#include "Mico32TargetMachine.h"
19  
-#include "Mico32TargetObjectFile.h"
20  
-#include "Mico32Subtarget.h"
  15
+#define DEBUG_TYPE "lm32-lower"
  16
+#include "LM32ISelLowering.h"
  17
+#include "LM32MachineFunctionInfo.h"
  18
+#include "LM32TargetMachine.h"
  19
+#include "LM32TargetObjectFile.h"
  20
+#include "LM32Subtarget.h"
21 21
 #include "llvm/DerivedTypes.h"
22 22
 #include "llvm/Function.h"
23 23
 #include "llvm/GlobalVariable.h"