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add JTAG support for Xilinx Spartan-6 devices

Use the BSCAN_SPARTAN6 slice to connect the design to the hardware JTAG
port.

Signed-off-by: Michael Walle <michael@walle.cc>
1 parent a4d16b3 commit 2d25c42a05ea9e84520ac5f8636ac1ad2ef9db67 @mwalle mwalle committed Sep 24, 2010
Showing with 145 additions and 35 deletions.
  1. +83 −31 rtl/jtag_cores.v
  2. +62 −0 rtl/jtag_tap_spartan6.v
  3. +0 −4 rtl/lm32_top.v
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@@ -1,36 +1,88 @@
-// TODO
+/*
+ * LatticeMico32
+ * JTAG Registers
+ *
+ * Copyright (C) 2010 Michael Walle
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
module jtag_cores (
- // ----- Inputs -------
- reg_d,
- reg_addr_d,
- // ----- Outputs -------
- reg_update,
- reg_q,
- reg_addr_q,
- jtck,
- jrstn
+ input [7:0] reg_d,
+ input [2:0] reg_addr_d,
+ output reg_update,
+ output [7:0] reg_q,
+ output [2:0] reg_addr_q,
+ output jtck,
+ output jrstn
);
-input [7:0] reg_d;
-input [2:0] reg_addr_d;
-
-output reg_update;
-wire reg_update;
-output [7:0] reg_q;
-wire [7:0] reg_q;
-output [2:0] reg_addr_q;
-wire [2:0] reg_addr_q;
-
-output jtck;
-wire jtck;
-output jrstn;
-wire jrstn;
-
-assign reg_update = 1'b0;
-assign reg_q = 8'hxx;
-assign reg_addr_q = 3'bxxx;
-assign jtck = 1'b0;
-assign jrstn = 1'b1;
-
+wire tck;
+wire tdi;
+wire tdo;
+wire shift;
+wire update;
+wire reset;
+
+jtag_tap jtag_tap (
+ .tck(tck),
+ .tdi(tdi),
+ .tdo(tdo),
+ .shift(shift),
+ .update(update),
+ .reset(reset)
+);
+
+reg [10:0] jtag_shift;
+reg [10:0] jtag_latched;
+
+always @(posedge tck or posedge reset)
+begin
+ if(reset)
+ jtag_shift <= 11'b0;
+ else begin
+ if(shift)
+ jtag_shift <= {tdi, jtag_shift[10:1]};
+ else
+ jtag_shift <= {reg_d, reg_addr_d};
+ end
+end
+
+assign tdo = jtag_shift[0];
+
+always @(posedge reg_update or posedge reset)
+begin
+ if(reset)
+ jtag_latched <= 11'b0;
+ else
+ jtag_latched <= jtag_shift;
+end
+
+assign reg_update = update;
+assign reg_q = jtag_latched[10:3];
+assign reg_addr_q = jtag_latched[2:0];
+assign jtck = tck;
+assign jrstn = ~reset;
+
endmodule
View
@@ -0,0 +1,62 @@
+/*
+ * LatticeMico32
+ * JTAG Test Access Port For Xilinx Sparan-6 Devices
+ *
+ * Copyright (C) 2010 Michael Walle
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+module jtag_tap(
+ output tck,
+ output tdi,
+ input tdo,
+ output shift,
+ output update,
+ output reset
+);
+
+wire g_shift;
+wire g_update;
+
+assign shift = g_shift & sel;
+assign update = g_update & sel;
+
+BSCAN_SPARTAN6 #(
+ .JTAG_CHAIN(1)
+) bscan (
+ .CAPTURE(),
+ .DRCK(tck),
+ .RESET(reset),
+ .RUNTEST(),
+ .SEL(sel),
+ .SHIFT(g_shift),
+ .TCK(),
+ .TDI(tdi),
+ .TMS(),
+ .UPDATE(g_update),
+ .TDO(tdo)
+);
+
+endmodule
View
@@ -293,16 +293,12 @@ lm32_cpu cpu (
// JTAG cores
jtag_cores jtag_cores (
// ----- Inputs -----
-`ifdef INCLUDE_LM32
.reg_d (jtag_reg_d),
.reg_addr_d (jtag_reg_addr_d),
-`endif
// ----- Outputs -----
-`ifdef INCLUDE_LM32
.reg_update (jtag_update),
.reg_q (jtag_reg_q),
.reg_addr_q (jtag_reg_addr_q),
-`endif
.jtck (jtck),
.jrstn (jrstn)
);

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