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add config option for level-sensitive interrupts

If interrupts are level-sensitive there is no need to latch the state in
the IP register. Thus, make the IP register reflect the state of the
interrupt lines and make it read-only.

Signed-off-by: Michael Walle <michael@walle.cc>
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commit 6d2b5b945563ced8e2289513c8ceb2f254285eb5 1 parent 8945e79
@mwalle mwalle authored
Showing with 26 additions and 0 deletions.
  1. +4 −0 rtl/lm32_config.v.sample
  2. +22 −0 rtl/lm32_interrupt.v
View
4 rtl/lm32_config.v.sample
@@ -55,6 +55,10 @@
// Enable support for 32 hardware interrupts
`define CFG_INTERRUPTS_ENABLED
+// Enable level-sensitive interrupts. The interrupt line status is
+// reflected in the IP register, which is then read-only.
+//`define CFG_LEVEL_SENSITIVE_INTERRUPTS
+
//
// USER INSTRUCTION
View
22 rtl/lm32_interrupt.v
@@ -126,8 +126,10 @@ reg [`LM32_WORD_RNG] csr_read_data;
// Internal nets and registers
/////////////////////////////////////////////////////
+`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
wire [interrupts-1:0] asserted; // Which interrupts are currently being asserted
//pragma attribute asserted preserve_signal true
+`endif
wire [interrupts-1:0] interrupt_n_exception;
// Interrupt CSRs
@@ -137,7 +139,11 @@ reg eie; // Exception interrupt enable
`ifdef CFG_DEBUG_ENABLED
reg bie; // Breakpoint interrupt enable
`endif
+`ifdef CFG_LEVEL_SENSITIVE_INTERRUPTS
+wire [interrupts-1:0] ip; // Interrupt pending
+`else
reg [interrupts-1:0] ip; // Interrupt pending
+`endif
reg [interrupts-1:0] im; // Interrupt mask
/////////////////////////////////////////////////////
@@ -151,7 +157,11 @@ assign interrupt_n_exception = ip & im;
assign interrupt_exception = (|interrupt_n_exception) & ie;
// Determine which interrupts are currently being asserted or are already pending
+`ifdef CFG_LEVEL_SENSITIVE_INTERRUPTS
+assign ip = interrupt;
+`else
assign asserted = ip | interrupt;
+`endif
assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
`ifdef CFG_DEBUG_ENABLED
@@ -229,12 +239,16 @@ begin
bie <= `FALSE;
`endif
im <= {interrupts{1'b0}};
+`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
ip <= {interrupts{1'b0}};
+`endif
end
else
begin
// Set IP bit when interrupt line is asserted
+`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
ip <= asserted;
+`endif
`ifdef CFG_DEBUG_ENABLED
if (non_debug_exception == `TRUE)
begin
@@ -283,8 +297,10 @@ begin
end
if (csr == `LM32_CSR_IM)
im <= csr_write_data[interrupts-1:0];
+`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
if (csr == `LM32_CSR_IP)
ip <= asserted & ~csr_write_data[interrupts-1:0];
+`endif
end
end
end
@@ -302,12 +318,16 @@ begin
`ifdef CFG_DEBUG_ENABLED
bie <= `FALSE;
`endif
+`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
ip <= {interrupts{1'b0}};
+`endif
end
else
begin
// Set IP bit when interrupt line is asserted
+`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
ip <= asserted;
+`endif
`ifdef CFG_DEBUG_ENABLED
if (non_debug_exception == `TRUE)
begin
@@ -354,8 +374,10 @@ begin
bie <= csr_write_data[2];
`endif
end
+`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
if (csr == `LM32_CSR_IP)
ip <= asserted & ~csr_write_data[interrupts-1:0];
+`endif
end
end
end
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