From 98dc41db089767bce00d4c6e0a473dfbd9a50e2e Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 12 Dec 2012 18:37:17 +0100 Subject: [PATCH] whitespace and indentation fixes Replace tabstops, correct indentation according to Lattice's coding style. This huge patch makes it harder to backport upstream fixes, but there was already a patch which replaced almost every line in the source code. So it was already hard :) Signed-off-by: Michael Walle --- rtl/lm32_adder.v | 26 +- rtl/lm32_addsub.v | 26 +- rtl/lm32_cpu.v | 755 +++++++++++++++++---------------- rtl/lm32_dcache.v | 220 +++++----- rtl/lm32_debug.v | 56 +-- rtl/lm32_decoder.v | 108 ++--- rtl/lm32_dp_ram.v | 24 +- rtl/lm32_icache.v | 182 ++++---- rtl/lm32_instruction_unit.v | 218 +++++----- rtl/lm32_interrupt.v | 42 +- rtl/lm32_jtag.v | 76 ++-- rtl/lm32_load_store_unit.v | 250 ++++++----- rtl/lm32_logic_op.v | 10 +- rtl/lm32_mc_arithmetic.v | 38 +- rtl/lm32_multiplier.v | 24 +- rtl/lm32_multiplier_spartan6.v | 280 ++++++------ rtl/lm32_ram.v | 41 +- rtl/lm32_shifter.v | 20 +- rtl/lm32_top.v | 60 +-- 19 files changed, 1227 insertions(+), 1229 deletions(-) diff --git a/rtl/lm32_adder.v b/rtl/lm32_adder.v index d4fa41d..fe81855 100644 --- a/rtl/lm32_adder.v +++ b/rtl/lm32_adder.v @@ -2,7 +2,7 @@ // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< // ------------------------------------------------------------------ // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED +// ALL RIGHTS RESERVED // ------------------------------------------------------------------ // // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. @@ -11,7 +11,7 @@ // // Lattice Semiconductor grants permission to use this code // pursuant to the terms of the Lattice Semiconductor Corporation -// Open Source License Agreement. +// Open Source License Agreement. // // Disclaimer: // @@ -37,7 +37,7 @@ // FILE DETAILS // Project : LatticeMico32 // File : lm32_adder.v -// Title : Integer adder / subtractor with comparison flag generation +// Title : Integer adder / subtractor with comparison flag generation // Dependencies : lm32_include.v // Version : 6.1.17 // : Initial Release @@ -84,9 +84,9 @@ output adder_carry_n_x; // Inverted carry wire adder_carry_n_x; output adder_overflow_x; // Indicates if overflow occured, only valid for subtractions reg adder_overflow_x; - + ///////////////////////////////////////////////////// -// Internal nets and registers +// Internal nets and registers ///////////////////////////////////////////////////// wire a_sign; // Sign (i.e. positive or negative) of operand 0 @@ -94,17 +94,17 @@ wire b_sign; // Sign of operand 1 wire result_sign; // Sign of result ///////////////////////////////////////////////////// -// Instantiations +// Instantiations ///////////////////////////////////////////////////// lm32_addsub addsub ( // ----- Inputs ----- - .DataA (operand_0_x), - .DataB (operand_1_x), - .Cin (adder_op_x), - .Add_Sub (adder_op_x_n), + .DataA (operand_0_x), + .DataB (operand_1_x), + .Cin (adder_op_x), + .Add_Sub (adder_op_x_n), // ----- Ouputs ----- - .Result (adder_result_x), + .Result (adder_result_x), .Cout (adder_carry_n_x) ); @@ -121,7 +121,7 @@ assign result_sign = adder_result_x[`LM32_WORD_WIDTH-1]; // Determine whether an overflow occured when performing a subtraction always @(*) -begin +begin // +ve - -ve = -ve -> overflow // -ve - +ve = +ve -> overflow if ( (!a_sign & b_sign & result_sign) @@ -131,6 +131,6 @@ begin else adder_overflow_x = `FALSE; end - + endmodule diff --git a/rtl/lm32_addsub.v b/rtl/lm32_addsub.v index 2a37ad2..d13a19d 100644 --- a/rtl/lm32_addsub.v +++ b/rtl/lm32_addsub.v @@ -2,7 +2,7 @@ // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< // ------------------------------------------------------------------ // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED +// ALL RIGHTS RESERVED // ------------------------------------------------------------------ // // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. @@ -11,7 +11,7 @@ // // Lattice Semiconductor grants permission to use this code // pursuant to the terms of the Lattice Semiconductor Corporation -// Open Source License Agreement. +// Open Source License Agreement. // // Disclaimer: // @@ -54,12 +54,12 @@ module lm32_addsub ( // ----- Inputs ------- - DataA, - DataB, - Cin, - Add_Sub, + DataA, + DataB, + Cin, + Add_Sub, // ----- Outputs ------- - Result, + Result, Cout ); @@ -83,13 +83,13 @@ wire Cout; ///////////////////////////////////////////////////// // Instantiations -///////////////////////////////////////////////////// +///////////////////////////////////////////////////// // Modified for Milkymist: removed non-portable instantiated block - wire [32:0] tmp_addResult = DataA + DataB + Cin; - wire [32:0] tmp_subResult = DataA - DataB - !Cin; - - assign Result = (Add_Sub == 1) ? tmp_addResult[31:0] : tmp_subResult[31:0]; - assign Cout = (Add_Sub == 1) ? tmp_addResult[32] : !tmp_subResult[32]; +wire [32:0] tmp_addResult = DataA + DataB + Cin; +wire [32:0] tmp_subResult = DataA - DataB - !Cin; + +assign Result = (Add_Sub == 1) ? tmp_addResult[31:0] : tmp_subResult[31:0]; +assign Cout = (Add_Sub == 1) ? tmp_addResult[32] : !tmp_subResult[32]; endmodule diff --git a/rtl/lm32_cpu.v b/rtl/lm32_cpu.v index b35bc85..ff760c2 100644 --- a/rtl/lm32_cpu.v +++ b/rtl/lm32_cpu.v @@ -2,7 +2,7 @@ // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< // ------------------------------------------------------------------ // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED +// ALL RIGHTS RESERVED // ------------------------------------------------------------------ // // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. @@ -11,7 +11,7 @@ // // Lattice Semiconductor grants permission to use this code // pursuant to the terms of the Lattice Semiconductor Corporation -// Open Source License Agreement. +// Open Source License Agreement. // // Disclaimer: // @@ -46,11 +46,11 @@ // next instruction. // // Version 3.4 -// 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were +// 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were // never serviced. -// +// // Version 3.3 -// 1. Feature: Support for memory that is tightly coupled to processor core, and +// 1. Feature: Support for memory that is tightly coupled to processor core, and // has a single-cycle access latency (same as caches). Instruction port has // access to a dedicated physically-mapped memory. Data port has access to // a dedicated physically-mapped memory. In order to be able to manipulate @@ -76,11 +76,11 @@ // // Version 3.1 // 1. Feature: LM32 Register File can now be mapped in to on-chip block RAM (EBR) -// instead of distributed memory by enabling the option in LM32 GUI. -// 2. Feature: LM32 also adds a static branch predictor to improve branch -// performance. All immediate-based forward-pointing branches are predicted +// instead of distributed memory by enabling the option in LM32 GUI. +// 2. Feature: LM32 also adds a static branch predictor to improve branch +// performance. All immediate-based forward-pointing branches are predicted // not-taken. All immediate-based backward-pointing branches are predicted taken. -// +// // Version 7.0SP2, 3.0 // No Change // @@ -99,12 +99,12 @@ module lm32_cpu ( clk_i, `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE clk_n_i, -`endif +`endif rst_i, `ifdef CFG_DEBUG_ENABLED - `ifdef CFG_ALTERNATE_EBA +`ifdef CFG_ALTERNATE_EBA at_debug, - `endif +`endif `endif // From external devices `ifdef CFG_INTERRUPTS_ENABLED @@ -114,11 +114,11 @@ module lm32_cpu ( `ifdef CFG_USER_ENABLED user_result, user_complete, -`endif +`endif `ifdef CFG_JTAG_ENABLED // From JTAG jtag_clk, - jtag_update, + jtag_update, jtag_reg_q, jtag_reg_addr_q, `endif @@ -152,12 +152,12 @@ module lm32_cpu ( jtag_reg_d, jtag_reg_addr_d, `endif -`ifdef CFG_USER_ENABLED +`ifdef CFG_USER_ENABLED user_valid, user_opcode, user_operand_0, user_operand_1, -`endif +`endif `ifdef CFG_IWB_ENABLED // Instruction Wishbone master I_DAT_O, @@ -198,11 +198,11 @@ parameter icache_bytes_per_line = `CFG_ICACHE_BYTES_PER_LINE; // Number of byt parameter icache_base_address = `CFG_ICACHE_BASE_ADDRESS; // Base address of cachable memory parameter icache_limit = `CFG_ICACHE_LIMIT; // Limit (highest address) of cachable memory `else -parameter icache_associativity = 1; -parameter icache_sets = 512; -parameter icache_bytes_per_line = 16; -parameter icache_base_address = 0; -parameter icache_limit = 0; +parameter icache_associativity = 1; +parameter icache_sets = 512; +parameter icache_bytes_per_line = 16; +parameter icache_base_address = 0; +parameter icache_limit = 0; `endif `ifdef CFG_DCACHE_ENABLED @@ -212,11 +212,11 @@ parameter dcache_bytes_per_line = `CFG_DCACHE_BYTES_PER_LINE; // Number of byt parameter dcache_base_address = `CFG_DCACHE_BASE_ADDRESS; // Base address of cachable memory parameter dcache_limit = `CFG_DCACHE_LIMIT; // Limit (highest address) of cachable memory `else -parameter dcache_associativity = 1; -parameter dcache_sets = 512; -parameter dcache_bytes_per_line = 16; -parameter dcache_base_address = 0; -parameter dcache_limit = 0; +parameter dcache_associativity = 1; +parameter dcache_sets = 512; +parameter dcache_bytes_per_line = 16; +parameter dcache_base_address = 0; +parameter dcache_limit = 0; `endif `ifdef CFG_DEBUG_ENABLED @@ -243,13 +243,13 @@ parameter interrupts = 0; input clk_i; // Clock `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE input clk_n_i; // Inverted clock -`endif +`endif input rst_i; // Reset `ifdef CFG_DEBUG_ENABLED - `ifdef CFG_ALTERNATE_EBA - input at_debug; // GPIO input that maps EBA to DEBA - `endif +`ifdef CFG_ALTERNATE_EBA +input at_debug; // GPIO input that maps EBA to DEBA +`endif `endif `ifdef CFG_INTERRUPTS_ENABLED @@ -259,12 +259,12 @@ input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins `ifdef CFG_USER_ENABLED input [`LM32_WORD_RNG] user_result; // User-defined instruction result input user_complete; // User-defined instruction execution is complete -`endif +`endif `ifdef CFG_JTAG_ENABLED input jtag_clk; // JTAG clock input jtag_update; // JTAG state machine is in data register update state -input [`LM32_BYTE_RNG] jtag_reg_q; +input [`LM32_BYTE_RNG] jtag_reg_q; input [2:0] jtag_reg_addr_q; `endif @@ -336,11 +336,11 @@ output I_STB_O; // Instruction Wishbone interfac wire I_STB_O; output I_WE_O; // Instruction Wishbone interface write enable wire I_WE_O; -output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type +output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type wire [`LM32_CTYPE_RNG] I_CTI_O; output I_LOCK_O; // Instruction Wishbone interface lock bus wire I_LOCK_O; -output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type +output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type wire [`LM32_BTYPE_RNG] I_BTE_O; `endif @@ -356,15 +356,15 @@ output D_STB_O; // Data Wishbone interface strob wire D_STB_O; output D_WE_O; // Data Wishbone interface write enable wire D_WE_O; -output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type +output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type wire [`LM32_CTYPE_RNG] D_CTI_O; output D_LOCK_O; // Date Wishbone interface lock bus wire D_LOCK_O; -output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type +output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type wire [`LM32_BTYPE_RNG] D_BTE_O; ///////////////////////////////////////////////////// -// Internal nets and registers +// Internal nets and registers ///////////////////////////////////////////////////// // Pipeline registers @@ -377,11 +377,11 @@ reg valid_d; // Instruction in D stage is val reg valid_x; // Instruction in X stage is valid reg valid_m; // Instruction in M stage is valid reg valid_w; // Instruction in W stage is valid - + wire q_x; wire [`LM32_WORD_RNG] immediate_d; // Immediate operand wire load_d; // Indicates a load instruction -reg load_x; +reg load_x; reg load_m; wire load_q_x; wire store_q_x; @@ -397,7 +397,7 @@ wire [`LM32_PC_RNG] branch_predict_address_d; // Address to which predicted br wire [`LM32_PC_RNG] branch_target_d; wire bi_unconditional; wire bi_conditional; -reg branch_x; +reg branch_x; reg branch_predict_x; reg branch_predict_taken_x; reg branch_m; @@ -418,7 +418,7 @@ reg x_result_sel_csr_x; wire x_result_sel_mc_arith_d; // Select X stage result from multi-cycle arithmetic unit reg x_result_sel_mc_arith_x; `endif -`ifdef LM32_NO_BARREL_SHIFT +`ifdef LM32_NO_BARREL_SHIFT wire x_result_sel_shift_d; // Select X stage result from shifter reg x_result_sel_shift_x; `endif @@ -453,9 +453,9 @@ reg w_result_sel_mul_m; reg w_result_sel_mul_w; `endif wire x_bypass_enable_d; // Whether result is bypassable in X stage -reg x_bypass_enable_x; +reg x_bypass_enable_x; wire m_bypass_enable_d; // Whether result is bypassable in M stage -reg m_bypass_enable_x; +reg m_bypass_enable_x; reg m_bypass_enable_m; wire sign_extend_d; // Whether to sign-extend or zero-extend reg sign_extend_x; @@ -471,19 +471,19 @@ wire [`LM32_REG_IDX_RNG] read_idx_0_d; // Register file read index 0 wire read_enable_1_d; // Register file read enable 1 wire [`LM32_REG_IDX_RNG] read_idx_1_d; // Register file read index 1 wire [`LM32_REG_IDX_RNG] write_idx_d; // Register file write index -reg [`LM32_REG_IDX_RNG] write_idx_x; +reg [`LM32_REG_IDX_RNG] write_idx_x; reg [`LM32_REG_IDX_RNG] write_idx_m; reg [`LM32_REG_IDX_RNG] write_idx_w; wire [`LM32_CSR_RNG] csr_d; // CSR read/write index -reg [`LM32_CSR_RNG] csr_x; +reg [`LM32_CSR_RNG] csr_x; wire [`LM32_CONDITION_RNG] condition_d; // Branch condition -reg [`LM32_CONDITION_RNG] condition_x; +reg [`LM32_CONDITION_RNG] condition_x; `ifdef CFG_DEBUG_ENABLED wire break_d; // Indicates a break instruction -reg break_x; +reg break_x; `endif wire scall_d; // Indicates a scall instruction -reg scall_x; +reg scall_x; wire eret_d; // Indicates an eret instruction reg eret_x; wire eret_q_x; @@ -528,8 +528,8 @@ reg [`LM32_WORD_RNG] operand_w; // Operand for W stage instructi // To/from register file `ifdef CFG_EBR_POSEDGE_REGISTER_FILE -reg [`LM32_WORD_RNG] reg_data_live_0; -reg [`LM32_WORD_RNG] reg_data_live_1; +reg [`LM32_WORD_RNG] reg_data_live_0; +reg [`LM32_WORD_RNG] reg_data_live_1; reg use_buf; // Whether to use reg_data_live or reg_data_buf reg [`LM32_WORD_RNG] reg_data_buf_0; reg [`LM32_WORD_RNG] reg_data_buf_1; @@ -538,7 +538,7 @@ reg [`LM32_WORD_RNG] reg_data_buf_1; `else reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1]; // Register file `endif -wire [`LM32_WORD_RNG] reg_data_0; // Register file read port 0 data +wire [`LM32_WORD_RNG] reg_data_0; // Register file read port 0 data wire [`LM32_WORD_RNG] reg_data_1; // Register file read port 1 data reg [`LM32_WORD_RNG] bypass_data_0; // Register value 0 after bypassing reg [`LM32_WORD_RNG] bypass_data_1; // Register value 1 after bypassing @@ -554,7 +554,7 @@ wire stall_m; // Stall instruction in M pipeli // To/from adder wire adder_op_d; // Whether to add or subtract -reg adder_op_x; +reg adder_op_x; reg adder_op_x_n; // Inverted version of adder_op_x wire [`LM32_WORD_RNG] adder_result_x; // Result from adder wire adder_overflow_x; // Whether a signed overflow occured @@ -562,7 +562,7 @@ wire adder_carry_n_x; // Whether a carry was generated // To/from logical operations unit wire [`LM32_LOGIC_OP_RNG] logic_op_d; // Which operation to perform -reg [`LM32_LOGIC_OP_RNG] logic_op_x; +reg [`LM32_LOGIC_OP_RNG] logic_op_x; wire [`LM32_WORD_RNG] logic_result_x; // Result of logical operation `ifdef CFG_SIGN_EXTEND_ENABLED @@ -576,10 +576,10 @@ wire [`LM32_WORD_RNG] sext_result_x; // Result of sign-extension spec `ifdef CFG_PL_BARREL_SHIFT_ENABLED `ifdef CFG_ROTATE_ENABLED wire rotate_d; // Whether we should rotate or shift -reg rotate_x; +reg rotate_x; `endif wire direction_d; // Which direction to shift in -reg direction_x; +reg direction_x; wire [`LM32_WORD_RNG] shifter_result_m; // Result of shifter `endif `ifdef CFG_MC_BARREL_SHIFT_ENABLED @@ -659,8 +659,8 @@ wire irom_stall_request_x; // Indicates D stage needs to be // To/from load/store unit `ifdef CFG_DCACHE_ENABLED -wire dflush_x; // Flush data cache -reg dflush_m; +wire dflush_x; // Flush data cache +reg dflush_m; wire dcache_stall_request; // Stall pipeline because data cache is busy wire dcache_restart_request; // Restart instruction that caused a data cache miss wire dcache_refill_request; // Request to refill data cache @@ -679,7 +679,7 @@ wire [`LM32_WORD_RNG] jrx_csr_read_data; // Read data for JRX CSR wire jtag_csr_write_enable; // Debugger CSR write enable wire [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR wire [`LM32_CSR_RNG] jtag_csr; // Which CSR to write -wire jtag_read_enable; +wire jtag_read_enable; wire [`LM32_BYTE_RNG] jtag_read_data; wire jtag_write_enable; wire [`LM32_BYTE_RNG] jtag_write_data; @@ -706,7 +706,7 @@ wire cmp_overflow; // Comparison produced an overfl wire cmp_carry_n; // Comparison produced a carry, inverted reg condition_met_x; // Condition of branch instruction is met reg condition_met_m; -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH wire branch_taken_x; // Branch is taken in X stage `endif wire branch_taken_m; // Branch is taken in M stage @@ -784,7 +784,7 @@ reg ext_break_r; ///////////////////////////////////////////////////// // Instantiations -///////////////////////////////////////////////////// +///////////////////////////////////////////////////// // Instruction unit lm32_instruction_unit #( @@ -798,9 +798,9 @@ lm32_instruction_unit #( .clk_i (clk_i), .rst_i (rst_i), `ifdef CFG_DEBUG_ENABLED - `ifdef CFG_ALTERNATE_EBA +`ifdef CFG_ALTERNATE_EBA .at_debug (at_debug), - `endif +`endif `endif // From pipeline .stall_a (stall_a), @@ -813,7 +813,7 @@ lm32_instruction_unit #( .kill_f (kill_f), .branch_predict_taken_d (branch_predict_taken_d), .branch_predict_address_d (branch_predict_address_d), -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH .branch_taken_x (branch_taken_x), .branch_target_x (branch_target_x), `endif @@ -833,7 +833,7 @@ lm32_instruction_unit #( .dcache_restart_request (dcache_restart_request), .dcache_refill_request (dcache_refill_request), .dcache_refilling (dcache_refilling), -`endif +`endif `ifdef CFG_IWB_ENABLED // From Wishbone .i_dat_i (I_DAT_I), @@ -898,12 +898,12 @@ lm32_decoder decoder ( `ifdef LM32_MC_ARITHMETIC_ENABLED .x_result_sel_mc_arith (x_result_sel_mc_arith_d), `endif -`ifdef LM32_NO_BARREL_SHIFT +`ifdef LM32_NO_BARREL_SHIFT .x_result_sel_shift (x_result_sel_shift_d), `endif `ifdef CFG_SIGN_EXTEND_ENABLED .x_result_sel_sext (x_result_sel_sext_d), -`endif +`endif .x_result_sel_logic (x_result_sel_logic_d), `ifdef CFG_USER_ENABLED .x_result_sel_user (x_result_sel_user_d), @@ -911,8 +911,8 @@ lm32_decoder decoder ( .x_result_sel_add (x_result_sel_add_d), .m_result_sel_compare (m_result_sel_compare_d), `ifdef CFG_PL_BARREL_SHIFT_ENABLED - .m_result_sel_shift (m_result_sel_shift_d), -`endif + .m_result_sel_shift (m_result_sel_shift_d), +`endif .w_result_sel_load (w_result_sel_load_d), `ifdef CFG_PL_MULTIPLY_ENABLED .w_result_sel_mul (w_result_sel_mul_d), @@ -964,9 +964,9 @@ lm32_decoder decoder ( .user_opcode (user_opcode_d), `endif .csr_write_enable (csr_write_enable_d) - ); + ); -// Load/store unit +// Load/store unit lm32_load_store_unit #( .associativity (dcache_associativity), .sets (dcache_sets), @@ -981,7 +981,6 @@ lm32_load_store_unit #( .stall_a (stall_a), .stall_x (stall_x), .stall_m (stall_m), - .kill_x (kill_x), .kill_m (kill_m), .exception_m (exception_m), .store_operand_x (store_operand_x), @@ -1014,7 +1013,7 @@ lm32_load_store_unit #( .dcache_restart_request (dcache_restart_request), .dcache_stall_request (dcache_stall_request), .dcache_refilling (dcache_refilling), -`endif +`endif `ifdef CFG_IROM_ENABLED .irom_store_data_m (irom_store_data_m), .irom_address_xm (irom_address_xm), @@ -1033,9 +1032,9 @@ lm32_load_store_unit #( .d_cti_o (D_CTI_O), .d_lock_o (D_LOCK_O), .d_bte_o (D_BTE_O) - ); - -// Adder + ); + +// Adder lm32_adder adder ( // ----- Inputs ------- .adder_op_x (adder_op_x), @@ -1058,7 +1057,7 @@ lm32_logic_op logic_op ( // ----- Outputs ------- .logic_result_x (logic_result_x) ); - + `ifdef CFG_PL_BARREL_SHIFT_ENABLED // Pipelined barrel-shifter lm32_shifter shifter ( @@ -1086,7 +1085,7 @@ lm32_multiplier multiplier ( .operand_0 (d_result_0), .operand_1 (d_result_1), // ----- Outputs ------- - .result (multiplier_result_w) + .result (multiplier_result_w) ); `endif @@ -1098,44 +1097,44 @@ lm32_mc_arithmetic mc_arithmetic ( .rst_i (rst_i), .stall_d (stall_d), .kill_x (kill_x), -`ifdef CFG_MC_DIVIDE_ENABLED +`ifdef CFG_MC_DIVIDE_ENABLED .divide_d (divide_q_d), .modulus_d (modulus_q_d), `endif -`ifdef CFG_MC_MULTIPLY_ENABLED +`ifdef CFG_MC_MULTIPLY_ENABLED .multiply_d (multiply_q_d), `endif `ifdef CFG_MC_BARREL_SHIFT_ENABLED .shift_left_d (shift_left_q_d), .shift_right_d (shift_right_q_d), .sign_extend_d (sign_extend_d), -`endif +`endif .operand_0_d (d_result_0), .operand_1_d (d_result_1), // ----- Outputs ------- .result_x (mc_result_x), -`ifdef CFG_MC_DIVIDE_ENABLED +`ifdef CFG_MC_DIVIDE_ENABLED .divide_by_zero_x (divide_by_zero_x), `endif .stall_request_x (mc_stall_request_x) ); `endif - + `ifdef CFG_INTERRUPTS_ENABLED // Interrupt unit lm32_interrupt interrupt_unit ( // ----- Inputs ------- - .clk_i (clk_i), + .clk_i (clk_i), .rst_i (rst_i), // From external devices .interrupt (interrupt), // From pipeline .stall_x (stall_x), `ifdef CFG_DEBUG_ENABLED - .non_debug_exception (non_debug_exception_q_w), + .non_debug_exception (non_debug_exception_q_w), .debug_exception (debug_exception_q_w), `else - .exception (exception_q_w), + .exception (exception_q_w), `endif .eret_q_x (eret_q_x), `ifdef CFG_DEBUG_ENABLED @@ -1175,7 +1174,7 @@ lm32_jtag jtag ( `endif `ifdef CFG_DEBUG_ENABLED .exception_q_w (debug_exception_q_w || non_debug_exception_q_w), -`endif +`endif // ----- Outputs ------- // To pipeline `ifdef CFG_JTAG_UART_ENABLED @@ -1195,7 +1194,7 @@ lm32_jtag jtag ( .jtag_break (jtag_break), .jtag_reset (reset_exception), `endif - // To JTAG + // To JTAG .jtag_reg_d (jtag_reg_d), .jtag_reg_addr_d (jtag_reg_addr_d) ); @@ -1208,7 +1207,7 @@ lm32_debug #( .watchpoints (watchpoints) ) hw_debug ( // ----- Inputs ------- - .clk_i (clk_i), + .clk_i (clk_i), .rst_i (rst_i), .pc_x (pc_x), .load_x (load_x), @@ -1251,37 +1250,37 @@ lm32_debug #( RAM has two read/write ports. To accomodate three accesses, two on-chip block RAMs are used (each register file "write" is made to both block RAMs). - - One limitation of the on-chip block RAMs is that one cannot perform a + + One limitation of the on-chip block RAMs is that one cannot perform a read and write to same location in a cycle (if this is done, then the data read out is indeterminate). ----------------------------------------------------------------------*/ wire [31:0] regfile_data_0, regfile_data_1; reg [31:0] w_result_d; - reg regfile_raw_0, regfile_raw_0_nxt; - reg regfile_raw_1, regfile_raw_1_nxt; - + reg regfile_raw_0, regfile_raw_0_nxt; + reg regfile_raw_1, regfile_raw_1_nxt; + /*---------------------------------------------------------------------- - Check if read and write is being performed to same register in current + Check if read and write is being performed to same register in current cycle? This is done by comparing the read and write IDXs. ----------------------------------------------------------------------*/ always @(reg_write_enable_q_w or write_idx_w or instruction_f) begin - if (reg_write_enable_q_w - && (write_idx_w == instruction_f[25:21])) - regfile_raw_0_nxt = 1'b1; - else - regfile_raw_0_nxt = 1'b0; - - if (reg_write_enable_q_w - && (write_idx_w == instruction_f[20:16])) - regfile_raw_1_nxt = 1'b1; - else - regfile_raw_1_nxt = 1'b0; + if (reg_write_enable_q_w + && (write_idx_w == instruction_f[25:21])) + regfile_raw_0_nxt = 1'b1; + else + regfile_raw_0_nxt = 1'b0; + + if (reg_write_enable_q_w + && (write_idx_w == instruction_f[20:16])) + regfile_raw_1_nxt = 1'b1; + else + regfile_raw_1_nxt = 1'b0; end - + /*---------------------------------------------------------------------- - Select latched (delayed) write value or data from register file. If + Select latched (delayed) write value or data from register file. If read in previous cycle was performed to register written to in same cycle, then latched (delayed) write value is selected. ----------------------------------------------------------------------*/ @@ -1290,9 +1289,9 @@ lm32_debug #( reg_data_live_0 = w_result_d; else reg_data_live_0 = regfile_data_0; - + /*---------------------------------------------------------------------- - Select latched (delayed) write value or data from register file. If + Select latched (delayed) write value or data from register file. If read in previous cycle was performed to register written to in same cycle, then latched (delayed) write value is selected. ----------------------------------------------------------------------*/ @@ -1301,24 +1300,24 @@ lm32_debug #( reg_data_live_1 = w_result_d; else reg_data_live_1 = regfile_data_1; - + /*---------------------------------------------------------------------- Latch value written to register file ----------------------------------------------------------------------*/ always @(posedge clk_i `CFG_RESET_SENSITIVITY) if (rst_i == `TRUE) begin - regfile_raw_0 <= 1'b0; - regfile_raw_1 <= 1'b0; - w_result_d <= 32'b0; + regfile_raw_0 <= 1'b0; + regfile_raw_1 <= 1'b0; + w_result_d <= 32'b0; end else begin - regfile_raw_0 <= regfile_raw_0_nxt; - regfile_raw_1 <= regfile_raw_1_nxt; - w_result_d <= w_result; + regfile_raw_0 <= regfile_raw_0_nxt; + regfile_raw_1 <= regfile_raw_1_nxt; + w_result_d <= w_result; end - + /*---------------------------------------------------------------------- Register file instantiation as Pseudo-Dual Port EBRs. ----------------------------------------------------------------------*/ @@ -1332,14 +1331,14 @@ lm32_debug #( reg_0 ( // ----- Inputs ----- - .clk_i (clk_i), - .rst_i (rst_i), - .we_i (reg_write_enable_q_w), - .wdata_i (w_result), - .waddr_i (write_idx_w), - .raddr_i (instruction_f[25:21]), + .clk_i (clk_i), + .rst_i (rst_i), + .we_i (reg_write_enable_q_w), + .wdata_i (w_result), + .waddr_i (write_idx_w), + .raddr_i (instruction_f[25:21]), // ----- Outputs ----- - .rdata_o (regfile_data_0) + .rdata_o (regfile_data_0) ); lm32_dp_ram @@ -1350,14 +1349,14 @@ lm32_debug #( reg_1 ( // ----- Inputs ----- - .clk_i (clk_i), - .rst_i (rst_i), - .we_i (reg_write_enable_q_w), - .wdata_i (w_result), - .waddr_i (write_idx_w), - .raddr_i (instruction_f[20:16]), + .clk_i (clk_i), + .rst_i (rst_i), + .we_i (reg_write_enable_q_w), + .wdata_i (w_result), + .waddr_i (write_idx_w), + .raddr_i (instruction_f[20:16]), // ----- Outputs ----- - .rdata_o (regfile_data_1) + .rdata_o (regfile_data_1) ); `endif @@ -1390,11 +1389,11 @@ lm32_debug #( .WrClockEn(`TRUE), .RdClockEn(stall_f == `FALSE), .WE(reg_write_enable_q_w), - .Reset(rst_i), + .Reset(rst_i), // ----- Outputs ----- .Q(reg_data_0) ); - + pmi_ram_dp #( // ----- Parameters ----- @@ -1423,7 +1422,7 @@ lm32_debug #( .WrClockEn(`TRUE), .RdClockEn(stall_f == `FALSE), .WE(reg_write_enable_q_w), - .Reset(rst_i), + .Reset(rst_i), // ----- Outputs ----- .Q(reg_data_1) ); @@ -1454,7 +1453,7 @@ assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == `TRUE); assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == `TRUE); assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == `TRUE); -// Interlock detection - Raise an interlock for RAW hazzards +// Interlock detection - Raise an interlock for RAW hazzards always @(*) begin if ( ( (x_bypass_enable_x == `FALSE) @@ -1476,7 +1475,7 @@ end // Bypass for reg port 0 always @(*) begin - if (raw_x_0 == `TRUE) + if (raw_x_0 == `TRUE) bypass_data_0 = x_result; else if (raw_m_0 == `TRUE) bypass_data_0 = m_result; @@ -1502,12 +1501,12 @@ end /*---------------------------------------------------------------------- Branch prediction is performed in D stage of pipeline. Only PC-relative branches are predicted: forward-pointing conditional branches are not- - taken, while backward-pointing conditional branches are taken. + taken, while backward-pointing conditional branches are taken. Unconditional branches are always predicted taken! ----------------------------------------------------------------------*/ assign branch_predict_d = bi_unconditional | bi_conditional; assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0); - + // Compute branch target address: Branch PC PLUS Offset assign branch_target_d = pc_d + branch_offset_d; @@ -1519,7 +1518,7 @@ end // D stage result selection always @(*) begin - d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; + d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; case (d_result_sel_1_d) `LM32_D_RESULT_SEL_1_ZERO: d_result_1 = {`LM32_WORD_WIDTH{1'b0}}; `LM32_D_RESULT_SEL_1_REG_1: d_result_1 = bypass_data_1; @@ -1528,7 +1527,7 @@ begin endcase end -`ifdef CFG_USER_ENABLED +`ifdef CFG_USER_ENABLED // Operands for user-defined instructions assign user_operand_0 = operand_0_x; assign user_operand_1 = operand_1_x; @@ -1563,13 +1562,13 @@ begin `LM32_CONDITION_GE: condition_met_x = cmp_negative == cmp_overflow; `LM32_CONDITION_GEU: condition_met_x = cmp_carry_n; default: condition_met_x = 1'bx; - endcase + endcase end // X stage result selection always @(*) begin - x_result = x_result_sel_add_x ? adder_result_x + x_result = x_result_sel_add_x ? adder_result_x : x_result_sel_csr_x ? csr_read_data_x `ifdef CFG_SIGN_EXTEND_ENABLED : x_result_sel_sext_x ? sext_result_x @@ -1593,7 +1592,7 @@ begin `ifdef CFG_PL_BARREL_SHIFT_ENABLED : m_result_sel_shift_m ? shifter_result_m `endif - : operand_m; + : operand_m; end // W stage result selection @@ -1606,101 +1605,101 @@ begin : operand_w; end -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH // Indicate when a branch should be taken in X stage assign branch_taken_x = (stall_x == `FALSE) && ( (branch_x == `TRUE) && ((condition_x == `LM32_CONDITION_U1) || (condition_x == `LM32_CONDITION_U2)) && (valid_x == `TRUE) && (branch_predict_x == `FALSE) - ); + ); `endif // Indicate when a branch should be taken in M stage (exceptions are a type of branch) -assign branch_taken_m = (stall_m == `FALSE) - && ( ( (branch_m == `TRUE) +assign branch_taken_m = (stall_m == `FALSE) + && ( ( (branch_m == `TRUE) && (valid_m == `TRUE) && ( ( (condition_met_m == `TRUE) - && (branch_predict_taken_m == `FALSE) - ) - || ( (condition_met_m == `FALSE) - && (branch_predict_m == `TRUE) - && (branch_predict_taken_m == `TRUE) - ) - ) - ) + && (branch_predict_taken_m == `FALSE) + ) + || ( (condition_met_m == `FALSE) + && (branch_predict_m == `TRUE) + && (branch_predict_taken_m == `TRUE) + ) + ) + ) || (exception_m == `TRUE) ); // Indicate when a branch in M stage is mispredicted as being taken assign branch_mispredict_taken_m = (condition_met_m == `FALSE) && (branch_predict_m == `TRUE) - && (branch_predict_taken_m == `TRUE); - + && (branch_predict_taken_m == `TRUE); + // Indicate when a branch in M stage will cause flush in X stage assign branch_flushX_m = (stall_m == `FALSE) - && ( ( (branch_m == `TRUE) + && ( ( (branch_m == `TRUE) && (valid_m == `TRUE) - && ( (condition_met_m == `TRUE) - || ( (condition_met_m == `FALSE) - && (branch_predict_m == `TRUE) - && (branch_predict_taken_m == `TRUE) - ) - ) - ) - || (exception_m == `TRUE) - ); + && ( (condition_met_m == `TRUE) + || ( (condition_met_m == `FALSE) + && (branch_predict_m == `TRUE) + && (branch_predict_taken_m == `TRUE) + ) + ) + ) + || (exception_m == `TRUE) + ); // Generate signal that will kill instructions in each pipeline stage when necessary assign kill_f = ( (valid_d == `TRUE) && (branch_predict_taken_d == `TRUE) - ) - || (branch_taken_m == `TRUE) -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH + ) + || (branch_taken_m == `TRUE) +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH || (branch_taken_x == `TRUE) `endif `ifdef CFG_ICACHE_ENABLED - || (icache_refill_request == `TRUE) + || (icache_refill_request == `TRUE) `endif -`ifdef CFG_DCACHE_ENABLED +`ifdef CFG_DCACHE_ENABLED || (dcache_refill_request == `TRUE) `endif ; -assign kill_d = (branch_taken_m == `TRUE) -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH +assign kill_d = (branch_taken_m == `TRUE) +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH || (branch_taken_x == `TRUE) `endif `ifdef CFG_ICACHE_ENABLED - || (icache_refill_request == `TRUE) -`endif -`ifdef CFG_DCACHE_ENABLED + || (icache_refill_request == `TRUE) +`endif +`ifdef CFG_DCACHE_ENABLED || (dcache_refill_request == `TRUE) `endif ; -assign kill_x = (branch_flushX_m == `TRUE) -`ifdef CFG_DCACHE_ENABLED +assign kill_x = (branch_flushX_m == `TRUE) +`ifdef CFG_DCACHE_ENABLED || (dcache_refill_request == `TRUE) `endif ; assign kill_m = `FALSE -`ifdef CFG_DCACHE_ENABLED +`ifdef CFG_DCACHE_ENABLED || (dcache_refill_request == `TRUE) `endif - ; + ; assign kill_w = `FALSE -`ifdef CFG_DCACHE_ENABLED +`ifdef CFG_DCACHE_ENABLED || (dcache_refill_request == `TRUE) -`endif +`endif ; // Exceptions `ifdef CFG_DEBUG_ENABLED assign breakpoint_exception = ( ( (break_x == `TRUE) - || (bp_match == `TRUE) - ) - && (valid_x == `TRUE) - ) + || (bp_match == `TRUE) + ) + && (valid_x == `TRUE) + ) `ifdef CFG_JTAG_ENABLED || (jtag_break == `TRUE) `endif @@ -1729,7 +1728,7 @@ assign system_call_exception = ( (scall_x == `TRUE) `ifdef CFG_BUS_ERRORS_ENABLED && (valid_x == `TRUE) `endif - ); + ); `ifdef CFG_DEBUG_ENABLED assign debug_exception_x = (breakpoint_exception == `TRUE) @@ -1751,10 +1750,10 @@ assign non_debug_exception_x = (system_call_exception == `TRUE) || ( (interrupt_exception == `TRUE) `ifdef LM32_SINGLE_STEP_ENABLED && (dc_ss == `FALSE) -`endif +`endif `ifdef CFG_BUS_ERRORS_ENABLED - && (store_q_m == `FALSE) - && (D_CYC_O == `FALSE) + && (store_q_m == `FALSE) + && (D_CYC_O == `FALSE) `endif ) `endif @@ -1774,10 +1773,10 @@ assign exception_x = (system_call_exception == `TRUE) || ( (interrupt_exception == `TRUE) `ifdef LM32_SINGLE_STEP_ENABLED && (dc_ss == `FALSE) -`endif +`endif `ifdef CFG_BUS_ERRORS_ENABLED - && (store_q_m == `FALSE) - && (D_CYC_O == `FALSE) + && (store_q_m == `FALSE) + && (D_CYC_O == `FALSE) `endif ) `endif @@ -1792,7 +1791,7 @@ begin if (reset_exception == `TRUE) eid_x = `LM32_EID_RESET; else -`endif +`endif `ifdef CFG_BUS_ERRORS_ENABLED if (data_bus_error_exception == `TRUE) eid_x = `LM32_EID_DATA_BUS_ERROR; @@ -1813,7 +1812,7 @@ begin `ifdef CFG_DEBUG_ENABLED if (watchpoint_exception == `TRUE) eid_x = `LM32_EID_WATCHPOINT; - else + else `endif `ifdef CFG_MC_DIVIDE_ENABLED if (divide_by_zero_exception == `TRUE) @@ -1824,7 +1823,7 @@ begin if ( (interrupt_exception == `TRUE) `ifdef LM32_SINGLE_STEP_ENABLED && (dc_ss == `FALSE) -`endif +`endif ) eid_x = `LM32_EID_INTERRUPT; else @@ -1835,59 +1834,59 @@ end // Stall generation assign stall_a = (stall_f == `TRUE); - + assign stall_f = (stall_d == `TRUE); - -assign stall_d = (stall_x == `TRUE) + +assign stall_d = (stall_x == `TRUE) || ( (interlock == `TRUE) && (kill_d == `FALSE) - ) - || ( ( (eret_d == `TRUE) - || (scall_d == `TRUE) + ) + || ( ( (eret_d == `TRUE) + || (scall_d == `TRUE) `ifdef CFG_BUS_ERRORS_ENABLED - || (bus_error_d == `TRUE) -`endif - ) - && ( (load_q_x == `TRUE) - || (load_q_m == `TRUE) - || (store_q_x == `TRUE) - || (store_q_m == `TRUE) - || (D_CYC_O == `TRUE) - ) + || (bus_error_d == `TRUE) +`endif + ) + && ( (load_q_x == `TRUE) + || (load_q_m == `TRUE) + || (store_q_x == `TRUE) + || (store_q_m == `TRUE) + || (D_CYC_O == `TRUE) + ) && (kill_d == `FALSE) - ) + ) `ifdef CFG_DEBUG_ENABLED - || ( ( (break_d == `TRUE) - || (bret_d == `TRUE) - ) - && ( (load_q_x == `TRUE) - || (store_q_x == `TRUE) - || (load_q_m == `TRUE) - || (store_q_m == `TRUE) - || (D_CYC_O == `TRUE) - ) + || ( ( (break_d == `TRUE) + || (bret_d == `TRUE) + ) + && ( (load_q_x == `TRUE) + || (store_q_x == `TRUE) + || (load_q_m == `TRUE) + || (store_q_m == `TRUE) + || (D_CYC_O == `TRUE) + ) && (kill_d == `FALSE) - ) -`endif + ) +`endif || ( (csr_write_enable_d == `TRUE) && (load_q_x == `TRUE) - ) + ) ; - + assign stall_x = (stall_m == `TRUE) `ifdef LM32_MC_ARITHMETIC_ENABLED || ( (mc_stall_request_x == `TRUE) && (kill_x == `FALSE) - ) + ) `endif `ifdef CFG_IROM_ENABLED // Stall load/store instruction in D stage if there is an ongoing store // operation to instruction ROM in M stage || ( (irom_stall_request_x == `TRUE) - && ( (load_d == `TRUE) - || (store_d == `TRUE) - ) - ) + && ( (load_d == `TRUE) + || (store_d == `TRUE) + ) + ) `endif ; @@ -1897,44 +1896,44 @@ assign stall_m = (stall_wb_load == `TRUE) `else || ( (D_CYC_O == `TRUE) && ( (store_m == `TRUE) - /* - Bug: Following loop does not allow interrupts to be services since - either D_CYC_O or store_m is always high during entire duration of - loop. - L1: addi r1, r1, 1 - sw (r2,0), r1 - bi L1 - - Introduce a single-cycle stall when a wishbone cycle is in progress - and a new store instruction is in Execute stage and a interrupt - exception has occured. This stall will ensure that D_CYC_O and - store_m will both be low for one cycle. - */ + /* + Bug: Following loop does not allow interrupts to be services since + either D_CYC_O or store_m is always high during entire duration of + loop. + L1: addi r1, r1, 1 + sw (r2,0), r1 + bi L1 + + Introduce a single-cycle stall when a wishbone cycle is in progress + and a new store instruction is in Execute stage and a interrupt + exception has occured. This stall will ensure that D_CYC_O and + store_m will both be low for one cycle. + */ `ifdef CFG_INTERRUPTS_ENABLED - || ((store_x == `TRUE) && (interrupt_exception == `TRUE)) + || ((store_x == `TRUE) && (interrupt_exception == `TRUE)) `endif || (load_m == `TRUE) || (load_x == `TRUE) - ) - ) -`endif + ) + ) +`endif `ifdef CFG_DCACHE_ENABLED || (dcache_stall_request == `TRUE) // Need to stall in case a taken branch is in M stage and data cache is only being flush, so wont be restarted -`endif +`endif `ifdef CFG_ICACHE_ENABLED || (icache_stall_request == `TRUE) // Pipeline needs to be stalled otherwise branches may be lost - || ((I_CYC_O == `TRUE) && ((branch_m == `TRUE) || (exception_m == `TRUE))) + || ((I_CYC_O == `TRUE) && ((branch_m == `TRUE) || (exception_m == `TRUE))) `else `ifdef CFG_IWB_ENABLED - || (I_CYC_O == `TRUE) + || (I_CYC_O == `TRUE) +`endif `endif -`endif `ifdef CFG_USER_ENABLED || ( (user_valid == `TRUE) // Stall whole pipeline, rather than just X stage, where the instruction is, so we don't have to worry about exceptions (maybe) && (user_complete == `FALSE) ) `endif - ; + ; // Qualify state changing control signals `ifdef LM32_MC_ARITHMETIC_ENABLED @@ -1957,13 +1956,13 @@ assign eret_q_x = (eret_x == `TRUE) && (q_x == `TRUE); `ifdef CFG_DEBUG_ENABLED assign bret_q_x = (bret_x == `TRUE) && (q_x == `TRUE); `endif -assign load_q_x = (load_x == `TRUE) +assign load_q_x = (load_x == `TRUE) && (q_x == `TRUE) `ifdef CFG_DEBUG_ENABLED && (bp_match == `FALSE) `endif ; -assign store_q_x = (store_x == `TRUE) +assign store_q_x = (store_x == `TRUE) && (q_x == `TRUE) `ifdef CFG_DEBUG_ENABLED && (bp_match == `FALSE) @@ -1971,15 +1970,15 @@ assign store_q_x = (store_x == `TRUE) ; `ifdef CFG_USER_ENABLED assign user_valid = (x_result_sel_user_x == `TRUE) && (q_x == `TRUE); -`endif +`endif assign q_m = (valid_m == `TRUE) && (kill_m == `FALSE) && (exception_m == `FALSE); assign load_q_m = (load_m == `TRUE) && (q_m == `TRUE); assign store_q_m = (store_m == `TRUE) && (q_m == `TRUE); `ifdef CFG_DEBUG_ENABLED assign debug_exception_q_w = ((debug_exception_w == `TRUE) && (valid_w == `TRUE)); -assign non_debug_exception_q_w = ((non_debug_exception_w == `TRUE) && (valid_w == `TRUE)); +assign non_debug_exception_q_w = ((non_debug_exception_w == `TRUE) && (valid_w == `TRUE)); `else -assign exception_q_w = ((exception_w == `TRUE) && (valid_w == `TRUE)); +assign exception_q_w = ((exception_w == `TRUE) && (valid_w == `TRUE)); `endif // Don't qualify register write enables with kill, as the signal is needed early, and it doesn't matter if the instruction is killed (except for the actual write - but that is handled separately) assign write_enable_q_x = (write_enable_x == `TRUE) && (valid_x == `TRUE) && (branch_flushX_m == `FALSE); @@ -2049,7 +2048,7 @@ assign cfg = { `else `FALSE, `endif -`ifdef LM32_MULTIPLY_ENABLED +`ifdef LM32_MULTIPLY_ENABLED `TRUE `else `FALSE @@ -2057,22 +2056,22 @@ assign cfg = { }; assign cfg2 = { - 30'b0, + 30'b0, `ifdef CFG_IROM_ENABLED - `TRUE, + `TRUE, `else - `FALSE, + `FALSE, `endif `ifdef CFG_DRAM_ENABLED - `TRUE + `TRUE `else - `FALSE + `FALSE `endif - }; - + }; + // Cache flush `ifdef CFG_ICACHE_ENABLED -assign iflush = ( (csr_write_enable_d == `TRUE) +assign iflush = ( (csr_write_enable_d == `TRUE) && (csr_d == `LM32_CSR_ICC) && (stall_d == `FALSE) && (kill_d == `FALSE) @@ -2081,21 +2080,21 @@ assign iflush = ( (csr_write_enable_d == `TRUE) `ifdef CFG_HW_DEBUG_ENABLED || ( (jtag_csr_write_enable == `TRUE) - && (jtag_csr == `LM32_CSR_ICC)) + && (jtag_csr == `LM32_CSR_ICC)) +`endif + ; `endif - ; -`endif `ifdef CFG_DCACHE_ENABLED -assign dflush_x = ( (csr_write_enable_q_x == `TRUE) +assign dflush_x = ( (csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DCC)) // Added by GSI: needed to flush cache after loading firmware per JTAG `ifdef CFG_HW_DEBUG_ENABLED || ( (jtag_csr_write_enable == `TRUE) - && (jtag_csr == `LM32_CSR_DCC)) + && (jtag_csr == `LM32_CSR_DCC)) +`endif + ; `endif - ; -`endif // Extract CSR index assign csr_d = read_idx_0_d[`LM32_CSR_RNG]; @@ -2107,7 +2106,7 @@ begin `ifdef CFG_INTERRUPTS_ENABLED `LM32_CSR_IE, `LM32_CSR_IM, - `LM32_CSR_IP: csr_read_data_x = interrupt_csr_read_data_x; + `LM32_CSR_IP: csr_read_data_x = interrupt_csr_read_data_x; `endif `ifdef CFG_CYCLE_COUNTER_ENABLED `LM32_CSR_CC: csr_read_data_x = cc; @@ -2118,11 +2117,11 @@ begin `LM32_CSR_DEBA: csr_read_data_x = {deba, 8'h00}; `endif `ifdef CFG_JTAG_UART_ENABLED - `LM32_CSR_JTX: csr_read_data_x = jtx_csr_read_data; + `LM32_CSR_JTX: csr_read_data_x = jtx_csr_read_data; `LM32_CSR_JRX: csr_read_data_x = jrx_csr_read_data; `endif `LM32_CSR_CFG2: csr_read_data_x = cfg2; - + default: csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}}; endcase end @@ -2193,7 +2192,7 @@ begin end end `endif - + `ifdef CFG_EXTERNAL_BREAK_ENABLED always @(posedge clk_i `CFG_RESET_SENSITIVITY) begin @@ -2209,45 +2208,45 @@ begin end `endif -// Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not +// Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not `ifdef CFG_ICACHE_ENABLED `ifdef CFG_DCACHE_ENABLED always @(*) begin - if ( (icache_refill_request == `TRUE) + if ( (icache_refill_request == `TRUE) || (dcache_refill_request == `TRUE) ) valid_a = `FALSE; - else if ( (icache_restart_request == `TRUE) - || (dcache_restart_request == `TRUE) - ) + else if ( (icache_restart_request == `TRUE) + || (dcache_restart_request == `TRUE) + ) valid_a = `TRUE; - else + else valid_a = !icache_refilling && !dcache_refilling; -end +end `else always @(*) begin - if (icache_refill_request == `TRUE) + if (icache_refill_request == `TRUE) valid_a = `FALSE; - else if (icache_restart_request == `TRUE) + else if (icache_restart_request == `TRUE) valid_a = `TRUE; - else + else valid_a = !icache_refilling; -end +end `endif `else `ifdef CFG_DCACHE_ENABLED always @(*) begin - if (dcache_refill_request == `TRUE) + if (dcache_refill_request == `TRUE) valid_a = `FALSE; - else if (dcache_restart_request == `TRUE) + else if (dcache_restart_request == `TRUE) valid_a = `TRUE; - else + else valid_a = !dcache_refilling; -end +end `endif `endif @@ -2262,15 +2261,15 @@ begin valid_w <= `FALSE; end else - begin + begin if ((kill_f == `TRUE) || (stall_a == `FALSE)) `ifdef LM32_CACHE_ENABLED - valid_f <= valid_a; + valid_f <= valid_a; `else valid_f <= `TRUE; -`endif +`endif else if (stall_f == `FALSE) - valid_f <= `FALSE; + valid_f <= `FALSE; if (kill_d == `TRUE) valid_d <= `FALSE; @@ -2278,7 +2277,7 @@ begin valid_d <= valid_f & !kill_f; else if (stall_d == `FALSE) valid_d <= `FALSE; - + if (stall_d == `FALSE) valid_x <= valid_d & !kill_d; else if (kill_x == `TRUE) @@ -2295,8 +2294,8 @@ begin if (stall_m == `FALSE) valid_w <= valid_m & !kill_m; - else - valid_w <= `FALSE; + else + valid_w <= `FALSE; end end @@ -2306,22 +2305,22 @@ begin if (rst_i == `TRUE) begin `ifdef CFG_USER_ENABLED - user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}}; -`endif + user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}}; +`endif operand_0_x <= {`LM32_WORD_WIDTH{1'b0}}; operand_1_x <= {`LM32_WORD_WIDTH{1'b0}}; store_operand_x <= {`LM32_WORD_WIDTH{1'b0}}; - branch_target_x <= {`LM32_PC_WIDTH{1'b0}}; + branch_target_x <= {`LM32_PC_WIDTH{1'b0}}; x_result_sel_csr_x <= `FALSE; `ifdef LM32_MC_ARITHMETIC_ENABLED x_result_sel_mc_arith_x <= `FALSE; `endif -`ifdef LM32_NO_BARREL_SHIFT +`ifdef LM32_NO_BARREL_SHIFT x_result_sel_shift_x <= `FALSE; `endif `ifdef CFG_SIGN_EXTEND_ENABLED x_result_sel_sext_x <= `FALSE; -`endif +`endif x_result_sel_logic_x <= `FALSE; `ifdef CFG_USER_ENABLED x_result_sel_user_x <= `FALSE; @@ -2330,7 +2329,7 @@ begin m_result_sel_compare_x <= `FALSE; `ifdef CFG_PL_BARREL_SHIFT_ENABLED m_result_sel_shift_x <= `FALSE; -`endif +`endif w_result_sel_load_x <= `FALSE; `ifdef CFG_PL_MULTIPLY_ENABLED w_result_sel_mul_x <= `FALSE; @@ -2376,7 +2375,7 @@ begin m_result_sel_compare_m <= `FALSE; `ifdef CFG_PL_BARREL_SHIFT_ENABLED m_result_sel_shift_m <= `FALSE; -`endif +`endif w_result_sel_load_m <= `FALSE; `ifdef CFG_PL_MULTIPLY_ENABLED w_result_sel_mul_m <= `FALSE; @@ -2384,11 +2383,11 @@ begin m_bypass_enable_m <= `FALSE; branch_m <= `FALSE; branch_predict_m <= `FALSE; - branch_predict_taken_m <= `FALSE; + branch_predict_taken_m <= `FALSE; exception_m <= `FALSE; load_m <= `FALSE; store_m <= `FALSE; - write_enable_m <= `FALSE; + write_enable_m <= `FALSE; write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}}; condition_met_m <= `FALSE; `ifdef CFG_DCACHE_ENABLED @@ -2396,18 +2395,18 @@ begin `endif `ifdef CFG_DEBUG_ENABLED debug_exception_m <= `FALSE; - non_debug_exception_m <= `FALSE; + non_debug_exception_m <= `FALSE; `endif - operand_w <= {`LM32_WORD_WIDTH{1'b0}}; + operand_w <= {`LM32_WORD_WIDTH{1'b0}}; w_result_sel_load_w <= `FALSE; `ifdef CFG_PL_MULTIPLY_ENABLED w_result_sel_mul_w <= `FALSE; `endif - write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}}; + write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}}; write_enable_w <= `FALSE; `ifdef CFG_DEBUG_ENABLED debug_exception_w <= `FALSE; - non_debug_exception_w <= `FALSE; + non_debug_exception_w <= `FALSE; `else exception_w <= `FALSE; `endif @@ -2418,26 +2417,26 @@ begin else begin // D/X stage registers - + if (stall_x == `FALSE) begin `ifdef CFG_USER_ENABLED - user_opcode <= user_opcode_d; -`endif + user_opcode <= user_opcode_d; +`endif operand_0_x <= d_result_0; operand_1_x <= d_result_1; store_operand_x <= bypass_data_1; - branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d; + branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d; x_result_sel_csr_x <= x_result_sel_csr_d; `ifdef LM32_MC_ARITHMETIC_ENABLED x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d; `endif -`ifdef LM32_NO_BARREL_SHIFT +`ifdef LM32_NO_BARREL_SHIFT x_result_sel_shift_x <= x_result_sel_shift_d; `endif `ifdef CFG_SIGN_EXTEND_ENABLED x_result_sel_sext_x <= x_result_sel_sext_d; -`endif +`endif x_result_sel_logic_x <= x_result_sel_logic_d; `ifdef CFG_USER_ENABLED x_result_sel_user_x <= x_result_sel_user_d; @@ -2446,7 +2445,7 @@ begin m_result_sel_compare_x <= m_result_sel_compare_d; `ifdef CFG_PL_BARREL_SHIFT_ENABLED m_result_sel_shift_x <= m_result_sel_shift_d; -`endif +`endif w_result_sel_load_x <= w_result_sel_load_d; `ifdef CFG_PL_MULTIPLY_ENABLED w_result_sel_mul_x <= w_result_sel_mul_d; @@ -2456,9 +2455,9 @@ begin load_x <= load_d; store_x <= store_d; branch_x <= branch_d; - branch_predict_x <= branch_predict_d; - branch_predict_taken_x <= branch_predict_taken_d; - write_idx_x <= write_idx_d; + branch_predict_x <= branch_predict_d; + branch_predict_taken_x <= branch_predict_taken_d; + write_idx_x <= write_idx_d; csr_x <= csr_d; size_x <= size_d; sign_extend_x <= sign_extend_d; @@ -2482,11 +2481,11 @@ begin `endif eret_x <= eret_d; `ifdef CFG_DEBUG_ENABLED - bret_x <= bret_d; + bret_x <= bret_d; `endif write_enable_x <= write_enable_d; end - + // X/M stage registers if (stall_m == `FALSE) @@ -2495,7 +2494,7 @@ begin m_result_sel_compare_m <= m_result_sel_compare_x; `ifdef CFG_PL_BARREL_SHIFT_ENABLED m_result_sel_shift_m <= m_result_sel_shift_x; -`endif +`endif if (exception_x == `TRUE) begin w_result_sel_load_m <= `FALSE; @@ -2513,46 +2512,46 @@ begin m_bypass_enable_m <= m_bypass_enable_x; load_m <= load_x; store_m <= store_x; -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH branch_m <= branch_x && !branch_taken_x; `else branch_m <= branch_x; - branch_predict_m <= branch_predict_x; - branch_predict_taken_m <= branch_predict_taken_x; + branch_predict_m <= branch_predict_x; + branch_predict_taken_m <= branch_predict_taken_x; `endif `ifdef CFG_DEBUG_ENABLED - // Data bus errors are generated by the wishbone and are - // made known to the processor only in next cycle (as a - // non-debug exception). A break instruction can be seen - // in same cycle (causing a debug exception). Handle non - // -debug exception first! - if (non_debug_exception_x == `TRUE) + // Data bus errors are generated by the wishbone and are + // made known to the processor only in next cycle (as a + // non-debug exception). A break instruction can be seen + // in same cycle (causing a debug exception). Handle non + // -debug exception first! + if (non_debug_exception_x == `TRUE) write_idx_m <= `LM32_EA_REG; else if (debug_exception_x == `TRUE) write_idx_m <= `LM32_BA_REG; - else + else write_idx_m <= write_idx_x; `else if (exception_x == `TRUE) write_idx_m <= `LM32_EA_REG; - else + else write_idx_m <= write_idx_x; `endif condition_met_m <= condition_met_x; `ifdef CFG_DEBUG_ENABLED - if (exception_x == `TRUE) - if ((dc_re == `TRUE) + if (exception_x == `TRUE) + if ( (dc_re == `TRUE) `ifdef CFG_ALTERNATE_EBA - || (at_debug == `TRUE) -`endif - - || ((debug_exception_x == `TRUE) - && (non_debug_exception_x == `FALSE))) - branch_target_m <= {deba, eid_x, {3{1'b0}}}; - else - branch_target_m <= {eba, eid_x, {3{1'b0}}}; - else - branch_target_m <= branch_target_x; + || (at_debug == `TRUE) +`endif + || ( (debug_exception_x == `TRUE) + && (non_debug_exception_x == `FALSE)) + ) + branch_target_m <= {deba, eid_x, {3{1'b0}}}; + else + branch_target_m <= {eba, eid_x, {3{1'b0}}}; + else + branch_target_m <= branch_target_x; `else branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x; `endif @@ -2564,31 +2563,31 @@ begin `endif eret_m <= eret_q_x; `ifdef CFG_DEBUG_ENABLED - bret_m <= bret_q_x; + bret_m <= bret_q_x; `endif - write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x; + write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x; `ifdef CFG_DEBUG_ENABLED debug_exception_m <= debug_exception_x; - non_debug_exception_m <= non_debug_exception_x; + non_debug_exception_m <= non_debug_exception_x; `endif end - + // State changing regs if (stall_m == `FALSE) begin if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE)) exception_m <= `TRUE; - else + else exception_m <= `FALSE; `ifdef CFG_BUS_ERRORS_ENABLED - data_bus_error_exception_m <= (data_bus_error_exception == `TRUE) + data_bus_error_exception_m <= (data_bus_error_exception == `TRUE) `ifdef CFG_DEBUG_ENABLED - && (reset_exception == `FALSE) + && (reset_exception == `FALSE) `endif - ; + ; `endif - end - + end + // M/W stage registers `ifdef CFG_BUS_ERRORS_ENABLED operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result; @@ -2604,7 +2603,7 @@ begin eid_w <= eid_m; eret_w <= eret_m; `ifdef CFG_DEBUG_ENABLED - bret_w <= bret_m; + bret_w <= bret_m; `endif `endif write_enable_w <= write_enable_m; @@ -2617,10 +2616,10 @@ begin `ifdef CFG_BUS_ERRORS_ENABLED if ( (stall_m == `FALSE) && (data_bus_error_exception == `FALSE) - && ( (load_q_m == `TRUE) + && ( (load_q_m == `TRUE) || (store_q_m == `TRUE) ) - ) + ) memop_pc_w <= pc_m; `endif end @@ -2642,11 +2641,11 @@ begin if (stall_d == `FALSE) use_buf <= `FALSE; else if (use_buf == `FALSE) - begin + begin reg_data_buf_0 <= reg_data_live_0; reg_data_buf_1 <= reg_data_live_1; use_buf <= `TRUE; - end + end if (reg_write_enable_q_w == `TRUE) begin if (write_idx_w == read_idx_0_d) @@ -2663,7 +2662,8 @@ end // Register file write port always @(posedge clk_i `CFG_RESET_SENSITIVITY) begin - if (rst_i == `TRUE) begin + if (rst_i == `TRUE) + begin registers[0] <= {`LM32_WORD_WIDTH{1'b0}}; registers[1] <= {`LM32_WORD_WIDTH{1'b0}}; registers[2] <= {`LM32_WORD_WIDTH{1'b0}}; @@ -2695,12 +2695,13 @@ begin registers[28] <= {`LM32_WORD_WIDTH{1'b0}}; registers[29] <= {`LM32_WORD_WIDTH{1'b0}}; registers[30] <= {`LM32_WORD_WIDTH{1'b0}}; - registers[31] <= {`LM32_WORD_WIDTH{1'b0}}; - end - else begin + registers[31] <= {`LM32_WORD_WIDTH{1'b0}}; + end + else + begin if (reg_write_enable_q_w == `TRUE) - registers[write_idx_w] <= w_result; - end + registers[write_idx_w] <= w_result; + end end `endif @@ -2729,7 +2730,7 @@ begin `else if (exception_q_w == `TRUE) `endif - begin + begin trace_exception <= `TRUE; trace_pc_valid <= `TRUE; trace_pc <= pc_w; @@ -2737,7 +2738,7 @@ begin end else trace_exception <= `FALSE; - + if ((valid_w == `TRUE) && (!kill_w)) begin // An instruction is commiting. Determine if it is non-sequential @@ -2765,14 +2766,14 @@ begin end end `endif - + ///////////////////////////////////////////////////// // Behavioural Logic ///////////////////////////////////////////////////// -// synthesis translate_off +// synthesis translate_off -// Reset register 0. Only needed for simulation. +// Reset register 0. Only needed for simulation. initial begin `ifdef LM32_EBR_REGISTER_FILE @@ -2784,5 +2785,5 @@ begin end // synthesis translate_on - -endmodule + +endmodule diff --git a/rtl/lm32_dcache.v b/rtl/lm32_dcache.v index fd50780..762478c 100644 --- a/rtl/lm32_dcache.v +++ b/rtl/lm32_dcache.v @@ -2,7 +2,7 @@ // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< // ------------------------------------------------------------------ // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED +// ALL RIGHTS RESERVED // ------------------------------------------------------------------ // // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. @@ -11,7 +11,7 @@ // // Lattice Semiconductor grants permission to use this code // pursuant to the terms of the Lattice Semiconductor Corporation -// Open Source License Agreement. +// Open Source License Agreement. // // Disclaimer: // @@ -43,12 +43,12 @@ // : Initial Release // Version : 7.0SP2, 3.0 // : No Change -// Version : 3.1 +// Version : 3.1 // : Support for user-selected resource usage when implementing // : cache memory. Additional parameters must be defined when // : invoking lm32_ram.v // ============================================================================= - + `include "lm32_include.v" `ifdef CFG_DCACHE_ENABLED @@ -77,10 +77,10 @@ // Module interface ///////////////////////////////////////////////////// -module lm32_dcache ( +module lm32_dcache ( // ----- Inputs ----- clk_i, - rst_i, + rst_i, stall_a, stall_x, stall_m, @@ -153,7 +153,7 @@ output stall_request; // Request pipeline be s wire stall_request; output restart_request; // Request to restart instruction that caused the cache miss reg restart_request; -output refill_request; // Request a refill +output refill_request; // Request a refill reg refill_request; output [`LM32_WORD_RNG] refill_address; // Address to refill from reg [`LM32_WORD_RNG] refill_address; @@ -163,7 +163,7 @@ output [`LM32_WORD_RNG] load_data; // Data read from cache wire [`LM32_WORD_RNG] load_data; ///////////////////////////////////////////////////// -// Internal nets and registers +// Internal nets and registers ///////////////////////////////////////////////////// wire read_port_enable; // Cache memory read port clock enable @@ -180,7 +180,7 @@ wire [`LM32_DC_TMEM_ADDR_RNG] tmem_read_address; // Tag memory read addre wire [`LM32_DC_TMEM_ADDR_RNG] tmem_write_address; // Tag memory write address wire [`LM32_DC_DMEM_ADDR_RNG] dmem_read_address; // Data memory read address wire [`LM32_DC_DMEM_ADDR_RNG] dmem_write_address; // Data memory write address -wire [`LM32_DC_TAGS_RNG] tmem_write_data; // Tag memory write data +wire [`LM32_DC_TAGS_RNG] tmem_write_data; // Tag memory write data reg [`LM32_WORD_RNG] dmem_write_data; // Data memory write data reg [`LM32_DC_STATE_RNG] state; // Current state of FSM @@ -205,85 +205,85 @@ genvar i, j; ///////////////////////////////////////////////////// generate - for (i = 0; i < associativity; i = i + 1) - begin : memories - // Way data + for (i = 0; i < associativity; i = i + 1) + begin : memories + // Way data if (`LM32_DC_DMEM_ADDR_WIDTH < 11) begin : data_memories - lm32_ram - #( - // ----- Parameters ------- - .data_width (32), - .address_width (`LM32_DC_DMEM_ADDR_WIDTH) + lm32_ram + #( + // ----- Parameters ------- + .data_width (32), + .address_width (`LM32_DC_DMEM_ADDR_WIDTH) // Modified for Milkymist: removed non-portable RAM parameters - ) way_0_data_ram - ( - // ----- Inputs ------- - .read_clk (clk_i), - .write_clk (clk_i), - .reset (rst_i), - .read_address (dmem_read_address), - .enable_read (read_port_enable), - .write_address (dmem_write_address), - .enable_write (write_port_enable), - .write_enable (way_dmem_we[i]), - .write_data (dmem_write_data), - // ----- Outputs ------- - .read_data (way_data[i]) - ); + ) way_0_data_ram + ( + // ----- Inputs ------- + .read_clk (clk_i), + .write_clk (clk_i), + .reset (rst_i), + .read_address (dmem_read_address), + .enable_read (read_port_enable), + .write_address (dmem_write_address), + .enable_write (write_port_enable), + .write_enable (way_dmem_we[i]), + .write_data (dmem_write_data), + // ----- Outputs ------- + .read_data (way_data[i]) + ); end else begin - for (j = 0; j < 4; j = j + 1) - begin : byte_memories - lm32_ram - #( - // ----- Parameters ------- - .data_width (8), - .address_width (`LM32_DC_DMEM_ADDR_WIDTH) + for (j = 0; j < 4; j = j + 1) + begin : byte_memories + lm32_ram + #( + // ----- Parameters ------- + .data_width (8), + .address_width (`LM32_DC_DMEM_ADDR_WIDTH) // Modified for Milkymist: removed non-portable RAM parameters - ) way_0_data_ram - ( - // ----- Inputs ------- - .read_clk (clk_i), - .write_clk (clk_i), - .reset (rst_i), - .read_address (dmem_read_address), - .enable_read (read_port_enable), - .write_address (dmem_write_address), - .enable_write (write_port_enable), - .write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)), - .write_data (dmem_write_data[(j+1)*8-1:j*8]), - // ----- Outputs ------- - .read_data (way_data[i][(j+1)*8-1:j*8]) - ); - end + ) way_0_data_ram + ( + // ----- Inputs ------- + .read_clk (clk_i), + .write_clk (clk_i), + .reset (rst_i), + .read_address (dmem_read_address), + .enable_read (read_port_enable), + .write_address (dmem_write_address), + .enable_write (write_port_enable), + .write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)), + .write_data (dmem_write_data[(j+1)*8-1:j*8]), + // ----- Outputs ------- + .read_data (way_data[i][(j+1)*8-1:j*8]) + ); + end end - - // Way tags - lm32_ram - #( - // ----- Parameters ------- - .data_width (`LM32_DC_TAGS_WIDTH), - .address_width (`LM32_DC_TMEM_ADDR_WIDTH) + + // Way tags + lm32_ram + #( + // ----- Parameters ------- + .data_width (`LM32_DC_TAGS_WIDTH), + .address_width (`LM32_DC_TMEM_ADDR_WIDTH) // Modified for Milkymist: removed non-portable RAM parameters - ) way_0_tag_ram - ( - // ----- Inputs ------- - .read_clk (clk_i), - .write_clk (clk_i), - .reset (rst_i), - .read_address (tmem_read_address), - .enable_read (read_port_enable), - .write_address (tmem_write_address), - .enable_write (`TRUE), - .write_enable (way_tmem_we[i]), - .write_data (tmem_write_data), - // ----- Outputs ------- - .read_data ({way_tag[i], way_valid[i]}) - ); - end - + ) way_0_tag_ram + ( + // ----- Inputs ------- + .read_clk (clk_i), + .write_clk (clk_i), + .reset (rst_i), + .read_address (tmem_read_address), + .enable_read (read_port_enable), + .write_address (tmem_write_address), + .enable_write (`TRUE), + .write_enable (way_tmem_we[i]), + .write_data (tmem_write_data), + // ----- Outputs ------- + .read_data ({way_tag[i], way_valid[i]}) + ); + end + endgenerate ///////////////////////////////////////////////////// @@ -298,15 +298,15 @@ assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TA end endgenerate -// Select data from way that matched the address being read +// Select data from way that matched the address being read generate - if (associativity == 1) - begin : data_1 + if (associativity == 1) + begin : data_1 assign load_data = way_data[0]; end else if (associativity == 2) - begin : data_2 -assign load_data = way_match[0] ? way_data[0] : way_data[1]; + begin : data_2 +assign load_data = way_match[0] ? way_data[0] : way_data[1]; end endgenerate @@ -341,26 +341,26 @@ end endgenerate // Compute address to use to index into the data memories -generate +generate if (bytes_per_line > 4) -assign dmem_write_address = (refill == `TRUE) +assign dmem_write_address = (refill == `TRUE) ? {refill_address[`LM32_DC_ADDR_SET_RNG], refill_offset} : address_m[`LM32_DC_ADDR_IDX_RNG]; else -assign dmem_write_address = (refill == `TRUE) +assign dmem_write_address = (refill == `TRUE) ? refill_address[`LM32_DC_ADDR_SET_RNG] : address_m[`LM32_DC_ADDR_IDX_RNG]; endgenerate assign dmem_read_address = address_x[`LM32_DC_ADDR_IDX_RNG]; -// Compute address to use to index into the tag memories +// Compute address to use to index into the tag memories assign tmem_write_address = (flushing == `TRUE) ? flush_set : refill_address[`LM32_DC_ADDR_SET_RNG]; assign tmem_read_address = address_x[`LM32_DC_ADDR_SET_RNG]; // Compute signal to indicate when we are on the last refill accesses -generate - if (bytes_per_line > 4) +generate + if (bytes_per_line > 4) assign last_refill = refill_offset == {addr_offset_width{1'b1}}; else assign last_refill = `TRUE; @@ -375,12 +375,12 @@ assign valid_store = (store_q_m == `TRUE) && (check == `TRUE); // Compute data and tag memory write enables generate - if (associativity == 1) - begin : we_1 + if (associativity == 1) + begin : we_1 assign way_dmem_we[0] = (refill_ready == `TRUE) || ((valid_store == `TRUE) && (way_match[0] == `TRUE)); assign way_tmem_we[0] = (refill_ready == `TRUE) || (flushing == `TRUE); - end - else + end + else begin : we_2 assign way_dmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || ((valid_store == `TRUE) && (way_match[0] == `TRUE)); assign way_dmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || ((valid_store == `TRUE) && (way_match[1] == `TRUE)); @@ -400,34 +400,34 @@ assign refill = state[2]; assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE); assign stall_request = (check == `FALSE); - + ///////////////////////////////////////////////////// // Sequential logic ///////////////////////////////////////////////////// // Record way selected for replacement on a cache miss generate - if (associativity >= 2) - begin : way_select + if (associativity >= 2) + begin : way_select always @(posedge clk_i `CFG_RESET_SENSITIVITY) begin if (rst_i == `TRUE) refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; else - begin + begin if (refill_request == `TRUE) refill_way_select <= {refill_way_select[0], refill_way_select[1]}; end end - end -endgenerate + end +endgenerate // Record whether we are currently refilling always @(posedge clk_i `CFG_RESET_SENSITIVITY) begin if (rst_i == `TRUE) refilling <= `FALSE; - else + else refilling <= refill; end @@ -442,18 +442,18 @@ begin refill_address <= {`LM32_WORD_WIDTH{1'bx}}; restart_request <= `FALSE; end - else + else begin case (state) - // Flush the cache + // Flush the cache `LM32_DC_STATE_FLUSH: begin if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}}) state <= `LM32_DC_STATE_CHECK; flush_set <= flush_set - 1'b1; end - + // Check for cache misses `LM32_DC_STATE_CHECK: begin @@ -482,8 +482,8 @@ begin end end end - - endcase + + endcase end end @@ -495,10 +495,10 @@ always @(posedge clk_i `CFG_RESET_SENSITIVITY) begin if (rst_i == `TRUE) refill_offset <= {addr_offset_width{1'b0}}; - else + else begin case (state) - + // Check for cache misses `LM32_DC_STATE_CHECK: begin @@ -512,8 +512,8 @@ begin if (refill_ready == `TRUE) refill_offset <= refill_offset + 1'b1; end - - endcase + + endcase end end end diff --git a/rtl/lm32_debug.v b/rtl/lm32_debug.v index 5a22a2e..d697fab 100644 --- a/rtl/lm32_debug.v +++ b/rtl/lm32_debug.v @@ -2,7 +2,7 @@ // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< // ------------------------------------------------------------------ // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED +// ALL RIGHTS RESERVED // ------------------------------------------------------------------ // // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. @@ -11,7 +11,7 @@ // // Lattice Semiconductor grants permission to use this code // pursuant to the terms of the Lattice Semiconductor Corporation -// Open Source License Agreement. +// Open Source License Agreement. // // Disclaimer: // @@ -46,7 +46,7 @@ // Version : 3.1 // : No Change // Version : 3.2 -// : Fixed simulation bug which flares up when number of +// : Fixed simulation bug which flares up when number of // : watchpoints is zero. // ============================================================================= @@ -68,7 +68,7 @@ module lm32_debug ( // ----- Inputs ------- - clk_i, + clk_i, rst_i, pc_x, load_x, @@ -100,7 +100,7 @@ module lm32_debug ( bp_match, wp_match ); - + ///////////////////////////////////////////////////// // Parameters ///////////////////////////////////////////////////// @@ -131,10 +131,10 @@ input [`LM32_CSR_RNG] jtag_csr; // Which CSR to write input eret_q_x; // eret instruction in X stage input bret_q_x; // bret instruction in X stage input stall_x; // Instruction in X stage is stalled -input exception_x; // An exception has occured in X stage +input exception_x; // An exception has occured in X stage input q_x; // Indicates the instruction in the X stage is qualified `ifdef CFG_DCACHE_ENABLED -input dcache_refill_request; // Indicates data cache wants to be refilled +input dcache_refill_request; // Indicates data cache wants to be refilled `endif `endif @@ -149,12 +149,12 @@ reg dc_ss; output dc_re; // Remap exceptions reg dc_re; output bp_match; // Indicates a breakpoint has matched -wire bp_match; +wire bp_match; output wp_match; // Indicates a watchpoint has matched wire wp_match; ///////////////////////////////////////////////////// -// Internal nets and registers +// Internal nets and registers ///////////////////////////////////////////////////// genvar i; // Loop index for generate statements @@ -194,35 +194,35 @@ generate assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == `TRUE)); end endgenerate -generate +generate `ifdef LM32_SINGLE_STEP_ENABLED - if (breakpoints > 0) + if (breakpoints > 0) assign bp_match = (|bp_match_n) || (state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT); else assign bp_match = state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT; `else - if (breakpoints > 0) + if (breakpoints > 0) assign bp_match = |bp_match_n; else assign bp_match = `FALSE; `endif -endgenerate - +endgenerate + // Check for watchpoints -generate +generate for (i = 0; i < watchpoints; i = i + 1) begin : wp_comb assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1])); - end + end endgenerate generate - if (watchpoints > 0) -assign wp_match = |wp_match_n; + if (watchpoints > 0) +assign wp_match = |wp_match_n; else assign wp_match = `FALSE; endgenerate - -`ifdef CFG_HW_DEBUG_ENABLED + +`ifdef CFG_HW_DEBUG_ENABLED // Multiplex between wcsr instruction writes and debugger writes to the debug CSRs assign debug_csr_write_enable = (csr_write_enable_x == `TRUE) || (jtag_csr_write_enable == `TRUE); assign debug_csr_write_data = jtag_csr_write_enable == `TRUE ? jtag_csr_write_data : csr_write_data; @@ -256,7 +256,7 @@ begin bp_e[i] <= debug_csr_write_data[0]; end end -end +end end endgenerate @@ -280,7 +280,7 @@ begin if (debug_csr == `LM32_CSR_WP0 + i) wp[i] <= debug_csr_write_data; end - end + end end end endgenerate @@ -295,7 +295,7 @@ begin if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC)) dc_re <= debug_csr_write_data[1]; end -end +end `ifdef LM32_SINGLE_STEP_ENABLED // Single-step control flag @@ -311,9 +311,9 @@ begin if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC)) begin dc_ss <= debug_csr_write_data[0]; - if (debug_csr_write_data[0] == `FALSE) + if (debug_csr_write_data[0] == `FALSE) state <= `LM32_DEBUG_SS_STATE_IDLE; - else + else state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET; end case (state) @@ -325,7 +325,7 @@ begin ) && (stall_x == `FALSE) ) - state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; + state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; end `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN: begin @@ -339,7 +339,7 @@ begin `ifdef CFG_DCACHE_ENABLED if (dcache_refill_request == `TRUE) state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; - else + else `endif if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE)) begin @@ -353,7 +353,7 @@ begin `ifdef CFG_DCACHE_ENABLED if (dcache_refill_request == `TRUE) state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; - else + else `endif state <= `LM32_DEBUG_SS_STATE_IDLE; end diff --git a/rtl/lm32_decoder.v b/rtl/lm32_decoder.v index be20c16..c206ec7 100644 --- a/rtl/lm32_decoder.v +++ b/rtl/lm32_decoder.v @@ -2,7 +2,7 @@ // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< // ------------------------------------------------------------------ // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED +// ALL RIGHTS RESERVED // ------------------------------------------------------------------ // // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. @@ -11,7 +11,7 @@ // // Lattice Semiconductor grants permission to use this code // pursuant to the terms of the Lattice Semiconductor Corporation -// Open Source License Agreement. +// Open Source License Agreement. // // Disclaimer: // @@ -115,17 +115,17 @@ module lm32_decoder ( instruction, // ----- Outputs ------- d_result_sel_0, - d_result_sel_1, + d_result_sel_1, x_result_sel_csr, `ifdef LM32_MC_ARITHMETIC_ENABLED x_result_sel_mc_arith, -`endif -`ifdef LM32_NO_BARREL_SHIFT +`endif +`ifdef LM32_NO_BARREL_SHIFT x_result_sel_shift, `endif `ifdef CFG_SIGN_EXTEND_ENABLED x_result_sel_sext, -`endif +`endif x_result_sel_logic, `ifdef CFG_USER_ENABLED x_result_sel_user, @@ -133,8 +133,8 @@ module lm32_decoder ( x_result_sel_add, m_result_sel_compare, `ifdef CFG_PL_BARREL_SHIFT_ENABLED - m_result_sel_shift, -`endif + m_result_sel_shift, +`endif w_result_sel_load, `ifdef CFG_PL_MULTIPLY_ENABLED w_result_sel_mul, @@ -208,7 +208,7 @@ reg x_result_sel_csr; output x_result_sel_mc_arith; reg x_result_sel_mc_arith; `endif -`ifdef LM32_NO_BARREL_SHIFT +`ifdef LM32_NO_BARREL_SHIFT output x_result_sel_shift; reg x_result_sel_shift; `endif @@ -318,7 +318,7 @@ output csr_write_enable; wire csr_write_enable; ///////////////////////////////////////////////////// -// Internal nets and registers +// Internal nets and registers ///////////////////////////////////////////////////// wire [`LM32_WORD_RNG] extended_immediate; // Zero or sign extended immediate @@ -326,8 +326,8 @@ wire [`LM32_WORD_RNG] high_immediate; // Immediate as high 16 bits wire [`LM32_WORD_RNG] call_immediate; // Call immediate wire [`LM32_WORD_RNG] branch_immediate; // Conditional branch immediate wire sign_extend_immediate; // Whether the immediate should be sign extended (`TRUE) or zero extended (`FALSE) -wire select_high_immediate; // Whether to select the high immediate -wire select_call_immediate; // Whether to select the call immediate +wire select_high_immediate; // Whether to select the high immediate +wire select_call_immediate; // Whether to select the call immediate ///////////////////////////////////////////////////// // Functions @@ -383,7 +383,7 @@ assign op_sexth = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTH; `endif assign op_sh = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SH; `ifdef LM32_BARREL_SHIFT_ENABLED -assign op_sl = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SL; +assign op_sl = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SL; `endif assign op_sr = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SR; assign op_sru = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SRU; @@ -419,7 +419,7 @@ assign sext = op_sextb | op_sexth; assign multiply = op_mul; `endif `ifdef CFG_MC_DIVIDE_ENABLED -assign divide = op_divu; +assign divide = op_divu; assign modulus = op_modu; `endif assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw; @@ -429,16 +429,16 @@ assign store = op_sb | op_sh | op_sw; always @(*) begin // D stage - if (call) + if (call) d_result_sel_0 = `LM32_D_RESULT_SEL_0_NEXT_PC; - else + else d_result_sel_0 = `LM32_D_RESULT_SEL_0_REG_0; - if (call) - d_result_sel_1 = `LM32_D_RESULT_SEL_1_ZERO; - else if ((instruction[31] == 1'b0) && !bra) + if (call) + d_result_sel_1 = `LM32_D_RESULT_SEL_1_ZERO; + else if ((instruction[31] == 1'b0) && !bra) d_result_sel_1 = `LM32_D_RESULT_SEL_1_IMMEDIATE; else - d_result_sel_1 = `LM32_D_RESULT_SEL_1_REG_1; + d_result_sel_1 = `LM32_D_RESULT_SEL_1_REG_1; // X stage x_result_sel_csr = `FALSE; `ifdef LM32_MC_ARITHMETIC_ENABLED @@ -451,43 +451,43 @@ begin x_result_sel_sext = `FALSE; `endif x_result_sel_logic = `FALSE; -`ifdef CFG_USER_ENABLED +`ifdef CFG_USER_ENABLED x_result_sel_user = `FALSE; `endif x_result_sel_add = `FALSE; if (op_rcsr) x_result_sel_csr = `TRUE; -`ifdef LM32_MC_ARITHMETIC_ENABLED +`ifdef LM32_MC_ARITHMETIC_ENABLED `ifdef CFG_MC_BARREL_SHIFT_ENABLED - else if (shift_left | shift_right) + else if (shift_left | shift_right) x_result_sel_mc_arith = `TRUE; `endif `ifdef CFG_MC_DIVIDE_ENABLED else if (divide | modulus) - x_result_sel_mc_arith = `TRUE; + x_result_sel_mc_arith = `TRUE; `endif `ifdef CFG_MC_MULTIPLY_ENABLED else if (multiply) - x_result_sel_mc_arith = `TRUE; + x_result_sel_mc_arith = `TRUE; `endif `endif `ifdef LM32_NO_BARREL_SHIFT else if (shift) - x_result_sel_shift = `TRUE; + x_result_sel_shift = `TRUE; `endif `ifdef CFG_SIGN_EXTEND_ENABLED else if (sext) x_result_sel_sext = `TRUE; -`endif - else if (logical) +`endif + else if (logical) x_result_sel_logic = `TRUE; -`ifdef CFG_USER_ENABLED +`ifdef CFG_USER_ENABLED else if (op_user) x_result_sel_user = `TRUE; `endif - else - x_result_sel_add = `TRUE; - + else + x_result_sel_add = `TRUE; + // M stage m_result_sel_compare = cmp; @@ -498,17 +498,17 @@ begin // W stage w_result_sel_load = load; `ifdef CFG_PL_MULTIPLY_ENABLED - w_result_sel_mul = op_mul; + w_result_sel_mul = op_mul; `endif end // Set if result is valid at end of X stage -assign x_bypass_enable = arith +assign x_bypass_enable = arith | logical `ifdef CFG_MC_BARREL_SHIFT_ENABLED | shift_left | shift_right -`endif +`endif `ifdef CFG_MC_MULTIPLY_ENABLED | multiply `endif @@ -518,40 +518,40 @@ assign x_bypass_enable = arith `endif `ifdef LM32_NO_BARREL_SHIFT | shift -`endif +`endif `ifdef CFG_SIGN_EXTEND_ENABLED - | sext -`endif + | sext +`endif `ifdef CFG_USER_ENABLED | op_user `endif | op_rcsr ; -// Set if result is valid at end of M stage -assign m_bypass_enable = x_bypass_enable +// Set if result is valid at end of M stage +assign m_bypass_enable = x_bypass_enable `ifdef CFG_PL_BARREL_SHIFT_ENABLED | shift `endif | cmp ; -// Register file read port 0 +// Register file read port 0 assign read_enable_0 = ~(op_bi | op_calli); assign read_idx_0 = instruction[25:21]; -// Register file read port 1 +// Register file read port 1 assign read_enable_1 = ~(op_bi | op_calli | load); assign read_idx_1 = instruction[20:16]; // Register file write port assign write_enable = ~(bra | op_raise | store | op_wcsr); assign write_idx = call ? 5'd29 - : instruction[31] == 1'b0 - ? instruction[20:16] + : instruction[31] == 1'b0 + ? instruction[20:16] : instruction[15:11]; - -// Size of load/stores + +// Size of load/stores assign size = instruction[27:26]; // Whether to sign or zero extend -assign sign_extend = instruction[28]; +assign sign_extend = instruction[28]; // Set adder_op to 1 to perform a subtraction assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra; // Logic operation (and, or, etc) @@ -563,7 +563,7 @@ assign direction = instruction[29]; // Control flow microcodes assign branch = bra | call; assign branch_reg = op_call | op_b; -assign condition = instruction[28:26]; +assign condition = instruction[28:26]; `ifdef CFG_DEBUG_ENABLED assign break_opcode = op_raise & ~instruction[2]; `endif @@ -590,13 +590,13 @@ assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, inst assign call_immediate = {{6{instruction[25]}}, instruction[25:0]}; assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]}; -assign immediate = select_high_immediate == `TRUE - ? high_immediate +assign immediate = select_high_immediate == `TRUE + ? high_immediate : extended_immediate; - -assign branch_offset = select_call_immediate == `TRUE + +assign branch_offset = select_call_immediate == `TRUE ? call_immediate : branch_immediate; - -endmodule + +endmodule diff --git a/rtl/lm32_dp_ram.v b/rtl/lm32_dp_ram.v index bc752b0..be9b225 100644 --- a/rtl/lm32_dp_ram.v +++ b/rtl/lm32_dp_ram.v @@ -3,15 +3,15 @@ ///////////////////////////////////////////////////// module lm32_dp_ram( - // ----- Inputs ----- - clk_i, - rst_i, - we_i, - waddr_i, - wdata_i, - raddr_i, - // ----- Outputs ----- - rdata_o + // ----- Inputs ----- + clk_i, + rst_i, + we_i, + waddr_i, + wdata_i, + raddr_i, + // ----- Outputs ----- + rdata_o ); ///////////////////////////////////////////////////// @@ -57,9 +57,9 @@ assign rdata_o = mem[raddr_r]; always @(posedge clk_i) begin - if (we_i) - mem[waddr_i] <= wdata_i; - raddr_r <= raddr_i; + if (we_i) + mem[waddr_i] <= wdata_i; + raddr_r <= raddr_i; end endmodule diff --git a/rtl/lm32_icache.v b/rtl/lm32_icache.v index b329d8e..b26fcd2 100644 --- a/rtl/lm32_icache.v +++ b/rtl/lm32_icache.v @@ -2,7 +2,7 @@ // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< // ------------------------------------------------------------------ // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED +// ALL RIGHTS RESERVED // ------------------------------------------------------------------ // // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. @@ -11,7 +11,7 @@ // // Lattice Semiconductor grants permission to use this code // pursuant to the terms of the Lattice Semiconductor Corporation -// Open Source License Agreement. +// Open Source License Agreement. // // Disclaimer: // @@ -39,7 +39,7 @@ // File : lm32_icache.v // Title : Instruction cache // Dependencies : lm32_include.v -// +// // Version 3.5 // 1. Bug Fix: Instruction cache flushes issued from Instruction Inline Memory // cause segmentation fault due to incorrect fetches. @@ -53,7 +53,7 @@ // Version 7.0SP2, 3.0 // No change // ============================================================================= - + `include "lm32_include.v" `ifdef CFG_ICACHE_ENABLED @@ -83,10 +83,10 @@ // Module interface ///////////////////////////////////////////////////// -module lm32_icache ( +module lm32_icache ( // ----- Inputs ----- clk_i, - rst_i, + rst_i, stall_a, stall_f, address_a, @@ -133,7 +133,7 @@ localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1); // Inputs ///////////////////////////////////////////////////// -input clk_i; // Clock +input clk_i; // Clock input rst_i; // Reset input stall_a; // Stall instruction in A stage @@ -141,7 +141,7 @@ input stall_f; // Stall instruction in F st input valid_d; // Valid instruction in D stage input branch_predict_taken_d; // Instruction in D stage is a branch and is predicted taken - + input [`LM32_PC_RNG] address_a; // Address of instruction in A stage input [`LM32_PC_RNG] address_f; // Address of instruction in F stage input read_enable_f; // Indicates if cache access is valid @@ -153,7 +153,7 @@ input iflush; // Flush the cache `ifdef CFG_IROM_ENABLED input select_f; // Instruction in F stage is mapped through instruction cache `endif - + ///////////////////////////////////////////////////// // Outputs ///////////////////////////////////////////////////// @@ -165,14 +165,14 @@ reg restart_request; output refill_request; // Request to refill a cache line wire refill_request; output [`LM32_PC_RNG] refill_address; // Base address of cache refill -reg [`LM32_PC_RNG] refill_address; +reg [`LM32_PC_RNG] refill_address; output refilling; // Indicates the instruction cache is currently refilling reg refilling; output [`LM32_INSTRUCTION_RNG] inst; // Instruction read from cache wire [`LM32_INSTRUCTION_RNG] inst; ///////////////////////////////////////////////////// -// Internal nets and registers +// Internal nets and registers ///////////////////////////////////////////////////// wire enable; @@ -211,55 +211,55 @@ genvar i; generate for (i = 0; i < associativity; i = i + 1) - begin : memories - - lm32_ram - #( - // ----- Parameters ------- - .data_width (32), - .address_width (`LM32_IC_DMEM_ADDR_WIDTH) + begin : memories + + lm32_ram + #( + // ----- Parameters ------- + .data_width (32), + .address_width (`LM32_IC_DMEM_ADDR_WIDTH) // Modified for Milkymist: removed non-portable RAM parameters -) - way_0_data_ram - ( - // ----- Inputs ------- - .read_clk (clk_i), - .write_clk (clk_i), - .reset (rst_i), - .read_address (dmem_read_address), - .enable_read (enable), - .write_address (dmem_write_address), - .enable_write (`TRUE), - .write_enable (way_mem_we[i]), - .write_data (refill_data), - // ----- Outputs ------- - .read_data (way_data[i]) - ); - - lm32_ram - #( - // ----- Parameters ------- - .data_width (`LM32_IC_TAGS_WIDTH), - .address_width (`LM32_IC_TMEM_ADDR_WIDTH) +) + way_0_data_ram + ( + // ----- Inputs ------- + .read_clk (clk_i), + .write_clk (clk_i), + .reset (rst_i), + .read_address (dmem_read_address), + .enable_read (enable), + .write_address (dmem_write_address), + .enable_write (`TRUE), + .write_enable (way_mem_we[i]), + .write_data (refill_data), + // ----- Outputs ------- + .read_data (way_data[i]) + ); + + lm32_ram + #( + // ----- Parameters ------- + .data_width (`LM32_IC_TAGS_WIDTH), + .address_width (`LM32_IC_TMEM_ADDR_WIDTH) // Modified for Milkymist: removed non-portable RAM parameters - ) - way_0_tag_ram - ( - // ----- Inputs ------- - .read_clk (clk_i), - .write_clk (clk_i), - .reset (rst_i), - .read_address (tmem_read_address), - .enable_read (enable), - .write_address (tmem_write_address), - .enable_write (`TRUE), - .write_enable (way_mem_we[i] | flushing), - .write_data (tmem_write_data), - // ----- Outputs ------- - .read_data ({way_tag[i], way_valid[i]}) - ); - - end + ) + way_0_tag_ram + ( + // ----- Inputs ------- + .read_clk (clk_i), + .write_clk (clk_i), + .reset (rst_i), + .read_address (tmem_read_address), + .enable_read (enable), + .write_address (tmem_write_address), + .enable_write (`TRUE), + .write_enable (way_mem_we[i] | flushing), + .write_data (tmem_write_data), + // ----- Outputs ------- + .read_data ({way_tag[i], way_valid[i]}) + ); + + end endgenerate ///////////////////////////////////////////////////// @@ -274,37 +274,37 @@ assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TA end endgenerate -// Select data from way that matched the address being read +// Select data from way that matched the address being read generate if (associativity == 1) begin : inst_1 assign inst = way_match[0] ? way_data[0] : 32'b0; end else if (associativity == 2) - begin : inst_2 + begin : inst_2 assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0); end endgenerate // Compute address to use to index into the data memories -generate +generate if (bytes_per_line > 4) assign dmem_write_address = {refill_address[`LM32_IC_ADDR_SET_RNG], refill_offset}; else assign dmem_write_address = refill_address[`LM32_IC_ADDR_SET_RNG]; endgenerate - + assign dmem_read_address = address_a[`LM32_IC_ADDR_IDX_RNG]; -// Compute address to use to index into the tag memories +// Compute address to use to index into the tag memories assign tmem_read_address = address_a[`LM32_IC_ADDR_SET_RNG]; -assign tmem_write_address = flushing +assign tmem_write_address = flushing ? flush_set : refill_address[`LM32_IC_ADDR_SET_RNG]; // Compute signal to indicate when we are on the last refill accesses -generate - if (bytes_per_line > 4) +generate + if (bytes_per_line > 4) assign last_refill = refill_offset == {addr_offset_width{1'b1}}; else assign last_refill = `TRUE; @@ -315,8 +315,8 @@ assign enable = (stall_a == `FALSE); // Compute data and tag memory write enables generate - if (associativity == 1) - begin : we_1 + if (associativity == 1) + begin : we_1 assign way_mem_we[0] = (refill_ready == `TRUE); end else @@ -324,7 +324,7 @@ assign way_mem_we[0] = (refill_ready == `TRUE); assign way_mem_we[0] = (refill_ready == `TRUE) && (refill_way_select[0] == `TRUE); assign way_mem_we[1] = (refill_ready == `TRUE) && (refill_way_select[1] == `TRUE); end -endgenerate +endgenerate // On the last refill cycle set the valid bit, for all other writes it should be cleared assign tmem_write_data[`LM32_IC_TAGS_VALID_RNG] = last_refill & !flushing; @@ -338,21 +338,21 @@ assign refill = state[3]; assign miss = (~(|way_match)) && (read_enable_f == `TRUE) && (stall_f == `FALSE) && !(valid_d && branch_predict_taken_d); assign stall_request = (check == `FALSE); assign refill_request = (refill == `TRUE); - + ///////////////////////////////////////////////////// // Sequential logic ///////////////////////////////////////////////////// // Record way selected for replacement on a cache miss generate - if (associativity >= 2) - begin : way_select + if (associativity >= 2) + begin : way_select always @(posedge clk_i `CFG_RESET_SENSITIVITY) begin if (rst_i == `TRUE) refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; else - begin + begin if (miss == `TRUE) refill_way_select <= {refill_way_select[0], refill_way_select[1]}; end @@ -379,13 +379,13 @@ begin refill_address <= {`LM32_PC_WIDTH{1'bx}}; restart_request <= `FALSE; end - else + else begin case (state) // Flush the cache for the first time after reset `LM32_IC_STATE_FLUSH_INIT: - begin + begin if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}}) state <= `LM32_IC_STATE_CHECK; flush_set <= flush_set - 1'b1; @@ -393,21 +393,21 @@ begin // Flush the cache in response to an write to the ICC CSR `LM32_IC_STATE_FLUSH: - begin + begin if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}}) `ifdef CFG_IROM_ENABLED - if (select_f) + if (select_f) state <= `LM32_IC_STATE_REFILL; - else + else `endif - state <= `LM32_IC_STATE_CHECK; - + state <= `LM32_IC_STATE_CHECK; + flush_set <= flush_set - 1'b1; end - + // Check for cache misses `LM32_IC_STATE_CHECK: - begin + begin if (stall_a == `FALSE) restart_request <= `FALSE; if (iflush == `TRUE) @@ -424,7 +424,7 @@ begin // Refill a cache line `LM32_IC_STATE_REFILL: - begin + begin if (refill_ready == `TRUE) begin if (last_refill == `TRUE) @@ -435,11 +435,11 @@ begin end end - endcase + endcase end end -generate +generate if (bytes_per_line > 4) begin // Refill offset @@ -447,13 +447,13 @@ always @(posedge clk_i `CFG_RESET_SENSITIVITY) begin if (rst_i == `TRUE) refill_offset <= {addr_offset_width{1'b0}}; - else + else begin case (state) - + // Check for cache misses `LM32_IC_STATE_CHECK: - begin + begin if (iflush == `TRUE) refill_offset <= {addr_offset_width{1'b0}}; else if (miss == `TRUE) @@ -462,17 +462,17 @@ begin // Refill a cache line `LM32_IC_STATE_REFILL: - begin + begin if (refill_ready == `TRUE) refill_offset <= refill_offset + 1'b1; end - endcase + endcase end end end endgenerate - + endmodule `endif diff --git a/rtl/lm32_instruction_unit.v b/rtl/lm32_instruction_unit.v index 2f5112d..fbb3b43 100644 --- a/rtl/lm32_instruction_unit.v +++ b/rtl/lm32_instruction_unit.v @@ -2,7 +2,7 @@ // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< // ------------------------------------------------------------------ // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED +// ALL RIGHTS RESERVED // ------------------------------------------------------------------ // // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. @@ -11,7 +11,7 @@ // // Lattice Semiconductor grants permission to use this code // pursuant to the terms of the Lattice Semiconductor Corporation -// Open Source License Agreement. +// Open Source License Agreement. // // Disclaimer: // @@ -46,12 +46,12 @@ // Version : 3.1 // : Support for static branch prediction is added. Fetching of // : instructions can also be altered by branches predicted in D -// : stage of pipeline, and mispredicted branches in the X and M +// : stage of pipeline, and mispredicted branches in the X and M // : stages of the pipeline. // Version : 3.2 // : EBRs use SYNC resets instead of ASYNC resets. // Version : 3.3 -// : Support for a non-cacheable Instruction Memory that has a +// : Support for a non-cacheable Instruction Memory that has a // : single-cycle access latency. This memory can be accessed by // : data port of LM32 (so that debugger has access to it). // Version : 3.4 @@ -60,11 +60,11 @@ // : Bug fix: Inline memory is correctly generated if it is not a // : power-of-two. // : Bug fix: Fixed a bug that caused LM32 (configured without -// : instruction cache) to lock up in to an infinite loop due to a +// : instruction cache) to lock up in to an infinite loop due to a // : instruction bus error when EBA was set to instruction inline // : memory. -// Version : 3.8 -// : Feature: Support for dynamically switching EBA to DEBA via a +// Version : 3.8 +// : Feature: Support for dynamically switching EBA to DEBA via a // : GPIO. // ============================================================================= @@ -79,9 +79,9 @@ module lm32_instruction_unit ( clk_i, rst_i, `ifdef CFG_DEBUG_ENABLED - `ifdef CFG_ALTERNATE_EBA +`ifdef CFG_ALTERNATE_EBA at_debug, - `endif +`endif `endif // From pipeline stall_a, @@ -94,7 +94,7 @@ module lm32_instruction_unit ( kill_f, branch_predict_taken_d, branch_predict_address_d, -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH branch_taken_x, branch_target_x, `endif @@ -109,7 +109,7 @@ module lm32_instruction_unit ( dcache_restart_request, dcache_refill_request, dcache_refilling, -`endif +`endif `ifdef CFG_IROM_ENABLED irom_store_data_m, irom_address_xm, @@ -164,7 +164,7 @@ module lm32_instruction_unit ( `endif `ifdef CFG_EBR_POSEDGE_REGISTER_FILE instruction_f, -`endif +`endif instruction_d ); @@ -178,7 +178,7 @@ parameter bytes_per_line = 16; // Number of bytes per c parameter base_address = 0; // Base address of cachable memory parameter limit = 0; // Limit (highest address) of cachable memory -// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used +// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used localparam addr_offset_width = bytes_per_line == 4 ? 1 : `CLOG2(bytes_per_line)-2; localparam addr_offset_lsb = 2; localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); @@ -191,9 +191,9 @@ input clk_i; // Clock input rst_i; // Reset `ifdef CFG_DEBUG_ENABLED - `ifdef CFG_ALTERNATE_EBA - input at_debug; // GPIO input that maps EBA to DEBA - `endif +`ifdef CFG_ALTERNATE_EBA +input at_debug; // GPIO input that maps EBA to DEBA +`endif `endif input stall_a; // Stall A stage instruction @@ -207,8 +207,8 @@ input kill_f; // Kill instruction in F input branch_predict_taken_d; // Branch is predicted taken in D stage input [`LM32_PC_RNG] branch_predict_address_d; // Branch target address - -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH + +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH input branch_taken_x; // Branch instruction in X stage is taken input [`LM32_PC_RNG] branch_target_x; // Target PC of X stage branch instruction `endif @@ -224,7 +224,7 @@ input iflush; // Flush instruction cac input dcache_restart_request; // Restart instruction that caused a data cache miss input dcache_refill_request; // Request to refill data cache input dcache_refilling; -`endif +`endif `ifdef CFG_IROM_ENABLED input [`LM32_WORD_RNG] irom_store_data_m; // Data from load-store unit @@ -248,7 +248,7 @@ input [`LM32_WORD_RNG] jtag_address; // JTAG read/write addre ///////////////////////////////////////////////////// // Outputs ///////////////////////////////////////////////////// - + output [`LM32_PC_RNG] pc_f; // F stage PC reg [`LM32_PC_RNG] pc_f; output [`LM32_PC_RNG] pc_d; // D stage PC @@ -273,8 +273,8 @@ wire icache_refilling; `ifdef CFG_IROM_ENABLED output [`LM32_WORD_RNG] irom_data_m; // Data to load-store unit on load -wire [`LM32_WORD_RNG] irom_data_m; -`endif +wire [`LM32_WORD_RNG] irom_data_m; +`endif `ifdef CFG_IWB_ENABLED output [`LM32_WORD_RNG] i_dat_o; // Instruction Wishbone interface write data @@ -286,7 +286,7 @@ wire [`LM32_WORD_RNG] i_dat_o; output [`LM32_WORD_RNG] i_adr_o; // Instruction Wishbone interface address reg [`LM32_WORD_RNG] i_adr_o; output i_cyc_o; // Instruction Wishbone interface cycle -reg i_cyc_o; +reg i_cyc_o; output [`LM32_BYTE_SELECT_RNG] i_sel_o; // Instruction Wishbone interface byte select `ifdef CFG_HW_DEBUG_ENABLED reg [`LM32_BYTE_SELECT_RNG] i_sel_o; @@ -301,11 +301,11 @@ reg i_we_o; `else wire i_we_o; `endif -output [`LM32_CTYPE_RNG] i_cti_o; // Instruction Wishbone interface cycle type +output [`LM32_CTYPE_RNG] i_cti_o; // Instruction Wishbone interface cycle type reg [`LM32_CTYPE_RNG] i_cti_o; output i_lock_o; // Instruction Wishbone interface lock bus reg i_lock_o; -output [`LM32_BTYPE_RNG] i_bte_o; // Instruction Wishbone interface burst type +output [`LM32_BTYPE_RNG] i_bte_o; // Instruction Wishbone interface burst type wire [`LM32_BTYPE_RNG] i_bte_o; `endif @@ -328,13 +328,13 @@ output [`LM32_INSTRUCTION_RNG] instruction_d; // D stage instruction t reg [`LM32_INSTRUCTION_RNG] instruction_d; ///////////////////////////////////////////////////// -// Internal nets and registers +// Internal nets and registers ///////////////////////////////////////////////////// reg [`LM32_PC_RNG] pc_a; // A stage PC `ifdef LM32_CACHE_ENABLED -reg [`LM32_PC_RNG] restart_address; // Address to restart from after a cache miss +reg [`LM32_PC_RNG] restart_address; // Address to restart from after a cache miss `endif `ifdef CFG_ICACHE_ENABLED @@ -382,26 +382,26 @@ reg alternate_eba_taken; ///////////////////////////////////////////////////// // Instruction ROM -`ifdef CFG_IROM_ENABLED - pmi_ram_dp_true +`ifdef CFG_IROM_ENABLED + pmi_ram_dp_true #( // ----- Parameters ------- .pmi_family (`LATTICE_FAMILY), - + //.pmi_addr_depth_a (1 << `CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)), //.pmi_addr_width_a (`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)), //.pmi_data_width_a (`LM32_WORD_WIDTH), //.pmi_addr_depth_b (1 << `CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)), //.pmi_addr_width_b (`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)), //.pmi_data_width_b (`LM32_WORD_WIDTH), - + .pmi_addr_depth_a (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1), .pmi_addr_width_a (`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)), .pmi_data_width_a (`LM32_WORD_WIDTH), .pmi_addr_depth_b (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1), .pmi_addr_width_b (`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)), .pmi_data_width_b (`LM32_WORD_WIDTH), - + .pmi_regmode_a ("noreg"), .pmi_regmode_b ("noreg"), .pmi_gsr ("enable"), @@ -409,27 +409,27 @@ reg alternate_eba_taken; .pmi_init_file (`CFG_IROM_INIT_FILE), .pmi_init_file_format (`CFG_IROM_INIT_FILE_FORMAT), .module_type ("pmi_ram_dp_true") - ) + ) ram ( - // ----- Inputs ------- - .ClockA (clk_i), - .ClockB (clk_i), - .ResetA (rst_i), - .ResetB (rst_i), - .DataInA ({32{1'b0}}), - .DataInB (irom_store_data_m), - .AddressA (pc_a[`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]), - .AddressB (irom_address_xm[`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]), - .ClockEnA (!stall_a), - .ClockEnB (!stall_x || !stall_m), - .WrA (`FALSE), - .WrB (irom_we_xm), - // ----- Outputs ------- - .QA (irom_data_f), - .QB (irom_data_m) - ); -`endif - + // ----- Inputs ------- + .ClockA (clk_i), + .ClockB (clk_i), + .ResetA (rst_i), + .ResetB (rst_i), + .DataInA ({32{1'b0}}), + .DataInB (irom_store_data_m), + .AddressA (pc_a[`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]), + .AddressB (irom_address_xm[`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]), + .ClockEnA (!stall_a), + .ClockEnB (!stall_x || !stall_m), + .WrA (`FALSE), + .WrB (irom_we_xm), + // ----- Outputs ------- + .QA (irom_data_f), + .QB (irom_data_m) + ); +`endif + `ifdef CFG_ICACHE_ENABLED // Instruction cache lm32_icache #( @@ -438,10 +438,10 @@ lm32_icache #( .bytes_per_line (bytes_per_line), .base_address (base_address), .limit (limit) - ) icache ( + ) icache ( // ----- Inputs ----- .clk_i (clk_i), - .rst_i (rst_i), + .rst_i (rst_i), .stall_a (stall_a), .stall_f (stall_f), .branch_predict_taken_d (branch_predict_taken_d), @@ -472,10 +472,10 @@ assign icache_read_enable_f = (valid_f == `TRUE) && (kill_f == `FALSE) `ifdef CFG_DCACHE_ENABLED && (dcache_restart_request == `FALSE) -`endif -`ifdef CFG_IROM_ENABLED +`endif +`ifdef CFG_IROM_ENABLED && (irom_select_f == `FALSE) -`endif +`endif ; `endif @@ -486,26 +486,26 @@ begin `ifdef CFG_DCACHE_ENABLED if (dcache_restart_request == `TRUE) pc_a = restart_address; - else -`endif + else +`endif if (branch_taken_m == `TRUE) - if ((branch_mispredict_taken_m == `TRUE) && (exception_m == `FALSE)) - pc_a = pc_x; - else + if ((branch_mispredict_taken_m == `TRUE) && (exception_m == `FALSE)) + pc_a = pc_x; + else pc_a = branch_target_m; -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH else if (branch_taken_x == `TRUE) pc_a = branch_target_x; `endif else - if ( (valid_d == `TRUE) && (branch_predict_taken_d == `TRUE) ) - pc_a = branch_predict_address_d; - else + if ( (valid_d == `TRUE) && (branch_predict_taken_d == `TRUE) ) + pc_a = branch_predict_address_d; + else `ifdef CFG_ICACHE_ENABLED if (icache_restart_request == `TRUE) pc_a = restart_address; - else -`endif + else +`endif pc_a = pc_f + 1'b1; end @@ -513,7 +513,7 @@ end `ifdef CFG_IROM_ENABLED assign irom_select_a = ({pc_a, 2'b00} >= `CFG_IROM_BASE_ADDRESS) && ({pc_a, 2'b00} <= `CFG_IROM_LIMIT); `endif - + // Select instruction from selected source `ifdef CFG_ICACHE_ENABLED `ifdef CFG_IROM_ENABLED @@ -545,7 +545,7 @@ assign i_bte_o = `LM32_BTYPE_LINEAR; `endif `ifdef CFG_ICACHE_ENABLED -// Determine parameters for next cache refill Wishbone access +// Determine parameters for next cache refill Wishbone access generate case (bytes_per_line) 4: @@ -572,25 +572,25 @@ assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb endcase endgenerate `endif - + ///////////////////////////////////////////////////// // Sequential Logic ///////////////////////////////////////////////////// -// PC +// PC always @(posedge clk_i `CFG_RESET_SENSITIVITY) begin if (rst_i == `TRUE) begin `ifdef CFG_DEBUG_ENABLED - `ifdef CFG_ALTERNATE_EBA +`ifdef CFG_ALTERNATE_EBA if (at_debug == `TRUE) pc_f <= (`CFG_DEBA_RESET-4)/4; else pc_f <= (`CFG_EBA_RESET-4)/4; - `else +`else pc_f <= (`CFG_EBA_RESET-4)/4; - `endif +`endif `else pc_f <= (`CFG_EBA_RESET-4)/4; `endif @@ -622,7 +622,7 @@ begin else begin `ifdef CFG_DCACHE_ENABLED -`ifdef CFG_ICACHE_ENABLED +`ifdef CFG_ICACHE_ENABLED // D-cache restart address must take priority, otherwise instructions will be lost if (dcache_refill_request == `TRUE) restart_address <= pc_w; @@ -633,7 +633,7 @@ begin restart_address <= pc_w; `endif `else -`ifdef CFG_ICACHE_ENABLED +`ifdef CFG_ICACHE_ENABLED if (icache_refill_request == `TRUE) restart_address <= icache_refill_address; `endif @@ -665,13 +665,13 @@ begin 2'b01: jtag_read_data = i_dat_i[`LM32_BYTE_2_RNG]; 2'b10: jtag_read_data = i_dat_i[`LM32_BYTE_1_RNG]; 2'b11: jtag_read_data = i_dat_i[`LM32_BYTE_0_RNG]; - endcase + endcase end `endif `ifdef CFG_IWB_ENABLED // Instruction Wishbone interface -`ifdef CFG_ICACHE_ENABLED +`ifdef CFG_ICACHE_ENABLED always @(posedge clk_i `CFG_RESET_SENSITIVITY) begin if (rst_i == `TRUE) @@ -693,7 +693,7 @@ begin `endif end else - begin + begin icache_refill_ready <= `FALSE; // Is a cycle in progress? if (i_cyc_o == `TRUE) @@ -705,16 +705,16 @@ begin if (jtag_access == `TRUE) begin i_cyc_o <= `FALSE; - i_stb_o <= `FALSE; - i_we_o <= `FALSE; - jtag_access <= `FALSE; + i_stb_o <= `FALSE; + i_we_o <= `FALSE; + jtag_access <= `FALSE; end else `endif begin if (last_word == `TRUE) begin - // Cache line fill complete + // Cache line fill complete i_cyc_o <= `FALSE; i_stb_o <= `FALSE; i_lock_o <= `FALSE; @@ -740,12 +740,12 @@ begin if ((icache_refill_request == `TRUE) && (icache_refill_ready == `FALSE)) begin // Read first word of cache line -`ifdef CFG_HW_DEBUG_ENABLED +`ifdef CFG_HW_DEBUG_ENABLED i_sel_o <= 4'b1111; `endif i_adr_o <= {first_address, 2'b00}; i_cyc_o <= `TRUE; - i_stb_o <= `TRUE; + i_stb_o <= `TRUE; i_cti_o <= first_cycle_type; //i_lock_o <= `TRUE; `ifdef CFG_BUS_ERRORS_ENABLED @@ -771,12 +771,12 @@ begin i_cti_o <= `LM32_CTYPE_END; jtag_access <= `TRUE; end - end -`endif + end +`endif `ifdef CFG_BUS_ERRORS_ENABLED - // Clear bus error when exception taken, otherwise they would be + // Clear bus error when exception taken, otherwise they would be // continually generated if exception handler is cached -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH if (branch_taken_x == `TRUE) bus_error_f <= `FALSE; `endif @@ -802,7 +802,7 @@ begin `endif end else - begin + begin // Is a cycle in progress? if (i_cyc_o == `TRUE) begin @@ -825,15 +825,15 @@ begin end else begin - // Wait for an instruction fetch from an external address - if ( (stall_a == `FALSE) -`ifdef CFG_IROM_ENABLED + // Wait for an instruction fetch from an external address + if ( (stall_a == `FALSE) +`ifdef CFG_IROM_ENABLED && (irom_select_a == `FALSE) -`endif +`endif ) begin // Fetch instruction -`ifdef CFG_HW_DEBUG_ENABLED +`ifdef CFG_HW_DEBUG_ENABLED i_sel_o <= 4'b1111; `endif i_adr_o <= {pc_a, 2'b00}; @@ -843,19 +843,19 @@ begin bus_error_f <= `FALSE; `endif end - else - begin - if ( (stall_a == `FALSE) -`ifdef CFG_IROM_ENABLED - && (irom_select_a == `TRUE) -`endif - ) - begin + else + begin + if ( (stall_a == `FALSE) +`ifdef CFG_IROM_ENABLED + && (irom_select_a == `TRUE) +`endif + ) + begin `ifdef CFG_BUS_ERRORS_ENABLED - bus_error_f <= `FALSE; + bus_error_f <= `FALSE; `endif - end - end + end + end end end end @@ -882,6 +882,6 @@ begin `endif end end -end - +end + endmodule diff --git a/rtl/lm32_interrupt.v b/rtl/lm32_interrupt.v index 41f9a14..d2e1e9f 100644 --- a/rtl/lm32_interrupt.v +++ b/rtl/lm32_interrupt.v @@ -2,7 +2,7 @@ // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< // ------------------------------------------------------------------ // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED +// ALL RIGHTS RESERVED // ------------------------------------------------------------------ // // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. @@ -11,7 +11,7 @@ // // Lattice Semiconductor grants permission to use this code // pursuant to the terms of the Lattice Semiconductor Corporation -// Open Source License Agreement. +// Open Source License Agreement. // // Disclaimer: // @@ -55,7 +55,7 @@ module lm32_interrupt ( // ----- Inputs ------- - clk_i, + clk_i, rst_i, // From external devices interrupt, @@ -103,9 +103,9 @@ input debug_exception; // Debug-related exception has b `else input exception; // Exception has been raised `endif -input eret_q_x; // Return from exception +input eret_q_x; // Return from exception `ifdef CFG_DEBUG_ENABLED -input bret_q_x; // Return from breakpoint +input bret_q_x; // Return from breakpoint `endif input [`LM32_CSR_RNG] csr; // CSR read/write index @@ -123,7 +123,7 @@ output [`LM32_WORD_RNG] csr_read_data; // Data read from CSR reg [`LM32_WORD_RNG] csr_read_data; ///////////////////////////////////////////////////// -// Internal nets and registers +// Internal nets and registers ///////////////////////////////////////////////////// wire [interrupts-1:0] asserted; // Which interrupts are currently being asserted @@ -152,32 +152,32 @@ assign interrupt_exception = (|interrupt_n_exception) & ie; // Determine which interrupts are currently being asserted (active-low) or are already pending assign asserted = ip | interrupt; - -assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, + +assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, `ifdef CFG_DEBUG_ENABLED bie, `else 1'b0, -`endif - eie, +`endif + eie, ie }; assign ip_csr_read_data = ip; assign im_csr_read_data = im; generate - if (interrupts > 1) + if (interrupts > 1) begin // CSR read always @(*) begin case (csr) - `LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, + `LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, `ifdef CFG_DEBUG_ENABLED bie, `else - 1'b0, + 1'b0, `endif - eie, + eie, ie }; `LM32_CSR_IP: csr_read_data = ip; @@ -192,13 +192,13 @@ end always @(*) begin case (csr) - `LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, + `LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, `ifdef CFG_DEBUG_ENABLED - bie, + bie, `else - 1'b0, + 1'b0, `endif - eie, + eie, ie }; `LM32_CSR_IP: csr_read_data = ip; @@ -207,7 +207,7 @@ begin end end endgenerate - + ///////////////////////////////////////////////////// // Sequential Logic ///////////////////////////////////////////////////// @@ -257,7 +257,7 @@ begin begin if (eret_q_x == `TRUE) // Restore interrupt enable - ie <= eie; + ie <= eie; `ifdef CFG_DEBUG_ENABLED else if (bret_q_x == `TRUE) // Restore interrupt enable @@ -326,7 +326,7 @@ begin begin if (eret_q_x == `TRUE) // Restore interrupt enable - ie <= eie; + ie <= eie; `ifdef CFG_DEBUG_ENABLED else if (bret_q_x == `TRUE) // Restore interrupt enable diff --git a/rtl/lm32_jtag.v b/rtl/lm32_jtag.v index 1904ccb..95975ac 100644 --- a/rtl/lm32_jtag.v +++ b/rtl/lm32_jtag.v @@ -2,7 +2,7 @@ // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< // ------------------------------------------------------------------ // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED +// ALL RIGHTS RESERVED // ------------------------------------------------------------------ // // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. @@ -11,7 +11,7 @@ // // Lattice Semiconductor grants permission to use this code // pursuant to the terms of the Lattice Semiconductor Corporation -// Open Source License Agreement. +// Open Source License Agreement. // // Disclaimer: // @@ -85,7 +85,7 @@ module lm32_jtag ( // ----- Inputs ------- clk_i, rst_i, - jtag_clk, + jtag_clk, jtag_update, jtag_reg_q, jtag_reg_addr_q, @@ -153,7 +153,7 @@ input exception_q_w; // Indicates an exceptio ///////////////////////////////////////////////////// // Outputs ///////////////////////////////////////////////////// - + `ifdef CFG_JTAG_UART_ENABLED output [`LM32_WORD_RNG] jtx_csr_read_data; // Value of JTX CSR for rcsr instructions wire [`LM32_WORD_RNG] jtx_csr_read_data; @@ -172,7 +172,7 @@ reg jtag_read_enable; output jtag_write_enable; // Memory write enable reg jtag_write_enable; output [`LM32_BYTE_RNG] jtag_write_data; // Data to write to specified address -wire [`LM32_BYTE_RNG] jtag_write_data; +wire [`LM32_BYTE_RNG] jtag_write_data; output [`LM32_WORD_RNG] jtag_address; // Memory read/write address wire [`LM32_WORD_RNG] jtag_address; `endif @@ -186,9 +186,9 @@ output [`LM32_BYTE_RNG] jtag_reg_d; reg [`LM32_BYTE_RNG] jtag_reg_d; output [2:0] jtag_reg_addr_d; wire [2:0] jtag_reg_addr_d; - + ///////////////////////////////////////////////////// -// Internal nets and registers +// Internal nets and registers ///////////////////////////////////////////////////// reg rx_toggle; // Clock-domain crossing registers @@ -196,10 +196,10 @@ reg rx_toggle_r; // Registered version of rx_toggle reg rx_toggle_r_r; // Registered version of rx_toggle_r reg rx_toggle_r_r_r; // Registered version of rx_toggle_r_r -reg [`LM32_BYTE_RNG] rx_byte; +reg [`LM32_BYTE_RNG] rx_byte; reg [2:0] rx_addr; -`ifdef CFG_JTAG_UART_ENABLED +`ifdef CFG_JTAG_UART_ENABLED reg [`LM32_BYTE_RNG] uart_tx_byte; // UART TX data reg uart_tx_valid; // TX data is valid reg [`LM32_BYTE_RNG] uart_rx_byte; // UART RX data @@ -228,10 +228,10 @@ assign jtag_csr = jtag_byte_4[`LM32_CSR_RNG]; assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3}; assign jtag_write_data = jtag_byte_4; `endif - -// Generate status flags for reading via the JTAG interface -`ifdef CFG_JTAG_UART_ENABLED -assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid}; + +// Generate status flags for reading via the JTAG interface +`ifdef CFG_JTAG_UART_ENABLED +assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid}; `else assign jtag_reg_addr_d[1:0] = 2'b00; `endif @@ -241,22 +241,22 @@ assign jtag_reg_addr_d[2] = processing; assign jtag_reg_addr_d[2] = 1'b0; `endif -`ifdef CFG_JTAG_UART_ENABLED +`ifdef CFG_JTAG_UART_ENABLED assign jtx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_tx_valid, 8'h00}; assign jrx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_rx_valid, uart_rx_byte}; -`endif - +`endif + ///////////////////////////////////////////////////// // Sequential Logic ///////////////////////////////////////////////////// // Toggle a flag when a JTAG write occurs - + always @(negedge jtag_update `CFG_RESET_SENSITIVITY) begin if (rst_i == `TRUE) rx_toggle <= 1'b0; -else +else rx_toggle <= ~rx_toggle; end @@ -301,7 +301,7 @@ begin jtag_break <= `FALSE; jtag_reset <= `FALSE; `endif -`ifdef CFG_JTAG_UART_ENABLED +`ifdef CFG_JTAG_UART_ENABLED uart_tx_byte <= 8'h00; uart_tx_valid <= `FALSE; uart_rx_byte <= 8'h00; @@ -310,7 +310,7 @@ begin end else begin -`ifdef CFG_JTAG_UART_ENABLED +`ifdef CFG_JTAG_UART_ENABLED if ((csr_write_enable == `TRUE) && (stall_x == `FALSE)) begin case (csr) @@ -342,7 +342,7 @@ begin // Wait for rx register to toggle which indicates new data is available if (rx_toggle_r_r != rx_toggle_r_r_r) begin - command <= rx_byte[7:4]; + command <= rx_byte[7:4]; case (rx_addr) `ifdef CFG_DEBUG_ENABLED `LM32_DP: @@ -365,32 +365,32 @@ begin end `LM32_DP_WRITE_CSR: state <= `LM32_JTAG_STATE_READ_BYTE_0; -`endif +`endif `LM32_DP_BREAK: begin -`ifdef CFG_JTAG_UART_ENABLED - uart_rx_valid <= `FALSE; - uart_tx_valid <= `FALSE; +`ifdef CFG_JTAG_UART_ENABLED + uart_rx_valid <= `FALSE; + uart_tx_valid <= `FALSE; `endif jtag_break <= `TRUE; end `LM32_DP_RESET: begin -`ifdef CFG_JTAG_UART_ENABLED - uart_rx_valid <= `FALSE; - uart_tx_valid <= `FALSE; +`ifdef CFG_JTAG_UART_ENABLED + uart_rx_valid <= `FALSE; + uart_tx_valid <= `FALSE; `endif jtag_reset <= `TRUE; end - endcase + endcase end `endif -`ifdef CFG_JTAG_UART_ENABLED +`ifdef CFG_JTAG_UART_ENABLED `LM32_TX: begin uart_rx_byte <= rx_byte; uart_rx_valid <= `TRUE; - end + end `LM32_RX: begin jtag_reg_d <= uart_tx_byte; @@ -399,7 +399,7 @@ begin `endif default: ; - endcase + endcase end end `ifdef CFG_HW_DEBUG_ENABLED @@ -434,7 +434,7 @@ begin jtag_byte_3 <= rx_byte; if (command == `LM32_DP_READ_MEMORY) state <= `LM32_JTAG_STATE_PROCESS_COMMAND; - else + else state <= `LM32_JTAG_STATE_READ_BYTE_4; end end @@ -474,25 +474,25 @@ begin `LM32_JTAG_STATE_WAIT_FOR_MEMORY: begin if (jtag_access_complete == `TRUE) - begin + begin jtag_read_enable <= `FALSE; jtag_reg_d <= jtag_read_data; - jtag_write_enable <= `FALSE; + jtag_write_enable <= `FALSE; processing <= `FALSE; state <= `LM32_JTAG_STATE_READ_COMMAND; end - end + end `LM32_JTAG_STATE_WAIT_FOR_CSR: begin jtag_csr_write_enable <= `FALSE; processing <= `FALSE; state <= `LM32_JTAG_STATE_READ_COMMAND; - end + end `endif endcase end end - + endmodule `endif diff --git a/rtl/lm32_load_store_unit.v b/rtl/lm32_load_store_unit.v index fcf9bc3..1e249c4 100644 --- a/rtl/lm32_load_store_unit.v +++ b/rtl/lm32_load_store_unit.v @@ -2,7 +2,7 @@ // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< // ------------------------------------------------------------------ // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED +// ALL RIGHTS RESERVED // ------------------------------------------------------------------ // // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. @@ -11,7 +11,7 @@ // // Lattice Semiconductor grants permission to use this code // pursuant to the terms of the Lattice Semiconductor Corporation -// Open Source License Agreement. +// Open Source License Agreement. // // Disclaimer: // @@ -44,14 +44,14 @@ // Version : 7.0SP2, 3.0 // : No Change // Version : 3.1 -// : Instead of disallowing an instruction cache miss on a data cache -// : miss, both can now occur at the same time. If both occur at same -// : time, then restart address is the address of instruction that +// : Instead of disallowing an instruction cache miss on a data cache +// : miss, both can now occur at the same time. If both occur at same +// : time, then restart address is the address of instruction that // : caused data cache miss. // Version : 3.2 // : EBRs use SYNC resets instead of ASYNC resets. // Version : 3.3 -// : Support for new non-cacheable Data Memory that is accessible by +// : Support for new non-cacheable Data Memory that is accessible by // : the data port and has a one cycle access latency. // Version : 3.4 // : No change @@ -74,7 +74,6 @@ module lm32_load_store_unit ( stall_a, stall_x, stall_m, - kill_x, kill_m, exception_m, store_operand_x, @@ -107,13 +106,13 @@ module lm32_load_store_unit ( dcache_restart_request, dcache_stall_request, dcache_refilling, -`endif +`endif `ifdef CFG_IROM_ENABLED irom_store_data_m, irom_address_xm, irom_we_xm, irom_stall_request_x, -`endif +`endif load_data_w, stall_wb_load, // To Wishbone @@ -138,7 +137,7 @@ parameter bytes_per_line = 16; // Number of bytes per c parameter base_address = 0; // Base address of cachable memory parameter limit = 0; // Limit (highest address) of cachable memory -// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used +// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used localparam addr_offset_width = bytes_per_line == 4 ? 1 : `CLOG2(bytes_per_line)-2; localparam addr_offset_lsb = 2; localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); @@ -147,13 +146,12 @@ localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); // Inputs ///////////////////////////////////////////////////// -input clk_i; // Clock +input clk_i; // Clock input rst_i; // Reset -input stall_a; // A stage stall -input stall_x; // X stage stall +input stall_a; // A stage stall +input stall_x; // X stage stall input stall_m; // M stage stall -input kill_x; // Kill instruction in X stage input kill_m; // Kill instruction in M stage input exception_m; // An exception occured in the M stage @@ -174,7 +172,7 @@ input [`LM32_SIZE_RNG] size_x; // Size of load or store input dflush; // Flush the data cache `endif -`ifdef CFG_IROM_ENABLED +`ifdef CFG_IROM_ENABLED input [`LM32_WORD_RNG] irom_data_m; // Data from Instruction-ROM `endif @@ -198,17 +196,17 @@ output dcache_refilling; wire dcache_refilling; `endif -`ifdef CFG_IROM_ENABLED +`ifdef CFG_IROM_ENABLED output irom_store_data_m; // Store data to Instruction ROM wire [`LM32_WORD_RNG] irom_store_data_m; output [`LM32_WORD_RNG] irom_address_xm; // Load/store address to Instruction ROM wire [`LM32_WORD_RNG] irom_address_xm; output irom_we_xm; // Write-enable of 2nd port of Instruction ROM wire irom_we_xm; -output irom_stall_request_x; // Stall instruction in D stage -wire irom_stall_request_x; +output irom_stall_request_x; // Stall instruction in D stage +wire irom_stall_request_x; `endif - + output [`LM32_WORD_RNG] load_data_w; // Result of a load instruction reg [`LM32_WORD_RNG] load_data_w; output stall_wb_load; // Request to stall pipeline due to a load from the Wishbone interface @@ -223,18 +221,18 @@ reg d_cyc_o; output [`LM32_BYTE_SELECT_RNG] d_sel_o; // Data Wishbone interface byte select reg [`LM32_BYTE_SELECT_RNG] d_sel_o; output d_stb_o; // Data Wishbone interface strobe -reg d_stb_o; +reg d_stb_o; output d_we_o; // Data Wishbone interface write enable reg d_we_o; -output [`LM32_CTYPE_RNG] d_cti_o; // Data Wishbone interface cycle type +output [`LM32_CTYPE_RNG] d_cti_o; // Data Wishbone interface cycle type reg [`LM32_CTYPE_RNG] d_cti_o; output d_lock_o; // Date Wishbone interface lock bus reg d_lock_o; -output [`LM32_BTYPE_RNG] d_bte_o; // Data Wishbone interface burst type +output [`LM32_BTYPE_RNG] d_bte_o; // Data Wishbone interface burst type wire [`LM32_BTYPE_RNG] d_bte_o; ///////////////////////////////////////////////////// -// Internal nets and registers +// Internal nets and registers ///////////////////////////////////////////////////// // Microcode pipeline registers - See inputs for description @@ -242,8 +240,8 @@ reg [`LM32_SIZE_RNG] size_m; reg [`LM32_SIZE_RNG] size_w; reg sign_extend_m; reg sign_extend_w; -reg [`LM32_WORD_RNG] store_data_x; -reg [`LM32_WORD_RNG] store_data_m; +reg [`LM32_WORD_RNG] store_data_x; +reg [`LM32_WORD_RNG] store_data_m; reg [`LM32_BYTE_SELECT_RNG] byte_enable_x; reg [`LM32_BYTE_SELECT_RNG] byte_enable_m; wire [`LM32_WORD_RNG] data_m; @@ -288,7 +286,7 @@ reg wb_load_complete; // Indicates when a Wish `ifdef CFG_DRAM_ENABLED // Data RAM - pmi_ram_dp_true + pmi_ram_dp_true #( // ----- Parameters ------- .pmi_family (`LATTICE_FAMILY), @@ -299,7 +297,7 @@ reg wb_load_complete; // Indicates when a Wish //.pmi_addr_depth_b (1 << `CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)), //.pmi_addr_width_b (`CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)), //.pmi_data_width_b (`LM32_WORD_WIDTH), - + .pmi_addr_depth_a (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1), .pmi_addr_width_a (`CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)), .pmi_data_width_a (`LM32_WORD_WIDTH), @@ -314,27 +312,27 @@ reg wb_load_complete; // Indicates when a Wish .pmi_init_file (`CFG_DRAM_INIT_FILE), .pmi_init_file_format (`CFG_DRAM_INIT_FILE_FORMAT), .module_type ("pmi_ram_dp_true") - ) + ) ram ( - // ----- Inputs ------- - .ClockA (clk_i), - .ClockB (clk_i), - .ResetA (rst_i), - .ResetB (rst_i), - .DataInA ({32{1'b0}}), - .DataInB (dram_store_data_m), - .AddressA (load_store_address_x[`CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]), - .AddressB (load_store_address_m[`CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]), - // .ClockEnA (!stall_x & (load_x | store_x)), - .ClockEnA (!stall_x), - .ClockEnB (!stall_m), - .WrA (`FALSE), - .WrB (store_q_m & dram_select_m), - // ----- Outputs ------- - .QA (dram_data_out), - .QB () - ); - + // ----- Inputs ------- + .ClockA (clk_i), + .ClockB (clk_i), + .ResetA (rst_i), + .ResetB (rst_i), + .DataInA ({32{1'b0}}), + .DataInB (dram_store_data_m), + .AddressA (load_store_address_x[`CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]), + .AddressB (load_store_address_m[`CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]), + // .ClockEnA (!stall_x & (load_x | store_x)), + .ClockEnA (!stall_x), + .ClockEnB (!stall_m), + .WrA (`FALSE), + .WrB (store_q_m & dram_select_m), + // ----- Outputs ------- + .QA (dram_data_out), + .QB () + ); + /*---------------------------------------------------------------------- EBRs cannot perform reads from location 'written to' on the same clock edge. Therefore bypass logic is required to latch the store'd value @@ -343,30 +341,30 @@ reg wb_load_complete; // Indicates when a Wish always @(posedge clk_i `CFG_RESET_SENSITIVITY) if (rst_i == `TRUE) begin - dram_bypass_en <= `FALSE; - dram_bypass_data <= 0; + dram_bypass_en <= `FALSE; + dram_bypass_data <= 0; end else begin - if (stall_x == `FALSE) - dram_bypass_data <= dram_store_data_m; - - if ( (stall_m == `FALSE) + if (stall_x == `FALSE) + dram_bypass_data <= dram_store_data_m; + + if ( (stall_m == `FALSE) && (stall_x == `FALSE) - && (store_q_m == `TRUE) - && ( (load_x == `TRUE) - || (store_x == `TRUE) - ) - && (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2]) - ) - dram_bypass_en <= `TRUE; - else - if ( (dram_bypass_en == `TRUE) - && (stall_x == `FALSE) - ) - dram_bypass_en <= `FALSE; + && (store_q_m == `TRUE) + && ( (load_x == `TRUE) + || (store_x == `TRUE) + ) + && (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2]) + ) + dram_bypass_en <= `TRUE; + else + if ( (dram_bypass_en == `TRUE) + && (stall_x == `FALSE) + ) + dram_bypass_en <= `FALSE; end - + assign dram_data_m = dram_bypass_en ? dram_bypass_data : dram_data_out; `endif @@ -378,10 +376,10 @@ lm32_dcache #( .bytes_per_line (bytes_per_line), .base_address (base_address), .limit (limit) - ) dcache ( + ) dcache ( // ----- Inputs ----- .clk_i (clk_i), - .rst_i (rst_i), + .rst_i (rst_i), .stall_a (stall_a), .stall_x (stall_x), .stall_m (stall_m), @@ -410,17 +408,17 @@ lm32_dcache #( // Select where data should be loaded from / stored to `ifdef CFG_DRAM_ENABLED - assign dram_select_x = (load_store_address_x >= `CFG_DRAM_BASE_ADDRESS) + assign dram_select_x = (load_store_address_x >= `CFG_DRAM_BASE_ADDRESS) && (load_store_address_x <= `CFG_DRAM_LIMIT); `endif `ifdef CFG_IROM_ENABLED - assign irom_select_x = (load_store_address_x >= `CFG_IROM_BASE_ADDRESS) + assign irom_select_x = (load_store_address_x >= `CFG_IROM_BASE_ADDRESS) && (load_store_address_x <= `CFG_IROM_LIMIT); `endif - + `ifdef CFG_DCACHE_ENABLED - assign dcache_select_x = (load_store_address_x >= `CFG_DCACHE_BASE_ADDRESS) + assign dcache_select_x = (load_store_address_x >= `CFG_DCACHE_BASE_ADDRESS) && (load_store_address_x <= `CFG_DCACHE_LIMIT) `ifdef CFG_DRAM_ENABLED && (dram_select_x == `FALSE) @@ -430,10 +428,10 @@ lm32_dcache #( `endif ; `endif - + assign wb_select_x = `TRUE `ifdef CFG_DCACHE_ENABLED - && !dcache_select_x + && !dcache_select_x `endif `ifdef CFG_DRAM_ENABLED && !dram_select_x @@ -449,7 +447,7 @@ begin case (size_x) `LM32_SIZE_BYTE: store_data_x = {4{store_operand_x[7:0]}}; `LM32_SIZE_HWORD: store_data_x = {2{store_operand_x[15:0]}}; - `LM32_SIZE_WORD: store_data_x = store_operand_x; + `LM32_SIZE_WORD: store_data_x = store_operand_x; default: store_data_x = {`LM32_WORD_WIDTH{1'bx}}; endcase end @@ -489,54 +487,54 @@ assign irom_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM // Instead of implementing a byte-addressable instruction ROM (for store byte instruction), // a load-and-store architecture is used wherein a 32-bit value is loaded, the requisite // byte is replaced, and the whole 32-bit value is written back - + assign irom_address_xm = ((irom_select_m == `TRUE) && (store_q_m == `TRUE)) - ? load_store_address_m - : load_store_address_x; - + ? load_store_address_m + : load_store_address_x; + // All store instructions perform a write operation in the M stage assign irom_we_xm = (irom_select_m == `TRUE) - && (store_q_m == `TRUE); - + && (store_q_m == `TRUE); + // A single port in instruction ROM is available to load-store unit for doing loads/stores. // Since every store requires a load (in X stage) and then a store (in M stage), we cannot - // allow load (or store) instructions sequentially after the store instructions to proceed + // allow load (or store) instructions sequentially after the store instructions to proceed // until the store instruction has vacated M stage (i.e., completed the store operation) assign irom_stall_request_x = (irom_select_x == `TRUE) - && (store_q_x == `TRUE); + && (store_q_x == `TRUE); `endif - + `ifdef CFG_DCACHE_ENABLED `ifdef CFG_DRAM_ENABLED `ifdef CFG_IROM_ENABLED // WB + DC + DRAM + IROM - assign data_m = wb_select_m == `TRUE + assign data_m = wb_select_m == `TRUE ? wb_data_m - : dram_select_m == `TRUE + : dram_select_m == `TRUE ? dram_data_m : irom_select_m == `TRUE - ? irom_data_m + ? irom_data_m : dcache_data_m; `else // WB + DC + DRAM - assign data_m = wb_select_m == `TRUE + assign data_m = wb_select_m == `TRUE ? wb_data_m - : dram_select_m == `TRUE + : dram_select_m == `TRUE ? dram_data_m : dcache_data_m; `endif `else `ifdef CFG_IROM_ENABLED // WB + DC + IROM - assign data_m = wb_select_m == `TRUE + assign data_m = wb_select_m == `TRUE ? wb_data_m - : irom_select_m == `TRUE + : irom_select_m == `TRUE ? irom_data_m : dcache_data_m; `else // WB + DC - assign data_m = wb_select_m == `TRUE - ? wb_data_m + assign data_m = wb_select_m == `TRUE + ? wb_data_m : dcache_data_m; `endif `endif @@ -544,22 +542,22 @@ assign irom_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM `ifdef CFG_DRAM_ENABLED `ifdef CFG_IROM_ENABLED // WB + DRAM + IROM - assign data_m = wb_select_m == `TRUE - ? wb_data_m + assign data_m = wb_select_m == `TRUE + ? wb_data_m : dram_select_m == `TRUE ? dram_data_m : irom_data_m; `else // WB + DRAM - assign data_m = wb_select_m == `TRUE - ? wb_data_m + assign data_m = wb_select_m == `TRUE + ? wb_data_m : dram_data_m; `endif `else `ifdef CFG_IROM_ENABLED // WB + IROM - assign data_m = wb_select_m == `TRUE - ? wb_data_m + assign data_m = wb_select_m == `TRUE + ? wb_data_m : irom_data_m; `else // WB @@ -586,9 +584,9 @@ end // Unused/constant Wishbone signals assign d_bte_o = `LM32_BTYPE_LINEAR; -`ifdef CFG_DCACHE_ENABLED +`ifdef CFG_DCACHE_ENABLED // Generate signal to indicate last word in cache line -generate +generate case (bytes_per_line) 4: begin @@ -635,39 +633,39 @@ begin wb_data_m <= {`LM32_WORD_WIDTH{1'b0}}; wb_load_complete <= `FALSE; stall_wb_load <= `FALSE; -`ifdef CFG_DCACHE_ENABLED +`ifdef CFG_DCACHE_ENABLED dcache_refill_ready <= `FALSE; -`endif +`endif end else begin -`ifdef CFG_DCACHE_ENABLED - // Refill ready should only be asserted for a single cycle +`ifdef CFG_DCACHE_ENABLED + // Refill ready should only be asserted for a single cycle dcache_refill_ready <= `FALSE; -`endif +`endif // Is a Wishbone cycle already in progress? if (d_cyc_o == `TRUE) begin // Is the cycle complete? if ((d_ack_i == `TRUE) || (d_err_i == `TRUE)) begin -`ifdef CFG_DCACHE_ENABLED +`ifdef CFG_DCACHE_ENABLED if ((dcache_refilling == `TRUE) && (!last_word)) begin - // Fetch next word of cache line + // Fetch next word of cache line d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; end else -`endif +`endif begin // Refill/access complete d_cyc_o <= `FALSE; d_stb_o <= `FALSE; d_lock_o <= `FALSE; end -`ifdef CFG_DCACHE_ENABLED +`ifdef CFG_DCACHE_ENABLED d_cti_o <= next_cycle_type; - // If we are performing a refill, indicate to cache next word of data is ready + // If we are performing a refill, indicate to cache next word of data is ready dcache_refill_ready <= dcache_refilling; `endif // Register data read from Wishbone interface @@ -675,35 +673,35 @@ begin // Don't set when stores complete - otherwise we'll deadlock if load in m stage wb_load_complete <= !d_we_o; end - // synthesis translate_off + // synthesis translate_off if (d_err_i == `TRUE) $display ("Data bus error. Address: %x", d_adr_o); // synthesis translate_on end else begin -`ifdef CFG_DCACHE_ENABLED +`ifdef CFG_DCACHE_ENABLED if (dcache_refill_request == `TRUE) begin // Start cache refill d_adr_o <= first_address; d_cyc_o <= `TRUE; d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}}; - d_stb_o <= `TRUE; + d_stb_o <= `TRUE; d_we_o <= `FALSE; d_cti_o <= first_cycle_type; //d_lock_o <= `TRUE; end - else -`endif + else +`endif if ( (store_q_m == `TRUE) && (stall_m == `FALSE) `ifdef CFG_DRAM_ENABLED && (dram_select_m == `FALSE) `endif `ifdef CFG_IROM_ENABLED - && (irom_select_m == `FALSE) -`endif + && (irom_select_m == `FALSE) +`endif ) begin // Data cache is write through, so all stores go to memory @@ -714,11 +712,11 @@ begin d_stb_o <= `TRUE; d_we_o <= `TRUE; d_cti_o <= `LM32_CTYPE_END; - end - else if ( (load_q_m == `TRUE) - && (wb_select_m == `TRUE) + end + else if ( (load_q_m == `TRUE) + && (wb_select_m == `TRUE) && (wb_load_complete == `FALSE) - // stall_m will be TRUE, because stall_wb_load will be TRUE + // stall_m will be TRUE, because stall_wb_load will be TRUE ) begin // Read requested address @@ -743,7 +741,7 @@ begin end end -// Pipeline registers +// Pipeline registers // X/M stage pipeline registers always @(posedge clk_i `CFG_RESET_SENSITIVITY) @@ -763,7 +761,7 @@ begin `ifdef CFG_IROM_ENABLED irom_select_m <= `FALSE; `endif - wb_select_m <= `FALSE; + wb_select_m <= `FALSE; end else begin @@ -771,7 +769,7 @@ begin begin sign_extend_m <= sign_extend_x; size_m <= size_x; - byte_enable_m <= byte_enable_x; + byte_enable_m <= byte_enable_x; store_data_m <= store_data_x; `ifdef CFG_DCACHE_ENABLED dcache_select_m <= dcache_select_x; @@ -813,7 +811,7 @@ end // Check for non-aligned loads or stores always @(posedge clk_i) begin - if (((load_q_m == `TRUE) || (store_q_m == `TRUE)) && (stall_m == `FALSE)) + if (((load_q_m == `TRUE) || (store_q_m == `TRUE)) && (stall_m == `FALSE)) begin if ((size_m === `LM32_SIZE_HWORD) && (load_store_address_m[0] !== 1'b0)) $display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time); diff --git a/rtl/lm32_logic_op.v b/rtl/lm32_logic_op.v index 7b1a20d..0f523c8 100644 --- a/rtl/lm32_logic_op.v +++ b/rtl/lm32_logic_op.v @@ -2,7 +2,7 @@ // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< // ------------------------------------------------------------------ // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED +// ALL RIGHTS RESERVED // ------------------------------------------------------------------ // // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. @@ -11,7 +11,7 @@ // // Lattice Semiconductor grants permission to use this code // pursuant to the terms of the Lattice Semiconductor Corporation -// Open Source License Agreement. +// Open Source License Agreement. // // Disclaimer: // @@ -76,9 +76,9 @@ input [`LM32_WORD_RNG] operand_1_x; output [`LM32_WORD_RNG] logic_result_x; reg [`LM32_WORD_RNG] logic_result_x; - + ///////////////////////////////////////////////////// -// Internal nets and registers +// Internal nets and registers ///////////////////////////////////////////////////// integer logic_idx; @@ -92,6 +92,6 @@ begin for(logic_idx = 0; logic_idx < `LM32_WORD_WIDTH; logic_idx = logic_idx + 1) logic_result_x[logic_idx] = logic_op_x[{operand_1_x[logic_idx], operand_0_x[logic_idx]}]; end - + endmodule diff --git a/rtl/lm32_mc_arithmetic.v b/rtl/lm32_mc_arithmetic.v index d476d55..631158a 100644 --- a/rtl/lm32_mc_arithmetic.v +++ b/rtl/lm32_mc_arithmetic.v @@ -2,7 +2,7 @@ // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< // ------------------------------------------------------------------ // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED +// ALL RIGHTS RESERVED // ------------------------------------------------------------------ // // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. @@ -11,7 +11,7 @@ // // Lattice Semiconductor grants permission to use this code // pursuant to the terms of the Lattice Semiconductor Corporation -// Open Source License Agreement. +// Open Source License Agreement. // // Disclaimer: // @@ -48,12 +48,12 @@ // ============================================================================= `include "lm32_include.v" - + `define LM32_MC_STATE_RNG 2:0 `define LM32_MC_STATE_IDLE 3'b000 `define LM32_MC_STATE_MULTIPLY 3'b001 -`define LM32_MC_STATE_MODULUS 3'b010 -`define LM32_MC_STATE_DIVIDE 3'b011 +`define LM32_MC_STATE_MODULUS 3'b010 +`define LM32_MC_STATE_DIVIDE 3'b011 `define LM32_MC_STATE_SHIFT_LEFT 3'b100 `define LM32_MC_STATE_SHIFT_RIGHT 3'b101 @@ -126,7 +126,7 @@ output stall_request_x; // Request to stall pipeline fro wire stall_request_x; ///////////////////////////////////////////////////// -// Internal nets and registers +// Internal nets and registers ///////////////////////////////////////////////////// reg [`LM32_WORD_RNG] p; // Temporary registers @@ -191,18 +191,18 @@ begin case (state) `LM32_MC_STATE_IDLE: begin - if (stall_d == `FALSE) - begin + if (stall_d == `FALSE) + begin cycles <= `LM32_WORD_WIDTH; p <= 32'b0; a <= operand_0_d; - b <= operand_1_d; + b <= operand_1_d; `ifdef CFG_MC_DIVIDE_ENABLED if (divide_d == `TRUE) state <= `LM32_MC_STATE_DIVIDE; if (modulus_d == `TRUE) state <= `LM32_MC_STATE_MODULUS; -`endif +`endif `ifdef CFG_MC_MULTIPLY_ENABLED if (multiply_d == `TRUE) state <= `LM32_MC_STATE_MULTIPLY; @@ -225,7 +225,7 @@ begin b <= operand_0_d; end `endif - end + end end `ifdef CFG_MC_DIVIDE_ENABLED `LM32_MC_STATE_DIVIDE: @@ -235,7 +235,7 @@ begin p <= t[31:0]; a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1}; end - else + else begin p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]}; a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; @@ -256,7 +256,7 @@ begin p <= t[31:0]; a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1}; end - else + else begin p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]}; a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; @@ -270,7 +270,7 @@ begin end cycles <= cycles - 1'b1; end -`endif +`endif `ifdef CFG_MC_MULTIPLY_ENABLED `LM32_MC_STATE_MULTIPLY: begin @@ -283,10 +283,10 @@ begin state <= `LM32_MC_STATE_IDLE; cycles <= cycles - 1'b1; end -`endif +`endif `ifdef CFG_MC_BARREL_SHIFT_ENABLED `LM32_MC_STATE_SHIFT_LEFT: - begin + begin a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; result_x <= a; if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) @@ -294,16 +294,16 @@ begin cycles <= cycles - 1'b1; end `LM32_MC_STATE_SHIFT_RIGHT: - begin + begin b <= {fill_value, b[`LM32_WORD_WIDTH-1:1]}; result_x <= b; if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) state <= `LM32_MC_STATE_IDLE; cycles <= cycles - 1'b1; end -`endif +`endif endcase end -end +end endmodule diff --git a/rtl/lm32_multiplier.v b/rtl/lm32_multiplier.v index d68d150..ae8c934 100644 --- a/rtl/lm32_multiplier.v +++ b/rtl/lm32_multiplier.v @@ -2,7 +2,7 @@ // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< // ------------------------------------------------------------------ // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED +// ALL RIGHTS RESERVED // ------------------------------------------------------------------ // // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. @@ -11,7 +11,7 @@ // // Lattice Semiconductor grants permission to use this code // pursuant to the terms of the Lattice Semiconductor Corporation -// Open Source License Agreement. +// Open Source License Agreement. // // Disclaimer: // @@ -46,7 +46,7 @@ // Version : 3.1 // : No Change // ============================================================================= - + `include "lm32_include.v" ///////////////////////////////////////////////////// @@ -69,27 +69,27 @@ module lm32_multiplier ( // Inputs ///////////////////////////////////////////////////// -input clk_i; // Clock +input clk_i; // Clock input rst_i; // Reset input stall_x; // Stall instruction in X stage input stall_m; // Stall instruction in M stage -input [`LM32_WORD_RNG] operand_0; // Muliplicand -input [`LM32_WORD_RNG] operand_1; // Multiplier +input [`LM32_WORD_RNG] operand_0; // Muliplicand +input [`LM32_WORD_RNG] operand_1; // Multiplier ///////////////////////////////////////////////////// // Outputs ///////////////////////////////////////////////////// -output [`LM32_WORD_RNG] result; // Product of multiplication +output [`LM32_WORD_RNG] result; // Product of multiplication reg [`LM32_WORD_RNG] result; ///////////////////////////////////////////////////// -// Internal nets and registers +// Internal nets and registers ///////////////////////////////////////////////////// -reg [`LM32_WORD_RNG] muliplicand; -reg [`LM32_WORD_RNG] multiplier; -reg [`LM32_WORD_RNG] product; +reg [`LM32_WORD_RNG] muliplicand; +reg [`LM32_WORD_RNG] multiplier; +reg [`LM32_WORD_RNG] product; ///////////////////////////////////////////////////// // Sequential logic @@ -107,7 +107,7 @@ begin else begin if (stall_x == `FALSE) - begin + begin muliplicand <= operand_0; multiplier <= operand_1; end diff --git a/rtl/lm32_multiplier_spartan6.v b/rtl/lm32_multiplier_spartan6.v index 5e367b6..b687285 100644 --- a/rtl/lm32_multiplier_spartan6.v +++ b/rtl/lm32_multiplier_spartan6.v @@ -27,13 +27,13 @@ */ module lm32_multiplier( - input clk_i, - input rst_i, - input stall_x, - input stall_m, - input [31:0] operand_0, - input [31:0] operand_1, - output [31:0] result + input clk_i, + input rst_i, + input stall_x, + input stall_m, + input [31:0] operand_0, + input [31:0] operand_1, + output [31:0] result ); // See UG389, esp. p. 29 "Fully Pipelined, 35 x 35 Multiplier Use Model (Large Multiplier)" @@ -48,157 +48,157 @@ wire [35:0] al_bl; reg [16:0] result_low; always @(posedge clk_i) begin - if(rst_i) - result_low <= 17'd0; - else - result_low <= al_bl[16:0]; + if(rst_i) + result_low <= 17'd0; + else + result_low <= al_bl[16:0]; end assign result[16:0] = result_low; DSP48A1 #( - .A0REG(1), - .A1REG(0), - .B0REG(1), - .B1REG(0), - .CARRYINREG(0), - .CARRYINSEL("OPMODE5"), - .CARRYOUTREG(0), - .CREG(0), - .DREG(0), - .MREG(1), - .OPMODEREG(0), - .PREG(0), - .RSTTYPE("SYNC") + .A0REG(1), + .A1REG(0), + .B0REG(1), + .B1REG(0), + .CARRYINREG(0), + .CARRYINSEL("OPMODE5"), + .CARRYOUTREG(0), + .CREG(0), + .DREG(0), + .MREG(1), + .OPMODEREG(0), + .PREG(0), + .RSTTYPE("SYNC") ) D1 ( - .BCOUT(bl_forward), - .PCOUT(), - .CARRYOUT(), - .CARRYOUTF(), - .M(al_bl), - .P(), - .PCIN(), - .CLK(clk_i), - .OPMODE(8'd1), - .A(al), - .B(bl), - .C(), - .CARRYIN(), - .D(), - .CEA(~stall_x), - .CEB(~stall_x), - .CEC(), - .CECARRYIN(), - .CED(), - .CEM(~stall_m), - .CEOPMODE(), - .CEP(1'b1), - .RSTA(rst_i), - .RSTB(rst_i), - .RSTC(), - .RSTCARRYIN(), - .RSTD(), - .RSTM(rst_i), - .RSTOPMODE(), - .RSTP() + .BCOUT(bl_forward), + .PCOUT(), + .CARRYOUT(), + .CARRYOUTF(), + .M(al_bl), + .P(), + .PCIN(), + .CLK(clk_i), + .OPMODE(8'd1), + .A(al), + .B(bl), + .C(), + .CARRYIN(), + .D(), + .CEA(~stall_x), + .CEB(~stall_x), + .CEC(), + .CECARRYIN(), + .CED(), + .CEM(~stall_m), + .CEOPMODE(), + .CEP(1'b1), + .RSTA(rst_i), + .RSTB(rst_i), + .RSTC(), + .RSTCARRYIN(), + .RSTD(), + .RSTM(rst_i), + .RSTOPMODE(), + .RSTP() ); wire [47:0] au_bl_sum; DSP48A1 #( - .A0REG(1), - .A1REG(0), - .B0REG(0), - .B1REG(0), - .CARRYINREG(0), - .CARRYINSEL("OPMODE5"), - .CARRYOUTREG(0), - .CREG(0), - .DREG(0), - .MREG(1), - .OPMODEREG(0), - .PREG(0), - .RSTTYPE("SYNC") + .A0REG(1), + .A1REG(0), + .B0REG(0), + .B1REG(0), + .CARRYINREG(0), + .CARRYINSEL("OPMODE5"), + .CARRYOUTREG(0), + .CREG(0), + .DREG(0), + .MREG(1), + .OPMODEREG(0), + .PREG(0), + .RSTTYPE("SYNC") ) D2 ( - .BCOUT(), - .PCOUT(au_bl_sum), - .CARRYOUT(), - .CARRYOUTF(), - .M(), - .P(), - .PCIN(), - .CLK(clk_i), - .OPMODE(8'd13), - .A(au), - .B(bl_forward), - .C({31'd0, al_bl[33:17]}), - .CARRYIN(), - .D(), - .CEA(~stall_x), - .CEB(), - .CEC(), - .CECARRYIN(), - .CED(), - .CEM(~stall_m), - .CEOPMODE(), - .CEP(), - .RSTA(rst_i), - .RSTB(), - .RSTC(), - .RSTCARRYIN(), - .RSTD(), - .RSTM(rst_i), - .RSTOPMODE(), - .RSTP() + .BCOUT(), + .PCOUT(au_bl_sum), + .CARRYOUT(), + .CARRYOUTF(), + .M(), + .P(), + .PCIN(), + .CLK(clk_i), + .OPMODE(8'd13), + .A(au), + .B(bl_forward), + .C({31'd0, al_bl[33:17]}), + .CARRYIN(), + .D(), + .CEA(~stall_x), + .CEB(), + .CEC(), + .CECARRYIN(), + .CED(), + .CEM(~stall_m), + .CEOPMODE(), + .CEP(), + .RSTA(rst_i), + .RSTB(), + .RSTC(), + .RSTCARRYIN(), + .RSTD(), + .RSTM(rst_i), + .RSTOPMODE(), + .RSTP() ); wire [47:0] r_full; assign result[31:17] = r_full[16:0]; DSP48A1 #( - .A0REG(1), - .A1REG(0), - .B0REG(1), - .B1REG(0), - .CARRYINREG(0), - .CARRYINSEL("OPMODE5"), - .CARRYOUTREG(0), - .CREG(0), - .DREG(0), - .MREG(1), - .OPMODEREG(0), - .PREG(1), - .RSTTYPE("SYNC") + .A0REG(1), + .A1REG(0), + .B0REG(1), + .B1REG(0), + .CARRYINREG(0), + .CARRYINSEL("OPMODE5"), + .CARRYOUTREG(0), + .CREG(0), + .DREG(0), + .MREG(1), + .OPMODEREG(0), + .PREG(1), + .RSTTYPE("SYNC") ) D3 ( - .BCOUT(), - .PCOUT(), - .CARRYOUT(), - .CARRYOUTF(), - .M(), - .P(r_full), - .PCIN(au_bl_sum), - .CLK(clk_i), - .OPMODE(8'd5), - .A(bu), - .B(al), - .C(), - .CARRYIN(), - .D(), - .CEA(~stall_x), - .CEB(~stall_x), - .CEC(), - .CECARRYIN(), - .CED(), - .CEM(~stall_m), - .CEOPMODE(), - .CEP(1'b1), - .RSTA(rst_i), - .RSTB(rst_i), - .RSTC(), - .RSTCARRYIN(), - .RSTD(), - .RSTM(rst_i), - .RSTOPMODE(), - .RSTP(rst_i) + .BCOUT(), + .PCOUT(), + .CARRYOUT(), + .CARRYOUTF(), + .M(), + .P(r_full), + .PCIN(au_bl_sum), + .CLK(clk_i), + .OPMODE(8'd5), + .A(bu), + .B(al), + .C(), + .CARRYIN(), + .D(), + .CEA(~stall_x), + .CEB(~stall_x), + .CEC(), + .CECARRYIN(), + .CED(), + .CEM(~stall_m), + .CEOPMODE(), + .CEP(1'b1), + .RSTA(rst_i), + .RSTB(rst_i), + .RSTC(), + .RSTCARRYIN(), + .RSTD(), + .RSTM(rst_i), + .RSTOPMODE(), + .RSTP(rst_i) ); endmodule diff --git a/rtl/lm32_ram.v b/rtl/lm32_ram.v index d84352f..6584902 100644 --- a/rtl/lm32_ram.v +++ b/rtl/lm32_ram.v @@ -2,7 +2,7 @@ // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< // ------------------------------------------------------------------ // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED +// ALL RIGHTS RESERVED // ------------------------------------------------------------------ // // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. @@ -11,7 +11,7 @@ // // Lattice Semiconductor grants permission to use this code // pursuant to the terms of the Lattice Semiconductor Corporation -// Open Source License Agreement. +// Open Source License Agreement. // // Disclaimer: // @@ -58,21 +58,20 @@ // Module interface ///////////////////////////////////////////////////// -module lm32_ram - ( - // ----- Inputs ------- - read_clk, - write_clk, - reset, - enable_read, - read_address, - enable_write, - write_address, - write_data, - write_enable, - // ----- Outputs ------- - read_data - ); +module lm32_ram ( + // ----- Inputs ------- + read_clk, + write_clk, + reset, + enable_read, + read_address, + enable_write, + write_address, + write_data, + write_enable, + // ----- Outputs ------- + read_data + ); /*---------------------------------------------------------------------- Parameters @@ -117,12 +116,12 @@ assign read_data = mem[ra]; ----------------------------------------------------------------------*/ // Write port always @(posedge write_clk) - if ((write_enable == `TRUE) && (enable_write == `TRUE)) - mem[write_address] <= write_data; + if ((write_enable == `TRUE) && (enable_write == `TRUE)) + mem[write_address] <= write_data; // Register read address for use on next cycle always @(posedge read_clk) - if (enable_read) - ra <= read_address; + if (enable_read) + ra <= read_address; endmodule diff --git a/rtl/lm32_shifter.v b/rtl/lm32_shifter.v index ce5b85d..d34f8c5 100644 --- a/rtl/lm32_shifter.v +++ b/rtl/lm32_shifter.v @@ -2,7 +2,7 @@ // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< // ------------------------------------------------------------------ // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED +// ALL RIGHTS RESERVED // ------------------------------------------------------------------ // // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. @@ -11,7 +11,7 @@ // // Lattice Semiconductor grants permission to use this code // pursuant to the terms of the Lattice Semiconductor Corporation -// Open Source License Agreement. +// Open Source License Agreement. // // Disclaimer: // @@ -86,7 +86,7 @@ output [`LM32_WORD_RNG] shifter_result_m; // Result of shift wire [`LM32_WORD_RNG] shifter_result_m; ///////////////////////////////////////////////////// -// Internal nets and registers +// Internal nets and registers ///////////////////////////////////////////////////// reg direction_m; @@ -103,7 +103,7 @@ integer shift_idx_1; ///////////////////////////////////////////////////// // Combinational Logic ///////////////////////////////////////////////////// - + // Select operands - To perform a left shift, we reverse the bits and perform a right shift always @(*) begin @@ -113,8 +113,8 @@ end assign right_shift_operand = direction_x == `LM32_SHIFT_OP_LEFT ? left_shift_operand : operand_0_x; // Determine fill value for right shift - Sign bit for arithmetic shift, or zero for logical shift -assign fill_value = (sign_extend_x == `TRUE) && (direction_x == `LM32_SHIFT_OP_RIGHT) - ? operand_0_x[`LM32_WORD_WIDTH-1] +assign fill_value = (sign_extend_x == `TRUE) && (direction_x == `LM32_SHIFT_OP_RIGHT) + ? operand_0_x[`LM32_WORD_WIDTH-1] : 1'b0; // Determine bits to shift in for right shift or rotate @@ -127,9 +127,9 @@ begin left_shift_result[`LM32_WORD_WIDTH-1-shift_idx_1] = right_shift_result[shift_idx_1]; end -// Select result +// Select result assign shifter_result_m = direction_m == `LM32_SHIFT_OP_LEFT ? left_shift_result : right_shift_result; - + ///////////////////////////////////////////////////// // Sequential Logic ///////////////////////////////////////////////////// @@ -150,6 +150,6 @@ begin direction_m <= direction_x; end end -end - +end + endmodule diff --git a/rtl/lm32_top.v b/rtl/lm32_top.v index bc2bdf5..2ebe1b4 100644 --- a/rtl/lm32_top.v +++ b/rtl/lm32_top.v @@ -2,7 +2,7 @@ // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< // ------------------------------------------------------------------ // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED +// ALL RIGHTS RESERVED // ------------------------------------------------------------------ // // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. @@ -11,7 +11,7 @@ // // Lattice Semiconductor grants permission to use this code // pursuant to the terms of the Lattice Semiconductor Corporation -// Open Source License Agreement. +// Open Source License Agreement. // // Disclaimer: // @@ -58,9 +58,9 @@ module lm32_top ( clk_i, rst_i, `ifdef CFG_DEBUG_ENABLED - `ifdef CFG_ALTERNATE_EBA +`ifdef CFG_ALTERNATE_EBA at_debug, - `endif +`endif `endif // From external devices `ifdef CFG_INTERRUPTS_ENABLED @@ -70,7 +70,7 @@ module lm32_top ( `ifdef CFG_USER_ENABLED user_result, user_complete, -`endif +`endif `ifdef CFG_IWB_ENABLED // Instruction Wishbone master I_DAT_I, @@ -87,12 +87,12 @@ module lm32_top ( D_ERR_I, D_RTY_I, // ----- Outputs ------- -`ifdef CFG_USER_ENABLED +`ifdef CFG_USER_ENABLED user_valid, user_opcode, user_operand_0, user_operand_1, -`endif +`endif `ifdef CFG_IWB_ENABLED // Instruction Wishbone master I_DAT_O, @@ -125,9 +125,9 @@ input clk_i; // Clock input rst_i; // Reset `ifdef CFG_DEBUG_ENABLED - `ifdef CFG_ALTERNATE_EBA - input at_debug; // GPIO input that maps EBA to DEBA - `endif +`ifdef CFG_ALTERNATE_EBA +input at_debug; // GPIO input that maps EBA to DEBA +`endif `endif `ifdef CFG_INTERRUPTS_ENABLED @@ -137,7 +137,7 @@ input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins `ifdef CFG_USER_ENABLED input [`LM32_WORD_RNG] user_result; // User-defined instruction result input user_complete; // Indicates the user-defined instruction result is valid -`endif +`endif `ifdef CFG_IWB_ENABLED input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data @@ -183,11 +183,11 @@ output I_STB_O; // Instruction Wishbone interfac wire I_STB_O; output I_WE_O; // Instruction Wishbone interface write enable wire I_WE_O; -output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type +output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type wire [`LM32_CTYPE_RNG] I_CTI_O; output I_LOCK_O; // Instruction Wishbone interface lock bus wire I_LOCK_O; -output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type +output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type wire [`LM32_BTYPE_RNG] I_BTE_O; `endif @@ -203,17 +203,17 @@ output D_STB_O; // Data Wishbone interface strob wire D_STB_O; output D_WE_O; // Data Wishbone interface write enable wire D_WE_O; -output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type +output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type wire [`LM32_CTYPE_RNG] D_CTI_O; output D_LOCK_O; // Date Wishbone interface lock bus wire D_LOCK_O; -output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type +output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type wire [`LM32_BTYPE_RNG] D_BTE_O; ///////////////////////////////////////////////////// -// Internal nets and registers +// Internal nets and registers ///////////////////////////////////////////////////// - + `ifdef CFG_JTAG_ENABLED // Signals between JTAG interface and CPU wire [`LM32_BYTE_RNG] jtag_reg_d; @@ -244,9 +244,9 @@ wire trace_bret; // Indicates a bret instruction ///////////////////////////////////////////////////// // Instantiations -///////////////////////////////////////////////////// - -// LM32 CPU +///////////////////////////////////////////////////// + +// LM32 CPU lm32_cpu cpu ( // ----- Inputs ------- .clk_i (clk_i), @@ -255,9 +255,9 @@ lm32_cpu cpu ( `endif .rst_i (rst_i), `ifdef CFG_DEBUG_ENABLED - `ifdef CFG_ALTERNATE_EBA +`ifdef CFG_ALTERNATE_EBA .at_debug (at_debug), - `endif +`endif `endif // From external devices `ifdef CFG_INTERRUPTS_ENABLED @@ -267,7 +267,7 @@ lm32_cpu cpu ( `ifdef CFG_USER_ENABLED .user_result (user_result), .user_complete (user_complete), -`endif +`endif `ifdef CFG_JTAG_ENABLED // From JTAG .jtag_clk (jtck), @@ -305,12 +305,12 @@ lm32_cpu cpu ( .jtag_reg_d (jtag_reg_d), .jtag_reg_addr_d (jtag_reg_addr_d), `endif -`ifdef CFG_USER_ENABLED +`ifdef CFG_USER_ENABLED .user_valid (user_valid), .user_opcode (user_opcode), .user_operand_0 (user_operand_0), .user_operand_1 (user_operand_1), -`endif +`endif `ifdef CFG_IWB_ENABLED // Instruction Wishbone master .I_DAT_O (I_DAT_O), @@ -334,9 +334,9 @@ lm32_cpu cpu ( .D_LOCK_O (D_LOCK_O), .D_BTE_O (D_BTE_O) ); - -`ifdef CFG_JTAG_ENABLED -// JTAG cores + +`ifdef CFG_JTAG_ENABLED +// JTAG cores jtag_cores jtag_cores ( // ----- Inputs ----- .reg_d (jtag_reg_d), @@ -348,6 +348,6 @@ jtag_cores jtag_cores ( .jtck (jtck), .jrstn (jrstn) ); -`endif - +`endif + endmodule