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Based on core from mico32_72_linux.tar by Lattice Semiconductor.

Signed-off-by: lekernel <sebastien.bourdeauducq@lekernel.net>
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0 parents commit d1a411bf17c3fb2aef192a21537f4460e5fefca8 lekernel committed with mwalle Oct 2, 2009
607 LICENSE.LATTICE
@@ -0,0 +1,607 @@
+LATTICE SEMICONDUCTOR CORPORATION
+LatticeMico TM System License Agreement
+
+This is a legal agreement between you, the end user, and Lattice Semiconductor
+Corporation. By proceeding with the installation or use of the Software, you
+agree to be bound by the terms of this Agreement. If you do not agree to the
+terms of this Agreement, do not use, download or install the Software, and if you
+have already obtained the Software from an authorized source, promptly return the
+media package and all accompanying items (including written materials and
+binders or other containers) to the place you obtained them for a full refund
+of any applicable license fees.
+
+Lattice Semiconductor Corporation ("Lattice") and the individual or entity
+acquiring the Software ("Licensee") agree as follows:
+
+1. DEFINITIONS
+"Software" means the LatticeMico System computer program(s) other than the
+open source programs identified in Section 11 herein in machine-readable form
+furnished to Licensee by Lattice, in whatever media and by whatever method,
+which are enabled for use pursuant to Lattice's software protection mechanism,
+and for which Licensee has paid any applicable license fees. Software includes
+any related update or upgrade programs that may be added from time to time.
+
+2. SOFTWARE LICENSE
+a. Lattice hereby grants to Licensee a non-exclusive, nontransferable license
+to use the Software for Licensee's internal purposes only on any computer
+possessed by Licensee on which the Software is designed to operate, such use
+to be in accordance with and subject to the terms and conditions of this
+Agreement.
+
+b. Pursuant to this Agreement, Licensee may (i) physically transfer any
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+only one such computer at a time and (ii) use the Software and any output
+files generated by the Software for the sole purpose of designing and
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+into any other software to form an updated work; provided that, upon
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+c. Licensee shall include Lattice's (and Lattice's suppliers', as applicable)
+copyrights, trademarks, and other proprietary notices on any copies and merged
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+d. Licensee shall not distribute, copy, transfer, lend, incorporate, modify,
+or use the Software for any purpose except as expressly provided herein.
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+e. If Licensee fails to comply with the provisions of this Agreement, the
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+f. Except for the rights expressly granted herein to Licensee, the title and
+all intellectual property rights in and to the Software and any copy of the
+Software which may be made by Licensee hereunder remain the sole and exclusive
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+
+3. LIMITED WARRANTY AND REMEDIES
+a. Lattice warrants to Licensee that the media containing the Software will
+be free from defects in materials and workmanship under normal use and service
+for a period of ninety (90) days from the date of delivery. Lattice further
+warrants that the Software will substantially conform to Lattice's published
+specifications for the Software at the time of delivery for a period of ninety
+(90) days from the date of delivery.
+
+b. During the 90-day warranty period, (1) Lattice will replace any Software
+not meeting the foregoing warranty that is returned to Lattice; or (2) if
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+c. Any products which are not returned to Lattice within the warranty period
+or which have been subject to accident, abuse, misuse, alteration, neglect, or
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+4. WARRANTY DISCLAIMER
+EXCEPT FOR THE ABOVE EXPRESSED LIMITED WARRANTIES, LATTICE MAKES NO WARRANTIES
+ON THE SOFTWARE, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY OTHER
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+5. SOURCE CODE
+Licensee shall not attempt to reverse translate, decompile or otherwise
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+6. LIMITATION OF LIABILITY
+a. Licensee agrees that Lattice's entire liability to Licensee and Licensee's
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+b. IN NO EVENT WILL LATTICE OR ANY OF ITS SUPPLIERS BE LIABLE TO LICENSEE
+OR ANY OTHER PERSON FOR ANY DAMAGES, INCLUDING ANY DIRECT, INDIRECT,
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+SOME STATES DO NOT ALLOW THE LIMITATION OR EXCLUSION OF INCIDENTAL OR
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+7. DEFAULT AND TERMINATION
+This Agreement will continue indefinitely, until and unless terminated; it
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+8. EXPORT CONTROL
+Licensee shall not export the Software or the direct product thereof without
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+ - that Licensee is not on the Denied Persons List maintained by the U.S.
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+export of the referenced Software is prohibited; and
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+
+9. U.S. GOVERNMENT RESTRICTED RIGHTS
+The Software and any accompanying documentation provided to agencies of the
+U.S. Government are "commercial computer software" and "commercial computer
+software documentation" pursuant to DFARS 227.7202 and FAR 12.212, and their
+successors. All use, reproduction, release, performance, display or disclosure
+of the Software and related documentation by or for the U.S. Government shall
+be in strict accordance with the terms and conditions of this Agreement.
+Contractor/manufacturer is Lattice Semiconductor Corporation, 5555 NE Moore
+Court, Hillsboro, Oregon 97124 and its licensors.
+
+10. ADDITIONAL TERMS AND CONDITIONS APPLICABLE TO LATTICE PROGRAMMING HARDWARE
+Lattice programmers, ispDOWNLOADTM cables, and other hardware sold for use in
+conjunction with Lattice software ("Programming Hardware") are designed and
+intended for use solely with semiconductor components manufactured by Lattice
+Semiconductor Corporation. Programming Hardware is warranted to meet Lattice
+Specifications only for a period of ninety (90) days; in all other respects
+the terms and conditions of sale of Programming Hardware shall be Lattice's
+standard terms and conditions set forth in Lattice's Sales Order
+Acknowledgement. Furthermore, Lattice Specifications for the ispDOWNLOAD
+cable limit its use to low-volume engineering applications only, and not for
+volume production use. As with all other Programming Hardware, Lattice shall
+not be liable for any use of the ispDOWNLOAD cable in production, or use of
+worn or improperly installed hardware or use with incompatible systems or
+components.
+
+11. OPEN SOURCE SOFTWARE
+a. Your use of the Software is governed by the terms of this Agreement.
+However, certain separate source code modules identified in Section 11(b)
+and Section 11(c) below that are installed with, but not integrated with, the
+Software have been provided by third parties. By proceeding with the
+installation and use of such open source code, you are also agreeing to use
+this code in accordance with the terms of the agreements under which such
+code has been licensed.
+
+b. Certain open source code is licensed under the Eclipse Public License
+v. 1.0, a copy of which is attached hereto as Appendix A.
+
+c. Certain open source code is licensed pursuant to the terms of the notice
+attached hereto as Appendix B.
+
+d. Certain portion of the Software are licensed under the Mozilla Public License,
+Version 1.1. pursuant to the terms of the notice attached hereto as Appendix C.
+
+12. OPEN SOURCE LICENSE AGREEMENT FOR OUTPUT FILES GENERATED BY THE
+LATTICEMICO SYSTEM
+By proceeding with the installation and use of the LatticeMico System, you
+are agreeing to use the output files generated by it in accordance with the
+terms of the Lattice Semiconductor Corporation Open Source License Agreement,
+a copy of which is attached hereto as Appendix D.
+
+13. INFORMATION REGARDING PERSONAL DATA
+If you downloaded this Software from our website, we have collected
+information about you, including your name and contact information, from the
+information you provided when you registered to use the website.
+
+If you acquired the Software from a source other than our website, we will ask
+you for certain information, including your name and contact information, as
+part of the installation procedure.
+
+Some of our Software comes bundled with software from third party providers,
+including Aldec, Inc. and Synopsys, Inc. If you obtain a
+license key from us for such Software, we will provide your name, corporate
+affiliation, address, phone number, fax number, and email address, along with
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+
+14. GENERAL
+THIS AGREEMENT WILL BE GOVERNED BY THE LAWS OF THE STATE OF OREGON, WITHOUT
+REGARD TO ITS CONFLICT OF LAWS PROVISIONS.
+
+The prevailing party in any legal action or arbitration arising out of this
+Agreement shall be entitled to reimbursement for reasonable attorneys' fees
+and expenses, in addition to any other rights and remedies such party may have.
+
+Lattice reserves the right in its sole discretion to discontinue third party
+software tools that come bundled with the Software at any time.
+
+Licensee may not sublicense, assign, or transfer this license or the Software.
+Any attempted assignment, transfer or sublicense by Licensee in violation of
+this provision shall be void. Subject to the foregoing, this Agreement shall
+be binding upon and inure to the benefit of the successors and permitted
+assigns of the parties.
+
+This Agreement is the entire agreement between the parties with respect to use
+of the Software and supersedes any other communications or prior agreements,
+oral or written, regarding the Software.
+
+If any provision of this Agreement is held invalid, the remainder of the
+Agreement shall continue in full force and effect.
+
+Please direct all inquiries, in writing, to Lattice Semiconductor Corporation,
+5555 N.E. Moore Court, Hillsboro, Oregon 97124.
+
+(c)2006-2011 Lattice Semiconductor Corporation. All rights reserved.
+
+Intellectual Property Notice
+
+The software governed by this License Agreement is:
+
+Copyright (c), 2006-2011, Lattice Semiconductor Corporation, All Rights Reserved
+
+
+
+
+APPENDIX A
+
+Eclipse Public License v 1.0
+
+THE ACCOMPANYING PROGRAM IS PROVIDED UNDER THE TERMS OF THIS ECLIPSE PUBLIC
+LICENSE ("AGREEMENT"). ANY USE, REPRODUCTION OR DISTRIBUTION OF THE PROGRAM
+CONSTITUTES RECIPIENT'S ACCEPTANCE OF THIS AGREEMENT.
+
+1. DEFINITIONS
+
+"Contribution" means:
+
+a) in the case of the initial Contributor, the initial code and documentation
+distributed under this Agreement, and
+
+b) in the case of each subsequent Contributor: i) changes to the Program, and
+ii) additions to the Program; where such changes and/or additions to the
+Program originate from and are distributed by that particular Contributor.
+A Contribution 'originates' from a Contributor if it was added to the Program
+by such Contributor itself or anyone acting on such Contributor's behalf.
+Contributions do not include additions to the Program which: (i) are separate
+modules of software distributed in conjunction with the Program under their
+own license agreement, and (ii) are not derivative works of the Program.
+
+"Contributor" means any person or entity that distributes the Program.
+
+"Licensed Patents" mean patent claims licensable by a Contributor which are
+necessarily infringed by the use or sale of its Contribution alone or when
+combined with the Program.
+
+"Program" means the Contributions distributed in accordance with this
+Agreement.
+
+"Recipient" means anyone who receives the Program under this Agreement,
+including all Contributors.
+
+2. GRANT OF RIGHTS
+
+a) Subject to the terms of this Agreement, each Contributor hereby grants
+Recipient a non-exclusive, worldwide, royalty-free copyright license to
+reproduce, prepare derivative works of, publicly display, publicly perform,
+distribute and sublicense the Contribution of such Contributor, if any, and
+such derivative works, in source code and object code form.
+
+b) Subject to the terms of this Agreement, each Contributor hereby grants
+Recipient a non-exclusive, worldwide, royalty-free patent license under
+Licensed Patents to make, use, sell, offer to sell, import and otherwise
+transfer the Contribution of such Contributor, if any, in source code and
+object code form. This patent license shall apply to the combination of the
+Contribution and the Program if, at the time the Contribution is added by the
+Contributor, such addition of the Contribution causes such combination to be
+covered by the Licensed Patents. The patent license shall not apply to any
+other combinations which include the Contribution. No hardware per se is
+licensed hereunder.
+
+c) Recipient understands that although each Contributor grants the licenses
+to its Contributions set forth herein, no assurances are provided by any
+Contributor that the Program does not infringe the patent or other
+intellectual property rights of any other entity. Each Contributor disclaims
+any liability to Recipient for claims brought by any other entity based on
+infringement of intellectual property rights or otherwise. As a condition to
+exercising the rights and licenses granted hereunder, each Recipient hereby
+assumes sole responsibility to secure any other intellectual property rights
+needed, if any. For example, if a third party patent license is required to
+allow Recipient to distribute the Program, it is Recipient's responsibility to
+acquire that license before distributing the Program.
+
+d) Each Contributor represents that to its knowledge it has sufficient
+copyright rights in its Contribution, if any, to grant the copyright license
+set forth in this Agreement.
+
+3. REQUIREMENTS
+
+A Contributor may choose to distribute the Program in object code form under
+its own license agreement, provided that:
+a) it complies with the terms and conditions of this Agreement; and
+b) its license agreement:
+i) effectively disclaims on behalf of all Contributors all warranties and
+conditions, express and implied, including warranties or conditions of title
+and non-infringement, and implied warranties or conditions of merchantability
+and fitness for a particular purpose;
+ii) effectively excludes on behalf of all Contributors all liability for
+damages, including direct, indirect, special, incidental and consequential
+damages, such as lost profits;
+iii) states that any provisions which differ from this Agreement are offered
+by that Contributor alone and not by any other party; and
+iv) states that source code for the Program is available from such
+Contributor, and informs licensees how to obtain it in a reasonable manner
+on or through a medium customarily used for software exchange.
+When the Program is made available in source code form:
+a) it must be made available under this Agreement; and
+b) a copy of this Agreement must be included with each copy of the Program.
+Contributors may not remove or alter any copyright notices contained within
+the Program.
+Each Contributor must identify itself as the originator of its Contribution,
+if any, in a manner that reasonably allows subsequent Recipients to identify
+the originator of the Contribution.
+
+4. COMMERCIAL DISTRIBUTION
+
+Commercial distributors of software may accept certain responsibilities with
+respect to end users, business partners and the like. While this license is
+intended to facilitate the commercial use of the Program, the Contributor
+who includes the Program in a commercial product offering should do so in a
+manner which does not create potential liability for other Contributors.
+Therefore, if a Contributor includes the Program in a commercial product
+offering, such Contributor ("Commercial Contributor") hereby agrees to defend
+and indemnify every other Contributor ("Indemnified Contributor") against any
+losses, damages and costs (collectively "Losses") arising from claims,
+lawsuits and other legal actions brought by a third party against the
+Indemnified Contributor to the extent caused by the acts or omissions of such
+Commercial Contributor in connection with its distribution of the Program in a
+commercial product offering. The obligations in this section do not apply to
+any claims or Losses relating to any actual or alleged intellectual property
+infringement. In order to qualify, an Indemnified Contributor must: a)
+promptly notify the Commercial Contributor in writing of such claim, and b)
+allow the Commercial Contributor to control, and cooperate with the Commercial
+Contributor in, the defense and any related settlement negotiations. The
+Indemnified Contributor may participate in any such claim at its own expense.
+
+For example, a Contributor might include the Program in a commercial product
+offering, Product X. That Contributor is then a Commercial Contributor. If
+that Commercial Contributor then makes performance claims, or offers
+warranties related to Product X, those performance claims and warranties are
+such Commercial Contributor's responsibility alone. Under this section, the
+Commercial Contributor would have to defend claims against the other
+Contributors related to those performance claims and warranties, and if a
+court requires any other Contributor to pay any damages as a result, the
+Commercial Contributor must pay those damages.
+
+5. NO WARRANTY
+
+EXCEPT AS EXPRESSLY SET FORTH IN THIS AGREEMENT, THE PROGRAM IS PROVIDED ON
+AN "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, EITHER EXPRESS
+OR IMPLIED INCLUDING, WITHOUT LIMITATION, ANY WARRANTIES OR CONDITIONS OF
+TITLE, NON-INFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
+
+Each Recipient is solely responsible for determining the appropriateness of
+using and distributing the Program and assumes all risks associated with its
+exercise of rights under this Agreement , including but not limited to the
+risks and costs of program errors, compliance with applicable laws, damage to
+or loss of data, programs or equipment, and unavailability or interruption of
+operations.
+
+6. DISCLAIMER OF LIABILITY
+
+EXCEPT AS EXPRESSLY SET FORTH IN THIS AGREEMENT, NEITHER RECIPIENT NOR ANY
+CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING WITHOUT LIMITATION
+LOST PROFITS), HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OR DISTRIBUTION OF THE PROGRAM OR THE
+EXERCISE OF ANY RIGHTS GRANTED HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGES.
+
+7. GENERAL
+
+If any provision of this Agreement is invalid or unenforceable under
+applicable law, it shall not affect the validity or enforceability of the
+remainder of the terms of this Agreement, and without further action by the
+parties hereto, such provision shall be reformed to the minimum extent
+necessary to make such provision valid and enforceable.
+
+If Recipient institutes patent litigation against any entity (including a
+cross-claim or counterclaim in a lawsuit) alleging that the Program itself
+(excluding combinations of the Program with other software or hardware)
+infringes such Recipient's patent(s), then such Recipient's rights granted
+under Section 2(b) shall terminate as of the date such litigation is filed.
+
+All Recipient's rights under this Agreement shall terminate if it fails to
+comply with any of the material terms or conditions of this Agreement and
+does not cure such failure in a reasonable period of time after becoming
+aware of such noncompliance. If all Recipient's rights under this Agreement
+terminate, Recipient agrees to cease use and distribution of the Program as
+soon as reasonably practicable. However, Recipient's obligations under this
+Agreement and any licenses granted by Recipient relating to the Program shall
+continue and survive.
+
+Everyone is permitted to copy and distribute copies of this Agreement, but in
+order to avoid inconsistency the Agreement is copyrighted and may only be
+modified in the following manner. The Agreement Steward reserves the right
+to publish new versions (including revisions) of this Agreement from time to
+time. No one other than the Agreement Steward has the right to modify this
+Agreement. The Eclipse Foundation is the initial Agreement Steward. The
+Eclipse Foundation may assign the responsibility to serve as the Agreement
+Steward to a suitable separate entity. Each new version of the Agreement will
+be given a distinguishing version number. The Program (including
+Contributions) may always be distributed subject to the version of the
+Agreement under which it was received. In addition, after a new version of the
+Agreement is published, Contributor may elect to distribute the Program
+(including its Contributions) under the new version. Except as expressly
+stated in Sections 2(a) and 2(b) above, Recipient receives no rights or
+licenses to the intellectual property of any Contributor under this Agreement,
+whether expressly, by implication, estoppel or otherwise. All rights in the
+Program not expressly granted under this Agreement are reserved.
+
+This Agreement is governed by the laws of the State of New York and the
+intellectual property laws of the United States of America. No party to this
+Agreement will bring a legal action under this Agreement more than one year
+after the cause of action arose. Each party waives its rights to a jury trial
+in any resulting litigation.
+
+
+APPENDIX B
+
+Copyright (C) 2001 Richard Herveille
+richard@asics.ws
+
+This source file may be used and distributed without restriction provided that
+this copyright statement is not removed from the file and that any derivative
+work contains the original copyright notice and the associated disclaimer.
+
+THIS SOFTWARE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS OR IMPLIED
+WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL
+THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+APPENDIX C
+
+The following terms only apply to the executable code version of the SeaMonkey
+program made available with the Software ("the Product"):
+
+The Product is subject to the Mozilla Public License, Version 1.1 (the "License");
+you may not use the Product except in compliance with this License. You may
+obtain a copy of the License at http://www.mozilla.org/MPL/
+
+The Product distributed under this license is distributed on an "AS IS" basis,
+WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
+specific language governing rights and limitations under the License.
+
+A source code version of the SeaMonkey program is available to you from:
+http://www.seamonkey-project.org/releases/1.0.1
+
+
+APPENDIX D
+
+LATTICE SEMICONDUCTOR CORPORATION OPEN SOURCE LICENSE AGREEMENT
+
+This is a legal agreement between You (Licensee, either a company or an
+individual), and Lattice Semiconductor Corporation, the Provider (Licensor)
+of the Software. If a component covered by this Agreement can be
+included in the output files generated by the Provider's LatticeMico
+System or any other Provider source code generation tool, then Software
+refers to such output files that includes that component. Otherwise,
+Software refers to the component on a standalone basis. By
+proceeding with the installation, modification, use or distribution in whole
+or in part of Software that identifies itself as licensed under the Lattice
+Semiconductor Corporation Open Source License Agreement, You agree to be
+bound by the terms of this Agreement. If You do not agree to the terms of this
+Agreement, You are not permitted to use, modify or distribute the Software.
+
+1. The Provider grants to You a personal, non-exclusive right to use and
+distribute the source code of the Software provided that:
+ - You make distributions free of charge under these license terms
+ - You ensure that the original copyright notices and limitations of liability
+and warranty sections remain intact.
+
+2. The Provider grants to You a personal, non-exclusive right to modify the
+source code of the Software and incorporate it with other source code to
+create a Derivative Work (as defined below). At Your discretion, You may
+distribute this Derivative Work under terms of Your choosing provided:
+ - You arrange Your design such that the Derivative Work is an identifiable
+module within Your overall design.
+ - You distribute the source code associated with the modules containing the
+Derivative Work in a customarily accepted machine-readable format, free of
+charge under a license agreement that contains these license terms.
+ - You ensure that the original copyright notices and limitations of liability
+and warranty sections remain intact.
+ - You clearly identify areas of the source code that You have modified.
+
+"Derivative Work" means a version of the Software in source code form that
+contains modifications or additions to the original source code and includes all
+Software files used to implement Your design. Derivative Work does not include
+identifiable modules within Your design that are not derived from the Software
+and that can be reasonably considered independent and separate modules from
+the Software.
+
+3. The Provider grants to You a personal, non-exclusive right to use object
+code created from the Software or a Derivative Work to physically implement
+the design in devices such as a programmable logic devices or application
+specific integrated circuits. You may distribute these devices without
+accompanying them with a copy of this license or source code.
+
+4. This Software is provided free of charge. IN NO EVENT WILL THE PROVIDER
+OR ANY OF ITS SUPPLIERS BE LIABLE TO YOU OR ANY OTHER PERSON FOR ANY
+DAMAGES, INCLUDING ANY DIRECT, INDIRECT, INCIDENTAL, CONSEQUENTIAL, OR
+SPECIAL DAMAGES, WHETHER CHARACTERIZED AS EXPENSES, LOST PROFITS, LOST
+SAVINGS, OR OTHER DAMAGES OF ANY SORT, ARISING OUT OF THE USE OF OR INABILITY
+TO USE THE SOFTWARE, EVEN IF THE PROVIDER HAS BEEN ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGES.
+
+5. THE PROVIDER MAKES NO WARRANTIES WITH RESPECT TO THE SOFTWARE, WHETHER
+EXPRESSED, IMPLIED, STATUTORY, OR IN ANY OTHER PROVISION OF THIS AGREEMENT OR
+COMMUNICATION WITH YOU, AND THE PROVIDER SPECIFICALLY DISCLAIMS ANY IMPLIED
+WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR
+NON-INFRINGEMENT OF THIRD PARTY RIGHTS. THE PROVIDER DOES NOT WARRANT THAT USE
+OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR FREE. YOU ASSUME RESPONSIBILITY
+FOR SELECTION OF THE SOFTWARE TO ACHIEVE ITS INTENDED RESULTS AND FOR THE
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+WITH THE SOFTWARE ARE SET FORTH ABOVE.
+
+6. Export Control. You agree that neither the Software nor any Derivative
+Work will be exported, directly or indirectly, into any country or to any
+person or entity, in violation of laws or regulations of the United States
+government. This Agreement will be governed by the substantive laws of the
+State of Oregon, USA.
+
+7. Default and Termination. This Agreement will continue indefinitely, until
+and unless terminated. You may terminate this Agreement by destroying all
+copies of the materials to which this Agreement applies. The Agreement will
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+fail to perform any of Your obligations hereunder. In the event of termination,
+others that have received software from You under the terms of this Agreement
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+this Agreement.
+
+8. Your use of this Software is governed by this Lattice Semiconductor
+Corporation Open Source License Agreement. However, depending on your design,
+the output files generated by the LatticeMico System or by any
+other Provider source code generation tool may contain open
+source code provided by a third party. Specifically, the output files may
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+
+9. From time to time Lattice Semiconductor Corporation may issue revised
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+
+10. Any conflict between the terms of this Agreement and the licensing terms
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+
+(c)2006-2011 Lattice Semiconductor Corporation. You may freely distribute
+the text of this Agreement provided you include this copyright notice.
+However, modifications to the substantive terms herein are not permitted.
2 README
@@ -0,0 +1,2 @@
+Based on LatticeMico32 core from mico32_72_linux.tar.
+(LatticeMico32 v3.3)
42 rtl/JTAGB.v
@@ -0,0 +1,42 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : JTAGB.v
+// Title : JTAGB Black Box
+// Dependencies : None
+// Version : 6.0.14
+// : Initial Release
+// Version : 7.0SP2, 3.0
+// : No Change
+// Version : 3.1
+// : No Change
+// =============================================================================
+module JTAGB (
+ output JTCK,
+ output JRTI1,
+ output JRTI2,
+ output JTDI,
+ output JSHIFT,
+ output JUPDATE,
+ output JRSTN,
+ output JCE1,
+ output JCE2,
+ input JTDO1,
+ input JTDO2
+ ) /*synthesis syn_black_box */;
+
+endmodule
230 rtl/er1.v
@@ -0,0 +1,230 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : er1.v
+// Description:
+// This module is where the ER1 register implemented. ER1 and ER2 registers
+// can be registers implemented in Lattice FPGAs using normal FPGA's
+// programmable logic resources. Once they are implemented, they can be
+// accessed as if they are JTAG data registers through the FPGA JTAG port.
+// In order to accessing these registers, JTAG instructions ER1(0x32) or
+// ER2(0x38) needs to be written to the JTAG IR register for enabling the
+// ER1/ER2 accessing logic. The ER1 or ER2 accessing logic can only be
+// enabled one at a time. Once they are enabled, they will be disabled if
+// another JTAG instruction is written into the JTAG instruction register.
+// The registers allow dynamically accessing the FPGA internal information
+// even when the device is running. Therefore, they are very useful for some
+// of the IP cores. In order to let ER1/ER2 registers shared by multiple IP
+// cores or other designs, there is a ER1/ER2 structure patterned by Lattice.
+// The ER1/ER2 structure allows only one ER1 register but more than one ER2
+// registers in an FPGA device. Please refer to the related document for
+// this patterned ER1/ER2 structure.
+// Dependencies : None
+// Version : 6.0.14
+// : Initial Version
+// Version : 7.0SP2, 3.0
+// : No Change
+// Version : 3.1
+// : No Change
+// =============================================================================
+module ER1 (input JTCK,
+ input JTDI,
+ output JTDO1,
+ output reg JTDO2,
+ input JSHIFT,
+ input JUPDATE,
+ input JRSTN,
+ input JCE1,
+ input [14:0] ER2_TDO,
+ output reg [14:0] IP_ENABLE,
+ input ISPTRACY_ER2_TDO,
+ output ISPTRACY_ENABLE,
+ output CONTROL_DATAN)/* synthesis syn_hier = hard */;
+
+
+ wire controlDataNBit;
+ wire ispTracyEnableBit;
+ wire [3:0] encodedIpEnableBits;
+ wire [9:0] er1TdiBit;
+ wire captureDrER1;
+
+
+ assign JTDO1 = er1TdiBit[0];
+
+ TYPEB BIT0 (.CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(JCE1),
+ .TDI(er1TdiBit[1]),
+ .TDO(er1TdiBit[0]),
+ .DATA_IN(1'b0),
+ .CAPTURE_DR(captureDrER1));
+
+ TYPEB BIT1 (.CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(JCE1),
+ .TDI(er1TdiBit[2]),
+ .TDO(er1TdiBit[1]),
+ .DATA_IN(1'b0),
+ .CAPTURE_DR(captureDrER1));
+
+ TYPEB BIT2 (.CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(JCE1),
+ .TDI(er1TdiBit[3]),
+ .TDO(er1TdiBit[2]),
+ .DATA_IN(1'b1),
+ .CAPTURE_DR(captureDrER1));
+
+ TYPEA BIT3 (.CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(JCE1),
+ .TDI(er1TdiBit[4]),
+ .TDO(er1TdiBit[3]),
+ .DATA_OUT(controlDataNBit),
+ .DATA_IN(controlDataNBit),
+ .CAPTURE_DR(captureDrER1),
+ .UPDATE_DR(JUPDATE));
+
+ assign CONTROL_DATAN = controlDataNBit;
+
+ TYPEA BIT4 (.CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(JCE1),
+ .TDI(er1TdiBit[5]),
+ .TDO(er1TdiBit[4]),
+ .DATA_OUT(ispTracyEnableBit),
+ .DATA_IN(ispTracyEnableBit),
+ .CAPTURE_DR(captureDrER1),
+ .UPDATE_DR(JUPDATE)
+ );
+
+ assign ISPTRACY_ENABLE = ispTracyEnableBit;
+
+ TYPEA BIT5 (.CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(JCE1),
+ .TDI(er1TdiBit[6]),
+ .TDO(er1TdiBit[5]),
+ .DATA_OUT(encodedIpEnableBits[0]),
+ .DATA_IN(encodedIpEnableBits[0]),
+ .CAPTURE_DR(captureDrER1),
+ .UPDATE_DR(JUPDATE));
+
+ TYPEA BIT6 (.CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(JCE1),
+ .TDI(er1TdiBit[7]),
+ .TDO(er1TdiBit[6]),
+ .DATA_OUT(encodedIpEnableBits[1]),
+ .DATA_IN(encodedIpEnableBits[1]),
+ .CAPTURE_DR(captureDrER1),
+ .UPDATE_DR(JUPDATE));
+
+ TYPEA BIT7 (.CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(JCE1),
+ .TDI(er1TdiBit[8]),
+ .TDO(er1TdiBit[7]),
+ .DATA_OUT(encodedIpEnableBits[2]),
+ .DATA_IN(encodedIpEnableBits[2]),
+ .CAPTURE_DR(captureDrER1),
+ .UPDATE_DR(JUPDATE));
+
+ TYPEA BIT8 (.CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(JCE1),
+ .TDI(er1TdiBit[9]),
+ .TDO(er1TdiBit[8]),
+ .DATA_OUT(encodedIpEnableBits[3]),
+ .DATA_IN(encodedIpEnableBits[3]),
+ .CAPTURE_DR(captureDrER1),
+ .UPDATE_DR(JUPDATE)
+ );
+
+ assign er1TdiBit[9] = JTDI;
+ assign captureDrER1 = !JSHIFT & JCE1;
+
+ always @ (encodedIpEnableBits,ISPTRACY_ER2_TDO, ER2_TDO)
+ begin
+ case (encodedIpEnableBits)
+ 4'h0: begin
+ IP_ENABLE <= 15'b000000000000000;
+ JTDO2 <= ISPTRACY_ER2_TDO;
+ end
+ 4'h1: begin
+ IP_ENABLE <= 15'b000000000000001;
+ JTDO2 <= ER2_TDO[0];
+ end
+ 4'h2: begin
+ IP_ENABLE <= 15'b000000000000010;
+ JTDO2 <= ER2_TDO[1];
+ end
+ 4'h3: begin
+ IP_ENABLE <= 15'b000000000000100;
+ JTDO2 <= ER2_TDO[2];
+ end
+ 4'h4: begin
+ IP_ENABLE <= 15'b000000000001000;
+ JTDO2 <= ER2_TDO[3];
+ end
+ 4'h5: begin
+ IP_ENABLE <= 15'b000000000010000;
+ JTDO2 <= ER2_TDO[4];
+ end
+ 4'h6: begin
+ IP_ENABLE <= 15'b000000000100000;
+ JTDO2 <= ER2_TDO[5];
+ end
+ 4'h7: begin
+ IP_ENABLE <= 15'b000000001000000;
+ JTDO2 <= ER2_TDO[6];
+ end
+ 4'h8: begin
+ IP_ENABLE <= 15'b000000010000000;
+ JTDO2 <= ER2_TDO[7];
+ end
+ 4'h9: begin
+ IP_ENABLE <= 15'b000000100000000;
+ JTDO2 <= ER2_TDO[8];
+ end
+ 4'hA: begin
+ IP_ENABLE <= 15'b000001000000000;
+ JTDO2 <= ER2_TDO[9];
+ end
+ 4'hB: begin
+ IP_ENABLE <= 15'b000010000000000;
+ JTDO2 <= ER2_TDO[10];
+ end
+ 4'hC: begin
+ IP_ENABLE <= 15'b000100000000000;
+ JTDO2 <= ER2_TDO[11];
+ end
+ 4'hD: begin
+ IP_ENABLE <= 15'b001000000000000;
+ JTDO2 <= ER2_TDO[12];
+ end
+ 4'hE: begin
+ IP_ENABLE <= 15'b010000000000000;
+ JTDO2 <= ER2_TDO[13];
+ end
+ 4'hF: begin
+ IP_ENABLE <= 15'b100000000000000;
+ JTDO2 <= ER2_TDO[14];
+ end
+ endcase
+ end
+endmodule
125 rtl/jtag_cores.v
@@ -0,0 +1,125 @@
+// ============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// ============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : jtag_cores.v
+// Title : Instantiates all IP cores on JTAG chain.
+// Dependencies : system_conf.v
+// Version : 6.0.14
+// : modified to use jtagconn for LM32,
+// : all technologies 7/10/07
+// Version : 7.0SP2, 3.0
+// : No Change
+// Version : 3.1
+// : No Change
+// ============================================================================
+
+`include "system_conf.v"
+
+/////////////////////////////////////////////////////
+// jtagconn16 Module Definition
+/////////////////////////////////////////////////////
+
+module jtagconn16 (er2_tdo, jtck, jtdi, jshift, jupdate, jrstn, jce2, ip_enable) ;
+ input er2_tdo ;
+ output jtck ;
+ output jtdi ;
+ output jshift ;
+ output jupdate ;
+ output jrstn ;
+ output jce2 ;
+ output ip_enable ;
+endmodule
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+(* syn_hier="hard" *) module jtag_cores (
+ // ----- Inputs -------
+ reg_d,
+ reg_addr_d,
+ // ----- Outputs -------
+ reg_update,
+ reg_q,
+ reg_addr_q,
+ jtck,
+ jrstn
+ );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input [7:0] reg_d;
+input [2:0] reg_addr_d;
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output reg_update;
+wire reg_update;
+output [7:0] reg_q;
+wire [7:0] reg_q;
+output [2:0] reg_addr_q;
+wire [2:0] reg_addr_q;
+
+output jtck;
+wire jtck; /* synthesis syn_keep=1 */
+output jrstn;
+wire jrstn; /* synthesis syn_keep=1 */
+
+/////////////////////////////////////////////////////
+// Instantiations
+/////////////////////////////////////////////////////
+
+wire jtdi; /* synthesis syn_keep=1 */
+wire er2_tdo2; /* synthesis syn_keep=1 */
+wire jshift; /* synthesis syn_keep=1 */
+wire jupdate; /* synthesis syn_keep=1 */
+wire jce2; /* synthesis syn_keep=1 */
+wire ip_enable; /* synthesis syn_keep=1 */
+
+(* JTAG_IP="LM32", IP_ID="0", HUB_ID="0", syn_noprune=1 *) jtagconn16 jtagconn16_lm32_inst (
+ .er2_tdo (er2_tdo2),
+ .jtck (jtck),
+ .jtdi (jtdi),
+ .jshift (jshift),
+ .jupdate (jupdate),
+ .jrstn (jrstn),
+ .jce2 (jce2),
+ .ip_enable (ip_enable)
+);
+
+(* syn_noprune=1 *) jtag_lm32 jtag_lm32_inst (
+ .JTCK (jtck),
+ .JTDI (jtdi),
+ .JTDO2 (er2_tdo2),
+ .JSHIFT (jshift),
+ .JUPDATE (jupdate),
+ .JRSTN (jrstn),
+ .JCE2 (jce2),
+ .JTAGREG_ENABLE (ip_enable),
+ .CONTROL_DATAN (),
+ .REG_UPDATE (reg_update),
+ .REG_D (reg_d),
+ .REG_ADDR_D (reg_addr_d),
+ .REG_Q (reg_q),
+ .REG_ADDR_Q (reg_addr_q)
+ );
+
+endmodule
200 rtl/jtag_lm32.v
@@ -0,0 +1,200 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : jtag_lm32.v
+// Title : JTAG data register for LM32 CPU debug interface
+// Version : 6.0.13
+// : Initial Release
+// Version : 7.0SP2, 3.0
+// : No Change
+// Version : 3.1
+// : No Change
+// =============================================================================
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module jtag_lm32 (
+ input JTCK,
+ input JTDI,
+ output JTDO2,
+ input JSHIFT,
+ input JUPDATE,
+ input JRSTN,
+ input JCE2,
+ input JTAGREG_ENABLE,
+ input CONTROL_DATAN,
+ output REG_UPDATE,
+ input [7:0] REG_D,
+ input [2:0] REG_ADDR_D,
+ output [7:0] REG_Q,
+ output [2:0] REG_ADDR_Q
+ );
+
+/////////////////////////////////////////////////////
+// Internal nets and registers
+/////////////////////////////////////////////////////
+
+wire [9:0] tdibus;
+
+/////////////////////////////////////////////////////
+// Instantiations
+/////////////////////////////////////////////////////
+
+TYPEA DATA_BIT0 (
+ .CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(clk_enable),
+ .TDI(JTDI),
+ .TDO(tdibus[0]),
+ .DATA_OUT(REG_Q[0]),
+ .DATA_IN(REG_D[0]),
+ .CAPTURE_DR(captureDr),
+ .UPDATE_DR(JUPDATE)
+ );
+
+TYPEA DATA_BIT1 (
+ .CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(clk_enable),
+ .TDI(tdibus[0]),
+ .TDO(tdibus[1]),
+ .DATA_OUT(REG_Q[1]),
+ .DATA_IN(REG_D[1]),
+ .CAPTURE_DR(captureDr),
+ .UPDATE_DR(JUPDATE)
+ );
+
+TYPEA DATA_BIT2 (
+ .CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(clk_enable),
+ .TDI(tdibus[1]),
+ .TDO(tdibus[2]),
+ .DATA_OUT(REG_Q[2]),
+ .DATA_IN(REG_D[2]),
+ .CAPTURE_DR(captureDr),
+ .UPDATE_DR(JUPDATE)
+ );
+
+TYPEA DATA_BIT3 (
+ .CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(clk_enable),
+ .TDI(tdibus[2]),
+ .TDO(tdibus[3]),
+ .DATA_OUT(REG_Q[3]),
+ .DATA_IN(REG_D[3]),
+ .CAPTURE_DR(captureDr),
+ .UPDATE_DR(JUPDATE)
+ );
+
+TYPEA DATA_BIT4 (
+ .CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(clk_enable),
+ .TDI(tdibus[3]),
+ .TDO(tdibus[4]),
+ .DATA_OUT(REG_Q[4]),
+ .DATA_IN(REG_D[4]),
+ .CAPTURE_DR(captureDr),
+ .UPDATE_DR(JUPDATE)
+ );
+
+TYPEA DATA_BIT5 (
+ .CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(clk_enable),
+ .TDI(tdibus[4]),
+ .TDO(tdibus[5]),
+ .DATA_OUT(REG_Q[5]),
+ .DATA_IN(REG_D[5]),
+ .CAPTURE_DR(captureDr),
+ .UPDATE_DR(JUPDATE)
+ );
+
+TYPEA DATA_BIT6 (
+ .CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(clk_enable),
+ .TDI(tdibus[5]),
+ .TDO(tdibus[6]),
+ .DATA_OUT(REG_Q[6]),
+ .DATA_IN(REG_D[6]),
+ .CAPTURE_DR(captureDr),
+ .UPDATE_DR(JUPDATE)
+ );
+
+TYPEA DATA_BIT7 (
+ .CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(clk_enable),
+ .TDI(tdibus[6]),
+ .TDO(tdibus[7]),
+ .DATA_OUT(REG_Q[7]),
+ .DATA_IN(REG_D[7]),
+ .CAPTURE_DR(captureDr),
+ .UPDATE_DR(JUPDATE)
+ );
+
+TYPEA ADDR_BIT0 (
+ .CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(clk_enable),
+ .TDI(tdibus[7]),
+ .TDO(tdibus[8]),
+ .DATA_OUT(REG_ADDR_Q[0]),
+ .DATA_IN(REG_ADDR_D[0]),
+ .CAPTURE_DR(captureDr),
+ .UPDATE_DR(JUPDATE)
+ );
+
+TYPEA ADDR_BIT1 (
+ .CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(clk_enable),
+ .TDI(tdibus[8]),
+ .TDO(tdibus[9]),
+ .DATA_OUT(REG_ADDR_Q[1]),
+ .DATA_IN(REG_ADDR_D[1]),
+ .CAPTURE_DR(captureDr),
+ .UPDATE_DR(JUPDATE)
+ );
+
+TYPEA ADDR_BIT2 (
+ .CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(clk_enable),
+ .TDI(tdibus[9]),
+ .TDO(JTDO2),
+ .DATA_OUT(REG_ADDR_Q[2]),
+ .DATA_IN(REG_ADDR_D[2]),
+ .CAPTURE_DR(captureDr),
+ .UPDATE_DR(JUPDATE)
+ );
+
+/////////////////////////////////////////////////////
+// Combinational logic
+/////////////////////////////////////////////////////
+
+assign clk_enable = JTAGREG_ENABLE & JCE2;
+assign captureDr = !JSHIFT & JCE2;
+// JCE2 is only active during shift
+assign REG_UPDATE = JTAGREG_ENABLE & JUPDATE;
+
+endmodule
115 rtl/lm32_adder.v
@@ -0,0 +1,115 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// ============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm32_adder.v
+// Title : Integer adder / subtractor with comparison flag generation
+// Dependencies : lm32_include.v
+// Version : 6.1.17
+// : Initial Release
+// Version : 7.0SP2, 3.0
+// : No Change
+// Version : 3.1
+// : No Change
+// =============================================================================
+
+`include "lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_adder (
+ // ----- Inputs -------
+ adder_op_x,
+ adder_op_x_n,
+ operand_0_x,
+ operand_1_x,
+ // ----- Outputs -------
+ adder_result_x,
+ adder_carry_n_x,
+ adder_overflow_x
+ );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input adder_op_x; // Operating to perform, 0 for addition, 1 for subtraction
+input adder_op_x_n; // Inverted version of adder_op_x
+input [`LM32_WORD_RNG] operand_0_x; // Operand to add, or subtract from
+input [`LM32_WORD_RNG] operand_1_x; // Opearnd to add, or subtract by
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output [`LM32_WORD_RNG] adder_result_x; // Result of addition or subtraction
+wire [`LM32_WORD_RNG] adder_result_x;
+output adder_carry_n_x; // Inverted carry
+wire adder_carry_n_x;
+output adder_overflow_x; // Indicates if overflow occured, only valid for subtractions
+reg adder_overflow_x;
+
+/////////////////////////////////////////////////////
+// Internal nets and registers
+/////////////////////////////////////////////////////
+
+wire a_sign; // Sign (i.e. positive or negative) of operand 0
+wire b_sign; // Sign of operand 1
+wire result_sign; // Sign of result
+
+/////////////////////////////////////////////////////
+// Instantiations
+/////////////////////////////////////////////////////
+
+lm32_addsub addsub (
+ // ----- Inputs -----
+ .DataA (operand_0_x),
+ .DataB (operand_1_x),
+ .Cin (adder_op_x),
+ .Add_Sub (adder_op_x_n),
+ // ----- Ouputs -----
+ .Result (adder_result_x),
+ .Cout (adder_carry_n_x)
+ );
+
+/////////////////////////////////////////////////////
+// Combinational Logic
+/////////////////////////////////////////////////////
+
+// Extract signs of operands and result
+
+assign a_sign = operand_0_x[`LM32_WORD_WIDTH-1];
+assign b_sign = operand_1_x[`LM32_WORD_WIDTH-1];
+assign result_sign = adder_result_x[`LM32_WORD_WIDTH-1];
+
+// Determine whether an overflow occured when performing a subtraction
+
+always @(*)
+begin
+ // +ve - -ve = -ve -> overflow
+ // -ve - +ve = +ve -> overflow
+ if ( (!a_sign & b_sign & result_sign)
+ || (a_sign & !b_sign & !result_sign)
+ )
+ adder_overflow_x = `TRUE;
+ else
+ adder_overflow_x = `FALSE;
+end
+
+endmodule
+
74 rtl/lm32_addsub.v
@@ -0,0 +1,74 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm32_addsub.v
+// Title : PMI adder/subtractor.
+// Version : 6.1.17
+// : Initial Release
+// Version : 7.0SP2, 3.0
+// : No Change
+// Version : 3.1
+// : No Change
+// =============================================================================
+
+`include "lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_addsub (
+ // ----- Inputs -------
+ DataA,
+ DataB,
+ Cin,
+ Add_Sub,
+ // ----- Outputs -------
+ Result,
+ Cout
+ );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input [31:0] DataA;
+input [31:0] DataB;
+input Cin;
+input Add_Sub;
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output [31:0] Result;
+wire [31:0] Result;
+output Cout;
+wire Cout;
+
+/////////////////////////////////////////////////////
+// Instantiations
+/////////////////////////////////////////////////////
+
+// Modified for Milkymist: removed non-portable instantiated block
+ wire [32:0] tmp_addResult = DataA + DataB + Cin;
+ wire [32:0] tmp_subResult = DataA - DataB - !Cin;
+
+ assign Result = (Add_Sub == 1) ? tmp_addResult[31:0] : tmp_subResult[31:0];
+ assign Cout = (Add_Sub == 1) ? tmp_addResult[32] : !tmp_subResult[32];
+
+endmodule
2,714 rtl/lm32_cpu.v
@@ -0,0 +1,2714 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm32_cpu.v
+// Title : Top-level of CPU.
+// Dependencies : lm32_include.v
+//
+// Version 3.3
+// 1. Feature: Support for memory that is tightly coupled to processor core, and
+// has a single-cycle access latency (same as caches). Instruction port has
+// access to a dedicated physically-mapped memory. Data port has access to
+// a dedicated physically-mapped memory. In order to be able to manipulate
+// values in both these memories via the debugger, these memories also
+// interface with the data port of LM32.
+// 2. Feature: Extended Configuration Register
+// 3. Bug Fix: Removed port names that conflict with keywords reserved in System-
+// Verilog.
+//
+// Version 3.2
+// 1. Bug Fix: Single-stepping a load/store to invalid address causes debugger to
+// hang. At the same time CPU fails to register data bus error exception. Bug
+// is caused because (a) data bus error exception occurs after load/store has
+// passed X stage and next sequential instruction (e.g., brk) is already in X
+// stage, and (b) data bus error exception had lower priority than, say, brk
+// exception.
+// 2. Bug Fix: If a brk (or scall/eret/bret) sequentially follows a load/store to
+// invalid location, CPU will fail to register data bus error exception. The
+// solution is to stall scall/eret/bret/brk instructions in D pipeline stage
+// until load/store has completed.
+// 3. Feature: Enable precise identification of load/store that causes seg fault.
+// 4. SYNC resets used for register file when implemented in EBRs.
+//
+// Version 3.1
+// 1. Feature: LM32 Register File can now be mapped in to on-chip block RAM (EBR)
+// instead of distributed memory by enabling the option in LM32 GUI.
+// 2. Feature: LM32 also adds a static branch predictor to improve branch
+// performance. All immediate-based forward-pointing branches are predicted
+// not-taken. All immediate-based backward-pointing branches are predicted taken.
+//
+// Version 7.0SP2, 3.0
+// No Change
+//
+// Version 6.1.17
+// Initial Release
+// =============================================================================
+
+`include "lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_cpu (
+ // ----- Inputs -------
+ clk_i,
+`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
+ clk_n_i,
+`endif
+ rst_i,
+ // From external devices
+`ifdef CFG_INTERRUPTS_ENABLED
+ interrupt_n,
+`endif
+ // From user logic
+`ifdef CFG_USER_ENABLED
+ user_result,
+ user_complete,
+`endif
+`ifdef CFG_JTAG_ENABLED
+ // From JTAG
+ jtag_clk,
+ jtag_update,
+ jtag_reg_q,
+ jtag_reg_addr_q,
+`endif
+`ifdef CFG_IWB_ENABLED
+ // Instruction Wishbone master
+ I_DAT_I,
+ I_ACK_I,
+ I_ERR_I,
+ I_RTY_I,
+`endif
+ // Data Wishbone master
+ D_DAT_I,
+ D_ACK_I,
+ D_ERR_I,
+ D_RTY_I,
+ // ----- Outputs -------
+`ifdef CFG_TRACE_ENABLED
+ trace_pc,
+ trace_pc_valid,
+ trace_exception,
+ trace_eid,
+ trace_eret,
+`ifdef CFG_DEBUG_ENABLED
+ trace_bret,
+`endif
+`endif
+`ifdef CFG_JTAG_ENABLED
+ jtag_reg_d,
+ jtag_reg_addr_d,
+`endif
+`ifdef CFG_USER_ENABLED
+ user_valid,
+ user_opcode,
+ user_operand_0,
+ user_operand_1,
+`endif
+`ifdef CFG_IWB_ENABLED
+ // Instruction Wishbone master
+ I_DAT_O,
+ I_ADR_O,
+ I_CYC_O,
+ I_SEL_O,
+ I_STB_O,
+ I_WE_O,
+ I_CTI_O,
+ I_LOCK_O,
+ I_BTE_O,
+`endif
+ // Data Wishbone master
+ D_DAT_O,
+ D_ADR_O,
+ D_CYC_O,
+ D_SEL_O,
+ D_STB_O,
+ D_WE_O,
+ D_CTI_O,
+ D_LOCK_O,
+ D_BTE_O
+ );
+
+/////////////////////////////////////////////////////
+// Parameters
+/////////////////////////////////////////////////////
+
+parameter eba_reset = `CFG_EBA_RESET; // Reset value for EBA CSR
+`ifdef CFG_DEBUG_ENABLED
+parameter deba_reset = `CFG_DEBA_RESET; // Reset value for DEBA CSR
+`endif
+
+`ifdef CFG_ICACHE_ENABLED
+parameter icache_associativity = `CFG_ICACHE_ASSOCIATIVITY; // Associativity of the cache (Number of ways)
+parameter icache_sets = `CFG_ICACHE_SETS; // Number of sets
+parameter icache_bytes_per_line = `CFG_ICACHE_BYTES_PER_LINE; // Number of bytes per cache line
+parameter icache_base_address = `CFG_ICACHE_BASE_ADDRESS; // Base address of cachable memory
+parameter icache_limit = `CFG_ICACHE_LIMIT; // Limit (highest address) of cachable memory
+`else
+parameter icache_associativity = 1;
+parameter icache_sets = 512;
+parameter icache_bytes_per_line = 16;
+parameter icache_base_address = 0;
+parameter icache_limit = 0;
+`endif
+
+`ifdef CFG_DCACHE_ENABLED
+parameter dcache_associativity = `CFG_DCACHE_ASSOCIATIVITY; // Associativity of the cache (Number of ways)
+parameter dcache_sets = `CFG_DCACHE_SETS; // Number of sets
+parameter dcache_bytes_per_line = `CFG_DCACHE_BYTES_PER_LINE; // Number of bytes per cache line
+parameter dcache_base_address = `CFG_DCACHE_BASE_ADDRESS; // Base address of cachable memory
+parameter dcache_limit = `CFG_DCACHE_LIMIT; // Limit (highest address) of cachable memory
+`else
+parameter dcache_associativity = 1;
+parameter dcache_sets = 512;
+parameter dcache_bytes_per_line = 16;
+parameter dcache_base_address = 0;
+parameter dcache_limit = 0;
+`endif
+
+`ifdef CFG_DEBUG_ENABLED
+parameter watchpoints = `CFG_WATCHPOINTS; // Number of h/w watchpoint CSRs
+`else
+parameter watchpoints = 0;
+`endif
+`ifdef CFG_ROM_DEBUG_ENABLED
+parameter breakpoints = `CFG_BREAKPOINTS; // Number of h/w breakpoint CSRs
+`else
+parameter breakpoints = 0;
+`endif
+
+`ifdef CFG_INTERRUPTS_ENABLED
+parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts
+`else
+parameter interrupts = 0;
+`endif
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input clk_i; // Clock
+`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
+input clk_n_i; // Inverted clock
+`endif
+input rst_i; // Reset
+
+`ifdef CFG_INTERRUPTS_ENABLED
+input [`LM32_INTERRUPT_RNG] interrupt_n; // Interrupt pins, active-low
+`endif
+
+`ifdef CFG_USER_ENABLED
+input [`LM32_WORD_RNG] user_result; // User-defined instruction result
+input user_complete; // User-defined instruction execution is complete
+`endif
+
+`ifdef CFG_JTAG_ENABLED
+input jtag_clk; // JTAG clock
+input jtag_update; // JTAG state machine is in data register update state
+input [`LM32_BYTE_RNG] jtag_reg_q;
+input [2:0] jtag_reg_addr_q;
+`endif
+
+`ifdef CFG_IWB_ENABLED
+input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data
+input I_ACK_I; // Instruction Wishbone interface acknowledgement
+input I_ERR_I; // Instruction Wishbone interface error
+input I_RTY_I; // Instruction Wishbone interface retry
+`endif
+
+input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
+input D_ACK_I; // Data Wishbone interface acknowledgement
+input D_ERR_I; // Data Wishbone interface error
+input D_RTY_I; // Data Wishbone interface retry
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+`ifdef CFG_TRACE_ENABLED
+output [`LM32_PC_RNG] trace_pc; // PC to trace
+reg [`LM32_PC_RNG] trace_pc;
+output trace_pc_valid; // Indicates that a new trace PC is valid
+reg trace_pc_valid;
+output trace_exception; // Indicates an exception has occured
+reg trace_exception;
+output [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured
+reg [`LM32_EID_RNG] trace_eid;
+output trace_eret; // Indicates an eret instruction has been executed
+reg trace_eret;
+`ifdef CFG_DEBUG_ENABLED
+output trace_bret; // Indicates a bret instruction has been executed
+reg trace_bret;
+`endif
+`endif
+
+`ifdef CFG_JTAG_ENABLED
+output [`LM32_BYTE_RNG] jtag_reg_d;
+wire [`LM32_BYTE_RNG] jtag_reg_d;
+output [2:0] jtag_reg_addr_d;
+wire [2:0] jtag_reg_addr_d;
+`endif
+
+`ifdef CFG_USER_ENABLED
+output user_valid; // Indicates if user_opcode is valid
+wire user_valid;
+output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode
+reg [`LM32_USER_OPCODE_RNG] user_opcode;
+output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction
+wire [`LM32_WORD_RNG] user_operand_0;
+output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction
+wire [`LM32_WORD_RNG] user_operand_1;
+`endif
+
+`ifdef CFG_IWB_ENABLED
+output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data
+wire [`LM32_WORD_RNG] I_DAT_O;
+output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address
+wire [`LM32_WORD_RNG] I_ADR_O;
+output I_CYC_O; // Instruction Wishbone interface cycle
+wire I_CYC_O;
+output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select
+wire [`LM32_BYTE_SELECT_RNG] I_SEL_O;
+output I_STB_O; // Instruction Wishbone interface strobe
+wire I_STB_O;
+output I_WE_O; // Instruction Wishbone interface write enable
+wire I_WE_O;
+output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type
+wire [`LM32_CTYPE_RNG] I_CTI_O;
+output I_LOCK_O; // Instruction Wishbone interface lock bus
+wire I_LOCK_O;
+output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type
+wire [`LM32_BTYPE_RNG] I_BTE_O;
+`endif
+
+output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
+wire [`LM32_WORD_RNG] D_DAT_O;
+output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
+wire [`LM32_WORD_RNG] D_ADR_O;
+output D_CYC_O; // Data Wishbone interface cycle
+wire D_CYC_O;
+output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select
+wire [`LM32_BYTE_SELECT_RNG] D_SEL_O;
+output D_STB_O; // Data Wishbone interface strobe
+wire D_STB_O;
+output D_WE_O; // Data Wishbone interface write enable
+wire D_WE_O;
+output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type
+wire [`LM32_CTYPE_RNG] D_CTI_O;
+output D_LOCK_O; // Date Wishbone interface lock bus
+wire D_LOCK_O;
+output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
+wire [`LM32_BTYPE_RNG] D_BTE_O;
+
+/////////////////////////////////////////////////////
+// Internal nets and registers
+/////////////////////////////////////////////////////
+
+// Pipeline registers
+
+`ifdef LM32_CACHE_ENABLED
+reg valid_a; // Instruction in A stage is valid
+`endif
+reg valid_f; // Instruction in F stage is valid
+reg valid_d; // Instruction in D stage is valid
+reg valid_x; // Instruction in X stage is valid
+reg valid_m; // Instruction in M stage is valid
+reg valid_w; // Instruction in W stage is valid
+
+wire q_x;
+wire [`LM32_WORD_RNG] immediate_d; // Immediate operand
+wire load_d; // Indicates a load instruction
+reg load_x;
+reg load_m;
+wire load_q_x;
+wire store_q_x;
+wire store_d; // Indicates a store instruction
+reg store_x;
+reg store_m;
+wire [`LM32_SIZE_RNG] size_d; // Size of load/store (byte, hword, word)
+reg [`LM32_SIZE_RNG] size_x;
+wire branch_d; // Indicates a branch instruction
+wire branch_predict_d; // Indicates a branch is predicted
+wire branch_predict_taken_d; // Indicates a branch is predicted taken
+wire [`LM32_PC_RNG] branch_predict_address_d; // Address to which predicted branch jumps
+wire [`LM32_PC_RNG] branch_target_d;
+wire bi_unconditional;
+wire bi_conditional;
+reg branch_x;
+reg branch_predict_x;
+reg branch_predict_taken_x;
+reg branch_m;
+reg branch_predict_m;
+reg branch_predict_taken_m;
+wire branch_mispredict_taken_m; // Indicates a branch was mispredicted as taken
+wire branch_flushX_m; // Indicates that instruction in X stage must be squashed
+wire branch_reg_d; // Branch to register or immediate
+wire [`LM32_PC_RNG] branch_offset_d; // Branch offset for immediate branches
+reg [`LM32_PC_RNG] branch_target_x; // Address to branch to
+reg [`LM32_PC_RNG] branch_target_m;
+wire [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0_d; // Which result should be selected in D stage for operand 0
+wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be selected in D stage for operand 1
+
+wire x_result_sel_csr_d; // Select X stage result from CSRs
+reg x_result_sel_csr_x;
+`ifdef LM32_MC_ARITHMETIC_ENABLED
+wire x_result_sel_mc_arith_d; // Select X stage result from multi-cycle arithmetic unit
+reg x_result_sel_mc_arith_x;
+`endif
+`ifdef LM32_NO_BARREL_SHIFT
+wire x_result_sel_shift_d; // Select X stage result from shifter
+reg x_result_sel_shift_x;
+`endif
+`ifdef CFG_SIGN_EXTEND_ENABLED
+wire x_result_sel_sext_d; // Select X stage result from sign-extend logic
+reg x_result_sel_sext_x;
+`endif
+wire x_result_sel_logic_d; // Select X stage result from logic op unit
+reg x_result_sel_logic_x;
+`ifdef CFG_USER_ENABLED
+wire x_result_sel_user_d; // Select X stage result from user-defined logic
+reg x_result_sel_user_x;
+`endif
+wire x_result_sel_add_d; // Select X stage result from adder
+reg x_result_sel_add_x;
+wire m_result_sel_compare_d; // Select M stage result from comparison logic
+reg m_result_sel_compare_x;
+reg m_result_sel_compare_m;
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+wire m_result_sel_shift_d; // Select M stage result from shifter
+reg m_result_sel_shift_x;
+reg m_result_sel_shift_m;
+`endif
+wire w_result_sel_load_d; // Select W stage result from load/store unit
+reg w_result_sel_load_x;
+reg w_result_sel_load_m;
+reg w_result_sel_load_w;
+`ifdef CFG_PL_MULTIPLY_ENABLED
+wire w_result_sel_mul_d; // Select W stage result from multiplier
+reg w_result_sel_mul_x;
+reg w_result_sel_mul_m;
+reg w_result_sel_mul_w;
+`endif
+wire x_bypass_enable_d; // Whether result is bypassable in X stage
+reg x_bypass_enable_x;
+wire m_bypass_enable_d; // Whether result is bypassable in M stage
+reg m_bypass_enable_x;
+reg m_bypass_enable_m;
+wire sign_extend_d; // Whether to sign-extend or zero-extend
+reg sign_extend_x;
+wire write_enable_d; // Register file write enable
+reg write_enable_x;
+wire write_enable_q_x;
+reg write_enable_m;
+wire write_enable_q_m;
+reg write_enable_w;
+wire write_enable_q_w;
+wire read_enable_0_d; // Register file read enable 0
+wire [`LM32_REG_IDX_RNG] read_idx_0_d; // Register file read index 0
+wire read_enable_1_d; // Register file read enable 1
+wire [`LM32_REG_IDX_RNG] read_idx_1_d; // Register file read index 1
+wire [`LM32_REG_IDX_RNG] write_idx_d; // Register file write index
+reg [`LM32_REG_IDX_RNG] write_idx_x;
+reg [`LM32_REG_IDX_RNG] write_idx_m;
+reg [`LM32_REG_IDX_RNG] write_idx_w;
+wire [`LM32_CSR_RNG] csr_d; // CSR read/write index
+reg [`LM32_CSR_RNG] csr_x;
+wire [`LM32_CONDITION_RNG] condition_d; // Branch condition
+reg [`LM32_CONDITION_RNG] condition_x;
+`ifdef CFG_DEBUG_ENABLED
+wire break_d; // Indicates a break instruction
+reg break_x;
+`endif
+wire scall_d; // Indicates a scall instruction
+reg scall_x;
+wire eret_d; // Indicates an eret instruction
+reg eret_x;
+wire eret_q_x;
+reg eret_m;
+`ifdef CFG_TRACE_ENABLED
+reg eret_w;
+`endif
+`ifdef CFG_DEBUG_ENABLED
+wire bret_d; // Indicates a bret instruction
+reg bret_x;
+wire bret_q_x;
+reg bret_m;
+`ifdef CFG_TRACE_ENABLED
+reg bret_w;
+`endif
+`endif
+wire csr_write_enable_d; // CSR write enable
+reg csr_write_enable_x;
+wire csr_write_enable_q_x;
+`ifdef CFG_USER_ENABLED
+wire [`LM32_USER_OPCODE_RNG] user_opcode_d; // User-defined instruction opcode
+`endif
+
+`ifdef CFG_BUS_ERRORS_ENABLED
+wire bus_error_d; // Indicates an bus error occured while fetching the instruction in this pipeline stage
+reg bus_error_x;
+reg data_bus_error_exception_m;
+reg [`LM32_PC_RNG] memop_pc_w;
+`endif
+
+reg [`LM32_WORD_RNG] d_result_0; // Result of instruction in D stage (operand 0)
+reg [`LM32_WORD_RNG] d_result_1; // Result of instruction in D stage (operand 1)
+reg [`LM32_WORD_RNG] x_result; // Result of instruction in X stage
+reg [`LM32_WORD_RNG] m_result; // Result of instruction in M stage
+reg [`LM32_WORD_RNG] w_result; // Result of instruction in W stage
+
+reg [`LM32_WORD_RNG] operand_0_x; // Operand 0 for X stage instruction
+reg [`LM32_WORD_RNG] operand_1_x; // Operand 1 for X stage instruction
+reg [`LM32_WORD_RNG] store_operand_x; // Data read from register to store
+reg [`LM32_WORD_RNG] operand_m; // Operand for M stage instruction
+reg [`LM32_WORD_RNG] operand_w; // Operand for W stage instruction
+
+// To/from register file
+`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
+reg [`LM32_WORD_RNG] reg_data_live_0;
+reg [`LM32_WORD_RNG] reg_data_live_1;
+reg use_buf; // Whether to use reg_data_live or reg_data_buf
+reg [`LM32_WORD_RNG] reg_data_buf_0;
+reg [`LM32_WORD_RNG] reg_data_buf_1;
+`endif
+`ifdef LM32_EBR_REGISTER_FILE
+`else
+reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1]; // Register file
+`endif
+wire [`LM32_WORD_RNG] reg_data_0; // Register file read port 0 data
+wire [`LM32_WORD_RNG] reg_data_1; // Register file read port 1 data
+reg [`LM32_WORD_RNG] bypass_data_0; // Register value 0 after bypassing
+reg [`LM32_WORD_RNG] bypass_data_1; // Register value 1 after bypassing
+wire reg_write_enable_q_w;
+
+reg interlock; // Indicates pipeline should be stalled because of a read-after-write hazzard
+
+wire stall_a; // Stall instruction in A pipeline stage
+wire stall_f; // Stall instruction in F pipeline stage
+wire stall_d; // Stall instruction in D pipeline stage
+wire stall_x; // Stall instruction in X pipeline stage
+wire stall_m; // Stall instruction in M pipeline stage
+
+// To/from adder
+wire adder_op_d; // Whether to add or subtract
+reg adder_op_x;
+reg adder_op_x_n; // Inverted version of adder_op_x
+wire [`LM32_WORD_RNG] adder_result_x; // Result from adder
+wire adder_overflow_x; // Whether a signed overflow occured
+wire adder_carry_n_x; // Whether a carry was generated
+
+// To/from logical operations unit
+wire [`LM32_LOGIC_OP_RNG] logic_op_d; // Which operation to perform
+reg [`LM32_LOGIC_OP_RNG] logic_op_x;
+wire [`LM32_WORD_RNG] logic_result_x; // Result of logical operation
+
+`ifdef CFG_SIGN_EXTEND_ENABLED
+// From sign-extension unit
+wire [`LM32_WORD_RNG] sextb_result_x; // Result of byte sign-extension
+wire [`LM32_WORD_RNG] sexth_result_x; // Result of half-word sign-extenstion
+wire [`LM32_WORD_RNG] sext_result_x; // Result of sign-extension specified by instruction
+`endif
+
+// To/from shifter
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+`ifdef CFG_ROTATE_ENABLED
+wire rotate_d; // Whether we should rotate or shift
+reg rotate_x;
+`endif
+wire direction_d; // Which direction to shift in
+reg direction_x;
+reg direction_m;
+wire [`LM32_WORD_RNG] shifter_result_m; // Result of shifter
+`endif
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+wire shift_left_d; // Indicates whether to perform a left shift or not
+wire shift_left_q_d;
+wire shift_right_d; // Indicates whether to perform a right shift or not
+wire shift_right_q_d;
+`endif
+`ifdef LM32_NO_BARREL_SHIFT
+wire [`LM32_WORD_RNG] shifter_result_x; // Result of single-bit right shifter
+`endif
+
+// To/from multiplier
+`ifdef LM32_MULTIPLY_ENABLED
+wire [`LM32_WORD_RNG] multiplier_result_w; // Result from multiplier
+`endif
+`ifdef CFG_MC_MULTIPLY_ENABLED
+wire multiply_d; // Indicates whether to perform a multiply or not
+wire multiply_q_d;
+`endif
+
+// To/from divider
+`ifdef CFG_MC_DIVIDE_ENABLED
+wire divide_d; // Indicates whether to perform a divider or not
+wire divide_q_d;
+wire modulus_d;
+wire modulus_q_d;
+wire divide_by_zero_x; // Indicates an attempt was made to divide by zero
+`endif
+
+// To from multi-cycle arithmetic unit
+`ifdef LM32_MC_ARITHMETIC_ENABLED
+wire mc_stall_request_x; // Multi-cycle arithmetic unit stall request
+wire [`LM32_WORD_RNG] mc_result_x;
+`endif
+
+// From CSRs
+`ifdef CFG_INTERRUPTS_ENABLED
+wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs
+`endif
+wire [`LM32_WORD_RNG] cfg; // Configuration CSR
+wire [`LM32_WORD_RNG] cfg2; // Extended Configuration CSR
+`ifdef CFG_CYCLE_COUNTER_ENABLED
+reg [`LM32_WORD_RNG] cc; // Cycle counter CSR
+`endif
+reg [`LM32_WORD_RNG] csr_read_data_x; // Data read from CSRs
+
+// To/from instruction unit
+wire [`LM32_PC_RNG] pc_f; // PC of instruction in F stage
+wire [`LM32_PC_RNG] pc_d; // PC of instruction in D stage
+wire [`LM32_PC_RNG] pc_x; // PC of instruction in X stage
+wire [`LM32_PC_RNG] pc_m; // PC of instruction in M stage
+wire [`LM32_PC_RNG] pc_w; // PC of instruction in W stage
+`ifdef CFG_TRACE_ENABLED
+reg [`LM32_PC_RNG] pc_c; // PC of last commited instruction
+`endif
+`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
+wire [`LM32_INSTRUCTION_RNG] instruction_f; // Instruction in F stage
+`endif
+//pragma attribute instruction_d preserve_signal true
+//pragma attribute instruction_d preserve_driver true
+wire [`LM32_INSTRUCTION_RNG] instruction_d; // Instruction in D stage
+`ifdef CFG_ICACHE_ENABLED
+wire iflush; // Flush instruction cache
+wire icache_stall_request; // Stall pipeline because instruction cache is busy
+wire icache_restart_request; // Restart instruction that caused an instruction cache miss
+wire icache_refill_request; // Request to refill instruction cache
+wire icache_refilling; // Indicates the instruction cache is being refilled
+`endif
+`ifdef CFG_IROM_ENABLED
+wire [`LM32_WORD_RNG] irom_store_data_m; // Store data to instruction ROM
+wire [`LM32_WORD_RNG] irom_address_xm; // Address to instruction ROM from load-store unit
+wire [`LM32_WORD_RNG] irom_data_m; // Load data from instruction ROM
+wire irom_we_xm; // Indicates data needs to be written to instruction ROM
+wire irom_stall_request_x; // Indicates D stage needs to be stalled on a store to instruction ROM
+`endif
+
+// To/from load/store unit
+`ifdef CFG_DCACHE_ENABLED
+wire dflush_x; // Flush data cache
+reg dflush_m;
+wire dcache_stall_request; // Stall pipeline because data cache is busy
+wire dcache_restart_request; // Restart instruction that caused a data cache miss
+wire dcache_refill_request; // Request to refill data cache
+wire dcache_refilling; // Indicates the data cache is being refilled
+`endif
+wire [`LM32_WORD_RNG] load_data_w; // Result of a load instruction
+wire stall_wb_load; // Stall pipeline because of a load via the data Wishbone interface
+
+// To/from JTAG interface
+`ifdef CFG_JTAG_ENABLED
+`ifdef CFG_JTAG_UART_ENABLED
+wire [`LM32_WORD_RNG] jtx_csr_read_data; // Read data for JTX CSR
+wire [`LM32_WORD_RNG] jrx_csr_read_data; // Read data for JRX CSR
+`endif
+`ifdef CFG_HW_DEBUG_ENABLED
+wire jtag_csr_write_enable; // Debugger CSR write enable
+wire [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR
+wire [`LM32_CSR_RNG] jtag_csr; // Which CSR to write
+wire jtag_read_enable;
+wire [`LM32_BYTE_RNG] jtag_read_data;
+wire jtag_write_enable;
+wire [`LM32_BYTE_RNG] jtag_write_data;
+wire [`LM32_WORD_RNG] jtag_address;
+wire jtag_access_complete;
+`endif
+`ifdef CFG_DEBUG_ENABLED
+wire jtag_break; // Request from debugger to raise a breakpoint
+`endif
+`endif
+
+// Hazzard detection
+wire raw_x_0; // RAW hazzard between instruction in X stage and read port 0
+wire raw_x_1; // RAW hazzard between instruction in X stage and read port 1
+wire raw_m_0; // RAW hazzard between instruction in M stage and read port 0
+wire raw_m_1; // RAW hazzard between instruction in M stage and read port 1
+wire raw_w_0; // RAW hazzard between instruction in W stage and read port 0
+wire raw_w_1; // RAW hazzard between instruction in W stage and read port 1
+
+// Control flow
+wire cmp_zero; // Result of comparison is zero
+wire cmp_negative; // Result of comparison is negative
+wire cmp_overflow; // Comparison produced an overflow
+wire cmp_carry_n; // Comparison produced a carry, inverted
+reg condition_met_x; // Condition of branch instruction is met
+reg condition_met_m;
+`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
+wire branch_taken_x; // Branch is taken in X stage
+`endif
+wire branch_taken_m; // Branch is taken in M stage
+
+wire kill_f; // Kill instruction in F stage
+wire kill_d; // Kill instruction in D stage
+wire kill_x; // Kill instruction in X stage
+wire kill_m; // Kill instruction in M stage
+wire kill_w; // Kill instruction in W stage
+
+reg [`LM32_PC_WIDTH+2-1:8] eba; // Exception Base Address (EBA) CSR
+`ifdef CFG_DEBUG_ENABLED
+reg [`LM32_PC_WIDTH+2-1:8] deba; // Debug Exception Base Address (DEBA) CSR
+`endif
+reg [`LM32_EID_RNG] eid_x; // Exception ID in X stage
+`ifdef CFG_TRACE_ENABLED
+reg [`LM32_EID_RNG] eid_m; // Exception ID in M stage
+reg [`LM32_EID_RNG] eid_w; // Exception ID in W stage
+`endif
+
+`ifdef CFG_DEBUG_ENABLED
+`ifdef LM32_SINGLE_STEP_ENABLED
+wire dc_ss; // Is single-step enabled
+`endif
+wire dc_re; // Remap all exceptions
+wire exception_x; // An exception occured in the X stage
+reg exception_m; // An instruction that caused an exception is in the M stage
+wire debug_exception_x; // Indicates if a debug exception has occured
+reg debug_exception_m;
+reg debug_exception_w;
+wire debug_exception_q_w;
+wire non_debug_exception_x; // Indicates if a non debug exception has occured
+reg non_debug_exception_m;
+reg non_debug_exception_w;
+wire non_debug_exception_q_w;
+`else
+wire exception_x; // Indicates if a debug exception has occured
+reg exception_m;
+reg exception_w;
+wire exception_q_w;
+`endif
+
+`ifdef CFG_DEBUG_ENABLED
+`ifdef CFG_JTAG_ENABLED
+wire reset_exception; // Indicates if a reset exception has occured
+`endif
+`endif
+`ifdef CFG_INTERRUPTS_ENABLED
+wire interrupt_exception; // Indicates if an interrupt exception has occured
+`endif
+`ifdef CFG_DEBUG_ENABLED
+wire breakpoint_exception; // Indicates if a breakpoint exception has occured
+wire watchpoint_exception; // Indicates if a watchpoint exception has occured
+`endif
+`ifdef CFG_BUS_ERRORS_ENABLED
+wire instruction_bus_error_exception; // Indicates if an instruction bus error exception has occured
+wire data_bus_error_exception; // Indicates if a data bus error exception has occured
+`endif
+`ifdef CFG_MC_DIVIDE_ENABLED
+wire divide_by_zero_exception; // Indicates if a divide by zero exception has occured
+`endif
+wire system_call_exception; // Indicates if a system call exception has occured
+
+`ifdef CFG_BUS_ERRORS_ENABLED
+reg data_bus_error_seen; // Indicates if a data bus error was seen
+`endif
+
+/////////////////////////////////////////////////////
+// Functions
+/////////////////////////////////////////////////////
+
+`include "lm32_functions.v"
+
+/////////////////////////////////////////////////////
+// Instantiations
+/////////////////////////////////////////////////////
+
+// Instruction unit
+lm32_instruction_unit #(
+ .associativity (icache_associativity),
+ .sets (icache_sets),
+ .bytes_per_line (icache_bytes_per_line),
+ .base_address (icache_base_address),
+ .limit (icache_limit)
+ ) instruction_unit (
+ // ----- Inputs -------
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ // From pipeline
+ .stall_a (stall_a),
+ .stall_f (stall_f),
+ .stall_d (stall_d),
+ .stall_x (stall_x),
+ .stall_m (stall_m),
+ .valid_f (valid_f),
+ .valid_d (valid_d),
+ .kill_f (kill_f),
+ .branch_predict_taken_d (branch_predict_taken_d),
+ .branch_predict_address_d (branch_predict_address_d),
+`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
+ .branch_taken_x (branch_taken_x),
+ .branch_target_x (branch_target_x),
+`endif
+ .exception_m (exception_m),
+ .branch_taken_m (branch_taken_m),
+ .branch_mispredict_taken_m (branch_mispredict_taken_m),
+ .branch_target_m (branch_target_m),
+`ifdef CFG_ICACHE_ENABLED
+ .iflush (iflush),
+`endif
+`ifdef CFG_IROM_ENABLED
+ .irom_store_data_m (irom_store_data_m),
+ .irom_address_xm (irom_address_xm),
+ .irom_we_xm (irom_we_xm),
+`endif
+`ifdef CFG_DCACHE_ENABLED
+ .dcache_restart_request (dcache_restart_request),
+ .dcache_refill_request (dcache_refill_request),
+ .dcache_refilling (dcache_refilling),
+`endif
+`ifdef CFG_IWB_ENABLED
+ // From Wishbone
+ .i_dat_i (I_DAT_I),
+ .i_ack_i (I_ACK_I),
+ .i_err_i (I_ERR_I),
+ .i_rty_i (I_RTY_I),
+`endif
+`ifdef CFG_HW_DEBUG_ENABLED
+ .jtag_read_enable (jtag_read_enable),
+ .jtag_write_enable (jtag_write_enable),
+ .jtag_write_data (jtag_write_data),
+ .jtag_address (jtag_address),
+`endif
+ // ----- Outputs -------
+ // To pipeline
+ .pc_f (pc_f),
+ .pc_d (pc_d),
+ .pc_x (pc_x),
+ .pc_m (pc_m),
+ .pc_w (pc_w),
+`ifdef CFG_ICACHE_ENABLED
+ .icache_stall_request (icache_stall_request),
+ .icache_restart_request (icache_restart_request),
+ .icache_refill_request (icache_refill_request),
+ .icache_refilling (icache_refilling),
+`endif
+`ifdef CFG_IROM_ENABLED
+ .irom_data_m (irom_data_m),
+`endif
+`ifdef CFG_IWB_ENABLED
+ // To Wishbone
+ .i_dat_o (I_DAT_O),
+ .i_adr_o (I_ADR_O),
+ .i_cyc_o (I_CYC_O),
+ .i_sel_o (I_SEL_O),
+ .i_stb_o (I_STB_O),
+ .i_we_o (I_WE_O),
+ .i_cti_o (I_CTI_O),
+ .i_lock_o (I_LOCK_O),
+ .i_bte_o (I_BTE_O),
+`endif
+`ifdef CFG_HW_DEBUG_ENABLED
+ .jtag_read_data (jtag_read_data),
+ .jtag_access_complete (jtag_access_complete),
+`endif
+`ifdef CFG_BUS_ERRORS_ENABLED
+ .bus_error_d (bus_error_d),
+`endif
+`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
+ .instruction_f (instruction_f),
+`endif
+ .instruction_d (instruction_d)
+ );
+
+// Instruction decoder
+lm32_decoder decoder (
+ // ----- Inputs -------
+ .instruction (instruction_d),
+ // ----- Outputs -------
+ .d_result_sel_0 (d_result_sel_0_d),
+ .d_result_sel_1 (d_result_sel_1_d),
+ .x_result_sel_csr (x_result_sel_csr_d),
+`ifdef LM32_MC_ARITHMETIC_ENABLED
+ .x_result_sel_mc_arith (x_result_sel_mc_arith_d),
+`endif
+`ifdef LM32_NO_BARREL_SHIFT
+ .x_result_sel_shift (x_result_sel_shift_d),
+`endif
+`ifdef CFG_SIGN_EXTEND_ENABLED
+ .x_result_sel_sext (x_result_sel_sext_d),
+`endif
+ .x_result_sel_logic (x_result_sel_logic_d),
+`ifdef CFG_USER_ENABLED
+ .x_result_sel_user (x_result_sel_user_d),
+`endif
+ .x_result_sel_add (x_result_sel_add_d),
+ .m_result_sel_compare (m_result_sel_compare_d),
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+ .m_result_sel_shift (m_result_sel_shift_d),
+`endif
+ .w_result_sel_load (w_result_sel_load_d),
+`ifdef CFG_PL_MULTIPLY_ENABLED
+ .w_result_sel_mul (w_result_sel_mul_d),
+`endif
+ .x_bypass_enable (x_bypass_enable_d),
+ .m_bypass_enable (m_bypass_enable_d),
+ .read_enable_0 (read_enable_0_d),
+ .read_idx_0 (read_idx_0_d),
+ .read_enable_1 (read_enable_1_d),
+ .read_idx_1 (read_idx_1_d),
+ .write_enable (write_enable_d),
+ .write_idx (write_idx_d),
+ .immediate (immediate_d),
+ .branch_offset (branch_offset_d),
+ .load (load_d),
+ .store (store_d),
+ .size (size_d),
+ .sign_extend (sign_extend_d),
+ .adder_op (adder_op_d),
+ .logic_op (logic_op_d),
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+ .direction (direction_d),
+`endif
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+ .shift_left (shift_left_d),
+ .shift_right (shift_right_d),
+`endif
+`ifdef CFG_MC_MULTIPLY_ENABLED
+ .multiply (multiply_d),
+`endif
+`ifdef CFG_MC_DIVIDE_ENABLED
+ .divide (divide_d),
+ .modulus (modulus_d),
+`endif
+ .branch (branch_d),
+ .bi_unconditional (bi_unconditional),
+ .bi_conditional (bi_conditional),
+ .branch_reg (branch_reg_d),
+ .condition (condition_d),
+`ifdef CFG_DEBUG_ENABLED
+ .break_opcode (break_d),
+`endif
+ .scall (scall_d),
+ .eret (eret_d),
+`ifdef CFG_DEBUG_ENABLED
+ .bret (bret_d),
+`endif
+`ifdef CFG_USER_ENABLED
+ .user_opcode (user_opcode_d),
+`endif
+ .csr_write_enable (csr_write_enable_d)
+ );
+
+// Load/store unit
+lm32_load_store_unit #(
+ .associativity (dcache_associativity),
+ .sets (dcache_sets),
+ .bytes_per_line (dcache_bytes_per_line),
+ .base_address (dcache_base_address),
+ .limit (dcache_limit)
+ ) load_store_unit (
+ // ----- Inputs -------
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ // From pipeline
+ .stall_a (stall_a),
+ .stall_x (stall_x),
+ .stall_m (stall_m),
+ .kill_x (kill_x),
+ .kill_m (kill_m),
+ .exception_m (exception_m),
+ .store_operand_x (store_operand_x),
+ .load_store_address_x (adder_result_x),
+ .load_store_address_m (operand_m),
+ .load_store_address_w (operand_w[1:0]),
+ .load_x (load_x),
+ .store_x (store_x),
+ .load_q_x (load_q_x),
+ .store_q_x (store_q_x),
+ .load_q_m (load_q_m),
+ .store_q_m (store_q_m),
+ .sign_extend_x (sign_extend_x),
+ .size_x (size_x),
+`ifdef CFG_DCACHE_ENABLED
+ .dflush (dflush_m),
+`endif
+`ifdef CFG_IROM_ENABLED
+ .irom_data_m (irom_data_m),
+`endif
+ // From Wishbone
+ .d_dat_i (D_DAT_I),
+ .d_ack_i (D_ACK_I),
+ .d_err_i (D_ERR_I),
+ .d_rty_i (D_RTY_I),
+ // ----- Outputs -------
+ // To pipeline
+`ifdef CFG_DCACHE_ENABLED
+ .dcache_refill_request (dcache_refill_request),
+ .dcache_restart_request (dcache_restart_request),
+ .dcache_stall_request (dcache_stall_request),
+ .dcache_refilling (dcache_refilling),
+`endif
+`ifdef CFG_IROM_ENABLED
+ .irom_store_data_m (irom_store_data_m),
+ .irom_address_xm (irom_address_xm),
+ .irom_we_xm (irom_we_xm),
+ .irom_stall_request_x (irom_stall_request_x),
+`endif
+ .load_data_w (load_data_w),
+ .stall_wb_load (stall_wb_load),
+ // To Wishbone
+ .d_dat_o (D_DAT_O),
+ .d_adr_o (D_ADR_O),
+ .d_cyc_o (D_CYC_O),
+ .d_sel_o (D_SEL_O),
+ .d_stb_o (D_STB_O),
+ .d_we_o (D_WE_O),
+ .d_cti_o (D_CTI_O),
+ .d_lock_o (D_LOCK_O),
+ .d_bte_o (D_BTE_O)
+ );
+
+// Adder
+lm32_adder adder (
+ // ----- Inputs -------
+ .adder_op_x (adder_op_x),
+ .adder_op_x_n (adder_op_x_n),
+ .operand_0_x (operand_0_x),
+ .operand_1_x (operand_1_x),
+ // ----- Outputs -------
+ .adder_result_x (adder_result_x),
+ .adder_carry_n_x (adder_carry_n_x),
+ .adder_overflow_x (adder_overflow_x)
+ );
+
+// Logic operations
+lm32_logic_op logic_op (
+ // ----- Inputs -------
+ .logic_op_x (logic_op_x),
+ .operand_0_x (operand_0_x),
+
+ .operand_1_x (operand_1_x),
+ // ----- Outputs -------
+ .logic_result_x (logic_result_x)
+ );
+
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+// Pipelined barrel-shifter
+lm32_shifter shifter (
+ // ----- Inputs -------
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ .stall_x (stall_x),
+ .direction_x (direction_x),
+ .sign_extend_x (sign_extend_x),
+ .operand_0_x (operand_0_x),
+ .operand_1_x (operand_1_x),
+ // ----- Outputs -------
+ .shifter_result_m (shifter_result_m)
+ );
+`endif
+
+`ifdef CFG_PL_MULTIPLY_ENABLED
+// Pipeline fixed-point multiplier
+lm32_multiplier multiplier (
+ // ----- Inputs -------
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ .stall_x (stall_x),
+ .stall_m (stall_m),
+ .operand_0 (d_result_0),
+ .operand_1 (d_result_1),
+ // ----- Outputs -------
+ .result (multiplier_result_w)
+ );
+`endif
+
+`ifdef LM32_MC_ARITHMETIC_ENABLED
+// Multi-cycle arithmetic
+lm32_mc_arithmetic mc_arithmetic (
+ // ----- Inputs -------
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ .stall_d (stall_d),
+ .kill_x (kill_x),
+`ifdef CFG_MC_DIVIDE_ENABLED
+ .divide_d (divide_q_d),
+ .modulus_d (modulus_q_d),
+`endif
+`ifdef CFG_MC_MULTIPLY_ENABLED
+ .multiply_d (multiply_q_d),
+`endif
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+ .shift_left_d (shift_left_q_d),
+ .shift_right_d (shift_right_q_d),
+ .sign_extend_d (sign_extend_d),
+`endif
+ .operand_0_d (d_result_0),
+ .operand_1_d (d_result_1),
+ // ----- Outputs -------
+ .result_x (mc_result_x),
+`ifdef CFG_MC_DIVIDE_ENABLED
+ .divide_by_zero_x (divide_by_zero_x),
+`endif
+ .stall_request_x (mc_stall_request_x)
+ );
+`endif
+
+`ifdef CFG_INTERRUPTS_ENABLED
+// Interrupt unit
+lm32_interrupt interrupt (
+ // ----- Inputs -------
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ // From external devices
+ .interrupt_n (interrupt_n),
+ // From pipeline
+ .stall_x (stall_x),
+`ifdef CFG_DEBUG_ENABLED
+ .non_debug_exception (non_debug_exception_q_w),
+ .debug_exception (debug_exception_q_w),
+`else
+ .exception (exception_q_w),
+`endif
+ .eret_q_x (eret_q_x),
+`ifdef CFG_DEBUG_ENABLED
+ .bret_q_x (bret_q_x),
+`endif
+ .csr (csr_x),
+ .csr_write_data (operand_1_x),
+ .csr_write_enable (csr_write_enable_q_x),
+ // ----- Outputs -------
+ .interrupt_exception (interrupt_exception),
+ // To pipeline
+ .csr_read_data (interrupt_csr_read_data_x)
+ );
+`endif
+
+`ifdef CFG_JTAG_ENABLED
+// JTAG interface
+lm32_jtag jtag (
+ // ----- Inputs -------
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ // From JTAG
+ .jtag_clk (jtag_clk),
+ .jtag_update (jtag_update),
+ .jtag_reg_q (jtag_reg_q),
+ .jtag_reg_addr_q (jtag_reg_addr_q),
+ // From pipeline
+`ifdef CFG_JTAG_UART_ENABLED
+ .csr (csr_x),
+ .csr_write_data (operand_1_x),
+ .csr_write_enable (csr_write_enable_q_x),
+ .stall_x (stall_x),
+`endif
+`ifdef CFG_HW_DEBUG_ENABLED
+ .jtag_read_data (jtag_read_data),
+ .jtag_access_complete (jtag_access_complete),
+`endif
+`ifdef CFG_DEBUG_ENABLED
+ .exception_q_w (debug_exception_q_w || non_debug_exception_q_w),
+`endif
+ // ----- Outputs -------
+ // To pipeline
+`ifdef CFG_JTAG_UART_ENABLED
+ .jtx_csr_read_data (jtx_csr_read_data),
+ .jrx_csr_read_data (jrx_csr_read_data),
+`endif
+`ifdef CFG_HW_DEBUG_ENABLED
+ .jtag_csr_write_enable (jtag_csr_write_enable),
+ .jtag_csr_write_data (jtag_csr_write_data),
+ .jtag_csr (jtag_csr),
+ .jtag_read_enable (jtag_read_enable),
+ .jtag_write_enable (jtag_write_enable),
+ .jtag_write_data (jtag_write_data),
+ .jtag_address (jtag_address),
+`endif
+`ifdef CFG_DEBUG_ENABLED
+ .jtag_break (jtag_break),
+ .jtag_reset (reset_exception),
+`endif
+ // To JTAG
+ .jtag_reg_d (jtag_reg_d),
+ .jtag_reg_addr_d (jtag_reg_addr_d)
+ );
+`endif
+
+`ifdef CFG_DEBUG_ENABLED
+// Debug unit
+lm32_debug #(
+ .breakpoints (breakpoints),
+ .watchpoints (watchpoints)
+ ) hw_debug (
+ // ----- Inputs -------
+ .clk_i (clk_i),