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Commits on Oct 10, 2014
  1. convert the latex documention to rst

    This will ease editing the documentation. For now only a HTML output is
    generated.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle committed Oct 10, 2014
Commits on Apr 18, 2014
  1. Fix MMU documentation

    fallen committed with sbourdeauducq Apr 18, 2014
Commits on Feb 24, 2014
  1. add two more MMU test cases

    Make sure the three lowest bits in IE are shadowed to the PSW register.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle committed Feb 24, 2014
Commits on Dec 5, 2013
Commits on Nov 25, 2013
Commits on Nov 9, 2013
Commits on Aug 9, 2013
  1. Add LM32 MMU documentation

    fallen committed with sbourdeauducq Jun 24, 2013
Commits on Feb 24, 2013
  1. fix compilation with no CFG_DEBUG_ENABLED

    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle committed Feb 24, 2013
Commits on Jan 10, 2013
  1. define $(RM) in Makefiles

    In case make does not predefine it, eg. BSD make.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle committed Jan 10, 2013
Commits on Jan 8, 2013
  1. fix compilation of lm32 tests

    Fix compiling when using RTEMS toolchain (or any other non-bare-metal
    toolchain).
    
    Signed-off-by: Yann Sionneau <yann@minet.net>
    Signed-off-by: Michael Walle <michael@walle.cc>
    fallen committed with mwalle Jan 7, 2013
  2. lm32 test Makefiles cleanup

    Make the makefiles more portable and able to use different toolchain than
    lm32-elf (for instance lm32-rtems4.11).
    
    Signed-off-by: Yann Sionneau <yann@minet.net>
    Signed-off-by: Michael Walle <michael@walle.cc>
    fallen committed with mwalle Jan 7, 2013
Commits on Dec 17, 2012
  1. add README

    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle committed Dec 17, 2012
  2. add config option for level-sensitive interrupts

    If interrupts are level-sensitive there is no need to latch the state in
    the IP register. Thus, make the IP register reflect the state of the
    interrupt lines and make it read-only.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle committed Dec 17, 2012
  3. fix typos in interrupt_unit.v

    Interrupt lines are active-high since commit
      3593788
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle committed Dec 17, 2012
Commits on Dec 16, 2012
  1. add lm32_config.v example

    Add an extensively documented lm32_config.v example config file.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle committed Dec 14, 2012
  2. remove dead rotate code

    Never used, never defined. No opcode for rotate. Remove it.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle committed Dec 14, 2012
  3. remove register file reset

    The reset is not necessary. Without the reset, the register file can (and
    will be) instantiated as BlockRAM, at least with Xst.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle committed Dec 14, 2012
  4. convert instruction ROM non-portable instantiation

    Convert the last remaining device specific instantiation in
    lm32_instruction_unit.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle committed Dec 14, 2012
  5. convert more non-portable instantiations

    Convert the device specific dual-port RAM instantiation to use the
    lm32_ram.v module. Only the instruction ROM is still not converted
    because it uses true dual port ram.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle committed Dec 14, 2012
  6. support for init file in lm32_ram module

    This is used for the embedded instruction ROM and the data RAM.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle committed Dec 14, 2012
  7. remove lm32_dp_ram module

    The module is a duplicate of lm32_ram.v. Use that module instead.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle committed Dec 14, 2012
  8. remove Spartan-6 multiplier

    Xst (tested with 14.2) is now smart enought to infer the same pipelined
    multiplier (using DSP48A1 slices) with the generic verilog description of
    the multiplier (lm32_multiplier.v). Therefore, there is no more need for
    the specialized version. Remove it.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle committed Dec 13, 2012
  9. fix compilation if JTAG is not enabled

    reset_exception is only defined when both DEBUG and JTAG are enabled.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle committed Dec 13, 2012
  10. import qemu test cases

    Import the TCG test cases from QEMU. Emulate the lm32_sys device in the
    lm32 test bench. From time to time these test cases will be synchronized
    with QEMU.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle committed Dec 12, 2012
  11. privilege exception support

    Raise a privilege exception if we are in user mode and one of the following
    opcodes are executed: wcsr, eret, bret.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle committed Dec 6, 2012
  12. add TLB tracing to test bench

    Print traces on writes to TLB memories.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle committed Dec 12, 2012
  13. initial DTLB implemenation

    This patch add the data translation lookaside buffer.
    
    The pipeline is stalled for one cycle every load and store instruction
    if the DTLB is enabled. This cycle is needed for the TLB llokup. The
    lookup result is needed in the X stage to correctly handle a potential
    exception.
    
    Additionally, there are read only and cache inhibit flags in a TLB
    entry.  Writes to a read-only page will raise a DTLB fault exception. If
    the cache inhibit flag is set, load and stores will skip the data cache
    and go directly to the wishbone bus instead.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    Signed-off-by: Yann Sionneau <yann.sionneau@gmail.com>
    mwalle committed Dec 12, 2012
  14. initial ITLB implemenation

    This patch adds the instruction translation lookaside buffer.
    
    Miss exceptions are delayed until the X stage and if the instruction is
    still qualified (eg. not killed and still valid) the exception is taken.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    Signed-off-by: Yann Sionneau <yann.sionneau@gmail.com>
    mwalle committed Dec 12, 2012
  15. make wcsr, bret and eret privileged

    Make wcsr, bret and eret NOOPs if the processor is not in kernel mode.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle committed Dec 12, 2012
  16. add MMU flag to CFG2 register

    Use the most significant bit because Lattice will likely add new feature at
    the lower bits.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle committed Nov 30, 2012
  17. add PSW register

    Add the processor status word register. This register is used to enable the
    TLBs and the (non-privileged) user mode. If an exception occurs, the these
    enable bits will be saved and cleared. After an eret or bret opcode is
    executed, these bits will be restored.
    
    For backward compatibility, the lower three bits of this register are
    shadowed from the original IE register. A new program can then only use
    this register, eg. saving the state on an ISR, while older programs can
    still use the IE register.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle committed Dec 12, 2012
  18. add tlb control registers

    Add TLBVADDR, TLBPADDR and TLBBADVADDR registers. These are used to
    control the data and instruction TLBs.
    
    Control functions like flushing and invalidating an entry are executed by
    writing to the TLBVADDR register. An entry can be updated by writing to the
    TLBPADDR (before writing the virtual frame number to TLBVADDR, with the
    lower bits zero to indicate a NOOP).
    
    The lowest bit in the TLBVADDR and TLBPADDR register is used to address the
    corresponding TLB.
    
    After a TLB exception has happened, the TLBVADDR register is automatically
    preloaded with the missed virtual frame number. Because of this, an
    exception handler can read the missed virtual address by reading
    TLBBADVADDR register and set the physical frame number by writing the
    TLBPADDR register.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    Signed-off-by: Yann Sionneau <yann.sionneau@gmail.com>
    mwalle committed Dec 12, 2012
  19. enable MMU in test bench

    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle committed Dec 12, 2012
  20. generalize line size of {i,d}cache

    Don't hardcode only sizes of 4, 8 and 16. Instead allow any size that is
    a power of two.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    mwalle committed Nov 23, 2012