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Commits on Nov 25, 2013
  1. @sbourdeauducq
Commits on Feb 24, 2013
  1. @mwalle

    fix compilation with no CFG_DEBUG_ENABLED

    mwalle committed
    Signed-off-by: Michael Walle <michael@walle.cc>
Commits on Dec 17, 2012
  1. @mwalle

    add config option for level-sensitive interrupts

    mwalle committed
    If interrupts are level-sensitive there is no need to latch the state in
    the IP register. Thus, make the IP register reflect the state of the
    interrupt lines and make it read-only.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  2. @mwalle

    fix typos in interrupt_unit.v

    mwalle committed
    Interrupt lines are active-high since commit
      3593788
    
    Signed-off-by: Michael Walle <michael@walle.cc>
Commits on Dec 16, 2012
  1. @mwalle

    add lm32_config.v example

    mwalle committed
    Add an extensively documented lm32_config.v example config file.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  2. @mwalle

    remove dead rotate code

    mwalle committed
    Never used, never defined. No opcode for rotate. Remove it.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  3. @mwalle

    remove register file reset

    mwalle committed
    The reset is not necessary. Without the reset, the register file can (and
    will be) instantiated as BlockRAM, at least with Xst.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  4. @mwalle

    convert instruction ROM non-portable instantiation

    mwalle committed
    Convert the last remaining device specific instantiation in
    lm32_instruction_unit.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  5. @mwalle

    convert more non-portable instantiations

    mwalle committed
    Convert the device specific dual-port RAM instantiation to use the
    lm32_ram.v module. Only the instruction ROM is still not converted
    because it uses true dual port ram.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  6. @mwalle

    support for init file in lm32_ram module

    mwalle committed
    This is used for the embedded instruction ROM and the data RAM.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  7. @mwalle

    remove lm32_dp_ram module

    mwalle committed
    The module is a duplicate of lm32_ram.v. Use that module instead.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  8. @mwalle

    remove Spartan-6 multiplier

    mwalle committed
    Xst (tested with 14.2) is now smart enought to infer the same pipelined
    multiplier (using DSP48A1 slices) with the generic verilog description of
    the multiplier (lm32_multiplier.v). Therefore, there is no more need for
    the specialized version. Remove it.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  9. @mwalle

    fix compilation if JTAG is not enabled

    mwalle committed
    reset_exception is only defined when both DEBUG and JTAG are enabled.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  10. @mwalle

    privilege exception support

    mwalle committed
    Raise a privilege exception if we are in user mode and one of the following
    opcodes are executed: wcsr, eret, bret.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  11. @mwalle

    initial DTLB implemenation

    mwalle committed
    This patch add the data translation lookaside buffer.
    
    The pipeline is stalled for one cycle every load and store instruction
    if the DTLB is enabled. This cycle is needed for the TLB llokup. The
    lookup result is needed in the X stage to correctly handle a potential
    exception.
    
    Additionally, there are read only and cache inhibit flags in a TLB
    entry.  Writes to a read-only page will raise a DTLB fault exception. If
    the cache inhibit flag is set, load and stores will skip the data cache
    and go directly to the wishbone bus instead.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    Signed-off-by: Yann Sionneau <yann.sionneau@gmail.com>
  12. @mwalle

    initial ITLB implemenation

    mwalle committed
    This patch adds the instruction translation lookaside buffer.
    
    Miss exceptions are delayed until the X stage and if the instruction is
    still qualified (eg. not killed and still valid) the exception is taken.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    Signed-off-by: Yann Sionneau <yann.sionneau@gmail.com>
  13. @mwalle

    make wcsr, bret and eret privileged

    mwalle committed
    Make wcsr, bret and eret NOOPs if the processor is not in kernel mode.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  14. @mwalle

    add MMU flag to CFG2 register

    mwalle committed
    Use the most significant bit because Lattice will likely add new feature at
    the lower bits.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  15. @mwalle

    add PSW register

    mwalle committed
    Add the processor status word register. This register is used to enable the
    TLBs and the (non-privileged) user mode. If an exception occurs, the these
    enable bits will be saved and cleared. After an eret or bret opcode is
    executed, these bits will be restored.
    
    For backward compatibility, the lower three bits of this register are
    shadowed from the original IE register. A new program can then only use
    this register, eg. saving the state on an ISR, while older programs can
    still use the IE register.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  16. @mwalle

    add tlb control registers

    mwalle committed
    Add TLBVADDR, TLBPADDR and TLBBADVADDR registers. These are used to
    control the data and instruction TLBs.
    
    Control functions like flushing and invalidating an entry are executed by
    writing to the TLBVADDR register. An entry can be updated by writing to the
    TLBPADDR (before writing the virtual frame number to TLBVADDR, with the
    lower bits zero to indicate a NOOP).
    
    The lowest bit in the TLBVADDR and TLBPADDR register is used to address the
    corresponding TLB.
    
    After a TLB exception has happened, the TLBVADDR register is automatically
    preloaded with the missed virtual frame number. Because of this, an
    exception handler can read the missed virtual address by reading
    TLBBADVADDR register and set the physical frame number by writing the
    TLBPADDR register.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
    Signed-off-by: Yann Sionneau <yann.sionneau@gmail.com>
  17. @mwalle

    generalize line size of {i,d}cache

    mwalle committed
    Don't hardcode only sizes of 4, 8 and 16. Instead allow any size that is
    a power of two.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  18. @mwalle

    make eid width configurable

    mwalle committed
    This will be needed for the MMU implementation, where additional exception
    vectors are defined.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  19. @mwalle

    whitespace and indentation fixes

    mwalle committed
    Replace tabstops, correct indentation according to Lattice's coding style.
    This huge patch makes it harder to backport upstream fixes, but there was
    already a patch which replaced almost every line in the source code. So it
    was already hard :)
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  20. @mwalle

    fix watchpoints

    mwalle committed
    The wp_match_n vector is off by one. Which results in undefined states, at
    least in simulation.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  21. @mwalle

    replace $clog2 with macro

    mwalle committed
    Unfortunately, XST does not support $clog2 with the localparam keyword
    (the parameter keyword works just fine). Define a macro which replaces the
    call with a constant function.
    
    This commit can be reverted if the bug in XST is fixed.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  22. @mwalle

    split lm32_include.v

    mwalle committed
    Split lm32_include.v into common defines and actual processor
    configuration. Put the first module into the rtl/ directory.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  23. @mwalle

    fix documentation style

    mwalle committed
    Make lm32_dp_ram module conform to the remaining modules.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  24. @mwalle

    remove unneeded parameter in lm32_dp_ram

    mwalle committed
    addr_depth can be computed by addr_width.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  25. @mwalle

    rename mem array in lm32_dp_ram

    mwalle committed
    Be compatible with original proprietary DP RAM instantiation. This is
    needed for simulation, where r0 is initialized to zero in lm32_cpu.v.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  26. @mwalle

    replace clogb2 by builtin $clog2

    mwalle committed
    This function is fixed in ISE since version 14.1 (see AR #44586). If the
    builtin function is used, the design can be simulated with Icarus Verilog.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  27. @mwalle

    new license headers for lm32 source files

    mwalle committed
    These headers were introduced with LatticeMico System 1.3.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  28. @mwalle

    sync to upstream v3.6 sources

    mwalle committed
     - feature: support for dynamically switching EBA to DEBA via a GPIO.
     - bug: EA now reports instruction that caused the data abort, rather than
       next instruction.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  29. @mwalle

    add support for an external break pulse

    mwalle committed
    Pulsing this input generates a breakpoint exception.
    
    Signed-off-by: Michael Walle <michael@walle.cc>
  30. @terpstra @mwalle

    support register file backed by dual ported RAM

    terpstra committed with mwalle
    Convert non-portable instantiation to generic dual-port RAM module.
    
    Signed-off-by: Wesley W. Terpstra <w.terpstra@gsi.de>
  31. @terpstra @mwalle

    add support to flush i and d-cache per JTAG

    terpstra committed with mwalle
    Write to DCC or ICC to flush the corresponding cache.
    
    Signed-off-by: Wesley W. Terpstra <w.terpstra@gsi.de>
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