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Commits on Dec 17, 2012
Michael Walle mwalle fix typos in interrupt_unit.v
Interrupt lines are active-high since commit
  3593788

Signed-off-by: Michael Walle <michael@walle.cc>
8945e79
Michael Walle mwalle add config option for level-sensitive interrupts
If interrupts are level-sensitive there is no need to latch the state in
the IP register. Thus, make the IP register reflect the state of the
interrupt lines and make it read-only.

Signed-off-by: Michael Walle <michael@walle.cc>
6d2b5b9
Michael Walle mwalle add README
Signed-off-by: Michael Walle <michael@walle.cc>
ca5679d
Showing with 90 additions and 2 deletions.
  1. +62 −0 README
  2. +4 −0 rtl/lm32_config.v.sample
  3. +24 −2 rtl/lm32_interrupt.v
62 README
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@@ -0,0 +1,62 @@
+LatticeMico32
+=============
+
+LatticeMico32 is a soft processor originally developed by Lattice
+Semiconductor [1]. It was released under an open IP core license.
+
+This is a fork of the original sources distributed by Lattice. It includes
+new features, bugfixes and support for other FPGA devices. All additional
+features are BSD-licensed.
+
+Please note that this is only the processor core, not a complete SoC.
+
+
+Original Features
+=================
+
+ * 32-bit RISC architecture
+ * Six stage pipeline
+ * Two Wishbone bus interfaces for instruction and data
+ * 32 external interrupts
+ * 32 general purpose registers
+ * Instruction and data caches
+ * Embedded instruction ROM and data RAM support
+
+
+Added Features
+==============
+
+ * MMU support
+ * Non-privileged user-mode support
+ * JTAG support for Xilinx Spartan-6 devices
+ * Test bench (using Icarus Verilog [3])
+ * Replaced device specific primitives with generic verilog modules
+ * Unit tests shared with QEMU
+
+
+Reference Manual
+================
+
+You can find the reference manual at [2].
+
+
+Getting Started
+===============
+
+This repository provides all you need to simulate programs with the system
+test bench. Try it, by typing
+ make sim_hello_world
+in the test/ directory.
+
+For an example of a larger project which uses this core, see milkymist [4]
+and milkymist-ng [5].
+
+
+References
+==========
+
+[1] http://www.latticesemi.com
+[2] http://www.latticesemi.com/documents/doc20890x45.pdf
+[3] http://iverilog.icarus.com
+[4] http://github.com/milkymist/milkymist
+[5] http://github.com/milkymist/milkymist-ng
4 rtl/lm32_config.v.sample
View
@@ -55,6 +55,10 @@
// Enable support for 32 hardware interrupts
`define CFG_INTERRUPTS_ENABLED
+// Enable level-sensitive interrupts. The interrupt line status is
+// reflected in the IP register, which is then read-only.
+//`define CFG_LEVEL_SENSITIVE_INTERRUPTS
+
//
// USER INSTRUCTION
26 rtl/lm32_interrupt.v
View
@@ -93,7 +93,7 @@ parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts
input clk_i; // Clock
input rst_i; // Reset
-input [interrupts-1:0] interrupt; // Interrupt pins, active-low
+input [interrupts-1:0] interrupt; // Interrupt pins
input stall_x; // Stall X pipeline stage
@@ -126,8 +126,10 @@ reg [`LM32_WORD_RNG] csr_read_data;
// Internal nets and registers
/////////////////////////////////////////////////////
+`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
wire [interrupts-1:0] asserted; // Which interrupts are currently being asserted
//pragma attribute asserted preserve_signal true
+`endif
wire [interrupts-1:0] interrupt_n_exception;
// Interrupt CSRs
@@ -137,7 +139,11 @@ reg eie; // Exception interrupt enable
`ifdef CFG_DEBUG_ENABLED
reg bie; // Breakpoint interrupt enable
`endif
+`ifdef CFG_LEVEL_SENSITIVE_INTERRUPTS
+wire [interrupts-1:0] ip; // Interrupt pending
+`else
reg [interrupts-1:0] ip; // Interrupt pending
+`endif
reg [interrupts-1:0] im; // Interrupt mask
/////////////////////////////////////////////////////
@@ -150,8 +156,12 @@ assign interrupt_n_exception = ip & im;
// Determine if any unmasked interrupts have occured
assign interrupt_exception = (|interrupt_n_exception) & ie;
-// Determine which interrupts are currently being asserted (active-low) or are already pending
+// Determine which interrupts are currently being asserted or are already pending
+`ifdef CFG_LEVEL_SENSITIVE_INTERRUPTS
+assign ip = interrupt;
+`else
assign asserted = ip | interrupt;
+`endif
assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
`ifdef CFG_DEBUG_ENABLED
@@ -229,12 +239,16 @@ begin
bie <= `FALSE;
`endif
im <= {interrupts{1'b0}};
+`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
ip <= {interrupts{1'b0}};
+`endif
end
else
begin
// Set IP bit when interrupt line is asserted
+`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
ip <= asserted;
+`endif
`ifdef CFG_DEBUG_ENABLED
if (non_debug_exception == `TRUE)
begin
@@ -283,8 +297,10 @@ begin
end
if (csr == `LM32_CSR_IM)
im <= csr_write_data[interrupts-1:0];
+`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
if (csr == `LM32_CSR_IP)
ip <= asserted & ~csr_write_data[interrupts-1:0];
+`endif
end
end
end
@@ -302,12 +318,16 @@ begin
`ifdef CFG_DEBUG_ENABLED
bie <= `FALSE;
`endif
+`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
ip <= {interrupts{1'b0}};
+`endif
end
else
begin
// Set IP bit when interrupt line is asserted
+`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
ip <= asserted;
+`endif
`ifdef CFG_DEBUG_ENABLED
if (non_debug_exception == `TRUE)
begin
@@ -354,8 +374,10 @@ begin
bie <= csr_write_data[2];
`endif
end
+`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
if (csr == `LM32_CSR_IP)
ip <= asserted & ~csr_write_data[interrupts-1:0];
+`endif
end
end
end

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