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Dec 17, 2012
Michael Walle fix typos in interrupt_unit.v
Interrupt lines are active-high since commit
  3593788

Signed-off-by: Michael Walle <michael@walle.cc>
8945e79
Michael Walle add config option for level-sensitive interrupts
If interrupts are level-sensitive there is no need to latch the state in
the IP register. Thus, make the IP register reflect the state of the
interrupt lines and make it read-only.

Signed-off-by: Michael Walle <michael@walle.cc>
6d2b5b9
Michael Walle add README
Signed-off-by: Michael Walle <michael@walle.cc>
ca5679d
62  README
... ...
@@ -0,0 +1,62 @@
  1
+LatticeMico32
  2
+=============
  3
+
  4
+LatticeMico32 is a soft processor originally developed by Lattice
  5
+Semiconductor [1]. It was released under an open IP core license.
  6
+
  7
+This is a fork of the original sources distributed by Lattice. It includes
  8
+new features, bugfixes and support for other FPGA devices. All additional
  9
+features are BSD-licensed.
  10
+
  11
+Please note that this is only the processor core, not a complete SoC.
  12
+
  13
+
  14
+Original Features
  15
+=================
  16
+
  17
+ * 32-bit RISC architecture
  18
+ * Six stage pipeline
  19
+ * Two Wishbone bus interfaces for instruction and data
  20
+ * 32 external interrupts
  21
+ * 32 general purpose registers
  22
+ * Instruction and data caches
  23
+ * Embedded instruction ROM and data RAM support
  24
+
  25
+
  26
+Added Features
  27
+==============
  28
+
  29
+ * MMU support
  30
+ * Non-privileged user-mode support
  31
+ * JTAG support for Xilinx Spartan-6 devices
  32
+ * Test bench (using Icarus Verilog [3])
  33
+ * Replaced device specific primitives with generic verilog modules
  34
+ * Unit tests shared with QEMU
  35
+
  36
+
  37
+Reference Manual
  38
+================
  39
+
  40
+You can find the reference manual at [2].
  41
+
  42
+
  43
+Getting Started
  44
+===============
  45
+
  46
+This repository provides all you need to simulate programs with the system
  47
+test bench. Try it, by typing
  48
+  make sim_hello_world
  49
+in the test/ directory.
  50
+
  51
+For an example of a larger project which uses this core, see milkymist [4]
  52
+and milkymist-ng [5].
  53
+
  54
+
  55
+References
  56
+==========
  57
+
  58
+[1] http://www.latticesemi.com
  59
+[2] http://www.latticesemi.com/documents/doc20890x45.pdf
  60
+[3] http://iverilog.icarus.com
  61
+[4] http://github.com/milkymist/milkymist
  62
+[5] http://github.com/milkymist/milkymist-ng
4  rtl/lm32_config.v.sample
@@ -55,6 +55,10 @@
55 55
 // Enable support for 32 hardware interrupts
56 56
 `define CFG_INTERRUPTS_ENABLED
57 57
 
  58
+// Enable level-sensitive interrupts. The interrupt line status is
  59
+// reflected in the IP register, which is then read-only.
  60
+//`define CFG_LEVEL_SENSITIVE_INTERRUPTS
  61
+
58 62
 
59 63
 //
60 64
 // USER INSTRUCTION
26  rtl/lm32_interrupt.v
@@ -93,7 +93,7 @@ parameter interrupts = `CFG_INTERRUPTS;         // Number of interrupts
93 93
 input clk_i;                                    // Clock
94 94
 input rst_i;                                    // Reset
95 95
 
96  
-input [interrupts-1:0] interrupt;               // Interrupt pins, active-low
  96
+input [interrupts-1:0] interrupt;               // Interrupt pins
97 97
 
98 98
 input stall_x;                                  // Stall X pipeline stage
99 99
 
@@ -126,8 +126,10 @@ reg    [`LM32_WORD_RNG] csr_read_data;
126 126
 // Internal nets and registers
127 127
 /////////////////////////////////////////////////////
128 128
 
  129
+`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
129 130
 wire [interrupts-1:0] asserted;                 // Which interrupts are currently being asserted
130 131
 //pragma attribute asserted preserve_signal true
  132
+`endif
131 133
 wire [interrupts-1:0] interrupt_n_exception;
132 134
 
133 135
 // Interrupt CSRs
@@ -137,7 +139,11 @@ reg eie;                                        // Exception interrupt enable
137 139
 `ifdef CFG_DEBUG_ENABLED
138 140
 reg bie;                                        // Breakpoint interrupt enable
139 141
 `endif
  142
+`ifdef CFG_LEVEL_SENSITIVE_INTERRUPTS
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+wire [interrupts-1:0] ip;                       // Interrupt pending
  144
+`else
140 145
 reg [interrupts-1:0] ip;                        // Interrupt pending
  146
+`endif
141 147
 reg [interrupts-1:0] im;                        // Interrupt mask
142 148
 
143 149
 /////////////////////////////////////////////////////
@@ -150,8 +156,12 @@ assign interrupt_n_exception = ip & im;
150 156
 // Determine if any unmasked interrupts have occured
151 157
 assign interrupt_exception = (|interrupt_n_exception) & ie;
152 158
 
153  
-// Determine which interrupts are currently being asserted (active-low) or are already pending
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+// Determine which interrupts are currently being asserted or are already pending
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+`ifdef CFG_LEVEL_SENSITIVE_INTERRUPTS
  161
+assign ip = interrupt;
  162
+`else
154 163
 assign asserted = ip | interrupt;
  164
+`endif
155 165
 
156 166
 assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
157 167
 `ifdef CFG_DEBUG_ENABLED
@@ -229,12 +239,16 @@ begin
229 239
         bie <= `FALSE;
230 240
 `endif
231 241
         im <= {interrupts{1'b0}};
  242
+`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
232 243
         ip <= {interrupts{1'b0}};
  244
+`endif
233 245
     end
234 246
     else
235 247
     begin
236 248
         // Set IP bit when interrupt line is asserted
  249
+`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
237 250
         ip <= asserted;
  251
+`endif
238 252
 `ifdef CFG_DEBUG_ENABLED
239 253
         if (non_debug_exception == `TRUE)
240 254
         begin
@@ -283,8 +297,10 @@ begin
283 297
                 end
284 298
                 if (csr == `LM32_CSR_IM)
285 299
                     im <= csr_write_data[interrupts-1:0];
  300
+`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
286 301
                 if (csr == `LM32_CSR_IP)
287 302
                     ip <= asserted & ~csr_write_data[interrupts-1:0];
  303
+`endif
288 304
             end
289 305
         end
290 306
     end
@@ -302,12 +318,16 @@ begin
302 318
 `ifdef CFG_DEBUG_ENABLED
303 319
         bie <= `FALSE;
304 320
 `endif
  321
+`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
305 322
         ip <= {interrupts{1'b0}};
  323
+`endif
306 324
     end
307 325
     else
308 326
     begin
309 327
         // Set IP bit when interrupt line is asserted
  328
+`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
310 329
         ip <= asserted;
  330
+`endif
311 331
 `ifdef CFG_DEBUG_ENABLED
312 332
         if (non_debug_exception == `TRUE)
313 333
         begin
@@ -354,8 +374,10 @@ begin
354 374
                     bie <= csr_write_data[2];
355 375
 `endif
356 376
                 end
  377
+`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
357 378
                 if (csr == `LM32_CSR_IP)
358 379
                     ip <= asserted & ~csr_write_data[interrupts-1:0];
  380
+`endif
359 381
             end
360 382
         end
361 383
     end

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