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asmi: dat_wm high to disable data write

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commit 0bea1e25890908630f3cd403b0e41d4ecec042a1 1 parent f2c20e4
@sbourdeauducq sbourdeauducq authored
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2  doc/index.rst
@@ -377,7 +377,7 @@ The data signals are used to complete requests.
* Master-to-Hub
* ``data_w`` must supply data to the controller from the appropriate write transaction, on the cycle after they have been called using ``call`` and ``tag_call``.
- * ``data_wm`` are the byte-granular write data masks. They are used in combination with ``data_w`` to identify the bytes that should be modified in the memory. The ``data_wm`` bit should be high for its corresponding ``data_w`` byte to be written.
+ * ``data_wm`` are the byte-granular write data masks. They are used in combination with ``data_w`` to identify the bytes that should be modified in the memory. The ``data_wm`` bit should be low for its corresponding ``data_w`` byte to be written.
In order to avoid duplicating the tag matching and tracking logic, the master-to-hub data signals must be driven low when they are not in use, so that they can be simply ORed together inside the memory controller. This way, only masters have to track (their own) transactions for arbitrating the data lines.
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2  migen/bus/asmibus.py
@@ -205,7 +205,7 @@ def _execute(self, s, port, generator):
yield
if isinstance(transaction, TWrite):
s.wr(port.dat_w, transaction.data)
- s.wr(port.dat_wm, transaction.sel)
+ s.wr(port.dat_wm, ~transaction.sel)
yield
s.wr(port.dat_w, 0)
s.wr(port.dat_wm, 0)
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6 migen/bus/wishbone2asmi.py
@@ -54,10 +54,8 @@ def get_fragment(self):
displacer(self.wishbone.sel, adr_offset, data_we, 2**offsetbits, reverse=True)
)
),
- If(write_to_asmi,
- self.asmiport.dat_w.eq(data_do),
- self.asmiport.dat_wm.eq(Replicate(1, adw//8))
- ),
+ If(write_to_asmi, self.asmiport.dat_w.eq(data_do)),
+ self.asmiport.dat_wm.eq(0),
chooser(data_do, adr_offset_r, self.wishbone.dat_r, reverse=True)
]
sync += [
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