Permalink
Browse files

Variable conversion

  • Loading branch information...
1 parent 4340680 commit 0e8d894a354652c6dd361f31818e8b9e625efc77 @sbourdeauducq sbourdeauducq committed Dec 5, 2011
Showing with 27 additions and 9 deletions.
  1. +15 −0 migen/fhdl/convtools.py
  2. +12 −9 migen/fhdl/verilog.py
View
@@ -73,6 +73,21 @@ def ListTargets(node):
else:
raise TypeError
+def IsVariable(node):
+ if isinstance(node, Signal):
+ return node.variable
+ elif isinstance(node, Slice):
+ return IsVariable(node.value)
+ elif isinstance(node, Cat):
+ arevars = list(map(IsVariable, node.l))
+ r = arevars[0]
+ for x in arevars:
+ if x != r:
+ raise TypeError
+ return r
+ else:
+ raise TypeError
+
def InsertReset(rst, sl):
targets = ListTargets(sl)
resetcode = []
View
@@ -50,25 +50,28 @@ def printexpr(node):
else:
raise TypeError
- def printnode(level, node):
+ def printnode(level, comb, node):
if isinstance(node, Assign):
- # TODO: variables
- return "\t"*level + printexpr(node.l) + " <= " + printexpr(node.r) + ";\n"
+ if comb or IsVariable(node.l):
+ assignment = " = "
+ else:
+ assignment = " <= "
+ return "\t"*level + printexpr(node.l) + assignment + printexpr(node.r) + ";\n"
elif isinstance(node, StatementList):
- return "".join(list(map(partial(printnode, level), node.l)))
+ return "".join(list(map(partial(printnode, level, comb), node.l)))
elif isinstance(node, If):
r = "\t"*level + "if (" + printexpr(node.cond) + ") begin\n"
- r += printnode(level + 1, node.t)
+ r += printnode(level + 1, comb, node.t)
if node.f.l:
r += "\t"*level + "end else begin\n"
- r += printnode(level + 1, node.f)
+ r += printnode(level + 1, comb, node.f)
r += "\t"*level + "end\n"
return r
elif isinstance(node, Case):
r = "\t"*level + "case (" + printexpr(node.test) + ")\n"
for case in node.cases:
r += "\t"*(level + 1) + printexpr(case[0]) + ": begin\n"
- r += printnode(level + 2, case[1])
+ r += printnode(level + 2, comb, case[1])
r += "\t"*(level + 1) + "end\n"
r += "\t"*level + "endcase\n"
return r
@@ -91,12 +94,12 @@ def printnode(level, node):
if f.comb.l:
r += "always @(*) begin\n"
- r += printnode(1, f.comb)
+ r += printnode(1, True, f.comb)
r += "end\n\n"
if f.sync.l:
r += "always @(posedge " + clk + ") begin\n"
- r += printnode(1, InsertReset(rsts, f.sync))
+ r += printnode(1, False, InsertReset(rsts, f.sync))
r += "end\n\n"
r += "endmodule\n"

0 comments on commit 0e8d894

Please sign in to comment.