Permalink
Browse files

bank: support raw registers

  • Loading branch information...
1 parent d21e095 commit 135a2eb86899149d9877202600877577a6445983 @sbourdeauducq sbourdeauducq committed Dec 17, 2011
Showing with 46 additions and 30 deletions.
  1. +38 −28 migen/bank/csrgen.py
  2. +8 −2 migen/bank/description.py
View
@@ -22,36 +22,45 @@ def get_fragment(self):
bwcases = []
for i in range(nregs):
reg = self.description[i]
- nfields = len(reg.fields)
- bwra = [Constant(i, BV(nbits))]
- for j in range(nfields):
- field = reg.fields[j]
- if field.access_bus == WRITE_ONLY or field.access_bus == READ_WRITE:
- bwra.append(field.storage.eq(self.interface.d_i[j]))
- if len(bwra) > 1:
- bwcases.append(bwra)
+ if reg.raw is None:
+ bwra = [Constant(i, BV(nbits))]
+ nfields = len(reg.fields)
+ for j in range(nfields):
+ field = reg.fields[j]
+ if field.access_bus == WRITE_ONLY or field.access_bus == READ_WRITE:
+ bwra.append(field.storage.eq(self.interface.d_i[j]))
+ if len(bwra) > 1:
+ bwcases.append(bwra)
+ else:
+ comb.append(reg.dev_r.eq(self.interface.d_i[:reg.raw.width]))
+ comb.append(reg.dev_re.eq(self._sel & \
+ self.interface.we_i & \
+ (self.interface.a_i[:nbits] == Constant(i, BV(nbits)))))
if bwcases:
sync.append(If(self._sel & self.interface.we_i, Case(self.interface.a_i[:nbits], *bwcases)))
# Bus reads
brcases = []
for i in range(nregs):
reg = self.description[i]
- nfields = len(reg.fields)
- brs = []
- reg_readable = False
- for j in range(nfields):
- field = reg.fields[j]
- if field.access_bus == READ_ONLY or field.access_bus == READ_WRITE:
- brs.append(field.storage)
- reg_readable = True
- else:
- brs.append(Constant(0, BV(field.size)))
- if reg_readable:
- if len(brs) > 1:
- brcases.append([Constant(i, BV(nbits)), self.interface.d_o.eq(f.Cat(*brs))])
- else:
- brcases.append([Constant(i, BV(nbits)), self.interface.d_o.eq(brs[0])])
+ if reg.raw is None:
+ nfields = len(reg.fields)
+ brs = []
+ reg_readable = False
+ for j in range(nfields):
+ field = reg.fields[j]
+ if field.access_bus == READ_ONLY or field.access_bus == READ_WRITE:
+ brs.append(field.storage)
+ reg_readable = True
+ else:
+ brs.append(Constant(0, BV(field.size)))
+ if reg_readable:
+ if len(brs) > 1:
+ brcases.append([Constant(i, BV(nbits)), self.interface.d_o.eq(f.Cat(*brs))])
+ else:
+ brcases.append([Constant(i, BV(nbits)), self.interface.d_o.eq(brs[0])])
+ else:
+ brcases.append([Constant(i, BV(nbits)), self.interface.d_o.eq(reg.dev_w)])
if brcases:
sync.append(self.interface.d_o.eq(Constant(0, BV(8))))
sync.append(If(self._sel, Case(self.interface.a_i[:nbits], *brcases)))
@@ -60,10 +69,11 @@ def get_fragment(self):
# Device access
for reg in self.description:
- for field in reg.fields:
- if field.access_dev == READ_ONLY or field.access_dev == READ_WRITE:
- comb.append(field.dev_r.eq(field.storage))
- if field.access_dev == WRITE_ONLY or field.access_dev == READ_WRITE:
- sync.append(If(field.dev_we, field.storage.eq(field.dev_w)))
+ if reg.raw is None:
+ for field in reg.fields:
+ if field.access_dev == READ_ONLY or field.access_dev == READ_WRITE:
+ comb.append(field.dev_r.eq(field.storage))
+ if field.access_dev == WRITE_ONLY or field.access_dev == READ_WRITE:
+ sync.append(If(field.dev_we, field.storage.eq(field.dev_w)))
return Fragment(comb, sync)
View
@@ -1,9 +1,15 @@
from migen.fhdl.structure import *
class Register:
- def __init__(self, name):
+ def __init__(self, name, raw=None):
self.name = name
- self.fields = []
+ self.raw = raw
+ if raw is not None:
+ self.dev_re = Signal(name=name + "_re")
+ self.dev_r = Signal(raw, name + "_r")
+ self.dev_w = Signal(raw, name + "_w")
+ else:
+ self.fields = []
def add_field(self, f):
self.fields.append(f)

0 comments on commit 135a2eb

Please sign in to comment.