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fhdl: do not attempt slicing non-array signals to keep Verilog happy

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1 parent fcd6583 commit 1eb348c573dfb68c67ed09445e5fdb5f524ac8b6 @sbourdeauducq sbourdeauducq committed Feb 6, 2012
Showing with 6 additions and 0 deletions.
  1. +6 −0 migen/fhdl/verilog.py
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6 migen/fhdl/verilog.py
@@ -34,6 +34,12 @@ def _printexpr(ns, node):
raise TypeError
return "(" + r + ")"
elif isinstance(node, _Slice):
+ # Verilog does not like us slicing non-array signals...
+ if isinstance(node.value, Signal) \
+ and node.value.bv.width == 1 \
+ and node.start == 0 and node.stop == 1:
+ return _printexpr(ns, node.value)
+
if node.start + 1 == node.stop:
sr = "[" + str(node.start) + "]"
else:

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