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bus/lasmibus/Crossbar: support cba_shift=0

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commit 1ec1fb9ebe53c19bf5d1e2e4dfe1af8f3d4cad7c 1 parent fe54c68
@sbourdeauducq sbourdeauducq authored
Showing with 4 additions and 1 deletion.
  1. +4 −1 migen/bus/lasmibus.py
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5 migen/bus/lasmibus.py
@@ -133,7 +133,10 @@ def _split_master_addresses(self, controller_bits, bank_bits, rca_bits, cba_shif
cba_upper = cba_shift + controller_bits + bank_bits
self.comb += cba.eq(master.adr[cba_shift:cba_upper])
if cba_shift < rca_bits:
- self.comb += rca.eq(Cat(master.adr[:cba_shift], master.adr[cba_upper:]))
+ if cba_shift:
+ self.comb += rca.eq(Cat(master.adr[:cba_shift], master.adr[cba_upper:]))
+ else:
+ self.comb += rca.eq(master.adr[cba_upper:])
else:
self.comb += rca.eq(master.adr[:cba_shift])

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