From 2423404b70131c8de51721277ed3a73c12e4a46f Mon Sep 17 00:00:00 2001 From: whitequark Date: Fri, 25 May 2018 08:28:50 +0000 Subject: [PATCH] fhdl.verilog: fix nondeterminism in _printcomb. --- migen/fhdl/verilog.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index 0e4a1308b..ca4cb02a2 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -271,11 +271,11 @@ def _printcomb(f, ns, if display_run: r += "\t$display(\"Running comb block #" + str(n) + "\");\n" if blocking_assign: - for t in g[0]: + for t in sorted(g[0], key=lambda x: x.duid): r += "\t" + ns.get_name(t) + " = " + _printexpr(ns, t.reset)[0] + ";\n" r += _printnode(ns, _AT_BLOCKING, 1, g[1]) else: - for t in g[0]: + for t in sorted(g[0], key=lambda x: x.duid): r += "\t" + ns.get_name(t) + " <= " + _printexpr(ns, t.reset)[0] + ";\n" r += _printnode(ns, _AT_NONBLOCKING, 1, g[1]) if dummy_signal: