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csr: new data width API

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commit 246b860a8550a3972bfb63d50a8656e02e8cdebe 1 parent 6ba0d4b
Sébastien Bourdeauducq authored July 28, 2013
14  migen/bank/csrgen.py
@@ -21,7 +21,7 @@ def __init__(self, description, address=0, bus=None):
21 21
 			if isinstance(c, CSR):
22 22
 				simple_csrs.append(c)
23 23
 			else:
24  
-				c.finalize(csr.data_width)
  24
+				c.finalize(flen(self.bus.dat_w))
25 25
 				simple_csrs += c.get_simple_csrs()
26 26
 				self.submodules += c
27 27
 		nbits = bits_for(len(simple_csrs)-1)
@@ -53,12 +53,12 @@ def __init__(self, description, address=0, bus=None):
53 53
 # address_map is called exactly once for each object at each call to
54 54
 # scan(), so it can have side effects.
55 55
 class BankArray(Module):
56  
-	def __init__(self, source, address_map):
  56
+	def __init__(self, source, address_map, *ifargs, **ifkwargs):
57 57
 		self.source = source
58 58
 		self.address_map = address_map
59  
-		self.scan()
  59
+		self.scan(ifargs, ifkwargs)
60 60
 
61  
-	def scan(self):
  61
+	def scan(self, ifargs, ifkwargs):
62 62
 		self.banks = []
63 63
 		self.srams = []
64 64
 		for name, obj in sorted(self.source.__dict__.items(), key=itemgetter(0)):
@@ -70,13 +70,15 @@ def scan(self):
70 70
 				memories = obj.get_memories()
71 71
 				for memory in memories:
72 72
 					mapaddr = self.address_map(name, memory)
73  
-					mmap = csr.SRAM(memory, mapaddr)
  73
+					sram_bus = csr.Interface(*ifargs, **ifkwargs)
  74
+					mmap = csr.SRAM(memory, mapaddr, bus=sram_bus)
74 75
 					self.submodules += mmap
75 76
 					csrs += mmap.get_csrs()
76 77
 					self.srams.append((name, memory, mapaddr, mmap))
77 78
 			if csrs:
78 79
 				mapaddr = self.address_map(name, None)
79  
-				rmap = Bank(csrs, mapaddr)
  80
+				bank_bus = csr.Interface(*ifargs, **ifkwargs)
  81
+				rmap = Bank(csrs, mapaddr, bus=bank_bus)
80 82
 				self.submodules += rmap
81 83
 				self.banks.append((name, csrs, mapaddr, rmap))
82 84
 
22  migen/bus/csr.py
@@ -4,15 +4,16 @@
4 4
 from migen.genlib.record import *
5 5
 from migen.genlib.misc import chooser
6 6
 
7  
-data_width = 8
  7
+_layout = [
  8
+	("adr",		14,				DIR_M_TO_S),
  9
+	("we",		1,				DIR_M_TO_S),
  10
+	("dat_w",	"data_width",	DIR_M_TO_S),
  11
+	("dat_r",	"data_width",	DIR_S_TO_M)
  12
+]
8 13
 
9 14
 class Interface(Record):
10  
-	def __init__(self):
11  
-		Record.__init__(self, [
12  
-			("adr",		14,			DIR_M_TO_S),
13  
-			("we",		1,			DIR_M_TO_S),
14  
-			("dat_w",	data_width,	DIR_M_TO_S),
15  
-			("dat_r",	data_width,	DIR_S_TO_M)])
  15
+	def __init__(self, data_width=8):
  16
+		Record.__init__(self, _layout, data_width=data_width)
16 17
 
17 18
 class Interconnect(Module):
18 19
 	def __init__(self, master, slaves):
@@ -55,6 +56,10 @@ def do_simulation(self, s):
55 56
 
56 57
 class SRAM(Module):
57 58
 	def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
  59
+		if bus is None:
  60
+			bus = Interface()
  61
+		self.bus = bus
  62
+		data_width = flen(self.bus.dat_w)
58 63
 		if isinstance(mem_or_size, Memory):
59 64
 			mem = mem_or_size
60 65
 		else:
@@ -71,9 +76,6 @@ def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
71 76
 				read_only = mem.bus_read_only
72 77
 			else:
73 78
 				read_only = False
74  
-		if bus is None:
75  
-			bus = Interface()
76  
-		self.bus = bus
77 79
 	
78 80
 		###
79 81
 
14  migen/bus/wishbone2csr.py
@@ -4,16 +4,20 @@
4 4
 from migen.genlib.misc import timeline
5 5
 
6 6
 class WB2CSR(Module):
7  
-	def __init__(self):
8  
-		self.wishbone = wishbone.Interface()
9  
-		self.csr = csr.Interface()
  7
+	def __init__(self, bus_wishbone=None, bus_csr=None):
  8
+		if bus_wishbone is None:
  9
+			bus_wishbone = wishbone.Interface()
  10
+		self.wishbone = bus_wishbone
  11
+		if bus_csr is None:
  12
+			bus_csr = csr.Interface()
  13
+		self.csr = bus_csr
10 14
 	
11 15
 		###
12 16
 
13 17
 		self.sync += [
14 18
 			self.csr.we.eq(0),
15  
-			self.csr.dat_w.eq(self.wishbone.dat_w[:csr.data_width]),
16  
-			self.csr.adr.eq(self.wishbone.adr[:14]),
  19
+			self.csr.dat_w.eq(self.wishbone.dat_w),
  20
+			self.csr.adr.eq(self.wishbone.adr),
17 21
 			self.wishbone.dat_r.eq(self.csr.dat_r)
18 22
 		]
19 23
 		self.sync += timeline(self.wishbone.cyc & self.wishbone.stb, [

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