Pay a bit more attention to PEP8

examples/corelogic_conv.py

@@ -4,6 +4,6 @@
 
 r = roundrobin.Inst(5)
 d = divider.Inst(16)
-frag = r.GetFragment() + d.GetFragment()
+frag = r.get_fragment() + d.get_fragment()
 o = verilog.Convert(frag, {r.request, r.grant, d.ready_o, d.quotient_o, d.remainder_o, d.start_i, d.dividend_i, d.divisor_i})
-print(o)
+print(o)

examples/lm32_inst.py

@@ -37,11 +37,11 @@ def __init__(self):
 			"rst_i",
 			"lm32")
 
-	def GetFragment(self):
+	def get_fragment(self):
 		return f.Fragment(instances=[self.inst])
 
 cpus = [LM32() for i in range(4)]
 frag = f.Fragment()
 for cpu in cpus:
-	frag += cpu.GetFragment()
-print(verilog.Convert(frag, set([cpus[0].inst.ins["interrupt"], cpus[0].inst.outs["I_WE_O"]])))
+	frag += cpu.get_fragment()
+print(verilog.Convert(frag, set([cpus[0].inst.ins["interrupt"], cpus[0].inst.outs["I_WE_O"]])))

examples/simple_gpio.py

@@ -18,8 +18,8 @@
 inf = f.Fragment(incomb, insync)
 
 bank = csrgen.Bank([oreg, ireg])
-f = bank.GetFragment() + inf
+f = bank.get_fragment() + inf
 i = bank.interface
 ofield.dev_r.name = "gpio_out"
 v = verilog.Convert(f, {i.d_o, ofield.dev_r, i.a_i, i.we_i, i.d_i, gpio_in})
-print(v)
+print(v)

examples/wb_intercon/intercon_conv.py

@@ -12,7 +12,7 @@
 		register=True,
 		offset=1)
 
-frag = wishbonecon0.GetFragment()
+frag = wishbonecon0.get_fragment()
 v = verilog.Convert(frag, name="intercon", ios={m1.cyc_o, m1.stb_o, m1.we_o, m1.adr_o, m1.sel_o, m1.dat_o, m1.dat_i, m1.ack_i,
 	m2.cyc_o, m2.stb_o, m2.we_o, m2.adr_o, m2.sel_o, m2.dat_o, m2.dat_i, m2.ack_i,
 	s1.cyc_i, s1.stb_i, s1.we_i, s1.adr_i, s1.sel_i, s1.dat_i, s1.dat_o, s1.ack_o,

migen/bank/csrgen.py

@@ -1,25 +1,23 @@
-from ..fhdl import structure as f
-from ..bus.csr import *
-from .description import *
-from functools import partial
+from migen.fhdl import structure as f
+from migen.bus.csr import *
+from migen.bank.description import *
 
 class Bank:
 	def __init__(self, description, address=0):
 		self.description = description
 		self.address = address
 		self.interface = Slave()
-		d = partial(f.Declare, self)
-		d("_sel")
+		f.declare_signal(self, "_sel")
 
-	def GetFragment(self):
+	def get_fragment(self):
 		a = f.Assign
 		comb = []
 		sync = []
 
 		comb.append(a(self._sel, self.interface.a_i[10:] == f.Constant(self.address, f.BV(4))))
 
 		nregs = len(self.description)
-		nbits = f.BitsFor(nregs-1)
+		nbits = f.bits_for(nregs-1)
 
 		# Bus writes
 		bwcases = []

migen/bank/description.py

@@ -1,11 +1,11 @@
-from ..fhdl import structure as f
+from migen.fhdl import structure as f
 
 class Register:
 	def __init__(self, name):
 		self.name = name
 		self.fields = []
 
-	def AddField(self, f):
+	def add_field(self, f):
 		self.fields.append(f)
 
 (READ_ONLY, WRITE_ONLY, READ_WRITE) = range(3)
@@ -25,4 +25,4 @@ def __init__(self, parent, name, size=1, access_bus=READ_WRITE, access_dev=READ_
 		if self.access_dev == WRITE_ONLY or self.access_dev == READ_WRITE:
 			self.dev_w = f.Signal(f.BV(self.size), fullname + "_w")
 			self.dev_we = f.Signal(name=fullname + "_we")
-		self.parent.AddField(self)
+		self.parent.add_field(self)

migen/bus/csr.py

@@ -1,5 +1,5 @@
 from migen.fhdl import structure as f
-from .simple import Simple
+from migen.bus.simple import Simple
 
 _desc = [
 	(True,	"a",	14),
@@ -21,7 +21,7 @@ def __init__(self, master, slaves):
 		self.master = master
 		self.slaves = slaves
 
-	def GetFragment(self):
+	def get_fragment(self):
 		a = f.Assign
 		comb = []
 		rb = f.Constant(0, f.BV(32))

migen/bus/simple.py

@@ -1,6 +1,6 @@
 from migen.fhdl import structure as f
 
-def GetSigName(signal, slave):
+def get_sig_name(signal, slave):
 	if signal[0] ^ slave:
 		suffix = "_o"
 	else:
@@ -18,5 +18,5 @@ def __init__(self, desc, slave, name):
 			busname = modules[len(modules)-1]
 			if name:
 				busname += "_" + name
-			signame = GetSigName(signal, slave)
+			signame = get_sig_name(signal, slave)
 			setattr(self, signame, f.Signal(f.BV(signal[2]), busname + "_" + signame))

migen/bus/wishbone.py

@@ -1,7 +1,8 @@
+from functools import partial
+
 from migen.fhdl import structure as f
 from migen.corelogic import roundrobin, multimux
-from .simple import Simple, GetSigName
-from functools import partial
+from migen.bus.simple import Simple, get_sig_name
 
 _desc = [
 	(True,	"adr",	32),
@@ -31,17 +32,17 @@ def __init__(self, masters, target):
 		self.target = target
 		self.rr = roundrobin.Inst(len(self.masters))
 
-	def GetFragment(self):
+	def get_fragment(self):
 		comb = []
 
 		# mux master->slave signals
-		m2s_names = [GetSigName(x, False) for x in _desc if x[0]]
+		m2s_names = [get_sig_name(x, False) for x in _desc if x[0]]
 		m2s_masters = [[getattr(m, name) for name in m2s_names] for m in self.masters]
 		m2s_target = [getattr(self.target, name) for name in m2s_names]
-		comb += multimux.MultiMux(self.rr.grant, m2s_masters, m2s_target)
+		comb += multimux.multimux(self.rr.grant, m2s_masters, m2s_target)
 
 		# connect slave->master signals
-		s2m_names = [GetSigName(x, False) for x in _desc if not x[0]]
+		s2m_names = [get_sig_name(x, False) for x in _desc if not x[0]]
 		for name in s2m_names:
 			source = getattr(self.target, name)
 			i = 0
@@ -57,7 +58,7 @@ def GetFragment(self):
 		reqs = [m.cyc_o for m in self.masters]
 		comb.append(f.Assign(self.rr.request, f.Cat(*reqs)))
 
-		return f.Fragment(comb) + self.rr.GetFragment()
+		return f.Fragment(comb) + self.rr.get_fragment()
 
 class Decoder:
 	# slaves is a list of pairs:
@@ -75,7 +76,7 @@ def __init__(self, master, slaves, offset=0, register=False):
 		self.register = register
 
 		addresses = [slave[0] for slave in self.slaves]
-		maxbits = max([f.BitsFor(addr) for addr in addresses])
+		maxbits = max([f.bits_for(addr) for addr in addresses])
 		def mkconst(x):
 			if isinstance(x, int):
 				return f.Constant(x, f.BV(maxbits))
@@ -84,11 +85,11 @@ def mkconst(x):
 		self.addresses = list(map(mkconst, addresses))
 
 		ns = len(self.slaves)
-		d = partial(f.Declare, self)
+		d = partial(f.declare_signal, self)
 		d("_slave_sel", f.BV(ns))
 		d("_slave_sel_r", f.BV(ns))
 
-	def GetFragment(self):
+	def get_fragment(self):
 		comb = []
 		sync = []
 
@@ -105,7 +106,7 @@ def GetFragment(self):
 			comb.append(f.Assign(self._slave_sel_r, self._slave_sel))
 
 		# connect master->slaves signals except cyc
-		m2s_names = [(GetSigName(x, False), GetSigName(x, True))
+		m2s_names = [(get_sig_name(x, False), get_sig_name(x, True))
 			for x in _desc if x[0] and x[1] != "cyc"]
 		comb += [f.Assign(getattr(slave[1], name[1]), getattr(self.master, name[0]))
 			for name in m2s_names for slave in self.slaves]
@@ -142,5 +143,5 @@ def __init__(self, masters, slaves, offset=0, register=False):
 		self._decoder = Decoder(self._shared, slaves, offset, register)
 		self.addresses = self._decoder.addresses
 
-	def GetFragment(self):
-		return self._arbiter.GetFragment() + self._decoder.GetFragment()
+	def get_fragment(self):
+		return self._arbiter.get_fragment() + self._decoder.get_fragment()

migen/bus/wishbone2csr.py

@@ -1,7 +1,7 @@
+from migen.bus import wishbone
+from migen.bus import csr
 from migen.fhdl import structure as f
 from migen.corelogic import timeline
-from . import wishbone
-from . import csr
 
 class Inst():
 	def __init__(self):
@@ -12,11 +12,11 @@ def __init__(self):
 			(2, [f.Assign(self.wishbone.ack_o, 1)]),
 			(3, [f.Assign(self.wishbone.ack_o, 0)])])
 
-	def GetFragment(self):
+	def get_fragment(self):
 		sync = [
 			f.Assign(self.csr.we_o, 0),
 			f.Assign(self.csr.d_o, self.wishbone.dat_i),
 			f.Assign(self.csr.a_o, self.wishbone.adr_i[2:16]),
 			f.Assign(self.wishbone.dat_o, self.csr.d_i)
 		]
-		return f.Fragment(sync=sync) + self.timeline.GetFragment()
+		return f.Fragment(sync=sync) + self.timeline.get_fragment()

migen/corelogic/divider.py

@@ -1,11 +1,12 @@
-from migen.fhdl import structure as f
 from functools import partial
 
+from migen.fhdl import structure as f
+
 class Inst:
 	def __init__(self, w):
 		self.w = w
 
-		d = partial(f.Declare, self)
+		d = partial(f.declare_signal, self)
 
 		d("start_i")
 		d("dividend_i", f.BV(w))
@@ -15,11 +16,11 @@ def __init__(self, w):
 		d("remainder_o", f.BV(w))
 
 		d("_qr", f.BV(2*w))
-		d("_counter", f.BV(f.BitsFor(w)))
+		d("_counter", f.BV(f.bits_for(w)))
 		d("_divisor_r", f.BV(w))
 		d("_diff", f.BV(w+1))
 
-	def GetFragment(self):
+	def get_fragment(self):
 		a = f.Assign
 		comb = [
 			a(self.quotient_o, self._qr[:self.w]),

migen/corelogic/multimux.py

@@ -1,6 +1,6 @@
 from migen.fhdl import structure as f
 
-def MultiMux(sel, inputs, output):
+def multimux(sel, inputs, output):
 	n = len(inputs)
 	i = 0
 	comb = []
@@ -10,4 +10,4 @@ def MultiMux(sel, inputs, output):
 		default = cases.pop()[1]
 		comb.append(f.Case(sel, cases, default))
 		i += 1
-	return comb
+	return comb

migen/corelogic/roundrobin.py

@@ -3,11 +3,11 @@
 class Inst:
 	def __init__(self, n):
 		self.n = n
-		self.bn = f.BitsFor(self.n-1)
-		f.Declare(self, "request", f.BV(self.n))
-		f.Declare(self, "grant", f.BV(self.bn))
+		self.bn = f.bits_for(self.n-1)
+		f.declare_signal(self, "request", f.BV(self.n))
+		f.declare_signal(self, "grant", f.BV(self.bn))
 
-	def GetFragment(self):
+	def get_fragment(self):
 		cases = []
 		for i in range(self.n):
 			switch = []
@@ -19,4 +19,4 @@ def GetFragment(self):
 			case = f.If(~self.request[i], switch)
 			cases.append((f.Constant(i, f.BV(self.bn)), case))
 		statement = f.Case(self.grant, cases)
-		return f.Fragment(sync=[statement])
+		return f.Fragment(sync=[statement])

migen/corelogic/timeline.py

@@ -5,9 +5,9 @@ def __init__(self, trigger, events):
 		self.trigger = trigger
 		self.events = events
 		self.lastevent = max([e[0] for e in events])
-		f.Declare(self, "_counter", f.BV(f.BitsFor(self.lastevent)))
+		f.declare_signal(self, "_counter", f.BV(f.bits_for(self.lastevent)))
 
-	def GetFragment(self):
+	def get_fragment(self):
 		counterlogic = f.If(self._counter != f.Constant(0, self._counter.bv), 
 			[f.Assign(self._counter, self._counter + f.Constant(1, self._counter.bv))],
 			[f.If(self.trigger, [f.Assign(self._counter, f.Constant(1, self._counter.bv))])])
@@ -17,11 +17,11 @@ def GetFragment(self):
 			counterlogic = f.If(self._counter == self.lastevent,
 				[f.Assign(self._counter, f.Constant(0, self._counter.bv))],
 				[counterlogic])
-		def getcond(e):
+		def get_cond(e):
 			if e[0] == 0:
 				return self.trigger & (self._counter == f.Constant(0, self._counter.bv))
 			else:
 				return self._counter == f.Constant(e[0], self._counter.bv)
-		sync = [f.If(getcond(e), e[1]) for e in self.events]
+		sync = [f.If(get_cond(e), e[1]) for e in self.events]
 		sync.append(counterlogic)
 		return f.Fragment(sync=sync)

migen/fhdl/autofragment.py

@@ -1,12 +1,13 @@
-from .structure import *
 import inspect
 
-def FromLocal():
+from migen.fhdl.structure import *
+
+def from_local():
 	f = Fragment()
 	frame = inspect.currentframe().f_back
 	ns = frame.f_locals
 	for x in ns:
 		obj = ns[x]
-		if hasattr(obj, "GetFragment"):
-			f += obj.GetFragment()
+		if hasattr(obj, "get_fragment"):
+			f += obj.get_fragment()
 	return f