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bus/csr: configurable data width

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1 parent 9aa5ceb commit 4164fb4ac93a77cff1a777a52efe8a728bebec03 @sbourdeauducq sbourdeauducq committed Aug 26, 2012
Showing with 12 additions and 13 deletions.
  1. +5 −5 migen/bank/csrgen.py
  2. +6 −7 migen/bus/csr.py
  3. +1 −1 migen/bus/wishbone2csr.py
View
@@ -1,13 +1,13 @@
from migen.fhdl.structure import *
-from migen.bus.csr import *
+from migen.bus import csr
from migen.bank.description import *
class Bank:
def __init__(self, description, address=0, interface=None):
self.description = description
self.address = address
if interface is None:
- interface = Interface()
+ interface = csr.Interface()
self.interface = interface
def get_fragment(self):
@@ -17,7 +17,7 @@ def get_fragment(self):
sel = Signal()
comb.append(sel.eq(self.interface.adr[9:] == Constant(self.address, BV(5))))
- desc_exp = expand_description(self.description, 8)
+ desc_exp = expand_description(self.description, csr.data_width)
nbits = bits_for(len(desc_exp)-1)
# Bus writes
@@ -66,10 +66,10 @@ def get_fragment(self):
else:
raise TypeError
if brcases:
- sync.append(self.interface.dat_r.eq(Constant(0, BV(8))))
+ sync.append(self.interface.dat_r.eq(0))
sync.append(If(sel, Case(self.interface.adr[:nbits], *brcases)))
else:
- comb.append(self.interface.dat_r.eq(Constant(0, BV(8))))
+ comb.append(self.interface.dat_r.eq(0))
# Device access
for reg in self.description:
View
@@ -3,16 +3,15 @@
from migen.bus.transactions import *
from migen.sim.generic import PureSimulable
-_desc = Description(
- (M_TO_S, "adr", 14),
- (M_TO_S, "we", 1),
- (M_TO_S, "dat_w", 8),
- (S_TO_M, "dat_r", 8)
-)
+data_width = 8
class Interface(SimpleInterface):
def __init__(self):
- super().__init__(_desc)
+ super().__init__(Description(
+ (M_TO_S, "adr", 14),
+ (M_TO_S, "we", 1),
+ (M_TO_S, "dat_w", data_width),
+ (S_TO_M, "dat_r", data_width)))
class Interconnect(SimpleInterconnect):
pass
@@ -11,7 +11,7 @@ def __init__(self):
def get_fragment(self):
sync = [
self.csr.we.eq(0),
- self.csr.dat_w.eq(self.wishbone.dat_w[:8]),
+ self.csr.dat_w.eq(self.wishbone.dat_w[:csr.data_width]),
self.csr.adr.eq(self.wishbone.adr[:14]),
self.wishbone.dat_r.eq(self.csr.dat_r)
]

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