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CSR bus definitions

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1 parent 5acf2e1 commit 458cfc862325e256706d70eb7ee6f5fa012668a9 @sbourdeauducq sbourdeauducq committed Dec 4, 2011
Showing with 35 additions and 50 deletions.
  1. 0 migen/bus/__init__.py
  2. +35 −0 migen/bus/csr.py
  3. +0 −50 test.py
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@@ -0,0 +1,35 @@
+from migen.fhdl import structure as f
+from functools import partial
+
+class Master:
+ def __init__(self):
+ d = partial(f.Declare, self)
+ d("a_o", f.BV(16))
+ d("we_o")
+ d("d_o", f.BV(32))
+ d("d_i", f.BV(32))
+
+class Slave:
+ def __init__(self):
+ d = partial(f.Declare, self)
+ d("a_i", f.BV(16))
+ d("we_i")
+ d("d_i", f.BV(32))
+ d("d_o", f.BV(32))
+
+class Interconnect:
+ def __init__(self, master, slaves):
+ self.master = master
+ self.slaves = slaves
+
+ def GetFragment(self):
+ a = f.Assign
+ comb = []
+ rb = f.Constant(0, f.BV(32))
+ for slave in self.slaves:
+ comb.append(a(slave.a_i, self.master.a_o))
+ comb.append(a(slave.we_i, self.master.we_o))
+ comb.append(a(slave.d_i, self.master.d_o))
+ rb = rb | slave.d_o
+ comb.append(a(master.d_i, rb))
+ return f.Fragment(comb)
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50 test.py
@@ -1,50 +0,0 @@
-from migen.fhdl import structure as f
-from migen.fhdl import verilog
-from functools import partial
-
-class Divider:
- def __init__(self, w):
- self.w = w
-
- d = partial(f.Declare, self)
-
- d("start_i")
- d("dividend_i", f.BV(w))
- d("divisor_i", f.BV(w))
- d("ready_o")
- d("quotient_o", f.BV(w))
- d("remainder_o", f.BV(w))
-
- d("_qr", f.BV(2*w))
- d("_counter", f.BV(f.BitsFor(w)))
- d("_divisor_r", f.BV(w))
- d("_diff", f.BV(w+1))
-
- def GetFragment(self):
- a = f.Assign
- comb = [
- a(self.quotient_o, self._qr[:self.w]),
- a(self.remainder_o, self._qr[self.w:]),
- a(self.ready_o, self._counter == f.Constant(0, self._counter.bv)),
- a(self._diff, self.remainder_o - self._divisor_r)
- ]
- sync = [
- f.If(self.start_i == 1, [
- a(self._counter, self.w),
- a(self._qr, self.dividend_i),
- a(self._divisor_r, self.divisor_i)
- ], [
- f.If(self.ready_o == 0, [
- f.If(self._diff[self.w] == 1,
- [a(self._qr, f.Cat(0, self._qr[:2*self.w-1]))],
- [a(self._qr, f.Cat(1, self._qr[:self.w-1], self._diff[:self.w]))]),
- a(self._counter, self._counter - f.Constant(1, self._counter.bv)),
- ])
- ])
- ]
- return f.Fragment(comb, sync)
-
-d = Divider(32)
-f = d.GetFragment()
-o = verilog.Convert(f, {d.start_i, d.dividend_i, d.divisor_i}, {d.ready_o, d.quotient_o, d.remainder_o})
-print(o)

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